pgm.h@ 105745

Last change on this file since 105745 was 105745, checked in by vboxsync, 3 months ago
VMM/PGM: Some preparations for ARMv8 page table walking, introduce dedicated PGMMODE enumerations for ARMv8 and hide all accesses behind PGMMODE_XXX macros, bugref:10388
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1	/** @file
2	* PGM - Page Monitor / Monitor.
3	*/
4
5	/*
6	* Copyright (C) 2006-2023 Oracle and/or its affiliates.
7	*
8	* This file is part of VirtualBox base platform packages, as
9	* available from https://www.virtualbox.org.
10	*
11	* This program is free software; you can redistribute it and/or
12	* modify it under the terms of the GNU General Public License
13	* as published by the Free Software Foundation, in version 3 of the
14	* License.
15	*
16	* This program is distributed in the hope that it will be useful, but
17	* WITHOUT ANY WARRANTY; without even the implied warranty of
18	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19	* General Public License for more details.
20	*
21	* You should have received a copy of the GNU General Public License
22	* along with this program; if not, see <https://www.gnu.org/licenses>.
23	*
24	* The contents of this file may alternatively be used under the terms
25	* of the Common Development and Distribution License Version 1.0
26	* (CDDL), a copy of it is provided in the "COPYING.CDDL" file included
27	* in the VirtualBox distribution, in which case the provisions of the
28	* CDDL are applicable instead of those of the GPL.
29	*
30	* You may elect to license modified versions of this file under the
31	* terms and conditions of either the GPL or the CDDL or both.
32	*
33	* SPDX-License-Identifier: GPL-3.0-only OR CDDL-1.0
34	*/
35
36	#ifndef VBOX_INCLUDED_vmm_pgm_h
37	#define VBOX_INCLUDED_vmm_pgm_h
38	#ifndef RT_WITHOUT_PRAGMA_ONCE
39	# pragma once
40	#endif
41
42	#include <VBox/types.h>
43	#include <VBox/sup.h>
44	#include <VBox/vmm/vmapi.h>
45	#include <VBox/vmm/gmm.h> /* for PGMMREGISTERSHAREDMODULEREQ */
46	#include <VBox/vmm/hm_vmx.h>
47	#include <iprt/x86.h>
48	#include <VBox/param.h>
49
50	RT_C_DECLS_BEGIN
51
52	/** @defgroup grp_pgm The Page Monitor / Manager API
53	* @ingroup grp_vmm
54	* @{
55	*/
56
57	/**
58	* FNPGMRELOCATE callback mode.
59	*/
60	typedef enum PGMRELOCATECALL
61	{
62	/** The callback is for checking if the suggested address is suitable. */
63	PGMRELOCATECALL_SUGGEST = 1,
64	/** The callback is for executing the relocation. */
65	PGMRELOCATECALL_RELOCATE
66	} PGMRELOCATECALL;
67
68
69	/**
70	* Callback function which will be called when PGM is trying to find
71	* a new location for the mapping.
72	*
73	* The callback is called in two modes, 1) the check mode and 2) the relocate mode.
74	* In 1) the callback should say if it objects to a suggested new location. If it
75	* accepts the new location, it is called again for doing it's relocation.
76	*
77	*
78	* @returns true if the location is ok.
79	* @returns false if another location should be found.
80	* @param pVM The cross context VM structure.
81	* @param GCPtrOld The old virtual address.
82	* @param GCPtrNew The new virtual address.
83	* @param enmMode Used to indicate the callback mode.
84	* @param pvUser User argument.
85	* @remark The return value is no a failure indicator, it's an acceptance
86	* indicator. Relocation can not fail!
87	*/
88	typedef DECLCALLBACKTYPE(bool, FNPGMRELOCATE,(PVM pVM, RTGCPTR GCPtrOld, RTGCPTR GCPtrNew, PGMRELOCATECALL enmMode, void *pvUser));
89	/** Pointer to a relocation callback function. */
90	typedef FNPGMRELOCATE *PFNPGMRELOCATE;
91
92
93	/**
94	* Memory access origin.
95	*/
96	typedef enum PGMACCESSORIGIN
97	{
98	/** Invalid zero value. */
99	PGMACCESSORIGIN_INVALID = 0,
100	/** IEM is access memory. */
101	PGMACCESSORIGIN_IEM,
102	/** HM is access memory. */
103	PGMACCESSORIGIN_HM,
104	/** Some device is access memory. */
105	PGMACCESSORIGIN_DEVICE,
106	/** Someone debugging is access memory. */
107	PGMACCESSORIGIN_DEBUGGER,
108	/** SELM is access memory. */
109	PGMACCESSORIGIN_SELM,
110	/** FTM is access memory. */
111	PGMACCESSORIGIN_FTM,
112	/** REM is access memory. */
113	PGMACCESSORIGIN_REM,
114	/** IOM is access memory. */
115	PGMACCESSORIGIN_IOM,
116	/** End of valid values. */
117	PGMACCESSORIGIN_END,
118	/** Type size hack. */
119	PGMACCESSORIGIN_32BIT_HACK = 0x7fffffff
120	} PGMACCESSORIGIN;
121
122
123	/**
124	* Physical page access handler kind.
125	*/
126	typedef enum PGMPHYSHANDLERKIND
127	{
128	/** Invalid zero value. */
129	PGMPHYSHANDLERKIND_INVALID = 0,
130	/** MMIO range. Pages are not present, all access is done in interpreter or recompiler. */
131	PGMPHYSHANDLERKIND_MMIO,
132	/** Handler all write access to a physical page range. */
133	PGMPHYSHANDLERKIND_WRITE,
134	/** Handler all access to a physical page range. */
135	PGMPHYSHANDLERKIND_ALL,
136	/** End of the valid values. */
137	PGMPHYSHANDLERKIND_END,
138	/** Type size hack. */
139	PGMPHYSHANDLERKIND_32BIT_HACK = 0x7fffffff
140	} PGMPHYSHANDLERKIND;
141
142	/**
143	* Guest Access type
144	*/
145	typedef enum PGMACCESSTYPE
146	{
147	/** Read access. */
148	PGMACCESSTYPE_READ = 1,
149	/** Write access. */
150	PGMACCESSTYPE_WRITE
151	} PGMACCESSTYPE;
152
153
154	/** @def PGM_ALL_CB_DECL
155	* Macro for declaring a handler callback for all contexts. The handler
156	* callback is static in ring-3, and exported in RC and R0.
157	* @sa PGM_ALL_CB2_DECL.
158	*/
159	#if defined(IN_RC) \|\| defined(IN_RING0)
160	# ifdef __cplusplus
161	# define PGM_ALL_CB_DECL(type) extern "C" DECLCALLBACK(DECLEXPORT(type))
162	# else
163	# define PGM_ALL_CB_DECL(type) DECLCALLBACK(DECLEXPORT(type))
164	# endif
165	#else
166	# define PGM_ALL_CB_DECL(type) static DECLCALLBACK(type)
167	#endif
168
169	/** @def PGM_ALL_CB2_DECL
170	* Macro for declaring a handler callback for all contexts. The handler
171	* callback is hidden in ring-3, and exported in RC and R0.
172	* @sa PGM_ALL_CB2_DECL.
173	*/
174	#if defined(IN_RC) \|\| defined(IN_RING0)
175	# ifdef __cplusplus
176	# define PGM_ALL_CB2_DECL(type) extern "C" DECLCALLBACK(DECLEXPORT(type))
177	# else
178	# define PGM_ALL_CB2_DECL(type) DECLCALLBACK(DECLEXPORT(type))
179	# endif
180	#else
181	# define PGM_ALL_CB2_DECL(type) DECL_HIDDEN_CALLBACK(type)
182	#endif
183
184	/** @def PGM_ALL_CB2_PROTO
185	* Macro for declaring a handler callback for all contexts. The handler
186	* callback is hidden in ring-3, and exported in RC and R0.
187	* @param fnType The callback function type.
188	* @sa PGM_ALL_CB2_DECL.
189	*/
190	#if defined(IN_RC) \|\| defined(IN_RING0)
191	# ifdef __cplusplus
192	# define PGM_ALL_CB2_PROTO(fnType) extern "C" DECLEXPORT(fnType)
193	# else
194	# define PGM_ALL_CB2_PROTO(fnType) DECLEXPORT(fnType)
195	# endif
196	#else
197	# define PGM_ALL_CB2_PROTO(fnType) DECLHIDDEN(fnType)
198	#endif
199
200
201	/**
202	* \#PF Handler callback for physical access handler ranges in RC and R0.
203	*
204	* @returns Strict VBox status code (appropriate for ring-0 and raw-mode).
205	* @param pVM The cross context VM structure.
206	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
207	* @param uErrorCode CPU Error code.
208	* @param pCtx Pointer to the register context for the CPU.
209	* @param pvFault The fault address (cr2).
210	* @param GCPhysFault The GC physical address corresponding to pvFault.
211	* @param uUser User argument (not a pointer).
212	* @thread EMT(pVCpu)
213	*/
214	typedef DECLCALLBACKTYPE(VBOXSTRICTRC, FNPGMRZPHYSPFHANDLER,(PVMCC pVM, PVMCPUCC pVCpu, RTGCUINT uErrorCode, PCPUMCTX pCtx,
215	RTGCPTR pvFault, RTGCPHYS GCPhysFault, uint64_t uUser));
216	/** Pointer to PGM access callback. */
217	typedef FNPGMRZPHYSPFHANDLER *PFNPGMRZPHYSPFHANDLER;
218
219
220	/**
221	* Access handler callback for physical access handler ranges.
222	*
223	* The handler can not raise any faults, it's mainly for monitoring write access
224	* to certain pages (like MMIO).
225	*
226	* @returns Strict VBox status code in ring-0 and raw-mode context, in ring-3
227	* the only supported informational status code is
228	* VINF_PGM_HANDLER_DO_DEFAULT.
229	* @retval VINF_SUCCESS if the handler have carried out the operation.
230	* @retval VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the
231	* access operation.
232	* @retval VINF_EM_XXX in ring-0 and raw-mode context.
233	*
234	* @param pVM The cross context VM structure.
235	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
236	* @param GCPhys The physical address the guest is writing to.
237	* @param pvPhys The HC mapping of that address.
238	* @param pvBuf What the guest is reading/writing.
239	* @param cbBuf How much it's reading/writing.
240	* @param enmAccessType The access type.
241	* @param enmOrigin The origin of this call.
242	* @param uUser User argument (not a pointer).
243	* @thread EMT(pVCpu)
244	*/
245	typedef DECLCALLBACKTYPE(VBOXSTRICTRC, FNPGMPHYSHANDLER,(PVMCC pVM, PVMCPUCC pVCpu, RTGCPHYS GCPhys, void *pvPhys,
246	void *pvBuf, size_t cbBuf, PGMACCESSTYPE enmAccessType,
247	PGMACCESSORIGIN enmOrigin, uint64_t uUser));
248	/** Pointer to PGM access callback. */
249	typedef FNPGMPHYSHANDLER *PFNPGMPHYSHANDLER;
250
251
252	/** @todo r=aeichner This doesn't seem to be used outside of the VMM module, so we might make
253	* all APIs (PGMGetGuestMode(), etc.) internal and split this up into an
254	* x86 and arm specific header. */
255	/**
256	* Paging mode.
257	*
258	* @note Part of saved state. Change with extreme care.
259	*/
260	typedef enum PGMMODE
261	{
262	/** The usual invalid value. */
263	PGMMODE_INVALID = 0,
264	#ifndef VBOX_VMM_TARGET_ARMV8
265	/** Real mode. */
266	PGMMODE_REAL,
267	/** Protected mode, no paging. */
268	PGMMODE_PROTECTED,
269	/** 32-bit paging. */
270	PGMMODE_32_BIT,
271	/** PAE paging. */
272	PGMMODE_PAE,
273	/** PAE paging with NX enabled. */
274	PGMMODE_PAE_NX,
275	/** 64-bit AMD paging (long mode). */
276	PGMMODE_AMD64,
277	/** 64-bit AMD paging (long mode) with NX enabled. */
278	PGMMODE_AMD64_NX,
279	/** 32-bit nested paging mode (shadow only; guest physical to host physical). */
280	PGMMODE_NESTED_32BIT,
281	/** PAE nested paging mode (shadow only; guest physical to host physical). */
282	PGMMODE_NESTED_PAE,
283	/** AMD64 nested paging mode (shadow only; guest physical to host physical). */
284	PGMMODE_NESTED_AMD64,
285	/** Extended paging (Intel) mode. */
286	PGMMODE_EPT,
287	/** Special mode used by NEM to indicate no shadow paging necessary. */
288	PGMMODE_NONE,
289	#else
290	/** Paging is not enabled by the guest. */
291	PGMMODE_NONE,
292	/** VMSAv8-32 Virtual Memory System Architecture v8 - 32-bit variant enabled. */
293	PGMMODE_VMSA_V8_32,
294	/** VMSAv8-64 Virtual Memory System Architecture v8 - 64-bit variant enabled. */
295	PGMMODE_VMSA_V8_64,
296	#endif
297	/** The max number of modes */
298	PGMMODE_MAX,
299	/** 32bit hackishness. */
300	PGMMODE_32BIT_HACK = 0x7fffffff
301	} PGMMODE;
302
303
304	/**
305	* Second level address translation (SLAT) mode.
306	*/
307	typedef enum PGMSLAT
308	{
309	/** The usual invalid value. */
310	PGMSLAT_INVALID = 0,
311	/** No second level translation. */
312	PGMSLAT_DIRECT,
313	/** Intel Extended Page Tables (EPT). */
314	PGMSLAT_EPT,
315	/** AMD-V Nested Paging 32-bit. */
316	PGMSLAT_32BIT,
317	/** AMD-V Nested Paging PAE. */
318	PGMSLAT_PAE,
319	/** AMD-V Nested Paging 64-bit. */
320	PGMSLAT_AMD64,
321	/** 32bit hackishness. */
322	PGMSLAT_32BIT_HACK = 0x7fffffff
323	} PGMSLAT;
324
325
326	/** @name PGMPTWALK::fFailed flags.
327	* These flags indicate the type of a page-walk failure.
328	* @{
329	*/
330	typedef uint32_t PGMWALKFAIL;
331	/** No fault. */
332	#define PGM_WALKFAIL_SUCCESS UINT32_C(0)
333
334	/** Not present (X86_TRAP_PF_P). */
335	#define PGM_WALKFAIL_NOT_PRESENT RT_BIT_32(0)
336	/** Reserved bit set in table entry (X86_TRAP_PF_RSVD). */
337	#define PGM_WALKFAIL_RESERVED_BITS RT_BIT_32(1)
338	/** Bad physical address (VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS). */
339	#define PGM_WALKFAIL_BAD_PHYSICAL_ADDRESS RT_BIT_32(2)
340
341	/** EPT violation - Intel. */
342	#define PGM_WALKFAIL_EPT_VIOLATION RT_BIT_32(3)
343	/** EPT violation, convertible to \#VE exception - Intel. */
344	#define PGM_WALKFAIL_EPT_VIOLATION_CONVERTIBLE RT_BIT_32(4)
345	/** EPT misconfiguration - Intel. */
346	#define PGM_WALKFAIL_EPT_MISCONFIG RT_BIT_32(5)
347	/** Mask of all EPT induced page-walk failures - Intel. */
348	#define PGM_WALKFAIL_EPT ( PGM_WALKFAIL_EPT_VIOLATION \
349	\| PGM_WALKFAIL_EPT_VIOLATION_CONVERTIBLE \
350	\| PGM_WALKFAIL_EPT_MISCONFIG)
351
352	/** Access denied: Not writable (VERR_ACCESS_DENIED). */
353	#define PGM_WALKFAIL_NOT_WRITABLE RT_BIT_32(6)
354	/** Access denied: Not executable (VERR_ACCESS_DENIED). */
355	#define PGM_WALKFAIL_NOT_EXECUTABLE RT_BIT_32(7)
356	/** Access denied: Not user/supervisor mode accessible (VERR_ACCESS_DENIED). */
357	#define PGM_WALKFAIL_NOT_ACCESSIBLE_BY_MODE RT_BIT_32(8)
358
359	/** The level the problem arrised at.
360	* PTE is level 1, PDE is level 2, PDPE is level 3, PML4 is level 4, CR3 is
361	* level 8. This is 0 on success. */
362	#define PGM_WALKFAIL_LEVEL_MASK UINT32_C(0x0000f100)
363	/** Level shift (see PGM_WALKFAIL_LEVEL_MASK). */
364	#define PGM_WALKFAIL_LEVEL_SHIFT 11
365
366	/** @} */
367
368
369	/** @name PGM_PTATTRS_XXX - PGM page-table attributes.
370	*
371	* This is VirtualBox's combined page table attributes. It combines regular page
372	* table and Intel EPT attributes. It's 64-bit in size so there's ample room for
373	* bits added in the future to EPT or regular page tables (for e.g. Protection Key).
374	*
375	* The following bits map 1:1 (shifted by PGM_PTATTRS_EPT_SHIFT) to the Intel EPT
376	* attributes as these are unique to EPT and fit within 64-bits despite the shift:
377	* - EPT_R : Read access.
378	* - EPT_W : Write access.
379	* - EPT_X_SUPER : Execute or execute for supervisor-mode linear addr access.
380	* - EPT_MEMTYPE : EPT memory type.
381	* - EPT_IGNORE_PAT: Ignore PAT memory type.
382	* - EPT_X_USER : Execute access for user-mode linear addresses.
383	*
384	* For regular page tables, the R bit is always 1 (same as P bit).
385	* For Intel EPT, the EPT_R and EPT_W bits are copied to R and W bits respectively.
386	*
387	* The following EPT attributes are mapped to the following positions because they
388	* exist in the regular page tables at these positions OR are exclusive to EPT and
389	* have been mapped to arbitrarily chosen positions:
390	* - EPT_A : Accessed (EPT bit 8 maps to bit 5).
391	* - EPT_D : Dirty (EPT bit 9 maps to bit 6).
392	* - EPT_SUPER_SHW_STACK : Supervisor Shadow Stack (EPT bit 60 maps to bit 24).
393	* - EPT_SUPPRESS_VE_XCPT: Suppress \#VE exception (EPT bit 63 maps to bit 25).
394	*
395	* Bits 12, 11:9 and 43 are deliberately kept unused (correspond to bit PS and bits
396	* 11:9 in the regular page-table structures and to bit 11 in the EPT structures
397	* respectively) as bit 12 is the page-size bit and bits 11:9 are reserved for
398	* use by software and we may want to use/preserve them in the future.
399	*
400	* @{ */
401	typedef uint64_t PGMPTATTRS;
402	/** Pointer to a PGMPTATTRS type. */
403	typedef PGMPTATTRS *PPGMPTATTRS;
404
405	/** Read bit (always 1 for regular PT, copy of EPT_R for EPT). */
406	#define PGM_PTATTRS_R_SHIFT 0
407	#define PGM_PTATTRS_R_MASK RT_BIT_64(PGM_PTATTRS_R_SHIFT)
408	/** Write access bit (aka read/write bit for regular PT). */
409	#define PGM_PTATTRS_W_SHIFT 1
410	#define PGM_PTATTRS_W_MASK RT_BIT_64(PGM_PTATTRS_W_SHIFT)
411	/** User-mode access bit. */
412	#define PGM_PTATTRS_US_SHIFT 2
413	#define PGM_PTATTRS_US_MASK RT_BIT_64(PGM_PTATTRS_US_SHIFT)
414	/** Write through cache bit. */
415	#define PGM_PTATTRS_PWT_SHIFT 3
416	#define PGM_PTATTRS_PWT_MASK RT_BIT_64(PGM_PTATTRS_PWT_SHIFT)
417	/** Cache disabled bit. */
418	#define PGM_PTATTRS_PCD_SHIFT 4
419	#define PGM_PTATTRS_PCD_MASK RT_BIT_64(PGM_PTATTRS_PCD_SHIFT)
420	/** Accessed bit. */
421	#define PGM_PTATTRS_A_SHIFT 5
422	#define PGM_PTATTRS_A_MASK RT_BIT_64(PGM_PTATTRS_A_SHIFT)
423	/** Dirty bit. */
424	#define PGM_PTATTRS_D_SHIFT 6
425	#define PGM_PTATTRS_D_MASK RT_BIT_64(PGM_PTATTRS_D_SHIFT)
426	/** The PAT bit. */
427	#define PGM_PTATTRS_PAT_SHIFT 7
428	#define PGM_PTATTRS_PAT_MASK RT_BIT_64(PGM_PTATTRS_PAT_SHIFT)
429	/** The global bit. */
430	#define PGM_PTATTRS_G_SHIFT 8
431	#define PGM_PTATTRS_G_MASK RT_BIT_64(PGM_PTATTRS_G_SHIFT)
432	/** Reserved (bits 12:9) unused. */
433	#define PGM_PTATTRS_RSVD_12_9_SHIFT 9
434	#define PGM_PTATTRS_RSVD_12_9_MASK UINT64_C(0x0000000000001e00)
435	/** Read access bit - EPT only. */
436	#define PGM_PTATTRS_EPT_R_SHIFT 13
437	#define PGM_PTATTRS_EPT_R_MASK RT_BIT_64(PGM_PTATTRS_EPT_R_SHIFT)
438	/** Write access bit - EPT only. */
439	#define PGM_PTATTRS_EPT_W_SHIFT 14
440	#define PGM_PTATTRS_EPT_W_MASK RT_BIT_64(PGM_PTATTRS_EPT_W_SHIFT)
441	/** Execute or execute access for supervisor-mode linear addresses - EPT only. */
442	#define PGM_PTATTRS_EPT_X_SUPER_SHIFT 15
443	#define PGM_PTATTRS_EPT_X_SUPER_MASK RT_BIT_64(PGM_PTATTRS_EPT_X_SUPER_SHIFT)
444	/** EPT memory type - EPT only. */
445	#define PGM_PTATTRS_EPT_MEMTYPE_SHIFT 16
446	#define PGM_PTATTRS_EPT_MEMTYPE_MASK UINT64_C(0x0000000000070000)
447	/** Ignore PAT memory type - EPT only. */
448	#define PGM_PTATTRS_EPT_IGNORE_PAT_SHIFT 19
449	#define PGM_PTATTRS_EPT_IGNORE_PAT_MASK RT_BIT_64(PGM_PTATTRS_EPT_IGNORE_PAT_SHIFT)
450	/** Leaf paging entry (big or regular) - EPT only. */
451	#define PGM_PTATTRS_EPT_LEAF_SHIFT 20
452	#define PGM_PTATTRS_EPT_LEAF_MASK RT_BIT_64(PGM_PTATTRS_EPT_LEAF_SHIFT)
453	/** Accessed bit - EPT only. */
454	#define PGM_PTATTRS_EPT_A_SHIFT 21
455	#define PGM_PTATTRS_EPT_A_MASK RT_BIT_64(PGM_PTATTRS_EPT_A_SHIFT)
456	/** Dirty bit - EPT only. */
457	#define PGM_PTATTRS_EPT_D_SHIFT 22
458	#define PGM_PTATTRS_EPT_D_MASK RT_BIT_64(PGM_PTATTRS_EPT_D_SHIFT)
459	/** Execute access for user-mode linear addresses - EPT only. */
460	#define PGM_PTATTRS_EPT_X_USER_SHIFT 23
461	#define PGM_PTATTRS_EPT_X_USER_MASK RT_BIT_64(PGM_PTATTRS_EPT_X_USER_SHIFT)
462	/** Reserved (bits 29:24) - unused. */
463	#define PGM_PTATTRS_RSVD_29_24_SHIFT 24
464	#define PGM_PTATTRS_RSVD_29_24_MASK UINT64_C(0x000000003f000000)
465	/** Verify Guest Paging - EPT only. */
466	#define PGM_PTATTRS_EPT_VGP_SHIFT 30
467	#define PGM_PTATTRS_EPT_VGP_MASK RT_BIT_64(PGM_PTATTRS_EPT_VGP_SHIFT)
468	/** Paging-write - EPT only. */
469	#define PGM_PTATTRS_EPT_PW_SHIFT 31
470	#define PGM_PTATTRS_EPT_PW_MASK RT_BIT_64(PGM_PTATTRS_EPT_PW_SHIFT)
471	/** Reserved (bit 32) - unused. */
472	#define PGM_PTATTRS_RSVD_32_SHIFT 32
473	#define PGM_PTATTRS_RSVD_32_MASK UINT64_C(0x0000000100000000)
474	/** Supervisor shadow stack - EPT only. */
475	#define PGM_PTATTRS_EPT_SSS_SHIFT 33
476	#define PGM_PTATTRS_EPT_SSS_MASK RT_BIT_64(PGM_PTATTRS_EPT_SSS_SHIFT)
477	/** Sub-page write permission - EPT only. */
478	#define PGM_PTATTRS_EPT_SPP_SHIFT 34
479	#define PGM_PTATTRS_EPT_SPP_MASK RT_BIT_64(PGM_PTATTRS_EPT_SPP_SHIFT)
480	/** Reserved (bit 35) - unused. */
481	#define PGM_PTATTRS_RSVD_35_SHIFT 35
482	#define PGM_PTATTRS_RSVD_35_MASK UINT64_C(0x0000000800000000)
483	/** Suppress \#VE exception - EPT only. */
484	#define PGM_PTATTRS_EPT_SVE_SHIFT 36
485	#define PGM_PTATTRS_EPT_SVE_MASK RT_BIT_64(PGM_PTATTRS_EPT_SVE_SHIFT)
486	/** Reserved (bits 62:37) - unused. */
487	#define PGM_PTATTRS_RSVD_62_37_SHIFT 37
488	#define PGM_PTATTRS_RSVD_62_37_MASK UINT64_C(0x7fffffe000000000)
489	/** No-execute bit. */
490	#define PGM_PTATTRS_NX_SHIFT 63
491	#define PGM_PTATTRS_NX_MASK RT_BIT_64(PGM_PTATTRS_NX_SHIFT)
492
493	RT_BF_ASSERT_COMPILE_CHECKS(PGM_PTATTRS_, UINT64_C(0), UINT64_MAX,
494	(R, W, US, PWT, PCD, A, D, PAT, G, RSVD_12_9, EPT_R, EPT_W, EPT_X_SUPER, EPT_MEMTYPE, EPT_IGNORE_PAT,
495	EPT_LEAF, EPT_A, EPT_D, EPT_X_USER, RSVD_29_24, EPT_VGP, EPT_PW, RSVD_32, EPT_SSS, EPT_SPP,
496	RSVD_35, EPT_SVE, RSVD_62_37, NX));
497
498	/** The bit position where the EPT specific attributes begin. */
499	#define PGM_PTATTRS_EPT_SHIFT PGM_PTATTRS_EPT_R_SHIFT
500	/** The mask of EPT bits (bits 36:ATTR_SHIFT). In the future we might choose to
501	* use higher unused bits for something else, in that case adjust this mask. */
502	#define PGM_PTATTRS_EPT_MASK UINT64_C(0x0000001fffffe000)
503
504	/** The mask of all PGM page attribute bits for regular page-tables. */
505	#define PGM_PTATTRS_PT_VALID_MASK ( PGM_PTATTRS_R_MASK \
506	\| PGM_PTATTRS_W_MASK \
507	\| PGM_PTATTRS_US_MASK \
508	\| PGM_PTATTRS_PWT_MASK \
509	\| PGM_PTATTRS_PCD_MASK \
510	\| PGM_PTATTRS_A_MASK \
511	\| PGM_PTATTRS_D_MASK \
512	\| PGM_PTATTRS_PAT_MASK \
513	\| PGM_PTATTRS_G_MASK \
514	\| PGM_PTATTRS_NX_MASK)
515
516	/** The mask of all PGM page attribute bits for EPT. */
517	#define PGM_PTATTRS_EPT_VALID_MASK ( PGM_PTATTRS_EPT_R_MASK \
518	\| PGM_PTATTRS_EPT_W_MASK \
519	\| PGM_PTATTRS_EPT_X_SUPER_MASK \
520	\| PGM_PTATTRS_EPT_MEMTYPE_MASK \
521	\| PGM_PTATTRS_EPT_IGNORE_PAT_MASK \
522	\| PGM_PTATTRS_EPT_LEAF_MASK \
523	\| PGM_PTATTRS_EPT_A_MASK \
524	\| PGM_PTATTRS_EPT_D_MASK \
525	\| PGM_PTATTRS_EPT_X_USER_MASK \
526	\| PGM_PTATTRS_EPT_VGP_MASK \
527	\| PGM_PTATTRS_EPT_PW_MASK \
528	\| PGM_PTATTRS_EPT_SSS_MASK \
529	\| PGM_PTATTRS_EPT_SPP_MASK \
530	\| PGM_PTATTRS_EPT_SVE_MASK)
531
532	/* The mask of all PGM page attribute bits (combined). */
533	#define PGM_PTATTRS_VALID_MASK (PGM_PTATTRS_PT_VALID_MASK \| PGM_PTATTRS_EPT_VALID_MASK)
534
535	/* Verify bits match the regular PT bits. */
536	AssertCompile(PGM_PTATTRS_W_SHIFT == X86_PTE_BIT_RW);
537	AssertCompile(PGM_PTATTRS_US_SHIFT == X86_PTE_BIT_US);
538	AssertCompile(PGM_PTATTRS_PWT_SHIFT == X86_PTE_BIT_PWT);
539	AssertCompile(PGM_PTATTRS_PCD_SHIFT == X86_PTE_BIT_PCD);
540	AssertCompile(PGM_PTATTRS_A_SHIFT == X86_PTE_BIT_A);
541	AssertCompile(PGM_PTATTRS_D_SHIFT == X86_PTE_BIT_D);
542	AssertCompile(PGM_PTATTRS_PAT_SHIFT == X86_PTE_BIT_PAT);
543	AssertCompile(PGM_PTATTRS_G_SHIFT == X86_PTE_BIT_G);
544	AssertCompile(PGM_PTATTRS_W_MASK == X86_PTE_RW);
545	AssertCompile(PGM_PTATTRS_US_MASK == X86_PTE_US);
546	AssertCompile(PGM_PTATTRS_PWT_MASK == X86_PTE_PWT);
547	AssertCompile(PGM_PTATTRS_PCD_MASK == X86_PTE_PCD);
548	AssertCompile(PGM_PTATTRS_A_MASK == X86_PTE_A);
549	AssertCompile(PGM_PTATTRS_D_MASK == X86_PTE_D);
550	AssertCompile(PGM_PTATTRS_PAT_MASK == X86_PTE_PAT);
551	AssertCompile(PGM_PTATTRS_G_MASK == X86_PTE_G);
552	AssertCompile(PGM_PTATTRS_NX_MASK == X86_PTE_PAE_NX);
553
554	/* Verify those EPT bits that must map 1:1 (after shifting). */
555	AssertCompile(PGM_PTATTRS_EPT_R_SHIFT - PGM_PTATTRS_EPT_SHIFT == EPT_E_BIT_READ);
556	AssertCompile(PGM_PTATTRS_EPT_W_SHIFT - PGM_PTATTRS_EPT_SHIFT == EPT_E_BIT_WRITE);
557	AssertCompile(PGM_PTATTRS_EPT_X_SUPER_SHIFT - PGM_PTATTRS_EPT_SHIFT == EPT_E_BIT_EXECUTE);
558	AssertCompile(PGM_PTATTRS_EPT_IGNORE_PAT_SHIFT - PGM_PTATTRS_EPT_SHIFT == EPT_E_BIT_IGNORE_PAT);
559	AssertCompile(PGM_PTATTRS_EPT_X_USER_SHIFT - PGM_PTATTRS_EPT_SHIFT == EPT_E_BIT_USER_EXECUTE);
560	/** @} */
561
562
563	/**
564	* Page table walk information.
565	*
566	* This provides extensive information regarding page faults (or EPT
567	* violations/misconfigurations) while traversing page tables.
568	*/
569	typedef struct PGMPTWALK
570	{
571	/** The linear address that is being resolved (input). */
572	RTGCPTR GCPtr;
573
574	/** The second-level physical address (input/output).
575	* @remarks only valid if fIsSlat is set. */
576	RTGCPHYS GCPhysNested;
577
578	/** The physical address that is the result of the walk (output). */
579	RTGCPHYS GCPhys;
580
581	/** Set if the walk succeeded. */
582	bool fSucceeded;
583	/** Whether this is a second-level address translation. */
584	bool fIsSlat;
585	/** Whether the linear address (GCPtr) caused the second-level
586	* address translation. */
587	bool fIsLinearAddrValid;
588	/** The level problem arrised at.
589	* PTE is level 1, PDE is level 2, PDPE is level 3, PML4 is level 4, CR3 is
590	* level 8. This is 0 on success. */
591	uint8_t uLevel;
592	/** Set if the page isn't present. */
593	bool fNotPresent;
594	/** Encountered a bad physical address. */
595	bool fBadPhysAddr;
596	/** Set if there was reserved bit violations. */
597	bool fRsvdError;
598	/** Set if it involves a big page (2/4 MB). */
599	bool fBigPage;
600	/** Set if it involves a gigantic page (1 GB). */
601	bool fGigantPage;
602	bool afPadding[3];
603	/** Page-walk failure type, PGM_WALKFAIL_XXX. */
604	PGMWALKFAIL fFailed;
605
606	/** The effective page-table attributes, PGM_PTATTRS_XXX. */
607	PGMPTATTRS fEffective;
608	} PGMPTWALK;
609	/** Pointer to page walk information. */
610	typedef PGMPTWALK *PPGMPTWALK;
611	/** Pointer to const page walk information. */
612	typedef PGMPTWALK const *PCPGMPTWALK;
613
614
615	/** @name PGM_WALKINFO_XXX - flag based PGM page table walk info.
616	* @{ */
617	/** Set if the walk succeeded. */
618	#define PGM_WALKINFO_SUCCEEDED RT_BIT_32(0)
619	/** Whether this is a second-level address translation. */
620	#define PGM_WALKINFO_IS_SLAT RT_BIT_32(1)
621
622	/** Set if it involves a big page (2/4 MB). */
623	#define PGM_WALKINFO_BIG_PAGE RT_BIT_32(7)
624	/** Set if it involves a gigantic page (1 GB). */
625	#define PGM_WALKINFO_GIGANTIC_PAGE RT_BIT_32(8)
626
627	/** Whether the linear address (GCPtr) caused the second-level
628	* address translation - read the code to figure this one.
629	* @todo for PGMPTWALKFAST::fFailed? */
630	#define PGM_WALKINFO_IS_LINEAR_ADDR_VALID RT_BIT_32(10)
631	/** @} */
632
633	/**
634	* Fast page table walk information.
635	*
636	* This is a slimmed down version of PGMPTWALK for use by IEM.
637	*/
638	typedef struct PGMPTWALKFAST
639	{
640	/** The linear address that is being resolved (input). */
641	RTGCPTR GCPtr;
642
643	/** The physical address that is the result of the walk (output).
644	* This includes the offset mask from the GCPtr input value. */
645	RTGCPHYS GCPhys;
646
647	/** The second-level physical address (input/output).
648	* @remarks only valid if fIsSlat is set. */
649	RTGCPHYS GCPhysNested;
650
651	/** Walk information PGM_WALKINFO_XXX (output). */
652	uint32_t fInfo;
653	/** Page-walk failure type, PGM_WALKFAIL_XXX (output). */
654	PGMWALKFAIL fFailed;
655
656	/** The effective page-table attributes, PGM_PTATTRS_XXX (output). */
657	PGMPTATTRS fEffective;
658	} PGMPTWALKFAST;
659	/** Pointer to fast page walk information. */
660	typedef PGMPTWALKFAST *PPGMPTWALKFAST;
661	/** Pointer to const fast page walk information. */
662	typedef PGMPTWALKFAST const *PCPGMPTWALKFAST;
663
664	#define PGMPTWALKFAST_ZERO(a_pWalkFast) do { \
665	(a_pWalkFast)->GCPtr = 0; \
666	(a_pWalkFast)->GCPhys = 0; \
667	(a_pWalkFast)->GCPhysNested = 0; \
668	(a_pWalkFast)->fInfo = 0; \
669	(a_pWalkFast)->fFailed = 0; \
670	(a_pWalkFast)->fEffective = 0; \
671	} while (0)
672
673
674	#ifndef VBOX_VMM_TARGET_ARMV8
675	/** Macro for checking if the guest is using paging.
676	* @param enmMode PGMMODE_*.
677	* @remark ASSUMES certain order of the PGMMODE_* values.
678	*/
679	# define PGMMODE_WITH_PAGING(enmMode) ((enmMode) >= PGMMODE_32_BIT)
680
681	/** Macro for checking if it's one of the long mode modes.
682	* @param enmMode PGMMODE_*.
683	*/
684	# define PGMMODE_IS_64BIT_MODE(enmMode) ((enmMode) == PGMMODE_AMD64_NX \|\| (enmMode) == PGMMODE_AMD64)
685
686	/** Macro for checking if it's one of the AMD64 nested modes.
687	* @param enmMode PGMMODE_*.
688	*/
689	# define PGMMODE_IS_NESTED(enmMode) ( (enmMode) == PGMMODE_NESTED_32BIT \
690	\|\| (enmMode) == PGMMODE_NESTED_PAE \
691	\|\| (enmMode) == PGMMODE_NESTED_AMD64)
692
693	/** Macro for checking if it's one of the PAE modes.
694	* @param enmMode PGMMODE_*.
695	*/
696	# define PGMMODE_IS_PAE(enmMode) ( (enmMode) == PGMMODE_PAE \
697	\|\| (enmMode) == PGMMODE_PAE_NX)
698	#else
699	/** Macro for checking if the guest is using paging.
700	* @param enmMode PGMMODE_*.
701	* @remark ASSUMES certain order of the PGMMODE_* values.
702	*/
703	# define PGMMODE_WITH_PAGING(enmMode) ((enmMode) > PGMMODE_NONE)
704
705	/** Macro for checking if it's the 64-bit translation mode.
706	* @param enmMode PGMMODE_*.
707	*/
708	# define PGMMODE_IS_64BIT_MODE(enmMode) ((enmMode) == PGMMODE_VMSA_V8_64)
709	#endif
710
711
712	/**
713	* Is the ROM mapped (true) or is the shadow RAM mapped (false).
714	*
715	* @returns boolean.
716	* @param enmProt The PGMROMPROT value, must be valid.
717	*/
718	#define PGMROMPROT_IS_ROM(enmProt) \
719	( (enmProt) == PGMROMPROT_READ_ROM_WRITE_IGNORE \
720	\|\| (enmProt) == PGMROMPROT_READ_ROM_WRITE_RAM )
721
722
723	VMMDECL(bool) PGMIsLockOwner(PVMCC pVM);
724
725	VMMDECL(int) PGMRegisterStringFormatTypes(void);
726	VMMDECL(void) PGMDeregisterStringFormatTypes(void);
727	VMMDECL(RTHCPHYS) PGMGetHyperCR3(PVMCPU pVCpu);
728	VMMDECL(int) PGMTrap0eHandler(PVMCPUCC pVCpu, RTGCUINT uErr, PCPUMCTX pCtx, RTGCPTR pvFault);
729	VMMDECL(int) PGMPrefetchPage(PVMCPUCC pVCpu, RTGCPTR GCPtrPage);
730	VMMDECL(VBOXSTRICTRC) PGMInterpretInstruction(PVMCPUCC pVCpu, RTGCPTR pvFault);
731	VMMDECL(int) PGMShwGetPage(PVMCPUCC pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys);
732	VMMDECL(int) PGMShwMakePageReadonly(PVMCPUCC pVCpu, RTGCPTR GCPtr, uint32_t fFlags);
733	VMMDECL(int) PGMShwMakePageWritable(PVMCPUCC pVCpu, RTGCPTR GCPtr, uint32_t fFlags);
734	VMMDECL(int) PGMShwMakePageNotPresent(PVMCPUCC pVCpu, RTGCPTR GCPtr, uint32_t fFlags);
735	/** @name Flags for PGMShwMakePageReadonly, PGMShwMakePageWritable and
736	* PGMShwMakePageNotPresent
737	* @{ */
738	/** The call is from an access handler for dealing with the a faulting write
739	* operation. The virtual address is within the same page. */
740	#define PGM_MK_PG_IS_WRITE_FAULT RT_BIT(0)
741	/** The page is an MMIO2. */
742	#define PGM_MK_PG_IS_MMIO2 RT_BIT(1)
743	/** @}*/
744	VMMDECL(int) PGMGstGetPage(PVMCPUCC pVCpu, RTGCPTR GCPtr, PPGMPTWALK pWalk);
745	/** @name PGMQPAGE_F_XXX - Flags for PGMGstQueryPageFast
746	* @{ */
747	/** Querying for read access, set A bits accordingly. */
748	#define PGMQPAGE_F_READ RT_BIT_32(0)
749	/** Querying for write access, set A bits and D bit accordingly.
750	* Don't set leaf entry bits if is read-only. */
751	#define PGMQPAGE_F_WRITE RT_BIT_32(1)
752	/** Querying for execute access, set A bits accordingly. */
753	#define PGMQPAGE_F_EXECUTE RT_BIT_32(2)
754	/** The query is for a user mode access, so don't set leaf A or D bits
755	* unless the effective access allows usermode access.
756	* Assume supervisor access when not set. */
757	#define PGMQPAGE_F_USER_MODE RT_BIT_32(3)
758	/** Treat CR0.WP as zero when evalutating the access.
759	* @note Same value as X86_CR0_WP. */
760	#define PGMQPAGE_F_CR0_WP0 RT_BIT_32(16)
761	/** The valid flag mask. */
762	#define PGMQPAGE_F_VALID_MASK UINT32_C(0x0001000f)
763	/** @} */
764	VMM_INT_DECL(int) PGMGstQueryPageFast(PVMCPUCC pVCpu, RTGCPTR GCPtr, uint32_t fFlags, PPGMPTWALKFAST pWalkFast);
765	VMMDECL(int) PGMGstModifyPage(PVMCPUCC pVCpu, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask);
766	VMM_INT_DECL(bool) PGMGstArePaePdpesValid(PVMCPUCC pVCpu, PCX86PDPE paPaePdpes);
767	VMM_INT_DECL(int) PGMGstMapPaePdpes(PVMCPUCC pVCpu, PCX86PDPE paPaePdpes);
768	VMM_INT_DECL(int) PGMGstMapPaePdpesAtCr3(PVMCPUCC pVCpu, uint64_t cr3);
769
770	VMMDECL(int) PGMInvalidatePage(PVMCPUCC pVCpu, RTGCPTR GCPtrPage);
771	VMMDECL(int) PGMFlushTLB(PVMCPUCC pVCpu, uint64_t cr3, bool fGlobal);
772	VMMDECL(int) PGMSyncCR3(PVMCPUCC pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal);
773	VMMDECL(int) PGMUpdateCR3(PVMCPUCC pVCpu, uint64_t cr3);
774	VMMDECL(int) PGMChangeMode(PVMCPUCC pVCpu, uint64_t cr0, uint64_t cr4, uint64_t efer, bool fForce);
775	VMM_INT_DECL(int) PGMHCChangeMode(PVMCC pVM, PVMCPUCC pVCpu, PGMMODE enmGuestMode, bool fForce);
776	VMMDECL(void) PGMCr0WpEnabled(PVMCPUCC pVCpu);
777	VMMDECL(PGMMODE) PGMGetGuestMode(PVMCPU pVCpu);
778	VMMDECL(PGMMODE) PGMGetShadowMode(PVMCPU pVCpu);
779	VMMDECL(PGMMODE) PGMGetHostMode(PVM pVM);
780	VMMDECL(const char *) PGMGetModeName(PGMMODE enmMode);
781	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
782	VMM_INT_DECL(const char *) PGMGetSlatModeName(PGMSLAT enmSlatMode);
783	#endif
784	VMM_INT_DECL(RTGCPHYS) PGMGetGuestCR3Phys(PVMCPU pVCpu);
785	VMM_INT_DECL(void) PGMNotifyNxeChanged(PVMCPU pVCpu, bool fNxe);
786	VMMDECL(bool) PGMHasDirtyPages(PVM pVM);
787	VMM_INT_DECL(void) PGMSetGuestEptPtr(PVMCPUCC pVCpu, uint64_t uEptPtr);
788
789	/** PGM physical access handler type registration handle (heap offset, valid
790	* cross contexts without needing fixing up). Callbacks and handler type is
791	* associated with this and it is shared by all handler registrations. */
792	typedef uint64_t PGMPHYSHANDLERTYPE;
793	/** Pointer to a PGM physical handler type registration handle. */
794	typedef PGMPHYSHANDLERTYPE *PPGMPHYSHANDLERTYPE;
795	/** NIL value for PGM physical access handler type handle. */
796	#define NIL_PGMPHYSHANDLERTYPE UINT64_MAX
797	VMMDECL(int) PGMHandlerPhysicalRegister(PVMCC pVM, RTGCPHYS GCPhys, RTGCPHYS GCPhysLast, PGMPHYSHANDLERTYPE hType,
798	uint64_t uUser, R3PTRTYPE(const char *) pszDesc);
799	VMMDECL(int) PGMHandlerPhysicalRegisterVmxApicAccessPage(PVMCC pVM, RTGCPHYS GCPhys, PGMPHYSHANDLERTYPE hType);
800	VMMDECL(int) PGMHandlerPhysicalModify(PVMCC pVM, RTGCPHYS GCPhysCurrent, RTGCPHYS GCPhys, RTGCPHYS GCPhysLast);
801	VMMDECL(int) PGMHandlerPhysicalDeregister(PVMCC pVM, RTGCPHYS GCPhys);
802	VMMDECL(int) PGMHandlerPhysicalChangeUserArg(PVMCC pVM, RTGCPHYS GCPhys, uint64_t uUser);
803	VMMDECL(int) PGMHandlerPhysicalSplit(PVMCC pVM, RTGCPHYS GCPhys, RTGCPHYS GCPhysSplit);
804	VMMDECL(int) PGMHandlerPhysicalJoin(PVMCC pVM, RTGCPHYS GCPhys1, RTGCPHYS GCPhys2);
805	VMMDECL(int) PGMHandlerPhysicalPageTempOff(PVMCC pVM, RTGCPHYS GCPhys, RTGCPHYS GCPhysPage);
806	VMMDECL(int) PGMHandlerPhysicalPageAliasMmio2(PVMCC pVM, RTGCPHYS GCPhys, RTGCPHYS GCPhysPage,
807	PPDMDEVINS pDevIns, PGMMMIO2HANDLE hMmio2, RTGCPHYS offMMio2PageRemap);
808	VMMDECL(int) PGMHandlerPhysicalPageAliasHC(PVMCC pVM, RTGCPHYS GCPhys, RTGCPHYS GCPhysPage, RTHCPHYS HCPhysPageRemap);
809	VMMDECL(int) PGMHandlerPhysicalReset(PVMCC pVM, RTGCPHYS GCPhys);
810	VMMDECL(bool) PGMHandlerPhysicalIsRegistered(PVMCC pVM, RTGCPHYS GCPhys);
811
812	/** @name PGMPHYSHANDLER_F_XXX - flags for PGMR3HandlerPhysicalTypeRegister and PGMR0HandlerPhysicalTypeRegister
813	* @{ */
814	/** Whether to hold the PGM lock while calling the handler or not.
815	* Mainly an optimization for PGM callers. */
816	#define PGMPHYSHANDLER_F_KEEP_PGM_LOCK RT_BIT_32(0)
817	/** The uUser value is a ring-0 device instance index that needs translating
818	* into a PDMDEVINS pointer before calling the handler. This is a hack to make
819	* it possible to use access handlers in devices. */
820	#define PGMPHYSHANDLER_F_R0_DEVINS_IDX RT_BIT_32(1)
821	/** Don't apply the access handler to VT-x and AMD-V. Only works with full pages.
822	* This is a trick for the VT-x APIC access page in nested VT-x setups. */
823	#define PGMPHYSHANDLER_F_NOT_IN_HM RT_BIT_32(2)
824	/** Mask of valid bits. */
825	#define PGMPHYSHANDLER_F_VALID_MASK UINT32_C(7)
826	/** @} */
827
828
829	/**
830	* Page type.
831	*
832	* @remarks This enum has to fit in a 3-bit field (see PGMPAGE::u3Type).
833	* @remarks This is used in the saved state, so changes to it requires bumping
834	* the saved state version.
835	* @todo So, convert to \#defines!
836	*/
837	typedef enum PGMPAGETYPE
838	{
839	/** The usual invalid zero entry. */
840	PGMPAGETYPE_INVALID = 0,
841	/** RAM page. (RWX) */
842	PGMPAGETYPE_RAM,
843	/** MMIO2 page. (RWX) */
844	PGMPAGETYPE_MMIO2,
845	/** MMIO2 page aliased over an MMIO page. (RWX)
846	* See PGMHandlerPhysicalPageAlias(). */
847	PGMPAGETYPE_MMIO2_ALIAS_MMIO,
848	/** Special page aliased over an MMIO page. (RWX)
849	* See PGMHandlerPhysicalPageAliasHC(), but this is generally only used for
850	* VT-x's APIC access page at the moment. Treated as MMIO by everyone except
851	* the shadow paging code. */
852	PGMPAGETYPE_SPECIAL_ALIAS_MMIO,
853	/** Shadowed ROM. (RWX) */
854	PGMPAGETYPE_ROM_SHADOW,
855	/** ROM page. (R-X) */
856	PGMPAGETYPE_ROM,
857	/** MMIO page. (---) */
858	PGMPAGETYPE_MMIO,
859	/** End of valid entries. */
860	PGMPAGETYPE_END
861	} PGMPAGETYPE;
862	AssertCompile(PGMPAGETYPE_END == 8);
863
864	/** @name PGM page type predicates.
865	* @{ */
866	#define PGMPAGETYPE_IS_READABLE(a_enmType) ( (a_enmType) <= PGMPAGETYPE_ROM )
867	#define PGMPAGETYPE_IS_WRITEABLE(a_enmType) ( (a_enmType) <= PGMPAGETYPE_ROM_SHADOW )
868	#define PGMPAGETYPE_IS_RWX(a_enmType) ( (a_enmType) <= PGMPAGETYPE_ROM_SHADOW )
869	#define PGMPAGETYPE_IS_ROX(a_enmType) ( (a_enmType) == PGMPAGETYPE_ROM )
870	#define PGMPAGETYPE_IS_NP(a_enmType) ( (a_enmType) == PGMPAGETYPE_MMIO )
871	/** @} */
872
873	/**
874	* A physical memory range.
875	*
876	* @note This layout adheres to to GIM Hyper-V specs (asserted while compiling
877	* GIM Hyper-V that uses the PGM API).
878	*/
879	typedef struct PGMPHYSRANGE
880	{
881	/** The first address in the range. */
882	RTGCPHYS GCPhysStart;
883	/** The number of pages in the range. */
884	uint64_t cPages;
885	} PGMPHYSRANGE;
886	AssertCompileSize(PGMPHYSRANGE, 16);
887
888	/**
889	* A list of physical memory ranges.
890	*
891	* @note This layout adheres to to GIM Hyper-V specs (asserted while compiling
892	* GIM Hyper-V that uses the PGM API).
893	*/
894	typedef struct PGMPHYSRANGES
895	{
896	/** The number of ranges in the list. */
897	uint64_t cRanges;
898	/** Array of physical memory ranges. */
899	RT_FLEXIBLE_ARRAY_EXTENSION
900	PGMPHYSRANGE aRanges[RT_FLEXIBLE_ARRAY];
901	} PGMPHYSRANGES;
902	/** Pointer to a list of physical memory ranges. */
903	typedef PGMPHYSRANGES *PPGMPHYSRANGES;
904	/** Pointer to a const list of physical memory ranges. */
905	typedef PGMPHYSRANGES const *PCPGMPHYSRANGES;
906
907
908	VMM_INT_DECL(PGMPAGETYPE) PGMPhysGetPageType(PVMCC pVM, RTGCPHYS GCPhys);
909
910	VMM_INT_DECL(int) PGMPhysGCPhys2HCPhys(PVMCC pVM, RTGCPHYS GCPhys, PRTHCPHYS pHCPhys);
911	VMM_INT_DECL(int) PGMPhysGCPtr2HCPhys(PVMCPUCC pVCpu, RTGCPTR GCPtr, PRTHCPHYS pHCPhys);
912	VMM_INT_DECL(int) PGMPhysGCPhys2CCPtr(PVMCC pVM, RTGCPHYS GCPhys, void **ppv, PPGMPAGEMAPLOCK pLock);
913	VMM_INT_DECL(int) PGMPhysGCPhys2CCPtrReadOnly(PVMCC pVM, RTGCPHYS GCPhys, void const **ppv, PPGMPAGEMAPLOCK pLock);
914	VMM_INT_DECL(int) PGMPhysGCPtr2CCPtr(PVMCPUCC pVCpu, RTGCPTR GCPtr, void **ppv, PPGMPAGEMAPLOCK pLock);
915	VMM_INT_DECL(int) PGMPhysGCPtr2CCPtrReadOnly(PVMCPUCC pVCpu, RTGCPTR GCPtr, void const **ppv, PPGMPAGEMAPLOCK pLock);
916
917	VMMDECL(bool) PGMPhysIsA20Enabled(PVMCPU pVCpu);
918	VMMDECL(bool) PGMPhysIsGCPhysValid(PVMCC pVM, RTGCPHYS GCPhys);
919	VMMDECL(bool) PGMPhysIsGCPhysNormal(PVMCC pVM, RTGCPHYS GCPhys);
920	VMMDECL(int) PGMPhysGCPtr2GCPhys(PVMCPUCC pVCpu, RTGCPTR GCPtr, PRTGCPHYS pGCPhys);
921	VMMDECL(void) PGMPhysReleasePageMappingLock(PVMCC pVM, PPGMPAGEMAPLOCK pLock);
922	VMMDECL(void) PGMPhysBulkReleasePageMappingLocks(PVMCC pVM, uint32_t cPages, PPGMPAGEMAPLOCK paLock);
923
924	/** @def PGM_PHYS_RW_IS_SUCCESS
925	* Check whether a PGMPhysRead, PGMPhysWrite, PGMPhysReadGCPtr or
926	* PGMPhysWriteGCPtr call completed the given task.
927	*
928	* @returns true if completed, false if not.
929	* @param a_rcStrict The status code.
930	* @sa IOM_SUCCESS
931	*/
932	#ifdef IN_RING3
933	# define PGM_PHYS_RW_IS_SUCCESS(a_rcStrict) \
934	( (a_rcStrict) == VINF_SUCCESS \
935	\|\| (a_rcStrict) == VINF_EM_DBG_STOP \
936	\|\| (a_rcStrict) == VINF_EM_DBG_EVENT \
937	\|\| (a_rcStrict) == VINF_EM_DBG_BREAKPOINT \
938	)
939	#elif defined(IN_RING0)
940	# define PGM_PHYS_RW_IS_SUCCESS(a_rcStrict) \
941	( (a_rcStrict) == VINF_SUCCESS \
942	\|\| (a_rcStrict) == VINF_IOM_R3_MMIO_COMMIT_WRITE \
943	\|\| (a_rcStrict) == VINF_EM_OFF \
944	\|\| (a_rcStrict) == VINF_EM_SUSPEND \
945	\|\| (a_rcStrict) == VINF_EM_RESET \
946	\|\| (a_rcStrict) == VINF_EM_HALT \
947	\|\| (a_rcStrict) == VINF_EM_DBG_STOP \
948	\|\| (a_rcStrict) == VINF_EM_DBG_EVENT \
949	\|\| (a_rcStrict) == VINF_EM_DBG_BREAKPOINT \
950	)
951	#elif defined(IN_RC)
952	# define PGM_PHYS_RW_IS_SUCCESS(a_rcStrict) \
953	( (a_rcStrict) == VINF_SUCCESS \
954	\|\| (a_rcStrict) == VINF_IOM_R3_MMIO_COMMIT_WRITE \
955	\|\| (a_rcStrict) == VINF_EM_OFF \
956	\|\| (a_rcStrict) == VINF_EM_SUSPEND \
957	\|\| (a_rcStrict) == VINF_EM_RESET \
958	\|\| (a_rcStrict) == VINF_EM_HALT \
959	\|\| (a_rcStrict) == VINF_SELM_SYNC_GDT \
960	\|\| (a_rcStrict) == VINF_EM_RAW_EMULATE_INSTR_GDT_FAULT \
961	\|\| (a_rcStrict) == VINF_EM_DBG_STOP \
962	\|\| (a_rcStrict) == VINF_EM_DBG_EVENT \
963	\|\| (a_rcStrict) == VINF_EM_DBG_BREAKPOINT \
964	)
965	#endif
966	/** @def PGM_PHYS_RW_DO_UPDATE_STRICT_RC
967	* Updates the return code with a new result.
968	*
969	* Both status codes must be successes according to PGM_PHYS_RW_IS_SUCCESS.
970	*
971	* @param a_rcStrict The current return code, to be updated.
972	* @param a_rcStrict2 The new return code to merge in.
973	*/
974	#ifdef IN_RING3
975	# define PGM_PHYS_RW_DO_UPDATE_STRICT_RC(a_rcStrict, a_rcStrict2) \
976	do { \
977	Assert(rcStrict == VINF_SUCCESS); \
978	Assert(rcStrict2 == VINF_SUCCESS); \
979	} while (0)
980	#elif defined(IN_RING0)
981	# define PGM_PHYS_RW_DO_UPDATE_STRICT_RC(a_rcStrict, a_rcStrict2) \
982	do { \
983	Assert(PGM_PHYS_RW_IS_SUCCESS(rcStrict)); \
984	Assert(PGM_PHYS_RW_IS_SUCCESS(rcStrict2)); \
985	AssertCompile(VINF_IOM_R3_MMIO_COMMIT_WRITE > VINF_EM_LAST); \
986	if ((a_rcStrict2) == VINF_SUCCESS \|\| (a_rcStrict) == (a_rcStrict2)) \
987	{ /* likely */ } \
988	else if ( (a_rcStrict) == VINF_SUCCESS \
989	\|\| (a_rcStrict) > (a_rcStrict2)) \
990	(a_rcStrict) = (a_rcStrict2); \
991	} while (0)
992	#elif defined(IN_RC)
993	# define PGM_PHYS_RW_DO_UPDATE_STRICT_RC(a_rcStrict, a_rcStrict2) \
994	do { \
995	Assert(PGM_PHYS_RW_IS_SUCCESS(rcStrict)); \
996	Assert(PGM_PHYS_RW_IS_SUCCESS(rcStrict2)); \
997	AssertCompile(VINF_SELM_SYNC_GDT > VINF_EM_LAST); \
998	AssertCompile(VINF_EM_RAW_EMULATE_INSTR_GDT_FAULT > VINF_EM_LAST); \
999	AssertCompile(VINF_EM_RAW_EMULATE_INSTR_GDT_FAULT < VINF_SELM_SYNC_GDT); \
1000	AssertCompile(VINF_IOM_R3_MMIO_COMMIT_WRITE > VINF_EM_LAST); \
1001	AssertCompile(VINF_IOM_R3_MMIO_COMMIT_WRITE > VINF_SELM_SYNC_GDT); \
1002	AssertCompile(VINF_IOM_R3_MMIO_COMMIT_WRITE > VINF_EM_RAW_EMULATE_INSTR_GDT_FAULT); \
1003	if ((a_rcStrict2) == VINF_SUCCESS \|\| (a_rcStrict) == (a_rcStrict2)) \
1004	{ /* likely */ } \
1005	else if ((a_rcStrict) == VINF_SUCCESS) \
1006	(a_rcStrict) = (a_rcStrict2); \
1007	else if ( ( (a_rcStrict) > (a_rcStrict2) \
1008	&& ( (a_rcStrict2) <= VINF_EM_RESET \
1009	\|\| (a_rcStrict) != VINF_EM_RAW_EMULATE_INSTR_GDT_FAULT) ) \
1010	\|\| ( (a_rcStrict2) == VINF_EM_RAW_EMULATE_INSTR_GDT_FAULT \
1011	&& (a_rcStrict) > VINF_EM_RESET) ) \
1012	(a_rcStrict) = (a_rcStrict2); \
1013	} while (0)
1014	#endif
1015
1016	VMMDECL(VBOXSTRICTRC) PGMPhysRead(PVMCC pVM, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead, PGMACCESSORIGIN enmOrigin);
1017	VMMDECL(VBOXSTRICTRC) PGMPhysWrite(PVMCC pVM, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite, PGMACCESSORIGIN enmOrigin);
1018	VMMDECL(VBOXSTRICTRC) PGMPhysReadGCPtr(PVMCPUCC pVCpu, void *pvDst, RTGCPTR GCPtrSrc, size_t cb, PGMACCESSORIGIN enmOrigin);
1019	VMMDECL(VBOXSTRICTRC) PGMPhysWriteGCPtr(PVMCPUCC pVCpu, RTGCPTR GCPtrDst, const void *pvSrc, size_t cb, PGMACCESSORIGIN enmOrigin);
1020
1021	VMMDECL(int) PGMPhysSimpleReadGCPhys(PVMCC pVM, void *pvDst, RTGCPHYS GCPhysSrc, size_t cb);
1022	VMMDECL(int) PGMPhysSimpleWriteGCPhys(PVMCC pVM, RTGCPHYS GCPhysDst, const void *pvSrc, size_t cb);
1023	VMMDECL(int) PGMPhysSimpleReadGCPtr(PVMCPUCC pVCpu, void *pvDst, RTGCPTR GCPtrSrc, size_t cb);
1024	VMMDECL(int) PGMPhysSimpleWriteGCPtr(PVMCPUCC pVCpu, RTGCPTR GCPtrDst, const void *pvSrc, size_t cb);
1025	VMMDECL(int) PGMPhysSimpleDirtyWriteGCPtr(PVMCPUCC pVCpu, RTGCPTR GCPtrDst, const void *pvSrc, size_t cb);
1026
1027	VMM_INT_DECL(int) PGMPhysIemGCPhys2Ptr(PVMCC pVM, PVMCPUCC pVCpu, RTGCPHYS GCPhys, bool fWritable, bool fByPassHandlers, void **ppv, PPGMPAGEMAPLOCK pLock);
1028	VMM_INT_DECL(int) PGMPhysIemQueryAccess(PVMCC pVM, RTGCPHYS GCPhys, bool fWritable, bool fByPassHandlers);
1029	VMM_INT_DECL(int) PGMPhysIemGCPhys2PtrNoLock(PVMCC pVM, PVMCPUCC pVCpu, RTGCPHYS GCPhys, uint64_t const volatile *puTlbPhysRev,
1030	R3R0PTRTYPE(uint8_t ) ppb, uint64_t *pfTlb);
1031	/** @name Flags returned by PGMPhysIemGCPhys2PtrNoLock
1032	* @{ */
1033	#define PGMIEMGCPHYS2PTR_F_NO_WRITE RT_BIT_32(3) /*< Not writable (IEMTLBE_F_PG_NO_WRITE). /
1034	#define PGMIEMGCPHYS2PTR_F_NO_READ RT_BIT_32(4) /*< Not readable (IEMTLBE_F_PG_NO_READ). /
1035	#define PGMIEMGCPHYS2PTR_F_NO_MAPPINGR3 RT_BIT_32(8) /*< No ring-3 mapping (IEMTLBE_F_NO_MAPPINGR3). /
1036	#define PGMIEMGCPHYS2PTR_F_UNASSIGNED RT_BIT_32(9) /*< Unassgined memory (IEMTLBE_F_PG_UNASSIGNED). /
1037	#define PGMIEMGCPHYS2PTR_F_CODE_PAGE RT_BIT_32(10) /*< Write monitored IEM code page (IEMTLBE_F_PG_CODE_PAGE). /
1038	/** @} */
1039
1040	/** Information returned by PGMPhysNemQueryPageInfo. */
1041	typedef struct PGMPHYSNEMPAGEINFO
1042	{
1043	/** The host physical address of the page, NIL_HCPHYS if invalid page. */
1044	RTHCPHYS HCPhys;
1045	/** The NEM access mode for the page, NEM_PAGE_PROT_XXX */
1046	uint32_t fNemProt : 8;
1047	/** The NEM state associated with the PAGE. */
1048	uint32_t u2NemState : 2;
1049	/** The NEM state associated with the PAGE before pgmPhysPageMakeWritable was called. */
1050	uint32_t u2OldNemState : 2;
1051	/** Set if the page has handler. */
1052	uint32_t fHasHandlers : 1;
1053	/** Set if is the zero page backing it. */
1054	uint32_t fZeroPage : 1;
1055	/** Set if the page has handler. */
1056	PGMPAGETYPE enmType;
1057	} PGMPHYSNEMPAGEINFO;
1058	/** Pointer to page information for NEM. */
1059	typedef PGMPHYSNEMPAGEINFO *PPGMPHYSNEMPAGEINFO;
1060	/**
1061	* Callback for checking that the page is in sync while under the PGM lock.
1062	*
1063	* NEM passes this callback to PGMPhysNemQueryPageInfo to check that the page is
1064	* in-sync between PGM and the native hypervisor API in an atomic fashion.
1065	*
1066	* @returns VBox status code.
1067	* @param pVM The cross context VM structure.
1068	* @param pVCpu The cross context per virtual CPU structure. Optional,
1069	* see PGMPhysNemQueryPageInfo.
1070	* @param GCPhys The guest physical address (not A20 masked).
1071	* @param pInfo The page info structure. This function updates the
1072	* u2NemState memory and the caller will update the PGMPAGE
1073	* copy accordingly.
1074	* @param pvUser Callback user argument.
1075	*/
1076	typedef DECLCALLBACKTYPE(int, FNPGMPHYSNEMCHECKPAGE,(PVMCC pVM, PVMCPUCC pVCpu, RTGCPHYS GCPhys, PPGMPHYSNEMPAGEINFO pInfo, void *pvUser));
1077	/** Pointer to a FNPGMPHYSNEMCHECKPAGE function. */
1078	typedef FNPGMPHYSNEMCHECKPAGE *PFNPGMPHYSNEMCHECKPAGE;
1079
1080	VMM_INT_DECL(int) PGMPhysNemPageInfoChecker(PVMCC pVM, PVMCPUCC pVCpu, RTGCPHYS GCPhys, bool fMakeWritable,
1081	PPGMPHYSNEMPAGEINFO pInfo, PFNPGMPHYSNEMCHECKPAGE pfnChecker, void *pvUser);
1082
1083	/**
1084	* Callback for use with PGMPhysNemEnumPagesByState.
1085	* @returns VBox status code.
1086	* Failure status will stop enumeration immediately and return.
1087	* @param pVM The cross context VM structure.
1088	* @param pVCpu The cross context per virtual CPU structure. Optional,
1089	* see PGMPhysNemEnumPagesByState.
1090	* @param GCPhys The guest physical address (not A20 masked).
1091	* @param pu2NemState Pointer to variable with the NEM state. This can be
1092	* update.
1093	* @param pvUser The user argument.
1094	*/
1095	typedef DECLCALLBACKTYPE(int, FNPGMPHYSNEMENUMCALLBACK,(PVMCC pVM, PVMCPUCC pVCpu, RTGCPHYS GCPhys,
1096	uint8_t pu2NemState, void pvUser));
1097	/** Pointer to a FNPGMPHYSNEMENUMCALLBACK function. */
1098	typedef FNPGMPHYSNEMENUMCALLBACK *PFNPGMPHYSNEMENUMCALLBACK;
1099	VMM_INT_DECL(int) PGMPhysNemEnumPagesByState(PVMCC pVM, PVMCPUCC VCpu, uint8_t uMinState,
1100	PFNPGMPHYSNEMENUMCALLBACK pfnCallback, void *pvUser);
1101
1102
1103	#ifdef VBOX_STRICT
1104	VMMDECL(unsigned) PGMAssertHandlerAndFlagsInSync(PVMCC pVM);
1105	VMMDECL(unsigned) PGMAssertNoMappingConflicts(PVM pVM);
1106	VMMDECL(unsigned) PGMAssertCR3(PVMCC pVM, PVMCPUCC pVCpu, uint64_t cr3, uint64_t cr4);
1107	#endif /* VBOX_STRICT */
1108
1109	VMMDECL(int) PGMSetLargePageUsage(PVMCC pVM, bool fUseLargePages);
1110
1111	/**
1112	* Query large page usage state
1113	*
1114	* @returns 0 - disabled, 1 - enabled
1115	* @param pVM The cross context VM structure.
1116	*/
1117	#define PGMIsUsingLargePages(pVM) ((pVM)->pgm.s.fUseLargePages)
1118
1119
1120	/** @defgroup grp_pgm_r0 The PGM Host Context Ring-0 API
1121	* @{
1122	*/
1123	#ifdef IN_RING0
1124	VMMR0_INT_DECL(int) PGMR0InitPerVMData(PGVM pGVM, RTR0MEMOBJ hMemObj);
1125	VMMR0_INT_DECL(int) PGMR0InitVM(PGVM pGVM);
1126	VMMR0_INT_DECL(void) PGMR0DoneInitVM(PGVM pGVM);
1127	VMMR0_INT_DECL(void) PGMR0CleanupVM(PGVM pGVM);
1128	VMMR0_INT_DECL(int) PGMR0PhysAllocateHandyPages(PGVM pGVM, VMCPUID idCpu);
1129	VMMR0_INT_DECL(int) PGMR0PhysFlushHandyPages(PGVM pGVM, VMCPUID idCpu);
1130	VMMR0_INT_DECL(int) PGMR0PhysAllocateLargePage(PGVM pGVM, VMCPUID idCpu, RTGCPHYS GCPhys);
1131	VMMR0_INT_DECL(int) PGMR0PhysMMIO2MapKernel(PGVM pGVM, PPDMDEVINS pDevIns, PGMMMIO2HANDLE hMmio2,
1132	size_t offSub, size_t cbSub, void **ppvMapping);
1133	VMMR0_INT_DECL(int) PGMR0PhysSetupIoMmu(PGVM pGVM);
1134	VMMR0_INT_DECL(int) PGMR0PhysHandlerInitReqHandler(PGVM pGVM, uint32_t cEntries);
1135
1136	VMMR0_INT_DECL(int) PGMR0HandlerPhysicalTypeSetUpContext(PGVM pGVM, PGMPHYSHANDLERKIND enmKind, uint32_t fFlags,
1137	PFNPGMPHYSHANDLER pfnHandler, PFNPGMRZPHYSPFHANDLER pfnPfHandler,
1138	const char *pszDesc, PGMPHYSHANDLERTYPE hType);
1139
1140	VMMR0DECL(int) PGMR0SharedModuleCheck(PVMCC pVM, PGVM pGVM, VMCPUID idCpu, PGMMSHAREDMODULE pModule,
1141	PCRTGCPTR64 paRegionsGCPtrs);
1142	VMMR0DECL(int) PGMR0Trap0eHandlerNestedPaging(PGVM pGVM, PGVMCPU pGVCpu, PGMMODE enmShwPagingMode, RTGCUINT uErr,
1143	PCPUMCTX pCtx, RTGCPHYS pvFault);
1144	VMMR0DECL(VBOXSTRICTRC) PGMR0Trap0eHandlerNPMisconfig(PGVM pGVM, PGVMCPU pGVCpu, PGMMODE enmShwPagingMode,
1145	PCPUMCTX pCtx, RTGCPHYS GCPhysFault, uint32_t uErr);
1146	VMMR0_INT_DECL(int) PGMR0PoolGrow(PGVM pGVM, VMCPUID idCpu);
1147
1148	# ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
1149	VMMR0DECL(VBOXSTRICTRC) PGMR0NestedTrap0eHandlerNestedPaging(PGVMCPU pGVCpu, PGMMODE enmShwPagingMode, RTGCUINT uErr,
1150	PCPUMCTX pCtx, RTGCPHYS GCPhysNestedFault,
1151	bool fIsLinearAddrValid, RTGCPTR GCPtrNestedFault, PPGMPTWALK pWalk);
1152	# endif
1153	#endif /* IN_RING0 */
1154
1155	/**
1156	* Request buffer for PGMR0PhysAllocateRamRangeReq / VMMR0_DO_PGM_PHYS_ALLOCATE_RAM_RANGE
1157	*/
1158	typedef struct PGMPHYSALLOCATERAMRANGEREQ
1159	{
1160	/** The header. */
1161	SUPVMMR0REQHDR Hdr;
1162	/** Input: the GUEST_PAGE_SIZE value (for validation). */
1163	uint32_t cbGuestPage;
1164	/** Input: Number of guest pages in the range. */
1165	uint32_t cGuestPages;
1166	/** Input: The RAM range flags (PGM_RAM_RANGE_FLAGS_XXX). */
1167	uint32_t fFlags;
1168	/** Output: The range identifier. */
1169	uint32_t idNewRange;
1170	} PGMPHYSALLOCATERAMRANGEREQ;
1171	/** Pointer to a PGMR0PhysAllocateRamRangeReq / VMMR0_DO_PGM_PHYS_ALLOCATE_RAM_RANGE request buffer. */
1172	typedef PGMPHYSALLOCATERAMRANGEREQ *PPGMPHYSALLOCATERAMRANGEREQ;
1173
1174	VMMR0_INT_DECL(int) PGMR0PhysAllocateRamRangeReq(PGVM pGVM, PPGMPHYSALLOCATERAMRANGEREQ pReq);
1175
1176
1177	/**
1178	* Request buffer for PGMR0PhysMmio2RegisterReq / VMMR0_DO_PGM_PHYS_MMIO2_REGISTER
1179	*/
1180	typedef struct PGMPHYSMMIO2REGISTERREQ
1181	{
1182	/** The header. */
1183	SUPVMMR0REQHDR Hdr;
1184	/** Input: the GUEST_PAGE_SIZE value (for validation). */
1185	uint32_t cbGuestPage;
1186	/** Input: Number of guest pages in the MMIO2 range. */
1187	uint32_t cGuestPages;
1188	/** Input: The MMIO2 ID of the first chunk. */
1189	uint8_t idMmio2;
1190	/** Input: The number of MMIO2 chunks needed. */
1191	uint8_t cChunks;
1192	/** Input: The sub-device number. */
1193	uint8_t iSubDev;
1194	/** Input: The device region number. */
1195	uint8_t iRegion;
1196	/** Input: Flags (PGMPHYS_MMIO2_FLAGS_XXX). */
1197	uint32_t fFlags;
1198	/** Input: The owner device key. */
1199	PPDMDEVINSR3 pDevIns;
1200	} PGMPHYSMMIO2REGISTERREQ;
1201	/** Pointer to a PGMR0PhysAllocateRamRangeReq / VMMR0_DO_PGM_PHYS_MMIO2_REGISTER request buffer. */
1202	typedef PGMPHYSMMIO2REGISTERREQ *PPGMPHYSMMIO2REGISTERREQ;
1203
1204	VMMR0_INT_DECL(int) PGMR0PhysMmio2RegisterReq(PGVM pGVM, PPGMPHYSMMIO2REGISTERREQ pReq);
1205
1206
1207	/*
1208	* Request buffer for PGMR0PhysMmio2DeregisterReq / VMMR0_DO_PGM_PHYS_MMIO2_DEREGISTER
1209	*/
1210	typedef struct PGMPHYSMMIO2DEREGISTERREQ
1211	{
1212	/** The header. */
1213	SUPVMMR0REQHDR Hdr;
1214	/** Input: The MMIO2 ID of the first chunk. */
1215	uint8_t idMmio2;
1216	/** Input: The number of MMIO2 chunks to free. */
1217	uint8_t cChunks;
1218	/** Input: Reserved and must be zero. */
1219	uint8_t abReserved[6];
1220	/** Input: The owner device key. */
1221	PPDMDEVINSR3 pDevIns;
1222	} PGMPHYSMMIO2DEREGISTERREQ;
1223	/** Pointer to a PGMR0PhysMmio2DeregisterReq / VMMR0_DO_PGM_PHYS_MMIO2_DEREGISTER request buffer. */
1224	typedef PGMPHYSMMIO2DEREGISTERREQ *PPGMPHYSMMIO2DEREGISTERREQ;
1225
1226	VMMR0_INT_DECL(int) PGMR0PhysMmio2DeregisterReq(PGVM pGVM, PPGMPHYSMMIO2DEREGISTERREQ pReq);
1227
1228	/*
1229	* Request buffer for PGMR0PhysRomAllocateRangeReq / VMMR0_DO_PGM_PHYS_ROM_ALLOCATE_RANGE
1230	*/
1231	typedef struct PGMPHYSROMALLOCATERANGEREQ
1232	{
1233	/** The header. */
1234	SUPVMMR0REQHDR Hdr;
1235	/** Input: the GUEST_PAGE_SIZE value (for validation). */
1236	uint32_t cbGuestPage;
1237	/** Input: Number of guest pages in the range. */
1238	uint32_t cGuestPages;
1239	/** Input: The ROM range ID (index) to be allocated. */
1240	uint32_t idRomRange;
1241	/** Input: The ROM range flags (PGMPHYS_ROM_FLAGS_XXX). */
1242	uint32_t fFlags;
1243	} PGMPHYSROMALLOCATERANGEREQ;
1244	/* Pointer to a PGMR0PhysRomAllocateRangeReq / VMMR0_DO_PGM_PHYS_ROM_ALLOCATE_RANGE request buffer. */
1245	typedef PGMPHYSROMALLOCATERANGEREQ *PPGMPHYSROMALLOCATERANGEREQ;
1246
1247	VMMR0_INT_DECL(int) PGMR0PhysRomAllocateRangeReq(PGVM pGVM, PPGMPHYSROMALLOCATERANGEREQ pReq);
1248
1249
1250	/** @} */
1251
1252
1253
1254	/** @defgroup grp_pgm_r3 The PGM Host Context Ring-3 API
1255	* @{
1256	*/
1257	#ifdef IN_RING3
1258	VMMR3_INT_DECL(void) PGMR3EnableNemMode(PVM pVM);
1259	VMMR3_INT_DECL(bool) PGMR3IsNemModeEnabled(PVM pVM);
1260	VMMR3DECL(int) PGMR3Init(PVM pVM);
1261	VMMR3DECL(int) PGMR3InitFinalize(PVM pVM);
1262	VMMR3_INT_DECL(int) PGMR3InitCompleted(PVM pVM, VMINITCOMPLETED enmWhat);
1263	VMMR3DECL(void) PGMR3Relocate(PVM pVM, RTGCINTPTR offDelta);
1264	VMMR3DECL(void) PGMR3ResetCpu(PVM pVM, PVMCPU pVCpu);
1265	VMMR3_INT_DECL(void) PGMR3Reset(PVM pVM);
1266	VMMR3_INT_DECL(void) PGMR3ResetNoMorePhysWritesFlag(PVM pVM);
1267	VMMR3_INT_DECL(void) PGMR3MemSetup(PVM pVM, bool fReset);
1268	VMMR3DECL(int) PGMR3Term(PVM pVM);
1269
1270	VMMR3DECL(int) PGMR3PhysRegisterRam(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, const char *pszDesc);
1271	VMMR3DECL(int) PGMR3PhysChangeMemBalloon(PVM pVM, bool fInflate, unsigned cPages, RTGCPHYS *paPhysPage);
1272	VMMR3DECL(int) PGMR3PhysWriteProtectRAM(PVM pVM);
1273	VMMR3DECL(uint32_t) PGMR3PhysGetRamRangeCount(PVM pVM);
1274	VMMR3DECL(int) PGMR3PhysGetRange(PVM pVM, uint32_t iRange, PRTGCPHYS pGCPhysStart, PRTGCPHYS pGCPhysLast,
1275	const char *ppszDesc, bool pfIsMmio);
1276	VMMR3_INT_DECL(int) PGMR3PhysGetRamBootZeroedRanges(PVM pVM, PPGMPHYSRANGES pRanges, uint32_t cMaxRanges);
1277	VMMR3DECL(int) PGMR3QueryMemoryStats(PUVM pUVM, uint64_t pcbTotalMem, uint64_t pcbPrivateMem, uint64_t pcbSharedMem, uint64_t pcbZeroMem);
1278	VMMR3DECL(int) PGMR3QueryGlobalMemoryStats(PUVM pUVM, uint64_t pcbAllocMem, uint64_t pcbFreeMem, uint64_t pcbBallonedMem, uint64_t pcbSharedMem);
1279
1280	VMMR3_INT_DECL(int) PGMR3PhysMmioRegister(PVM pVM, PVMCPU pVCpu, RTGCPHYS cb, const char pszDesc, uint16_t pidRamRange);
1281	VMMR3_INT_DECL(int) PGMR3PhysMmioMap(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, RTGCPHYS cb, uint16_t idRamRange,
1282	PGMPHYSHANDLERTYPE hType, uint64_t uUser);
1283	VMMR3_INT_DECL(int) PGMR3PhysMmioUnmap(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, RTGCPHYS cb, uint16_t idRamRange);
1284	#endif /* IN_RING3 */
1285
1286	/** @name PGMPHYS_MMIO2_FLAGS_XXX - MMIO2 registration flags.
1287	* @see PGMR3PhysMmio2Register, PDMDevHlpMmio2Create
1288	* @{ */
1289	/** Track dirty pages.
1290	* @see PGMR3PhysMmio2QueryAndResetDirtyBitmap(), PGMR3PhysMmio2ControlDirtyPageTracking(). */
1291	#define PGMPHYS_MMIO2_FLAGS_TRACK_DIRTY_PAGES RT_BIT_32(0)
1292	/** Valid flags. */
1293	#define PGMPHYS_MMIO2_FLAGS_VALID_MASK UINT32_C(0x00000001)
1294	/** @} */
1295
1296	#ifdef IN_RING3
1297	VMMR3_INT_DECL(int) PGMR3PhysMmio2Register(PVM pVM, PPDMDEVINS pDevIns, uint32_t iSubDev, uint32_t iRegion, RTGCPHYS cb,
1298	uint32_t fFlags, const char pszDesc, void ppv, PGMMMIO2HANDLE phRegion);
1299	VMMR3_INT_DECL(int) PGMR3PhysMmio2Deregister(PVM pVM, PPDMDEVINS pDevIns, PGMMMIO2HANDLE hMmio2);
1300	VMMR3_INT_DECL(int) PGMR3PhysMmio2Map(PVM pVM, PPDMDEVINS pDevIns, PGMMMIO2HANDLE hMmio2, RTGCPHYS GCPhys);
1301	VMMR3_INT_DECL(int) PGMR3PhysMmio2Unmap(PVM pVM, PPDMDEVINS pDevIns, PGMMMIO2HANDLE hMmio2, RTGCPHYS GCPhys);
1302	VMMR3_INT_DECL(int) PGMR3PhysMmio2Reduce(PVM pVM, PPDMDEVINS pDevIns, PGMMMIO2HANDLE hMmio2, RTGCPHYS cbRegion);
1303	VMMR3_INT_DECL(int) PGMR3PhysMmio2ValidateHandle(PVM pVM, PPDMDEVINS pDevIns, PGMMMIO2HANDLE hMmio2);
1304	VMMR3_INT_DECL(RTGCPHYS) PGMR3PhysMmio2GetMappingAddress(PVM pVM, PPDMDEVINS pDevIns, PGMMMIO2HANDLE hMmio2);
1305	VMMR3_INT_DECL(int) PGMR3PhysMmio2ChangeRegionNo(PVM pVM, PPDMDEVINS pDevIns, PGMMMIO2HANDLE hMmio2, uint32_t iNewRegion);
1306	VMMR3_INT_DECL(int) PGMR3PhysMmio2QueryAndResetDirtyBitmap(PVM pVM, PPDMDEVINS pDevIns, PGMMMIO2HANDLE hMmio2,
1307	void *pvBitmap, size_t cbBitmap);
1308	VMMR3_INT_DECL(int) PGMR3PhysMmio2ControlDirtyPageTracking(PVM pVM, PPDMDEVINS pDevIns, PGMMMIO2HANDLE hMmio2, bool fEnabled);
1309	#endif /* IN_RING3 */
1310
1311	/** @name PGMPHYS_ROM_FLAGS_XXX - ROM registration flags.
1312	* @see PGMR3PhysRegisterRom, PDMDevHlpROMRegister
1313	* @{ */
1314	/** Inidicates that ROM shadowing should be enabled. */
1315	#define PGMPHYS_ROM_FLAGS_SHADOWED UINT8_C(0x01)
1316	/** Indicates that what pvBinary points to won't go away
1317	* and can be used for strictness checks. */
1318	#define PGMPHYS_ROM_FLAGS_PERMANENT_BINARY UINT8_C(0x02)
1319	/** Indicates that the ROM is allowed to be missing from saved state.
1320	* @note This is a hack for EFI, see @bugref{6940} */
1321	#define PGMPHYS_ROM_FLAGS_MAYBE_MISSING_FROM_STATE UINT8_C(0x04)
1322	/** Valid flags. */
1323	#define PGMPHYS_ROM_FLAGS_VALID_MASK UINT8_C(0x07)
1324	/** @} */
1325
1326	#ifdef IN_RING3
1327	VMMR3DECL(int) PGMR3PhysRomRegister(PVM pVM, PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTGCPHYS cb,
1328	const void pvBinary, uint32_t cbBinary, uint8_t fFlags, const char pszDesc);
1329	VMMR3DECL(int) PGMR3PhysRomProtect(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, PGMROMPROT enmProt);
1330	VMMDECL(void) PGMR3PhysSetA20(PVMCPU pVCpu, bool fEnable);
1331
1332	VMMR3_INT_DECL(int) PGMR3HandlerPhysicalTypeRegister(PVM pVM, PGMPHYSHANDLERKIND enmKind, uint32_t fFlags,
1333	PFNPGMPHYSHANDLER pfnHandlerR3, const char *pszDesc,
1334	PPGMPHYSHANDLERTYPE phType);
1335
1336	VMMR3_INT_DECL(int) PGMR3PoolGrow(PVM pVM, PVMCPU pVCpu);
1337
1338	VMMR3DECL(int) PGMR3PhysTlbGCPhys2Ptr(PVM pVM, RTGCPHYS GCPhys, bool fWritable, void **ppv);
1339	VMMR3DECL(uint8_t) PGMR3PhysReadU8(PVM pVM, RTGCPHYS GCPhys, PGMACCESSORIGIN enmOrigin);
1340	VMMR3DECL(uint16_t) PGMR3PhysReadU16(PVM pVM, RTGCPHYS GCPhys, PGMACCESSORIGIN enmOrigin);
1341	VMMR3DECL(uint32_t) PGMR3PhysReadU32(PVM pVM, RTGCPHYS GCPhys, PGMACCESSORIGIN enmOrigin);
1342	VMMR3DECL(uint64_t) PGMR3PhysReadU64(PVM pVM, RTGCPHYS GCPhys, PGMACCESSORIGIN enmOrigin);
1343	VMMR3DECL(void) PGMR3PhysWriteU8(PVM pVM, RTGCPHYS GCPhys, uint8_t Value, PGMACCESSORIGIN enmOrigin);
1344	VMMR3DECL(void) PGMR3PhysWriteU16(PVM pVM, RTGCPHYS GCPhys, uint16_t Value, PGMACCESSORIGIN enmOrigin);
1345	VMMR3DECL(void) PGMR3PhysWriteU32(PVM pVM, RTGCPHYS GCPhys, uint32_t Value, PGMACCESSORIGIN enmOrigin);
1346	VMMR3DECL(void) PGMR3PhysWriteU64(PVM pVM, RTGCPHYS GCPhys, uint64_t Value, PGMACCESSORIGIN enmOrigin);
1347	VMMR3DECL(int) PGMR3PhysReadExternal(PVM pVM, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead, PGMACCESSORIGIN enmOrigin);
1348	VMMR3DECL(int) PGMR3PhysWriteExternal(PVM pVM, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite, PGMACCESSORIGIN enmOrigin);
1349	VMMR3DECL(int) PGMR3PhysGCPhys2CCPtrExternal(PVM pVM, RTGCPHYS GCPhys, void **ppv, PPGMPAGEMAPLOCK pLock);
1350	VMMR3DECL(int) PGMR3PhysGCPhys2CCPtrReadOnlyExternal(PVM pVM, RTGCPHYS GCPhys, void const **ppv, PPGMPAGEMAPLOCK pLock);
1351	VMMR3DECL(int) PGMR3PhysBulkGCPhys2CCPtrExternal(PVM pVM, uint32_t cPages, PCRTGCPHYS paGCPhysPages,
1352	void **papvPages, PPGMPAGEMAPLOCK paLocks);
1353	VMMR3DECL(int) PGMR3PhysBulkGCPhys2CCPtrReadOnlyExternal(PVM pVM, uint32_t cPages, PCRTGCPHYS paGCPhysPages,
1354	void const **papvPages, PPGMPAGEMAPLOCK paLocks);
1355	VMMR3DECL(int) PGMR3PhysAllocateHandyPages(PVM pVM);
1356
1357	VMMR3DECL(int) PGMR3CheckIntegrity(PVM pVM);
1358
1359	VMMR3DECL(int) PGMR3DbgR3Ptr2GCPhys(PUVM pUVM, RTR3PTR R3Ptr, PRTGCPHYS pGCPhys);
1360	VMMR3DECL(int) PGMR3DbgR3Ptr2HCPhys(PUVM pUVM, RTR3PTR R3Ptr, PRTHCPHYS pHCPhys);
1361	VMMR3DECL(int) PGMR3DbgHCPhys2GCPhys(PUVM pUVM, RTHCPHYS HCPhys, PRTGCPHYS pGCPhys);
1362	VMMR3_INT_DECL(int) PGMR3DbgReadGCPhys(PVM pVM, void pvDst, RTGCPHYS GCPhysSrc, size_t cb, uint32_t fFlags, size_t pcbRead);
1363	VMMR3_INT_DECL(int) PGMR3DbgWriteGCPhys(PVM pVM, RTGCPHYS GCPhysDst, const void pvSrc, size_t cb, uint32_t fFlags, size_t pcbWritten);
1364	VMMR3_INT_DECL(int) PGMR3DbgReadGCPtr(PVM pVM, void pvDst, RTGCPTR GCPtrSrc, size_t cb, uint32_t fFlags, size_t pcbRead);
1365	VMMR3_INT_DECL(int) PGMR3DbgWriteGCPtr(PVM pVM, RTGCPTR GCPtrDst, void const pvSrc, size_t cb, uint32_t fFlags, size_t pcbWritten);
1366	VMMR3_INT_DECL(int) PGMR3DbgScanPhysical(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cbRange, RTGCPHYS GCPhysAlign, const uint8_t *pabNeedle, size_t cbNeedle, PRTGCPHYS pGCPhysHit);
1367	VMMR3_INT_DECL(int) PGMR3DbgScanVirtual(PVM pVM, PVMCPU pVCpu, RTGCPTR GCPtr, RTGCPTR cbRange, RTGCPTR GCPtrAlign, const uint8_t *pabNeedle, size_t cbNeedle, PRTGCUINTPTR pGCPhysHit);
1368	VMMR3_INT_DECL(int) PGMR3DumpHierarchyShw(PVM pVM, uint64_t cr3, uint32_t fFlags, uint64_t u64FirstAddr, uint64_t u64LastAddr, uint32_t cMaxDepth, PCDBGFINFOHLP pHlp);
1369	VMMR3_INT_DECL(int) PGMR3DumpHierarchyGst(PVM pVM, uint64_t cr3, uint32_t fFlags, RTGCPTR FirstAddr, RTGCPTR LastAddr, uint32_t cMaxDepth, PCDBGFINFOHLP pHlp);
1370	#endif /* IN_RING3 */
1371
1372	/** @name Page sharing
1373	* @{ */
1374	#ifdef IN_RING3
1375	VMMR3DECL(int) PGMR3SharedModuleRegister(PVM pVM, VBOXOSFAMILY enmGuestOS, char pszModuleName, char pszVersion,
1376	RTGCPTR GCBaseAddr, uint32_t cbModule,
1377	uint32_t cRegions, VMMDEVSHAREDREGIONDESC const *paRegions);
1378	VMMR3DECL(int) PGMR3SharedModuleUnregister(PVM pVM, char pszModuleName, char pszVersion,
1379	RTGCPTR GCBaseAddr, uint32_t cbModule);
1380	VMMR3DECL(int) PGMR3SharedModuleCheckAll(PVM pVM);
1381	VMMR3DECL(int) PGMR3SharedModuleGetPageState(PVM pVM, RTGCPTR GCPtrPage, bool pfShared, uint64_t pfPageFlags);
1382	#endif /* IN_RING3 */
1383	/** @} */
1384
1385	/** @} */
1386
1387	RT_C_DECLS_END
1388
1389	/** @} */
1390	#endif /* !VBOX_INCLUDED_vmm_pgm_h */
1391

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source: vbox/trunk/include/VBox/vmm/pgm.h@ 105745

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