VirtualBox

source: vbox/trunk/include/VBox/vmm/pgm.h@ 36891

Last change on this file since 36891 was 36891, checked in by vboxsync, 14 years ago

PGM: Put a TLB in front of the RAM ranges to speed up lookup (disabled).

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1/** @file
2 * PGM - Page Monitor / Monitor.
3 */
4
5/*
6 * Copyright (C) 2006-2010 Oracle Corporation
7 *
8 * This file is part of VirtualBox Open Source Edition (OSE), as
9 * available from http://www.virtualbox.org. This file is free software;
10 * you can redistribute it and/or modify it under the terms of the GNU
11 * General Public License (GPL) as published by the Free Software
12 * Foundation, in version 2 as it comes in the "COPYING" file of the
13 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15 *
16 * The contents of this file may alternatively be used under the terms
17 * of the Common Development and Distribution License Version 1.0
18 * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19 * VirtualBox OSE distribution, in which case the provisions of the
20 * CDDL are applicable instead of those of the GPL.
21 *
22 * You may elect to license modified versions of this file under the
23 * terms and conditions of either the GPL or the CDDL or both.
24 */
25
26#ifndef ___VBox_vmm_pgm_h
27#define ___VBox_vmm_pgm_h
28
29#include <VBox/types.h>
30#include <VBox/sup.h>
31#include <VBox/vmm/vmapi.h>
32#include <VBox/vmm/gmm.h> /* for PGMMREGISTERSHAREDMODULEREQ */
33#include <VBox/x86.h>
34#include <VBox/VMMDev.h> /* for VMMDEVSHAREDREGIONDESC */
35#include <VBox/param.h>
36
37RT_C_DECLS_BEGIN
38
39/** @defgroup grp_pgm The Page Monitor / Manager API
40 * @{
41 */
42
43/**
44 * FNPGMRELOCATE callback mode.
45 */
46typedef enum PGMRELOCATECALL
47{
48 /** The callback is for checking if the suggested address is suitable. */
49 PGMRELOCATECALL_SUGGEST = 1,
50 /** The callback is for executing the relocation. */
51 PGMRELOCATECALL_RELOCATE
52} PGMRELOCATECALL;
53
54
55/**
56 * Callback function which will be called when PGM is trying to find
57 * a new location for the mapping.
58 *
59 * The callback is called in two modes, 1) the check mode and 2) the relocate mode.
60 * In 1) the callback should say if it objects to a suggested new location. If it
61 * accepts the new location, it is called again for doing it's relocation.
62 *
63 *
64 * @returns true if the location is ok.
65 * @returns false if another location should be found.
66 * @param GCPtrOld The old virtual address.
67 * @param GCPtrNew The new virtual address.
68 * @param enmMode Used to indicate the callback mode.
69 * @param pvUser User argument.
70 * @remark The return value is no a failure indicator, it's an acceptance
71 * indicator. Relocation can not fail!
72 */
73typedef DECLCALLBACK(bool) FNPGMRELOCATE(PVM pVM, RTGCPTR GCPtrOld, RTGCPTR GCPtrNew, PGMRELOCATECALL enmMode, void *pvUser);
74/** Pointer to a relocation callback function. */
75typedef FNPGMRELOCATE *PFNPGMRELOCATE;
76
77
78/**
79 * Physical page access handler type.
80 */
81typedef enum PGMPHYSHANDLERTYPE
82{
83 /** MMIO range. Pages are not present, all access is done in interpreter or recompiler. */
84 PGMPHYSHANDLERTYPE_MMIO = 1,
85 /** Handler all write access to a physical page range. */
86 PGMPHYSHANDLERTYPE_PHYSICAL_WRITE,
87 /** Handler all access to a physical page range. */
88 PGMPHYSHANDLERTYPE_PHYSICAL_ALL
89
90} PGMPHYSHANDLERTYPE;
91
92/**
93 * \#PF Handler callback for physical access handler ranges in RC.
94 *
95 * @returns VBox status code (appropriate for RC return).
96 * @param pVM VM Handle.
97 * @param uErrorCode CPU Error code.
98 * @param pRegFrame Trap register frame.
99 * NULL on DMA and other non CPU access.
100 * @param pvFault The fault address (cr2).
101 * @param GCPhysFault The GC physical address corresponding to pvFault.
102 * @param pvUser User argument.
103 */
104typedef DECLCALLBACK(int) FNPGMRCPHYSHANDLER(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser);
105/** Pointer to PGM access callback. */
106typedef FNPGMRCPHYSHANDLER *PFNPGMRCPHYSHANDLER;
107
108/**
109 * \#PF Handler callback for physical access handler ranges in R0.
110 *
111 * @returns VBox status code (appropriate for R0 return).
112 * @param pVM VM Handle.
113 * @param uErrorCode CPU Error code.
114 * @param pRegFrame Trap register frame.
115 * NULL on DMA and other non CPU access.
116 * @param pvFault The fault address (cr2).
117 * @param GCPhysFault The GC physical address corresponding to pvFault.
118 * @param pvUser User argument.
119 */
120typedef DECLCALLBACK(int) FNPGMR0PHYSHANDLER(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser);
121/** Pointer to PGM access callback. */
122typedef FNPGMR0PHYSHANDLER *PFNPGMR0PHYSHANDLER;
123
124/**
125 * Guest Access type
126 */
127typedef enum PGMACCESSTYPE
128{
129 /** Read access. */
130 PGMACCESSTYPE_READ = 1,
131 /** Write access. */
132 PGMACCESSTYPE_WRITE
133} PGMACCESSTYPE;
134
135/**
136 * \#PF Handler callback for physical access handler ranges (MMIO among others) in HC.
137 *
138 * The handler can not raise any faults, it's mainly for monitoring write access
139 * to certain pages.
140 *
141 * @returns VINF_SUCCESS if the handler have carried out the operation.
142 * @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
143 * @param pVM VM Handle.
144 * @param GCPhys The physical address the guest is writing to.
145 * @param pvPhys The HC mapping of that address.
146 * @param pvBuf What the guest is reading/writing.
147 * @param cbBuf How much it's reading/writing.
148 * @param enmAccessType The access type.
149 * @param pvUser User argument.
150 */
151typedef DECLCALLBACK(int) FNPGMR3PHYSHANDLER(PVM pVM, RTGCPHYS GCPhys, void *pvPhys, void *pvBuf, size_t cbBuf, PGMACCESSTYPE enmAccessType, void *pvUser);
152/** Pointer to PGM access callback. */
153typedef FNPGMR3PHYSHANDLER *PFNPGMR3PHYSHANDLER;
154
155
156/**
157 * Virtual access handler type.
158 */
159typedef enum PGMVIRTHANDLERTYPE
160{
161 /** Write access handled. */
162 PGMVIRTHANDLERTYPE_WRITE = 1,
163 /** All access handled. */
164 PGMVIRTHANDLERTYPE_ALL,
165 /** Hypervisor write access handled.
166 * This is used to catch the guest trying to write to LDT, TSS and any other
167 * system structure which the brain dead intel guys let unprivilegde code find. */
168 PGMVIRTHANDLERTYPE_HYPERVISOR
169} PGMVIRTHANDLERTYPE;
170
171/**
172 * \#PF Handler callback for virtual access handler ranges, RC.
173 *
174 * Important to realize that a physical page in a range can have aliases, and
175 * for ALL and WRITE handlers these will also trigger.
176 *
177 * @returns VBox status code (appropriate for GC return).
178 * @param pVM VM Handle.
179 * @param uErrorCode CPU Error code.
180 * @param pRegFrame Trap register frame.
181 * @param pvFault The fault address (cr2).
182 * @param pvRange The base address of the handled virtual range.
183 * @param offRange The offset of the access into this range.
184 * (If it's a EIP range this is the EIP, if not it's pvFault.)
185 */
186typedef DECLCALLBACK(int) FNPGMRCVIRTHANDLER(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPTR pvRange, uintptr_t offRange);
187/** Pointer to PGM access callback. */
188typedef FNPGMRCVIRTHANDLER *PFNPGMRCVIRTHANDLER;
189
190/**
191 * \#PF Handler callback for virtual access handler ranges, R3.
192 *
193 * Important to realize that a physical page in a range can have aliases, and
194 * for ALL and WRITE handlers these will also trigger.
195 *
196 * @returns VINF_SUCCESS if the handler have carried out the operation.
197 * @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
198 * @param pVM VM Handle.
199 * @param GCPtr The virtual address the guest is writing to. (not correct if it's an alias!)
200 * @param pvPtr The HC mapping of that address.
201 * @param pvBuf What the guest is reading/writing.
202 * @param cbBuf How much it's reading/writing.
203 * @param enmAccessType The access type.
204 * @param pvUser User argument.
205 */
206typedef DECLCALLBACK(int) FNPGMR3VIRTHANDLER(PVM pVM, RTGCPTR GCPtr, void *pvPtr, void *pvBuf, size_t cbBuf, PGMACCESSTYPE enmAccessType, void *pvUser);
207/** Pointer to PGM access callback. */
208typedef FNPGMR3VIRTHANDLER *PFNPGMR3VIRTHANDLER;
209
210
211/**
212 * \#PF Handler callback for invalidation of virtual access handler ranges.
213 *
214 * @param pVM VM Handle.
215 * @param GCPtr The virtual address the guest has changed.
216 */
217typedef DECLCALLBACK(int) FNPGMR3VIRTINVALIDATE(PVM pVM, RTGCPTR GCPtr);
218/** Pointer to PGM invalidation callback. */
219typedef FNPGMR3VIRTINVALIDATE *PFNPGMR3VIRTINVALIDATE;
220
221/**
222 * PGMR3PhysEnumDirtyFTPages callback for syncing dirty physical pages
223 *
224 * @param pVM VM Handle.
225 * @param GCPhys GC physical address
226 * @param pRange HC virtual address of the page(s)
227 * @param cbRange Size of the dirty range in bytes.
228 * @param pvUser User argument.
229 */
230typedef DECLCALLBACK(int) FNPGMENUMDIRTYFTPAGES(PVM pVM, RTGCPHYS GCPhys, uint8_t *pRange, unsigned cbRange, void *pvUser);
231/** Pointer to PGMR3PhysEnumDirtyFTPages callback. */
232typedef FNPGMENUMDIRTYFTPAGES *PFNPGMENUMDIRTYFTPAGES;
233
234/**
235 * Paging mode.
236 */
237typedef enum PGMMODE
238{
239 /** The usual invalid value. */
240 PGMMODE_INVALID = 0,
241 /** Real mode. */
242 PGMMODE_REAL,
243 /** Protected mode, no paging. */
244 PGMMODE_PROTECTED,
245 /** 32-bit paging. */
246 PGMMODE_32_BIT,
247 /** PAE paging. */
248 PGMMODE_PAE,
249 /** PAE paging with NX enabled. */
250 PGMMODE_PAE_NX,
251 /** 64-bit AMD paging (long mode). */
252 PGMMODE_AMD64,
253 /** 64-bit AMD paging (long mode) with NX enabled. */
254 PGMMODE_AMD64_NX,
255 /** Nested paging mode (shadow only; guest physical to host physical). */
256 PGMMODE_NESTED,
257 /** Extended paging (Intel) mode. */
258 PGMMODE_EPT,
259 /** The max number of modes */
260 PGMMODE_MAX,
261 /** 32bit hackishness. */
262 PGMMODE_32BIT_HACK = 0x7fffffff
263} PGMMODE;
264
265/** Macro for checking if the guest is using paging.
266 * @param enmMode PGMMODE_*.
267 * @remark ASSUMES certain order of the PGMMODE_* values.
268 */
269#define PGMMODE_WITH_PAGING(enmMode) ((enmMode) >= PGMMODE_32_BIT)
270
271/** Macro for checking if it's one of the long mode modes.
272 * @param enmMode PGMMODE_*.
273 */
274#define PGMMODE_IS_LONG_MODE(enmMode) ((enmMode) == PGMMODE_AMD64_NX || (enmMode) == PGMMODE_AMD64)
275
276/**
277 * Is the ROM mapped (true) or is the shadow RAM mapped (false).
278 *
279 * @returns boolean.
280 * @param enmProt The PGMROMPROT value, must be valid.
281 */
282#define PGMROMPROT_IS_ROM(enmProt) \
283 ( (enmProt) == PGMROMPROT_READ_ROM_WRITE_IGNORE \
284 || (enmProt) == PGMROMPROT_READ_ROM_WRITE_RAM )
285
286
287
288VMMDECL(bool) PGMIsLocked(PVM pVM);
289VMMDECL(bool) PGMIsLockOwner(PVM pVM);
290
291VMMDECL(int) PGMRegisterStringFormatTypes(void);
292VMMDECL(void) PGMDeregisterStringFormatTypes(void);
293VMMDECL(RTHCPHYS) PGMGetHyperCR3(PVMCPU pVCpu);
294VMMDECL(RTHCPHYS) PGMGetNestedCR3(PVMCPU pVCpu, PGMMODE enmShadowMode);
295VMMDECL(RTHCPHYS) PGMGetInterHCCR3(PVM pVM);
296VMMDECL(RTHCPHYS) PGMGetInterRCCR3(PVM pVM, PVMCPU pVCpu);
297VMMDECL(RTHCPHYS) PGMGetInter32BitCR3(PVM pVM);
298VMMDECL(RTHCPHYS) PGMGetInterPaeCR3(PVM pVM);
299VMMDECL(RTHCPHYS) PGMGetInterAmd64CR3(PVM pVM);
300VMMDECL(int) PGMTrap0eHandler(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault);
301VMMDECL(int) PGMPrefetchPage(PVMCPU pVCpu, RTGCPTR GCPtrPage);
302VMMDECL(int) PGMVerifyAccess(PVMCPU pVCpu, RTGCPTR Addr, uint32_t cbSize, uint32_t fAccess);
303VMMDECL(int) PGMIsValidAccess(PVMCPU pVCpu, RTGCPTR Addr, uint32_t cbSize, uint32_t fAccess);
304VMMDECL(VBOXSTRICTRC) PGMInterpretInstruction(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault);
305VMMDECL(int) PGMMap(PVM pVM, RTGCPTR GCPtr, RTHCPHYS HCPhys, uint32_t cbPages, unsigned fFlags);
306VMMDECL(int) PGMMapGetPage(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys);
307VMMDECL(int) PGMMapSetPage(PVM pVM, RTGCPTR GCPtr, uint64_t cb, uint64_t fFlags);
308VMMDECL(int) PGMMapModifyPage(PVM pVM, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask);
309#ifndef IN_RING0
310VMMDECL(bool) PGMMapHasConflicts(PVM pVM);
311#endif
312#ifdef VBOX_STRICT
313VMMDECL(void) PGMMapCheck(PVM pVM);
314#endif
315VMMDECL(int) PGMShwGetPage(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys);
316VMMDECL(int) PGMShwMakePageReadonly(PVMCPU pVCpu, RTGCPTR GCPtr, uint32_t fFlags);
317VMMDECL(int) PGMShwMakePageWritable(PVMCPU pVCpu, RTGCPTR GCPtr, uint32_t fFlags);
318VMMDECL(int) PGMShwMakePageNotPresent(PVMCPU pVCpu, RTGCPTR GCPtr, uint32_t fFlags);
319/** @name Flags for PGMShwMakePageReadonly, PGMShwMakePageWritable and
320 * PGMShwMakePageNotPresent
321 * @{ */
322/** The call is from an access handler for dealing with the a faulting write
323 * operation. The virtual address is within the same page. */
324#define PGM_MK_PG_IS_WRITE_FAULT RT_BIT(0)
325/** The page is an MMIO2. */
326#define PGM_MK_PG_IS_MMIO2 RT_BIT(1)
327/** @}*/
328VMMDECL(int) PGMGstGetPage(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys);
329VMMDECL(bool) PGMGstIsPagePresent(PVMCPU pVCpu, RTGCPTR GCPtr);
330VMMDECL(int) PGMGstSetPage(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cb, uint64_t fFlags);
331VMMDECL(int) PGMGstModifyPage(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask);
332VMMDECL(int) PGMGstQueryPaePDPtr(PVMCPU pVCpu, unsigned iPdpt, PX86PDPE pPdpe);
333
334VMMDECL(int) PGMInvalidatePage(PVMCPU pVCpu, RTGCPTR GCPtrPage);
335VMMDECL(int) PGMFlushTLB(PVMCPU pVCpu, uint64_t cr3, bool fGlobal);
336VMMDECL(int) PGMSyncCR3(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal);
337VMMDECL(int) PGMUpdateCR3(PVMCPU pVCpu, uint64_t cr3);
338VMMDECL(int) PGMChangeMode(PVMCPU pVCpu, uint64_t cr0, uint64_t cr4, uint64_t efer);
339VMMDECL(PGMMODE) PGMGetGuestMode(PVMCPU pVCpu);
340VMMDECL(PGMMODE) PGMGetShadowMode(PVMCPU pVCpu);
341VMMDECL(PGMMODE) PGMGetHostMode(PVM pVM);
342VMMDECL(const char *) PGMGetModeName(PGMMODE enmMode);
343VMM_INT_DECL(void) PGMNotifyNxeChanged(PVMCPU pVCpu, bool fNxe);
344VMMDECL(bool) PGMHasDirtyPages(PVM pVM);
345VMMDECL(int) PGMHandlerPhysicalRegisterEx(PVM pVM, PGMPHYSHANDLERTYPE enmType, RTGCPHYS GCPhys, RTGCPHYS GCPhysLast,
346 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnHandlerR3, RTR3PTR pvUserR3,
347 R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnHandlerR0, RTR0PTR pvUserR0,
348 RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnHandlerRC, RTRCPTR pvUserRC,
349 R3PTRTYPE(const char *) pszDesc);
350VMMDECL(int) PGMHandlerPhysicalModify(PVM pVM, RTGCPHYS GCPhysCurrent, RTGCPHYS GCPhys, RTGCPHYS GCPhysLast);
351VMMDECL(int) PGMHandlerPhysicalDeregister(PVM pVM, RTGCPHYS GCPhys);
352VMMDECL(int) PGMHandlerPhysicalChangeCallbacks(PVM pVM, RTGCPHYS GCPhys,
353 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnHandlerR3, RTR3PTR pvUserR3,
354 R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnHandlerR0, RTR0PTR pvUserR0,
355 RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnHandlerRC, RTRCPTR pvUserRC,
356 R3PTRTYPE(const char *) pszDesc);
357VMMDECL(int) PGMHandlerPhysicalSplit(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS GCPhysSplit);
358VMMDECL(int) PGMHandlerPhysicalJoin(PVM pVM, RTGCPHYS GCPhys1, RTGCPHYS GCPhys2);
359VMMDECL(int) PGMHandlerPhysicalPageTempOff(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS GCPhysPage);
360VMMDECL(int) PGMHandlerPhysicalPageAlias(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS GCPhysPage, RTGCPHYS GCPhysPageRemap);
361VMMDECL(int) PGMHandlerPhysicalPageAliasHC(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS GCPhysPage, RTHCPHYS HCPhysPageRemap);
362VMMDECL(int) PGMHandlerPhysicalReset(PVM pVM, RTGCPHYS GCPhys);
363VMMDECL(bool) PGMHandlerPhysicalIsRegistered(PVM pVM, RTGCPHYS GCPhys);
364VMMDECL(bool) PGMHandlerVirtualIsRegistered(PVM pVM, RTGCPTR GCPtr);
365VMMDECL(bool) PGMPhysIsA20Enabled(PVMCPU pVCpu);
366VMMDECL(bool) PGMPhysIsGCPhysValid(PVM pVM, RTGCPHYS GCPhys);
367VMMDECL(bool) PGMPhysIsGCPhysNormal(PVM pVM, RTGCPHYS GCPhys);
368VMMDECL(int) PGMPhysGCPtr2GCPhys(PVMCPU pVCpu, RTGCPTR GCPtr, PRTGCPHYS pGCPhys);
369VMMDECL(void) PGMPhysInvalidatePageMapTLB(PVM pVM);
370VMMDECL(void) PGMPhysInvalidatePageMapTLBEntry(PVM pVM, RTGCPHYS GCPhys);
371VMMDECL(void) PGMPhysReleasePageMappingLock(PVM pVM, PPGMPAGEMAPLOCK pLock);
372VMMDECL(int) PGMPhysRead(PVM pVM, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead);
373VMMDECL(int) PGMPhysWrite(PVM pVM, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite);
374VMMDECL(int) PGMPhysSimpleReadGCPhys(PVM pVM, void *pvDst, RTGCPHYS GCPhysSrc, size_t cb);
375VMMDECL(int) PGMPhysSimpleWriteGCPhys(PVM pVM, RTGCPHYS GCPhysDst, const void *pvSrc, size_t cb);
376VMMDECL(int) PGMPhysSimpleReadGCPtr(PVMCPU pVCpu, void *pvDst, RTGCPTR GCPtrSrc, size_t cb);
377VMMDECL(int) PGMPhysSimpleWriteGCPtr(PVMCPU pVCpu, RTGCPTR GCPtrDst, const void *pvSrc, size_t cb);
378VMMDECL(int) PGMPhysReadGCPtr(PVMCPU pVCpu, void *pvDst, RTGCPTR GCPtrSrc, size_t cb);
379VMMDECL(int) PGMPhysWriteGCPtr(PVMCPU pVCpu, RTGCPTR GCPtrDst, const void *pvSrc, size_t cb);
380VMMDECL(int) PGMPhysSimpleDirtyWriteGCPtr(PVMCPU pVCpu, RTGCPTR GCPtrDst, const void *pvSrc, size_t cb);
381VMMDECL(int) PGMPhysInterpretedRead(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, void *pvDst, RTGCPTR GCPtrSrc, size_t cb);
382VMMDECL(int) PGMPhysInterpretedReadNoHandlers(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, void *pvDst, RTGCUINTPTR GCPtrSrc, size_t cb, bool fRaiseTrap);
383VMMDECL(int) PGMPhysInterpretedWriteNoHandlers(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, RTGCPTR GCPtrDst, void const *pvSrc, size_t cb, bool fRaiseTrap);
384#ifdef VBOX_STRICT
385VMMDECL(unsigned) PGMAssertHandlerAndFlagsInSync(PVM pVM);
386VMMDECL(unsigned) PGMAssertNoMappingConflicts(PVM pVM);
387VMMDECL(unsigned) PGMAssertCR3(PVM pVM, PVMCPU pVCpu, uint64_t cr3, uint64_t cr4);
388#endif /* VBOX_STRICT */
389
390#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE)
391VMMDECL(void) PGMRZDynMapStartAutoSet(PVMCPU pVCpu);
392VMMDECL(void) PGMRZDynMapReleaseAutoSet(PVMCPU pVCpu);
393VMMDECL(void) PGMRZDynMapFlushAutoSet(PVMCPU pVCpu);
394VMMDECL(uint32_t) PGMRZDynMapPushAutoSubset(PVMCPU pVCpu);
395VMMDECL(void) PGMRZDynMapPopAutoSubset(PVMCPU pVCpu, uint32_t iPrevSubset);
396#endif
397
398VMMDECL(void) PGMSetLargePageUsage(PVM pVM, bool fUseLargePages);
399
400/**
401 * Query large page usage state
402 *
403 * @returns 0 - disabled, 1 - enabled
404 * @param pVM The VM to operate on.
405 */
406#define PGMIsUsingLargePages(pVM) ((pVM)->fUseLargePages)
407
408
409#ifdef IN_RC
410/** @defgroup grp_pgm_gc The PGM Guest Context API
411 * @ingroup grp_pgm
412 * @{
413 */
414VMMRCDECL(int) PGMRCDynMapInit(PVM pVM);
415/** @} */
416#endif /* IN_RC */
417
418
419#ifdef IN_RING0
420/** @defgroup grp_pgm_r0 The PGM Host Context Ring-0 API
421 * @ingroup grp_pgm
422 * @{
423 */
424VMMR0DECL(int) PGMR0PhysAllocateHandyPages(PVM pVM, PVMCPU pVCpu);
425VMMR0DECL(int) PGMR0PhysAllocateLargeHandyPage(PVM pVM, PVMCPU pVCpu);
426VMMR0_INT_DECL(int) PGMR0PhysSetupIommu(PVM pVM);
427VMMR0DECL(int) PGMR0SharedModuleCheck(PVM pVM, PGVM pGVM, VMCPUID idCpu, PGMMSHAREDMODULE pModule, uint32_t cRegions, PGMMSHAREDREGIONDESC pRegions);
428VMMR0DECL(int) PGMR0Trap0eHandlerNestedPaging(PVM pVM, PVMCPU pVCpu, PGMMODE enmShwPagingMode, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPHYS pvFault);
429VMMR0DECL(VBOXSTRICTRC) PGMR0Trap0eHandlerNPMisconfig(PVM pVM, PVMCPU pVCpu, PGMMODE enmShwPagingMode, PCPUMCTXCORE pRegFrame, RTGCPHYS GCPhysFault, uint32_t uErr);
430# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
431VMMR0DECL(int) PGMR0DynMapInit(void);
432VMMR0DECL(void) PGMR0DynMapTerm(void);
433VMMR0DECL(int) PGMR0DynMapInitVM(PVM pVM);
434VMMR0DECL(void) PGMR0DynMapTermVM(PVM pVM);
435VMMR0DECL(int) PGMR0DynMapAssertIntegrity(void);
436VMMR0DECL(bool) PGMR0DynMapStartOrMigrateAutoSet(PVMCPU pVCpu);
437VMMR0DECL(void) PGMR0DynMapMigrateAutoSet(PVMCPU pVCpu);
438# endif
439/** @} */
440#endif /* IN_RING0 */
441
442
443
444#ifdef IN_RING3
445/** @defgroup grp_pgm_r3 The PGM Host Context Ring-3 API
446 * @ingroup grp_pgm
447 * @{
448 */
449VMMR3DECL(int) PGMR3Init(PVM pVM);
450VMMR3DECL(int) PGMR3InitDynMap(PVM pVM);
451VMMR3DECL(int) PGMR3InitFinalize(PVM pVM);
452VMMR3_INT_DECL(int) PGMR3InitCompleted(PVM pVM, VMINITCOMPLETED enmWhat);
453VMMR3DECL(void) PGMR3Relocate(PVM pVM, RTGCINTPTR offDelta);
454VMMR3DECL(void) PGMR3ResetUnpluggedCpu(PVM pVM, PVMCPU pVCpu);
455VMMR3DECL(void) PGMR3Reset(PVM pVM);
456VMMR3DECL(int) PGMR3Term(PVM pVM);
457VMMR3DECL(int) PGMR3LockCall(PVM pVM);
458VMMR3DECL(int) PGMR3ChangeMode(PVM pVM, PVMCPU pVCpu, PGMMODE enmGuestMode);
459
460VMMR3DECL(int) PGMR3PhysRegisterRam(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, const char *pszDesc);
461VMMR3DECL(int) PGMR3PhysChangeMemBalloon(PVM pVM, bool fInflate, unsigned cPages, RTGCPHYS *paPhysPage);
462VMMR3DECL(int) PGMR3PhysWriteProtectRAM(PVM pVM);
463VMMR3DECL(int) PGMR3PhysEnumDirtyFTPages(PVM pVM, PFNPGMENUMDIRTYFTPAGES pfnEnum, void *pvUser);
464VMMR3DECL(uint32_t) PGMR3PhysGetRamRangeCount(PVM pVM);
465VMMR3DECL(int) PGMR3PhysGetRange(PVM pVM, uint32_t iRange, PRTGCPHYS pGCPhysStart, PRTGCPHYS pGCPhysLast,
466 const char **ppszDesc, bool *pfIsMmio);
467VMMR3DECL(int) PGMR3QueryMemoryStats(PVM pVM, uint64_t *pcbTotalMem, uint64_t *pcbPrivateMem, uint64_t *pcbSharedMem, uint64_t *pcbZeroMem);
468VMMR3DECL(int) PGMR3QueryGlobalMemoryStats(PVM pVM, uint64_t *pcbAllocMem, uint64_t *pcbFreeMem, uint64_t *pcbBallonedMem, uint64_t *pcbSharedMem);
469
470VMMR3DECL(int) PGMR3PhysMMIORegister(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb,
471 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnHandlerR3, RTR3PTR pvUserR3,
472 R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnHandlerR0, RTR0PTR pvUserR0,
473 RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnHandlerRC, RTRCPTR pvUserRC,
474 R3PTRTYPE(const char *) pszDesc);
475VMMR3DECL(int) PGMR3PhysMMIODeregister(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb);
476VMMR3DECL(int) PGMR3PhysMMIO2Register(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS cb, uint32_t fFlags, void **ppv, const char *pszDesc);
477VMMR3DECL(int) PGMR3PhysMMIO2Deregister(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion);
478VMMR3DECL(int) PGMR3PhysMMIO2Map(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS GCPhys);
479VMMR3DECL(int) PGMR3PhysMMIO2Unmap(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS GCPhys);
480VMMR3DECL(bool) PGMR3PhysMMIO2IsBase(PVM pVM, PPDMDEVINS pDevIns, RTGCPHYS GCPhys);
481VMMR3DECL(int) PGMR3PhysMMIO2GetHCPhys(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS off, PRTHCPHYS pHCPhys);
482VMMR3DECL(int) PGMR3PhysMMIO2MapKernel(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS off, RTGCPHYS cb, const char *pszDesc, PRTR0PTR pR0Ptr);
483
484/** @name PGMR3PhysRegisterRom flags.
485 * @{ */
486/** Inidicates that ROM shadowing should be enabled. */
487#define PGMPHYS_ROM_FLAGS_SHADOWED RT_BIT_32(0)
488/** Indicates that what pvBinary points to won't go away
489 * and can be used for strictness checks. */
490#define PGMPHYS_ROM_FLAGS_PERMANENT_BINARY RT_BIT_32(1)
491/** @} */
492
493VMMR3DECL(int) PGMR3PhysRomRegister(PVM pVM, PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTGCPHYS cb,
494 const void *pvBinary, uint32_t cbBinary, uint32_t fFlags, const char *pszDesc);
495VMMR3DECL(int) PGMR3PhysRomProtect(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, PGMROMPROT enmProt);
496VMMR3DECL(int) PGMR3PhysRegister(PVM pVM, void *pvRam, RTGCPHYS GCPhys, size_t cb, unsigned fFlags, const SUPPAGE *paPages, const char *pszDesc);
497VMMDECL(void) PGMR3PhysSetA20(PVMCPU pVCpu, bool fEnable);
498/** @name PGMR3MapPT flags.
499 * @{ */
500/** The mapping may be unmapped later. The default is permanent mappings. */
501#define PGMR3MAPPT_FLAGS_UNMAPPABLE RT_BIT(0)
502/** @} */
503VMMR3DECL(int) PGMR3MapPT(PVM pVM, RTGCPTR GCPtr, uint32_t cb, uint32_t fFlags, PFNPGMRELOCATE pfnRelocate, void *pvUser, const char *pszDesc);
504VMMR3DECL(int) PGMR3UnmapPT(PVM pVM, RTGCPTR GCPtr);
505VMMR3DECL(int) PGMR3FinalizeMappings(PVM pVM);
506VMMR3DECL(int) PGMR3MappingsDisable(PVM pVM);
507VMMR3DECL(int) PGMR3MappingsSize(PVM pVM, uint32_t *pcb);
508VMMR3DECL(int) PGMR3MappingsFix(PVM pVM, RTGCPTR GCPtrBase, uint32_t cb);
509VMMR3DECL(int) PGMR3MappingsUnfix(PVM pVM);
510VMMR3DECL(bool) PGMR3MappingsNeedReFixing(PVM pVM);
511VMMR3DECL(int) PGMR3MapIntermediate(PVM pVM, RTUINTPTR Addr, RTHCPHYS HCPhys, unsigned cbPages);
512VMMR3DECL(int) PGMR3MapRead(PVM pVM, void *pvDst, RTGCPTR GCPtrSrc, size_t cb);
513
514VMMR3DECL(int) PGMR3HandlerPhysicalRegister(PVM pVM, PGMPHYSHANDLERTYPE enmType, RTGCPHYS GCPhys, RTGCPHYS GCPhysLast,
515 PFNPGMR3PHYSHANDLER pfnHandlerR3, void *pvUserR3,
516 const char *pszModR0, const char *pszHandlerR0, RTR0PTR pvUserR0,
517 const char *pszModRC, const char *pszHandlerRC, RTRCPTR pvUserRC, const char *pszDesc);
518VMMDECL(int) PGMR3HandlerVirtualRegisterEx(PVM pVM, PGMVIRTHANDLERTYPE enmType, RTGCPTR GCPtr, RTGCPTR GCPtrLast,
519 R3PTRTYPE(PFNPGMR3VIRTINVALIDATE) pfnInvalidateR3,
520 R3PTRTYPE(PFNPGMR3VIRTHANDLER) pfnHandlerR3,
521 RCPTRTYPE(PFNPGMRCVIRTHANDLER) pfnHandlerRC,
522 R3PTRTYPE(const char *) pszDesc);
523VMMR3DECL(int) PGMR3HandlerVirtualRegister(PVM pVM, PGMVIRTHANDLERTYPE enmType, RTGCPTR GCPtr, RTGCPTR GCPtrLast,
524 PFNPGMR3VIRTINVALIDATE pfnInvalidateR3,
525 PFNPGMR3VIRTHANDLER pfnHandlerR3,
526 const char *pszHandlerRC, const char *pszModRC, const char *pszDesc);
527VMMDECL(int) PGMHandlerVirtualChangeInvalidateCallback(PVM pVM, RTGCPTR GCPtr, R3PTRTYPE(PFNPGMR3VIRTINVALIDATE) pfnInvalidateR3);
528VMMDECL(int) PGMHandlerVirtualDeregister(PVM pVM, RTGCPTR GCPtr);
529VMMR3DECL(int) PGMR3PoolGrow(PVM pVM);
530
531VMMR3DECL(int) PGMR3PhysTlbGCPhys2Ptr(PVM pVM, RTGCPHYS GCPhys, bool fWritable, void **ppv);
532VMMR3DECL(uint8_t) PGMR3PhysReadU8(PVM pVM, RTGCPHYS GCPhys);
533VMMR3DECL(uint16_t) PGMR3PhysReadU16(PVM pVM, RTGCPHYS GCPhys);
534VMMR3DECL(uint32_t) PGMR3PhysReadU32(PVM pVM, RTGCPHYS GCPhys);
535VMMR3DECL(uint64_t) PGMR3PhysReadU64(PVM pVM, RTGCPHYS GCPhys);
536VMMR3DECL(void) PGMR3PhysWriteU8(PVM pVM, RTGCPHYS GCPhys, uint8_t Value);
537VMMR3DECL(void) PGMR3PhysWriteU16(PVM pVM, RTGCPHYS GCPhys, uint16_t Value);
538VMMR3DECL(void) PGMR3PhysWriteU32(PVM pVM, RTGCPHYS GCPhys, uint32_t Value);
539VMMR3DECL(void) PGMR3PhysWriteU64(PVM pVM, RTGCPHYS GCPhys, uint64_t Value);
540VMMR3DECL(int) PGMR3PhysReadExternal(PVM pVM, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead);
541VMMR3DECL(int) PGMR3PhysWriteExternal(PVM pVM, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite, const char *pszWho);
542VMMR3DECL(int) PGMR3PhysGCPhys2CCPtrExternal(PVM pVM, RTGCPHYS GCPhys, void **ppv, PPGMPAGEMAPLOCK pLock);
543VMMR3DECL(int) PGMR3PhysGCPhys2CCPtrReadOnlyExternal(PVM pVM, RTGCPHYS GCPhys, void const **ppv, PPGMPAGEMAPLOCK pLock);
544VMMR3DECL(int) PGMR3PhysChunkMap(PVM pVM, uint32_t idChunk);
545VMMR3DECL(void) PGMR3PhysChunkInvalidateTLB(PVM pVM);
546VMMR3DECL(int) PGMR3PhysAllocateHandyPages(PVM pVM);
547VMMR3DECL(int) PGMR3PhysAllocateLargeHandyPage(PVM pVM, RTGCPHYS GCPhys);
548
549VMMR3DECL(int) PGMR3CheckIntegrity(PVM pVM);
550
551VMMR3DECL(int) PGMR3DbgR3Ptr2GCPhys(PVM pVM, RTR3PTR R3Ptr, PRTGCPHYS pGCPhys);
552VMMR3DECL(int) PGMR3DbgR3Ptr2HCPhys(PVM pVM, RTR3PTR R3Ptr, PRTHCPHYS pHCPhys);
553VMMR3DECL(int) PGMR3DbgHCPhys2GCPhys(PVM pVM, RTHCPHYS HCPhys, PRTGCPHYS pGCPhys);
554VMMR3DECL(int) PGMR3DbgReadGCPhys(PVM pVM, void *pvDst, RTGCPHYS GCPhysSrc, size_t cb, uint32_t fFlags, size_t *pcbRead);
555VMMR3DECL(int) PGMR3DbgWriteGCPhys(PVM pVM, RTGCPHYS GCPhysDst, const void *pvSrc, size_t cb, uint32_t fFlags, size_t *pcbWritten);
556VMMR3DECL(int) PGMR3DbgReadGCPtr(PVM pVM, void *pvDst, RTGCPTR GCPtrSrc, size_t cb, uint32_t fFlags, size_t *pcbRead);
557VMMR3DECL(int) PGMR3DbgWriteGCPtr(PVM pVM, RTGCPTR GCPtrDst, void const *pvSrc, size_t cb, uint32_t fFlags, size_t *pcbWritten);
558VMMR3DECL(int) PGMR3DbgScanPhysical(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cbRange, RTGCPHYS GCPhysAlign, const uint8_t *pabNeedle, size_t cbNeedle, PRTGCPHYS pGCPhysHit);
559VMMR3DECL(int) PGMR3DbgScanVirtual(PVM pVM, PVMCPU pVCpu, RTGCPTR GCPtr, RTGCPTR cbRange, RTGCPTR GCPtrAlign, const uint8_t *pabNeedle, size_t cbNeedle, PRTGCUINTPTR pGCPhysHit);
560VMMR3_INT_DECL(int) PGMR3DumpHierarchyShw(PVM pVM, uint64_t cr3, uint32_t fFlags, uint64_t u64FirstAddr, uint64_t u64LastAddr, uint32_t cMaxDepth, PCDBGFINFOHLP pHlp);
561VMMR3_INT_DECL(int) PGMR3DumpHierarchyGst(PVM pVM, uint64_t cr3, uint32_t fFlags, RTGCPTR FirstAddr, RTGCPTR LastAddr, uint32_t cMaxDepth, PCDBGFINFOHLP pHlp);
562
563
564/** @name Page sharing
565 * @{ */
566VMMR3DECL(int) PGMR3SharedModuleRegister(PVM pVM, VBOXOSFAMILY enmGuestOS, char *pszModuleName, char *pszVersion, RTGCPTR GCBaseAddr, uint32_t cbModule, unsigned cRegions, VMMDEVSHAREDREGIONDESC *pRegions);
567VMMR3DECL(int) PGMR3SharedModuleUnregister(PVM pVM, char *pszModuleName, char *pszVersion, RTGCPTR GCBaseAddr, uint32_t cbModule);
568VMMR3DECL(int) PGMR3SharedModuleCheckAll(PVM pVM);
569VMMR3DECL(int) PGMR3SharedModuleGetPageState(PVM pVM, RTGCPTR GCPtrPage, bool *pfShared, uint64_t *puPageFlags);
570/** @} */
571
572/** @} */
573#endif /* IN_RING3 */
574
575RT_C_DECLS_END
576
577/** @} */
578#endif
579
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