pgm.h@ 45024

Last change on this file since 45024 was 45024, checked in by vboxsync, 12 years ago
PDM,PGM,DevEFI,DevACPI,DevPcBios: Added memory setup phase after construction and reset to solve PGM/PDM reset order issue (PDM first, then PGM, only that wasn't possible previously since PDM reset would plant stuff in guest RAM).
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 30.1 KB

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1	/** @file
2	* PGM - Page Monitor / Monitor.
3	*/
4
5	/*
6	* Copyright (C) 2006-2013 Oracle Corporation
7	*
8	* This file is part of VirtualBox Open Source Edition (OSE), as
9	* available from http://www.virtualbox.org. This file is free software;
10	* you can redistribute it and/or modify it under the terms of the GNU
11	* General Public License (GPL) as published by the Free Software
12	* Foundation, in version 2 as it comes in the "COPYING" file of the
13	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15	*
16	* The contents of this file may alternatively be used under the terms
17	* of the Common Development and Distribution License Version 1.0
18	* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19	* VirtualBox OSE distribution, in which case the provisions of the
20	* CDDL are applicable instead of those of the GPL.
21	*
22	* You may elect to license modified versions of this file under the
23	* terms and conditions of either the GPL or the CDDL or both.
24	*/
25
26	#ifndef ___VBox_vmm_pgm_h
27	#define ___VBox_vmm_pgm_h
28
29	#include <VBox/types.h>
30	#include <VBox/sup.h>
31	#include <VBox/vmm/vmapi.h>
32	#include <VBox/vmm/gmm.h> /* for PGMMREGISTERSHAREDMODULEREQ */
33	#include <iprt/x86.h>
34	#include <VBox/VMMDev.h> /* for VMMDEVSHAREDREGIONDESC */
35	#include <VBox/param.h>
36
37	RT_C_DECLS_BEGIN
38
39	/** @defgroup grp_pgm The Page Monitor / Manager API
40	* @{
41	*/
42
43	/**
44	* FNPGMRELOCATE callback mode.
45	*/
46	typedef enum PGMRELOCATECALL
47	{
48	/** The callback is for checking if the suggested address is suitable. */
49	PGMRELOCATECALL_SUGGEST = 1,
50	/** The callback is for executing the relocation. */
51	PGMRELOCATECALL_RELOCATE
52	} PGMRELOCATECALL;
53
54
55	/**
56	* Callback function which will be called when PGM is trying to find
57	* a new location for the mapping.
58	*
59	* The callback is called in two modes, 1) the check mode and 2) the relocate mode.
60	* In 1) the callback should say if it objects to a suggested new location. If it
61	* accepts the new location, it is called again for doing it's relocation.
62	*
63	*
64	* @returns true if the location is ok.
65	* @returns false if another location should be found.
66	* @param GCPtrOld The old virtual address.
67	* @param GCPtrNew The new virtual address.
68	* @param enmMode Used to indicate the callback mode.
69	* @param pvUser User argument.
70	* @remark The return value is no a failure indicator, it's an acceptance
71	* indicator. Relocation can not fail!
72	*/
73	typedef DECLCALLBACK(bool) FNPGMRELOCATE(PVM pVM, RTGCPTR GCPtrOld, RTGCPTR GCPtrNew, PGMRELOCATECALL enmMode, void *pvUser);
74	/** Pointer to a relocation callback function. */
75	typedef FNPGMRELOCATE *PFNPGMRELOCATE;
76
77
78	/**
79	* Physical page access handler type.
80	*/
81	typedef enum PGMPHYSHANDLERTYPE
82	{
83	/** MMIO range. Pages are not present, all access is done in interpreter or recompiler. */
84	PGMPHYSHANDLERTYPE_MMIO = 1,
85	/** Handler all write access to a physical page range. */
86	PGMPHYSHANDLERTYPE_PHYSICAL_WRITE,
87	/** Handler all access to a physical page range. */
88	PGMPHYSHANDLERTYPE_PHYSICAL_ALL
89
90	} PGMPHYSHANDLERTYPE;
91
92	/**
93	* \#PF Handler callback for physical access handler ranges in RC.
94	*
95	* @returns VBox status code (appropriate for RC return).
96	* @param pVM VM Handle.
97	* @param uErrorCode CPU Error code.
98	* @param pRegFrame Trap register frame.
99	* NULL on DMA and other non CPU access.
100	* @param pvFault The fault address (cr2).
101	* @param GCPhysFault The GC physical address corresponding to pvFault.
102	* @param pvUser User argument.
103	*/
104	typedef DECLCALLBACK(int) FNPGMRCPHYSHANDLER(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser);
105	/** Pointer to PGM access callback. */
106	typedef FNPGMRCPHYSHANDLER *PFNPGMRCPHYSHANDLER;
107
108	/**
109	* \#PF Handler callback for physical access handler ranges in R0.
110	*
111	* @returns VBox status code (appropriate for R0 return).
112	* @param pVM VM Handle.
113	* @param uErrorCode CPU Error code.
114	* @param pRegFrame Trap register frame.
115	* NULL on DMA and other non CPU access.
116	* @param pvFault The fault address (cr2).
117	* @param GCPhysFault The GC physical address corresponding to pvFault.
118	* @param pvUser User argument.
119	*/
120	typedef DECLCALLBACK(int) FNPGMR0PHYSHANDLER(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser);
121	/** Pointer to PGM access callback. */
122	typedef FNPGMR0PHYSHANDLER *PFNPGMR0PHYSHANDLER;
123
124	/**
125	* Guest Access type
126	*/
127	typedef enum PGMACCESSTYPE
128	{
129	/** Read access. */
130	PGMACCESSTYPE_READ = 1,
131	/** Write access. */
132	PGMACCESSTYPE_WRITE
133	} PGMACCESSTYPE;
134
135	/**
136	* \#PF Handler callback for physical access handler ranges (MMIO among others) in HC.
137	*
138	* The handler can not raise any faults, it's mainly for monitoring write access
139	* to certain pages.
140	*
141	* @returns VINF_SUCCESS if the handler have carried out the operation.
142	* @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
143	* @param pVM VM Handle.
144	* @param GCPhys The physical address the guest is writing to.
145	* @param pvPhys The HC mapping of that address.
146	* @param pvBuf What the guest is reading/writing.
147	* @param cbBuf How much it's reading/writing.
148	* @param enmAccessType The access type.
149	* @param pvUser User argument.
150	*
151	* @todo Add pVCpu, possibly replacing pVM.
152	*/
153	typedef DECLCALLBACK(int) FNPGMR3PHYSHANDLER(PVM pVM, RTGCPHYS GCPhys, void pvPhys, void pvBuf, size_t cbBuf, PGMACCESSTYPE enmAccessType, void *pvUser);
154	/** Pointer to PGM access callback. */
155	typedef FNPGMR3PHYSHANDLER *PFNPGMR3PHYSHANDLER;
156
157
158	/**
159	* Virtual access handler type.
160	*/
161	typedef enum PGMVIRTHANDLERTYPE
162	{
163	/** Write access handled. */
164	PGMVIRTHANDLERTYPE_WRITE = 1,
165	/** All access handled. */
166	PGMVIRTHANDLERTYPE_ALL,
167	/** Hypervisor write access handled.
168	* This is used to catch the guest trying to write to LDT, TSS and any other
169	* system structure which the brain dead intel guys let unprivilegde code find. */
170	PGMVIRTHANDLERTYPE_HYPERVISOR
171	} PGMVIRTHANDLERTYPE;
172
173	/**
174	* \#PF Handler callback for virtual access handler ranges, RC.
175	*
176	* Important to realize that a physical page in a range can have aliases, and
177	* for ALL and WRITE handlers these will also trigger.
178	*
179	* @returns VBox status code (appropriate for GC return).
180	* @param pVM VM Handle.
181	* @param uErrorCode CPU Error code.
182	* @param pRegFrame Trap register frame.
183	* @param pvFault The fault address (cr2).
184	* @param pvRange The base address of the handled virtual range.
185	* @param offRange The offset of the access into this range.
186	* (If it's a EIP range this is the EIP, if not it's pvFault.)
187	* @todo Add pVCpu, possibly replacing pVM.
188	*/
189	typedef DECLCALLBACK(int) FNPGMRCVIRTHANDLER(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPTR pvRange, uintptr_t offRange);
190	/** Pointer to PGM access callback. */
191	typedef FNPGMRCVIRTHANDLER *PFNPGMRCVIRTHANDLER;
192
193	/**
194	* \#PF Handler callback for virtual access handler ranges, R3.
195	*
196	* Important to realize that a physical page in a range can have aliases, and
197	* for ALL and WRITE handlers these will also trigger.
198	*
199	* @returns VINF_SUCCESS if the handler have carried out the operation.
200	* @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
201	* @param pVM VM Handle.
202	* @param GCPtr The virtual address the guest is writing to. (not correct if it's an alias!)
203	* @param pvPtr The HC mapping of that address.
204	* @param pvBuf What the guest is reading/writing.
205	* @param cbBuf How much it's reading/writing.
206	* @param enmAccessType The access type.
207	* @param pvUser User argument.
208	* @todo Add pVCpu, possibly replacing pVM.
209	*/
210	typedef DECLCALLBACK(int) FNPGMR3VIRTHANDLER(PVM pVM, RTGCPTR GCPtr, void pvPtr, void pvBuf, size_t cbBuf, PGMACCESSTYPE enmAccessType, void *pvUser);
211	/** Pointer to PGM access callback. */
212	typedef FNPGMR3VIRTHANDLER *PFNPGMR3VIRTHANDLER;
213
214
215	/**
216	* \#PF Handler callback for invalidation of virtual access handler ranges.
217	*
218	* @param pVM VM Handle.
219	* @param GCPtr The virtual address the guest has changed.
220	*/
221	typedef DECLCALLBACK(int) FNPGMR3VIRTINVALIDATE(PVM pVM, RTGCPTR GCPtr);
222	/** Pointer to PGM invalidation callback. */
223	typedef FNPGMR3VIRTINVALIDATE *PFNPGMR3VIRTINVALIDATE;
224
225	/**
226	* PGMR3PhysEnumDirtyFTPages callback for syncing dirty physical pages
227	*
228	* @param pVM VM Handle.
229	* @param GCPhys GC physical address
230	* @param pRange HC virtual address of the page(s)
231	* @param cbRange Size of the dirty range in bytes.
232	* @param pvUser User argument.
233	*/
234	typedef DECLCALLBACK(int) FNPGMENUMDIRTYFTPAGES(PVM pVM, RTGCPHYS GCPhys, uint8_t pRange, unsigned cbRange, void pvUser);
235	/** Pointer to PGMR3PhysEnumDirtyFTPages callback. */
236	typedef FNPGMENUMDIRTYFTPAGES *PFNPGMENUMDIRTYFTPAGES;
237
238	/**
239	* Paging mode.
240	*/
241	typedef enum PGMMODE
242	{
243	/** The usual invalid value. */
244	PGMMODE_INVALID = 0,
245	/** Real mode. */
246	PGMMODE_REAL,
247	/** Protected mode, no paging. */
248	PGMMODE_PROTECTED,
249	/** 32-bit paging. */
250	PGMMODE_32_BIT,
251	/** PAE paging. */
252	PGMMODE_PAE,
253	/** PAE paging with NX enabled. */
254	PGMMODE_PAE_NX,
255	/** 64-bit AMD paging (long mode). */
256	PGMMODE_AMD64,
257	/** 64-bit AMD paging (long mode) with NX enabled. */
258	PGMMODE_AMD64_NX,
259	/** Nested paging mode (shadow only; guest physical to host physical). */
260	PGMMODE_NESTED,
261	/** Extended paging (Intel) mode. */
262	PGMMODE_EPT,
263	/** The max number of modes */
264	PGMMODE_MAX,
265	/** 32bit hackishness. */
266	PGMMODE_32BIT_HACK = 0x7fffffff
267	} PGMMODE;
268
269	/** Macro for checking if the guest is using paging.
270	* @param enmMode PGMMODE_*.
271	* @remark ASSUMES certain order of the PGMMODE_* values.
272	*/
273	#define PGMMODE_WITH_PAGING(enmMode) ((enmMode) >= PGMMODE_32_BIT)
274
275	/** Macro for checking if it's one of the long mode modes.
276	* @param enmMode PGMMODE_*.
277	*/
278	#define PGMMODE_IS_LONG_MODE(enmMode) ((enmMode) == PGMMODE_AMD64_NX \|\| (enmMode) == PGMMODE_AMD64)
279
280	/**
281	* Is the ROM mapped (true) or is the shadow RAM mapped (false).
282	*
283	* @returns boolean.
284	* @param enmProt The PGMROMPROT value, must be valid.
285	*/
286	#define PGMROMPROT_IS_ROM(enmProt) \
287	( (enmProt) == PGMROMPROT_READ_ROM_WRITE_IGNORE \
288	\|\| (enmProt) == PGMROMPROT_READ_ROM_WRITE_RAM )
289
290
291
292	VMMDECL(bool) PGMIsLockOwner(PVM pVM);
293
294	VMMDECL(int) PGMRegisterStringFormatTypes(void);
295	VMMDECL(void) PGMDeregisterStringFormatTypes(void);
296	VMMDECL(RTHCPHYS) PGMGetHyperCR3(PVMCPU pVCpu);
297	VMMDECL(RTHCPHYS) PGMGetNestedCR3(PVMCPU pVCpu, PGMMODE enmShadowMode);
298	VMMDECL(RTHCPHYS) PGMGetInterHCCR3(PVM pVM);
299	VMMDECL(RTHCPHYS) PGMGetInterRCCR3(PVM pVM, PVMCPU pVCpu);
300	VMMDECL(RTHCPHYS) PGMGetInter32BitCR3(PVM pVM);
301	VMMDECL(RTHCPHYS) PGMGetInterPaeCR3(PVM pVM);
302	VMMDECL(RTHCPHYS) PGMGetInterAmd64CR3(PVM pVM);
303	VMMDECL(int) PGMTrap0eHandler(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault);
304	VMMDECL(int) PGMPrefetchPage(PVMCPU pVCpu, RTGCPTR GCPtrPage);
305	VMMDECL(int) PGMVerifyAccess(PVMCPU pVCpu, RTGCPTR Addr, uint32_t cbSize, uint32_t fAccess);
306	VMMDECL(int) PGMIsValidAccess(PVMCPU pVCpu, RTGCPTR Addr, uint32_t cbSize, uint32_t fAccess);
307	VMMDECL(VBOXSTRICTRC) PGMInterpretInstruction(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault);
308	VMMDECL(int) PGMMap(PVM pVM, RTGCPTR GCPtr, RTHCPHYS HCPhys, uint32_t cbPages, unsigned fFlags);
309	VMMDECL(int) PGMMapGetPage(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys);
310	VMMDECL(int) PGMMapSetPage(PVM pVM, RTGCPTR GCPtr, uint64_t cb, uint64_t fFlags);
311	VMMDECL(int) PGMMapModifyPage(PVM pVM, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask);
312	#ifndef IN_RING0
313	VMMDECL(bool) PGMMapHasConflicts(PVM pVM);
314	#endif
315	#ifdef VBOX_STRICT
316	VMMDECL(void) PGMMapCheck(PVM pVM);
317	#endif
318	VMMDECL(int) PGMShwGetPage(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys);
319	VMMDECL(int) PGMShwMakePageReadonly(PVMCPU pVCpu, RTGCPTR GCPtr, uint32_t fFlags);
320	VMMDECL(int) PGMShwMakePageWritable(PVMCPU pVCpu, RTGCPTR GCPtr, uint32_t fFlags);
321	VMMDECL(int) PGMShwMakePageNotPresent(PVMCPU pVCpu, RTGCPTR GCPtr, uint32_t fFlags);
322	/** @name Flags for PGMShwMakePageReadonly, PGMShwMakePageWritable and
323	* PGMShwMakePageNotPresent
324	* @{ */
325	/** The call is from an access handler for dealing with the a faulting write
326	* operation. The virtual address is within the same page. */
327	#define PGM_MK_PG_IS_WRITE_FAULT RT_BIT(0)
328	/** The page is an MMIO2. */
329	#define PGM_MK_PG_IS_MMIO2 RT_BIT(1)
330	/** @}*/
331	VMMDECL(int) PGMGstGetPage(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys);
332	VMMDECL(bool) PGMGstIsPagePresent(PVMCPU pVCpu, RTGCPTR GCPtr);
333	VMMDECL(int) PGMGstSetPage(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cb, uint64_t fFlags);
334	VMMDECL(int) PGMGstModifyPage(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask);
335	VMM_INT_DECL(int) PGMGstGetPaePdpes(PVMCPU pVCpu, PX86PDPE paPdpes);
336	VMM_INT_DECL(int) PGMGstUpdatePaePdpes(PVMCPU pVCpu, PCX86PDPE paPdpes);
337
338	VMMDECL(int) PGMInvalidatePage(PVMCPU pVCpu, RTGCPTR GCPtrPage);
339	VMMDECL(int) PGMFlushTLB(PVMCPU pVCpu, uint64_t cr3, bool fGlobal);
340	VMMDECL(int) PGMSyncCR3(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal);
341	VMMDECL(int) PGMUpdateCR3(PVMCPU pVCpu, uint64_t cr3);
342	VMMDECL(int) PGMChangeMode(PVMCPU pVCpu, uint64_t cr0, uint64_t cr4, uint64_t efer);
343	VMMDECL(PGMMODE) PGMGetGuestMode(PVMCPU pVCpu);
344	VMMDECL(PGMMODE) PGMGetShadowMode(PVMCPU pVCpu);
345	VMMDECL(PGMMODE) PGMGetHostMode(PVM pVM);
346	VMMDECL(const char *) PGMGetModeName(PGMMODE enmMode);
347	VMM_INT_DECL(void) PGMNotifyNxeChanged(PVMCPU pVCpu, bool fNxe);
348	VMMDECL(bool) PGMHasDirtyPages(PVM pVM);
349	VMMDECL(int) PGMHandlerPhysicalRegisterEx(PVM pVM, PGMPHYSHANDLERTYPE enmType, RTGCPHYS GCPhys, RTGCPHYS GCPhysLast,
350	R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnHandlerR3, RTR3PTR pvUserR3,
351	R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnHandlerR0, RTR0PTR pvUserR0,
352	RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnHandlerRC, RTRCPTR pvUserRC,
353	R3PTRTYPE(const char *) pszDesc);
354	VMMDECL(int) PGMHandlerPhysicalModify(PVM pVM, RTGCPHYS GCPhysCurrent, RTGCPHYS GCPhys, RTGCPHYS GCPhysLast);
355	VMMDECL(int) PGMHandlerPhysicalDeregister(PVM pVM, RTGCPHYS GCPhys);
356	VMMDECL(int) PGMHandlerPhysicalChangeCallbacks(PVM pVM, RTGCPHYS GCPhys,
357	R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnHandlerR3, RTR3PTR pvUserR3,
358	R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnHandlerR0, RTR0PTR pvUserR0,
359	RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnHandlerRC, RTRCPTR pvUserRC,
360	R3PTRTYPE(const char *) pszDesc);
361	VMMDECL(int) PGMHandlerPhysicalSplit(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS GCPhysSplit);
362	VMMDECL(int) PGMHandlerPhysicalJoin(PVM pVM, RTGCPHYS GCPhys1, RTGCPHYS GCPhys2);
363	VMMDECL(int) PGMHandlerPhysicalPageTempOff(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS GCPhysPage);
364	VMMDECL(int) PGMHandlerPhysicalPageAlias(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS GCPhysPage, RTGCPHYS GCPhysPageRemap);
365	VMMDECL(int) PGMHandlerPhysicalPageAliasHC(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS GCPhysPage, RTHCPHYS HCPhysPageRemap);
366	VMMDECL(int) PGMHandlerPhysicalReset(PVM pVM, RTGCPHYS GCPhys);
367	VMMDECL(bool) PGMHandlerPhysicalIsRegistered(PVM pVM, RTGCPHYS GCPhys);
368	VMMDECL(bool) PGMHandlerVirtualIsRegistered(PVM pVM, RTGCPTR GCPtr);
369	VMMDECL(bool) PGMPhysIsA20Enabled(PVMCPU pVCpu);
370	VMMDECL(bool) PGMPhysIsGCPhysValid(PVM pVM, RTGCPHYS GCPhys);
371	VMMDECL(bool) PGMPhysIsGCPhysNormal(PVM pVM, RTGCPHYS GCPhys);
372	VMMDECL(int) PGMPhysGCPtr2GCPhys(PVMCPU pVCpu, RTGCPTR GCPtr, PRTGCPHYS pGCPhys);
373	VMMDECL(void) PGMPhysReleasePageMappingLock(PVM pVM, PPGMPAGEMAPLOCK pLock);
374	VMMDECL(int) PGMPhysRead(PVM pVM, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead);
375	VMMDECL(int) PGMPhysWrite(PVM pVM, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite);
376	VMMDECL(int) PGMPhysSimpleReadGCPhys(PVM pVM, void *pvDst, RTGCPHYS GCPhysSrc, size_t cb);
377	VMMDECL(int) PGMPhysSimpleWriteGCPhys(PVM pVM, RTGCPHYS GCPhysDst, const void *pvSrc, size_t cb);
378	VMMDECL(int) PGMPhysSimpleReadGCPtr(PVMCPU pVCpu, void *pvDst, RTGCPTR GCPtrSrc, size_t cb);
379	VMMDECL(int) PGMPhysSimpleWriteGCPtr(PVMCPU pVCpu, RTGCPTR GCPtrDst, const void *pvSrc, size_t cb);
380	VMMDECL(int) PGMPhysReadGCPtr(PVMCPU pVCpu, void *pvDst, RTGCPTR GCPtrSrc, size_t cb);
381	VMMDECL(int) PGMPhysWriteGCPtr(PVMCPU pVCpu, RTGCPTR GCPtrDst, const void *pvSrc, size_t cb);
382	VMMDECL(int) PGMPhysSimpleDirtyWriteGCPtr(PVMCPU pVCpu, RTGCPTR GCPtrDst, const void *pvSrc, size_t cb);
383	VMMDECL(int) PGMPhysInterpretedRead(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, void *pvDst, RTGCPTR GCPtrSrc, size_t cb);
384	VMMDECL(int) PGMPhysInterpretedReadNoHandlers(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, void *pvDst, RTGCUINTPTR GCPtrSrc, size_t cb, bool fRaiseTrap);
385	VMMDECL(int) PGMPhysInterpretedWriteNoHandlers(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, RTGCPTR GCPtrDst, void const *pvSrc, size_t cb, bool fRaiseTrap);
386	VMM_INT_DECL(int) PGMPhysIemGCPhys2Ptr(PVM pVM, RTGCPHYS GCPhys, bool fWritable, bool fByPassHandlers, void **ppv, PPGMPAGEMAPLOCK pLock);
387	#ifdef VBOX_STRICT
388	VMMDECL(unsigned) PGMAssertHandlerAndFlagsInSync(PVM pVM);
389	VMMDECL(unsigned) PGMAssertNoMappingConflicts(PVM pVM);
390	VMMDECL(unsigned) PGMAssertCR3(PVM pVM, PVMCPU pVCpu, uint64_t cr3, uint64_t cr4);
391	#endif /* VBOX_STRICT */
392
393	#if defined(IN_RC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE)
394	VMMDECL(void) PGMRZDynMapStartAutoSet(PVMCPU pVCpu);
395	VMMDECL(void) PGMRZDynMapReleaseAutoSet(PVMCPU pVCpu);
396	VMMDECL(void) PGMRZDynMapFlushAutoSet(PVMCPU pVCpu);
397	VMMDECL(uint32_t) PGMRZDynMapPushAutoSubset(PVMCPU pVCpu);
398	VMMDECL(void) PGMRZDynMapPopAutoSubset(PVMCPU pVCpu, uint32_t iPrevSubset);
399	#endif
400
401	VMMDECL(int) PGMSetLargePageUsage(PVM pVM, bool fUseLargePages);
402
403	/**
404	* Query large page usage state
405	*
406	* @returns 0 - disabled, 1 - enabled
407	* @param pVM The VM to operate on.
408	*/
409	#define PGMIsUsingLargePages(pVM) ((pVM)->fUseLargePages)
410
411
412	#ifdef IN_RC
413	/** @defgroup grp_pgm_gc The PGM Guest Context API
414	* @ingroup grp_pgm
415	* @{
416	*/
417	VMMRCDECL(int) PGMRCDynMapInit(PVM pVM);
418	/** @} */
419	#endif /* IN_RC */
420
421
422	#ifdef IN_RING0
423	/** @defgroup grp_pgm_r0 The PGM Host Context Ring-0 API
424	* @ingroup grp_pgm
425	* @{
426	*/
427	VMMR0_INT_DECL(int) PGMR0PhysAllocateHandyPages(PVM pVM, PVMCPU pVCpu);
428	VMMR0_INT_DECL(int) PGMR0PhysFlushHandyPages(PVM pVM, PVMCPU pVCpu);
429	VMMR0_INT_DECL(int) PGMR0PhysAllocateLargeHandyPage(PVM pVM, PVMCPU pVCpu);
430	VMMR0_INT_DECL(int) PGMR0PhysSetupIommu(PVM pVM);
431	VMMR0DECL(int) PGMR0SharedModuleCheck(PVM pVM, PGVM pGVM, VMCPUID idCpu, PGMMSHAREDMODULE pModule, PCRTGCPTR64 paRegionsGCPtrs);
432	VMMR0DECL(int) PGMR0Trap0eHandlerNestedPaging(PVM pVM, PVMCPU pVCpu, PGMMODE enmShwPagingMode, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPHYS pvFault);
433	VMMR0DECL(VBOXSTRICTRC) PGMR0Trap0eHandlerNPMisconfig(PVM pVM, PVMCPU pVCpu, PGMMODE enmShwPagingMode, PCPUMCTXCORE pRegFrame, RTGCPHYS GCPhysFault, uint32_t uErr);
434	# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
435	VMMR0DECL(int) PGMR0DynMapInit(void);
436	VMMR0DECL(void) PGMR0DynMapTerm(void);
437	VMMR0DECL(int) PGMR0DynMapInitVM(PVM pVM);
438	VMMR0DECL(void) PGMR0DynMapTermVM(PVM pVM);
439	VMMR0DECL(int) PGMR0DynMapAssertIntegrity(void);
440	VMMR0DECL(bool) PGMR0DynMapStartOrMigrateAutoSet(PVMCPU pVCpu);
441	VMMR0DECL(void) PGMR0DynMapMigrateAutoSet(PVMCPU pVCpu);
442	# endif
443	/** @} */
444	#endif /* IN_RING0 */
445
446
447
448	#ifdef IN_RING3
449	/** @defgroup grp_pgm_r3 The PGM Host Context Ring-3 API
450	* @ingroup grp_pgm
451	* @{
452	*/
453	VMMR3DECL(int) PGMR3Init(PVM pVM);
454	VMMR3DECL(int) PGMR3InitDynMap(PVM pVM);
455	VMMR3DECL(int) PGMR3InitFinalize(PVM pVM);
456	VMMR3_INT_DECL(int) PGMR3InitCompleted(PVM pVM, VMINITCOMPLETED enmWhat);
457	VMMR3DECL(void) PGMR3Relocate(PVM pVM, RTGCINTPTR offDelta);
458	VMMR3DECL(void) PGMR3ResetCpu(PVM pVM, PVMCPU pVCpu);
459	VMMR3_INT_DECL(void) PGMR3Reset(PVM pVM);
460	VMMR3_INT_DECL(void) PGMR3MemSetup(PVM pVM, bool fReset);
461	VMMR3DECL(int) PGMR3Term(PVM pVM);
462	VMMR3DECL(int) PGMR3LockCall(PVM pVM);
463	VMMR3DECL(int) PGMR3ChangeMode(PVM pVM, PVMCPU pVCpu, PGMMODE enmGuestMode);
464
465	VMMR3DECL(int) PGMR3PhysRegisterRam(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, const char *pszDesc);
466	VMMR3DECL(int) PGMR3PhysChangeMemBalloon(PVM pVM, bool fInflate, unsigned cPages, RTGCPHYS *paPhysPage);
467	VMMR3DECL(int) PGMR3PhysWriteProtectRAM(PVM pVM);
468	VMMR3DECL(int) PGMR3PhysEnumDirtyFTPages(PVM pVM, PFNPGMENUMDIRTYFTPAGES pfnEnum, void *pvUser);
469	VMMR3DECL(uint32_t) PGMR3PhysGetRamRangeCount(PVM pVM);
470	VMMR3DECL(int) PGMR3PhysGetRange(PVM pVM, uint32_t iRange, PRTGCPHYS pGCPhysStart, PRTGCPHYS pGCPhysLast,
471	const char *ppszDesc, bool pfIsMmio);
472	VMMR3DECL(int) PGMR3QueryMemoryStats(PUVM pUVM, uint64_t pcbTotalMem, uint64_t pcbPrivateMem, uint64_t pcbSharedMem, uint64_t pcbZeroMem);
473	VMMR3DECL(int) PGMR3QueryGlobalMemoryStats(PUVM pUVM, uint64_t pcbAllocMem, uint64_t pcbFreeMem, uint64_t pcbBallonedMem, uint64_t pcbSharedMem);
474
475	VMMR3DECL(int) PGMR3PhysMMIORegister(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb,
476	R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnHandlerR3, RTR3PTR pvUserR3,
477	R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnHandlerR0, RTR0PTR pvUserR0,
478	RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnHandlerRC, RTRCPTR pvUserRC,
479	R3PTRTYPE(const char *) pszDesc);
480	VMMR3DECL(int) PGMR3PhysMMIODeregister(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb);
481	VMMR3DECL(int) PGMR3PhysMMIO2Register(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS cb, uint32_t fFlags, void *ppv, const char pszDesc);
482	VMMR3DECL(int) PGMR3PhysMMIO2Deregister(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion);
483	VMMR3DECL(int) PGMR3PhysMMIO2Map(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS GCPhys);
484	VMMR3DECL(int) PGMR3PhysMMIO2Unmap(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS GCPhys);
485	VMMR3DECL(bool) PGMR3PhysMMIO2IsBase(PVM pVM, PPDMDEVINS pDevIns, RTGCPHYS GCPhys);
486	VMMR3DECL(int) PGMR3PhysMMIO2GetHCPhys(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS off, PRTHCPHYS pHCPhys);
487	VMMR3DECL(int) PGMR3PhysMMIO2MapKernel(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS off, RTGCPHYS cb, const char *pszDesc, PRTR0PTR pR0Ptr);
488
489	/** @name PGMR3PhysRegisterRom flags.
490	* @{ */
491	/** Inidicates that ROM shadowing should be enabled. */
492	#define PGMPHYS_ROM_FLAGS_SHADOWED RT_BIT_32(0)
493	/** Indicates that what pvBinary points to won't go away
494	* and can be used for strictness checks. */
495	#define PGMPHYS_ROM_FLAGS_PERMANENT_BINARY RT_BIT_32(1)
496	/** @} */
497
498	VMMR3DECL(int) PGMR3PhysRomRegister(PVM pVM, PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTGCPHYS cb,
499	const void pvBinary, uint32_t cbBinary, uint32_t fFlags, const char pszDesc);
500	VMMR3DECL(int) PGMR3PhysRomProtect(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, PGMROMPROT enmProt);
501	VMMR3DECL(int) PGMR3PhysRegister(PVM pVM, void pvRam, RTGCPHYS GCPhys, size_t cb, unsigned fFlags, const SUPPAGE paPages, const char *pszDesc);
502	VMMDECL(void) PGMR3PhysSetA20(PVMCPU pVCpu, bool fEnable);
503	/** @name PGMR3MapPT flags.
504	* @{ */
505	/** The mapping may be unmapped later. The default is permanent mappings. */
506	#define PGMR3MAPPT_FLAGS_UNMAPPABLE RT_BIT(0)
507	/** @} */
508	VMMR3DECL(int) PGMR3MapPT(PVM pVM, RTGCPTR GCPtr, uint32_t cb, uint32_t fFlags, PFNPGMRELOCATE pfnRelocate, void pvUser, const char pszDesc);
509	VMMR3DECL(int) PGMR3UnmapPT(PVM pVM, RTGCPTR GCPtr);
510	VMMR3DECL(int) PGMR3FinalizeMappings(PVM pVM);
511	VMMR3DECL(int) PGMR3MappingsDisable(PVM pVM);
512	VMMR3DECL(int) PGMR3MappingsSize(PVM pVM, uint32_t *pcb);
513	VMMR3DECL(int) PGMR3MappingsFix(PVM pVM, RTGCPTR GCPtrBase, uint32_t cb);
514	VMMR3DECL(int) PGMR3MappingsUnfix(PVM pVM);
515	VMMR3DECL(bool) PGMR3MappingsNeedReFixing(PVM pVM);
516	#ifdef VBOX_WITH_RAW_MODE
517	VMMR3DECL(int) PGMR3MapIntermediate(PVM pVM, RTUINTPTR Addr, RTHCPHYS HCPhys, unsigned cbPages);
518	#endif
519	VMMR3DECL(int) PGMR3MapRead(PVM pVM, void *pvDst, RTGCPTR GCPtrSrc, size_t cb);
520
521	VMMR3DECL(int) PGMR3HandlerPhysicalRegister(PVM pVM, PGMPHYSHANDLERTYPE enmType, RTGCPHYS GCPhys, RTGCPHYS GCPhysLast,
522	PFNPGMR3PHYSHANDLER pfnHandlerR3, void *pvUserR3,
523	const char pszModR0, const char pszHandlerR0, RTR0PTR pvUserR0,
524	const char pszModRC, const char pszHandlerRC, RTRCPTR pvUserRC, const char *pszDesc);
525	VMMDECL(int) PGMR3HandlerVirtualRegisterEx(PVM pVM, PGMVIRTHANDLERTYPE enmType, RTGCPTR GCPtr, RTGCPTR GCPtrLast,
526	R3PTRTYPE(PFNPGMR3VIRTINVALIDATE) pfnInvalidateR3,
527	R3PTRTYPE(PFNPGMR3VIRTHANDLER) pfnHandlerR3,
528	RCPTRTYPE(PFNPGMRCVIRTHANDLER) pfnHandlerRC,
529	R3PTRTYPE(const char *) pszDesc);
530	VMMR3DECL(int) PGMR3HandlerVirtualRegister(PVM pVM, PGMVIRTHANDLERTYPE enmType, RTGCPTR GCPtr, RTGCPTR GCPtrLast,
531	PFNPGMR3VIRTINVALIDATE pfnInvalidateR3,
532	PFNPGMR3VIRTHANDLER pfnHandlerR3,
533	const char pszHandlerRC, const char pszModRC, const char *pszDesc);
534	VMMDECL(int) PGMHandlerVirtualChangeInvalidateCallback(PVM pVM, RTGCPTR GCPtr, R3PTRTYPE(PFNPGMR3VIRTINVALIDATE) pfnInvalidateR3);
535	VMMDECL(int) PGMHandlerVirtualDeregister(PVM pVM, RTGCPTR GCPtr);
536	VMMR3DECL(int) PGMR3PoolGrow(PVM pVM);
537
538	VMMR3DECL(int) PGMR3PhysTlbGCPhys2Ptr(PVM pVM, RTGCPHYS GCPhys, bool fWritable, void **ppv);
539	VMMR3DECL(uint8_t) PGMR3PhysReadU8(PVM pVM, RTGCPHYS GCPhys);
540	VMMR3DECL(uint16_t) PGMR3PhysReadU16(PVM pVM, RTGCPHYS GCPhys);
541	VMMR3DECL(uint32_t) PGMR3PhysReadU32(PVM pVM, RTGCPHYS GCPhys);
542	VMMR3DECL(uint64_t) PGMR3PhysReadU64(PVM pVM, RTGCPHYS GCPhys);
543	VMMR3DECL(void) PGMR3PhysWriteU8(PVM pVM, RTGCPHYS GCPhys, uint8_t Value);
544	VMMR3DECL(void) PGMR3PhysWriteU16(PVM pVM, RTGCPHYS GCPhys, uint16_t Value);
545	VMMR3DECL(void) PGMR3PhysWriteU32(PVM pVM, RTGCPHYS GCPhys, uint32_t Value);
546	VMMR3DECL(void) PGMR3PhysWriteU64(PVM pVM, RTGCPHYS GCPhys, uint64_t Value);
547	VMMR3DECL(int) PGMR3PhysReadExternal(PVM pVM, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead);
548	VMMR3DECL(int) PGMR3PhysWriteExternal(PVM pVM, RTGCPHYS GCPhys, const void pvBuf, size_t cbWrite, const char pszWho);
549	VMMR3DECL(int) PGMR3PhysGCPhys2CCPtrExternal(PVM pVM, RTGCPHYS GCPhys, void **ppv, PPGMPAGEMAPLOCK pLock);
550	VMMR3DECL(int) PGMR3PhysGCPhys2CCPtrReadOnlyExternal(PVM pVM, RTGCPHYS GCPhys, void const **ppv, PPGMPAGEMAPLOCK pLock);
551	VMMR3DECL(int) PGMR3PhysChunkMap(PVM pVM, uint32_t idChunk);
552	VMMR3DECL(void) PGMR3PhysChunkInvalidateTLB(PVM pVM);
553	VMMR3DECL(int) PGMR3PhysAllocateHandyPages(PVM pVM);
554	VMMR3DECL(int) PGMR3PhysAllocateLargeHandyPage(PVM pVM, RTGCPHYS GCPhys);
555
556	VMMR3DECL(int) PGMR3CheckIntegrity(PVM pVM);
557
558	VMMR3DECL(int) PGMR3DbgR3Ptr2GCPhys(PUVM pUVM, RTR3PTR R3Ptr, PRTGCPHYS pGCPhys);
559	VMMR3DECL(int) PGMR3DbgR3Ptr2HCPhys(PUVM pUVM, RTR3PTR R3Ptr, PRTHCPHYS pHCPhys);
560	VMMR3DECL(int) PGMR3DbgHCPhys2GCPhys(PUVM pUVM, RTHCPHYS HCPhys, PRTGCPHYS pGCPhys);
561	VMMR3_INT_DECL(int) PGMR3DbgReadGCPhys(PVM pVM, void pvDst, RTGCPHYS GCPhysSrc, size_t cb, uint32_t fFlags, size_t pcbRead);
562	VMMR3_INT_DECL(int) PGMR3DbgWriteGCPhys(PVM pVM, RTGCPHYS GCPhysDst, const void pvSrc, size_t cb, uint32_t fFlags, size_t pcbWritten);
563	VMMR3_INT_DECL(int) PGMR3DbgReadGCPtr(PVM pVM, void pvDst, RTGCPTR GCPtrSrc, size_t cb, uint32_t fFlags, size_t pcbRead);
564	VMMR3_INT_DECL(int) PGMR3DbgWriteGCPtr(PVM pVM, RTGCPTR GCPtrDst, void const pvSrc, size_t cb, uint32_t fFlags, size_t pcbWritten);
565	VMMR3_INT_DECL(int) PGMR3DbgScanPhysical(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cbRange, RTGCPHYS GCPhysAlign, const uint8_t *pabNeedle, size_t cbNeedle, PRTGCPHYS pGCPhysHit);
566	VMMR3_INT_DECL(int) PGMR3DbgScanVirtual(PVM pVM, PVMCPU pVCpu, RTGCPTR GCPtr, RTGCPTR cbRange, RTGCPTR GCPtrAlign, const uint8_t *pabNeedle, size_t cbNeedle, PRTGCUINTPTR pGCPhysHit);
567	VMMR3_INT_DECL(int) PGMR3DumpHierarchyShw(PVM pVM, uint64_t cr3, uint32_t fFlags, uint64_t u64FirstAddr, uint64_t u64LastAddr, uint32_t cMaxDepth, PCDBGFINFOHLP pHlp);
568	VMMR3_INT_DECL(int) PGMR3DumpHierarchyGst(PVM pVM, uint64_t cr3, uint32_t fFlags, RTGCPTR FirstAddr, RTGCPTR LastAddr, uint32_t cMaxDepth, PCDBGFINFOHLP pHlp);
569
570
571	/** @name Page sharing
572	* @{ */
573	VMMR3DECL(int) PGMR3SharedModuleRegister(PVM pVM, VBOXOSFAMILY enmGuestOS, char pszModuleName, char pszVersion,
574	RTGCPTR GCBaseAddr, uint32_t cbModule,
575	uint32_t cRegions, VMMDEVSHAREDREGIONDESC const *paRegions);
576	VMMR3DECL(int) PGMR3SharedModuleUnregister(PVM pVM, char pszModuleName, char pszVersion,
577	RTGCPTR GCBaseAddr, uint32_t cbModule);
578	VMMR3DECL(int) PGMR3SharedModuleCheckAll(PVM pVM);
579	VMMR3DECL(int) PGMR3SharedModuleGetPageState(PVM pVM, RTGCPTR GCPtrPage, bool pfShared, uint64_t pfPageFlags);
580	/** @} */
581
582	/** @} */
583	#endif /* IN_RING3 */
584
585	RT_C_DECLS_END
586
587	/** @} */
588	#endif
589

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source: vbox/trunk/include/VBox/vmm/pgm.h@ 45024

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