pgm.h@ 56954

Last change on this file since 56954 was 56627, checked in by vboxsync, 10 years ago
PGMPhys: The s_abPlayItSafe bits in dealing with PGMPAGETYPE_SPECIAL_ALIAS_MMIO pages screws up VBOX_STRICT assertions, triggering often with VBOX_WITH_2ND_IEM_STEP, so try the pvZeroPG now. Redefined what VINF_EM_DBG_STOP and VINF_EM_DBG_BREAKPOINT means when returned by access handlers and PGMPhysRead/Write APIs.
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 39.9 KB

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1	/** @file
2	* PGM - Page Monitor / Monitor.
3	*/
4
5	/*
6	* Copyright (C) 2006-2015 Oracle Corporation
7	*
8	* This file is part of VirtualBox Open Source Edition (OSE), as
9	* available from http://www.virtualbox.org. This file is free software;
10	* you can redistribute it and/or modify it under the terms of the GNU
11	* General Public License (GPL) as published by the Free Software
12	* Foundation, in version 2 as it comes in the "COPYING" file of the
13	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15	*
16	* The contents of this file may alternatively be used under the terms
17	* of the Common Development and Distribution License Version 1.0
18	* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19	* VirtualBox OSE distribution, in which case the provisions of the
20	* CDDL are applicable instead of those of the GPL.
21	*
22	* You may elect to license modified versions of this file under the
23	* terms and conditions of either the GPL or the CDDL or both.
24	*/
25
26	#ifndef ___VBox_vmm_pgm_h
27	#define ___VBox_vmm_pgm_h
28
29	#include <VBox/types.h>
30	#include <VBox/sup.h>
31	#include <VBox/vmm/vmapi.h>
32	#include <VBox/vmm/gmm.h> /* for PGMMREGISTERSHAREDMODULEREQ */
33	#include <iprt/x86.h>
34	#include <VBox/VMMDev.h> /* for VMMDEVSHAREDREGIONDESC */
35	#include <VBox/param.h>
36
37	RT_C_DECLS_BEGIN
38
39	/** @defgroup grp_pgm The Page Monitor / Manager API
40	* @{
41	*/
42
43	/**
44	* FNPGMRELOCATE callback mode.
45	*/
46	typedef enum PGMRELOCATECALL
47	{
48	/** The callback is for checking if the suggested address is suitable. */
49	PGMRELOCATECALL_SUGGEST = 1,
50	/** The callback is for executing the relocation. */
51	PGMRELOCATECALL_RELOCATE
52	} PGMRELOCATECALL;
53
54
55	/**
56	* Callback function which will be called when PGM is trying to find
57	* a new location for the mapping.
58	*
59	* The callback is called in two modes, 1) the check mode and 2) the relocate mode.
60	* In 1) the callback should say if it objects to a suggested new location. If it
61	* accepts the new location, it is called again for doing it's relocation.
62	*
63	*
64	* @returns true if the location is ok.
65	* @returns false if another location should be found.
66	* @param GCPtrOld The old virtual address.
67	* @param GCPtrNew The new virtual address.
68	* @param enmMode Used to indicate the callback mode.
69	* @param pvUser User argument.
70	* @remark The return value is no a failure indicator, it's an acceptance
71	* indicator. Relocation can not fail!
72	*/
73	typedef DECLCALLBACK(bool) FNPGMRELOCATE(PVM pVM, RTGCPTR GCPtrOld, RTGCPTR GCPtrNew, PGMRELOCATECALL enmMode, void *pvUser);
74	/** Pointer to a relocation callback function. */
75	typedef FNPGMRELOCATE *PFNPGMRELOCATE;
76
77
78	/**
79	* Memory access origin.
80	*/
81	typedef enum PGMACCESSORIGIN
82	{
83	/** Invalid zero value. */
84	PGMACCESSORIGIN_INVALID = 0,
85	/** IEM is access memory. */
86	PGMACCESSORIGIN_IEM,
87	/** HM is access memory. */
88	PGMACCESSORIGIN_HM,
89	/** Some device is access memory. */
90	PGMACCESSORIGIN_DEVICE,
91	/** Someone debugging is access memory. */
92	PGMACCESSORIGIN_DEBUGGER,
93	/** SELM is access memory. */
94	PGMACCESSORIGIN_SELM,
95	/** FTM is access memory. */
96	PGMACCESSORIGIN_FTM,
97	/** REM is access memory. */
98	PGMACCESSORIGIN_REM,
99	/** IOM is access memory. */
100	PGMACCESSORIGIN_IOM,
101	/** End of valid values. */
102	PGMACCESSORIGIN_END,
103	/** Type size hack. */
104	PGMACCESSORIGIN_32BIT_HACK = 0x7fffffff
105	} PGMACCESSORIGIN;
106
107
108	/**
109	* Physical page access handler kind.
110	*/
111	typedef enum PGMPHYSHANDLERKIND
112	{
113	/** MMIO range. Pages are not present, all access is done in interpreter or recompiler. */
114	PGMPHYSHANDLERKIND_MMIO = 1,
115	/** Handler all write access to a physical page range. */
116	PGMPHYSHANDLERKIND_WRITE,
117	/** Handler all access to a physical page range. */
118	PGMPHYSHANDLERKIND_ALL
119
120	} PGMPHYSHANDLERKIND;
121
122	/**
123	* Guest Access type
124	*/
125	typedef enum PGMACCESSTYPE
126	{
127	/** Read access. */
128	PGMACCESSTYPE_READ = 1,
129	/** Write access. */
130	PGMACCESSTYPE_WRITE
131	} PGMACCESSTYPE;
132
133
134	/** @def PGM_ALL_CB_DECL
135	* Macro for declaring a handler callback for all contexts. The handler
136	* callback is static in ring-3, and exported in RC and R0.
137	* @sa PGM_ALL_CB2_DECL.
138	*/
139	#if defined(IN_RC) \|\| defined(IN_RING0)
140	# ifdef __cplusplus
141	# define PGM_ALL_CB_DECL(type) extern "C" DECLEXPORT(type)
142	# else
143	# define PGM_ALL_CB_DECL(type) DECLEXPORT(type)
144	# endif
145	#else
146	# define PGM_ALL_CB_DECL(type) static type
147	#endif
148
149	/** @def PGM_ALL_CB2_DECL
150	* Macro for declaring a handler callback for all contexts. The handler
151	* callback is hidden in ring-3, and exported in RC and R0.
152	* @sa PGM_ALL_CB2_DECL.
153	*/
154	#if defined(IN_RC) \|\| defined(IN_RING0)
155	# ifdef __cplusplus
156	# define PGM_ALL_CB2_DECL(type) extern "C" DECLEXPORT(type)
157	# else
158	# define PGM_ALL_CB2_DECL(type) DECLEXPORT(type)
159	# endif
160	#else
161	# define PGM_ALL_CB2_DECL(type) DECLHIDDEN(type)
162	#endif
163
164
165	/**
166	* \#PF Handler callback for physical access handler ranges in RC and R0.
167	*
168	* @returns Strict VBox status code (appropriate for ring-0 and raw-mode).
169	* @param pVM VM Handle.
170	* @param pVCpu Pointer to the cross context CPU context for the
171	* calling EMT.
172	* @param uErrorCode CPU Error code.
173	* @param pRegFrame Trap register frame.
174	* NULL on DMA and other non CPU access.
175	* @param pvFault The fault address (cr2).
176	* @param GCPhysFault The GC physical address corresponding to pvFault.
177	* @param pvUser User argument.
178	* @thread EMT(pVCpu)
179	*/
180	typedef DECLCALLBACK(VBOXSTRICTRC) FNPGMRZPHYSPFHANDLER(PVM pVM, PVMCPU pVCpu, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame,
181	RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser);
182	/** Pointer to PGM access callback. */
183	typedef FNPGMRZPHYSPFHANDLER *PFNPGMRZPHYSPFHANDLER;
184
185
186	/**
187	* Access handler callback for physical access handler ranges.
188	*
189	* The handler can not raise any faults, it's mainly for monitoring write access
190	* to certain pages (like MMIO).
191	*
192	* @returns Strict VBox status code in ring-0 and raw-mode context, in ring-3
193	* the only supported informational status code is
194	* VINF_PGM_HANDLER_DO_DEFAULT.
195	* @retval VINF_SUCCESS if the handler have carried out the operation.
196	* @retval VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the
197	* access operation.
198	* @retval VINF_EM_XXX in ring-0 and raw-mode context.
199	*
200	* @param pVM VM Handle.
201	* @param pVCpu Pointer to the cross context CPU context for the
202	* calling EMT.
203	* @param GCPhys The physical address the guest is writing to.
204	* @param pvPhys The HC mapping of that address.
205	* @param pvBuf What the guest is reading/writing.
206	* @param cbBuf How much it's reading/writing.
207	* @param enmAccessType The access type.
208	* @param enmOrigin The origin of this call.
209	* @param pvUser User argument.
210	* @thread EMT(pVCpu)
211	*/
212	typedef DECLCALLBACK(VBOXSTRICTRC) FNPGMPHYSHANDLER(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void pvPhys, void pvBuf, size_t cbBuf,
213	PGMACCESSTYPE enmAccessType, PGMACCESSORIGIN enmOrigin, void *pvUser);
214	/** Pointer to PGM access callback. */
215	typedef FNPGMPHYSHANDLER *PFNPGMPHYSHANDLER;
216
217
218	/**
219	* Virtual access handler type.
220	*/
221	typedef enum PGMVIRTHANDLERKIND
222	{
223	/** Write access handled. */
224	PGMVIRTHANDLERKIND_WRITE = 1,
225	/** All access handled. */
226	PGMVIRTHANDLERKIND_ALL,
227	/** Hypervisor write access handled.
228	* This is used to catch the guest trying to write to LDT, TSS and any other
229	* system structure which the brain dead intel guys let unprivilegde code find. */
230	PGMVIRTHANDLERKIND_HYPERVISOR
231	} PGMVIRTHANDLERKIND;
232
233	/**
234	* \#PF handler callback for virtual access handler ranges, RC.
235	*
236	* Important to realize that a physical page in a range can have aliases, and
237	* for ALL and WRITE handlers these will also trigger.
238	*
239	* @returns Strict VBox status code (appropriate for raw-mode).
240	* @param pVM VM Handle.
241	* @param pVCpu Pointer to the cross context CPU context for the
242	* calling EMT.
243	* @param uErrorCode CPU Error code (X86_TRAP_PF_XXX).
244	* @param pRegFrame Trap register frame.
245	* @param pvFault The fault address (cr2).
246	* @param pvRange The base address of the handled virtual range.
247	* @param offRange The offset of the access into this range.
248	* (If it's a EIP range this is the EIP, if not it's pvFault.)
249	* @param pvUser User argument.
250	* @thread EMT(pVCpu)
251	*/
252	typedef DECLCALLBACK(VBOXSTRICTRC) FNPGMRCVIRTPFHANDLER(PVM pVM, PVMCPU pVCpu, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame,
253	RTGCPTR pvFault, RTGCPTR pvRange, uintptr_t offRange, void *pvUser);
254	/** Pointer to PGM access callback. */
255	typedef FNPGMRCVIRTPFHANDLER *PFNPGMRCVIRTPFHANDLER;
256
257	/**
258	* Access handler callback for virtual access handler ranges.
259	*
260	* Important to realize that a physical page in a range can have aliases, and
261	* for ALL and WRITE handlers these will also trigger.
262	*
263	* @returns VINF_SUCCESS if the handler have carried out the operation.
264	* @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
265	* @param pVM VM Handle.
266	* @param pVCpu Pointer to the cross context CPU context for the
267	* calling EMT.
268	* @param GCPtr The virtual address the guest is writing to. This
269	* is the registered address corresponding to the
270	* access, so no aliasing trouble here.
271	* @param pvPtr The HC mapping of that address.
272	* @param pvBuf What the guest is reading/writing.
273	* @param cbBuf How much it's reading/writing.
274	* @param enmAccessType The access type.
275	* @param enmOrigin Who is calling.
276	* @param pvUser User argument.
277	* @thread EMT(pVCpu)
278	*/
279	typedef DECLCALLBACK(VBOXSTRICTRC) FNPGMVIRTHANDLER(PVM pVM, PVMCPU pVCpu, RTGCPTR GCPtr, void pvPtr, void pvBuf, size_t cbBuf,
280	PGMACCESSTYPE enmAccessType, PGMACCESSORIGIN enmOrigin, void *pvUser);
281	/** Pointer to PGM access callback. */
282	typedef FNPGMVIRTHANDLER *PFNPGMVIRTHANDLER;
283
284	/**
285	* \#PF Handler callback for invalidation of virtual access handler ranges.
286	*
287	* @param pVM VM Handle.
288	* @param pVCpu Pointer to the cross context CPU context for the
289	* calling EMT.
290	* @param GCPtr The virtual address the guest has changed.
291	* @param pvUser User argument.
292	* @thread EMT(pVCpu)
293	*
294	* @todo FNPGMR3VIRTINVALIDATE will not actually be called! It was introduced
295	* in r13179 (1.1) and stopped working with r13806 (PGMPool merge,
296	* v1.2), exactly a month later.
297	*/
298	typedef DECLCALLBACK(int) FNPGMR3VIRTINVALIDATE(PVM pVM, PVMCPU pVCpu, RTGCPTR GCPtr, void *pvUser);
299	/** Pointer to PGM invalidation callback. */
300	typedef FNPGMR3VIRTINVALIDATE *PFNPGMR3VIRTINVALIDATE;
301
302
303	/**
304	* PGMR3PhysEnumDirtyFTPages callback for syncing dirty physical pages
305	*
306	* @param pVM VM Handle.
307	* @param GCPhys GC physical address
308	* @param pRange HC virtual address of the page(s)
309	* @param cbRange Size of the dirty range in bytes.
310	* @param pvUser User argument.
311	*/
312	typedef DECLCALLBACK(int) FNPGMENUMDIRTYFTPAGES(PVM pVM, RTGCPHYS GCPhys, uint8_t pRange, unsigned cbRange, void pvUser);
313	/** Pointer to PGMR3PhysEnumDirtyFTPages callback. */
314	typedef FNPGMENUMDIRTYFTPAGES *PFNPGMENUMDIRTYFTPAGES;
315
316
317	/**
318	* Paging mode.
319	*/
320	typedef enum PGMMODE
321	{
322	/** The usual invalid value. */
323	PGMMODE_INVALID = 0,
324	/** Real mode. */
325	PGMMODE_REAL,
326	/** Protected mode, no paging. */
327	PGMMODE_PROTECTED,
328	/** 32-bit paging. */
329	PGMMODE_32_BIT,
330	/** PAE paging. */
331	PGMMODE_PAE,
332	/** PAE paging with NX enabled. */
333	PGMMODE_PAE_NX,
334	/** 64-bit AMD paging (long mode). */
335	PGMMODE_AMD64,
336	/** 64-bit AMD paging (long mode) with NX enabled. */
337	PGMMODE_AMD64_NX,
338	/** Nested paging mode (shadow only; guest physical to host physical). */
339	PGMMODE_NESTED,
340	/** Extended paging (Intel) mode. */
341	PGMMODE_EPT,
342	/** The max number of modes */
343	PGMMODE_MAX,
344	/** 32bit hackishness. */
345	PGMMODE_32BIT_HACK = 0x7fffffff
346	} PGMMODE;
347
348	/** Macro for checking if the guest is using paging.
349	* @param enmMode PGMMODE_*.
350	* @remark ASSUMES certain order of the PGMMODE_* values.
351	*/
352	#define PGMMODE_WITH_PAGING(enmMode) ((enmMode) >= PGMMODE_32_BIT)
353
354	/** Macro for checking if it's one of the long mode modes.
355	* @param enmMode PGMMODE_*.
356	*/
357	#define PGMMODE_IS_LONG_MODE(enmMode) ((enmMode) == PGMMODE_AMD64_NX \|\| (enmMode) == PGMMODE_AMD64)
358
359	/**
360	* Is the ROM mapped (true) or is the shadow RAM mapped (false).
361	*
362	* @returns boolean.
363	* @param enmProt The PGMROMPROT value, must be valid.
364	*/
365	#define PGMROMPROT_IS_ROM(enmProt) \
366	( (enmProt) == PGMROMPROT_READ_ROM_WRITE_IGNORE \
367	\|\| (enmProt) == PGMROMPROT_READ_ROM_WRITE_RAM )
368
369
370	VMMDECL(bool) PGMIsLockOwner(PVM pVM);
371
372	VMMDECL(int) PGMRegisterStringFormatTypes(void);
373	VMMDECL(void) PGMDeregisterStringFormatTypes(void);
374	VMMDECL(RTHCPHYS) PGMGetHyperCR3(PVMCPU pVCpu);
375	VMMDECL(RTHCPHYS) PGMGetNestedCR3(PVMCPU pVCpu, PGMMODE enmShadowMode);
376	VMMDECL(RTHCPHYS) PGMGetInterHCCR3(PVM pVM);
377	VMMDECL(RTHCPHYS) PGMGetInterRCCR3(PVM pVM, PVMCPU pVCpu);
378	VMMDECL(RTHCPHYS) PGMGetInter32BitCR3(PVM pVM);
379	VMMDECL(RTHCPHYS) PGMGetInterPaeCR3(PVM pVM);
380	VMMDECL(RTHCPHYS) PGMGetInterAmd64CR3(PVM pVM);
381	VMMDECL(int) PGMTrap0eHandler(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault);
382	VMMDECL(int) PGMPrefetchPage(PVMCPU pVCpu, RTGCPTR GCPtrPage);
383	VMMDECL(int) PGMVerifyAccess(PVMCPU pVCpu, RTGCPTR Addr, uint32_t cbSize, uint32_t fAccess);
384	VMMDECL(int) PGMIsValidAccess(PVMCPU pVCpu, RTGCPTR Addr, uint32_t cbSize, uint32_t fAccess);
385	VMMDECL(VBOXSTRICTRC) PGMInterpretInstruction(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault);
386	VMMDECL(int) PGMMap(PVM pVM, RTGCPTR GCPtr, RTHCPHYS HCPhys, uint32_t cbPages, unsigned fFlags);
387	VMMDECL(int) PGMMapGetPage(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys);
388	VMMDECL(int) PGMMapSetPage(PVM pVM, RTGCPTR GCPtr, uint64_t cb, uint64_t fFlags);
389	VMMDECL(int) PGMMapModifyPage(PVM pVM, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask);
390	#ifndef IN_RING0
391	VMMDECL(bool) PGMMapHasConflicts(PVM pVM);
392	#endif
393	#ifdef VBOX_STRICT
394	VMMDECL(void) PGMMapCheck(PVM pVM);
395	#endif
396	VMMDECL(int) PGMShwGetPage(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys);
397	VMMDECL(int) PGMShwMakePageReadonly(PVMCPU pVCpu, RTGCPTR GCPtr, uint32_t fFlags);
398	VMMDECL(int) PGMShwMakePageWritable(PVMCPU pVCpu, RTGCPTR GCPtr, uint32_t fFlags);
399	VMMDECL(int) PGMShwMakePageNotPresent(PVMCPU pVCpu, RTGCPTR GCPtr, uint32_t fFlags);
400	/** @name Flags for PGMShwMakePageReadonly, PGMShwMakePageWritable and
401	* PGMShwMakePageNotPresent
402	* @{ */
403	/** The call is from an access handler for dealing with the a faulting write
404	* operation. The virtual address is within the same page. */
405	#define PGM_MK_PG_IS_WRITE_FAULT RT_BIT(0)
406	/** The page is an MMIO2. */
407	#define PGM_MK_PG_IS_MMIO2 RT_BIT(1)
408	/** @}*/
409	VMMDECL(int) PGMGstGetPage(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys);
410	VMMDECL(bool) PGMGstIsPagePresent(PVMCPU pVCpu, RTGCPTR GCPtr);
411	VMMDECL(int) PGMGstSetPage(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cb, uint64_t fFlags);
412	VMMDECL(int) PGMGstModifyPage(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask);
413	VMM_INT_DECL(int) PGMGstGetPaePdpes(PVMCPU pVCpu, PX86PDPE paPdpes);
414	VMM_INT_DECL(void) PGMGstUpdatePaePdpes(PVMCPU pVCpu, PCX86PDPE paPdpes);
415
416	VMMDECL(int) PGMInvalidatePage(PVMCPU pVCpu, RTGCPTR GCPtrPage);
417	VMMDECL(int) PGMFlushTLB(PVMCPU pVCpu, uint64_t cr3, bool fGlobal);
418	VMMDECL(int) PGMSyncCR3(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal);
419	VMMDECL(int) PGMUpdateCR3(PVMCPU pVCpu, uint64_t cr3);
420	VMMDECL(int) PGMChangeMode(PVMCPU pVCpu, uint64_t cr0, uint64_t cr4, uint64_t efer);
421	VMMDECL(void) PGMCr0WpEnabled(PVMCPU pVCpu);
422	VMMDECL(PGMMODE) PGMGetGuestMode(PVMCPU pVCpu);
423	VMMDECL(PGMMODE) PGMGetShadowMode(PVMCPU pVCpu);
424	VMMDECL(PGMMODE) PGMGetHostMode(PVM pVM);
425	VMMDECL(const char *) PGMGetModeName(PGMMODE enmMode);
426	VMM_INT_DECL(void) PGMNotifyNxeChanged(PVMCPU pVCpu, bool fNxe);
427	VMMDECL(bool) PGMHasDirtyPages(PVM pVM);
428
429	/** PGM physical access handler type registration handle (heap offset, valid
430	* cross contexts without needing fixing up). Callbacks and handler type is
431	* associated with this and it is shared by all handler registrations. */
432	typedef uint32_t PGMPHYSHANDLERTYPE;
433	/** Pointer to a PGM physical handler type registration handle. */
434	typedef PGMPHYSHANDLERTYPE *PPGMPHYSHANDLERTYPE;
435	/** NIL value for PGM physical access handler type handle. */
436	#define NIL_PGMPHYSHANDLERTYPE UINT32_MAX
437	VMMDECL(uint32_t) PGMHandlerPhysicalTypeRelease(PVM pVM, PGMPHYSHANDLERTYPE hType);
438	VMMDECL(uint32_t) PGMHandlerPhysicalTypeRetain(PVM pVM, PGMPHYSHANDLERTYPE hType);
439
440	VMMDECL(int) PGMHandlerPhysicalRegister(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS GCPhysLast, PGMPHYSHANDLERTYPE hType,
441	RTR3PTR pvUserR3, RTR0PTR pvUserR0, RTRCPTR pvUserRC,
442	R3PTRTYPE(const char *) pszDesc);
443	VMMDECL(int) PGMHandlerPhysicalModify(PVM pVM, RTGCPHYS GCPhysCurrent, RTGCPHYS GCPhys, RTGCPHYS GCPhysLast);
444	VMMDECL(int) PGMHandlerPhysicalDeregister(PVM pVM, RTGCPHYS GCPhys);
445	VMMDECL(int) PGMHandlerPhysicalChangeUserArgs(PVM pVM, RTGCPHYS GCPhys, RTR3PTR pvUserR3, RTR0PTR pvUserR0, RTRCPTR pvUserRC);
446	VMMDECL(int) PGMHandlerPhysicalSplit(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS GCPhysSplit);
447	VMMDECL(int) PGMHandlerPhysicalJoin(PVM pVM, RTGCPHYS GCPhys1, RTGCPHYS GCPhys2);
448	VMMDECL(int) PGMHandlerPhysicalPageTempOff(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS GCPhysPage);
449	VMMDECL(int) PGMHandlerPhysicalPageAlias(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS GCPhysPage, RTGCPHYS GCPhysPageRemap);
450	VMMDECL(int) PGMHandlerPhysicalPageAliasHC(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS GCPhysPage, RTHCPHYS HCPhysPageRemap);
451	VMMDECL(int) PGMHandlerPhysicalReset(PVM pVM, RTGCPHYS GCPhys);
452	VMMDECL(bool) PGMHandlerPhysicalIsRegistered(PVM pVM, RTGCPHYS GCPhys);
453
454	/** PGM virtual access handler type registration handle (heap offset, valid
455	* cross contexts without needing fixing up). Callbacks and handler type is
456	* associated with this and it is shared by all handler registrations. */
457	typedef uint32_t PGMVIRTHANDLERTYPE;
458	/** Pointer to a PGM virtual handler type registration handle. */
459	typedef PGMVIRTHANDLERTYPE *PPGMVIRTHANDLERTYPE;
460	/** NIL value for PGM virtual access handler type handle. */
461	#define NIL_PGMVIRTHANDLERTYPE UINT32_MAX
462	#ifdef VBOX_WITH_RAW_MODE
463	VMM_INT_DECL(uint32_t) PGMHandlerVirtualTypeRelease(PVM pVM, PGMVIRTHANDLERTYPE hType);
464	VMM_INT_DECL(uint32_t) PGMHandlerVirtualTypeRetain(PVM pVM, PGMVIRTHANDLERTYPE hType);
465	VMM_INT_DECL(bool) PGMHandlerVirtualIsRegistered(PVM pVM, RTGCPTR GCPtr);
466	#endif
467
468
469	/**
470	* Page type.
471	*
472	* @remarks This enum has to fit in a 3-bit field (see PGMPAGE::u3Type).
473	* @remarks This is used in the saved state, so changes to it requires bumping
474	* the saved state version.
475	* @todo So, convert to \#defines!
476	*/
477	typedef enum PGMPAGETYPE
478	{
479	/** The usual invalid zero entry. */
480	PGMPAGETYPE_INVALID = 0,
481	/** RAM page. (RWX) */
482	PGMPAGETYPE_RAM,
483	/** MMIO2 page. (RWX) */
484	PGMPAGETYPE_MMIO2,
485	/** MMIO2 page aliased over an MMIO page. (RWX)
486	* See PGMHandlerPhysicalPageAlias(). */
487	PGMPAGETYPE_MMIO2_ALIAS_MMIO,
488	/** Special page aliased over an MMIO page. (RWX)
489	* See PGMHandlerPhysicalPageAliasHC(), but this is generally only used for
490	* VT-x's APIC access page at the moment. Treated as MMIO by everyone except
491	* the shadow paging code. */
492	PGMPAGETYPE_SPECIAL_ALIAS_MMIO,
493	/** Shadowed ROM. (RWX) */
494	PGMPAGETYPE_ROM_SHADOW,
495	/** ROM page. (R-X) */
496	PGMPAGETYPE_ROM,
497	/** MMIO page. (---) */
498	PGMPAGETYPE_MMIO,
499	/** End of valid entries. */
500	PGMPAGETYPE_END
501	} PGMPAGETYPE;
502	AssertCompile(PGMPAGETYPE_END == 8);
503
504	VMM_INT_DECL(PGMPAGETYPE) PGMPhysGetPageType(PVM pVM, RTGCPHYS GCPhys);
505
506	VMM_INT_DECL(int) PGMPhysGCPhys2HCPhys(PVM pVM, RTGCPHYS GCPhys, PRTHCPHYS pHCPhys);
507	VMM_INT_DECL(int) PGMPhysGCPtr2HCPhys(PVMCPU pVCpu, RTGCPTR GCPtr, PRTHCPHYS pHCPhys);
508	VMM_INT_DECL(int) PGMPhysGCPhys2CCPtr(PVM pVM, RTGCPHYS GCPhys, void **ppv, PPGMPAGEMAPLOCK pLock);
509	VMM_INT_DECL(int) PGMPhysGCPhys2CCPtrReadOnly(PVM pVM, RTGCPHYS GCPhys, void const **ppv, PPGMPAGEMAPLOCK pLock);
510	VMM_INT_DECL(int) PGMPhysGCPtr2CCPtr(PVMCPU pVCpu, RTGCPTR GCPtr, void **ppv, PPGMPAGEMAPLOCK pLock);
511	VMM_INT_DECL(int) PGMPhysGCPtr2CCPtrReadOnly(PVMCPU pVCpu, RTGCPTR GCPtr, void const **ppv, PPGMPAGEMAPLOCK pLock);
512
513	VMMDECL(bool) PGMPhysIsA20Enabled(PVMCPU pVCpu);
514	VMMDECL(bool) PGMPhysIsGCPhysValid(PVM pVM, RTGCPHYS GCPhys);
515	VMMDECL(bool) PGMPhysIsGCPhysNormal(PVM pVM, RTGCPHYS GCPhys);
516	VMMDECL(int) PGMPhysGCPtr2GCPhys(PVMCPU pVCpu, RTGCPTR GCPtr, PRTGCPHYS pGCPhys);
517	VMMDECL(void) PGMPhysReleasePageMappingLock(PVM pVM, PPGMPAGEMAPLOCK pLock);
518
519	/** @def PGM_PHYS_RW_IS_SUCCESS
520	* Check whether a PGMPhysRead, PGMPhysWrite, PGMPhysReadGCPtr or
521	* PGMPhysWriteGCPtr call completed the given task.
522	*
523	* @returns true if completed, false if not.
524	* @param a_rcStrict The status code.
525	* @sa IOM_SUCCESS
526	*/
527	#ifdef IN_RING3
528	# define PGM_PHYS_RW_IS_SUCCESS(a_rcStrict) \
529	( (a_rcStrict) == VINF_SUCCESS \
530	\|\| (a_rcStrict) == VINF_EM_DBG_STOP \
531	\|\| (a_rcStrict) == VINF_EM_DBG_BREAKPOINT \
532	)
533	#elif defined(IN_RING0)
534	# define PGM_PHYS_RW_IS_SUCCESS(a_rcStrict) \
535	( (a_rcStrict) == VINF_SUCCESS \
536	\|\| (a_rcStrict) == VINF_EM_OFF \
537	\|\| (a_rcStrict) == VINF_EM_SUSPEND \
538	\|\| (a_rcStrict) == VINF_EM_RESET \
539	\|\| (a_rcStrict) == VINF_EM_HALT \
540	\|\| (a_rcStrict) == VINF_EM_DBG_STOP \
541	\|\| (a_rcStrict) == VINF_EM_DBG_BREAKPOINT \
542	)
543	#elif defined(IN_RC)
544	# define PGM_PHYS_RW_IS_SUCCESS(a_rcStrict) \
545	( (a_rcStrict) == VINF_SUCCESS \
546	\|\| (a_rcStrict) == VINF_EM_OFF \
547	\|\| (a_rcStrict) == VINF_EM_SUSPEND \
548	\|\| (a_rcStrict) == VINF_EM_RESET \
549	\|\| (a_rcStrict) == VINF_EM_HALT \
550	\|\| (a_rcStrict) == VINF_SELM_SYNC_GDT \
551	\|\| (a_rcStrict) == VINF_EM_RAW_EMULATE_INSTR_GDT_FAULT \
552	\|\| (a_rcStrict) == VINF_EM_DBG_STOP \
553	\|\| (a_rcStrict) == VINF_EM_DBG_BREAKPOINT \
554	)
555	#endif
556	/** @def PGM_PHYS_RW_DO_UPDATE_STRICT_RC
557	* Updates the return code with a new result.
558	*
559	* Both status codes must be successes according to PGM_PHYS_RW_IS_SUCCESS.
560	*
561	* @param a_rcStrict The current return code, to be updated.
562	* @param a_rcStrict2 The new return code to merge in.
563	*/
564	#ifdef IN_RING3
565	# define PGM_PHYS_RW_DO_UPDATE_STRICT_RC(a_rcStrict, a_rcStrict2) \
566	do { \
567	Assert(rcStrict == VINF_SUCCESS); \
568	Assert(rcStrict2 == VINF_SUCCESS); \
569	} while (0)
570	#elif defined(IN_RING0)
571	# define PGM_PHYS_RW_DO_UPDATE_STRICT_RC(a_rcStrict, a_rcStrict2) \
572	do { \
573	Assert(PGM_PHYS_RW_IS_SUCCESS(rcStrict)); \
574	Assert(PGM_PHYS_RW_IS_SUCCESS(rcStrict2)); \
575	if ((a_rcStrict2) == VINF_SUCCESS \|\| (a_rcStrict) == (a_rcStrict2)) \
576	{ /* likely */ } \
577	else if ( (a_rcStrict) == VINF_SUCCESS \
578	\|\| (a_rcStrict) > (a_rcStrict2)) \
579	(a_rcStrict) = (a_rcStrict2); \
580	} while (0)
581	#elif defined(IN_RC)
582	# define PGM_PHYS_RW_DO_UPDATE_STRICT_RC(a_rcStrict, a_rcStrict2) \
583	do { \
584	Assert(PGM_PHYS_RW_IS_SUCCESS(rcStrict)); \
585	Assert(PGM_PHYS_RW_IS_SUCCESS(rcStrict2)); \
586	AssertCompile(VINF_SELM_SYNC_GDT > VINF_EM_LAST); \
587	AssertCompile(VINF_EM_RAW_EMULATE_INSTR_GDT_FAULT > VINF_EM_LAST); \
588	AssertCompile(VINF_EM_RAW_EMULATE_INSTR_GDT_FAULT < VINF_SELM_SYNC_GDT); \
589	if ((a_rcStrict2) == VINF_SUCCESS \|\| (a_rcStrict) == (a_rcStrict2)) \
590	{ /* likely */ } \
591	else if ( (a_rcStrict) == VINF_SUCCESS \
592	\|\| ( (a_rcStrict) > (a_rcStrict2) \
593	&& ( (a_rcStrict2) <= VINF_EM_RESET \
594	\|\| (a_rcStrict) != VINF_EM_RAW_EMULATE_INSTR_GDT_FAULT) ) \
595	\|\| ( (a_rcStrict2) == VINF_EM_RAW_EMULATE_INSTR_GDT_FAULT \
596	&& (a_rcStrict) > VINF_EM_RESET) ) \
597	(a_rcStrict) = (a_rcStrict2); \
598	} while (0)
599	#endif
600
601	VMMDECL(VBOXSTRICTRC) PGMPhysRead(PVM pVM, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead, PGMACCESSORIGIN enmOrigin);
602	VMMDECL(VBOXSTRICTRC) PGMPhysWrite(PVM pVM, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite, PGMACCESSORIGIN enmOrigin);
603	VMMDECL(VBOXSTRICTRC) PGMPhysReadGCPtr(PVMCPU pVCpu, void *pvDst, RTGCPTR GCPtrSrc, size_t cb, PGMACCESSORIGIN enmOrigin);
604	VMMDECL(VBOXSTRICTRC) PGMPhysWriteGCPtr(PVMCPU pVCpu, RTGCPTR GCPtrDst, const void *pvSrc, size_t cb, PGMACCESSORIGIN enmOrigin);
605
606	VMMDECL(int) PGMPhysSimpleReadGCPhys(PVM pVM, void *pvDst, RTGCPHYS GCPhysSrc, size_t cb);
607	VMMDECL(int) PGMPhysSimpleWriteGCPhys(PVM pVM, RTGCPHYS GCPhysDst, const void *pvSrc, size_t cb);
608	VMMDECL(int) PGMPhysSimpleReadGCPtr(PVMCPU pVCpu, void *pvDst, RTGCPTR GCPtrSrc, size_t cb);
609	VMMDECL(int) PGMPhysSimpleWriteGCPtr(PVMCPU pVCpu, RTGCPTR GCPtrDst, const void *pvSrc, size_t cb);
610	VMMDECL(int) PGMPhysSimpleDirtyWriteGCPtr(PVMCPU pVCpu, RTGCPTR GCPtrDst, const void *pvSrc, size_t cb);
611	VMMDECL(int) PGMPhysInterpretedRead(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, void *pvDst, RTGCPTR GCPtrSrc, size_t cb);
612	VMMDECL(int) PGMPhysInterpretedReadNoHandlers(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, void *pvDst, RTGCUINTPTR GCPtrSrc, size_t cb, bool fRaiseTrap);
613	VMMDECL(int) PGMPhysInterpretedWriteNoHandlers(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, RTGCPTR GCPtrDst, void const *pvSrc, size_t cb, bool fRaiseTrap);
614	VMM_INT_DECL(int) PGMPhysIemGCPhys2Ptr(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, bool fWritable, bool fByPassHandlers, void **ppv, PPGMPAGEMAPLOCK pLock);
615	VMM_INT_DECL(int) PGMPhysIemQueryAccess(PVM pVM, RTGCPHYS GCPhys, bool fWritable, bool fByPassHandlers);
616
617	#ifdef VBOX_STRICT
618	VMMDECL(unsigned) PGMAssertHandlerAndFlagsInSync(PVM pVM);
619	VMMDECL(unsigned) PGMAssertNoMappingConflicts(PVM pVM);
620	VMMDECL(unsigned) PGMAssertCR3(PVM pVM, PVMCPU pVCpu, uint64_t cr3, uint64_t cr4);
621	#endif /* VBOX_STRICT */
622
623	#if defined(IN_RC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE)
624	VMMDECL(void) PGMRZDynMapStartAutoSet(PVMCPU pVCpu);
625	VMMDECL(void) PGMRZDynMapReleaseAutoSet(PVMCPU pVCpu);
626	VMMDECL(void) PGMRZDynMapFlushAutoSet(PVMCPU pVCpu);
627	VMMDECL(uint32_t) PGMRZDynMapPushAutoSubset(PVMCPU pVCpu);
628	VMMDECL(void) PGMRZDynMapPopAutoSubset(PVMCPU pVCpu, uint32_t iPrevSubset);
629	#endif
630
631	VMMDECL(int) PGMSetLargePageUsage(PVM pVM, bool fUseLargePages);
632
633	/**
634	* Query large page usage state
635	*
636	* @returns 0 - disabled, 1 - enabled
637	* @param pVM The VM to operate on.
638	*/
639	#define PGMIsUsingLargePages(pVM) ((pVM)->fUseLargePages)
640
641
642	#ifdef IN_RC
643	/** @defgroup grp_pgm_gc The PGM Guest Context API
644	* @{
645	*/
646	VMMRCDECL(int) PGMRCDynMapInit(PVM pVM);
647	/** @} */
648	#endif /* IN_RC */
649
650
651	#ifdef IN_RING0
652	/** @defgroup grp_pgm_r0 The PGM Host Context Ring-0 API
653	* @{
654	*/
655	VMMR0_INT_DECL(int) PGMR0PhysAllocateHandyPages(PVM pVM, PVMCPU pVCpu);
656	VMMR0_INT_DECL(int) PGMR0PhysFlushHandyPages(PVM pVM, PVMCPU pVCpu);
657	VMMR0_INT_DECL(int) PGMR0PhysAllocateLargeHandyPage(PVM pVM, PVMCPU pVCpu);
658	VMMR0_INT_DECL(int) PGMR0PhysSetupIommu(PVM pVM);
659	VMMR0DECL(int) PGMR0SharedModuleCheck(PVM pVM, PGVM pGVM, VMCPUID idCpu, PGMMSHAREDMODULE pModule, PCRTGCPTR64 paRegionsGCPtrs);
660	VMMR0DECL(int) PGMR0Trap0eHandlerNestedPaging(PVM pVM, PVMCPU pVCpu, PGMMODE enmShwPagingMode, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPHYS pvFault);
661	VMMR0DECL(VBOXSTRICTRC) PGMR0Trap0eHandlerNPMisconfig(PVM pVM, PVMCPU pVCpu, PGMMODE enmShwPagingMode, PCPUMCTXCORE pRegFrame, RTGCPHYS GCPhysFault, uint32_t uErr);
662	# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
663	VMMR0DECL(int) PGMR0DynMapInit(void);
664	VMMR0DECL(void) PGMR0DynMapTerm(void);
665	VMMR0DECL(int) PGMR0DynMapInitVM(PVM pVM);
666	VMMR0DECL(void) PGMR0DynMapTermVM(PVM pVM);
667	VMMR0DECL(int) PGMR0DynMapAssertIntegrity(void);
668	VMMR0DECL(bool) PGMR0DynMapStartOrMigrateAutoSet(PVMCPU pVCpu);
669	VMMR0DECL(void) PGMR0DynMapMigrateAutoSet(PVMCPU pVCpu);
670	# endif
671	/** @} */
672	#endif /* IN_RING0 */
673
674
675
676	#ifdef IN_RING3
677	/** @defgroup grp_pgm_r3 The PGM Host Context Ring-3 API
678	* @{
679	*/
680	VMMR3DECL(int) PGMR3Init(PVM pVM);
681	VMMR3DECL(int) PGMR3InitDynMap(PVM pVM);
682	VMMR3DECL(int) PGMR3InitFinalize(PVM pVM);
683	VMMR3_INT_DECL(int) PGMR3InitCompleted(PVM pVM, VMINITCOMPLETED enmWhat);
684	VMMR3DECL(void) PGMR3Relocate(PVM pVM, RTGCINTPTR offDelta);
685	VMMR3DECL(void) PGMR3ResetCpu(PVM pVM, PVMCPU pVCpu);
686	VMMR3_INT_DECL(void) PGMR3Reset(PVM pVM);
687	VMMR3_INT_DECL(void) PGMR3ResetNoMorePhysWritesFlag(PVM pVM);
688	VMMR3_INT_DECL(void) PGMR3MemSetup(PVM pVM, bool fReset);
689	VMMR3DECL(int) PGMR3Term(PVM pVM);
690	VMMR3DECL(int) PGMR3LockCall(PVM pVM);
691	VMMR3DECL(int) PGMR3ChangeMode(PVM pVM, PVMCPU pVCpu, PGMMODE enmGuestMode);
692
693	VMMR3DECL(int) PGMR3PhysRegisterRam(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, const char *pszDesc);
694	VMMR3DECL(int) PGMR3PhysChangeMemBalloon(PVM pVM, bool fInflate, unsigned cPages, RTGCPHYS *paPhysPage);
695	VMMR3DECL(int) PGMR3PhysWriteProtectRAM(PVM pVM);
696	VMMR3DECL(int) PGMR3PhysEnumDirtyFTPages(PVM pVM, PFNPGMENUMDIRTYFTPAGES pfnEnum, void *pvUser);
697	VMMR3DECL(uint32_t) PGMR3PhysGetRamRangeCount(PVM pVM);
698	VMMR3DECL(int) PGMR3PhysGetRange(PVM pVM, uint32_t iRange, PRTGCPHYS pGCPhysStart, PRTGCPHYS pGCPhysLast,
699	const char *ppszDesc, bool pfIsMmio);
700	VMMR3DECL(int) PGMR3QueryMemoryStats(PUVM pUVM, uint64_t pcbTotalMem, uint64_t pcbPrivateMem, uint64_t pcbSharedMem, uint64_t pcbZeroMem);
701	VMMR3DECL(int) PGMR3QueryGlobalMemoryStats(PUVM pUVM, uint64_t pcbAllocMem, uint64_t pcbFreeMem, uint64_t pcbBallonedMem, uint64_t pcbSharedMem);
702
703	VMMR3DECL(int) PGMR3PhysMMIORegister(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, PGMPHYSHANDLERTYPE hType,
704	RTR3PTR pvUserR3, RTR0PTR pvUserR0, RTRCPTR pvUserRC, const char *pszDesc);
705	VMMR3DECL(int) PGMR3PhysMMIODeregister(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb);
706	VMMR3DECL(int) PGMR3PhysMMIO2Register(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS cb, uint32_t fFlags, void *ppv, const char pszDesc);
707	VMMR3DECL(int) PGMR3PhysMMIO2Deregister(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion);
708	VMMR3DECL(int) PGMR3PhysMMIO2Map(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS GCPhys);
709	VMMR3DECL(int) PGMR3PhysMMIO2Unmap(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS GCPhys);
710	VMMR3DECL(bool) PGMR3PhysMMIO2IsBase(PVM pVM, PPDMDEVINS pDevIns, RTGCPHYS GCPhys);
711	VMMR3DECL(int) PGMR3PhysMMIO2GetHCPhys(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS off, PRTHCPHYS pHCPhys);
712	VMMR3DECL(int) PGMR3PhysMMIO2MapKernel(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS off, RTGCPHYS cb, const char *pszDesc, PRTR0PTR pR0Ptr);
713
714	/** @name PGMR3PhysRegisterRom flags.
715	* @{ */
716	/** Inidicates that ROM shadowing should be enabled. */
717	#define PGMPHYS_ROM_FLAGS_SHADOWED RT_BIT_32(0)
718	/** Indicates that what pvBinary points to won't go away
719	* and can be used for strictness checks. */
720	#define PGMPHYS_ROM_FLAGS_PERMANENT_BINARY RT_BIT_32(1)
721	/** @} */
722
723	VMMR3DECL(int) PGMR3PhysRomRegister(PVM pVM, PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTGCPHYS cb,
724	const void pvBinary, uint32_t cbBinary, uint32_t fFlags, const char pszDesc);
725	VMMR3DECL(int) PGMR3PhysRomProtect(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, PGMROMPROT enmProt);
726	VMMR3DECL(int) PGMR3PhysRegister(PVM pVM, void pvRam, RTGCPHYS GCPhys, size_t cb, unsigned fFlags, const SUPPAGE paPages, const char *pszDesc);
727	VMMDECL(void) PGMR3PhysSetA20(PVMCPU pVCpu, bool fEnable);
728	/** @name PGMR3MapPT flags.
729	* @{ */
730	/** The mapping may be unmapped later. The default is permanent mappings. */
731	#define PGMR3MAPPT_FLAGS_UNMAPPABLE RT_BIT(0)
732	/** @} */
733	VMMR3DECL(int) PGMR3MapPT(PVM pVM, RTGCPTR GCPtr, uint32_t cb, uint32_t fFlags, PFNPGMRELOCATE pfnRelocate, void pvUser, const char pszDesc);
734	VMMR3DECL(int) PGMR3UnmapPT(PVM pVM, RTGCPTR GCPtr);
735	VMMR3DECL(int) PGMR3FinalizeMappings(PVM pVM);
736	VMMR3DECL(int) PGMR3MappingsSize(PVM pVM, uint32_t *pcb);
737	VMMR3DECL(int) PGMR3MappingsFix(PVM pVM, RTGCPTR GCPtrBase, uint32_t cb);
738	VMMR3DECL(int) PGMR3MappingsUnfix(PVM pVM);
739	VMMR3DECL(bool) PGMR3MappingsNeedReFixing(PVM pVM);
740	#if defined(VBOX_WITH_RAW_MODE) \|\| (HC_ARCH_BITS != 64 && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL))
741	VMMR3DECL(int) PGMR3MapIntermediate(PVM pVM, RTUINTPTR Addr, RTHCPHYS HCPhys, unsigned cbPages);
742	#endif
743	VMMR3DECL(int) PGMR3MapRead(PVM pVM, void *pvDst, RTGCPTR GCPtrSrc, size_t cb);
744
745	VMMR3_INT_DECL(int) PGMR3HandlerPhysicalTypeRegisterEx(PVM pVM, PGMPHYSHANDLERKIND enmKind,
746	PFNPGMPHYSHANDLER pfnHandlerR3,
747	R0PTRTYPE(PFNPGMPHYSHANDLER) pfnHandlerR0,
748	R0PTRTYPE(PFNPGMRZPHYSPFHANDLER) pfnPfHandlerR0,
749	RCPTRTYPE(PFNPGMPHYSHANDLER) pfnHandlerRC,
750	RCPTRTYPE(PFNPGMRZPHYSPFHANDLER) pfnPfHandlerRC,
751	const char *pszDesc, PPGMPHYSHANDLERTYPE phType);
752	VMMR3DECL(int) PGMR3HandlerPhysicalTypeRegister(PVM pVM, PGMPHYSHANDLERKIND enmKind,
753	R3PTRTYPE(PFNPGMPHYSHANDLER) pfnHandlerR3,
754	const char pszModR0, const char pszHandlerR0, const char *pszPfHandlerR0,
755	const char pszModRC, const char pszHandlerRC, const char *pszPfHandlerRC,
756	const char *pszDesc,
757	PPGMPHYSHANDLERTYPE phType);
758	#ifdef VBOX_WITH_RAW_MODE
759	VMMR3_INT_DECL(int) PGMR3HandlerVirtualTypeRegisterEx(PVM pVM, PGMVIRTHANDLERKIND enmKind, bool fRelocUserRC,
760	PFNPGMR3VIRTINVALIDATE pfnInvalidateR3,
761	PFNPGMVIRTHANDLER pfnHandlerR3,
762	RCPTRTYPE(FNPGMVIRTHANDLER) pfnHandlerRC,
763	RCPTRTYPE(FNPGMRCVIRTPFHANDLER) pfnPfHandlerRC,
764	const char *pszDesc, PPGMVIRTHANDLERTYPE phType);
765	VMMR3_INT_DECL(int) PGMR3HandlerVirtualTypeRegister(PVM pVM, PGMVIRTHANDLERKIND enmKind, bool fRelocUserRC,
766	PFNPGMR3VIRTINVALIDATE pfnInvalidateR3,
767	PFNPGMVIRTHANDLER pfnHandlerR3,
768	const char pszHandlerRC, const char pszPfHandlerRC, const char *pszDesc,
769	PPGMVIRTHANDLERTYPE phType);
770	VMMR3_INT_DECL(int) PGMR3HandlerVirtualRegister(PVM pVM, PVMCPU pVCpu, PGMVIRTHANDLERTYPE hType, RTGCPTR GCPtr,
771	RTGCPTR GCPtrLast, void pvUserR3, RTRCPTR pvUserRC, const char pszDesc);
772	VMMR3_INT_DECL(int) PGMHandlerVirtualChangeType(PVM pVM, RTGCPTR GCPtr, PGMVIRTHANDLERTYPE hNewType);
773	VMMR3_INT_DECL(int) PGMHandlerVirtualDeregister(PVM pVM, PVMCPU pVCpu, RTGCPTR GCPtr, bool fHypervisor);
774	#endif
775	VMMR3DECL(int) PGMR3PoolGrow(PVM pVM);
776
777	VMMR3DECL(int) PGMR3PhysTlbGCPhys2Ptr(PVM pVM, RTGCPHYS GCPhys, bool fWritable, void **ppv);
778	VMMR3DECL(uint8_t) PGMR3PhysReadU8(PVM pVM, RTGCPHYS GCPhys, PGMACCESSORIGIN enmOrigin);
779	VMMR3DECL(uint16_t) PGMR3PhysReadU16(PVM pVM, RTGCPHYS GCPhys, PGMACCESSORIGIN enmOrigin);
780	VMMR3DECL(uint32_t) PGMR3PhysReadU32(PVM pVM, RTGCPHYS GCPhys, PGMACCESSORIGIN enmOrigin);
781	VMMR3DECL(uint64_t) PGMR3PhysReadU64(PVM pVM, RTGCPHYS GCPhys, PGMACCESSORIGIN enmOrigin);
782	VMMR3DECL(void) PGMR3PhysWriteU8(PVM pVM, RTGCPHYS GCPhys, uint8_t Value, PGMACCESSORIGIN enmOrigin);
783	VMMR3DECL(void) PGMR3PhysWriteU16(PVM pVM, RTGCPHYS GCPhys, uint16_t Value, PGMACCESSORIGIN enmOrigin);
784	VMMR3DECL(void) PGMR3PhysWriteU32(PVM pVM, RTGCPHYS GCPhys, uint32_t Value, PGMACCESSORIGIN enmOrigin);
785	VMMR3DECL(void) PGMR3PhysWriteU64(PVM pVM, RTGCPHYS GCPhys, uint64_t Value, PGMACCESSORIGIN enmOrigin);
786	VMMR3DECL(int) PGMR3PhysReadExternal(PVM pVM, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead, PGMACCESSORIGIN enmOrigin);
787	VMMR3DECL(int) PGMR3PhysWriteExternal(PVM pVM, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite, PGMACCESSORIGIN enmOrigin);
788	VMMR3DECL(int) PGMR3PhysGCPhys2CCPtrExternal(PVM pVM, RTGCPHYS GCPhys, void **ppv, PPGMPAGEMAPLOCK pLock);
789	VMMR3DECL(int) PGMR3PhysGCPhys2CCPtrReadOnlyExternal(PVM pVM, RTGCPHYS GCPhys, void const **ppv, PPGMPAGEMAPLOCK pLock);
790	VMMR3DECL(int) PGMR3PhysChunkMap(PVM pVM, uint32_t idChunk);
791	VMMR3DECL(void) PGMR3PhysChunkInvalidateTLB(PVM pVM);
792	VMMR3DECL(int) PGMR3PhysAllocateHandyPages(PVM pVM);
793	VMMR3DECL(int) PGMR3PhysAllocateLargeHandyPage(PVM pVM, RTGCPHYS GCPhys);
794
795	VMMR3DECL(int) PGMR3CheckIntegrity(PVM pVM);
796
797	VMMR3DECL(int) PGMR3DbgR3Ptr2GCPhys(PUVM pUVM, RTR3PTR R3Ptr, PRTGCPHYS pGCPhys);
798	VMMR3DECL(int) PGMR3DbgR3Ptr2HCPhys(PUVM pUVM, RTR3PTR R3Ptr, PRTHCPHYS pHCPhys);
799	VMMR3DECL(int) PGMR3DbgHCPhys2GCPhys(PUVM pUVM, RTHCPHYS HCPhys, PRTGCPHYS pGCPhys);
800	VMMR3_INT_DECL(int) PGMR3DbgReadGCPhys(PVM pVM, void pvDst, RTGCPHYS GCPhysSrc, size_t cb, uint32_t fFlags, size_t pcbRead);
801	VMMR3_INT_DECL(int) PGMR3DbgWriteGCPhys(PVM pVM, RTGCPHYS GCPhysDst, const void pvSrc, size_t cb, uint32_t fFlags, size_t pcbWritten);
802	VMMR3_INT_DECL(int) PGMR3DbgReadGCPtr(PVM pVM, void pvDst, RTGCPTR GCPtrSrc, size_t cb, uint32_t fFlags, size_t pcbRead);
803	VMMR3_INT_DECL(int) PGMR3DbgWriteGCPtr(PVM pVM, RTGCPTR GCPtrDst, void const pvSrc, size_t cb, uint32_t fFlags, size_t pcbWritten);
804	VMMR3_INT_DECL(int) PGMR3DbgScanPhysical(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cbRange, RTGCPHYS GCPhysAlign, const uint8_t *pabNeedle, size_t cbNeedle, PRTGCPHYS pGCPhysHit);
805	VMMR3_INT_DECL(int) PGMR3DbgScanVirtual(PVM pVM, PVMCPU pVCpu, RTGCPTR GCPtr, RTGCPTR cbRange, RTGCPTR GCPtrAlign, const uint8_t *pabNeedle, size_t cbNeedle, PRTGCUINTPTR pGCPhysHit);
806	VMMR3_INT_DECL(int) PGMR3DumpHierarchyShw(PVM pVM, uint64_t cr3, uint32_t fFlags, uint64_t u64FirstAddr, uint64_t u64LastAddr, uint32_t cMaxDepth, PCDBGFINFOHLP pHlp);
807	VMMR3_INT_DECL(int) PGMR3DumpHierarchyGst(PVM pVM, uint64_t cr3, uint32_t fFlags, RTGCPTR FirstAddr, RTGCPTR LastAddr, uint32_t cMaxDepth, PCDBGFINFOHLP pHlp);
808
809
810	/** @name Page sharing
811	* @{ */
812	VMMR3DECL(int) PGMR3SharedModuleRegister(PVM pVM, VBOXOSFAMILY enmGuestOS, char pszModuleName, char pszVersion,
813	RTGCPTR GCBaseAddr, uint32_t cbModule,
814	uint32_t cRegions, VMMDEVSHAREDREGIONDESC const *paRegions);
815	VMMR3DECL(int) PGMR3SharedModuleUnregister(PVM pVM, char pszModuleName, char pszVersion,
816	RTGCPTR GCBaseAddr, uint32_t cbModule);
817	VMMR3DECL(int) PGMR3SharedModuleCheckAll(PVM pVM);
818	VMMR3DECL(int) PGMR3SharedModuleGetPageState(PVM pVM, RTGCPTR GCPtrPage, bool pfShared, uint64_t pfPageFlags);
819	/** @} */
820
821	/** @} */
822	#endif /* IN_RING3 */
823
824	RT_C_DECLS_END
825
826	/** @} */
827	#endif
828

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source: vbox/trunk/include/VBox/vmm/pgm.h@ 56954

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