pgm.h@ 58110

Last change on this file since 58110 was 58110, checked in by vboxsync, 9 years ago
include,misc: Doxygen grouping adjustments, collecting all the VMM bits under one parent group, ditto for the COM library.
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1	/** @file
2	* PGM - Page Monitor / Monitor.
3	*/
4
5	/*
6	* Copyright (C) 2006-2015 Oracle Corporation
7	*
8	* This file is part of VirtualBox Open Source Edition (OSE), as
9	* available from http://www.virtualbox.org. This file is free software;
10	* you can redistribute it and/or modify it under the terms of the GNU
11	* General Public License (GPL) as published by the Free Software
12	* Foundation, in version 2 as it comes in the "COPYING" file of the
13	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15	*
16	* The contents of this file may alternatively be used under the terms
17	* of the Common Development and Distribution License Version 1.0
18	* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19	* VirtualBox OSE distribution, in which case the provisions of the
20	* CDDL are applicable instead of those of the GPL.
21	*
22	* You may elect to license modified versions of this file under the
23	* terms and conditions of either the GPL or the CDDL or both.
24	*/
25
26	#ifndef ___VBox_vmm_pgm_h
27	#define ___VBox_vmm_pgm_h
28
29	#include <VBox/types.h>
30	#include <VBox/sup.h>
31	#include <VBox/vmm/vmapi.h>
32	#include <VBox/vmm/gmm.h> /* for PGMMREGISTERSHAREDMODULEREQ */
33	#include <iprt/x86.h>
34	#include <VBox/VMMDev.h> /* for VMMDEVSHAREDREGIONDESC */
35	#include <VBox/param.h>
36
37	RT_C_DECLS_BEGIN
38
39	/** @defgroup grp_pgm The Page Monitor / Manager API
40	* @ingroup grp_vmm
41	* @{
42	*/
43
44	/**
45	* FNPGMRELOCATE callback mode.
46	*/
47	typedef enum PGMRELOCATECALL
48	{
49	/** The callback is for checking if the suggested address is suitable. */
50	PGMRELOCATECALL_SUGGEST = 1,
51	/** The callback is for executing the relocation. */
52	PGMRELOCATECALL_RELOCATE
53	} PGMRELOCATECALL;
54
55
56	/**
57	* Callback function which will be called when PGM is trying to find
58	* a new location for the mapping.
59	*
60	* The callback is called in two modes, 1) the check mode and 2) the relocate mode.
61	* In 1) the callback should say if it objects to a suggested new location. If it
62	* accepts the new location, it is called again for doing it's relocation.
63	*
64	*
65	* @returns true if the location is ok.
66	* @returns false if another location should be found.
67	* @param GCPtrOld The old virtual address.
68	* @param GCPtrNew The new virtual address.
69	* @param enmMode Used to indicate the callback mode.
70	* @param pvUser User argument.
71	* @remark The return value is no a failure indicator, it's an acceptance
72	* indicator. Relocation can not fail!
73	*/
74	typedef DECLCALLBACK(bool) FNPGMRELOCATE(PVM pVM, RTGCPTR GCPtrOld, RTGCPTR GCPtrNew, PGMRELOCATECALL enmMode, void *pvUser);
75	/** Pointer to a relocation callback function. */
76	typedef FNPGMRELOCATE *PFNPGMRELOCATE;
77
78
79	/**
80	* Memory access origin.
81	*/
82	typedef enum PGMACCESSORIGIN
83	{
84	/** Invalid zero value. */
85	PGMACCESSORIGIN_INVALID = 0,
86	/** IEM is access memory. */
87	PGMACCESSORIGIN_IEM,
88	/** HM is access memory. */
89	PGMACCESSORIGIN_HM,
90	/** Some device is access memory. */
91	PGMACCESSORIGIN_DEVICE,
92	/** Someone debugging is access memory. */
93	PGMACCESSORIGIN_DEBUGGER,
94	/** SELM is access memory. */
95	PGMACCESSORIGIN_SELM,
96	/** FTM is access memory. */
97	PGMACCESSORIGIN_FTM,
98	/** REM is access memory. */
99	PGMACCESSORIGIN_REM,
100	/** IOM is access memory. */
101	PGMACCESSORIGIN_IOM,
102	/** End of valid values. */
103	PGMACCESSORIGIN_END,
104	/** Type size hack. */
105	PGMACCESSORIGIN_32BIT_HACK = 0x7fffffff
106	} PGMACCESSORIGIN;
107
108
109	/**
110	* Physical page access handler kind.
111	*/
112	typedef enum PGMPHYSHANDLERKIND
113	{
114	/** MMIO range. Pages are not present, all access is done in interpreter or recompiler. */
115	PGMPHYSHANDLERKIND_MMIO = 1,
116	/** Handler all write access to a physical page range. */
117	PGMPHYSHANDLERKIND_WRITE,
118	/** Handler all access to a physical page range. */
119	PGMPHYSHANDLERKIND_ALL
120
121	} PGMPHYSHANDLERKIND;
122
123	/**
124	* Guest Access type
125	*/
126	typedef enum PGMACCESSTYPE
127	{
128	/** Read access. */
129	PGMACCESSTYPE_READ = 1,
130	/** Write access. */
131	PGMACCESSTYPE_WRITE
132	} PGMACCESSTYPE;
133
134
135	/** @def PGM_ALL_CB_DECL
136	* Macro for declaring a handler callback for all contexts. The handler
137	* callback is static in ring-3, and exported in RC and R0.
138	* @sa PGM_ALL_CB2_DECL.
139	*/
140	#if defined(IN_RC) \|\| defined(IN_RING0)
141	# ifdef __cplusplus
142	# define PGM_ALL_CB_DECL(type) extern "C" DECLEXPORT(type)
143	# else
144	# define PGM_ALL_CB_DECL(type) DECLEXPORT(type)
145	# endif
146	#else
147	# define PGM_ALL_CB_DECL(type) static type
148	#endif
149
150	/** @def PGM_ALL_CB2_DECL
151	* Macro for declaring a handler callback for all contexts. The handler
152	* callback is hidden in ring-3, and exported in RC and R0.
153	* @sa PGM_ALL_CB2_DECL.
154	*/
155	#if defined(IN_RC) \|\| defined(IN_RING0)
156	# ifdef __cplusplus
157	# define PGM_ALL_CB2_DECL(type) extern "C" DECLEXPORT(type)
158	# else
159	# define PGM_ALL_CB2_DECL(type) DECLEXPORT(type)
160	# endif
161	#else
162	# define PGM_ALL_CB2_DECL(type) DECLHIDDEN(type)
163	#endif
164
165
166	/**
167	* \#PF Handler callback for physical access handler ranges in RC and R0.
168	*
169	* @returns Strict VBox status code (appropriate for ring-0 and raw-mode).
170	* @param pVM VM Handle.
171	* @param pVCpu Pointer to the cross context CPU context for the
172	* calling EMT.
173	* @param uErrorCode CPU Error code.
174	* @param pRegFrame Trap register frame.
175	* NULL on DMA and other non CPU access.
176	* @param pvFault The fault address (cr2).
177	* @param GCPhysFault The GC physical address corresponding to pvFault.
178	* @param pvUser User argument.
179	* @thread EMT(pVCpu)
180	*/
181	typedef DECLCALLBACK(VBOXSTRICTRC) FNPGMRZPHYSPFHANDLER(PVM pVM, PVMCPU pVCpu, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame,
182	RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser);
183	/** Pointer to PGM access callback. */
184	typedef FNPGMRZPHYSPFHANDLER *PFNPGMRZPHYSPFHANDLER;
185
186
187	/**
188	* Access handler callback for physical access handler ranges.
189	*
190	* The handler can not raise any faults, it's mainly for monitoring write access
191	* to certain pages (like MMIO).
192	*
193	* @returns Strict VBox status code in ring-0 and raw-mode context, in ring-3
194	* the only supported informational status code is
195	* VINF_PGM_HANDLER_DO_DEFAULT.
196	* @retval VINF_SUCCESS if the handler have carried out the operation.
197	* @retval VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the
198	* access operation.
199	* @retval VINF_EM_XXX in ring-0 and raw-mode context.
200	*
201	* @param pVM VM Handle.
202	* @param pVCpu Pointer to the cross context CPU context for the
203	* calling EMT.
204	* @param GCPhys The physical address the guest is writing to.
205	* @param pvPhys The HC mapping of that address.
206	* @param pvBuf What the guest is reading/writing.
207	* @param cbBuf How much it's reading/writing.
208	* @param enmAccessType The access type.
209	* @param enmOrigin The origin of this call.
210	* @param pvUser User argument.
211	* @thread EMT(pVCpu)
212	*/
213	typedef DECLCALLBACK(VBOXSTRICTRC) FNPGMPHYSHANDLER(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void pvPhys, void pvBuf, size_t cbBuf,
214	PGMACCESSTYPE enmAccessType, PGMACCESSORIGIN enmOrigin, void *pvUser);
215	/** Pointer to PGM access callback. */
216	typedef FNPGMPHYSHANDLER *PFNPGMPHYSHANDLER;
217
218
219	/**
220	* Virtual access handler type.
221	*/
222	typedef enum PGMVIRTHANDLERKIND
223	{
224	/** Write access handled. */
225	PGMVIRTHANDLERKIND_WRITE = 1,
226	/** All access handled. */
227	PGMVIRTHANDLERKIND_ALL,
228	/** Hypervisor write access handled.
229	* This is used to catch the guest trying to write to LDT, TSS and any other
230	* system structure which the brain dead intel guys let unprivilegde code find. */
231	PGMVIRTHANDLERKIND_HYPERVISOR
232	} PGMVIRTHANDLERKIND;
233
234	/**
235	* \#PF handler callback for virtual access handler ranges, RC.
236	*
237	* Important to realize that a physical page in a range can have aliases, and
238	* for ALL and WRITE handlers these will also trigger.
239	*
240	* @returns Strict VBox status code (appropriate for raw-mode).
241	* @param pVM VM Handle.
242	* @param pVCpu Pointer to the cross context CPU context for the
243	* calling EMT.
244	* @param uErrorCode CPU Error code (X86_TRAP_PF_XXX).
245	* @param pRegFrame Trap register frame.
246	* @param pvFault The fault address (cr2).
247	* @param pvRange The base address of the handled virtual range.
248	* @param offRange The offset of the access into this range.
249	* (If it's a EIP range this is the EIP, if not it's pvFault.)
250	* @param pvUser User argument.
251	* @thread EMT(pVCpu)
252	*/
253	typedef DECLCALLBACK(VBOXSTRICTRC) FNPGMRCVIRTPFHANDLER(PVM pVM, PVMCPU pVCpu, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame,
254	RTGCPTR pvFault, RTGCPTR pvRange, uintptr_t offRange, void *pvUser);
255	/** Pointer to PGM access callback. */
256	typedef FNPGMRCVIRTPFHANDLER *PFNPGMRCVIRTPFHANDLER;
257
258	/**
259	* Access handler callback for virtual access handler ranges.
260	*
261	* Important to realize that a physical page in a range can have aliases, and
262	* for ALL and WRITE handlers these will also trigger.
263	*
264	* @returns VINF_SUCCESS if the handler have carried out the operation.
265	* @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
266	* @param pVM VM Handle.
267	* @param pVCpu Pointer to the cross context CPU context for the
268	* calling EMT.
269	* @param GCPtr The virtual address the guest is writing to. This
270	* is the registered address corresponding to the
271	* access, so no aliasing trouble here.
272	* @param pvPtr The HC mapping of that address.
273	* @param pvBuf What the guest is reading/writing.
274	* @param cbBuf How much it's reading/writing.
275	* @param enmAccessType The access type.
276	* @param enmOrigin Who is calling.
277	* @param pvUser User argument.
278	* @thread EMT(pVCpu)
279	*/
280	typedef DECLCALLBACK(VBOXSTRICTRC) FNPGMVIRTHANDLER(PVM pVM, PVMCPU pVCpu, RTGCPTR GCPtr, void pvPtr, void pvBuf, size_t cbBuf,
281	PGMACCESSTYPE enmAccessType, PGMACCESSORIGIN enmOrigin, void *pvUser);
282	/** Pointer to PGM access callback. */
283	typedef FNPGMVIRTHANDLER *PFNPGMVIRTHANDLER;
284
285	/**
286	* \#PF Handler callback for invalidation of virtual access handler ranges.
287	*
288	* @param pVM VM Handle.
289	* @param pVCpu Pointer to the cross context CPU context for the
290	* calling EMT.
291	* @param GCPtr The virtual address the guest has changed.
292	* @param pvUser User argument.
293	* @thread EMT(pVCpu)
294	*
295	* @todo FNPGMR3VIRTINVALIDATE will not actually be called! It was introduced
296	* in r13179 (1.1) and stopped working with r13806 (PGMPool merge,
297	* v1.2), exactly a month later.
298	*/
299	typedef DECLCALLBACK(int) FNPGMR3VIRTINVALIDATE(PVM pVM, PVMCPU pVCpu, RTGCPTR GCPtr, void *pvUser);
300	/** Pointer to PGM invalidation callback. */
301	typedef FNPGMR3VIRTINVALIDATE *PFNPGMR3VIRTINVALIDATE;
302
303
304	/**
305	* PGMR3PhysEnumDirtyFTPages callback for syncing dirty physical pages
306	*
307	* @param pVM VM Handle.
308	* @param GCPhys GC physical address
309	* @param pRange HC virtual address of the page(s)
310	* @param cbRange Size of the dirty range in bytes.
311	* @param pvUser User argument.
312	*/
313	typedef DECLCALLBACK(int) FNPGMENUMDIRTYFTPAGES(PVM pVM, RTGCPHYS GCPhys, uint8_t pRange, unsigned cbRange, void pvUser);
314	/** Pointer to PGMR3PhysEnumDirtyFTPages callback. */
315	typedef FNPGMENUMDIRTYFTPAGES *PFNPGMENUMDIRTYFTPAGES;
316
317
318	/**
319	* Paging mode.
320	*/
321	typedef enum PGMMODE
322	{
323	/** The usual invalid value. */
324	PGMMODE_INVALID = 0,
325	/** Real mode. */
326	PGMMODE_REAL,
327	/** Protected mode, no paging. */
328	PGMMODE_PROTECTED,
329	/** 32-bit paging. */
330	PGMMODE_32_BIT,
331	/** PAE paging. */
332	PGMMODE_PAE,
333	/** PAE paging with NX enabled. */
334	PGMMODE_PAE_NX,
335	/** 64-bit AMD paging (long mode). */
336	PGMMODE_AMD64,
337	/** 64-bit AMD paging (long mode) with NX enabled. */
338	PGMMODE_AMD64_NX,
339	/** Nested paging mode (shadow only; guest physical to host physical). */
340	PGMMODE_NESTED,
341	/** Extended paging (Intel) mode. */
342	PGMMODE_EPT,
343	/** The max number of modes */
344	PGMMODE_MAX,
345	/** 32bit hackishness. */
346	PGMMODE_32BIT_HACK = 0x7fffffff
347	} PGMMODE;
348
349	/** Macro for checking if the guest is using paging.
350	* @param enmMode PGMMODE_*.
351	* @remark ASSUMES certain order of the PGMMODE_* values.
352	*/
353	#define PGMMODE_WITH_PAGING(enmMode) ((enmMode) >= PGMMODE_32_BIT)
354
355	/** Macro for checking if it's one of the long mode modes.
356	* @param enmMode PGMMODE_*.
357	*/
358	#define PGMMODE_IS_LONG_MODE(enmMode) ((enmMode) == PGMMODE_AMD64_NX \|\| (enmMode) == PGMMODE_AMD64)
359
360	/**
361	* Is the ROM mapped (true) or is the shadow RAM mapped (false).
362	*
363	* @returns boolean.
364	* @param enmProt The PGMROMPROT value, must be valid.
365	*/
366	#define PGMROMPROT_IS_ROM(enmProt) \
367	( (enmProt) == PGMROMPROT_READ_ROM_WRITE_IGNORE \
368	\|\| (enmProt) == PGMROMPROT_READ_ROM_WRITE_RAM )
369
370
371	VMMDECL(bool) PGMIsLockOwner(PVM pVM);
372
373	VMMDECL(int) PGMRegisterStringFormatTypes(void);
374	VMMDECL(void) PGMDeregisterStringFormatTypes(void);
375	VMMDECL(RTHCPHYS) PGMGetHyperCR3(PVMCPU pVCpu);
376	VMMDECL(RTHCPHYS) PGMGetNestedCR3(PVMCPU pVCpu, PGMMODE enmShadowMode);
377	VMMDECL(RTHCPHYS) PGMGetInterHCCR3(PVM pVM);
378	VMMDECL(RTHCPHYS) PGMGetInterRCCR3(PVM pVM, PVMCPU pVCpu);
379	VMMDECL(RTHCPHYS) PGMGetInter32BitCR3(PVM pVM);
380	VMMDECL(RTHCPHYS) PGMGetInterPaeCR3(PVM pVM);
381	VMMDECL(RTHCPHYS) PGMGetInterAmd64CR3(PVM pVM);
382	VMMDECL(int) PGMTrap0eHandler(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault);
383	VMMDECL(int) PGMPrefetchPage(PVMCPU pVCpu, RTGCPTR GCPtrPage);
384	VMMDECL(int) PGMVerifyAccess(PVMCPU pVCpu, RTGCPTR Addr, uint32_t cbSize, uint32_t fAccess);
385	VMMDECL(int) PGMIsValidAccess(PVMCPU pVCpu, RTGCPTR Addr, uint32_t cbSize, uint32_t fAccess);
386	VMMDECL(VBOXSTRICTRC) PGMInterpretInstruction(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault);
387	VMMDECL(int) PGMMap(PVM pVM, RTGCPTR GCPtr, RTHCPHYS HCPhys, uint32_t cbPages, unsigned fFlags);
388	VMMDECL(int) PGMMapGetPage(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys);
389	VMMDECL(int) PGMMapSetPage(PVM pVM, RTGCPTR GCPtr, uint64_t cb, uint64_t fFlags);
390	VMMDECL(int) PGMMapModifyPage(PVM pVM, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask);
391	#ifndef IN_RING0
392	VMMDECL(bool) PGMMapHasConflicts(PVM pVM);
393	#endif
394	#ifdef VBOX_STRICT
395	VMMDECL(void) PGMMapCheck(PVM pVM);
396	#endif
397	VMMDECL(int) PGMShwGetPage(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys);
398	VMMDECL(int) PGMShwMakePageReadonly(PVMCPU pVCpu, RTGCPTR GCPtr, uint32_t fFlags);
399	VMMDECL(int) PGMShwMakePageWritable(PVMCPU pVCpu, RTGCPTR GCPtr, uint32_t fFlags);
400	VMMDECL(int) PGMShwMakePageNotPresent(PVMCPU pVCpu, RTGCPTR GCPtr, uint32_t fFlags);
401	/** @name Flags for PGMShwMakePageReadonly, PGMShwMakePageWritable and
402	* PGMShwMakePageNotPresent
403	* @{ */
404	/** The call is from an access handler for dealing with the a faulting write
405	* operation. The virtual address is within the same page. */
406	#define PGM_MK_PG_IS_WRITE_FAULT RT_BIT(0)
407	/** The page is an MMIO2. */
408	#define PGM_MK_PG_IS_MMIO2 RT_BIT(1)
409	/** @}*/
410	VMMDECL(int) PGMGstGetPage(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys);
411	VMMDECL(bool) PGMGstIsPagePresent(PVMCPU pVCpu, RTGCPTR GCPtr);
412	VMMDECL(int) PGMGstSetPage(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cb, uint64_t fFlags);
413	VMMDECL(int) PGMGstModifyPage(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask);
414	VMM_INT_DECL(int) PGMGstGetPaePdpes(PVMCPU pVCpu, PX86PDPE paPdpes);
415	VMM_INT_DECL(void) PGMGstUpdatePaePdpes(PVMCPU pVCpu, PCX86PDPE paPdpes);
416
417	VMMDECL(int) PGMInvalidatePage(PVMCPU pVCpu, RTGCPTR GCPtrPage);
418	VMMDECL(int) PGMFlushTLB(PVMCPU pVCpu, uint64_t cr3, bool fGlobal);
419	VMMDECL(int) PGMSyncCR3(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal);
420	VMMDECL(int) PGMUpdateCR3(PVMCPU pVCpu, uint64_t cr3);
421	VMMDECL(int) PGMChangeMode(PVMCPU pVCpu, uint64_t cr0, uint64_t cr4, uint64_t efer);
422	VMMDECL(void) PGMCr0WpEnabled(PVMCPU pVCpu);
423	VMMDECL(PGMMODE) PGMGetGuestMode(PVMCPU pVCpu);
424	VMMDECL(PGMMODE) PGMGetShadowMode(PVMCPU pVCpu);
425	VMMDECL(PGMMODE) PGMGetHostMode(PVM pVM);
426	VMMDECL(const char *) PGMGetModeName(PGMMODE enmMode);
427	VMM_INT_DECL(void) PGMNotifyNxeChanged(PVMCPU pVCpu, bool fNxe);
428	VMMDECL(bool) PGMHasDirtyPages(PVM pVM);
429
430	/** PGM physical access handler type registration handle (heap offset, valid
431	* cross contexts without needing fixing up). Callbacks and handler type is
432	* associated with this and it is shared by all handler registrations. */
433	typedef uint32_t PGMPHYSHANDLERTYPE;
434	/** Pointer to a PGM physical handler type registration handle. */
435	typedef PGMPHYSHANDLERTYPE *PPGMPHYSHANDLERTYPE;
436	/** NIL value for PGM physical access handler type handle. */
437	#define NIL_PGMPHYSHANDLERTYPE UINT32_MAX
438	VMMDECL(uint32_t) PGMHandlerPhysicalTypeRelease(PVM pVM, PGMPHYSHANDLERTYPE hType);
439	VMMDECL(uint32_t) PGMHandlerPhysicalTypeRetain(PVM pVM, PGMPHYSHANDLERTYPE hType);
440
441	VMMDECL(int) PGMHandlerPhysicalRegister(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS GCPhysLast, PGMPHYSHANDLERTYPE hType,
442	RTR3PTR pvUserR3, RTR0PTR pvUserR0, RTRCPTR pvUserRC,
443	R3PTRTYPE(const char *) pszDesc);
444	VMMDECL(int) PGMHandlerPhysicalModify(PVM pVM, RTGCPHYS GCPhysCurrent, RTGCPHYS GCPhys, RTGCPHYS GCPhysLast);
445	VMMDECL(int) PGMHandlerPhysicalDeregister(PVM pVM, RTGCPHYS GCPhys);
446	VMMDECL(int) PGMHandlerPhysicalChangeUserArgs(PVM pVM, RTGCPHYS GCPhys, RTR3PTR pvUserR3, RTR0PTR pvUserR0, RTRCPTR pvUserRC);
447	VMMDECL(int) PGMHandlerPhysicalSplit(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS GCPhysSplit);
448	VMMDECL(int) PGMHandlerPhysicalJoin(PVM pVM, RTGCPHYS GCPhys1, RTGCPHYS GCPhys2);
449	VMMDECL(int) PGMHandlerPhysicalPageTempOff(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS GCPhysPage);
450	VMMDECL(int) PGMHandlerPhysicalPageAlias(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS GCPhysPage, RTGCPHYS GCPhysPageRemap);
451	VMMDECL(int) PGMHandlerPhysicalPageAliasHC(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS GCPhysPage, RTHCPHYS HCPhysPageRemap);
452	VMMDECL(int) PGMHandlerPhysicalReset(PVM pVM, RTGCPHYS GCPhys);
453	VMMDECL(bool) PGMHandlerPhysicalIsRegistered(PVM pVM, RTGCPHYS GCPhys);
454
455	/** PGM virtual access handler type registration handle (heap offset, valid
456	* cross contexts without needing fixing up). Callbacks and handler type is
457	* associated with this and it is shared by all handler registrations. */
458	typedef uint32_t PGMVIRTHANDLERTYPE;
459	/** Pointer to a PGM virtual handler type registration handle. */
460	typedef PGMVIRTHANDLERTYPE *PPGMVIRTHANDLERTYPE;
461	/** NIL value for PGM virtual access handler type handle. */
462	#define NIL_PGMVIRTHANDLERTYPE UINT32_MAX
463	#ifdef VBOX_WITH_RAW_MODE
464	VMM_INT_DECL(uint32_t) PGMHandlerVirtualTypeRelease(PVM pVM, PGMVIRTHANDLERTYPE hType);
465	VMM_INT_DECL(uint32_t) PGMHandlerVirtualTypeRetain(PVM pVM, PGMVIRTHANDLERTYPE hType);
466	VMM_INT_DECL(bool) PGMHandlerVirtualIsRegistered(PVM pVM, RTGCPTR GCPtr);
467	#endif
468
469
470	/**
471	* Page type.
472	*
473	* @remarks This enum has to fit in a 3-bit field (see PGMPAGE::u3Type).
474	* @remarks This is used in the saved state, so changes to it requires bumping
475	* the saved state version.
476	* @todo So, convert to \#defines!
477	*/
478	typedef enum PGMPAGETYPE
479	{
480	/** The usual invalid zero entry. */
481	PGMPAGETYPE_INVALID = 0,
482	/** RAM page. (RWX) */
483	PGMPAGETYPE_RAM,
484	/** MMIO2 page. (RWX) */
485	PGMPAGETYPE_MMIO2,
486	/** MMIO2 page aliased over an MMIO page. (RWX)
487	* See PGMHandlerPhysicalPageAlias(). */
488	PGMPAGETYPE_MMIO2_ALIAS_MMIO,
489	/** Special page aliased over an MMIO page. (RWX)
490	* See PGMHandlerPhysicalPageAliasHC(), but this is generally only used for
491	* VT-x's APIC access page at the moment. Treated as MMIO by everyone except
492	* the shadow paging code. */
493	PGMPAGETYPE_SPECIAL_ALIAS_MMIO,
494	/** Shadowed ROM. (RWX) */
495	PGMPAGETYPE_ROM_SHADOW,
496	/** ROM page. (R-X) */
497	PGMPAGETYPE_ROM,
498	/** MMIO page. (---) */
499	PGMPAGETYPE_MMIO,
500	/** End of valid entries. */
501	PGMPAGETYPE_END
502	} PGMPAGETYPE;
503	AssertCompile(PGMPAGETYPE_END == 8);
504
505	VMM_INT_DECL(PGMPAGETYPE) PGMPhysGetPageType(PVM pVM, RTGCPHYS GCPhys);
506
507	VMM_INT_DECL(int) PGMPhysGCPhys2HCPhys(PVM pVM, RTGCPHYS GCPhys, PRTHCPHYS pHCPhys);
508	VMM_INT_DECL(int) PGMPhysGCPtr2HCPhys(PVMCPU pVCpu, RTGCPTR GCPtr, PRTHCPHYS pHCPhys);
509	VMM_INT_DECL(int) PGMPhysGCPhys2CCPtr(PVM pVM, RTGCPHYS GCPhys, void **ppv, PPGMPAGEMAPLOCK pLock);
510	VMM_INT_DECL(int) PGMPhysGCPhys2CCPtrReadOnly(PVM pVM, RTGCPHYS GCPhys, void const **ppv, PPGMPAGEMAPLOCK pLock);
511	VMM_INT_DECL(int) PGMPhysGCPtr2CCPtr(PVMCPU pVCpu, RTGCPTR GCPtr, void **ppv, PPGMPAGEMAPLOCK pLock);
512	VMM_INT_DECL(int) PGMPhysGCPtr2CCPtrReadOnly(PVMCPU pVCpu, RTGCPTR GCPtr, void const **ppv, PPGMPAGEMAPLOCK pLock);
513
514	VMMDECL(bool) PGMPhysIsA20Enabled(PVMCPU pVCpu);
515	VMMDECL(bool) PGMPhysIsGCPhysValid(PVM pVM, RTGCPHYS GCPhys);
516	VMMDECL(bool) PGMPhysIsGCPhysNormal(PVM pVM, RTGCPHYS GCPhys);
517	VMMDECL(int) PGMPhysGCPtr2GCPhys(PVMCPU pVCpu, RTGCPTR GCPtr, PRTGCPHYS pGCPhys);
518	VMMDECL(void) PGMPhysReleasePageMappingLock(PVM pVM, PPGMPAGEMAPLOCK pLock);
519
520	/** @def PGM_PHYS_RW_IS_SUCCESS
521	* Check whether a PGMPhysRead, PGMPhysWrite, PGMPhysReadGCPtr or
522	* PGMPhysWriteGCPtr call completed the given task.
523	*
524	* @returns true if completed, false if not.
525	* @param a_rcStrict The status code.
526	* @sa IOM_SUCCESS
527	*/
528	#ifdef IN_RING3
529	# define PGM_PHYS_RW_IS_SUCCESS(a_rcStrict) \
530	( (a_rcStrict) == VINF_SUCCESS \
531	\|\| (a_rcStrict) == VINF_EM_DBG_STOP \
532	\|\| (a_rcStrict) == VINF_EM_DBG_BREAKPOINT \
533	)
534	#elif defined(IN_RING0)
535	# define PGM_PHYS_RW_IS_SUCCESS(a_rcStrict) \
536	( (a_rcStrict) == VINF_SUCCESS \
537	\|\| (a_rcStrict) == VINF_EM_OFF \
538	\|\| (a_rcStrict) == VINF_EM_SUSPEND \
539	\|\| (a_rcStrict) == VINF_EM_RESET \
540	\|\| (a_rcStrict) == VINF_EM_HALT \
541	\|\| (a_rcStrict) == VINF_EM_DBG_STOP \
542	\|\| (a_rcStrict) == VINF_EM_DBG_BREAKPOINT \
543	)
544	#elif defined(IN_RC)
545	# define PGM_PHYS_RW_IS_SUCCESS(a_rcStrict) \
546	( (a_rcStrict) == VINF_SUCCESS \
547	\|\| (a_rcStrict) == VINF_EM_OFF \
548	\|\| (a_rcStrict) == VINF_EM_SUSPEND \
549	\|\| (a_rcStrict) == VINF_EM_RESET \
550	\|\| (a_rcStrict) == VINF_EM_HALT \
551	\|\| (a_rcStrict) == VINF_SELM_SYNC_GDT \
552	\|\| (a_rcStrict) == VINF_EM_RAW_EMULATE_INSTR_GDT_FAULT \
553	\|\| (a_rcStrict) == VINF_EM_DBG_STOP \
554	\|\| (a_rcStrict) == VINF_EM_DBG_BREAKPOINT \
555	)
556	#endif
557	/** @def PGM_PHYS_RW_DO_UPDATE_STRICT_RC
558	* Updates the return code with a new result.
559	*
560	* Both status codes must be successes according to PGM_PHYS_RW_IS_SUCCESS.
561	*
562	* @param a_rcStrict The current return code, to be updated.
563	* @param a_rcStrict2 The new return code to merge in.
564	*/
565	#ifdef IN_RING3
566	# define PGM_PHYS_RW_DO_UPDATE_STRICT_RC(a_rcStrict, a_rcStrict2) \
567	do { \
568	Assert(rcStrict == VINF_SUCCESS); \
569	Assert(rcStrict2 == VINF_SUCCESS); \
570	} while (0)
571	#elif defined(IN_RING0)
572	# define PGM_PHYS_RW_DO_UPDATE_STRICT_RC(a_rcStrict, a_rcStrict2) \
573	do { \
574	Assert(PGM_PHYS_RW_IS_SUCCESS(rcStrict)); \
575	Assert(PGM_PHYS_RW_IS_SUCCESS(rcStrict2)); \
576	if ((a_rcStrict2) == VINF_SUCCESS \|\| (a_rcStrict) == (a_rcStrict2)) \
577	{ /* likely */ } \
578	else if ( (a_rcStrict) == VINF_SUCCESS \
579	\|\| (a_rcStrict) > (a_rcStrict2)) \
580	(a_rcStrict) = (a_rcStrict2); \
581	} while (0)
582	#elif defined(IN_RC)
583	# define PGM_PHYS_RW_DO_UPDATE_STRICT_RC(a_rcStrict, a_rcStrict2) \
584	do { \
585	Assert(PGM_PHYS_RW_IS_SUCCESS(rcStrict)); \
586	Assert(PGM_PHYS_RW_IS_SUCCESS(rcStrict2)); \
587	AssertCompile(VINF_SELM_SYNC_GDT > VINF_EM_LAST); \
588	AssertCompile(VINF_EM_RAW_EMULATE_INSTR_GDT_FAULT > VINF_EM_LAST); \
589	AssertCompile(VINF_EM_RAW_EMULATE_INSTR_GDT_FAULT < VINF_SELM_SYNC_GDT); \
590	if ((a_rcStrict2) == VINF_SUCCESS \|\| (a_rcStrict) == (a_rcStrict2)) \
591	{ /* likely */ } \
592	else if ( (a_rcStrict) == VINF_SUCCESS \
593	\|\| ( (a_rcStrict) > (a_rcStrict2) \
594	&& ( (a_rcStrict2) <= VINF_EM_RESET \
595	\|\| (a_rcStrict) != VINF_EM_RAW_EMULATE_INSTR_GDT_FAULT) ) \
596	\|\| ( (a_rcStrict2) == VINF_EM_RAW_EMULATE_INSTR_GDT_FAULT \
597	&& (a_rcStrict) > VINF_EM_RESET) ) \
598	(a_rcStrict) = (a_rcStrict2); \
599	} while (0)
600	#endif
601
602	VMMDECL(VBOXSTRICTRC) PGMPhysRead(PVM pVM, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead, PGMACCESSORIGIN enmOrigin);
603	VMMDECL(VBOXSTRICTRC) PGMPhysWrite(PVM pVM, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite, PGMACCESSORIGIN enmOrigin);
604	VMMDECL(VBOXSTRICTRC) PGMPhysReadGCPtr(PVMCPU pVCpu, void *pvDst, RTGCPTR GCPtrSrc, size_t cb, PGMACCESSORIGIN enmOrigin);
605	VMMDECL(VBOXSTRICTRC) PGMPhysWriteGCPtr(PVMCPU pVCpu, RTGCPTR GCPtrDst, const void *pvSrc, size_t cb, PGMACCESSORIGIN enmOrigin);
606
607	VMMDECL(int) PGMPhysSimpleReadGCPhys(PVM pVM, void *pvDst, RTGCPHYS GCPhysSrc, size_t cb);
608	VMMDECL(int) PGMPhysSimpleWriteGCPhys(PVM pVM, RTGCPHYS GCPhysDst, const void *pvSrc, size_t cb);
609	VMMDECL(int) PGMPhysSimpleReadGCPtr(PVMCPU pVCpu, void *pvDst, RTGCPTR GCPtrSrc, size_t cb);
610	VMMDECL(int) PGMPhysSimpleWriteGCPtr(PVMCPU pVCpu, RTGCPTR GCPtrDst, const void *pvSrc, size_t cb);
611	VMMDECL(int) PGMPhysSimpleDirtyWriteGCPtr(PVMCPU pVCpu, RTGCPTR GCPtrDst, const void *pvSrc, size_t cb);
612	VMMDECL(int) PGMPhysInterpretedRead(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, void *pvDst, RTGCPTR GCPtrSrc, size_t cb);
613	VMMDECL(int) PGMPhysInterpretedReadNoHandlers(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, void *pvDst, RTGCUINTPTR GCPtrSrc, size_t cb, bool fRaiseTrap);
614	VMMDECL(int) PGMPhysInterpretedWriteNoHandlers(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, RTGCPTR GCPtrDst, void const *pvSrc, size_t cb, bool fRaiseTrap);
615	VMM_INT_DECL(int) PGMPhysIemGCPhys2Ptr(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, bool fWritable, bool fByPassHandlers, void **ppv, PPGMPAGEMAPLOCK pLock);
616	VMM_INT_DECL(int) PGMPhysIemQueryAccess(PVM pVM, RTGCPHYS GCPhys, bool fWritable, bool fByPassHandlers);
617
618	#ifdef VBOX_STRICT
619	VMMDECL(unsigned) PGMAssertHandlerAndFlagsInSync(PVM pVM);
620	VMMDECL(unsigned) PGMAssertNoMappingConflicts(PVM pVM);
621	VMMDECL(unsigned) PGMAssertCR3(PVM pVM, PVMCPU pVCpu, uint64_t cr3, uint64_t cr4);
622	#endif /* VBOX_STRICT */
623
624	#if defined(IN_RC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE)
625	VMMDECL(void) PGMRZDynMapStartAutoSet(PVMCPU pVCpu);
626	VMMDECL(void) PGMRZDynMapReleaseAutoSet(PVMCPU pVCpu);
627	VMMDECL(void) PGMRZDynMapFlushAutoSet(PVMCPU pVCpu);
628	VMMDECL(uint32_t) PGMRZDynMapPushAutoSubset(PVMCPU pVCpu);
629	VMMDECL(void) PGMRZDynMapPopAutoSubset(PVMCPU pVCpu, uint32_t iPrevSubset);
630	#endif
631
632	VMMDECL(int) PGMSetLargePageUsage(PVM pVM, bool fUseLargePages);
633
634	/**
635	* Query large page usage state
636	*
637	* @returns 0 - disabled, 1 - enabled
638	* @param pVM The VM to operate on.
639	*/
640	#define PGMIsUsingLargePages(pVM) ((pVM)->fUseLargePages)
641
642
643	#ifdef IN_RC
644	/** @defgroup grp_pgm_gc The PGM Guest Context API
645	* @{
646	*/
647	VMMRCDECL(int) PGMRCDynMapInit(PVM pVM);
648	/** @} */
649	#endif /* IN_RC */
650
651
652	#ifdef IN_RING0
653	/** @defgroup grp_pgm_r0 The PGM Host Context Ring-0 API
654	* @{
655	*/
656	VMMR0_INT_DECL(int) PGMR0PhysAllocateHandyPages(PVM pVM, PVMCPU pVCpu);
657	VMMR0_INT_DECL(int) PGMR0PhysFlushHandyPages(PVM pVM, PVMCPU pVCpu);
658	VMMR0_INT_DECL(int) PGMR0PhysAllocateLargeHandyPage(PVM pVM, PVMCPU pVCpu);
659	VMMR0_INT_DECL(int) PGMR0PhysSetupIommu(PVM pVM);
660	VMMR0DECL(int) PGMR0SharedModuleCheck(PVM pVM, PGVM pGVM, VMCPUID idCpu, PGMMSHAREDMODULE pModule, PCRTGCPTR64 paRegionsGCPtrs);
661	VMMR0DECL(int) PGMR0Trap0eHandlerNestedPaging(PVM pVM, PVMCPU pVCpu, PGMMODE enmShwPagingMode, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPHYS pvFault);
662	VMMR0DECL(VBOXSTRICTRC) PGMR0Trap0eHandlerNPMisconfig(PVM pVM, PVMCPU pVCpu, PGMMODE enmShwPagingMode, PCPUMCTXCORE pRegFrame, RTGCPHYS GCPhysFault, uint32_t uErr);
663	# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
664	VMMR0DECL(int) PGMR0DynMapInit(void);
665	VMMR0DECL(void) PGMR0DynMapTerm(void);
666	VMMR0DECL(int) PGMR0DynMapInitVM(PVM pVM);
667	VMMR0DECL(void) PGMR0DynMapTermVM(PVM pVM);
668	VMMR0DECL(int) PGMR0DynMapAssertIntegrity(void);
669	VMMR0DECL(bool) PGMR0DynMapStartOrMigrateAutoSet(PVMCPU pVCpu);
670	VMMR0DECL(void) PGMR0DynMapMigrateAutoSet(PVMCPU pVCpu);
671	# endif
672	/** @} */
673	#endif /* IN_RING0 */
674
675
676
677	#ifdef IN_RING3
678	/** @defgroup grp_pgm_r3 The PGM Host Context Ring-3 API
679	* @{
680	*/
681	VMMR3DECL(int) PGMR3Init(PVM pVM);
682	VMMR3DECL(int) PGMR3InitDynMap(PVM pVM);
683	VMMR3DECL(int) PGMR3InitFinalize(PVM pVM);
684	VMMR3_INT_DECL(int) PGMR3InitCompleted(PVM pVM, VMINITCOMPLETED enmWhat);
685	VMMR3DECL(void) PGMR3Relocate(PVM pVM, RTGCINTPTR offDelta);
686	VMMR3DECL(void) PGMR3ResetCpu(PVM pVM, PVMCPU pVCpu);
687	VMMR3_INT_DECL(void) PGMR3Reset(PVM pVM);
688	VMMR3_INT_DECL(void) PGMR3ResetNoMorePhysWritesFlag(PVM pVM);
689	VMMR3_INT_DECL(void) PGMR3MemSetup(PVM pVM, bool fReset);
690	VMMR3DECL(int) PGMR3Term(PVM pVM);
691	VMMR3DECL(int) PGMR3LockCall(PVM pVM);
692	VMMR3DECL(int) PGMR3ChangeMode(PVM pVM, PVMCPU pVCpu, PGMMODE enmGuestMode);
693
694	VMMR3DECL(int) PGMR3PhysRegisterRam(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, const char *pszDesc);
695	VMMR3DECL(int) PGMR3PhysChangeMemBalloon(PVM pVM, bool fInflate, unsigned cPages, RTGCPHYS *paPhysPage);
696	VMMR3DECL(int) PGMR3PhysWriteProtectRAM(PVM pVM);
697	VMMR3DECL(int) PGMR3PhysEnumDirtyFTPages(PVM pVM, PFNPGMENUMDIRTYFTPAGES pfnEnum, void *pvUser);
698	VMMR3DECL(uint32_t) PGMR3PhysGetRamRangeCount(PVM pVM);
699	VMMR3DECL(int) PGMR3PhysGetRange(PVM pVM, uint32_t iRange, PRTGCPHYS pGCPhysStart, PRTGCPHYS pGCPhysLast,
700	const char *ppszDesc, bool pfIsMmio);
701	VMMR3DECL(int) PGMR3QueryMemoryStats(PUVM pUVM, uint64_t pcbTotalMem, uint64_t pcbPrivateMem, uint64_t pcbSharedMem, uint64_t pcbZeroMem);
702	VMMR3DECL(int) PGMR3QueryGlobalMemoryStats(PUVM pUVM, uint64_t pcbAllocMem, uint64_t pcbFreeMem, uint64_t pcbBallonedMem, uint64_t pcbSharedMem);
703
704	VMMR3DECL(int) PGMR3PhysMMIORegister(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, PGMPHYSHANDLERTYPE hType,
705	RTR3PTR pvUserR3, RTR0PTR pvUserR0, RTRCPTR pvUserRC, const char *pszDesc);
706	VMMR3DECL(int) PGMR3PhysMMIODeregister(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb);
707	VMMR3DECL(int) PGMR3PhysMMIO2Register(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS cb, uint32_t fFlags, void *ppv, const char pszDesc);
708	VMMR3DECL(int) PGMR3PhysMMIO2Deregister(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion);
709	VMMR3DECL(int) PGMR3PhysMMIO2Map(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS GCPhys);
710	VMMR3DECL(int) PGMR3PhysMMIO2Unmap(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS GCPhys);
711	VMMR3DECL(bool) PGMR3PhysMMIO2IsBase(PVM pVM, PPDMDEVINS pDevIns, RTGCPHYS GCPhys);
712	VMMR3DECL(int) PGMR3PhysMMIO2GetHCPhys(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS off, PRTHCPHYS pHCPhys);
713	VMMR3DECL(int) PGMR3PhysMMIO2MapKernel(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS off, RTGCPHYS cb, const char *pszDesc, PRTR0PTR pR0Ptr);
714
715	/** @name PGMR3PhysRegisterRom flags.
716	* @{ */
717	/** Inidicates that ROM shadowing should be enabled. */
718	#define PGMPHYS_ROM_FLAGS_SHADOWED RT_BIT_32(0)
719	/** Indicates that what pvBinary points to won't go away
720	* and can be used for strictness checks. */
721	#define PGMPHYS_ROM_FLAGS_PERMANENT_BINARY RT_BIT_32(1)
722	/** @} */
723
724	VMMR3DECL(int) PGMR3PhysRomRegister(PVM pVM, PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTGCPHYS cb,
725	const void pvBinary, uint32_t cbBinary, uint32_t fFlags, const char pszDesc);
726	VMMR3DECL(int) PGMR3PhysRomProtect(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, PGMROMPROT enmProt);
727	VMMR3DECL(int) PGMR3PhysRegister(PVM pVM, void pvRam, RTGCPHYS GCPhys, size_t cb, unsigned fFlags, const SUPPAGE paPages, const char *pszDesc);
728	VMMDECL(void) PGMR3PhysSetA20(PVMCPU pVCpu, bool fEnable);
729	/** @name PGMR3MapPT flags.
730	* @{ */
731	/** The mapping may be unmapped later. The default is permanent mappings. */
732	#define PGMR3MAPPT_FLAGS_UNMAPPABLE RT_BIT(0)
733	/** @} */
734	VMMR3DECL(int) PGMR3MapPT(PVM pVM, RTGCPTR GCPtr, uint32_t cb, uint32_t fFlags, PFNPGMRELOCATE pfnRelocate, void pvUser, const char pszDesc);
735	VMMR3DECL(int) PGMR3UnmapPT(PVM pVM, RTGCPTR GCPtr);
736	VMMR3DECL(int) PGMR3FinalizeMappings(PVM pVM);
737	VMMR3DECL(int) PGMR3MappingsSize(PVM pVM, uint32_t *pcb);
738	VMMR3DECL(int) PGMR3MappingsFix(PVM pVM, RTGCPTR GCPtrBase, uint32_t cb);
739	VMMR3DECL(int) PGMR3MappingsUnfix(PVM pVM);
740	VMMR3DECL(bool) PGMR3MappingsNeedReFixing(PVM pVM);
741	#if defined(VBOX_WITH_RAW_MODE) \|\| HC_ARCH_BITS == 32 /* (latter for 64-bit guests on 32-bit hosts) */
742	VMMR3DECL(int) PGMR3MapIntermediate(PVM pVM, RTUINTPTR Addr, RTHCPHYS HCPhys, unsigned cbPages);
743	#endif
744	VMMR3DECL(int) PGMR3MapRead(PVM pVM, void *pvDst, RTGCPTR GCPtrSrc, size_t cb);
745
746	VMMR3_INT_DECL(int) PGMR3HandlerPhysicalTypeRegisterEx(PVM pVM, PGMPHYSHANDLERKIND enmKind,
747	PFNPGMPHYSHANDLER pfnHandlerR3,
748	R0PTRTYPE(PFNPGMPHYSHANDLER) pfnHandlerR0,
749	R0PTRTYPE(PFNPGMRZPHYSPFHANDLER) pfnPfHandlerR0,
750	RCPTRTYPE(PFNPGMPHYSHANDLER) pfnHandlerRC,
751	RCPTRTYPE(PFNPGMRZPHYSPFHANDLER) pfnPfHandlerRC,
752	const char *pszDesc, PPGMPHYSHANDLERTYPE phType);
753	VMMR3DECL(int) PGMR3HandlerPhysicalTypeRegister(PVM pVM, PGMPHYSHANDLERKIND enmKind,
754	R3PTRTYPE(PFNPGMPHYSHANDLER) pfnHandlerR3,
755	const char pszModR0, const char pszHandlerR0, const char *pszPfHandlerR0,
756	const char pszModRC, const char pszHandlerRC, const char *pszPfHandlerRC,
757	const char *pszDesc,
758	PPGMPHYSHANDLERTYPE phType);
759	#ifdef VBOX_WITH_RAW_MODE
760	VMMR3_INT_DECL(int) PGMR3HandlerVirtualTypeRegisterEx(PVM pVM, PGMVIRTHANDLERKIND enmKind, bool fRelocUserRC,
761	PFNPGMR3VIRTINVALIDATE pfnInvalidateR3,
762	PFNPGMVIRTHANDLER pfnHandlerR3,
763	RCPTRTYPE(FNPGMVIRTHANDLER) pfnHandlerRC,
764	RCPTRTYPE(FNPGMRCVIRTPFHANDLER) pfnPfHandlerRC,
765	const char *pszDesc, PPGMVIRTHANDLERTYPE phType);
766	VMMR3_INT_DECL(int) PGMR3HandlerVirtualTypeRegister(PVM pVM, PGMVIRTHANDLERKIND enmKind, bool fRelocUserRC,
767	PFNPGMR3VIRTINVALIDATE pfnInvalidateR3,
768	PFNPGMVIRTHANDLER pfnHandlerR3,
769	const char pszHandlerRC, const char pszPfHandlerRC, const char *pszDesc,
770	PPGMVIRTHANDLERTYPE phType);
771	VMMR3_INT_DECL(int) PGMR3HandlerVirtualRegister(PVM pVM, PVMCPU pVCpu, PGMVIRTHANDLERTYPE hType, RTGCPTR GCPtr,
772	RTGCPTR GCPtrLast, void pvUserR3, RTRCPTR pvUserRC, const char pszDesc);
773	VMMR3_INT_DECL(int) PGMHandlerVirtualChangeType(PVM pVM, RTGCPTR GCPtr, PGMVIRTHANDLERTYPE hNewType);
774	VMMR3_INT_DECL(int) PGMHandlerVirtualDeregister(PVM pVM, PVMCPU pVCpu, RTGCPTR GCPtr, bool fHypervisor);
775	#endif
776	VMMR3DECL(int) PGMR3PoolGrow(PVM pVM);
777
778	VMMR3DECL(int) PGMR3PhysTlbGCPhys2Ptr(PVM pVM, RTGCPHYS GCPhys, bool fWritable, void **ppv);
779	VMMR3DECL(uint8_t) PGMR3PhysReadU8(PVM pVM, RTGCPHYS GCPhys, PGMACCESSORIGIN enmOrigin);
780	VMMR3DECL(uint16_t) PGMR3PhysReadU16(PVM pVM, RTGCPHYS GCPhys, PGMACCESSORIGIN enmOrigin);
781	VMMR3DECL(uint32_t) PGMR3PhysReadU32(PVM pVM, RTGCPHYS GCPhys, PGMACCESSORIGIN enmOrigin);
782	VMMR3DECL(uint64_t) PGMR3PhysReadU64(PVM pVM, RTGCPHYS GCPhys, PGMACCESSORIGIN enmOrigin);
783	VMMR3DECL(void) PGMR3PhysWriteU8(PVM pVM, RTGCPHYS GCPhys, uint8_t Value, PGMACCESSORIGIN enmOrigin);
784	VMMR3DECL(void) PGMR3PhysWriteU16(PVM pVM, RTGCPHYS GCPhys, uint16_t Value, PGMACCESSORIGIN enmOrigin);
785	VMMR3DECL(void) PGMR3PhysWriteU32(PVM pVM, RTGCPHYS GCPhys, uint32_t Value, PGMACCESSORIGIN enmOrigin);
786	VMMR3DECL(void) PGMR3PhysWriteU64(PVM pVM, RTGCPHYS GCPhys, uint64_t Value, PGMACCESSORIGIN enmOrigin);
787	VMMR3DECL(int) PGMR3PhysReadExternal(PVM pVM, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead, PGMACCESSORIGIN enmOrigin);
788	VMMR3DECL(int) PGMR3PhysWriteExternal(PVM pVM, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite, PGMACCESSORIGIN enmOrigin);
789	VMMR3DECL(int) PGMR3PhysGCPhys2CCPtrExternal(PVM pVM, RTGCPHYS GCPhys, void **ppv, PPGMPAGEMAPLOCK pLock);
790	VMMR3DECL(int) PGMR3PhysGCPhys2CCPtrReadOnlyExternal(PVM pVM, RTGCPHYS GCPhys, void const **ppv, PPGMPAGEMAPLOCK pLock);
791	VMMR3DECL(int) PGMR3PhysChunkMap(PVM pVM, uint32_t idChunk);
792	VMMR3DECL(void) PGMR3PhysChunkInvalidateTLB(PVM pVM);
793	VMMR3DECL(int) PGMR3PhysAllocateHandyPages(PVM pVM);
794	VMMR3DECL(int) PGMR3PhysAllocateLargeHandyPage(PVM pVM, RTGCPHYS GCPhys);
795
796	VMMR3DECL(int) PGMR3CheckIntegrity(PVM pVM);
797
798	VMMR3DECL(int) PGMR3DbgR3Ptr2GCPhys(PUVM pUVM, RTR3PTR R3Ptr, PRTGCPHYS pGCPhys);
799	VMMR3DECL(int) PGMR3DbgR3Ptr2HCPhys(PUVM pUVM, RTR3PTR R3Ptr, PRTHCPHYS pHCPhys);
800	VMMR3DECL(int) PGMR3DbgHCPhys2GCPhys(PUVM pUVM, RTHCPHYS HCPhys, PRTGCPHYS pGCPhys);
801	VMMR3_INT_DECL(int) PGMR3DbgReadGCPhys(PVM pVM, void pvDst, RTGCPHYS GCPhysSrc, size_t cb, uint32_t fFlags, size_t pcbRead);
802	VMMR3_INT_DECL(int) PGMR3DbgWriteGCPhys(PVM pVM, RTGCPHYS GCPhysDst, const void pvSrc, size_t cb, uint32_t fFlags, size_t pcbWritten);
803	VMMR3_INT_DECL(int) PGMR3DbgReadGCPtr(PVM pVM, void pvDst, RTGCPTR GCPtrSrc, size_t cb, uint32_t fFlags, size_t pcbRead);
804	VMMR3_INT_DECL(int) PGMR3DbgWriteGCPtr(PVM pVM, RTGCPTR GCPtrDst, void const pvSrc, size_t cb, uint32_t fFlags, size_t pcbWritten);
805	VMMR3_INT_DECL(int) PGMR3DbgScanPhysical(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cbRange, RTGCPHYS GCPhysAlign, const uint8_t *pabNeedle, size_t cbNeedle, PRTGCPHYS pGCPhysHit);
806	VMMR3_INT_DECL(int) PGMR3DbgScanVirtual(PVM pVM, PVMCPU pVCpu, RTGCPTR GCPtr, RTGCPTR cbRange, RTGCPTR GCPtrAlign, const uint8_t *pabNeedle, size_t cbNeedle, PRTGCUINTPTR pGCPhysHit);
807	VMMR3_INT_DECL(int) PGMR3DumpHierarchyShw(PVM pVM, uint64_t cr3, uint32_t fFlags, uint64_t u64FirstAddr, uint64_t u64LastAddr, uint32_t cMaxDepth, PCDBGFINFOHLP pHlp);
808	VMMR3_INT_DECL(int) PGMR3DumpHierarchyGst(PVM pVM, uint64_t cr3, uint32_t fFlags, RTGCPTR FirstAddr, RTGCPTR LastAddr, uint32_t cMaxDepth, PCDBGFINFOHLP pHlp);
809
810
811	/** @name Page sharing
812	* @{ */
813	VMMR3DECL(int) PGMR3SharedModuleRegister(PVM pVM, VBOXOSFAMILY enmGuestOS, char pszModuleName, char pszVersion,
814	RTGCPTR GCBaseAddr, uint32_t cbModule,
815	uint32_t cRegions, VMMDEVSHAREDREGIONDESC const *paRegions);
816	VMMR3DECL(int) PGMR3SharedModuleUnregister(PVM pVM, char pszModuleName, char pszVersion,
817	RTGCPTR GCBaseAddr, uint32_t cbModule);
818	VMMR3DECL(int) PGMR3SharedModuleCheckAll(PVM pVM);
819	VMMR3DECL(int) PGMR3SharedModuleGetPageState(PVM pVM, RTGCPTR GCPtrPage, bool pfShared, uint64_t pfPageFlags);
820	/** @} */
821
822	/** @} */
823	#endif /* IN_RING3 */
824
825	RT_C_DECLS_END
826
827	/** @} */
828	#endif
829

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source: vbox/trunk/include/VBox/vmm/pgm.h@ 58110

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