pgm.h@ 67937

Last change on this file since 67937 was 66023, checked in by vboxsync, 8 years ago
VBox/vmm/pgm.h: Note that PGMMODE is part of saved state.
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Line
1	/** @file
2	* PGM - Page Monitor / Monitor.
3	*/
4
5	/*
6	* Copyright (C) 2006-2016 Oracle Corporation
7	*
8	* This file is part of VirtualBox Open Source Edition (OSE), as
9	* available from http://www.virtualbox.org. This file is free software;
10	* you can redistribute it and/or modify it under the terms of the GNU
11	* General Public License (GPL) as published by the Free Software
12	* Foundation, in version 2 as it comes in the "COPYING" file of the
13	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15	*
16	* The contents of this file may alternatively be used under the terms
17	* of the Common Development and Distribution License Version 1.0
18	* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19	* VirtualBox OSE distribution, in which case the provisions of the
20	* CDDL are applicable instead of those of the GPL.
21	*
22	* You may elect to license modified versions of this file under the
23	* terms and conditions of either the GPL or the CDDL or both.
24	*/
25
26	#ifndef ___VBox_vmm_pgm_h
27	#define ___VBox_vmm_pgm_h
28
29	#include <VBox/types.h>
30	#include <VBox/sup.h>
31	#include <VBox/vmm/vmapi.h>
32	#include <VBox/vmm/gmm.h> /* for PGMMREGISTERSHAREDMODULEREQ */
33	#include <iprt/x86.h>
34	#include <VBox/VMMDev.h> /* for VMMDEVSHAREDREGIONDESC */
35	#include <VBox/param.h>
36
37	RT_C_DECLS_BEGIN
38
39	/** @defgroup grp_pgm The Page Monitor / Manager API
40	* @ingroup grp_vmm
41	* @{
42	*/
43
44	/**
45	* FNPGMRELOCATE callback mode.
46	*/
47	typedef enum PGMRELOCATECALL
48	{
49	/** The callback is for checking if the suggested address is suitable. */
50	PGMRELOCATECALL_SUGGEST = 1,
51	/** The callback is for executing the relocation. */
52	PGMRELOCATECALL_RELOCATE
53	} PGMRELOCATECALL;
54
55
56	/**
57	* Callback function which will be called when PGM is trying to find
58	* a new location for the mapping.
59	*
60	* The callback is called in two modes, 1) the check mode and 2) the relocate mode.
61	* In 1) the callback should say if it objects to a suggested new location. If it
62	* accepts the new location, it is called again for doing it's relocation.
63	*
64	*
65	* @returns true if the location is ok.
66	* @returns false if another location should be found.
67	* @param pVM The cross context VM structure.
68	* @param GCPtrOld The old virtual address.
69	* @param GCPtrNew The new virtual address.
70	* @param enmMode Used to indicate the callback mode.
71	* @param pvUser User argument.
72	* @remark The return value is no a failure indicator, it's an acceptance
73	* indicator. Relocation can not fail!
74	*/
75	typedef DECLCALLBACK(bool) FNPGMRELOCATE(PVM pVM, RTGCPTR GCPtrOld, RTGCPTR GCPtrNew, PGMRELOCATECALL enmMode, void *pvUser);
76	/** Pointer to a relocation callback function. */
77	typedef FNPGMRELOCATE *PFNPGMRELOCATE;
78
79
80	/**
81	* Memory access origin.
82	*/
83	typedef enum PGMACCESSORIGIN
84	{
85	/** Invalid zero value. */
86	PGMACCESSORIGIN_INVALID = 0,
87	/** IEM is access memory. */
88	PGMACCESSORIGIN_IEM,
89	/** HM is access memory. */
90	PGMACCESSORIGIN_HM,
91	/** Some device is access memory. */
92	PGMACCESSORIGIN_DEVICE,
93	/** Someone debugging is access memory. */
94	PGMACCESSORIGIN_DEBUGGER,
95	/** SELM is access memory. */
96	PGMACCESSORIGIN_SELM,
97	/** FTM is access memory. */
98	PGMACCESSORIGIN_FTM,
99	/** REM is access memory. */
100	PGMACCESSORIGIN_REM,
101	/** IOM is access memory. */
102	PGMACCESSORIGIN_IOM,
103	/** End of valid values. */
104	PGMACCESSORIGIN_END,
105	/** Type size hack. */
106	PGMACCESSORIGIN_32BIT_HACK = 0x7fffffff
107	} PGMACCESSORIGIN;
108
109
110	/**
111	* Physical page access handler kind.
112	*/
113	typedef enum PGMPHYSHANDLERKIND
114	{
115	/** MMIO range. Pages are not present, all access is done in interpreter or recompiler. */
116	PGMPHYSHANDLERKIND_MMIO = 1,
117	/** Handler all write access to a physical page range. */
118	PGMPHYSHANDLERKIND_WRITE,
119	/** Handler all access to a physical page range. */
120	PGMPHYSHANDLERKIND_ALL
121
122	} PGMPHYSHANDLERKIND;
123
124	/**
125	* Guest Access type
126	*/
127	typedef enum PGMACCESSTYPE
128	{
129	/** Read access. */
130	PGMACCESSTYPE_READ = 1,
131	/** Write access. */
132	PGMACCESSTYPE_WRITE
133	} PGMACCESSTYPE;
134
135
136	/** @def PGM_ALL_CB_DECL
137	* Macro for declaring a handler callback for all contexts. The handler
138	* callback is static in ring-3, and exported in RC and R0.
139	* @sa PGM_ALL_CB2_DECL.
140	*/
141	#if defined(IN_RC) \|\| defined(IN_RING0)
142	# ifdef __cplusplus
143	# define PGM_ALL_CB_DECL(type) extern "C" DECLCALLBACK(DECLEXPORT(type))
144	# else
145	# define PGM_ALL_CB_DECL(type) DECLCALLBACK(DECLEXPORT(type))
146	# endif
147	#else
148	# define PGM_ALL_CB_DECL(type) static DECLCALLBACK(type)
149	#endif
150
151	/** @def PGM_ALL_CB2_DECL
152	* Macro for declaring a handler callback for all contexts. The handler
153	* callback is hidden in ring-3, and exported in RC and R0.
154	* @sa PGM_ALL_CB2_DECL.
155	*/
156	#if defined(IN_RC) \|\| defined(IN_RING0)
157	# ifdef __cplusplus
158	# define PGM_ALL_CB2_DECL(type) extern "C" DECLCALLBACK(DECLEXPORT(type))
159	# else
160	# define PGM_ALL_CB2_DECL(type) DECLCALLBACK(DECLEXPORT(type))
161	# endif
162	#else
163	# define PGM_ALL_CB2_DECL(type) DECLCALLBACK(DECLHIDDEN(type))
164	#endif
165
166	/** @def PGM_ALL_CB2_PROTO
167	* Macro for declaring a handler callback for all contexts. The handler
168	* callback is hidden in ring-3, and exported in RC and R0.
169	* @param fnType The callback function type.
170	* @sa PGM_ALL_CB2_DECL.
171	*/
172	#if defined(IN_RC) \|\| defined(IN_RING0)
173	# ifdef __cplusplus
174	# define PGM_ALL_CB2_PROTO(fnType) extern "C" DECLEXPORT(fnType)
175	# else
176	# define PGM_ALL_CB2_PROTO(fnType) DECLEXPORT(fnType)
177	# endif
178	#else
179	# define PGM_ALL_CB2_PROTO(fnType) DECLHIDDEN(fnType)
180	#endif
181
182
183	/**
184	* \#PF Handler callback for physical access handler ranges in RC and R0.
185	*
186	* @returns Strict VBox status code (appropriate for ring-0 and raw-mode).
187	* @param pVM The cross context VM structure.
188	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
189	* @param uErrorCode CPU Error code.
190	* @param pRegFrame Trap register frame.
191	* NULL on DMA and other non CPU access.
192	* @param pvFault The fault address (cr2).
193	* @param GCPhysFault The GC physical address corresponding to pvFault.
194	* @param pvUser User argument.
195	* @thread EMT(pVCpu)
196	*/
197	typedef DECLCALLBACK(VBOXSTRICTRC) FNPGMRZPHYSPFHANDLER(PVM pVM, PVMCPU pVCpu, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame,
198	RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser);
199	/** Pointer to PGM access callback. */
200	typedef FNPGMRZPHYSPFHANDLER *PFNPGMRZPHYSPFHANDLER;
201
202
203	/**
204	* Access handler callback for physical access handler ranges.
205	*
206	* The handler can not raise any faults, it's mainly for monitoring write access
207	* to certain pages (like MMIO).
208	*
209	* @returns Strict VBox status code in ring-0 and raw-mode context, in ring-3
210	* the only supported informational status code is
211	* VINF_PGM_HANDLER_DO_DEFAULT.
212	* @retval VINF_SUCCESS if the handler have carried out the operation.
213	* @retval VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the
214	* access operation.
215	* @retval VINF_EM_XXX in ring-0 and raw-mode context.
216	*
217	* @param pVM The cross context VM structure.
218	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
219	* @param GCPhys The physical address the guest is writing to.
220	* @param pvPhys The HC mapping of that address.
221	* @param pvBuf What the guest is reading/writing.
222	* @param cbBuf How much it's reading/writing.
223	* @param enmAccessType The access type.
224	* @param enmOrigin The origin of this call.
225	* @param pvUser User argument.
226	* @thread EMT(pVCpu)
227	*/
228	typedef DECLCALLBACK(VBOXSTRICTRC) FNPGMPHYSHANDLER(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void pvPhys, void pvBuf, size_t cbBuf,
229	PGMACCESSTYPE enmAccessType, PGMACCESSORIGIN enmOrigin, void *pvUser);
230	/** Pointer to PGM access callback. */
231	typedef FNPGMPHYSHANDLER *PFNPGMPHYSHANDLER;
232
233
234	/**
235	* Virtual access handler type.
236	*/
237	typedef enum PGMVIRTHANDLERKIND
238	{
239	/** Write access handled. */
240	PGMVIRTHANDLERKIND_WRITE = 1,
241	/** All access handled. */
242	PGMVIRTHANDLERKIND_ALL,
243	/** Hypervisor write access handled.
244	* This is used to catch the guest trying to write to LDT, TSS and any other
245	* system structure which the brain dead intel guys let unprivilegde code find. */
246	PGMVIRTHANDLERKIND_HYPERVISOR
247	} PGMVIRTHANDLERKIND;
248
249	/**
250	* \#PF handler callback for virtual access handler ranges, RC.
251	*
252	* Important to realize that a physical page in a range can have aliases, and
253	* for ALL and WRITE handlers these will also trigger.
254	*
255	* @returns Strict VBox status code (appropriate for raw-mode).
256	* @param pVM The cross context VM structure.
257	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
258	* @param uErrorCode CPU Error code (X86_TRAP_PF_XXX).
259	* @param pRegFrame Trap register frame.
260	* @param pvFault The fault address (cr2).
261	* @param pvRange The base address of the handled virtual range.
262	* @param offRange The offset of the access into this range.
263	* (If it's a EIP range this is the EIP, if not it's pvFault.)
264	* @param pvUser User argument.
265	* @thread EMT(pVCpu)
266	*/
267	typedef DECLCALLBACK(VBOXSTRICTRC) FNPGMRCVIRTPFHANDLER(PVM pVM, PVMCPU pVCpu, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame,
268	RTGCPTR pvFault, RTGCPTR pvRange, uintptr_t offRange, void *pvUser);
269	/** Pointer to PGM access callback. */
270	typedef FNPGMRCVIRTPFHANDLER *PFNPGMRCVIRTPFHANDLER;
271
272	/**
273	* Access handler callback for virtual access handler ranges.
274	*
275	* Important to realize that a physical page in a range can have aliases, and
276	* for ALL and WRITE handlers these will also trigger.
277	*
278	* @returns VINF_SUCCESS if the handler have carried out the operation.
279	* @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
280	* @param pVM The cross context VM structure.
281	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
282	* @param GCPtr The virtual address the guest is writing to. This
283	* is the registered address corresponding to the
284	* access, so no aliasing trouble here.
285	* @param pvPtr The HC mapping of that address.
286	* @param pvBuf What the guest is reading/writing.
287	* @param cbBuf How much it's reading/writing.
288	* @param enmAccessType The access type.
289	* @param enmOrigin Who is calling.
290	* @param pvUser User argument.
291	* @thread EMT(pVCpu)
292	*/
293	typedef DECLCALLBACK(VBOXSTRICTRC) FNPGMVIRTHANDLER(PVM pVM, PVMCPU pVCpu, RTGCPTR GCPtr, void pvPtr, void pvBuf, size_t cbBuf,
294	PGMACCESSTYPE enmAccessType, PGMACCESSORIGIN enmOrigin, void *pvUser);
295	/** Pointer to PGM access callback. */
296	typedef FNPGMVIRTHANDLER *PFNPGMVIRTHANDLER;
297
298	/**
299	* \#PF Handler callback for invalidation of virtual access handler ranges.
300	*
301	* @param pVM The cross context VM structure.
302	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
303	* @param GCPtr The virtual address the guest has changed.
304	* @param pvUser User argument.
305	* @thread EMT(pVCpu)
306	*
307	* @todo FNPGMR3VIRTINVALIDATE will not actually be called! It was introduced
308	* in r13179 (1.1) and stopped working with r13806 (PGMPool merge,
309	* v1.2), exactly a month later.
310	*/
311	typedef DECLCALLBACK(int) FNPGMR3VIRTINVALIDATE(PVM pVM, PVMCPU pVCpu, RTGCPTR GCPtr, void *pvUser);
312	/** Pointer to PGM invalidation callback. */
313	typedef FNPGMR3VIRTINVALIDATE *PFNPGMR3VIRTINVALIDATE;
314
315
316	/**
317	* PGMR3PhysEnumDirtyFTPages callback for syncing dirty physical pages
318	*
319	* @param pVM The cross context VM structure.
320	* @param GCPhys GC physical address
321	* @param pRange HC virtual address of the page(s)
322	* @param cbRange Size of the dirty range in bytes.
323	* @param pvUser User argument.
324	*/
325	typedef DECLCALLBACK(int) FNPGMENUMDIRTYFTPAGES(PVM pVM, RTGCPHYS GCPhys, uint8_t pRange, unsigned cbRange, void pvUser);
326	/** Pointer to PGMR3PhysEnumDirtyFTPages callback. */
327	typedef FNPGMENUMDIRTYFTPAGES *PFNPGMENUMDIRTYFTPAGES;
328
329
330	/**
331	* Paging mode.
332	*
333	* @note Part of saved state. Change with extreme care.
334	*/
335	typedef enum PGMMODE
336	{
337	/** The usual invalid value. */
338	PGMMODE_INVALID = 0,
339	/** Real mode. */
340	PGMMODE_REAL,
341	/** Protected mode, no paging. */
342	PGMMODE_PROTECTED,
343	/** 32-bit paging. */
344	PGMMODE_32_BIT,
345	/** PAE paging. */
346	PGMMODE_PAE,
347	/** PAE paging with NX enabled. */
348	PGMMODE_PAE_NX,
349	/** 64-bit AMD paging (long mode). */
350	PGMMODE_AMD64,
351	/** 64-bit AMD paging (long mode) with NX enabled. */
352	PGMMODE_AMD64_NX,
353	/** Nested paging mode (shadow only; guest physical to host physical). */
354	PGMMODE_NESTED,
355	/** Extended paging (Intel) mode. */
356	PGMMODE_EPT,
357	/** The max number of modes */
358	PGMMODE_MAX,
359	/** 32bit hackishness. */
360	PGMMODE_32BIT_HACK = 0x7fffffff
361	} PGMMODE;
362
363	/** Macro for checking if the guest is using paging.
364	* @param enmMode PGMMODE_*.
365	* @remark ASSUMES certain order of the PGMMODE_* values.
366	*/
367	#define PGMMODE_WITH_PAGING(enmMode) ((enmMode) >= PGMMODE_32_BIT)
368
369	/** Macro for checking if it's one of the long mode modes.
370	* @param enmMode PGMMODE_*.
371	*/
372	#define PGMMODE_IS_LONG_MODE(enmMode) ((enmMode) == PGMMODE_AMD64_NX \|\| (enmMode) == PGMMODE_AMD64)
373
374	/**
375	* Is the ROM mapped (true) or is the shadow RAM mapped (false).
376	*
377	* @returns boolean.
378	* @param enmProt The PGMROMPROT value, must be valid.
379	*/
380	#define PGMROMPROT_IS_ROM(enmProt) \
381	( (enmProt) == PGMROMPROT_READ_ROM_WRITE_IGNORE \
382	\|\| (enmProt) == PGMROMPROT_READ_ROM_WRITE_RAM )
383
384
385	VMMDECL(bool) PGMIsLockOwner(PVM pVM);
386
387	VMMDECL(int) PGMRegisterStringFormatTypes(void);
388	VMMDECL(void) PGMDeregisterStringFormatTypes(void);
389	VMMDECL(RTHCPHYS) PGMGetHyperCR3(PVMCPU pVCpu);
390	VMMDECL(RTHCPHYS) PGMGetNestedCR3(PVMCPU pVCpu, PGMMODE enmShadowMode);
391	VMMDECL(RTHCPHYS) PGMGetInterHCCR3(PVM pVM);
392	VMMDECL(RTHCPHYS) PGMGetInterRCCR3(PVM pVM, PVMCPU pVCpu);
393	VMMDECL(RTHCPHYS) PGMGetInter32BitCR3(PVM pVM);
394	VMMDECL(RTHCPHYS) PGMGetInterPaeCR3(PVM pVM);
395	VMMDECL(RTHCPHYS) PGMGetInterAmd64CR3(PVM pVM);
396	VMMDECL(int) PGMTrap0eHandler(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault);
397	VMMDECL(int) PGMPrefetchPage(PVMCPU pVCpu, RTGCPTR GCPtrPage);
398	VMMDECL(int) PGMVerifyAccess(PVMCPU pVCpu, RTGCPTR Addr, uint32_t cbSize, uint32_t fAccess);
399	VMMDECL(int) PGMIsValidAccess(PVMCPU pVCpu, RTGCPTR Addr, uint32_t cbSize, uint32_t fAccess);
400	VMMDECL(VBOXSTRICTRC) PGMInterpretInstruction(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault);
401	VMMDECL(int) PGMMap(PVM pVM, RTGCPTR GCPtr, RTHCPHYS HCPhys, uint32_t cbPages, unsigned fFlags);
402	VMMDECL(int) PGMMapGetPage(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys);
403	VMMDECL(int) PGMMapSetPage(PVM pVM, RTGCPTR GCPtr, uint64_t cb, uint64_t fFlags);
404	VMMDECL(int) PGMMapModifyPage(PVM pVM, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask);
405	#ifndef IN_RING0
406	VMMDECL(bool) PGMMapHasConflicts(PVM pVM);
407	#endif
408	#ifdef VBOX_STRICT
409	VMMDECL(void) PGMMapCheck(PVM pVM);
410	#endif
411	VMMDECL(int) PGMShwGetPage(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys);
412	VMMDECL(int) PGMShwMakePageReadonly(PVMCPU pVCpu, RTGCPTR GCPtr, uint32_t fFlags);
413	VMMDECL(int) PGMShwMakePageWritable(PVMCPU pVCpu, RTGCPTR GCPtr, uint32_t fFlags);
414	VMMDECL(int) PGMShwMakePageNotPresent(PVMCPU pVCpu, RTGCPTR GCPtr, uint32_t fFlags);
415	/** @name Flags for PGMShwMakePageReadonly, PGMShwMakePageWritable and
416	* PGMShwMakePageNotPresent
417	* @{ */
418	/** The call is from an access handler for dealing with the a faulting write
419	* operation. The virtual address is within the same page. */
420	#define PGM_MK_PG_IS_WRITE_FAULT RT_BIT(0)
421	/** The page is an MMIO2. */
422	#define PGM_MK_PG_IS_MMIO2 RT_BIT(1)
423	/** @}*/
424	VMMDECL(int) PGMGstGetPage(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys);
425	VMMDECL(bool) PGMGstIsPagePresent(PVMCPU pVCpu, RTGCPTR GCPtr);
426	VMMDECL(int) PGMGstSetPage(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cb, uint64_t fFlags);
427	VMMDECL(int) PGMGstModifyPage(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask);
428	VMM_INT_DECL(int) PGMGstGetPaePdpes(PVMCPU pVCpu, PX86PDPE paPdpes);
429	VMM_INT_DECL(void) PGMGstUpdatePaePdpes(PVMCPU pVCpu, PCX86PDPE paPdpes);
430
431	VMMDECL(int) PGMInvalidatePage(PVMCPU pVCpu, RTGCPTR GCPtrPage);
432	VMMDECL(int) PGMFlushTLB(PVMCPU pVCpu, uint64_t cr3, bool fGlobal);
433	VMMDECL(int) PGMSyncCR3(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal);
434	VMMDECL(int) PGMUpdateCR3(PVMCPU pVCpu, uint64_t cr3);
435	VMMDECL(int) PGMChangeMode(PVMCPU pVCpu, uint64_t cr0, uint64_t cr4, uint64_t efer);
436	VMMDECL(void) PGMCr0WpEnabled(PVMCPU pVCpu);
437	VMMDECL(PGMMODE) PGMGetGuestMode(PVMCPU pVCpu);
438	VMMDECL(PGMMODE) PGMGetShadowMode(PVMCPU pVCpu);
439	VMMDECL(PGMMODE) PGMGetHostMode(PVM pVM);
440	VMMDECL(const char *) PGMGetModeName(PGMMODE enmMode);
441	VMM_INT_DECL(void) PGMNotifyNxeChanged(PVMCPU pVCpu, bool fNxe);
442	VMMDECL(bool) PGMHasDirtyPages(PVM pVM);
443
444	/** PGM physical access handler type registration handle (heap offset, valid
445	* cross contexts without needing fixing up). Callbacks and handler type is
446	* associated with this and it is shared by all handler registrations. */
447	typedef uint32_t PGMPHYSHANDLERTYPE;
448	/** Pointer to a PGM physical handler type registration handle. */
449	typedef PGMPHYSHANDLERTYPE *PPGMPHYSHANDLERTYPE;
450	/** NIL value for PGM physical access handler type handle. */
451	#define NIL_PGMPHYSHANDLERTYPE UINT32_MAX
452	VMMDECL(uint32_t) PGMHandlerPhysicalTypeRelease(PVM pVM, PGMPHYSHANDLERTYPE hType);
453	VMMDECL(uint32_t) PGMHandlerPhysicalTypeRetain(PVM pVM, PGMPHYSHANDLERTYPE hType);
454
455	VMMDECL(int) PGMHandlerPhysicalRegister(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS GCPhysLast, PGMPHYSHANDLERTYPE hType,
456	RTR3PTR pvUserR3, RTR0PTR pvUserR0, RTRCPTR pvUserRC,
457	R3PTRTYPE(const char *) pszDesc);
458	VMMDECL(int) PGMHandlerPhysicalModify(PVM pVM, RTGCPHYS GCPhysCurrent, RTGCPHYS GCPhys, RTGCPHYS GCPhysLast);
459	VMMDECL(int) PGMHandlerPhysicalDeregister(PVM pVM, RTGCPHYS GCPhys);
460	VMMDECL(int) PGMHandlerPhysicalChangeUserArgs(PVM pVM, RTGCPHYS GCPhys, RTR3PTR pvUserR3, RTR0PTR pvUserR0, RTRCPTR pvUserRC);
461	VMMDECL(int) PGMHandlerPhysicalSplit(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS GCPhysSplit);
462	VMMDECL(int) PGMHandlerPhysicalJoin(PVM pVM, RTGCPHYS GCPhys1, RTGCPHYS GCPhys2);
463	VMMDECL(int) PGMHandlerPhysicalPageTempOff(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS GCPhysPage);
464	VMMDECL(int) PGMHandlerPhysicalPageAlias(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS GCPhysPage, RTGCPHYS GCPhysPageRemap);
465	VMMDECL(int) PGMHandlerPhysicalPageAliasHC(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS GCPhysPage, RTHCPHYS HCPhysPageRemap);
466	VMMDECL(int) PGMHandlerPhysicalReset(PVM pVM, RTGCPHYS GCPhys);
467	VMMDECL(bool) PGMHandlerPhysicalIsRegistered(PVM pVM, RTGCPHYS GCPhys);
468
469	/** PGM virtual access handler type registration handle (heap offset, valid
470	* cross contexts without needing fixing up). Callbacks and handler type is
471	* associated with this and it is shared by all handler registrations. */
472	typedef uint32_t PGMVIRTHANDLERTYPE;
473	/** Pointer to a PGM virtual handler type registration handle. */
474	typedef PGMVIRTHANDLERTYPE *PPGMVIRTHANDLERTYPE;
475	/** NIL value for PGM virtual access handler type handle. */
476	#define NIL_PGMVIRTHANDLERTYPE UINT32_MAX
477	#ifdef VBOX_WITH_RAW_MODE
478	VMM_INT_DECL(uint32_t) PGMHandlerVirtualTypeRelease(PVM pVM, PGMVIRTHANDLERTYPE hType);
479	VMM_INT_DECL(uint32_t) PGMHandlerVirtualTypeRetain(PVM pVM, PGMVIRTHANDLERTYPE hType);
480	VMM_INT_DECL(bool) PGMHandlerVirtualIsRegistered(PVM pVM, RTGCPTR GCPtr);
481	#endif
482
483
484	/**
485	* Page type.
486	*
487	* @remarks This enum has to fit in a 3-bit field (see PGMPAGE::u3Type).
488	* @remarks This is used in the saved state, so changes to it requires bumping
489	* the saved state version.
490	* @todo So, convert to \#defines!
491	*/
492	typedef enum PGMPAGETYPE
493	{
494	/** The usual invalid zero entry. */
495	PGMPAGETYPE_INVALID = 0,
496	/** RAM page. (RWX) */
497	PGMPAGETYPE_RAM,
498	/** MMIO2 page. (RWX) */
499	PGMPAGETYPE_MMIO2,
500	/** MMIO2 page aliased over an MMIO page. (RWX)
501	* See PGMHandlerPhysicalPageAlias(). */
502	PGMPAGETYPE_MMIO2_ALIAS_MMIO,
503	/** Special page aliased over an MMIO page. (RWX)
504	* See PGMHandlerPhysicalPageAliasHC(), but this is generally only used for
505	* VT-x's APIC access page at the moment. Treated as MMIO by everyone except
506	* the shadow paging code. */
507	PGMPAGETYPE_SPECIAL_ALIAS_MMIO,
508	/** Shadowed ROM. (RWX) */
509	PGMPAGETYPE_ROM_SHADOW,
510	/** ROM page. (R-X) */
511	PGMPAGETYPE_ROM,
512	/** MMIO page. (---) */
513	PGMPAGETYPE_MMIO,
514	/** End of valid entries. */
515	PGMPAGETYPE_END
516	} PGMPAGETYPE;
517	AssertCompile(PGMPAGETYPE_END == 8);
518
519	VMM_INT_DECL(PGMPAGETYPE) PGMPhysGetPageType(PVM pVM, RTGCPHYS GCPhys);
520
521	VMM_INT_DECL(int) PGMPhysGCPhys2HCPhys(PVM pVM, RTGCPHYS GCPhys, PRTHCPHYS pHCPhys);
522	VMM_INT_DECL(int) PGMPhysGCPtr2HCPhys(PVMCPU pVCpu, RTGCPTR GCPtr, PRTHCPHYS pHCPhys);
523	VMM_INT_DECL(int) PGMPhysGCPhys2CCPtr(PVM pVM, RTGCPHYS GCPhys, void **ppv, PPGMPAGEMAPLOCK pLock);
524	VMM_INT_DECL(int) PGMPhysGCPhys2CCPtrReadOnly(PVM pVM, RTGCPHYS GCPhys, void const **ppv, PPGMPAGEMAPLOCK pLock);
525	VMM_INT_DECL(int) PGMPhysGCPtr2CCPtr(PVMCPU pVCpu, RTGCPTR GCPtr, void **ppv, PPGMPAGEMAPLOCK pLock);
526	VMM_INT_DECL(int) PGMPhysGCPtr2CCPtrReadOnly(PVMCPU pVCpu, RTGCPTR GCPtr, void const **ppv, PPGMPAGEMAPLOCK pLock);
527
528	VMMDECL(bool) PGMPhysIsA20Enabled(PVMCPU pVCpu);
529	VMMDECL(bool) PGMPhysIsGCPhysValid(PVM pVM, RTGCPHYS GCPhys);
530	VMMDECL(bool) PGMPhysIsGCPhysNormal(PVM pVM, RTGCPHYS GCPhys);
531	VMMDECL(int) PGMPhysGCPtr2GCPhys(PVMCPU pVCpu, RTGCPTR GCPtr, PRTGCPHYS pGCPhys);
532	VMMDECL(void) PGMPhysReleasePageMappingLock(PVM pVM, PPGMPAGEMAPLOCK pLock);
533
534	/** @def PGM_PHYS_RW_IS_SUCCESS
535	* Check whether a PGMPhysRead, PGMPhysWrite, PGMPhysReadGCPtr or
536	* PGMPhysWriteGCPtr call completed the given task.
537	*
538	* @returns true if completed, false if not.
539	* @param a_rcStrict The status code.
540	* @sa IOM_SUCCESS
541	*/
542	#ifdef IN_RING3
543	# define PGM_PHYS_RW_IS_SUCCESS(a_rcStrict) \
544	( (a_rcStrict) == VINF_SUCCESS \
545	\|\| (a_rcStrict) == VINF_EM_DBG_STOP \
546	\|\| (a_rcStrict) == VINF_EM_DBG_EVENT \
547	\|\| (a_rcStrict) == VINF_EM_DBG_BREAKPOINT \
548	)
549	#elif defined(IN_RING0)
550	# define PGM_PHYS_RW_IS_SUCCESS(a_rcStrict) \
551	( (a_rcStrict) == VINF_SUCCESS \
552	\|\| (a_rcStrict) == VINF_IOM_R3_MMIO_COMMIT_WRITE \
553	\|\| (a_rcStrict) == VINF_EM_OFF \
554	\|\| (a_rcStrict) == VINF_EM_SUSPEND \
555	\|\| (a_rcStrict) == VINF_EM_RESET \
556	\|\| (a_rcStrict) == VINF_EM_HALT \
557	\|\| (a_rcStrict) == VINF_EM_DBG_STOP \
558	\|\| (a_rcStrict) == VINF_EM_DBG_EVENT \
559	\|\| (a_rcStrict) == VINF_EM_DBG_BREAKPOINT \
560	)
561	#elif defined(IN_RC)
562	# define PGM_PHYS_RW_IS_SUCCESS(a_rcStrict) \
563	( (a_rcStrict) == VINF_SUCCESS \
564	\|\| (a_rcStrict) == VINF_IOM_R3_MMIO_COMMIT_WRITE \
565	\|\| (a_rcStrict) == VINF_EM_OFF \
566	\|\| (a_rcStrict) == VINF_EM_SUSPEND \
567	\|\| (a_rcStrict) == VINF_EM_RESET \
568	\|\| (a_rcStrict) == VINF_EM_HALT \
569	\|\| (a_rcStrict) == VINF_SELM_SYNC_GDT \
570	\|\| (a_rcStrict) == VINF_EM_RAW_EMULATE_INSTR_GDT_FAULT \
571	\|\| (a_rcStrict) == VINF_EM_DBG_STOP \
572	\|\| (a_rcStrict) == VINF_EM_DBG_EVENT \
573	\|\| (a_rcStrict) == VINF_EM_DBG_BREAKPOINT \
574	)
575	#endif
576	/** @def PGM_PHYS_RW_DO_UPDATE_STRICT_RC
577	* Updates the return code with a new result.
578	*
579	* Both status codes must be successes according to PGM_PHYS_RW_IS_SUCCESS.
580	*
581	* @param a_rcStrict The current return code, to be updated.
582	* @param a_rcStrict2 The new return code to merge in.
583	*/
584	#ifdef IN_RING3
585	# define PGM_PHYS_RW_DO_UPDATE_STRICT_RC(a_rcStrict, a_rcStrict2) \
586	do { \
587	Assert(rcStrict == VINF_SUCCESS); \
588	Assert(rcStrict2 == VINF_SUCCESS); \
589	} while (0)
590	#elif defined(IN_RING0)
591	# define PGM_PHYS_RW_DO_UPDATE_STRICT_RC(a_rcStrict, a_rcStrict2) \
592	do { \
593	Assert(PGM_PHYS_RW_IS_SUCCESS(rcStrict)); \
594	Assert(PGM_PHYS_RW_IS_SUCCESS(rcStrict2)); \
595	AssertCompile(VINF_IOM_R3_MMIO_COMMIT_WRITE > VINF_EM_LAST); \
596	if ((a_rcStrict2) == VINF_SUCCESS \|\| (a_rcStrict) == (a_rcStrict2)) \
597	{ /* likely */ } \
598	else if ( (a_rcStrict) == VINF_SUCCESS \
599	\|\| (a_rcStrict) > (a_rcStrict2)) \
600	(a_rcStrict) = (a_rcStrict2); \
601	} while (0)
602	#elif defined(IN_RC)
603	# define PGM_PHYS_RW_DO_UPDATE_STRICT_RC(a_rcStrict, a_rcStrict2) \
604	do { \
605	Assert(PGM_PHYS_RW_IS_SUCCESS(rcStrict)); \
606	Assert(PGM_PHYS_RW_IS_SUCCESS(rcStrict2)); \
607	AssertCompile(VINF_SELM_SYNC_GDT > VINF_EM_LAST); \
608	AssertCompile(VINF_EM_RAW_EMULATE_INSTR_GDT_FAULT > VINF_EM_LAST); \
609	AssertCompile(VINF_EM_RAW_EMULATE_INSTR_GDT_FAULT < VINF_SELM_SYNC_GDT); \
610	AssertCompile(VINF_IOM_R3_MMIO_COMMIT_WRITE > VINF_EM_LAST); \
611	AssertCompile(VINF_IOM_R3_MMIO_COMMIT_WRITE > VINF_SELM_SYNC_GDT); \
612	AssertCompile(VINF_IOM_R3_MMIO_COMMIT_WRITE > VINF_EM_RAW_EMULATE_INSTR_GDT_FAULT); \
613	if ((a_rcStrict2) == VINF_SUCCESS \|\| (a_rcStrict) == (a_rcStrict2)) \
614	{ /* likely */ } \
615	else if ((a_rcStrict) == VINF_SUCCESS) \
616	(a_rcStrict) = (a_rcStrict2); \
617	else if ( ( (a_rcStrict) > (a_rcStrict2) \
618	&& ( (a_rcStrict2) <= VINF_EM_RESET \
619	\|\| (a_rcStrict) != VINF_EM_RAW_EMULATE_INSTR_GDT_FAULT) ) \
620	\|\| ( (a_rcStrict2) == VINF_EM_RAW_EMULATE_INSTR_GDT_FAULT \
621	&& (a_rcStrict) > VINF_EM_RESET) ) \
622	(a_rcStrict) = (a_rcStrict2); \
623	} while (0)
624	#endif
625
626	VMMDECL(VBOXSTRICTRC) PGMPhysRead(PVM pVM, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead, PGMACCESSORIGIN enmOrigin);
627	VMMDECL(VBOXSTRICTRC) PGMPhysWrite(PVM pVM, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite, PGMACCESSORIGIN enmOrigin);
628	VMMDECL(VBOXSTRICTRC) PGMPhysReadGCPtr(PVMCPU pVCpu, void *pvDst, RTGCPTR GCPtrSrc, size_t cb, PGMACCESSORIGIN enmOrigin);
629	VMMDECL(VBOXSTRICTRC) PGMPhysWriteGCPtr(PVMCPU pVCpu, RTGCPTR GCPtrDst, const void *pvSrc, size_t cb, PGMACCESSORIGIN enmOrigin);
630
631	VMMDECL(int) PGMPhysSimpleReadGCPhys(PVM pVM, void *pvDst, RTGCPHYS GCPhysSrc, size_t cb);
632	VMMDECL(int) PGMPhysSimpleWriteGCPhys(PVM pVM, RTGCPHYS GCPhysDst, const void *pvSrc, size_t cb);
633	VMMDECL(int) PGMPhysSimpleReadGCPtr(PVMCPU pVCpu, void *pvDst, RTGCPTR GCPtrSrc, size_t cb);
634	VMMDECL(int) PGMPhysSimpleWriteGCPtr(PVMCPU pVCpu, RTGCPTR GCPtrDst, const void *pvSrc, size_t cb);
635	VMMDECL(int) PGMPhysSimpleDirtyWriteGCPtr(PVMCPU pVCpu, RTGCPTR GCPtrDst, const void *pvSrc, size_t cb);
636	VMMDECL(int) PGMPhysInterpretedRead(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, void *pvDst, RTGCPTR GCPtrSrc, size_t cb);
637	VMMDECL(int) PGMPhysInterpretedReadNoHandlers(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, void *pvDst, RTGCUINTPTR GCPtrSrc, size_t cb, bool fRaiseTrap);
638	VMMDECL(int) PGMPhysInterpretedWriteNoHandlers(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, RTGCPTR GCPtrDst, void const *pvSrc, size_t cb, bool fRaiseTrap);
639
640	VMM_INT_DECL(int) PGMPhysIemGCPhys2Ptr(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, bool fWritable, bool fByPassHandlers, void **ppv, PPGMPAGEMAPLOCK pLock);
641	VMM_INT_DECL(int) PGMPhysIemQueryAccess(PVM pVM, RTGCPHYS GCPhys, bool fWritable, bool fByPassHandlers);
642	VMM_INT_DECL(int) PGMPhysIemGCPhys2PtrNoLock(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, uint64_t const volatile *puTlbPhysRev,
643	#if defined(IN_RC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
644	R3PTRTYPE(uint8_t ) ppb,
645	#else
646	R3R0PTRTYPE(uint8_t ) ppb,
647	#endif
648	uint64_t *pfTlb);
649	/** @name Flags returned by PGMPhysIemGCPhys2PtrNoLock
650	* @{ */
651	#define PGMIEMGCPHYS2PTR_F_NO_WRITE RT_BIT_32(3) /*< Not writable (IEMTLBE_F_PG_NO_WRITE). /
652	#define PGMIEMGCPHYS2PTR_F_NO_READ RT_BIT_32(4) /*< Not readable (IEMTLBE_F_PG_NO_READ). /
653	#define PGMIEMGCPHYS2PTR_F_NO_MAPPINGR3 RT_BIT_32(7) /*< No ring-3 mapping (IEMTLBE_F_NO_MAPPINGR3). /
654	/** @} */
655
656	#ifdef VBOX_STRICT
657	VMMDECL(unsigned) PGMAssertHandlerAndFlagsInSync(PVM pVM);
658	VMMDECL(unsigned) PGMAssertNoMappingConflicts(PVM pVM);
659	VMMDECL(unsigned) PGMAssertCR3(PVM pVM, PVMCPU pVCpu, uint64_t cr3, uint64_t cr4);
660	#endif /* VBOX_STRICT */
661
662	#if defined(IN_RC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE)
663	VMMDECL(void) PGMRZDynMapStartAutoSet(PVMCPU pVCpu);
664	VMMDECL(void) PGMRZDynMapReleaseAutoSet(PVMCPU pVCpu);
665	VMMDECL(void) PGMRZDynMapFlushAutoSet(PVMCPU pVCpu);
666	VMMDECL(uint32_t) PGMRZDynMapPushAutoSubset(PVMCPU pVCpu);
667	VMMDECL(void) PGMRZDynMapPopAutoSubset(PVMCPU pVCpu, uint32_t iPrevSubset);
668	#endif
669
670	VMMDECL(int) PGMSetLargePageUsage(PVM pVM, bool fUseLargePages);
671
672	/**
673	* Query large page usage state
674	*
675	* @returns 0 - disabled, 1 - enabled
676	* @param pVM The cross context VM structure.
677	*/
678	#define PGMIsUsingLargePages(pVM) ((pVM)->fUseLargePages)
679
680
681	#ifdef IN_RC
682	/** @defgroup grp_pgm_gc The PGM Guest Context API
683	* @{
684	*/
685	VMMRCDECL(int) PGMRCDynMapInit(PVM pVM);
686	/** @} */
687	#endif /* IN_RC */
688
689
690	#ifdef IN_RING0
691	/** @defgroup grp_pgm_r0 The PGM Host Context Ring-0 API
692	* @{
693	*/
694	VMMR0_INT_DECL(int) PGMR0PhysAllocateHandyPages(PVM pVM, PVMCPU pVCpu);
695	VMMR0_INT_DECL(int) PGMR0PhysFlushHandyPages(PVM pVM, PVMCPU pVCpu);
696	VMMR0_INT_DECL(int) PGMR0PhysAllocateLargeHandyPage(PVM pVM, PVMCPU pVCpu);
697	VMMR0_INT_DECL(int) PGMR0PhysSetupIommu(PVM pVM);
698	VMMR0DECL(int) PGMR0SharedModuleCheck(PVM pVM, PGVM pGVM, VMCPUID idCpu, PGMMSHAREDMODULE pModule, PCRTGCPTR64 paRegionsGCPtrs);
699	VMMR0DECL(int) PGMR0Trap0eHandlerNestedPaging(PVM pVM, PVMCPU pVCpu, PGMMODE enmShwPagingMode, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPHYS pvFault);
700	VMMR0DECL(VBOXSTRICTRC) PGMR0Trap0eHandlerNPMisconfig(PVM pVM, PVMCPU pVCpu, PGMMODE enmShwPagingMode, PCPUMCTXCORE pRegFrame, RTGCPHYS GCPhysFault, uint32_t uErr);
701	# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
702	VMMR0DECL(int) PGMR0DynMapInit(void);
703	VMMR0DECL(void) PGMR0DynMapTerm(void);
704	VMMR0DECL(int) PGMR0DynMapInitVM(PVM pVM);
705	VMMR0DECL(void) PGMR0DynMapTermVM(PVM pVM);
706	VMMR0DECL(int) PGMR0DynMapAssertIntegrity(void);
707	VMMR0DECL(bool) PGMR0DynMapStartOrMigrateAutoSet(PVMCPU pVCpu);
708	VMMR0DECL(void) PGMR0DynMapMigrateAutoSet(PVMCPU pVCpu);
709	# endif
710	/** @} */
711	#endif /* IN_RING0 */
712
713
714
715	#ifdef IN_RING3
716	/** @defgroup grp_pgm_r3 The PGM Host Context Ring-3 API
717	* @{
718	*/
719	VMMR3DECL(int) PGMR3Init(PVM pVM);
720	VMMR3DECL(int) PGMR3InitDynMap(PVM pVM);
721	VMMR3DECL(int) PGMR3InitFinalize(PVM pVM);
722	VMMR3_INT_DECL(int) PGMR3InitCompleted(PVM pVM, VMINITCOMPLETED enmWhat);
723	VMMR3DECL(void) PGMR3Relocate(PVM pVM, RTGCINTPTR offDelta);
724	VMMR3DECL(void) PGMR3ResetCpu(PVM pVM, PVMCPU pVCpu);
725	VMMR3_INT_DECL(void) PGMR3Reset(PVM pVM);
726	VMMR3_INT_DECL(void) PGMR3ResetNoMorePhysWritesFlag(PVM pVM);
727	VMMR3_INT_DECL(void) PGMR3MemSetup(PVM pVM, bool fReset);
728	VMMR3DECL(int) PGMR3Term(PVM pVM);
729	VMMR3DECL(int) PGMR3LockCall(PVM pVM);
730	VMMR3DECL(int) PGMR3ChangeMode(PVM pVM, PVMCPU pVCpu, PGMMODE enmGuestMode);
731
732	VMMR3DECL(int) PGMR3PhysRegisterRam(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, const char *pszDesc);
733	VMMR3DECL(int) PGMR3PhysChangeMemBalloon(PVM pVM, bool fInflate, unsigned cPages, RTGCPHYS *paPhysPage);
734	VMMR3DECL(int) PGMR3PhysWriteProtectRAM(PVM pVM);
735	VMMR3DECL(int) PGMR3PhysEnumDirtyFTPages(PVM pVM, PFNPGMENUMDIRTYFTPAGES pfnEnum, void *pvUser);
736	VMMR3DECL(uint32_t) PGMR3PhysGetRamRangeCount(PVM pVM);
737	VMMR3DECL(int) PGMR3PhysGetRange(PVM pVM, uint32_t iRange, PRTGCPHYS pGCPhysStart, PRTGCPHYS pGCPhysLast,
738	const char *ppszDesc, bool pfIsMmio);
739	VMMR3DECL(int) PGMR3QueryMemoryStats(PUVM pUVM, uint64_t pcbTotalMem, uint64_t pcbPrivateMem, uint64_t pcbSharedMem, uint64_t pcbZeroMem);
740	VMMR3DECL(int) PGMR3QueryGlobalMemoryStats(PUVM pUVM, uint64_t pcbAllocMem, uint64_t pcbFreeMem, uint64_t pcbBallonedMem, uint64_t pcbSharedMem);
741
742	VMMR3DECL(int) PGMR3PhysMMIORegister(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, PGMPHYSHANDLERTYPE hType,
743	RTR3PTR pvUserR3, RTR0PTR pvUserR0, RTRCPTR pvUserRC, const char *pszDesc);
744	VMMR3DECL(int) PGMR3PhysMMIODeregister(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb);
745	VMMR3DECL(int) PGMR3PhysMMIO2Register(PVM pVM, PPDMDEVINS pDevIns, uint32_t iSubDev, uint32_t iRegion, RTGCPHYS cb, uint32_t fFlags, void *ppv, const char pszDesc);
746	VMMR3DECL(int) PGMR3PhysMMIOExPreRegister(PVM pVM, PPDMDEVINS pDevIns, uint32_t iSubDev, uint32_t iRegion, RTGCPHYS cbRegion, PGMPHYSHANDLERTYPE hType,
747	RTR3PTR pvUserR3, RTR0PTR pvUserR0, RTRCPTR pvUserRC, const char *pszDesc);
748	VMMR3DECL(int) PGMR3PhysMMIOExDeregister(PVM pVM, PPDMDEVINS pDevIns, uint32_t iSubDev, uint32_t iRegion);
749	VMMR3DECL(int) PGMR3PhysMMIOExMap(PVM pVM, PPDMDEVINS pDevIns, uint32_t iSubDev, uint32_t iRegion, RTGCPHYS GCPhys);
750	VMMR3DECL(int) PGMR3PhysMMIOExUnmap(PVM pVM, PPDMDEVINS pDevIns, uint32_t iSubDev, uint32_t iRegion, RTGCPHYS GCPhys);
751	VMMR3_INT_DECL(int) PGMR3PhysMMIOExReduce(PVM pVM, PPDMDEVINS pDevIns, uint32_t iSubDev, uint32_t iRegion, RTGCPHYS cbRegion);
752	VMMR3DECL(bool) PGMR3PhysMMIOExIsBase(PVM pVM, PPDMDEVINS pDevIns, RTGCPHYS GCPhys);
753	VMMR3_INT_DECL(int) PGMR3PhysMMIO2GetHCPhys(PVM pVM, PPDMDEVINS pDevIns, uint32_t iSubDev, uint32_t iRegion, RTGCPHYS off, PRTHCPHYS pHCPhys);
754	VMMR3_INT_DECL(int) PGMR3PhysMMIO2MapKernel(PVM pVM, PPDMDEVINS pDevIns, uint32_t iSubDev, uint32_t iRegion, RTGCPHYS off, RTGCPHYS cb, const char *pszDesc, PRTR0PTR pR0Ptr);
755
756	/** @name PGMR3PhysRegisterRom flags.
757	* @{ */
758	/** Inidicates that ROM shadowing should be enabled. */
759	#define PGMPHYS_ROM_FLAGS_SHADOWED RT_BIT_32(0)
760	/** Indicates that what pvBinary points to won't go away
761	* and can be used for strictness checks. */
762	#define PGMPHYS_ROM_FLAGS_PERMANENT_BINARY RT_BIT_32(1)
763	/** @} */
764
765	VMMR3DECL(int) PGMR3PhysRomRegister(PVM pVM, PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTGCPHYS cb,
766	const void pvBinary, uint32_t cbBinary, uint32_t fFlags, const char pszDesc);
767	VMMR3DECL(int) PGMR3PhysRomProtect(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, PGMROMPROT enmProt);
768	VMMR3DECL(int) PGMR3PhysRegister(PVM pVM, void pvRam, RTGCPHYS GCPhys, size_t cb, unsigned fFlags, const SUPPAGE paPages, const char *pszDesc);
769	VMMDECL(void) PGMR3PhysSetA20(PVMCPU pVCpu, bool fEnable);
770	/** @name PGMR3MapPT flags.
771	* @{ */
772	/** The mapping may be unmapped later. The default is permanent mappings. */
773	#define PGMR3MAPPT_FLAGS_UNMAPPABLE RT_BIT(0)
774	/** @} */
775	VMMR3DECL(int) PGMR3MapPT(PVM pVM, RTGCPTR GCPtr, uint32_t cb, uint32_t fFlags, PFNPGMRELOCATE pfnRelocate, void pvUser, const char pszDesc);
776	VMMR3DECL(int) PGMR3UnmapPT(PVM pVM, RTGCPTR GCPtr);
777	VMMR3DECL(int) PGMR3FinalizeMappings(PVM pVM);
778	VMMR3DECL(int) PGMR3MappingsSize(PVM pVM, uint32_t *pcb);
779	VMMR3DECL(int) PGMR3MappingsFix(PVM pVM, RTGCPTR GCPtrBase, uint32_t cb);
780	VMMR3DECL(int) PGMR3MappingsUnfix(PVM pVM);
781	VMMR3DECL(bool) PGMR3MappingsNeedReFixing(PVM pVM);
782	#if defined(VBOX_WITH_RAW_MODE) \|\| HC_ARCH_BITS == 32 /* (latter for 64-bit guests on 32-bit hosts) */
783	VMMR3DECL(int) PGMR3MapIntermediate(PVM pVM, RTUINTPTR Addr, RTHCPHYS HCPhys, unsigned cbPages);
784	#endif
785	VMMR3DECL(int) PGMR3MapRead(PVM pVM, void *pvDst, RTGCPTR GCPtrSrc, size_t cb);
786
787	VMMR3_INT_DECL(int) PGMR3HandlerPhysicalTypeRegisterEx(PVM pVM, PGMPHYSHANDLERKIND enmKind,
788	PFNPGMPHYSHANDLER pfnHandlerR3,
789	R0PTRTYPE(PFNPGMPHYSHANDLER) pfnHandlerR0,
790	R0PTRTYPE(PFNPGMRZPHYSPFHANDLER) pfnPfHandlerR0,
791	RCPTRTYPE(PFNPGMPHYSHANDLER) pfnHandlerRC,
792	RCPTRTYPE(PFNPGMRZPHYSPFHANDLER) pfnPfHandlerRC,
793	const char *pszDesc, PPGMPHYSHANDLERTYPE phType);
794	VMMR3DECL(int) PGMR3HandlerPhysicalTypeRegister(PVM pVM, PGMPHYSHANDLERKIND enmKind,
795	R3PTRTYPE(PFNPGMPHYSHANDLER) pfnHandlerR3,
796	const char pszModR0, const char pszHandlerR0, const char *pszPfHandlerR0,
797	const char pszModRC, const char pszHandlerRC, const char *pszPfHandlerRC,
798	const char *pszDesc,
799	PPGMPHYSHANDLERTYPE phType);
800	#ifdef VBOX_WITH_RAW_MODE
801	VMMR3_INT_DECL(int) PGMR3HandlerVirtualTypeRegisterEx(PVM pVM, PGMVIRTHANDLERKIND enmKind, bool fRelocUserRC,
802	PFNPGMR3VIRTINVALIDATE pfnInvalidateR3,
803	PFNPGMVIRTHANDLER pfnHandlerR3,
804	RCPTRTYPE(FNPGMVIRTHANDLER) pfnHandlerRC,
805	RCPTRTYPE(FNPGMRCVIRTPFHANDLER) pfnPfHandlerRC,
806	const char *pszDesc, PPGMVIRTHANDLERTYPE phType);
807	VMMR3_INT_DECL(int) PGMR3HandlerVirtualTypeRegister(PVM pVM, PGMVIRTHANDLERKIND enmKind, bool fRelocUserRC,
808	PFNPGMR3VIRTINVALIDATE pfnInvalidateR3,
809	PFNPGMVIRTHANDLER pfnHandlerR3,
810	const char pszHandlerRC, const char pszPfHandlerRC, const char *pszDesc,
811	PPGMVIRTHANDLERTYPE phType);
812	VMMR3_INT_DECL(int) PGMR3HandlerVirtualRegister(PVM pVM, PVMCPU pVCpu, PGMVIRTHANDLERTYPE hType, RTGCPTR GCPtr,
813	RTGCPTR GCPtrLast, void pvUserR3, RTRCPTR pvUserRC, const char pszDesc);
814	VMMR3_INT_DECL(int) PGMHandlerVirtualChangeType(PVM pVM, RTGCPTR GCPtr, PGMVIRTHANDLERTYPE hNewType);
815	VMMR3_INT_DECL(int) PGMHandlerVirtualDeregister(PVM pVM, PVMCPU pVCpu, RTGCPTR GCPtr, bool fHypervisor);
816	#endif
817	VMMR3DECL(int) PGMR3PoolGrow(PVM pVM);
818
819	VMMR3DECL(int) PGMR3PhysTlbGCPhys2Ptr(PVM pVM, RTGCPHYS GCPhys, bool fWritable, void **ppv);
820	VMMR3DECL(uint8_t) PGMR3PhysReadU8(PVM pVM, RTGCPHYS GCPhys, PGMACCESSORIGIN enmOrigin);
821	VMMR3DECL(uint16_t) PGMR3PhysReadU16(PVM pVM, RTGCPHYS GCPhys, PGMACCESSORIGIN enmOrigin);
822	VMMR3DECL(uint32_t) PGMR3PhysReadU32(PVM pVM, RTGCPHYS GCPhys, PGMACCESSORIGIN enmOrigin);
823	VMMR3DECL(uint64_t) PGMR3PhysReadU64(PVM pVM, RTGCPHYS GCPhys, PGMACCESSORIGIN enmOrigin);
824	VMMR3DECL(void) PGMR3PhysWriteU8(PVM pVM, RTGCPHYS GCPhys, uint8_t Value, PGMACCESSORIGIN enmOrigin);
825	VMMR3DECL(void) PGMR3PhysWriteU16(PVM pVM, RTGCPHYS GCPhys, uint16_t Value, PGMACCESSORIGIN enmOrigin);
826	VMMR3DECL(void) PGMR3PhysWriteU32(PVM pVM, RTGCPHYS GCPhys, uint32_t Value, PGMACCESSORIGIN enmOrigin);
827	VMMR3DECL(void) PGMR3PhysWriteU64(PVM pVM, RTGCPHYS GCPhys, uint64_t Value, PGMACCESSORIGIN enmOrigin);
828	VMMR3DECL(int) PGMR3PhysReadExternal(PVM pVM, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead, PGMACCESSORIGIN enmOrigin);
829	VMMR3DECL(int) PGMR3PhysWriteExternal(PVM pVM, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite, PGMACCESSORIGIN enmOrigin);
830	VMMR3DECL(int) PGMR3PhysGCPhys2CCPtrExternal(PVM pVM, RTGCPHYS GCPhys, void **ppv, PPGMPAGEMAPLOCK pLock);
831	VMMR3DECL(int) PGMR3PhysGCPhys2CCPtrReadOnlyExternal(PVM pVM, RTGCPHYS GCPhys, void const **ppv, PPGMPAGEMAPLOCK pLock);
832	VMMR3DECL(int) PGMR3PhysChunkMap(PVM pVM, uint32_t idChunk);
833	VMMR3DECL(void) PGMR3PhysChunkInvalidateTLB(PVM pVM);
834	VMMR3DECL(int) PGMR3PhysAllocateHandyPages(PVM pVM);
835	VMMR3DECL(int) PGMR3PhysAllocateLargeHandyPage(PVM pVM, RTGCPHYS GCPhys);
836
837	VMMR3DECL(int) PGMR3CheckIntegrity(PVM pVM);
838
839	VMMR3DECL(int) PGMR3DbgR3Ptr2GCPhys(PUVM pUVM, RTR3PTR R3Ptr, PRTGCPHYS pGCPhys);
840	VMMR3DECL(int) PGMR3DbgR3Ptr2HCPhys(PUVM pUVM, RTR3PTR R3Ptr, PRTHCPHYS pHCPhys);
841	VMMR3DECL(int) PGMR3DbgHCPhys2GCPhys(PUVM pUVM, RTHCPHYS HCPhys, PRTGCPHYS pGCPhys);
842	VMMR3_INT_DECL(int) PGMR3DbgReadGCPhys(PVM pVM, void pvDst, RTGCPHYS GCPhysSrc, size_t cb, uint32_t fFlags, size_t pcbRead);
843	VMMR3_INT_DECL(int) PGMR3DbgWriteGCPhys(PVM pVM, RTGCPHYS GCPhysDst, const void pvSrc, size_t cb, uint32_t fFlags, size_t pcbWritten);
844	VMMR3_INT_DECL(int) PGMR3DbgReadGCPtr(PVM pVM, void pvDst, RTGCPTR GCPtrSrc, size_t cb, uint32_t fFlags, size_t pcbRead);
845	VMMR3_INT_DECL(int) PGMR3DbgWriteGCPtr(PVM pVM, RTGCPTR GCPtrDst, void const pvSrc, size_t cb, uint32_t fFlags, size_t pcbWritten);
846	VMMR3_INT_DECL(int) PGMR3DbgScanPhysical(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cbRange, RTGCPHYS GCPhysAlign, const uint8_t *pabNeedle, size_t cbNeedle, PRTGCPHYS pGCPhysHit);
847	VMMR3_INT_DECL(int) PGMR3DbgScanVirtual(PVM pVM, PVMCPU pVCpu, RTGCPTR GCPtr, RTGCPTR cbRange, RTGCPTR GCPtrAlign, const uint8_t *pabNeedle, size_t cbNeedle, PRTGCUINTPTR pGCPhysHit);
848	VMMR3_INT_DECL(int) PGMR3DumpHierarchyShw(PVM pVM, uint64_t cr3, uint32_t fFlags, uint64_t u64FirstAddr, uint64_t u64LastAddr, uint32_t cMaxDepth, PCDBGFINFOHLP pHlp);
849	VMMR3_INT_DECL(int) PGMR3DumpHierarchyGst(PVM pVM, uint64_t cr3, uint32_t fFlags, RTGCPTR FirstAddr, RTGCPTR LastAddr, uint32_t cMaxDepth, PCDBGFINFOHLP pHlp);
850
851
852	/** @name Page sharing
853	* @{ */
854	VMMR3DECL(int) PGMR3SharedModuleRegister(PVM pVM, VBOXOSFAMILY enmGuestOS, char pszModuleName, char pszVersion,
855	RTGCPTR GCBaseAddr, uint32_t cbModule,
856	uint32_t cRegions, VMMDEVSHAREDREGIONDESC const *paRegions);
857	VMMR3DECL(int) PGMR3SharedModuleUnregister(PVM pVM, char pszModuleName, char pszVersion,
858	RTGCPTR GCBaseAddr, uint32_t cbModule);
859	VMMR3DECL(int) PGMR3SharedModuleCheckAll(PVM pVM);
860	VMMR3DECL(int) PGMR3SharedModuleGetPageState(PVM pVM, RTGCPTR GCPtrPage, bool pfShared, uint64_t pfPageFlags);
861	/** @} */
862
863	/** @} */
864	#endif /* IN_RING3 */
865
866	RT_C_DECLS_END
867
868	/** @} */
869	#endif
870

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source: vbox/trunk/include/VBox/vmm/pgm.h@ 67937

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