pgm.h@ 80118

Last change on this file since 80118 was 80118, checked in by vboxsync, 6 years ago
VMM: Kicking out raw-mode and 32-bit hosts - MM, PGM, ++. bugref:9517 bugref:9511
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1	/** @file
2	* PGM - Page Monitor / Monitor.
3	*/
4
5	/*
6	* Copyright (C) 2006-2019 Oracle Corporation
7	*
8	* This file is part of VirtualBox Open Source Edition (OSE), as
9	* available from http://www.virtualbox.org. This file is free software;
10	* you can redistribute it and/or modify it under the terms of the GNU
11	* General Public License (GPL) as published by the Free Software
12	* Foundation, in version 2 as it comes in the "COPYING" file of the
13	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15	*
16	* The contents of this file may alternatively be used under the terms
17	* of the Common Development and Distribution License Version 1.0
18	* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19	* VirtualBox OSE distribution, in which case the provisions of the
20	* CDDL are applicable instead of those of the GPL.
21	*
22	* You may elect to license modified versions of this file under the
23	* terms and conditions of either the GPL or the CDDL or both.
24	*/
25
26	#ifndef VBOX_INCLUDED_vmm_pgm_h
27	#define VBOX_INCLUDED_vmm_pgm_h
28	#ifndef RT_WITHOUT_PRAGMA_ONCE
29	# pragma once
30	#endif
31
32	#include <VBox/types.h>
33	#include <VBox/sup.h>
34	#include <VBox/vmm/vmapi.h>
35	#include <VBox/vmm/gmm.h> /* for PGMMREGISTERSHAREDMODULEREQ */
36	#include <iprt/x86.h>
37	#include <VBox/param.h>
38
39	RT_C_DECLS_BEGIN
40
41	/** @defgroup grp_pgm The Page Monitor / Manager API
42	* @ingroup grp_vmm
43	* @{
44	*/
45
46	/**
47	* FNPGMRELOCATE callback mode.
48	*/
49	typedef enum PGMRELOCATECALL
50	{
51	/** The callback is for checking if the suggested address is suitable. */
52	PGMRELOCATECALL_SUGGEST = 1,
53	/** The callback is for executing the relocation. */
54	PGMRELOCATECALL_RELOCATE
55	} PGMRELOCATECALL;
56
57
58	/** No guest context mappings (might be removed entirely later, if we don't
59	* need it again (see new raw-mode ideas)).
60	* @internal */
61	#define PGM_WITHOUT_MAPPINGS
62
63
64	/**
65	* Callback function which will be called when PGM is trying to find
66	* a new location for the mapping.
67	*
68	* The callback is called in two modes, 1) the check mode and 2) the relocate mode.
69	* In 1) the callback should say if it objects to a suggested new location. If it
70	* accepts the new location, it is called again for doing it's relocation.
71	*
72	*
73	* @returns true if the location is ok.
74	* @returns false if another location should be found.
75	* @param pVM The cross context VM structure.
76	* @param GCPtrOld The old virtual address.
77	* @param GCPtrNew The new virtual address.
78	* @param enmMode Used to indicate the callback mode.
79	* @param pvUser User argument.
80	* @remark The return value is no a failure indicator, it's an acceptance
81	* indicator. Relocation can not fail!
82	*/
83	typedef DECLCALLBACK(bool) FNPGMRELOCATE(PVM pVM, RTGCPTR GCPtrOld, RTGCPTR GCPtrNew, PGMRELOCATECALL enmMode, void *pvUser);
84	/** Pointer to a relocation callback function. */
85	typedef FNPGMRELOCATE *PFNPGMRELOCATE;
86
87
88	/**
89	* Memory access origin.
90	*/
91	typedef enum PGMACCESSORIGIN
92	{
93	/** Invalid zero value. */
94	PGMACCESSORIGIN_INVALID = 0,
95	/** IEM is access memory. */
96	PGMACCESSORIGIN_IEM,
97	/** HM is access memory. */
98	PGMACCESSORIGIN_HM,
99	/** Some device is access memory. */
100	PGMACCESSORIGIN_DEVICE,
101	/** Someone debugging is access memory. */
102	PGMACCESSORIGIN_DEBUGGER,
103	/** SELM is access memory. */
104	PGMACCESSORIGIN_SELM,
105	/** FTM is access memory. */
106	PGMACCESSORIGIN_FTM,
107	/** REM is access memory. */
108	PGMACCESSORIGIN_REM,
109	/** IOM is access memory. */
110	PGMACCESSORIGIN_IOM,
111	/** End of valid values. */
112	PGMACCESSORIGIN_END,
113	/** Type size hack. */
114	PGMACCESSORIGIN_32BIT_HACK = 0x7fffffff
115	} PGMACCESSORIGIN;
116
117
118	/**
119	* Physical page access handler kind.
120	*/
121	typedef enum PGMPHYSHANDLERKIND
122	{
123	/** MMIO range. Pages are not present, all access is done in interpreter or recompiler. */
124	PGMPHYSHANDLERKIND_MMIO = 1,
125	/** Handler all write access to a physical page range. */
126	PGMPHYSHANDLERKIND_WRITE,
127	/** Handler all access to a physical page range. */
128	PGMPHYSHANDLERKIND_ALL
129
130	} PGMPHYSHANDLERKIND;
131
132	/**
133	* Guest Access type
134	*/
135	typedef enum PGMACCESSTYPE
136	{
137	/** Read access. */
138	PGMACCESSTYPE_READ = 1,
139	/** Write access. */
140	PGMACCESSTYPE_WRITE
141	} PGMACCESSTYPE;
142
143
144	/** @def PGM_ALL_CB_DECL
145	* Macro for declaring a handler callback for all contexts. The handler
146	* callback is static in ring-3, and exported in RC and R0.
147	* @sa PGM_ALL_CB2_DECL.
148	*/
149	#if defined(IN_RC) \|\| defined(IN_RING0)
150	# ifdef __cplusplus
151	# define PGM_ALL_CB_DECL(type) extern "C" DECLCALLBACK(DECLEXPORT(type))
152	# else
153	# define PGM_ALL_CB_DECL(type) DECLCALLBACK(DECLEXPORT(type))
154	# endif
155	#else
156	# define PGM_ALL_CB_DECL(type) static DECLCALLBACK(type)
157	#endif
158
159	/** @def PGM_ALL_CB2_DECL
160	* Macro for declaring a handler callback for all contexts. The handler
161	* callback is hidden in ring-3, and exported in RC and R0.
162	* @sa PGM_ALL_CB2_DECL.
163	*/
164	#if defined(IN_RC) \|\| defined(IN_RING0)
165	# ifdef __cplusplus
166	# define PGM_ALL_CB2_DECL(type) extern "C" DECLCALLBACK(DECLEXPORT(type))
167	# else
168	# define PGM_ALL_CB2_DECL(type) DECLCALLBACK(DECLEXPORT(type))
169	# endif
170	#else
171	# define PGM_ALL_CB2_DECL(type) DECLCALLBACK(DECLHIDDEN(type))
172	#endif
173
174	/** @def PGM_ALL_CB2_PROTO
175	* Macro for declaring a handler callback for all contexts. The handler
176	* callback is hidden in ring-3, and exported in RC and R0.
177	* @param fnType The callback function type.
178	* @sa PGM_ALL_CB2_DECL.
179	*/
180	#if defined(IN_RC) \|\| defined(IN_RING0)
181	# ifdef __cplusplus
182	# define PGM_ALL_CB2_PROTO(fnType) extern "C" DECLEXPORT(fnType)
183	# else
184	# define PGM_ALL_CB2_PROTO(fnType) DECLEXPORT(fnType)
185	# endif
186	#else
187	# define PGM_ALL_CB2_PROTO(fnType) DECLHIDDEN(fnType)
188	#endif
189
190
191	/**
192	* \#PF Handler callback for physical access handler ranges in RC and R0.
193	*
194	* @returns Strict VBox status code (appropriate for ring-0 and raw-mode).
195	* @param pVM The cross context VM structure.
196	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
197	* @param uErrorCode CPU Error code.
198	* @param pRegFrame Trap register frame.
199	* NULL on DMA and other non CPU access.
200	* @param pvFault The fault address (cr2).
201	* @param GCPhysFault The GC physical address corresponding to pvFault.
202	* @param pvUser User argument.
203	* @thread EMT(pVCpu)
204	*/
205	typedef DECLCALLBACK(VBOXSTRICTRC) FNPGMRZPHYSPFHANDLER(PVM pVM, PVMCPU pVCpu, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame,
206	RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser);
207	/** Pointer to PGM access callback. */
208	typedef FNPGMRZPHYSPFHANDLER *PFNPGMRZPHYSPFHANDLER;
209
210
211	/**
212	* Access handler callback for physical access handler ranges.
213	*
214	* The handler can not raise any faults, it's mainly for monitoring write access
215	* to certain pages (like MMIO).
216	*
217	* @returns Strict VBox status code in ring-0 and raw-mode context, in ring-3
218	* the only supported informational status code is
219	* VINF_PGM_HANDLER_DO_DEFAULT.
220	* @retval VINF_SUCCESS if the handler have carried out the operation.
221	* @retval VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the
222	* access operation.
223	* @retval VINF_EM_XXX in ring-0 and raw-mode context.
224	*
225	* @param pVM The cross context VM structure.
226	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
227	* @param GCPhys The physical address the guest is writing to.
228	* @param pvPhys The HC mapping of that address.
229	* @param pvBuf What the guest is reading/writing.
230	* @param cbBuf How much it's reading/writing.
231	* @param enmAccessType The access type.
232	* @param enmOrigin The origin of this call.
233	* @param pvUser User argument.
234	* @thread EMT(pVCpu)
235	*/
236	typedef DECLCALLBACK(VBOXSTRICTRC) FNPGMPHYSHANDLER(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void pvPhys, void pvBuf, size_t cbBuf,
237	PGMACCESSTYPE enmAccessType, PGMACCESSORIGIN enmOrigin, void *pvUser);
238	/** Pointer to PGM access callback. */
239	typedef FNPGMPHYSHANDLER *PFNPGMPHYSHANDLER;
240
241
242	/**
243	* Virtual access handler type.
244	*/
245	typedef enum PGMVIRTHANDLERKIND
246	{
247	/** Write access handled. */
248	PGMVIRTHANDLERKIND_WRITE = 1,
249	/** All access handled. */
250	PGMVIRTHANDLERKIND_ALL,
251	/** Hypervisor write access handled.
252	* This is used to catch the guest trying to write to LDT, TSS and any other
253	* system structure which the brain dead intel guys let unprivilegde code find. */
254	PGMVIRTHANDLERKIND_HYPERVISOR
255	} PGMVIRTHANDLERKIND;
256
257	/**
258	* \#PF handler callback for virtual access handler ranges, RC.
259	*
260	* Important to realize that a physical page in a range can have aliases, and
261	* for ALL and WRITE handlers these will also trigger.
262	*
263	* @returns Strict VBox status code (appropriate for raw-mode).
264	* @param pVM The cross context VM structure.
265	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
266	* @param uErrorCode CPU Error code (X86_TRAP_PF_XXX).
267	* @param pRegFrame Trap register frame.
268	* @param pvFault The fault address (cr2).
269	* @param pvRange The base address of the handled virtual range.
270	* @param offRange The offset of the access into this range.
271	* (If it's a EIP range this is the EIP, if not it's pvFault.)
272	* @param pvUser User argument.
273	* @thread EMT(pVCpu)
274	*/
275	typedef DECLCALLBACK(VBOXSTRICTRC) FNPGMRCVIRTPFHANDLER(PVM pVM, PVMCPU pVCpu, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame,
276	RTGCPTR pvFault, RTGCPTR pvRange, uintptr_t offRange, void *pvUser);
277	/** Pointer to PGM access callback. */
278	typedef FNPGMRCVIRTPFHANDLER *PFNPGMRCVIRTPFHANDLER;
279
280	/**
281	* Access handler callback for virtual access handler ranges.
282	*
283	* Important to realize that a physical page in a range can have aliases, and
284	* for ALL and WRITE handlers these will also trigger.
285	*
286	* @returns VINF_SUCCESS if the handler have carried out the operation.
287	* @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
288	* @param pVM The cross context VM structure.
289	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
290	* @param GCPtr The virtual address the guest is writing to. This
291	* is the registered address corresponding to the
292	* access, so no aliasing trouble here.
293	* @param pvPtr The HC mapping of that address.
294	* @param pvBuf What the guest is reading/writing.
295	* @param cbBuf How much it's reading/writing.
296	* @param enmAccessType The access type.
297	* @param enmOrigin Who is calling.
298	* @param pvUser User argument.
299	* @thread EMT(pVCpu)
300	*/
301	typedef DECLCALLBACK(VBOXSTRICTRC) FNPGMVIRTHANDLER(PVM pVM, PVMCPU pVCpu, RTGCPTR GCPtr, void pvPtr, void pvBuf, size_t cbBuf,
302	PGMACCESSTYPE enmAccessType, PGMACCESSORIGIN enmOrigin, void *pvUser);
303	/** Pointer to PGM access callback. */
304	typedef FNPGMVIRTHANDLER *PFNPGMVIRTHANDLER;
305
306	/**
307	* \#PF Handler callback for invalidation of virtual access handler ranges.
308	*
309	* @param pVM The cross context VM structure.
310	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
311	* @param GCPtr The virtual address the guest has changed.
312	* @param pvUser User argument.
313	* @thread EMT(pVCpu)
314	*
315	* @todo FNPGMR3VIRTINVALIDATE will not actually be called! It was introduced
316	* in r13179 (1.1) and stopped working with r13806 (PGMPool merge,
317	* v1.2), exactly a month later.
318	*/
319	typedef DECLCALLBACK(int) FNPGMR3VIRTINVALIDATE(PVM pVM, PVMCPU pVCpu, RTGCPTR GCPtr, void *pvUser);
320	/** Pointer to PGM invalidation callback. */
321	typedef FNPGMR3VIRTINVALIDATE *PFNPGMR3VIRTINVALIDATE;
322
323
324	/**
325	* Paging mode.
326	*
327	* @note Part of saved state. Change with extreme care.
328	*/
329	typedef enum PGMMODE
330	{
331	/** The usual invalid value. */
332	PGMMODE_INVALID = 0,
333	/** Real mode. */
334	PGMMODE_REAL,
335	/** Protected mode, no paging. */
336	PGMMODE_PROTECTED,
337	/** 32-bit paging. */
338	PGMMODE_32_BIT,
339	/** PAE paging. */
340	PGMMODE_PAE,
341	/** PAE paging with NX enabled. */
342	PGMMODE_PAE_NX,
343	/** 64-bit AMD paging (long mode). */
344	PGMMODE_AMD64,
345	/** 64-bit AMD paging (long mode) with NX enabled. */
346	PGMMODE_AMD64_NX,
347	/** 32-bit nested paging mode (shadow only; guest physical to host physical). */
348	PGMMODE_NESTED_32BIT,
349	/** PAE nested paging mode (shadow only; guest physical to host physical). */
350	PGMMODE_NESTED_PAE,
351	/** AMD64 nested paging mode (shadow only; guest physical to host physical). */
352	PGMMODE_NESTED_AMD64,
353	/** Extended paging (Intel) mode. */
354	PGMMODE_EPT,
355	/** Special mode used by NEM to indicate no shadow paging necessary. */
356	PGMMODE_NONE,
357	/** The max number of modes */
358	PGMMODE_MAX,
359	/** 32bit hackishness. */
360	PGMMODE_32BIT_HACK = 0x7fffffff
361	} PGMMODE;
362
363	/** Macro for checking if the guest is using paging.
364	* @param enmMode PGMMODE_*.
365	* @remark ASSUMES certain order of the PGMMODE_* values.
366	*/
367	#define PGMMODE_WITH_PAGING(enmMode) ((enmMode) >= PGMMODE_32_BIT)
368
369	/** Macro for checking if it's one of the long mode modes.
370	* @param enmMode PGMMODE_*.
371	*/
372	#define PGMMODE_IS_LONG_MODE(enmMode) ((enmMode) == PGMMODE_AMD64_NX \|\| (enmMode) == PGMMODE_AMD64)
373
374	/** Macro for checking if it's one of the AMD64 nested modes.
375	* @param enmMode PGMMODE_*.
376	*/
377	#define PGMMODE_IS_NESTED(enmMode) ( (enmMode) == PGMMODE_NESTED_32BIT \
378	\|\| (enmMode) == PGMMODE_NESTED_PAE \
379	\|\| (enmMode) == PGMMODE_NESTED_AMD64)
380
381	/**
382	* Is the ROM mapped (true) or is the shadow RAM mapped (false).
383	*
384	* @returns boolean.
385	* @param enmProt The PGMROMPROT value, must be valid.
386	*/
387	#define PGMROMPROT_IS_ROM(enmProt) \
388	( (enmProt) == PGMROMPROT_READ_ROM_WRITE_IGNORE \
389	\|\| (enmProt) == PGMROMPROT_READ_ROM_WRITE_RAM )
390
391
392	VMMDECL(bool) PGMIsLockOwner(PVM pVM);
393
394	VMMDECL(int) PGMRegisterStringFormatTypes(void);
395	VMMDECL(void) PGMDeregisterStringFormatTypes(void);
396	VMMDECL(RTHCPHYS) PGMGetHyperCR3(PVMCPU pVCpu);
397	VMMDECL(int) PGMTrap0eHandler(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault);
398	VMMDECL(int) PGMPrefetchPage(PVMCPU pVCpu, RTGCPTR GCPtrPage);
399	VMMDECL(int) PGMVerifyAccess(PVMCPU pVCpu, RTGCPTR Addr, uint32_t cbSize, uint32_t fAccess);
400	VMMDECL(int) PGMIsValidAccess(PVMCPU pVCpu, RTGCPTR Addr, uint32_t cbSize, uint32_t fAccess);
401	VMMDECL(VBOXSTRICTRC) PGMInterpretInstruction(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault);
402	#ifndef PGM_WITHOUT_MAPPINGS
403	VMMDECL(int) PGMMap(PVM pVM, RTGCPTR GCPtr, RTHCPHYS HCPhys, uint32_t cbPages, unsigned fFlags);
404	VMMDECL(int) PGMMapGetPage(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys);
405	VMMDECL(int) PGMMapSetPage(PVM pVM, RTGCPTR GCPtr, uint64_t cb, uint64_t fFlags);
406	VMMDECL(int) PGMMapModifyPage(PVM pVM, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask);
407	# ifndef IN_RING0
408	VMMDECL(bool) PGMMapHasConflicts(PVM pVM);
409	# endif
410	# ifdef VBOX_STRICT
411	VMMDECL(void) PGMMapCheck(PVM pVM);
412	# endif
413	#endif /* !PGM_WITHOUT_MAPPINGS */
414	VMMDECL(int) PGMShwGetPage(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys);
415	VMMDECL(int) PGMShwMakePageReadonly(PVMCPU pVCpu, RTGCPTR GCPtr, uint32_t fFlags);
416	VMMDECL(int) PGMShwMakePageWritable(PVMCPU pVCpu, RTGCPTR GCPtr, uint32_t fFlags);
417	VMMDECL(int) PGMShwMakePageNotPresent(PVMCPU pVCpu, RTGCPTR GCPtr, uint32_t fFlags);
418	/** @name Flags for PGMShwMakePageReadonly, PGMShwMakePageWritable and
419	* PGMShwMakePageNotPresent
420	* @{ */
421	/** The call is from an access handler for dealing with the a faulting write
422	* operation. The virtual address is within the same page. */
423	#define PGM_MK_PG_IS_WRITE_FAULT RT_BIT(0)
424	/** The page is an MMIO2. */
425	#define PGM_MK_PG_IS_MMIO2 RT_BIT(1)
426	/** @}*/
427	VMMDECL(int) PGMGstGetPage(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys);
428	VMMDECL(bool) PGMGstIsPagePresent(PVMCPU pVCpu, RTGCPTR GCPtr);
429	VMMDECL(int) PGMGstSetPage(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cb, uint64_t fFlags);
430	VMMDECL(int) PGMGstModifyPage(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask);
431	VMM_INT_DECL(int) PGMGstGetPaePdpes(PVMCPU pVCpu, PX86PDPE paPdpes);
432	VMM_INT_DECL(void) PGMGstUpdatePaePdpes(PVMCPU pVCpu, PCX86PDPE paPdpes);
433
434	VMMDECL(int) PGMInvalidatePage(PVMCPU pVCpu, RTGCPTR GCPtrPage);
435	VMMDECL(int) PGMFlushTLB(PVMCPU pVCpu, uint64_t cr3, bool fGlobal);
436	VMMDECL(int) PGMSyncCR3(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal);
437	VMMDECL(int) PGMUpdateCR3(PVMCPU pVCpu, uint64_t cr3);
438	VMMDECL(int) PGMChangeMode(PVMCPU pVCpu, uint64_t cr0, uint64_t cr4, uint64_t efer);
439	VMM_INT_DECL(int) PGMHCChangeMode(PVM pVM, PVMCPU pVCpu, PGMMODE enmGuestMode);
440	VMMDECL(void) PGMCr0WpEnabled(PVMCPU pVCpu);
441	VMMDECL(PGMMODE) PGMGetGuestMode(PVMCPU pVCpu);
442	VMMDECL(PGMMODE) PGMGetShadowMode(PVMCPU pVCpu);
443	VMMDECL(PGMMODE) PGMGetHostMode(PVM pVM);
444	VMMDECL(const char *) PGMGetModeName(PGMMODE enmMode);
445	VMM_INT_DECL(RTGCPHYS) PGMGetGuestCR3Phys(PVMCPU pVCpu);
446	VMM_INT_DECL(void) PGMNotifyNxeChanged(PVMCPU pVCpu, bool fNxe);
447	VMMDECL(bool) PGMHasDirtyPages(PVM pVM);
448
449	/** PGM physical access handler type registration handle (heap offset, valid
450	* cross contexts without needing fixing up). Callbacks and handler type is
451	* associated with this and it is shared by all handler registrations. */
452	typedef uint32_t PGMPHYSHANDLERTYPE;
453	/** Pointer to a PGM physical handler type registration handle. */
454	typedef PGMPHYSHANDLERTYPE *PPGMPHYSHANDLERTYPE;
455	/** NIL value for PGM physical access handler type handle. */
456	#define NIL_PGMPHYSHANDLERTYPE UINT32_MAX
457	VMMDECL(uint32_t) PGMHandlerPhysicalTypeRelease(PVM pVM, PGMPHYSHANDLERTYPE hType);
458	VMMDECL(uint32_t) PGMHandlerPhysicalTypeRetain(PVM pVM, PGMPHYSHANDLERTYPE hType);
459
460	VMMDECL(int) PGMHandlerPhysicalRegister(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS GCPhysLast, PGMPHYSHANDLERTYPE hType,
461	RTR3PTR pvUserR3, RTR0PTR pvUserR0, RTRCPTR pvUserRC,
462	R3PTRTYPE(const char *) pszDesc);
463	VMMDECL(int) PGMHandlerPhysicalModify(PVM pVM, RTGCPHYS GCPhysCurrent, RTGCPHYS GCPhys, RTGCPHYS GCPhysLast);
464	VMMDECL(int) PGMHandlerPhysicalDeregister(PVM pVM, RTGCPHYS GCPhys);
465	VMMDECL(int) PGMHandlerPhysicalChangeUserArgs(PVM pVM, RTGCPHYS GCPhys, RTR3PTR pvUserR3, RTR0PTR pvUserR0, RTRCPTR pvUserRC);
466	VMMDECL(int) PGMHandlerPhysicalSplit(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS GCPhysSplit);
467	VMMDECL(int) PGMHandlerPhysicalJoin(PVM pVM, RTGCPHYS GCPhys1, RTGCPHYS GCPhys2);
468	VMMDECL(int) PGMHandlerPhysicalPageTempOff(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS GCPhysPage);
469	VMMDECL(int) PGMHandlerPhysicalPageAlias(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS GCPhysPage, RTGCPHYS GCPhysPageRemap);
470	VMMDECL(int) PGMHandlerPhysicalPageAliasHC(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS GCPhysPage, RTHCPHYS HCPhysPageRemap);
471	VMMDECL(int) PGMHandlerPhysicalReset(PVM pVM, RTGCPHYS GCPhys);
472	VMMDECL(bool) PGMHandlerPhysicalIsRegistered(PVM pVM, RTGCPHYS GCPhys);
473
474	/** PGM virtual access handler type registration handle (heap offset, valid
475	* cross contexts without needing fixing up). Callbacks and handler type is
476	* associated with this and it is shared by all handler registrations. */
477	typedef uint32_t PGMVIRTHANDLERTYPE;
478	/** Pointer to a PGM virtual handler type registration handle. */
479	typedef PGMVIRTHANDLERTYPE *PPGMVIRTHANDLERTYPE;
480	/** NIL value for PGM virtual access handler type handle. */
481	#define NIL_PGMVIRTHANDLERTYPE UINT32_MAX
482	#ifdef VBOX_WITH_RAW_MODE
483	VMM_INT_DECL(uint32_t) PGMHandlerVirtualTypeRelease(PVM pVM, PGMVIRTHANDLERTYPE hType);
484	VMM_INT_DECL(uint32_t) PGMHandlerVirtualTypeRetain(PVM pVM, PGMVIRTHANDLERTYPE hType);
485	VMM_INT_DECL(bool) PGMHandlerVirtualIsRegistered(PVM pVM, RTGCPTR GCPtr);
486	#endif
487
488
489	/**
490	* Page type.
491	*
492	* @remarks This enum has to fit in a 3-bit field (see PGMPAGE::u3Type).
493	* @remarks This is used in the saved state, so changes to it requires bumping
494	* the saved state version.
495	* @todo So, convert to \#defines!
496	*/
497	typedef enum PGMPAGETYPE
498	{
499	/** The usual invalid zero entry. */
500	PGMPAGETYPE_INVALID = 0,
501	/** RAM page. (RWX) */
502	PGMPAGETYPE_RAM,
503	/** MMIO2 page. (RWX) */
504	PGMPAGETYPE_MMIO2,
505	/** MMIO2 page aliased over an MMIO page. (RWX)
506	* See PGMHandlerPhysicalPageAlias(). */
507	PGMPAGETYPE_MMIO2_ALIAS_MMIO,
508	/** Special page aliased over an MMIO page. (RWX)
509	* See PGMHandlerPhysicalPageAliasHC(), but this is generally only used for
510	* VT-x's APIC access page at the moment. Treated as MMIO by everyone except
511	* the shadow paging code. */
512	PGMPAGETYPE_SPECIAL_ALIAS_MMIO,
513	/** Shadowed ROM. (RWX) */
514	PGMPAGETYPE_ROM_SHADOW,
515	/** ROM page. (R-X) */
516	PGMPAGETYPE_ROM,
517	/** MMIO page. (---) */
518	PGMPAGETYPE_MMIO,
519	/** End of valid entries. */
520	PGMPAGETYPE_END
521	} PGMPAGETYPE;
522	AssertCompile(PGMPAGETYPE_END == 8);
523
524	/** @name PGM page type predicates.
525	* @{ */
526	#define PGMPAGETYPE_IS_READABLE(a_enmType) ( (a_enmType) <= PGMPAGETYPE_ROM )
527	#define PGMPAGETYPE_IS_WRITEABLE(a_enmType) ( (a_enmType) <= PGMPAGETYPE_ROM_SHADOW )
528	#define PGMPAGETYPE_IS_RWX(a_enmType) ( (a_enmType) <= PGMPAGETYPE_ROM_SHADOW )
529	#define PGMPAGETYPE_IS_ROX(a_enmType) ( (a_enmType) == PGMPAGETYPE_ROM )
530	#define PGMPAGETYPE_IS_NP(a_enmType) ( (a_enmType) == PGMPAGETYPE_MMIO )
531	/** @} */
532
533
534	VMM_INT_DECL(PGMPAGETYPE) PGMPhysGetPageType(PVM pVM, RTGCPHYS GCPhys);
535
536	VMM_INT_DECL(int) PGMPhysGCPhys2HCPhys(PVM pVM, RTGCPHYS GCPhys, PRTHCPHYS pHCPhys);
537	VMM_INT_DECL(int) PGMPhysGCPtr2HCPhys(PVMCPU pVCpu, RTGCPTR GCPtr, PRTHCPHYS pHCPhys);
538	VMM_INT_DECL(int) PGMPhysGCPhys2CCPtr(PVM pVM, RTGCPHYS GCPhys, void **ppv, PPGMPAGEMAPLOCK pLock);
539	VMM_INT_DECL(int) PGMPhysGCPhys2CCPtrReadOnly(PVM pVM, RTGCPHYS GCPhys, void const **ppv, PPGMPAGEMAPLOCK pLock);
540	VMM_INT_DECL(int) PGMPhysGCPtr2CCPtr(PVMCPU pVCpu, RTGCPTR GCPtr, void **ppv, PPGMPAGEMAPLOCK pLock);
541	VMM_INT_DECL(int) PGMPhysGCPtr2CCPtrReadOnly(PVMCPU pVCpu, RTGCPTR GCPtr, void const **ppv, PPGMPAGEMAPLOCK pLock);
542
543	VMMDECL(bool) PGMPhysIsA20Enabled(PVMCPU pVCpu);
544	VMMDECL(bool) PGMPhysIsGCPhysValid(PVM pVM, RTGCPHYS GCPhys);
545	VMMDECL(bool) PGMPhysIsGCPhysNormal(PVM pVM, RTGCPHYS GCPhys);
546	VMMDECL(int) PGMPhysGCPtr2GCPhys(PVMCPU pVCpu, RTGCPTR GCPtr, PRTGCPHYS pGCPhys);
547	VMMDECL(void) PGMPhysReleasePageMappingLock(PVM pVM, PPGMPAGEMAPLOCK pLock);
548	VMMDECL(void) PGMPhysBulkReleasePageMappingLocks(PVM pVM, uint32_t cPages, PPGMPAGEMAPLOCK paLock);
549
550	/** @def PGM_PHYS_RW_IS_SUCCESS
551	* Check whether a PGMPhysRead, PGMPhysWrite, PGMPhysReadGCPtr or
552	* PGMPhysWriteGCPtr call completed the given task.
553	*
554	* @returns true if completed, false if not.
555	* @param a_rcStrict The status code.
556	* @sa IOM_SUCCESS
557	*/
558	#ifdef IN_RING3
559	# define PGM_PHYS_RW_IS_SUCCESS(a_rcStrict) \
560	( (a_rcStrict) == VINF_SUCCESS \
561	\|\| (a_rcStrict) == VINF_EM_DBG_STOP \
562	\|\| (a_rcStrict) == VINF_EM_DBG_EVENT \
563	\|\| (a_rcStrict) == VINF_EM_DBG_BREAKPOINT \
564	)
565	#elif defined(IN_RING0)
566	# define PGM_PHYS_RW_IS_SUCCESS(a_rcStrict) \
567	( (a_rcStrict) == VINF_SUCCESS \
568	\|\| (a_rcStrict) == VINF_IOM_R3_MMIO_COMMIT_WRITE \
569	\|\| (a_rcStrict) == VINF_EM_OFF \
570	\|\| (a_rcStrict) == VINF_EM_SUSPEND \
571	\|\| (a_rcStrict) == VINF_EM_RESET \
572	\|\| (a_rcStrict) == VINF_EM_HALT \
573	\|\| (a_rcStrict) == VINF_EM_DBG_STOP \
574	\|\| (a_rcStrict) == VINF_EM_DBG_EVENT \
575	\|\| (a_rcStrict) == VINF_EM_DBG_BREAKPOINT \
576	)
577	#elif defined(IN_RC)
578	# define PGM_PHYS_RW_IS_SUCCESS(a_rcStrict) \
579	( (a_rcStrict) == VINF_SUCCESS \
580	\|\| (a_rcStrict) == VINF_IOM_R3_MMIO_COMMIT_WRITE \
581	\|\| (a_rcStrict) == VINF_EM_OFF \
582	\|\| (a_rcStrict) == VINF_EM_SUSPEND \
583	\|\| (a_rcStrict) == VINF_EM_RESET \
584	\|\| (a_rcStrict) == VINF_EM_HALT \
585	\|\| (a_rcStrict) == VINF_SELM_SYNC_GDT \
586	\|\| (a_rcStrict) == VINF_EM_RAW_EMULATE_INSTR_GDT_FAULT \
587	\|\| (a_rcStrict) == VINF_EM_DBG_STOP \
588	\|\| (a_rcStrict) == VINF_EM_DBG_EVENT \
589	\|\| (a_rcStrict) == VINF_EM_DBG_BREAKPOINT \
590	)
591	#endif
592	/** @def PGM_PHYS_RW_DO_UPDATE_STRICT_RC
593	* Updates the return code with a new result.
594	*
595	* Both status codes must be successes according to PGM_PHYS_RW_IS_SUCCESS.
596	*
597	* @param a_rcStrict The current return code, to be updated.
598	* @param a_rcStrict2 The new return code to merge in.
599	*/
600	#ifdef IN_RING3
601	# define PGM_PHYS_RW_DO_UPDATE_STRICT_RC(a_rcStrict, a_rcStrict2) \
602	do { \
603	Assert(rcStrict == VINF_SUCCESS); \
604	Assert(rcStrict2 == VINF_SUCCESS); \
605	} while (0)
606	#elif defined(IN_RING0)
607	# define PGM_PHYS_RW_DO_UPDATE_STRICT_RC(a_rcStrict, a_rcStrict2) \
608	do { \
609	Assert(PGM_PHYS_RW_IS_SUCCESS(rcStrict)); \
610	Assert(PGM_PHYS_RW_IS_SUCCESS(rcStrict2)); \
611	AssertCompile(VINF_IOM_R3_MMIO_COMMIT_WRITE > VINF_EM_LAST); \
612	if ((a_rcStrict2) == VINF_SUCCESS \|\| (a_rcStrict) == (a_rcStrict2)) \
613	{ /* likely */ } \
614	else if ( (a_rcStrict) == VINF_SUCCESS \
615	\|\| (a_rcStrict) > (a_rcStrict2)) \
616	(a_rcStrict) = (a_rcStrict2); \
617	} while (0)
618	#elif defined(IN_RC)
619	# define PGM_PHYS_RW_DO_UPDATE_STRICT_RC(a_rcStrict, a_rcStrict2) \
620	do { \
621	Assert(PGM_PHYS_RW_IS_SUCCESS(rcStrict)); \
622	Assert(PGM_PHYS_RW_IS_SUCCESS(rcStrict2)); \
623	AssertCompile(VINF_SELM_SYNC_GDT > VINF_EM_LAST); \
624	AssertCompile(VINF_EM_RAW_EMULATE_INSTR_GDT_FAULT > VINF_EM_LAST); \
625	AssertCompile(VINF_EM_RAW_EMULATE_INSTR_GDT_FAULT < VINF_SELM_SYNC_GDT); \
626	AssertCompile(VINF_IOM_R3_MMIO_COMMIT_WRITE > VINF_EM_LAST); \
627	AssertCompile(VINF_IOM_R3_MMIO_COMMIT_WRITE > VINF_SELM_SYNC_GDT); \
628	AssertCompile(VINF_IOM_R3_MMIO_COMMIT_WRITE > VINF_EM_RAW_EMULATE_INSTR_GDT_FAULT); \
629	if ((a_rcStrict2) == VINF_SUCCESS \|\| (a_rcStrict) == (a_rcStrict2)) \
630	{ /* likely */ } \
631	else if ((a_rcStrict) == VINF_SUCCESS) \
632	(a_rcStrict) = (a_rcStrict2); \
633	else if ( ( (a_rcStrict) > (a_rcStrict2) \
634	&& ( (a_rcStrict2) <= VINF_EM_RESET \
635	\|\| (a_rcStrict) != VINF_EM_RAW_EMULATE_INSTR_GDT_FAULT) ) \
636	\|\| ( (a_rcStrict2) == VINF_EM_RAW_EMULATE_INSTR_GDT_FAULT \
637	&& (a_rcStrict) > VINF_EM_RESET) ) \
638	(a_rcStrict) = (a_rcStrict2); \
639	} while (0)
640	#endif
641
642	VMMDECL(VBOXSTRICTRC) PGMPhysRead(PVM pVM, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead, PGMACCESSORIGIN enmOrigin);
643	VMMDECL(VBOXSTRICTRC) PGMPhysWrite(PVM pVM, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite, PGMACCESSORIGIN enmOrigin);
644	VMMDECL(VBOXSTRICTRC) PGMPhysReadGCPtr(PVMCPU pVCpu, void *pvDst, RTGCPTR GCPtrSrc, size_t cb, PGMACCESSORIGIN enmOrigin);
645	VMMDECL(VBOXSTRICTRC) PGMPhysWriteGCPtr(PVMCPU pVCpu, RTGCPTR GCPtrDst, const void *pvSrc, size_t cb, PGMACCESSORIGIN enmOrigin);
646
647	VMMDECL(int) PGMPhysSimpleReadGCPhys(PVM pVM, void *pvDst, RTGCPHYS GCPhysSrc, size_t cb);
648	VMMDECL(int) PGMPhysSimpleWriteGCPhys(PVM pVM, RTGCPHYS GCPhysDst, const void *pvSrc, size_t cb);
649	VMMDECL(int) PGMPhysSimpleReadGCPtr(PVMCPU pVCpu, void *pvDst, RTGCPTR GCPtrSrc, size_t cb);
650	VMMDECL(int) PGMPhysSimpleWriteGCPtr(PVMCPU pVCpu, RTGCPTR GCPtrDst, const void *pvSrc, size_t cb);
651	VMMDECL(int) PGMPhysSimpleDirtyWriteGCPtr(PVMCPU pVCpu, RTGCPTR GCPtrDst, const void *pvSrc, size_t cb);
652	VMMDECL(int) PGMPhysInterpretedRead(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, void *pvDst, RTGCPTR GCPtrSrc, size_t cb);
653	VMMDECL(int) PGMPhysInterpretedReadNoHandlers(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, void *pvDst, RTGCUINTPTR GCPtrSrc, size_t cb, bool fRaiseTrap);
654	VMMDECL(int) PGMPhysInterpretedWriteNoHandlers(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, RTGCPTR GCPtrDst, void const *pvSrc, size_t cb, bool fRaiseTrap);
655
656	VMM_INT_DECL(int) PGMPhysIemGCPhys2Ptr(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, bool fWritable, bool fByPassHandlers, void **ppv, PPGMPAGEMAPLOCK pLock);
657	VMM_INT_DECL(int) PGMPhysIemQueryAccess(PVM pVM, RTGCPHYS GCPhys, bool fWritable, bool fByPassHandlers);
658	VMM_INT_DECL(int) PGMPhysIemGCPhys2PtrNoLock(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, uint64_t const volatile *puTlbPhysRev,
659	#if defined(IN_RC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
660	R3PTRTYPE(uint8_t ) ppb,
661	#else
662	R3R0PTRTYPE(uint8_t ) ppb,
663	#endif
664	uint64_t *pfTlb);
665	/** @name Flags returned by PGMPhysIemGCPhys2PtrNoLock
666	* @{ */
667	#define PGMIEMGCPHYS2PTR_F_NO_WRITE RT_BIT_32(3) /*< Not writable (IEMTLBE_F_PG_NO_WRITE). /
668	#define PGMIEMGCPHYS2PTR_F_NO_READ RT_BIT_32(4) /*< Not readable (IEMTLBE_F_PG_NO_READ). /
669	#define PGMIEMGCPHYS2PTR_F_NO_MAPPINGR3 RT_BIT_32(7) /*< No ring-3 mapping (IEMTLBE_F_NO_MAPPINGR3). /
670	/** @} */
671
672	/** Information returned by PGMPhysNemQueryPageInfo. */
673	typedef struct PGMPHYSNEMPAGEINFO
674	{
675	/** The host physical address of the page, NIL_HCPHYS if invalid page. */
676	RTHCPHYS HCPhys;
677	/** The NEM access mode for the page, NEM_PAGE_PROT_XXX */
678	uint32_t fNemProt : 8;
679	/** The NEM state associated with the PAGE. */
680	uint32_t u2NemState : 2;
681	/** The NEM state associated with the PAGE before pgmPhysPageMakeWritable was called. */
682	uint32_t u2OldNemState : 2;
683	/** Set if the page has handler. */
684	uint32_t fHasHandlers : 1;
685	/** Set if is the zero page backing it. */
686	uint32_t fZeroPage : 1;
687	/** Set if the page has handler. */
688	PGMPAGETYPE enmType;
689	} PGMPHYSNEMPAGEINFO;
690	/** Pointer to page information for NEM. */
691	typedef PGMPHYSNEMPAGEINFO *PPGMPHYSNEMPAGEINFO;
692	/**
693	* Callback for checking that the page is in sync while under the PGM lock.
694	*
695	* NEM passes this callback to PGMPhysNemQueryPageInfo to check that the page is
696	* in-sync between PGM and the native hypervisor API in an atomic fashion.
697	*
698	* @returns VBox status code.
699	* @param pVM The cross context VM structure.
700	* @param pVCpu The cross context per virtual CPU structure. Optional,
701	* see PGMPhysNemQueryPageInfo.
702	* @param GCPhys The guest physical address (not A20 masked).
703	* @param pInfo The page info structure. This function updates the
704	* u2NemState memory and the caller will update the PGMPAGE
705	* copy accordingly.
706	* @param pvUser Callback user argument.
707	*/
708	typedef DECLCALLBACK(int) FNPGMPHYSNEMCHECKPAGE(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, PPGMPHYSNEMPAGEINFO pInfo, void *pvUser);
709	/** Pointer to a FNPGMPHYSNEMCHECKPAGE function. */
710	typedef FNPGMPHYSNEMCHECKPAGE *PFNPGMPHYSNEMCHECKPAGE;
711
712	VMM_INT_DECL(int) PGMPhysNemPageInfoChecker(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, bool fMakeWritable,
713	PPGMPHYSNEMPAGEINFO pInfo, PFNPGMPHYSNEMCHECKPAGE pfnChecker, void *pvUser);
714
715	/**
716	* Callback for use with PGMPhysNemEnumPagesByState.
717	* @returns VBox status code.
718	* Failure status will stop enumeration immediately and return.
719	* @param pVM The cross context VM structure.
720	* @param pVCpu The cross context per virtual CPU structure. Optional,
721	* see PGMPhysNemEnumPagesByState.
722	* @param GCPhys The guest physical address (not A20 masked).
723	* @param pu2NemState Pointer to variable with the NEM state. This can be
724	* update.
725	* @param pvUser The user argument.
726	*/
727	typedef DECLCALLBACK(int) FNPGMPHYSNEMENUMCALLBACK(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, uint8_t pu2NemState, void pvUser);
728	/** Pointer to a FNPGMPHYSNEMENUMCALLBACK function. */
729	typedef FNPGMPHYSNEMENUMCALLBACK *PFNPGMPHYSNEMENUMCALLBACK;
730	VMM_INT_DECL(int) PGMPhysNemEnumPagesByState(PVM pVM, PVMCPU VCpu, uint8_t uMinState,
731	PFNPGMPHYSNEMENUMCALLBACK pfnCallback, void *pvUser);
732
733
734	#ifdef VBOX_STRICT
735	VMMDECL(unsigned) PGMAssertHandlerAndFlagsInSync(PVM pVM);
736	VMMDECL(unsigned) PGMAssertNoMappingConflicts(PVM pVM);
737	VMMDECL(unsigned) PGMAssertCR3(PVM pVM, PVMCPU pVCpu, uint64_t cr3, uint64_t cr4);
738	#endif /* VBOX_STRICT */
739
740	#if defined(IN_RC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE)
741	VMMDECL(void) PGMRZDynMapStartAutoSet(PVMCPU pVCpu);
742	VMMDECL(void) PGMRZDynMapReleaseAutoSet(PVMCPU pVCpu);
743	VMMDECL(void) PGMRZDynMapFlushAutoSet(PVMCPU pVCpu);
744	VMMDECL(uint32_t) PGMRZDynMapPushAutoSubset(PVMCPU pVCpu);
745	VMMDECL(void) PGMRZDynMapPopAutoSubset(PVMCPU pVCpu, uint32_t iPrevSubset);
746	#endif
747
748	VMMDECL(int) PGMSetLargePageUsage(PVM pVM, bool fUseLargePages);
749
750	/**
751	* Query large page usage state
752	*
753	* @returns 0 - disabled, 1 - enabled
754	* @param pVM The cross context VM structure.
755	*/
756	#define PGMIsUsingLargePages(pVM) ((pVM)->fUseLargePages)
757
758
759	#ifdef IN_RC
760	/** @defgroup grp_pgm_gc The PGM Guest Context API
761	* @{
762	*/
763	VMMRCDECL(int) PGMRCDynMapInit(PVM pVM);
764	/** @} */
765	#endif /* IN_RC */
766
767
768	#ifdef IN_RING0
769	/** @defgroup grp_pgm_r0 The PGM Host Context Ring-0 API
770	* @{
771	*/
772	VMMR0_INT_DECL(int) PGMR0PhysAllocateHandyPages(PGVM pGVM, PVM pVM, VMCPUID idCpu);
773	VMMR0_INT_DECL(int) PGMR0PhysFlushHandyPages(PGVM pGVM, PVM pVM, VMCPUID idCpu);
774	VMMR0_INT_DECL(int) PGMR0PhysAllocateLargeHandyPage(PGVM pGVM, PVM pVM, VMCPUID idCpu);
775	VMMR0_INT_DECL(int) PGMR0PhysSetupIoMmu(PGVM pGVM, PVM pVM);
776	VMMR0DECL(int) PGMR0SharedModuleCheck(PVM pVM, PGVM pGVM, VMCPUID idCpu, PGMMSHAREDMODULE pModule, PCRTGCPTR64 paRegionsGCPtrs);
777	VMMR0DECL(int) PGMR0Trap0eHandlerNestedPaging(PVM pVM, PVMCPU pVCpu, PGMMODE enmShwPagingMode, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPHYS pvFault);
778	VMMR0DECL(VBOXSTRICTRC) PGMR0Trap0eHandlerNPMisconfig(PVM pVM, PVMCPU pVCpu, PGMMODE enmShwPagingMode, PCPUMCTXCORE pRegFrame, RTGCPHYS GCPhysFault, uint32_t uErr);
779	# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
780	VMMR0DECL(int) PGMR0DynMapInit(void);
781	VMMR0DECL(void) PGMR0DynMapTerm(void);
782	VMMR0DECL(int) PGMR0DynMapInitVM(PVM pVM);
783	VMMR0DECL(void) PGMR0DynMapTermVM(PVM pVM);
784	VMMR0DECL(int) PGMR0DynMapAssertIntegrity(void);
785	VMMR0DECL(bool) PGMR0DynMapStartOrMigrateAutoSet(PVMCPU pVCpu);
786	VMMR0DECL(void) PGMR0DynMapMigrateAutoSet(PVMCPU pVCpu);
787	# endif
788	/** @} */
789	#endif /* IN_RING0 */
790
791
792
793	#ifdef IN_RING3
794	/** @defgroup grp_pgm_r3 The PGM Host Context Ring-3 API
795	* @{
796	*/
797	VMMR3DECL(int) PGMR3Init(PVM pVM);
798	VMMR3DECL(int) PGMR3InitDynMap(PVM pVM);
799	VMMR3DECL(int) PGMR3InitFinalize(PVM pVM);
800	VMMR3_INT_DECL(int) PGMR3InitCompleted(PVM pVM, VMINITCOMPLETED enmWhat);
801	VMMR3DECL(void) PGMR3Relocate(PVM pVM, RTGCINTPTR offDelta);
802	VMMR3DECL(void) PGMR3ResetCpu(PVM pVM, PVMCPU pVCpu);
803	VMMR3_INT_DECL(void) PGMR3Reset(PVM pVM);
804	VMMR3_INT_DECL(void) PGMR3ResetNoMorePhysWritesFlag(PVM pVM);
805	VMMR3_INT_DECL(void) PGMR3MemSetup(PVM pVM, bool fReset);
806	VMMR3DECL(int) PGMR3Term(PVM pVM);
807	VMMR3DECL(int) PGMR3LockCall(PVM pVM);
808
809	VMMR3DECL(int) PGMR3PhysRegisterRam(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, const char *pszDesc);
810	VMMR3DECL(int) PGMR3PhysChangeMemBalloon(PVM pVM, bool fInflate, unsigned cPages, RTGCPHYS *paPhysPage);
811	VMMR3DECL(int) PGMR3PhysWriteProtectRAM(PVM pVM);
812	VMMR3DECL(uint32_t) PGMR3PhysGetRamRangeCount(PVM pVM);
813	VMMR3DECL(int) PGMR3PhysGetRange(PVM pVM, uint32_t iRange, PRTGCPHYS pGCPhysStart, PRTGCPHYS pGCPhysLast,
814	const char *ppszDesc, bool pfIsMmio);
815	VMMR3DECL(int) PGMR3QueryMemoryStats(PUVM pUVM, uint64_t pcbTotalMem, uint64_t pcbPrivateMem, uint64_t pcbSharedMem, uint64_t pcbZeroMem);
816	VMMR3DECL(int) PGMR3QueryGlobalMemoryStats(PUVM pUVM, uint64_t pcbAllocMem, uint64_t pcbFreeMem, uint64_t pcbBallonedMem, uint64_t pcbSharedMem);
817
818	VMMR3DECL(int) PGMR3PhysMMIORegister(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, PGMPHYSHANDLERTYPE hType,
819	RTR3PTR pvUserR3, RTR0PTR pvUserR0, RTRCPTR pvUserRC, const char *pszDesc);
820	VMMR3DECL(int) PGMR3PhysMMIODeregister(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb);
821	VMMR3DECL(int) PGMR3PhysMMIO2Register(PVM pVM, PPDMDEVINS pDevIns, uint32_t iSubDev, uint32_t iRegion, RTGCPHYS cb, uint32_t fFlags, void *ppv, const char pszDesc);
822	VMMR3DECL(int) PGMR3PhysMMIOExPreRegister(PVM pVM, PPDMDEVINS pDevIns, uint32_t iSubDev, uint32_t iRegion, RTGCPHYS cbRegion, PGMPHYSHANDLERTYPE hType,
823	RTR3PTR pvUserR3, RTR0PTR pvUserR0, RTRCPTR pvUserRC, const char *pszDesc);
824	VMMR3DECL(int) PGMR3PhysMMIOExDeregister(PVM pVM, PPDMDEVINS pDevIns, uint32_t iSubDev, uint32_t iRegion);
825	VMMR3DECL(int) PGMR3PhysMMIOExMap(PVM pVM, PPDMDEVINS pDevIns, uint32_t iSubDev, uint32_t iRegion, RTGCPHYS GCPhys);
826	VMMR3DECL(int) PGMR3PhysMMIOExUnmap(PVM pVM, PPDMDEVINS pDevIns, uint32_t iSubDev, uint32_t iRegion, RTGCPHYS GCPhys);
827	VMMR3_INT_DECL(int) PGMR3PhysMMIOExReduce(PVM pVM, PPDMDEVINS pDevIns, uint32_t iSubDev, uint32_t iRegion, RTGCPHYS cbRegion);
828	VMMR3DECL(bool) PGMR3PhysMMIOExIsBase(PVM pVM, PPDMDEVINS pDevIns, RTGCPHYS GCPhys);
829	VMMR3_INT_DECL(int) PGMR3PhysMMIO2GetHCPhys(PVM pVM, PPDMDEVINS pDevIns, uint32_t iSubDev, uint32_t iRegion, RTGCPHYS off, PRTHCPHYS pHCPhys);
830	VMMR3_INT_DECL(int) PGMR3PhysMMIO2MapKernel(PVM pVM, PPDMDEVINS pDevIns, uint32_t iSubDev, uint32_t iRegion, RTGCPHYS off, RTGCPHYS cb, const char *pszDesc, PRTR0PTR pR0Ptr);
831	VMMR3_INT_DECL(int) PGMR3PhysMMIOExChangeRegionNo(PVM pVM, PPDMDEVINS pDevIns, uint32_t iSubDev, uint32_t iRegion, uint32_t iNewRegion);
832
833
834	/** @name PGMR3PhysRegisterRom flags.
835	* @{ */
836	/** Inidicates that ROM shadowing should be enabled. */
837	#define PGMPHYS_ROM_FLAGS_SHADOWED RT_BIT_32(0)
838	/** Indicates that what pvBinary points to won't go away
839	* and can be used for strictness checks. */
840	#define PGMPHYS_ROM_FLAGS_PERMANENT_BINARY RT_BIT_32(1)
841	/** @} */
842
843	VMMR3DECL(int) PGMR3PhysRomRegister(PVM pVM, PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTGCPHYS cb,
844	const void pvBinary, uint32_t cbBinary, uint32_t fFlags, const char pszDesc);
845	VMMR3DECL(int) PGMR3PhysRomProtect(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, PGMROMPROT enmProt);
846	VMMR3DECL(int) PGMR3PhysRegister(PVM pVM, void pvRam, RTGCPHYS GCPhys, size_t cb, unsigned fFlags, const SUPPAGE paPages, const char *pszDesc);
847	VMMDECL(void) PGMR3PhysSetA20(PVMCPU pVCpu, bool fEnable);
848	#ifndef PGM_WITHOUT_MAPPINGS
849	/** @name PGMR3MapPT flags.
850	* @{ */
851	/** The mapping may be unmapped later. The default is permanent mappings. */
852	# define PGMR3MAPPT_FLAGS_UNMAPPABLE RT_BIT(0)
853	/** @} */
854	VMMR3DECL(int) PGMR3MapPT(PVM pVM, RTGCPTR GCPtr, uint32_t cb, uint32_t fFlags, PFNPGMRELOCATE pfnRelocate, void pvUser, const char pszDesc);
855	VMMR3DECL(int) PGMR3UnmapPT(PVM pVM, RTGCPTR GCPtr);
856	VMMR3DECL(int) PGMR3FinalizeMappings(PVM pVM);
857	VMMR3DECL(bool) PGMR3MappingsNeedReFixing(PVM pVM);
858	# if defined(VBOX_WITH_RAW_MODE) \|\| HC_ARCH_BITS == 32 /* (latter for 64-bit guests on 32-bit hosts) */
859	VMMR3DECL(int) PGMR3MapIntermediate(PVM pVM, RTUINTPTR Addr, RTHCPHYS HCPhys, unsigned cbPages);
860	# endif
861	VMMR3DECL(int) PGMR3MapRead(PVM pVM, void *pvDst, RTGCPTR GCPtrSrc, size_t cb);
862	#endif /* !PGM_WITHOUT_MAPPINGS */
863	VMMR3DECL(int) PGMR3MappingsSize(PVM pVM, uint32_t *pcb);
864	VMMR3DECL(int) PGMR3MappingsFix(PVM pVM, RTGCPTR GCPtrBase, uint32_t cb);
865	VMMR3DECL(int) PGMR3MappingsUnfix(PVM pVM);
866
867	VMMR3_INT_DECL(int) PGMR3HandlerPhysicalTypeRegisterEx(PVM pVM, PGMPHYSHANDLERKIND enmKind,
868	PFNPGMPHYSHANDLER pfnHandlerR3,
869	R0PTRTYPE(PFNPGMPHYSHANDLER) pfnHandlerR0,
870	R0PTRTYPE(PFNPGMRZPHYSPFHANDLER) pfnPfHandlerR0,
871	RCPTRTYPE(PFNPGMPHYSHANDLER) pfnHandlerRC,
872	RCPTRTYPE(PFNPGMRZPHYSPFHANDLER) pfnPfHandlerRC,
873	const char *pszDesc, PPGMPHYSHANDLERTYPE phType);
874	VMMR3DECL(int) PGMR3HandlerPhysicalTypeRegister(PVM pVM, PGMPHYSHANDLERKIND enmKind,
875	R3PTRTYPE(PFNPGMPHYSHANDLER) pfnHandlerR3,
876	const char pszModR0, const char pszHandlerR0, const char *pszPfHandlerR0,
877	const char pszModRC, const char pszHandlerRC, const char *pszPfHandlerRC,
878	const char *pszDesc,
879	PPGMPHYSHANDLERTYPE phType);
880	#ifdef VBOX_WITH_RAW_MODE
881	VMMR3_INT_DECL(int) PGMR3HandlerVirtualTypeRegisterEx(PVM pVM, PGMVIRTHANDLERKIND enmKind, bool fRelocUserRC,
882	PFNPGMR3VIRTINVALIDATE pfnInvalidateR3,
883	PFNPGMVIRTHANDLER pfnHandlerR3,
884	RCPTRTYPE(FNPGMVIRTHANDLER) pfnHandlerRC,
885	RCPTRTYPE(FNPGMRCVIRTPFHANDLER) pfnPfHandlerRC,
886	const char *pszDesc, PPGMVIRTHANDLERTYPE phType);
887	VMMR3_INT_DECL(int) PGMR3HandlerVirtualTypeRegister(PVM pVM, PGMVIRTHANDLERKIND enmKind, bool fRelocUserRC,
888	PFNPGMR3VIRTINVALIDATE pfnInvalidateR3,
889	PFNPGMVIRTHANDLER pfnHandlerR3,
890	const char pszHandlerRC, const char pszPfHandlerRC, const char *pszDesc,
891	PPGMVIRTHANDLERTYPE phType);
892	VMMR3_INT_DECL(int) PGMR3HandlerVirtualRegister(PVM pVM, PVMCPU pVCpu, PGMVIRTHANDLERTYPE hType, RTGCPTR GCPtr,
893	RTGCPTR GCPtrLast, void pvUserR3, RTRCPTR pvUserRC, const char pszDesc);
894	VMMR3_INT_DECL(int) PGMHandlerVirtualChangeType(PVM pVM, RTGCPTR GCPtr, PGMVIRTHANDLERTYPE hNewType);
895	VMMR3_INT_DECL(int) PGMHandlerVirtualDeregister(PVM pVM, PVMCPU pVCpu, RTGCPTR GCPtr, bool fHypervisor);
896	#endif
897	VMMR3DECL(int) PGMR3PoolGrow(PVM pVM);
898
899	VMMR3DECL(int) PGMR3PhysTlbGCPhys2Ptr(PVM pVM, RTGCPHYS GCPhys, bool fWritable, void **ppv);
900	VMMR3DECL(uint8_t) PGMR3PhysReadU8(PVM pVM, RTGCPHYS GCPhys, PGMACCESSORIGIN enmOrigin);
901	VMMR3DECL(uint16_t) PGMR3PhysReadU16(PVM pVM, RTGCPHYS GCPhys, PGMACCESSORIGIN enmOrigin);
902	VMMR3DECL(uint32_t) PGMR3PhysReadU32(PVM pVM, RTGCPHYS GCPhys, PGMACCESSORIGIN enmOrigin);
903	VMMR3DECL(uint64_t) PGMR3PhysReadU64(PVM pVM, RTGCPHYS GCPhys, PGMACCESSORIGIN enmOrigin);
904	VMMR3DECL(void) PGMR3PhysWriteU8(PVM pVM, RTGCPHYS GCPhys, uint8_t Value, PGMACCESSORIGIN enmOrigin);
905	VMMR3DECL(void) PGMR3PhysWriteU16(PVM pVM, RTGCPHYS GCPhys, uint16_t Value, PGMACCESSORIGIN enmOrigin);
906	VMMR3DECL(void) PGMR3PhysWriteU32(PVM pVM, RTGCPHYS GCPhys, uint32_t Value, PGMACCESSORIGIN enmOrigin);
907	VMMR3DECL(void) PGMR3PhysWriteU64(PVM pVM, RTGCPHYS GCPhys, uint64_t Value, PGMACCESSORIGIN enmOrigin);
908	VMMR3DECL(int) PGMR3PhysReadExternal(PVM pVM, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead, PGMACCESSORIGIN enmOrigin);
909	VMMR3DECL(int) PGMR3PhysWriteExternal(PVM pVM, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite, PGMACCESSORIGIN enmOrigin);
910	VMMR3DECL(int) PGMR3PhysGCPhys2CCPtrExternal(PVM pVM, RTGCPHYS GCPhys, void **ppv, PPGMPAGEMAPLOCK pLock);
911	VMMR3DECL(int) PGMR3PhysGCPhys2CCPtrReadOnlyExternal(PVM pVM, RTGCPHYS GCPhys, void const **ppv, PPGMPAGEMAPLOCK pLock);
912	VMMR3DECL(int) PGMR3PhysBulkGCPhys2CCPtrExternal(PVM pVM, uint32_t cPages, PCRTGCPHYS paGCPhysPages,
913	void **papvPages, PPGMPAGEMAPLOCK paLocks);
914	VMMR3DECL(int) PGMR3PhysBulkGCPhys2CCPtrReadOnlyExternal(PVM pVM, uint32_t cPages, PCRTGCPHYS paGCPhysPages,
915	void const **papvPages, PPGMPAGEMAPLOCK paLocks);
916	VMMR3DECL(int) PGMR3PhysChunkMap(PVM pVM, uint32_t idChunk);
917	VMMR3DECL(void) PGMR3PhysChunkInvalidateTLB(PVM pVM);
918	VMMR3DECL(int) PGMR3PhysAllocateHandyPages(PVM pVM);
919	VMMR3DECL(int) PGMR3PhysAllocateLargeHandyPage(PVM pVM, RTGCPHYS GCPhys);
920
921	VMMR3DECL(int) PGMR3CheckIntegrity(PVM pVM);
922
923	VMMR3DECL(int) PGMR3DbgR3Ptr2GCPhys(PUVM pUVM, RTR3PTR R3Ptr, PRTGCPHYS pGCPhys);
924	VMMR3DECL(int) PGMR3DbgR3Ptr2HCPhys(PUVM pUVM, RTR3PTR R3Ptr, PRTHCPHYS pHCPhys);
925	VMMR3DECL(int) PGMR3DbgHCPhys2GCPhys(PUVM pUVM, RTHCPHYS HCPhys, PRTGCPHYS pGCPhys);
926	VMMR3_INT_DECL(int) PGMR3DbgReadGCPhys(PVM pVM, void pvDst, RTGCPHYS GCPhysSrc, size_t cb, uint32_t fFlags, size_t pcbRead);
927	VMMR3_INT_DECL(int) PGMR3DbgWriteGCPhys(PVM pVM, RTGCPHYS GCPhysDst, const void pvSrc, size_t cb, uint32_t fFlags, size_t pcbWritten);
928	VMMR3_INT_DECL(int) PGMR3DbgReadGCPtr(PVM pVM, void pvDst, RTGCPTR GCPtrSrc, size_t cb, uint32_t fFlags, size_t pcbRead);
929	VMMR3_INT_DECL(int) PGMR3DbgWriteGCPtr(PVM pVM, RTGCPTR GCPtrDst, void const pvSrc, size_t cb, uint32_t fFlags, size_t pcbWritten);
930	VMMR3_INT_DECL(int) PGMR3DbgScanPhysical(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cbRange, RTGCPHYS GCPhysAlign, const uint8_t *pabNeedle, size_t cbNeedle, PRTGCPHYS pGCPhysHit);
931	VMMR3_INT_DECL(int) PGMR3DbgScanVirtual(PVM pVM, PVMCPU pVCpu, RTGCPTR GCPtr, RTGCPTR cbRange, RTGCPTR GCPtrAlign, const uint8_t *pabNeedle, size_t cbNeedle, PRTGCUINTPTR pGCPhysHit);
932	VMMR3_INT_DECL(int) PGMR3DumpHierarchyShw(PVM pVM, uint64_t cr3, uint32_t fFlags, uint64_t u64FirstAddr, uint64_t u64LastAddr, uint32_t cMaxDepth, PCDBGFINFOHLP pHlp);
933	VMMR3_INT_DECL(int) PGMR3DumpHierarchyGst(PVM pVM, uint64_t cr3, uint32_t fFlags, RTGCPTR FirstAddr, RTGCPTR LastAddr, uint32_t cMaxDepth, PCDBGFINFOHLP pHlp);
934
935
936	/** @name Page sharing
937	* @{ */
938	VMMR3DECL(int) PGMR3SharedModuleRegister(PVM pVM, VBOXOSFAMILY enmGuestOS, char pszModuleName, char pszVersion,
939	RTGCPTR GCBaseAddr, uint32_t cbModule,
940	uint32_t cRegions, VMMDEVSHAREDREGIONDESC const *paRegions);
941	VMMR3DECL(int) PGMR3SharedModuleUnregister(PVM pVM, char pszModuleName, char pszVersion,
942	RTGCPTR GCBaseAddr, uint32_t cbModule);
943	VMMR3DECL(int) PGMR3SharedModuleCheckAll(PVM pVM);
944	VMMR3DECL(int) PGMR3SharedModuleGetPageState(PVM pVM, RTGCPTR GCPtrPage, bool pfShared, uint64_t pfPageFlags);
945	/** @} */
946
947	/** @} */
948	#endif /* IN_RING3 */
949
950	RT_C_DECLS_END
951
952	/** @} */
953	#endif /* !VBOX_INCLUDED_vmm_pgm_h */
954

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source: vbox/trunk/include/VBox/vmm/pgm.h@ 80118

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