pgm.h@ 80537

Last change on this file since 80537 was 80346, checked in by vboxsync, 5 years ago
VMM,PciRaw: Eliminate duplicate PGVM/PVMCC and PGVMCPU/PVMCPUCC parameters in ring-0 code. butref:9217
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1	/** @file
2	* PGM - Page Monitor / Monitor.
3	*/
4
5	/*
6	* Copyright (C) 2006-2019 Oracle Corporation
7	*
8	* This file is part of VirtualBox Open Source Edition (OSE), as
9	* available from http://www.virtualbox.org. This file is free software;
10	* you can redistribute it and/or modify it under the terms of the GNU
11	* General Public License (GPL) as published by the Free Software
12	* Foundation, in version 2 as it comes in the "COPYING" file of the
13	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15	*
16	* The contents of this file may alternatively be used under the terms
17	* of the Common Development and Distribution License Version 1.0
18	* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19	* VirtualBox OSE distribution, in which case the provisions of the
20	* CDDL are applicable instead of those of the GPL.
21	*
22	* You may elect to license modified versions of this file under the
23	* terms and conditions of either the GPL or the CDDL or both.
24	*/
25
26	#ifndef VBOX_INCLUDED_vmm_pgm_h
27	#define VBOX_INCLUDED_vmm_pgm_h
28	#ifndef RT_WITHOUT_PRAGMA_ONCE
29	# pragma once
30	#endif
31
32	#include <VBox/types.h>
33	#include <VBox/sup.h>
34	#include <VBox/vmm/vmapi.h>
35	#include <VBox/vmm/gmm.h> /* for PGMMREGISTERSHAREDMODULEREQ */
36	#include <iprt/x86.h>
37	#include <VBox/param.h>
38
39	RT_C_DECLS_BEGIN
40
41	/** @defgroup grp_pgm The Page Monitor / Manager API
42	* @ingroup grp_vmm
43	* @{
44	*/
45
46	/**
47	* FNPGMRELOCATE callback mode.
48	*/
49	typedef enum PGMRELOCATECALL
50	{
51	/** The callback is for checking if the suggested address is suitable. */
52	PGMRELOCATECALL_SUGGEST = 1,
53	/** The callback is for executing the relocation. */
54	PGMRELOCATECALL_RELOCATE
55	} PGMRELOCATECALL;
56
57
58	/** No guest context mappings (might be removed entirely later, if we don't
59	* need it again (see new raw-mode ideas)).
60	* @internal */
61	#define PGM_WITHOUT_MAPPINGS
62
63
64	/**
65	* Callback function which will be called when PGM is trying to find
66	* a new location for the mapping.
67	*
68	* The callback is called in two modes, 1) the check mode and 2) the relocate mode.
69	* In 1) the callback should say if it objects to a suggested new location. If it
70	* accepts the new location, it is called again for doing it's relocation.
71	*
72	*
73	* @returns true if the location is ok.
74	* @returns false if another location should be found.
75	* @param pVM The cross context VM structure.
76	* @param GCPtrOld The old virtual address.
77	* @param GCPtrNew The new virtual address.
78	* @param enmMode Used to indicate the callback mode.
79	* @param pvUser User argument.
80	* @remark The return value is no a failure indicator, it's an acceptance
81	* indicator. Relocation can not fail!
82	*/
83	typedef DECLCALLBACK(bool) FNPGMRELOCATE(PVM pVM, RTGCPTR GCPtrOld, RTGCPTR GCPtrNew, PGMRELOCATECALL enmMode, void *pvUser);
84	/** Pointer to a relocation callback function. */
85	typedef FNPGMRELOCATE *PFNPGMRELOCATE;
86
87
88	/**
89	* Memory access origin.
90	*/
91	typedef enum PGMACCESSORIGIN
92	{
93	/** Invalid zero value. */
94	PGMACCESSORIGIN_INVALID = 0,
95	/** IEM is access memory. */
96	PGMACCESSORIGIN_IEM,
97	/** HM is access memory. */
98	PGMACCESSORIGIN_HM,
99	/** Some device is access memory. */
100	PGMACCESSORIGIN_DEVICE,
101	/** Someone debugging is access memory. */
102	PGMACCESSORIGIN_DEBUGGER,
103	/** SELM is access memory. */
104	PGMACCESSORIGIN_SELM,
105	/** FTM is access memory. */
106	PGMACCESSORIGIN_FTM,
107	/** REM is access memory. */
108	PGMACCESSORIGIN_REM,
109	/** IOM is access memory. */
110	PGMACCESSORIGIN_IOM,
111	/** End of valid values. */
112	PGMACCESSORIGIN_END,
113	/** Type size hack. */
114	PGMACCESSORIGIN_32BIT_HACK = 0x7fffffff
115	} PGMACCESSORIGIN;
116
117
118	/**
119	* Physical page access handler kind.
120	*/
121	typedef enum PGMPHYSHANDLERKIND
122	{
123	/** MMIO range. Pages are not present, all access is done in interpreter or recompiler. */
124	PGMPHYSHANDLERKIND_MMIO = 1,
125	/** Handler all write access to a physical page range. */
126	PGMPHYSHANDLERKIND_WRITE,
127	/** Handler all access to a physical page range. */
128	PGMPHYSHANDLERKIND_ALL
129
130	} PGMPHYSHANDLERKIND;
131
132	/**
133	* Guest Access type
134	*/
135	typedef enum PGMACCESSTYPE
136	{
137	/** Read access. */
138	PGMACCESSTYPE_READ = 1,
139	/** Write access. */
140	PGMACCESSTYPE_WRITE
141	} PGMACCESSTYPE;
142
143
144	/** @def PGM_ALL_CB_DECL
145	* Macro for declaring a handler callback for all contexts. The handler
146	* callback is static in ring-3, and exported in RC and R0.
147	* @sa PGM_ALL_CB2_DECL.
148	*/
149	#if defined(IN_RC) \|\| defined(IN_RING0)
150	# ifdef __cplusplus
151	# define PGM_ALL_CB_DECL(type) extern "C" DECLCALLBACK(DECLEXPORT(type))
152	# else
153	# define PGM_ALL_CB_DECL(type) DECLCALLBACK(DECLEXPORT(type))
154	# endif
155	#else
156	# define PGM_ALL_CB_DECL(type) static DECLCALLBACK(type)
157	#endif
158
159	/** @def PGM_ALL_CB2_DECL
160	* Macro for declaring a handler callback for all contexts. The handler
161	* callback is hidden in ring-3, and exported in RC and R0.
162	* @sa PGM_ALL_CB2_DECL.
163	*/
164	#if defined(IN_RC) \|\| defined(IN_RING0)
165	# ifdef __cplusplus
166	# define PGM_ALL_CB2_DECL(type) extern "C" DECLCALLBACK(DECLEXPORT(type))
167	# else
168	# define PGM_ALL_CB2_DECL(type) DECLCALLBACK(DECLEXPORT(type))
169	# endif
170	#else
171	# define PGM_ALL_CB2_DECL(type) DECLCALLBACK(DECLHIDDEN(type))
172	#endif
173
174	/** @def PGM_ALL_CB2_PROTO
175	* Macro for declaring a handler callback for all contexts. The handler
176	* callback is hidden in ring-3, and exported in RC and R0.
177	* @param fnType The callback function type.
178	* @sa PGM_ALL_CB2_DECL.
179	*/
180	#if defined(IN_RC) \|\| defined(IN_RING0)
181	# ifdef __cplusplus
182	# define PGM_ALL_CB2_PROTO(fnType) extern "C" DECLEXPORT(fnType)
183	# else
184	# define PGM_ALL_CB2_PROTO(fnType) DECLEXPORT(fnType)
185	# endif
186	#else
187	# define PGM_ALL_CB2_PROTO(fnType) DECLHIDDEN(fnType)
188	#endif
189
190
191	/**
192	* \#PF Handler callback for physical access handler ranges in RC and R0.
193	*
194	* @returns Strict VBox status code (appropriate for ring-0 and raw-mode).
195	* @param pVM The cross context VM structure.
196	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
197	* @param uErrorCode CPU Error code.
198	* @param pRegFrame Trap register frame.
199	* NULL on DMA and other non CPU access.
200	* @param pvFault The fault address (cr2).
201	* @param GCPhysFault The GC physical address corresponding to pvFault.
202	* @param pvUser User argument.
203	* @thread EMT(pVCpu)
204	*/
205	typedef DECLCALLBACK(VBOXSTRICTRC) FNPGMRZPHYSPFHANDLER(PVMCC pVM, PVMCPUCC pVCpu, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame,
206	RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser);
207	/** Pointer to PGM access callback. */
208	typedef FNPGMRZPHYSPFHANDLER *PFNPGMRZPHYSPFHANDLER;
209
210
211	/**
212	* Access handler callback for physical access handler ranges.
213	*
214	* The handler can not raise any faults, it's mainly for monitoring write access
215	* to certain pages (like MMIO).
216	*
217	* @returns Strict VBox status code in ring-0 and raw-mode context, in ring-3
218	* the only supported informational status code is
219	* VINF_PGM_HANDLER_DO_DEFAULT.
220	* @retval VINF_SUCCESS if the handler have carried out the operation.
221	* @retval VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the
222	* access operation.
223	* @retval VINF_EM_XXX in ring-0 and raw-mode context.
224	*
225	* @param pVM The cross context VM structure.
226	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
227	* @param GCPhys The physical address the guest is writing to.
228	* @param pvPhys The HC mapping of that address.
229	* @param pvBuf What the guest is reading/writing.
230	* @param cbBuf How much it's reading/writing.
231	* @param enmAccessType The access type.
232	* @param enmOrigin The origin of this call.
233	* @param pvUser User argument.
234	* @thread EMT(pVCpu)
235	*/
236	typedef DECLCALLBACK(VBOXSTRICTRC) FNPGMPHYSHANDLER(PVMCC pVM, PVMCPUCC pVCpu, RTGCPHYS GCPhys, void pvPhys, void pvBuf, size_t cbBuf,
237	PGMACCESSTYPE enmAccessType, PGMACCESSORIGIN enmOrigin, void *pvUser);
238	/** Pointer to PGM access callback. */
239	typedef FNPGMPHYSHANDLER *PFNPGMPHYSHANDLER;
240
241
242	/**
243	* Paging mode.
244	*
245	* @note Part of saved state. Change with extreme care.
246	*/
247	typedef enum PGMMODE
248	{
249	/** The usual invalid value. */
250	PGMMODE_INVALID = 0,
251	/** Real mode. */
252	PGMMODE_REAL,
253	/** Protected mode, no paging. */
254	PGMMODE_PROTECTED,
255	/** 32-bit paging. */
256	PGMMODE_32_BIT,
257	/** PAE paging. */
258	PGMMODE_PAE,
259	/** PAE paging with NX enabled. */
260	PGMMODE_PAE_NX,
261	/** 64-bit AMD paging (long mode). */
262	PGMMODE_AMD64,
263	/** 64-bit AMD paging (long mode) with NX enabled. */
264	PGMMODE_AMD64_NX,
265	/** 32-bit nested paging mode (shadow only; guest physical to host physical). */
266	PGMMODE_NESTED_32BIT,
267	/** PAE nested paging mode (shadow only; guest physical to host physical). */
268	PGMMODE_NESTED_PAE,
269	/** AMD64 nested paging mode (shadow only; guest physical to host physical). */
270	PGMMODE_NESTED_AMD64,
271	/** Extended paging (Intel) mode. */
272	PGMMODE_EPT,
273	/** Special mode used by NEM to indicate no shadow paging necessary. */
274	PGMMODE_NONE,
275	/** The max number of modes */
276	PGMMODE_MAX,
277	/** 32bit hackishness. */
278	PGMMODE_32BIT_HACK = 0x7fffffff
279	} PGMMODE;
280
281	/** Macro for checking if the guest is using paging.
282	* @param enmMode PGMMODE_*.
283	* @remark ASSUMES certain order of the PGMMODE_* values.
284	*/
285	#define PGMMODE_WITH_PAGING(enmMode) ((enmMode) >= PGMMODE_32_BIT)
286
287	/** Macro for checking if it's one of the long mode modes.
288	* @param enmMode PGMMODE_*.
289	*/
290	#define PGMMODE_IS_LONG_MODE(enmMode) ((enmMode) == PGMMODE_AMD64_NX \|\| (enmMode) == PGMMODE_AMD64)
291
292	/** Macro for checking if it's one of the AMD64 nested modes.
293	* @param enmMode PGMMODE_*.
294	*/
295	#define PGMMODE_IS_NESTED(enmMode) ( (enmMode) == PGMMODE_NESTED_32BIT \
296	\|\| (enmMode) == PGMMODE_NESTED_PAE \
297	\|\| (enmMode) == PGMMODE_NESTED_AMD64)
298
299	/**
300	* Is the ROM mapped (true) or is the shadow RAM mapped (false).
301	*
302	* @returns boolean.
303	* @param enmProt The PGMROMPROT value, must be valid.
304	*/
305	#define PGMROMPROT_IS_ROM(enmProt) \
306	( (enmProt) == PGMROMPROT_READ_ROM_WRITE_IGNORE \
307	\|\| (enmProt) == PGMROMPROT_READ_ROM_WRITE_RAM )
308
309
310	VMMDECL(bool) PGMIsLockOwner(PVM pVM);
311
312	VMMDECL(int) PGMRegisterStringFormatTypes(void);
313	VMMDECL(void) PGMDeregisterStringFormatTypes(void);
314	VMMDECL(RTHCPHYS) PGMGetHyperCR3(PVMCPU pVCpu);
315	VMMDECL(int) PGMTrap0eHandler(PVMCPUCC pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault);
316	VMMDECL(int) PGMPrefetchPage(PVMCPUCC pVCpu, RTGCPTR GCPtrPage);
317	VMMDECL(int) PGMVerifyAccess(PVMCPUCC pVCpu, RTGCPTR Addr, uint32_t cbSize, uint32_t fAccess);
318	VMMDECL(int) PGMIsValidAccess(PVMCPUCC pVCpu, RTGCPTR Addr, uint32_t cbSize, uint32_t fAccess);
319	VMMDECL(VBOXSTRICTRC) PGMInterpretInstruction(PVMCC pVM, PVMCPUCC pVCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault);
320	#ifndef PGM_WITHOUT_MAPPINGS
321	VMMDECL(int) PGMMap(PVM pVM, RTGCPTR GCPtr, RTHCPHYS HCPhys, uint32_t cbPages, unsigned fFlags);
322	VMMDECL(int) PGMMapGetPage(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys);
323	VMMDECL(int) PGMMapSetPage(PVM pVM, RTGCPTR GCPtr, uint64_t cb, uint64_t fFlags);
324	VMMDECL(int) PGMMapModifyPage(PVM pVM, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask);
325	# ifndef IN_RING0
326	VMMDECL(bool) PGMMapHasConflicts(PVM pVM);
327	# endif
328	# ifdef VBOX_STRICT
329	VMMDECL(void) PGMMapCheck(PVM pVM);
330	# endif
331	#endif /* !PGM_WITHOUT_MAPPINGS */
332	VMMDECL(int) PGMShwGetPage(PVMCPUCC pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys);
333	VMMDECL(int) PGMShwMakePageReadonly(PVMCPUCC pVCpu, RTGCPTR GCPtr, uint32_t fFlags);
334	VMMDECL(int) PGMShwMakePageWritable(PVMCPUCC pVCpu, RTGCPTR GCPtr, uint32_t fFlags);
335	VMMDECL(int) PGMShwMakePageNotPresent(PVMCPUCC pVCpu, RTGCPTR GCPtr, uint32_t fFlags);
336	/** @name Flags for PGMShwMakePageReadonly, PGMShwMakePageWritable and
337	* PGMShwMakePageNotPresent
338	* @{ */
339	/** The call is from an access handler for dealing with the a faulting write
340	* operation. The virtual address is within the same page. */
341	#define PGM_MK_PG_IS_WRITE_FAULT RT_BIT(0)
342	/** The page is an MMIO2. */
343	#define PGM_MK_PG_IS_MMIO2 RT_BIT(1)
344	/** @}*/
345	VMMDECL(int) PGMGstGetPage(PVMCPUCC pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys);
346	VMMDECL(bool) PGMGstIsPagePresent(PVMCPUCC pVCpu, RTGCPTR GCPtr);
347	VMMDECL(int) PGMGstSetPage(PVMCPUCC pVCpu, RTGCPTR GCPtr, size_t cb, uint64_t fFlags);
348	VMMDECL(int) PGMGstModifyPage(PVMCPUCC pVCpu, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask);
349	VMM_INT_DECL(int) PGMGstGetPaePdpes(PVMCPUCC pVCpu, PX86PDPE paPdpes);
350	VMM_INT_DECL(void) PGMGstUpdatePaePdpes(PVMCPUCC pVCpu, PCX86PDPE paPdpes);
351
352	VMMDECL(int) PGMInvalidatePage(PVMCPUCC pVCpu, RTGCPTR GCPtrPage);
353	VMMDECL(int) PGMFlushTLB(PVMCPUCC pVCpu, uint64_t cr3, bool fGlobal);
354	VMMDECL(int) PGMSyncCR3(PVMCPUCC pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal);
355	VMMDECL(int) PGMUpdateCR3(PVMCPUCC pVCpu, uint64_t cr3);
356	VMMDECL(int) PGMChangeMode(PVMCPUCC pVCpu, uint64_t cr0, uint64_t cr4, uint64_t efer);
357	VMM_INT_DECL(int) PGMHCChangeMode(PVMCC pVM, PVMCPUCC pVCpu, PGMMODE enmGuestMode);
358	VMMDECL(void) PGMCr0WpEnabled(PVMCPUCC pVCpu);
359	VMMDECL(PGMMODE) PGMGetGuestMode(PVMCPU pVCpu);
360	VMMDECL(PGMMODE) PGMGetShadowMode(PVMCPU pVCpu);
361	VMMDECL(PGMMODE) PGMGetHostMode(PVM pVM);
362	VMMDECL(const char *) PGMGetModeName(PGMMODE enmMode);
363	VMM_INT_DECL(RTGCPHYS) PGMGetGuestCR3Phys(PVMCPU pVCpu);
364	VMM_INT_DECL(void) PGMNotifyNxeChanged(PVMCPU pVCpu, bool fNxe);
365	VMMDECL(bool) PGMHasDirtyPages(PVM pVM);
366
367	/** PGM physical access handler type registration handle (heap offset, valid
368	* cross contexts without needing fixing up). Callbacks and handler type is
369	* associated with this and it is shared by all handler registrations. */
370	typedef uint32_t PGMPHYSHANDLERTYPE;
371	/** Pointer to a PGM physical handler type registration handle. */
372	typedef PGMPHYSHANDLERTYPE *PPGMPHYSHANDLERTYPE;
373	/** NIL value for PGM physical access handler type handle. */
374	#define NIL_PGMPHYSHANDLERTYPE UINT32_MAX
375	VMMDECL(uint32_t) PGMHandlerPhysicalTypeRelease(PVMCC pVM, PGMPHYSHANDLERTYPE hType);
376	VMMDECL(uint32_t) PGMHandlerPhysicalTypeRetain(PVM pVM, PGMPHYSHANDLERTYPE hType);
377
378	VMMDECL(int) PGMHandlerPhysicalRegister(PVMCC pVM, RTGCPHYS GCPhys, RTGCPHYS GCPhysLast, PGMPHYSHANDLERTYPE hType,
379	RTR3PTR pvUserR3, RTR0PTR pvUserR0, RTRCPTR pvUserRC,
380	R3PTRTYPE(const char *) pszDesc);
381	VMMDECL(int) PGMHandlerPhysicalModify(PVMCC pVM, RTGCPHYS GCPhysCurrent, RTGCPHYS GCPhys, RTGCPHYS GCPhysLast);
382	VMMDECL(int) PGMHandlerPhysicalDeregister(PVMCC pVM, RTGCPHYS GCPhys);
383	VMMDECL(int) PGMHandlerPhysicalChangeUserArgs(PVMCC pVM, RTGCPHYS GCPhys, RTR3PTR pvUserR3, RTR0PTR pvUserR0);
384	VMMDECL(int) PGMHandlerPhysicalSplit(PVMCC pVM, RTGCPHYS GCPhys, RTGCPHYS GCPhysSplit);
385	VMMDECL(int) PGMHandlerPhysicalJoin(PVMCC pVM, RTGCPHYS GCPhys1, RTGCPHYS GCPhys2);
386	VMMDECL(int) PGMHandlerPhysicalPageTempOff(PVMCC pVM, RTGCPHYS GCPhys, RTGCPHYS GCPhysPage);
387	VMMDECL(int) PGMHandlerPhysicalPageAlias(PVMCC pVM, RTGCPHYS GCPhys, RTGCPHYS GCPhysPage, RTGCPHYS GCPhysPageRemap);
388	VMMDECL(int) PGMHandlerPhysicalPageAliasHC(PVMCC pVM, RTGCPHYS GCPhys, RTGCPHYS GCPhysPage, RTHCPHYS HCPhysPageRemap);
389	VMMDECL(int) PGMHandlerPhysicalReset(PVMCC pVM, RTGCPHYS GCPhys);
390	VMMDECL(bool) PGMHandlerPhysicalIsRegistered(PVMCC pVM, RTGCPHYS GCPhys);
391
392
393	/**
394	* Page type.
395	*
396	* @remarks This enum has to fit in a 3-bit field (see PGMPAGE::u3Type).
397	* @remarks This is used in the saved state, so changes to it requires bumping
398	* the saved state version.
399	* @todo So, convert to \#defines!
400	*/
401	typedef enum PGMPAGETYPE
402	{
403	/** The usual invalid zero entry. */
404	PGMPAGETYPE_INVALID = 0,
405	/** RAM page. (RWX) */
406	PGMPAGETYPE_RAM,
407	/** MMIO2 page. (RWX) */
408	PGMPAGETYPE_MMIO2,
409	/** MMIO2 page aliased over an MMIO page. (RWX)
410	* See PGMHandlerPhysicalPageAlias(). */
411	PGMPAGETYPE_MMIO2_ALIAS_MMIO,
412	/** Special page aliased over an MMIO page. (RWX)
413	* See PGMHandlerPhysicalPageAliasHC(), but this is generally only used for
414	* VT-x's APIC access page at the moment. Treated as MMIO by everyone except
415	* the shadow paging code. */
416	PGMPAGETYPE_SPECIAL_ALIAS_MMIO,
417	/** Shadowed ROM. (RWX) */
418	PGMPAGETYPE_ROM_SHADOW,
419	/** ROM page. (R-X) */
420	PGMPAGETYPE_ROM,
421	/** MMIO page. (---) */
422	PGMPAGETYPE_MMIO,
423	/** End of valid entries. */
424	PGMPAGETYPE_END
425	} PGMPAGETYPE;
426	AssertCompile(PGMPAGETYPE_END == 8);
427
428	/** @name PGM page type predicates.
429	* @{ */
430	#define PGMPAGETYPE_IS_READABLE(a_enmType) ( (a_enmType) <= PGMPAGETYPE_ROM )
431	#define PGMPAGETYPE_IS_WRITEABLE(a_enmType) ( (a_enmType) <= PGMPAGETYPE_ROM_SHADOW )
432	#define PGMPAGETYPE_IS_RWX(a_enmType) ( (a_enmType) <= PGMPAGETYPE_ROM_SHADOW )
433	#define PGMPAGETYPE_IS_ROX(a_enmType) ( (a_enmType) == PGMPAGETYPE_ROM )
434	#define PGMPAGETYPE_IS_NP(a_enmType) ( (a_enmType) == PGMPAGETYPE_MMIO )
435	/** @} */
436
437
438	VMM_INT_DECL(PGMPAGETYPE) PGMPhysGetPageType(PVMCC pVM, RTGCPHYS GCPhys);
439
440	VMM_INT_DECL(int) PGMPhysGCPhys2HCPhys(PVMCC pVM, RTGCPHYS GCPhys, PRTHCPHYS pHCPhys);
441	VMM_INT_DECL(int) PGMPhysGCPtr2HCPhys(PVMCPUCC pVCpu, RTGCPTR GCPtr, PRTHCPHYS pHCPhys);
442	VMM_INT_DECL(int) PGMPhysGCPhys2CCPtr(PVMCC pVM, RTGCPHYS GCPhys, void **ppv, PPGMPAGEMAPLOCK pLock);
443	VMM_INT_DECL(int) PGMPhysGCPhys2CCPtrReadOnly(PVMCC pVM, RTGCPHYS GCPhys, void const **ppv, PPGMPAGEMAPLOCK pLock);
444	VMM_INT_DECL(int) PGMPhysGCPtr2CCPtr(PVMCPU pVCpu, RTGCPTR GCPtr, void **ppv, PPGMPAGEMAPLOCK pLock);
445	VMM_INT_DECL(int) PGMPhysGCPtr2CCPtrReadOnly(PVMCPUCC pVCpu, RTGCPTR GCPtr, void const **ppv, PPGMPAGEMAPLOCK pLock);
446
447	VMMDECL(bool) PGMPhysIsA20Enabled(PVMCPU pVCpu);
448	VMMDECL(bool) PGMPhysIsGCPhysValid(PVMCC pVM, RTGCPHYS GCPhys);
449	VMMDECL(bool) PGMPhysIsGCPhysNormal(PVMCC pVM, RTGCPHYS GCPhys);
450	VMMDECL(int) PGMPhysGCPtr2GCPhys(PVMCPUCC pVCpu, RTGCPTR GCPtr, PRTGCPHYS pGCPhys);
451	VMMDECL(void) PGMPhysReleasePageMappingLock(PVMCC pVM, PPGMPAGEMAPLOCK pLock);
452	VMMDECL(void) PGMPhysBulkReleasePageMappingLocks(PVMCC pVM, uint32_t cPages, PPGMPAGEMAPLOCK paLock);
453
454	/** @def PGM_PHYS_RW_IS_SUCCESS
455	* Check whether a PGMPhysRead, PGMPhysWrite, PGMPhysReadGCPtr or
456	* PGMPhysWriteGCPtr call completed the given task.
457	*
458	* @returns true if completed, false if not.
459	* @param a_rcStrict The status code.
460	* @sa IOM_SUCCESS
461	*/
462	#ifdef IN_RING3
463	# define PGM_PHYS_RW_IS_SUCCESS(a_rcStrict) \
464	( (a_rcStrict) == VINF_SUCCESS \
465	\|\| (a_rcStrict) == VINF_EM_DBG_STOP \
466	\|\| (a_rcStrict) == VINF_EM_DBG_EVENT \
467	\|\| (a_rcStrict) == VINF_EM_DBG_BREAKPOINT \
468	)
469	#elif defined(IN_RING0)
470	# define PGM_PHYS_RW_IS_SUCCESS(a_rcStrict) \
471	( (a_rcStrict) == VINF_SUCCESS \
472	\|\| (a_rcStrict) == VINF_IOM_R3_MMIO_COMMIT_WRITE \
473	\|\| (a_rcStrict) == VINF_EM_OFF \
474	\|\| (a_rcStrict) == VINF_EM_SUSPEND \
475	\|\| (a_rcStrict) == VINF_EM_RESET \
476	\|\| (a_rcStrict) == VINF_EM_HALT \
477	\|\| (a_rcStrict) == VINF_EM_DBG_STOP \
478	\|\| (a_rcStrict) == VINF_EM_DBG_EVENT \
479	\|\| (a_rcStrict) == VINF_EM_DBG_BREAKPOINT \
480	)
481	#elif defined(IN_RC)
482	# define PGM_PHYS_RW_IS_SUCCESS(a_rcStrict) \
483	( (a_rcStrict) == VINF_SUCCESS \
484	\|\| (a_rcStrict) == VINF_IOM_R3_MMIO_COMMIT_WRITE \
485	\|\| (a_rcStrict) == VINF_EM_OFF \
486	\|\| (a_rcStrict) == VINF_EM_SUSPEND \
487	\|\| (a_rcStrict) == VINF_EM_RESET \
488	\|\| (a_rcStrict) == VINF_EM_HALT \
489	\|\| (a_rcStrict) == VINF_SELM_SYNC_GDT \
490	\|\| (a_rcStrict) == VINF_EM_RAW_EMULATE_INSTR_GDT_FAULT \
491	\|\| (a_rcStrict) == VINF_EM_DBG_STOP \
492	\|\| (a_rcStrict) == VINF_EM_DBG_EVENT \
493	\|\| (a_rcStrict) == VINF_EM_DBG_BREAKPOINT \
494	)
495	#endif
496	/** @def PGM_PHYS_RW_DO_UPDATE_STRICT_RC
497	* Updates the return code with a new result.
498	*
499	* Both status codes must be successes according to PGM_PHYS_RW_IS_SUCCESS.
500	*
501	* @param a_rcStrict The current return code, to be updated.
502	* @param a_rcStrict2 The new return code to merge in.
503	*/
504	#ifdef IN_RING3
505	# define PGM_PHYS_RW_DO_UPDATE_STRICT_RC(a_rcStrict, a_rcStrict2) \
506	do { \
507	Assert(rcStrict == VINF_SUCCESS); \
508	Assert(rcStrict2 == VINF_SUCCESS); \
509	} while (0)
510	#elif defined(IN_RING0)
511	# define PGM_PHYS_RW_DO_UPDATE_STRICT_RC(a_rcStrict, a_rcStrict2) \
512	do { \
513	Assert(PGM_PHYS_RW_IS_SUCCESS(rcStrict)); \
514	Assert(PGM_PHYS_RW_IS_SUCCESS(rcStrict2)); \
515	AssertCompile(VINF_IOM_R3_MMIO_COMMIT_WRITE > VINF_EM_LAST); \
516	if ((a_rcStrict2) == VINF_SUCCESS \|\| (a_rcStrict) == (a_rcStrict2)) \
517	{ /* likely */ } \
518	else if ( (a_rcStrict) == VINF_SUCCESS \
519	\|\| (a_rcStrict) > (a_rcStrict2)) \
520	(a_rcStrict) = (a_rcStrict2); \
521	} while (0)
522	#elif defined(IN_RC)
523	# define PGM_PHYS_RW_DO_UPDATE_STRICT_RC(a_rcStrict, a_rcStrict2) \
524	do { \
525	Assert(PGM_PHYS_RW_IS_SUCCESS(rcStrict)); \
526	Assert(PGM_PHYS_RW_IS_SUCCESS(rcStrict2)); \
527	AssertCompile(VINF_SELM_SYNC_GDT > VINF_EM_LAST); \
528	AssertCompile(VINF_EM_RAW_EMULATE_INSTR_GDT_FAULT > VINF_EM_LAST); \
529	AssertCompile(VINF_EM_RAW_EMULATE_INSTR_GDT_FAULT < VINF_SELM_SYNC_GDT); \
530	AssertCompile(VINF_IOM_R3_MMIO_COMMIT_WRITE > VINF_EM_LAST); \
531	AssertCompile(VINF_IOM_R3_MMIO_COMMIT_WRITE > VINF_SELM_SYNC_GDT); \
532	AssertCompile(VINF_IOM_R3_MMIO_COMMIT_WRITE > VINF_EM_RAW_EMULATE_INSTR_GDT_FAULT); \
533	if ((a_rcStrict2) == VINF_SUCCESS \|\| (a_rcStrict) == (a_rcStrict2)) \
534	{ /* likely */ } \
535	else if ((a_rcStrict) == VINF_SUCCESS) \
536	(a_rcStrict) = (a_rcStrict2); \
537	else if ( ( (a_rcStrict) > (a_rcStrict2) \
538	&& ( (a_rcStrict2) <= VINF_EM_RESET \
539	\|\| (a_rcStrict) != VINF_EM_RAW_EMULATE_INSTR_GDT_FAULT) ) \
540	\|\| ( (a_rcStrict2) == VINF_EM_RAW_EMULATE_INSTR_GDT_FAULT \
541	&& (a_rcStrict) > VINF_EM_RESET) ) \
542	(a_rcStrict) = (a_rcStrict2); \
543	} while (0)
544	#endif
545
546	VMMDECL(VBOXSTRICTRC) PGMPhysRead(PVMCC pVM, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead, PGMACCESSORIGIN enmOrigin);
547	VMMDECL(VBOXSTRICTRC) PGMPhysWrite(PVMCC pVM, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite, PGMACCESSORIGIN enmOrigin);
548	VMMDECL(VBOXSTRICTRC) PGMPhysReadGCPtr(PVMCPUCC pVCpu, void *pvDst, RTGCPTR GCPtrSrc, size_t cb, PGMACCESSORIGIN enmOrigin);
549	VMMDECL(VBOXSTRICTRC) PGMPhysWriteGCPtr(PVMCPUCC pVCpu, RTGCPTR GCPtrDst, const void *pvSrc, size_t cb, PGMACCESSORIGIN enmOrigin);
550
551	VMMDECL(int) PGMPhysSimpleReadGCPhys(PVMCC pVM, void *pvDst, RTGCPHYS GCPhysSrc, size_t cb);
552	VMMDECL(int) PGMPhysSimpleWriteGCPhys(PVMCC pVM, RTGCPHYS GCPhysDst, const void *pvSrc, size_t cb);
553	VMMDECL(int) PGMPhysSimpleReadGCPtr(PVMCPUCC pVCpu, void *pvDst, RTGCPTR GCPtrSrc, size_t cb);
554	VMMDECL(int) PGMPhysSimpleWriteGCPtr(PVMCPUCC pVCpu, RTGCPTR GCPtrDst, const void *pvSrc, size_t cb);
555	VMMDECL(int) PGMPhysSimpleDirtyWriteGCPtr(PVMCPUCC pVCpu, RTGCPTR GCPtrDst, const void *pvSrc, size_t cb);
556	VMMDECL(int) PGMPhysInterpretedRead(PVMCPUCC pVCpu, PCPUMCTXCORE pCtxCore, void *pvDst, RTGCPTR GCPtrSrc, size_t cb);
557	VMMDECL(int) PGMPhysInterpretedReadNoHandlers(PVMCPUCC pVCpu, PCPUMCTXCORE pCtxCore, void *pvDst, RTGCUINTPTR GCPtrSrc, size_t cb, bool fRaiseTrap);
558	VMMDECL(int) PGMPhysInterpretedWriteNoHandlers(PVMCPUCC pVCpu, PCPUMCTXCORE pCtxCore, RTGCPTR GCPtrDst, void const *pvSrc, size_t cb, bool fRaiseTrap);
559
560	VMM_INT_DECL(int) PGMPhysIemGCPhys2Ptr(PVMCC pVM, PVMCPUCC pVCpu, RTGCPHYS GCPhys, bool fWritable, bool fByPassHandlers, void **ppv, PPGMPAGEMAPLOCK pLock);
561	VMM_INT_DECL(int) PGMPhysIemQueryAccess(PVMCC pVM, RTGCPHYS GCPhys, bool fWritable, bool fByPassHandlers);
562	VMM_INT_DECL(int) PGMPhysIemGCPhys2PtrNoLock(PVMCC pVM, PVMCPUCC pVCpu, RTGCPHYS GCPhys, uint64_t const volatile *puTlbPhysRev,
563	#if defined(IN_RC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
564	R3PTRTYPE(uint8_t ) ppb,
565	#else
566	R3R0PTRTYPE(uint8_t ) ppb,
567	#endif
568	uint64_t *pfTlb);
569	/** @name Flags returned by PGMPhysIemGCPhys2PtrNoLock
570	* @{ */
571	#define PGMIEMGCPHYS2PTR_F_NO_WRITE RT_BIT_32(3) /*< Not writable (IEMTLBE_F_PG_NO_WRITE). /
572	#define PGMIEMGCPHYS2PTR_F_NO_READ RT_BIT_32(4) /*< Not readable (IEMTLBE_F_PG_NO_READ). /
573	#define PGMIEMGCPHYS2PTR_F_NO_MAPPINGR3 RT_BIT_32(7) /*< No ring-3 mapping (IEMTLBE_F_NO_MAPPINGR3). /
574	/** @} */
575
576	/** Information returned by PGMPhysNemQueryPageInfo. */
577	typedef struct PGMPHYSNEMPAGEINFO
578	{
579	/** The host physical address of the page, NIL_HCPHYS if invalid page. */
580	RTHCPHYS HCPhys;
581	/** The NEM access mode for the page, NEM_PAGE_PROT_XXX */
582	uint32_t fNemProt : 8;
583	/** The NEM state associated with the PAGE. */
584	uint32_t u2NemState : 2;
585	/** The NEM state associated with the PAGE before pgmPhysPageMakeWritable was called. */
586	uint32_t u2OldNemState : 2;
587	/** Set if the page has handler. */
588	uint32_t fHasHandlers : 1;
589	/** Set if is the zero page backing it. */
590	uint32_t fZeroPage : 1;
591	/** Set if the page has handler. */
592	PGMPAGETYPE enmType;
593	} PGMPHYSNEMPAGEINFO;
594	/** Pointer to page information for NEM. */
595	typedef PGMPHYSNEMPAGEINFO *PPGMPHYSNEMPAGEINFO;
596	/**
597	* Callback for checking that the page is in sync while under the PGM lock.
598	*
599	* NEM passes this callback to PGMPhysNemQueryPageInfo to check that the page is
600	* in-sync between PGM and the native hypervisor API in an atomic fashion.
601	*
602	* @returns VBox status code.
603	* @param pVM The cross context VM structure.
604	* @param pVCpu The cross context per virtual CPU structure. Optional,
605	* see PGMPhysNemQueryPageInfo.
606	* @param GCPhys The guest physical address (not A20 masked).
607	* @param pInfo The page info structure. This function updates the
608	* u2NemState memory and the caller will update the PGMPAGE
609	* copy accordingly.
610	* @param pvUser Callback user argument.
611	*/
612	typedef DECLCALLBACK(int) FNPGMPHYSNEMCHECKPAGE(PVMCC pVM, PVMCPUCC pVCpu, RTGCPHYS GCPhys, PPGMPHYSNEMPAGEINFO pInfo, void *pvUser);
613	/** Pointer to a FNPGMPHYSNEMCHECKPAGE function. */
614	typedef FNPGMPHYSNEMCHECKPAGE *PFNPGMPHYSNEMCHECKPAGE;
615
616	VMM_INT_DECL(int) PGMPhysNemPageInfoChecker(PVMCC pVM, PVMCPUCC pVCpu, RTGCPHYS GCPhys, bool fMakeWritable,
617	PPGMPHYSNEMPAGEINFO pInfo, PFNPGMPHYSNEMCHECKPAGE pfnChecker, void *pvUser);
618
619	/**
620	* Callback for use with PGMPhysNemEnumPagesByState.
621	* @returns VBox status code.
622	* Failure status will stop enumeration immediately and return.
623	* @param pVM The cross context VM structure.
624	* @param pVCpu The cross context per virtual CPU structure. Optional,
625	* see PGMPhysNemEnumPagesByState.
626	* @param GCPhys The guest physical address (not A20 masked).
627	* @param pu2NemState Pointer to variable with the NEM state. This can be
628	* update.
629	* @param pvUser The user argument.
630	*/
631	typedef DECLCALLBACK(int) FNPGMPHYSNEMENUMCALLBACK(PVMCC pVM, PVMCPUCC pVCpu, RTGCPHYS GCPhys, uint8_t pu2NemState, void pvUser);
632	/** Pointer to a FNPGMPHYSNEMENUMCALLBACK function. */
633	typedef FNPGMPHYSNEMENUMCALLBACK *PFNPGMPHYSNEMENUMCALLBACK;
634	VMM_INT_DECL(int) PGMPhysNemEnumPagesByState(PVMCC pVM, PVMCPUCC VCpu, uint8_t uMinState,
635	PFNPGMPHYSNEMENUMCALLBACK pfnCallback, void *pvUser);
636
637
638	#ifdef VBOX_STRICT
639	VMMDECL(unsigned) PGMAssertHandlerAndFlagsInSync(PVM pVM);
640	VMMDECL(unsigned) PGMAssertNoMappingConflicts(PVM pVM);
641	VMMDECL(unsigned) PGMAssertCR3(PVMCC pVM, PVMCPUCC pVCpu, uint64_t cr3, uint64_t cr4);
642	#endif /* VBOX_STRICT */
643
644	#if defined(IN_RC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE)
645	VMMDECL(void) PGMRZDynMapStartAutoSet(PVMCPU pVCpu);
646	VMMDECL(void) PGMRZDynMapReleaseAutoSet(PVMCPU pVCpu);
647	VMMDECL(void) PGMRZDynMapFlushAutoSet(PVMCPU pVCpu);
648	VMMDECL(uint32_t) PGMRZDynMapPushAutoSubset(PVMCPU pVCpu);
649	VMMDECL(void) PGMRZDynMapPopAutoSubset(PVMCPU pVCpu, uint32_t iPrevSubset);
650	#endif
651
652	VMMDECL(int) PGMSetLargePageUsage(PVMCC pVM, bool fUseLargePages);
653
654	/**
655	* Query large page usage state
656	*
657	* @returns 0 - disabled, 1 - enabled
658	* @param pVM The cross context VM structure.
659	*/
660	#define PGMIsUsingLargePages(pVM) ((pVM)->fUseLargePages)
661
662
663	#ifdef IN_RC
664	/** @defgroup grp_pgm_gc The PGM Guest Context API
665	* @{
666	*/
667	VMMRCDECL(int) PGMRCDynMapInit(PVM pVM);
668	/** @} */
669	#endif /* IN_RC */
670
671
672	#ifdef IN_RING0
673	/** @defgroup grp_pgm_r0 The PGM Host Context Ring-0 API
674	* @{
675	*/
676	VMMR0_INT_DECL(int) PGMR0PhysAllocateHandyPages(PGVM pGVM, VMCPUID idCpu);
677	VMMR0_INT_DECL(int) PGMR0PhysFlushHandyPages(PGVM pGVM, VMCPUID idCpu);
678	VMMR0_INT_DECL(int) PGMR0PhysAllocateLargeHandyPage(PGVM pGVM, VMCPUID idCpu);
679	VMMR0_INT_DECL(int) PGMR0PhysSetupIoMmu(PGVM pGVM);
680	VMMR0DECL(int) PGMR0SharedModuleCheck(PVMCC pVM, PGVM pGVM, VMCPUID idCpu, PGMMSHAREDMODULE pModule, PCRTGCPTR64 paRegionsGCPtrs);
681	VMMR0DECL(int) PGMR0Trap0eHandlerNestedPaging(PGVM pGVM, PGVMCPU pGVCpu, PGMMODE enmShwPagingMode, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPHYS pvFault);
682	VMMR0DECL(VBOXSTRICTRC) PGMR0Trap0eHandlerNPMisconfig(PGVM pGVM, PGVMCPU pGVCpu, PGMMODE enmShwPagingMode, PCPUMCTXCORE pRegFrame, RTGCPHYS GCPhysFault, uint32_t uErr);
683	# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
684	VMMR0DECL(int) PGMR0DynMapInit(void);
685	VMMR0DECL(void) PGMR0DynMapTerm(void);
686	VMMR0DECL(int) PGMR0DynMapInitVM(PVMCC pVM);
687	VMMR0DECL(void) PGMR0DynMapTermVM(PVMCC pVM);
688	VMMR0DECL(int) PGMR0DynMapAssertIntegrity(void);
689	VMMR0DECL(bool) PGMR0DynMapStartOrMigrateAutoSet(PVMCPUCC pVCpu);
690	VMMR0DECL(void) PGMR0DynMapMigrateAutoSet(PVMCPUCC pVCpu);
691	# endif
692	/** @} */
693	#endif /* IN_RING0 */
694
695
696
697	#ifdef IN_RING3
698	/** @defgroup grp_pgm_r3 The PGM Host Context Ring-3 API
699	* @{
700	*/
701	VMMR3DECL(int) PGMR3Init(PVM pVM);
702	VMMR3DECL(int) PGMR3InitDynMap(PVM pVM);
703	VMMR3DECL(int) PGMR3InitFinalize(PVM pVM);
704	VMMR3_INT_DECL(int) PGMR3InitCompleted(PVM pVM, VMINITCOMPLETED enmWhat);
705	VMMR3DECL(void) PGMR3Relocate(PVM pVM, RTGCINTPTR offDelta);
706	VMMR3DECL(void) PGMR3ResetCpu(PVM pVM, PVMCPU pVCpu);
707	VMMR3_INT_DECL(void) PGMR3Reset(PVM pVM);
708	VMMR3_INT_DECL(void) PGMR3ResetNoMorePhysWritesFlag(PVM pVM);
709	VMMR3_INT_DECL(void) PGMR3MemSetup(PVM pVM, bool fReset);
710	VMMR3DECL(int) PGMR3Term(PVM pVM);
711	VMMR3DECL(int) PGMR3LockCall(PVM pVM);
712
713	VMMR3DECL(int) PGMR3PhysRegisterRam(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, const char *pszDesc);
714	VMMR3DECL(int) PGMR3PhysChangeMemBalloon(PVM pVM, bool fInflate, unsigned cPages, RTGCPHYS *paPhysPage);
715	VMMR3DECL(int) PGMR3PhysWriteProtectRAM(PVM pVM);
716	VMMR3DECL(uint32_t) PGMR3PhysGetRamRangeCount(PVM pVM);
717	VMMR3DECL(int) PGMR3PhysGetRange(PVM pVM, uint32_t iRange, PRTGCPHYS pGCPhysStart, PRTGCPHYS pGCPhysLast,
718	const char *ppszDesc, bool pfIsMmio);
719	VMMR3DECL(int) PGMR3QueryMemoryStats(PUVM pUVM, uint64_t pcbTotalMem, uint64_t pcbPrivateMem, uint64_t pcbSharedMem, uint64_t pcbZeroMem);
720	VMMR3DECL(int) PGMR3QueryGlobalMemoryStats(PUVM pUVM, uint64_t pcbAllocMem, uint64_t pcbFreeMem, uint64_t pcbBallonedMem, uint64_t pcbSharedMem);
721
722	VMMR3DECL(int) PGMR3PhysMMIORegister(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, PGMPHYSHANDLERTYPE hType,
723	RTR3PTR pvUserR3, RTR0PTR pvUserR0, RTRCPTR pvUserRC, const char *pszDesc);
724	VMMR3DECL(int) PGMR3PhysMMIODeregister(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb);
725	VMMR3DECL(int) PGMR3PhysMMIO2Register(PVM pVM, PPDMDEVINS pDevIns, uint32_t iSubDev, uint32_t iRegion, RTGCPHYS cb, uint32_t fFlags, void *ppv, const char pszDesc);
726	VMMR3DECL(int) PGMR3PhysMMIOExPreRegister(PVM pVM, PPDMDEVINS pDevIns, uint32_t iSubDev, uint32_t iRegion, RTGCPHYS cbRegion, PGMPHYSHANDLERTYPE hType,
727	RTR3PTR pvUserR3, RTR0PTR pvUserR0, RTRCPTR pvUserRC, const char *pszDesc);
728	VMMR3DECL(int) PGMR3PhysMMIOExDeregister(PVM pVM, PPDMDEVINS pDevIns, uint32_t iSubDev, uint32_t iRegion);
729	VMMR3DECL(int) PGMR3PhysMMIOExMap(PVM pVM, PPDMDEVINS pDevIns, uint32_t iSubDev, uint32_t iRegion, RTGCPHYS GCPhys);
730	VMMR3DECL(int) PGMR3PhysMMIOExUnmap(PVM pVM, PPDMDEVINS pDevIns, uint32_t iSubDev, uint32_t iRegion, RTGCPHYS GCPhys);
731	VMMR3_INT_DECL(int) PGMR3PhysMMIOExReduce(PVM pVM, PPDMDEVINS pDevIns, uint32_t iSubDev, uint32_t iRegion, RTGCPHYS cbRegion);
732	VMMR3DECL(bool) PGMR3PhysMMIOExIsBase(PVM pVM, PPDMDEVINS pDevIns, RTGCPHYS GCPhys);
733	VMMR3_INT_DECL(int) PGMR3PhysMMIO2GetHCPhys(PVM pVM, PPDMDEVINS pDevIns, uint32_t iSubDev, uint32_t iRegion, RTGCPHYS off, PRTHCPHYS pHCPhys);
734	VMMR3_INT_DECL(int) PGMR3PhysMMIO2MapKernel(PVM pVM, PPDMDEVINS pDevIns, uint32_t iSubDev, uint32_t iRegion, RTGCPHYS off, RTGCPHYS cb, const char *pszDesc, PRTR0PTR pR0Ptr);
735	VMMR3_INT_DECL(int) PGMR3PhysMMIOExChangeRegionNo(PVM pVM, PPDMDEVINS pDevIns, uint32_t iSubDev, uint32_t iRegion, uint32_t iNewRegion);
736
737
738	/** @name PGMR3PhysRegisterRom flags.
739	* @{ */
740	/** Inidicates that ROM shadowing should be enabled. */
741	#define PGMPHYS_ROM_FLAGS_SHADOWED RT_BIT_32(0)
742	/** Indicates that what pvBinary points to won't go away
743	* and can be used for strictness checks. */
744	#define PGMPHYS_ROM_FLAGS_PERMANENT_BINARY RT_BIT_32(1)
745	/** @} */
746
747	VMMR3DECL(int) PGMR3PhysRomRegister(PVM pVM, PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTGCPHYS cb,
748	const void pvBinary, uint32_t cbBinary, uint32_t fFlags, const char pszDesc);
749	VMMR3DECL(int) PGMR3PhysRomProtect(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, PGMROMPROT enmProt);
750	VMMR3DECL(int) PGMR3PhysRegister(PVM pVM, void pvRam, RTGCPHYS GCPhys, size_t cb, unsigned fFlags, const SUPPAGE paPages, const char *pszDesc);
751	VMMDECL(void) PGMR3PhysSetA20(PVMCPU pVCpu, bool fEnable);
752	#ifndef PGM_WITHOUT_MAPPINGS
753	/** @name PGMR3MapPT flags.
754	* @{ */
755	/** The mapping may be unmapped later. The default is permanent mappings. */
756	# define PGMR3MAPPT_FLAGS_UNMAPPABLE RT_BIT(0)
757	/** @} */
758	VMMR3DECL(int) PGMR3MapPT(PVM pVM, RTGCPTR GCPtr, uint32_t cb, uint32_t fFlags, PFNPGMRELOCATE pfnRelocate, void pvUser, const char pszDesc);
759	VMMR3DECL(int) PGMR3UnmapPT(PVM pVM, RTGCPTR GCPtr);
760	VMMR3DECL(int) PGMR3FinalizeMappings(PVM pVM);
761	VMMR3DECL(bool) PGMR3MappingsNeedReFixing(PVM pVM);
762	# if defined(VBOX_WITH_RAW_MODE) \|\| HC_ARCH_BITS == 32 /* (latter for 64-bit guests on 32-bit hosts) */
763	VMMR3DECL(int) PGMR3MapIntermediate(PVM pVM, RTUINTPTR Addr, RTHCPHYS HCPhys, unsigned cbPages);
764	# endif
765	VMMR3DECL(int) PGMR3MapRead(PVM pVM, void *pvDst, RTGCPTR GCPtrSrc, size_t cb);
766	#endif /* !PGM_WITHOUT_MAPPINGS */
767	VMMR3DECL(int) PGMR3MappingsSize(PVM pVM, uint32_t *pcb);
768	VMMR3DECL(int) PGMR3MappingsFix(PVM pVM, RTGCPTR GCPtrBase, uint32_t cb);
769	VMMR3DECL(int) PGMR3MappingsUnfix(PVM pVM);
770
771	VMMR3_INT_DECL(int) PGMR3HandlerPhysicalTypeRegisterEx(PVM pVM, PGMPHYSHANDLERKIND enmKind,
772	PFNPGMPHYSHANDLER pfnHandlerR3,
773	R0PTRTYPE(PFNPGMPHYSHANDLER) pfnHandlerR0,
774	R0PTRTYPE(PFNPGMRZPHYSPFHANDLER) pfnPfHandlerR0,
775	const char *pszDesc, PPGMPHYSHANDLERTYPE phType);
776	VMMR3DECL(int) PGMR3HandlerPhysicalTypeRegister(PVM pVM, PGMPHYSHANDLERKIND enmKind,
777	R3PTRTYPE(PFNPGMPHYSHANDLER) pfnHandlerR3,
778	const char pszModR0, const char pszHandlerR0, const char *pszPfHandlerR0,
779	const char pszModRC, const char pszHandlerRC, const char *pszPfHandlerRC,
780	const char *pszDesc,
781	PPGMPHYSHANDLERTYPE phType);
782	VMMR3DECL(int) PGMR3PoolGrow(PVM pVM);
783
784	VMMR3DECL(int) PGMR3PhysTlbGCPhys2Ptr(PVM pVM, RTGCPHYS GCPhys, bool fWritable, void **ppv);
785	VMMR3DECL(uint8_t) PGMR3PhysReadU8(PVM pVM, RTGCPHYS GCPhys, PGMACCESSORIGIN enmOrigin);
786	VMMR3DECL(uint16_t) PGMR3PhysReadU16(PVM pVM, RTGCPHYS GCPhys, PGMACCESSORIGIN enmOrigin);
787	VMMR3DECL(uint32_t) PGMR3PhysReadU32(PVM pVM, RTGCPHYS GCPhys, PGMACCESSORIGIN enmOrigin);
788	VMMR3DECL(uint64_t) PGMR3PhysReadU64(PVM pVM, RTGCPHYS GCPhys, PGMACCESSORIGIN enmOrigin);
789	VMMR3DECL(void) PGMR3PhysWriteU8(PVM pVM, RTGCPHYS GCPhys, uint8_t Value, PGMACCESSORIGIN enmOrigin);
790	VMMR3DECL(void) PGMR3PhysWriteU16(PVM pVM, RTGCPHYS GCPhys, uint16_t Value, PGMACCESSORIGIN enmOrigin);
791	VMMR3DECL(void) PGMR3PhysWriteU32(PVM pVM, RTGCPHYS GCPhys, uint32_t Value, PGMACCESSORIGIN enmOrigin);
792	VMMR3DECL(void) PGMR3PhysWriteU64(PVM pVM, RTGCPHYS GCPhys, uint64_t Value, PGMACCESSORIGIN enmOrigin);
793	VMMR3DECL(int) PGMR3PhysReadExternal(PVM pVM, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead, PGMACCESSORIGIN enmOrigin);
794	VMMR3DECL(int) PGMR3PhysWriteExternal(PVM pVM, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite, PGMACCESSORIGIN enmOrigin);
795	VMMR3DECL(int) PGMR3PhysGCPhys2CCPtrExternal(PVM pVM, RTGCPHYS GCPhys, void **ppv, PPGMPAGEMAPLOCK pLock);
796	VMMR3DECL(int) PGMR3PhysGCPhys2CCPtrReadOnlyExternal(PVM pVM, RTGCPHYS GCPhys, void const **ppv, PPGMPAGEMAPLOCK pLock);
797	VMMR3DECL(int) PGMR3PhysBulkGCPhys2CCPtrExternal(PVM pVM, uint32_t cPages, PCRTGCPHYS paGCPhysPages,
798	void **papvPages, PPGMPAGEMAPLOCK paLocks);
799	VMMR3DECL(int) PGMR3PhysBulkGCPhys2CCPtrReadOnlyExternal(PVM pVM, uint32_t cPages, PCRTGCPHYS paGCPhysPages,
800	void const **papvPages, PPGMPAGEMAPLOCK paLocks);
801	VMMR3DECL(int) PGMR3PhysChunkMap(PVM pVM, uint32_t idChunk);
802	VMMR3DECL(void) PGMR3PhysChunkInvalidateTLB(PVM pVM);
803	VMMR3DECL(int) PGMR3PhysAllocateHandyPages(PVM pVM);
804	VMMR3DECL(int) PGMR3PhysAllocateLargeHandyPage(PVM pVM, RTGCPHYS GCPhys);
805
806	VMMR3DECL(int) PGMR3CheckIntegrity(PVM pVM);
807
808	VMMR3DECL(int) PGMR3DbgR3Ptr2GCPhys(PUVM pUVM, RTR3PTR R3Ptr, PRTGCPHYS pGCPhys);
809	VMMR3DECL(int) PGMR3DbgR3Ptr2HCPhys(PUVM pUVM, RTR3PTR R3Ptr, PRTHCPHYS pHCPhys);
810	VMMR3DECL(int) PGMR3DbgHCPhys2GCPhys(PUVM pUVM, RTHCPHYS HCPhys, PRTGCPHYS pGCPhys);
811	VMMR3_INT_DECL(int) PGMR3DbgReadGCPhys(PVM pVM, void pvDst, RTGCPHYS GCPhysSrc, size_t cb, uint32_t fFlags, size_t pcbRead);
812	VMMR3_INT_DECL(int) PGMR3DbgWriteGCPhys(PVM pVM, RTGCPHYS GCPhysDst, const void pvSrc, size_t cb, uint32_t fFlags, size_t pcbWritten);
813	VMMR3_INT_DECL(int) PGMR3DbgReadGCPtr(PVM pVM, void pvDst, RTGCPTR GCPtrSrc, size_t cb, uint32_t fFlags, size_t pcbRead);
814	VMMR3_INT_DECL(int) PGMR3DbgWriteGCPtr(PVM pVM, RTGCPTR GCPtrDst, void const pvSrc, size_t cb, uint32_t fFlags, size_t pcbWritten);
815	VMMR3_INT_DECL(int) PGMR3DbgScanPhysical(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cbRange, RTGCPHYS GCPhysAlign, const uint8_t *pabNeedle, size_t cbNeedle, PRTGCPHYS pGCPhysHit);
816	VMMR3_INT_DECL(int) PGMR3DbgScanVirtual(PVM pVM, PVMCPU pVCpu, RTGCPTR GCPtr, RTGCPTR cbRange, RTGCPTR GCPtrAlign, const uint8_t *pabNeedle, size_t cbNeedle, PRTGCUINTPTR pGCPhysHit);
817	VMMR3_INT_DECL(int) PGMR3DumpHierarchyShw(PVM pVM, uint64_t cr3, uint32_t fFlags, uint64_t u64FirstAddr, uint64_t u64LastAddr, uint32_t cMaxDepth, PCDBGFINFOHLP pHlp);
818	VMMR3_INT_DECL(int) PGMR3DumpHierarchyGst(PVM pVM, uint64_t cr3, uint32_t fFlags, RTGCPTR FirstAddr, RTGCPTR LastAddr, uint32_t cMaxDepth, PCDBGFINFOHLP pHlp);
819
820
821	/** @name Page sharing
822	* @{ */
823	VMMR3DECL(int) PGMR3SharedModuleRegister(PVM pVM, VBOXOSFAMILY enmGuestOS, char pszModuleName, char pszVersion,
824	RTGCPTR GCBaseAddr, uint32_t cbModule,
825	uint32_t cRegions, VMMDEVSHAREDREGIONDESC const *paRegions);
826	VMMR3DECL(int) PGMR3SharedModuleUnregister(PVM pVM, char pszModuleName, char pszVersion,
827	RTGCPTR GCBaseAddr, uint32_t cbModule);
828	VMMR3DECL(int) PGMR3SharedModuleCheckAll(PVM pVM);
829	VMMR3DECL(int) PGMR3SharedModuleGetPageState(PVM pVM, RTGCPTR GCPtrPage, bool pfShared, uint64_t pfPageFlags);
830	/** @} */
831
832	/** @} */
833	#endif /* IN_RING3 */
834
835	RT_C_DECLS_END
836
837	/** @} */
838	#endif /* !VBOX_INCLUDED_vmm_pgm_h */
839

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source: vbox/trunk/include/VBox/vmm/pgm.h@ 80537

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