pgm.h@ 82555

Last change on this file since 82555 was 82555, checked in by vboxsync, 5 years ago
PGMPool,MM: Use ring-0 mapping while in ring-0, so let the page pool do its own allocations rather than going through MMPage. The MMPage code is mostly code, but we still need it for a dummy page allocation. I'll address this tomorrow. bugref:9528
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1	/** @file
2	* PGM - Page Monitor / Monitor.
3	*/
4
5	/*
6	* Copyright (C) 2006-2019 Oracle Corporation
7	*
8	* This file is part of VirtualBox Open Source Edition (OSE), as
9	* available from http://www.virtualbox.org. This file is free software;
10	* you can redistribute it and/or modify it under the terms of the GNU
11	* General Public License (GPL) as published by the Free Software
12	* Foundation, in version 2 as it comes in the "COPYING" file of the
13	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15	*
16	* The contents of this file may alternatively be used under the terms
17	* of the Common Development and Distribution License Version 1.0
18	* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19	* VirtualBox OSE distribution, in which case the provisions of the
20	* CDDL are applicable instead of those of the GPL.
21	*
22	* You may elect to license modified versions of this file under the
23	* terms and conditions of either the GPL or the CDDL or both.
24	*/
25
26	#ifndef VBOX_INCLUDED_vmm_pgm_h
27	#define VBOX_INCLUDED_vmm_pgm_h
28	#ifndef RT_WITHOUT_PRAGMA_ONCE
29	# pragma once
30	#endif
31
32	#include <VBox/types.h>
33	#include <VBox/sup.h>
34	#include <VBox/vmm/vmapi.h>
35	#include <VBox/vmm/gmm.h> /* for PGMMREGISTERSHAREDMODULEREQ */
36	#include <iprt/x86.h>
37	#include <VBox/param.h>
38
39	RT_C_DECLS_BEGIN
40
41	/** @defgroup grp_pgm The Page Monitor / Manager API
42	* @ingroup grp_vmm
43	* @{
44	*/
45
46	/**
47	* FNPGMRELOCATE callback mode.
48	*/
49	typedef enum PGMRELOCATECALL
50	{
51	/** The callback is for checking if the suggested address is suitable. */
52	PGMRELOCATECALL_SUGGEST = 1,
53	/** The callback is for executing the relocation. */
54	PGMRELOCATECALL_RELOCATE
55	} PGMRELOCATECALL;
56
57
58	/** No guest context mappings (might be removed entirely later, if we don't
59	* need it again (see new raw-mode ideas)).
60	* @internal */
61	#define PGM_WITHOUT_MAPPINGS
62
63
64	/**
65	* Callback function which will be called when PGM is trying to find
66	* a new location for the mapping.
67	*
68	* The callback is called in two modes, 1) the check mode and 2) the relocate mode.
69	* In 1) the callback should say if it objects to a suggested new location. If it
70	* accepts the new location, it is called again for doing it's relocation.
71	*
72	*
73	* @returns true if the location is ok.
74	* @returns false if another location should be found.
75	* @param pVM The cross context VM structure.
76	* @param GCPtrOld The old virtual address.
77	* @param GCPtrNew The new virtual address.
78	* @param enmMode Used to indicate the callback mode.
79	* @param pvUser User argument.
80	* @remark The return value is no a failure indicator, it's an acceptance
81	* indicator. Relocation can not fail!
82	*/
83	typedef DECLCALLBACK(bool) FNPGMRELOCATE(PVM pVM, RTGCPTR GCPtrOld, RTGCPTR GCPtrNew, PGMRELOCATECALL enmMode, void *pvUser);
84	/** Pointer to a relocation callback function. */
85	typedef FNPGMRELOCATE *PFNPGMRELOCATE;
86
87
88	/**
89	* Memory access origin.
90	*/
91	typedef enum PGMACCESSORIGIN
92	{
93	/** Invalid zero value. */
94	PGMACCESSORIGIN_INVALID = 0,
95	/** IEM is access memory. */
96	PGMACCESSORIGIN_IEM,
97	/** HM is access memory. */
98	PGMACCESSORIGIN_HM,
99	/** Some device is access memory. */
100	PGMACCESSORIGIN_DEVICE,
101	/** Someone debugging is access memory. */
102	PGMACCESSORIGIN_DEBUGGER,
103	/** SELM is access memory. */
104	PGMACCESSORIGIN_SELM,
105	/** FTM is access memory. */
106	PGMACCESSORIGIN_FTM,
107	/** REM is access memory. */
108	PGMACCESSORIGIN_REM,
109	/** IOM is access memory. */
110	PGMACCESSORIGIN_IOM,
111	/** End of valid values. */
112	PGMACCESSORIGIN_END,
113	/** Type size hack. */
114	PGMACCESSORIGIN_32BIT_HACK = 0x7fffffff
115	} PGMACCESSORIGIN;
116
117
118	/**
119	* Physical page access handler kind.
120	*/
121	typedef enum PGMPHYSHANDLERKIND
122	{
123	/** MMIO range. Pages are not present, all access is done in interpreter or recompiler. */
124	PGMPHYSHANDLERKIND_MMIO = 1,
125	/** Handler all write access to a physical page range. */
126	PGMPHYSHANDLERKIND_WRITE,
127	/** Handler all access to a physical page range. */
128	PGMPHYSHANDLERKIND_ALL
129
130	} PGMPHYSHANDLERKIND;
131
132	/**
133	* Guest Access type
134	*/
135	typedef enum PGMACCESSTYPE
136	{
137	/** Read access. */
138	PGMACCESSTYPE_READ = 1,
139	/** Write access. */
140	PGMACCESSTYPE_WRITE
141	} PGMACCESSTYPE;
142
143
144	/** @def PGM_ALL_CB_DECL
145	* Macro for declaring a handler callback for all contexts. The handler
146	* callback is static in ring-3, and exported in RC and R0.
147	* @sa PGM_ALL_CB2_DECL.
148	*/
149	#if defined(IN_RC) \|\| defined(IN_RING0)
150	# ifdef __cplusplus
151	# define PGM_ALL_CB_DECL(type) extern "C" DECLCALLBACK(DECLEXPORT(type))
152	# else
153	# define PGM_ALL_CB_DECL(type) DECLCALLBACK(DECLEXPORT(type))
154	# endif
155	#else
156	# define PGM_ALL_CB_DECL(type) static DECLCALLBACK(type)
157	#endif
158
159	/** @def PGM_ALL_CB2_DECL
160	* Macro for declaring a handler callback for all contexts. The handler
161	* callback is hidden in ring-3, and exported in RC and R0.
162	* @sa PGM_ALL_CB2_DECL.
163	*/
164	#if defined(IN_RC) \|\| defined(IN_RING0)
165	# ifdef __cplusplus
166	# define PGM_ALL_CB2_DECL(type) extern "C" DECLCALLBACK(DECLEXPORT(type))
167	# else
168	# define PGM_ALL_CB2_DECL(type) DECLCALLBACK(DECLEXPORT(type))
169	# endif
170	#else
171	# define PGM_ALL_CB2_DECL(type) DECLCALLBACK(DECLHIDDEN(type))
172	#endif
173
174	/** @def PGM_ALL_CB2_PROTO
175	* Macro for declaring a handler callback for all contexts. The handler
176	* callback is hidden in ring-3, and exported in RC and R0.
177	* @param fnType The callback function type.
178	* @sa PGM_ALL_CB2_DECL.
179	*/
180	#if defined(IN_RC) \|\| defined(IN_RING0)
181	# ifdef __cplusplus
182	# define PGM_ALL_CB2_PROTO(fnType) extern "C" DECLEXPORT(fnType)
183	# else
184	# define PGM_ALL_CB2_PROTO(fnType) DECLEXPORT(fnType)
185	# endif
186	#else
187	# define PGM_ALL_CB2_PROTO(fnType) DECLHIDDEN(fnType)
188	#endif
189
190
191	/**
192	* \#PF Handler callback for physical access handler ranges in RC and R0.
193	*
194	* @returns Strict VBox status code (appropriate for ring-0 and raw-mode).
195	* @param pVM The cross context VM structure.
196	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
197	* @param uErrorCode CPU Error code.
198	* @param pRegFrame Trap register frame.
199	* NULL on DMA and other non CPU access.
200	* @param pvFault The fault address (cr2).
201	* @param GCPhysFault The GC physical address corresponding to pvFault.
202	* @param pvUser User argument.
203	* @thread EMT(pVCpu)
204	*/
205	typedef DECLCALLBACK(VBOXSTRICTRC) FNPGMRZPHYSPFHANDLER(PVMCC pVM, PVMCPUCC pVCpu, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame,
206	RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser);
207	/** Pointer to PGM access callback. */
208	typedef FNPGMRZPHYSPFHANDLER *PFNPGMRZPHYSPFHANDLER;
209
210
211	/**
212	* Access handler callback for physical access handler ranges.
213	*
214	* The handler can not raise any faults, it's mainly for monitoring write access
215	* to certain pages (like MMIO).
216	*
217	* @returns Strict VBox status code in ring-0 and raw-mode context, in ring-3
218	* the only supported informational status code is
219	* VINF_PGM_HANDLER_DO_DEFAULT.
220	* @retval VINF_SUCCESS if the handler have carried out the operation.
221	* @retval VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the
222	* access operation.
223	* @retval VINF_EM_XXX in ring-0 and raw-mode context.
224	*
225	* @param pVM The cross context VM structure.
226	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
227	* @param GCPhys The physical address the guest is writing to.
228	* @param pvPhys The HC mapping of that address.
229	* @param pvBuf What the guest is reading/writing.
230	* @param cbBuf How much it's reading/writing.
231	* @param enmAccessType The access type.
232	* @param enmOrigin The origin of this call.
233	* @param pvUser User argument.
234	* @thread EMT(pVCpu)
235	*/
236	typedef DECLCALLBACK(VBOXSTRICTRC) FNPGMPHYSHANDLER(PVMCC pVM, PVMCPUCC pVCpu, RTGCPHYS GCPhys, void pvPhys, void pvBuf, size_t cbBuf,
237	PGMACCESSTYPE enmAccessType, PGMACCESSORIGIN enmOrigin, void *pvUser);
238	/** Pointer to PGM access callback. */
239	typedef FNPGMPHYSHANDLER *PFNPGMPHYSHANDLER;
240
241
242	/**
243	* Paging mode.
244	*
245	* @note Part of saved state. Change with extreme care.
246	*/
247	typedef enum PGMMODE
248	{
249	/** The usual invalid value. */
250	PGMMODE_INVALID = 0,
251	/** Real mode. */
252	PGMMODE_REAL,
253	/** Protected mode, no paging. */
254	PGMMODE_PROTECTED,
255	/** 32-bit paging. */
256	PGMMODE_32_BIT,
257	/** PAE paging. */
258	PGMMODE_PAE,
259	/** PAE paging with NX enabled. */
260	PGMMODE_PAE_NX,
261	/** 64-bit AMD paging (long mode). */
262	PGMMODE_AMD64,
263	/** 64-bit AMD paging (long mode) with NX enabled. */
264	PGMMODE_AMD64_NX,
265	/** 32-bit nested paging mode (shadow only; guest physical to host physical). */
266	PGMMODE_NESTED_32BIT,
267	/** PAE nested paging mode (shadow only; guest physical to host physical). */
268	PGMMODE_NESTED_PAE,
269	/** AMD64 nested paging mode (shadow only; guest physical to host physical). */
270	PGMMODE_NESTED_AMD64,
271	/** Extended paging (Intel) mode. */
272	PGMMODE_EPT,
273	/** Special mode used by NEM to indicate no shadow paging necessary. */
274	PGMMODE_NONE,
275	/** The max number of modes */
276	PGMMODE_MAX,
277	/** 32bit hackishness. */
278	PGMMODE_32BIT_HACK = 0x7fffffff
279	} PGMMODE;
280
281	/** Macro for checking if the guest is using paging.
282	* @param enmMode PGMMODE_*.
283	* @remark ASSUMES certain order of the PGMMODE_* values.
284	*/
285	#define PGMMODE_WITH_PAGING(enmMode) ((enmMode) >= PGMMODE_32_BIT)
286
287	/** Macro for checking if it's one of the long mode modes.
288	* @param enmMode PGMMODE_*.
289	*/
290	#define PGMMODE_IS_LONG_MODE(enmMode) ((enmMode) == PGMMODE_AMD64_NX \|\| (enmMode) == PGMMODE_AMD64)
291
292	/** Macro for checking if it's one of the AMD64 nested modes.
293	* @param enmMode PGMMODE_*.
294	*/
295	#define PGMMODE_IS_NESTED(enmMode) ( (enmMode) == PGMMODE_NESTED_32BIT \
296	\|\| (enmMode) == PGMMODE_NESTED_PAE \
297	\|\| (enmMode) == PGMMODE_NESTED_AMD64)
298
299	/**
300	* Is the ROM mapped (true) or is the shadow RAM mapped (false).
301	*
302	* @returns boolean.
303	* @param enmProt The PGMROMPROT value, must be valid.
304	*/
305	#define PGMROMPROT_IS_ROM(enmProt) \
306	( (enmProt) == PGMROMPROT_READ_ROM_WRITE_IGNORE \
307	\|\| (enmProt) == PGMROMPROT_READ_ROM_WRITE_RAM )
308
309
310	VMMDECL(bool) PGMIsLockOwner(PVM pVM);
311
312	VMMDECL(int) PGMRegisterStringFormatTypes(void);
313	VMMDECL(void) PGMDeregisterStringFormatTypes(void);
314	VMMDECL(RTHCPHYS) PGMGetHyperCR3(PVMCPU pVCpu);
315	VMMDECL(int) PGMTrap0eHandler(PVMCPUCC pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault);
316	VMMDECL(int) PGMPrefetchPage(PVMCPUCC pVCpu, RTGCPTR GCPtrPage);
317	VMMDECL(int) PGMVerifyAccess(PVMCPUCC pVCpu, RTGCPTR Addr, uint32_t cbSize, uint32_t fAccess);
318	VMMDECL(int) PGMIsValidAccess(PVMCPUCC pVCpu, RTGCPTR Addr, uint32_t cbSize, uint32_t fAccess);
319	VMMDECL(VBOXSTRICTRC) PGMInterpretInstruction(PVMCC pVM, PVMCPUCC pVCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault);
320	#ifndef PGM_WITHOUT_MAPPINGS
321	VMMDECL(int) PGMMap(PVM pVM, RTGCPTR GCPtr, RTHCPHYS HCPhys, uint32_t cbPages, unsigned fFlags);
322	VMMDECL(int) PGMMapGetPage(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys);
323	VMMDECL(int) PGMMapSetPage(PVM pVM, RTGCPTR GCPtr, uint64_t cb, uint64_t fFlags);
324	VMMDECL(int) PGMMapModifyPage(PVM pVM, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask);
325	# ifndef IN_RING0
326	VMMDECL(bool) PGMMapHasConflicts(PVM pVM);
327	# endif
328	# ifdef VBOX_STRICT
329	VMMDECL(void) PGMMapCheck(PVM pVM);
330	# endif
331	#endif /* !PGM_WITHOUT_MAPPINGS */
332	VMMDECL(int) PGMShwGetPage(PVMCPUCC pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys);
333	VMMDECL(int) PGMShwMakePageReadonly(PVMCPUCC pVCpu, RTGCPTR GCPtr, uint32_t fFlags);
334	VMMDECL(int) PGMShwMakePageWritable(PVMCPUCC pVCpu, RTGCPTR GCPtr, uint32_t fFlags);
335	VMMDECL(int) PGMShwMakePageNotPresent(PVMCPUCC pVCpu, RTGCPTR GCPtr, uint32_t fFlags);
336	/** @name Flags for PGMShwMakePageReadonly, PGMShwMakePageWritable and
337	* PGMShwMakePageNotPresent
338	* @{ */
339	/** The call is from an access handler for dealing with the a faulting write
340	* operation. The virtual address is within the same page. */
341	#define PGM_MK_PG_IS_WRITE_FAULT RT_BIT(0)
342	/** The page is an MMIO2. */
343	#define PGM_MK_PG_IS_MMIO2 RT_BIT(1)
344	/** @}*/
345	VMMDECL(int) PGMGstGetPage(PVMCPUCC pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys);
346	VMMDECL(bool) PGMGstIsPagePresent(PVMCPUCC pVCpu, RTGCPTR GCPtr);
347	VMMDECL(int) PGMGstSetPage(PVMCPUCC pVCpu, RTGCPTR GCPtr, size_t cb, uint64_t fFlags);
348	VMMDECL(int) PGMGstModifyPage(PVMCPUCC pVCpu, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask);
349	VMM_INT_DECL(int) PGMGstGetPaePdpes(PVMCPUCC pVCpu, PX86PDPE paPdpes);
350	VMM_INT_DECL(void) PGMGstUpdatePaePdpes(PVMCPUCC pVCpu, PCX86PDPE paPdpes);
351
352	VMMDECL(int) PGMInvalidatePage(PVMCPUCC pVCpu, RTGCPTR GCPtrPage);
353	VMMDECL(int) PGMFlushTLB(PVMCPUCC pVCpu, uint64_t cr3, bool fGlobal);
354	VMMDECL(int) PGMSyncCR3(PVMCPUCC pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal);
355	VMMDECL(int) PGMUpdateCR3(PVMCPUCC pVCpu, uint64_t cr3);
356	VMMDECL(int) PGMChangeMode(PVMCPUCC pVCpu, uint64_t cr0, uint64_t cr4, uint64_t efer);
357	VMM_INT_DECL(int) PGMHCChangeMode(PVMCC pVM, PVMCPUCC pVCpu, PGMMODE enmGuestMode);
358	VMMDECL(void) PGMCr0WpEnabled(PVMCPUCC pVCpu);
359	VMMDECL(PGMMODE) PGMGetGuestMode(PVMCPU pVCpu);
360	VMMDECL(PGMMODE) PGMGetShadowMode(PVMCPU pVCpu);
361	VMMDECL(PGMMODE) PGMGetHostMode(PVM pVM);
362	VMMDECL(const char *) PGMGetModeName(PGMMODE enmMode);
363	VMM_INT_DECL(RTGCPHYS) PGMGetGuestCR3Phys(PVMCPU pVCpu);
364	VMM_INT_DECL(void) PGMNotifyNxeChanged(PVMCPU pVCpu, bool fNxe);
365	VMMDECL(bool) PGMHasDirtyPages(PVM pVM);
366
367	/** PGM physical access handler type registration handle (heap offset, valid
368	* cross contexts without needing fixing up). Callbacks and handler type is
369	* associated with this and it is shared by all handler registrations. */
370	typedef uint32_t PGMPHYSHANDLERTYPE;
371	/** Pointer to a PGM physical handler type registration handle. */
372	typedef PGMPHYSHANDLERTYPE *PPGMPHYSHANDLERTYPE;
373	/** NIL value for PGM physical access handler type handle. */
374	#define NIL_PGMPHYSHANDLERTYPE UINT32_MAX
375	VMMDECL(uint32_t) PGMHandlerPhysicalTypeRelease(PVMCC pVM, PGMPHYSHANDLERTYPE hType);
376	VMMDECL(uint32_t) PGMHandlerPhysicalTypeRetain(PVM pVM, PGMPHYSHANDLERTYPE hType);
377
378	VMMDECL(int) PGMHandlerPhysicalRegister(PVMCC pVM, RTGCPHYS GCPhys, RTGCPHYS GCPhysLast, PGMPHYSHANDLERTYPE hType,
379	RTR3PTR pvUserR3, RTR0PTR pvUserR0, RTRCPTR pvUserRC,
380	R3PTRTYPE(const char *) pszDesc);
381	VMMDECL(int) PGMHandlerPhysicalModify(PVMCC pVM, RTGCPHYS GCPhysCurrent, RTGCPHYS GCPhys, RTGCPHYS GCPhysLast);
382	VMMDECL(int) PGMHandlerPhysicalDeregister(PVMCC pVM, RTGCPHYS GCPhys);
383	VMMDECL(int) PGMHandlerPhysicalChangeUserArgs(PVMCC pVM, RTGCPHYS GCPhys, RTR3PTR pvUserR3, RTR0PTR pvUserR0);
384	VMMDECL(int) PGMHandlerPhysicalSplit(PVMCC pVM, RTGCPHYS GCPhys, RTGCPHYS GCPhysSplit);
385	VMMDECL(int) PGMHandlerPhysicalJoin(PVMCC pVM, RTGCPHYS GCPhys1, RTGCPHYS GCPhys2);
386	VMMDECL(int) PGMHandlerPhysicalPageTempOff(PVMCC pVM, RTGCPHYS GCPhys, RTGCPHYS GCPhysPage);
387	VMMDECL(int) PGMHandlerPhysicalPageAliasMmio2(PVMCC pVM, RTGCPHYS GCPhys, RTGCPHYS GCPhysPage,
388	PPDMDEVINS pDevIns, PGMMMIO2HANDLE hMmio2, RTGCPHYS offMMio2PageRemap);
389	VMMDECL(int) PGMHandlerPhysicalPageAliasHC(PVMCC pVM, RTGCPHYS GCPhys, RTGCPHYS GCPhysPage, RTHCPHYS HCPhysPageRemap);
390	VMMDECL(int) PGMHandlerPhysicalReset(PVMCC pVM, RTGCPHYS GCPhys);
391	VMMDECL(bool) PGMHandlerPhysicalIsRegistered(PVMCC pVM, RTGCPHYS GCPhys);
392
393
394	/**
395	* Page type.
396	*
397	* @remarks This enum has to fit in a 3-bit field (see PGMPAGE::u3Type).
398	* @remarks This is used in the saved state, so changes to it requires bumping
399	* the saved state version.
400	* @todo So, convert to \#defines!
401	*/
402	typedef enum PGMPAGETYPE
403	{
404	/** The usual invalid zero entry. */
405	PGMPAGETYPE_INVALID = 0,
406	/** RAM page. (RWX) */
407	PGMPAGETYPE_RAM,
408	/** MMIO2 page. (RWX) */
409	PGMPAGETYPE_MMIO2,
410	/** MMIO2 page aliased over an MMIO page. (RWX)
411	* See PGMHandlerPhysicalPageAlias(). */
412	PGMPAGETYPE_MMIO2_ALIAS_MMIO,
413	/** Special page aliased over an MMIO page. (RWX)
414	* See PGMHandlerPhysicalPageAliasHC(), but this is generally only used for
415	* VT-x's APIC access page at the moment. Treated as MMIO by everyone except
416	* the shadow paging code. */
417	PGMPAGETYPE_SPECIAL_ALIAS_MMIO,
418	/** Shadowed ROM. (RWX) */
419	PGMPAGETYPE_ROM_SHADOW,
420	/** ROM page. (R-X) */
421	PGMPAGETYPE_ROM,
422	/** MMIO page. (---) */
423	PGMPAGETYPE_MMIO,
424	/** End of valid entries. */
425	PGMPAGETYPE_END
426	} PGMPAGETYPE;
427	AssertCompile(PGMPAGETYPE_END == 8);
428
429	/** @name PGM page type predicates.
430	* @{ */
431	#define PGMPAGETYPE_IS_READABLE(a_enmType) ( (a_enmType) <= PGMPAGETYPE_ROM )
432	#define PGMPAGETYPE_IS_WRITEABLE(a_enmType) ( (a_enmType) <= PGMPAGETYPE_ROM_SHADOW )
433	#define PGMPAGETYPE_IS_RWX(a_enmType) ( (a_enmType) <= PGMPAGETYPE_ROM_SHADOW )
434	#define PGMPAGETYPE_IS_ROX(a_enmType) ( (a_enmType) == PGMPAGETYPE_ROM )
435	#define PGMPAGETYPE_IS_NP(a_enmType) ( (a_enmType) == PGMPAGETYPE_MMIO )
436	/** @} */
437
438
439	VMM_INT_DECL(PGMPAGETYPE) PGMPhysGetPageType(PVMCC pVM, RTGCPHYS GCPhys);
440
441	VMM_INT_DECL(int) PGMPhysGCPhys2HCPhys(PVMCC pVM, RTGCPHYS GCPhys, PRTHCPHYS pHCPhys);
442	VMM_INT_DECL(int) PGMPhysGCPtr2HCPhys(PVMCPUCC pVCpu, RTGCPTR GCPtr, PRTHCPHYS pHCPhys);
443	VMM_INT_DECL(int) PGMPhysGCPhys2CCPtr(PVMCC pVM, RTGCPHYS GCPhys, void **ppv, PPGMPAGEMAPLOCK pLock);
444	VMM_INT_DECL(int) PGMPhysGCPhys2CCPtrReadOnly(PVMCC pVM, RTGCPHYS GCPhys, void const **ppv, PPGMPAGEMAPLOCK pLock);
445	VMM_INT_DECL(int) PGMPhysGCPtr2CCPtr(PVMCPU pVCpu, RTGCPTR GCPtr, void **ppv, PPGMPAGEMAPLOCK pLock);
446	VMM_INT_DECL(int) PGMPhysGCPtr2CCPtrReadOnly(PVMCPUCC pVCpu, RTGCPTR GCPtr, void const **ppv, PPGMPAGEMAPLOCK pLock);
447
448	VMMDECL(bool) PGMPhysIsA20Enabled(PVMCPU pVCpu);
449	VMMDECL(bool) PGMPhysIsGCPhysValid(PVMCC pVM, RTGCPHYS GCPhys);
450	VMMDECL(bool) PGMPhysIsGCPhysNormal(PVMCC pVM, RTGCPHYS GCPhys);
451	VMMDECL(int) PGMPhysGCPtr2GCPhys(PVMCPUCC pVCpu, RTGCPTR GCPtr, PRTGCPHYS pGCPhys);
452	VMMDECL(void) PGMPhysReleasePageMappingLock(PVMCC pVM, PPGMPAGEMAPLOCK pLock);
453	VMMDECL(void) PGMPhysBulkReleasePageMappingLocks(PVMCC pVM, uint32_t cPages, PPGMPAGEMAPLOCK paLock);
454
455	/** @def PGM_PHYS_RW_IS_SUCCESS
456	* Check whether a PGMPhysRead, PGMPhysWrite, PGMPhysReadGCPtr or
457	* PGMPhysWriteGCPtr call completed the given task.
458	*
459	* @returns true if completed, false if not.
460	* @param a_rcStrict The status code.
461	* @sa IOM_SUCCESS
462	*/
463	#ifdef IN_RING3
464	# define PGM_PHYS_RW_IS_SUCCESS(a_rcStrict) \
465	( (a_rcStrict) == VINF_SUCCESS \
466	\|\| (a_rcStrict) == VINF_EM_DBG_STOP \
467	\|\| (a_rcStrict) == VINF_EM_DBG_EVENT \
468	\|\| (a_rcStrict) == VINF_EM_DBG_BREAKPOINT \
469	)
470	#elif defined(IN_RING0)
471	# define PGM_PHYS_RW_IS_SUCCESS(a_rcStrict) \
472	( (a_rcStrict) == VINF_SUCCESS \
473	\|\| (a_rcStrict) == VINF_IOM_R3_MMIO_COMMIT_WRITE \
474	\|\| (a_rcStrict) == VINF_EM_OFF \
475	\|\| (a_rcStrict) == VINF_EM_SUSPEND \
476	\|\| (a_rcStrict) == VINF_EM_RESET \
477	\|\| (a_rcStrict) == VINF_EM_HALT \
478	\|\| (a_rcStrict) == VINF_EM_DBG_STOP \
479	\|\| (a_rcStrict) == VINF_EM_DBG_EVENT \
480	\|\| (a_rcStrict) == VINF_EM_DBG_BREAKPOINT \
481	)
482	#elif defined(IN_RC)
483	# define PGM_PHYS_RW_IS_SUCCESS(a_rcStrict) \
484	( (a_rcStrict) == VINF_SUCCESS \
485	\|\| (a_rcStrict) == VINF_IOM_R3_MMIO_COMMIT_WRITE \
486	\|\| (a_rcStrict) == VINF_EM_OFF \
487	\|\| (a_rcStrict) == VINF_EM_SUSPEND \
488	\|\| (a_rcStrict) == VINF_EM_RESET \
489	\|\| (a_rcStrict) == VINF_EM_HALT \
490	\|\| (a_rcStrict) == VINF_SELM_SYNC_GDT \
491	\|\| (a_rcStrict) == VINF_EM_RAW_EMULATE_INSTR_GDT_FAULT \
492	\|\| (a_rcStrict) == VINF_EM_DBG_STOP \
493	\|\| (a_rcStrict) == VINF_EM_DBG_EVENT \
494	\|\| (a_rcStrict) == VINF_EM_DBG_BREAKPOINT \
495	)
496	#endif
497	/** @def PGM_PHYS_RW_DO_UPDATE_STRICT_RC
498	* Updates the return code with a new result.
499	*
500	* Both status codes must be successes according to PGM_PHYS_RW_IS_SUCCESS.
501	*
502	* @param a_rcStrict The current return code, to be updated.
503	* @param a_rcStrict2 The new return code to merge in.
504	*/
505	#ifdef IN_RING3
506	# define PGM_PHYS_RW_DO_UPDATE_STRICT_RC(a_rcStrict, a_rcStrict2) \
507	do { \
508	Assert(rcStrict == VINF_SUCCESS); \
509	Assert(rcStrict2 == VINF_SUCCESS); \
510	} while (0)
511	#elif defined(IN_RING0)
512	# define PGM_PHYS_RW_DO_UPDATE_STRICT_RC(a_rcStrict, a_rcStrict2) \
513	do { \
514	Assert(PGM_PHYS_RW_IS_SUCCESS(rcStrict)); \
515	Assert(PGM_PHYS_RW_IS_SUCCESS(rcStrict2)); \
516	AssertCompile(VINF_IOM_R3_MMIO_COMMIT_WRITE > VINF_EM_LAST); \
517	if ((a_rcStrict2) == VINF_SUCCESS \|\| (a_rcStrict) == (a_rcStrict2)) \
518	{ /* likely */ } \
519	else if ( (a_rcStrict) == VINF_SUCCESS \
520	\|\| (a_rcStrict) > (a_rcStrict2)) \
521	(a_rcStrict) = (a_rcStrict2); \
522	} while (0)
523	#elif defined(IN_RC)
524	# define PGM_PHYS_RW_DO_UPDATE_STRICT_RC(a_rcStrict, a_rcStrict2) \
525	do { \
526	Assert(PGM_PHYS_RW_IS_SUCCESS(rcStrict)); \
527	Assert(PGM_PHYS_RW_IS_SUCCESS(rcStrict2)); \
528	AssertCompile(VINF_SELM_SYNC_GDT > VINF_EM_LAST); \
529	AssertCompile(VINF_EM_RAW_EMULATE_INSTR_GDT_FAULT > VINF_EM_LAST); \
530	AssertCompile(VINF_EM_RAW_EMULATE_INSTR_GDT_FAULT < VINF_SELM_SYNC_GDT); \
531	AssertCompile(VINF_IOM_R3_MMIO_COMMIT_WRITE > VINF_EM_LAST); \
532	AssertCompile(VINF_IOM_R3_MMIO_COMMIT_WRITE > VINF_SELM_SYNC_GDT); \
533	AssertCompile(VINF_IOM_R3_MMIO_COMMIT_WRITE > VINF_EM_RAW_EMULATE_INSTR_GDT_FAULT); \
534	if ((a_rcStrict2) == VINF_SUCCESS \|\| (a_rcStrict) == (a_rcStrict2)) \
535	{ /* likely */ } \
536	else if ((a_rcStrict) == VINF_SUCCESS) \
537	(a_rcStrict) = (a_rcStrict2); \
538	else if ( ( (a_rcStrict) > (a_rcStrict2) \
539	&& ( (a_rcStrict2) <= VINF_EM_RESET \
540	\|\| (a_rcStrict) != VINF_EM_RAW_EMULATE_INSTR_GDT_FAULT) ) \
541	\|\| ( (a_rcStrict2) == VINF_EM_RAW_EMULATE_INSTR_GDT_FAULT \
542	&& (a_rcStrict) > VINF_EM_RESET) ) \
543	(a_rcStrict) = (a_rcStrict2); \
544	} while (0)
545	#endif
546
547	VMMDECL(VBOXSTRICTRC) PGMPhysRead(PVMCC pVM, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead, PGMACCESSORIGIN enmOrigin);
548	VMMDECL(VBOXSTRICTRC) PGMPhysWrite(PVMCC pVM, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite, PGMACCESSORIGIN enmOrigin);
549	VMMDECL(VBOXSTRICTRC) PGMPhysReadGCPtr(PVMCPUCC pVCpu, void *pvDst, RTGCPTR GCPtrSrc, size_t cb, PGMACCESSORIGIN enmOrigin);
550	VMMDECL(VBOXSTRICTRC) PGMPhysWriteGCPtr(PVMCPUCC pVCpu, RTGCPTR GCPtrDst, const void *pvSrc, size_t cb, PGMACCESSORIGIN enmOrigin);
551
552	VMMDECL(int) PGMPhysSimpleReadGCPhys(PVMCC pVM, void *pvDst, RTGCPHYS GCPhysSrc, size_t cb);
553	VMMDECL(int) PGMPhysSimpleWriteGCPhys(PVMCC pVM, RTGCPHYS GCPhysDst, const void *pvSrc, size_t cb);
554	VMMDECL(int) PGMPhysSimpleReadGCPtr(PVMCPUCC pVCpu, void *pvDst, RTGCPTR GCPtrSrc, size_t cb);
555	VMMDECL(int) PGMPhysSimpleWriteGCPtr(PVMCPUCC pVCpu, RTGCPTR GCPtrDst, const void *pvSrc, size_t cb);
556	VMMDECL(int) PGMPhysSimpleDirtyWriteGCPtr(PVMCPUCC pVCpu, RTGCPTR GCPtrDst, const void *pvSrc, size_t cb);
557	VMMDECL(int) PGMPhysInterpretedRead(PVMCPUCC pVCpu, PCPUMCTXCORE pCtxCore, void *pvDst, RTGCPTR GCPtrSrc, size_t cb);
558	VMMDECL(int) PGMPhysInterpretedReadNoHandlers(PVMCPUCC pVCpu, PCPUMCTXCORE pCtxCore, void *pvDst, RTGCUINTPTR GCPtrSrc, size_t cb, bool fRaiseTrap);
559	VMMDECL(int) PGMPhysInterpretedWriteNoHandlers(PVMCPUCC pVCpu, PCPUMCTXCORE pCtxCore, RTGCPTR GCPtrDst, void const *pvSrc, size_t cb, bool fRaiseTrap);
560
561	VMM_INT_DECL(int) PGMPhysIemGCPhys2Ptr(PVMCC pVM, PVMCPUCC pVCpu, RTGCPHYS GCPhys, bool fWritable, bool fByPassHandlers, void **ppv, PPGMPAGEMAPLOCK pLock);
562	VMM_INT_DECL(int) PGMPhysIemQueryAccess(PVMCC pVM, RTGCPHYS GCPhys, bool fWritable, bool fByPassHandlers);
563	VMM_INT_DECL(int) PGMPhysIemGCPhys2PtrNoLock(PVMCC pVM, PVMCPUCC pVCpu, RTGCPHYS GCPhys, uint64_t const volatile *puTlbPhysRev,
564	#if defined(IN_RC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
565	R3PTRTYPE(uint8_t ) ppb,
566	#else
567	R3R0PTRTYPE(uint8_t ) ppb,
568	#endif
569	uint64_t *pfTlb);
570	/** @name Flags returned by PGMPhysIemGCPhys2PtrNoLock
571	* @{ */
572	#define PGMIEMGCPHYS2PTR_F_NO_WRITE RT_BIT_32(3) /*< Not writable (IEMTLBE_F_PG_NO_WRITE). /
573	#define PGMIEMGCPHYS2PTR_F_NO_READ RT_BIT_32(4) /*< Not readable (IEMTLBE_F_PG_NO_READ). /
574	#define PGMIEMGCPHYS2PTR_F_NO_MAPPINGR3 RT_BIT_32(7) /*< No ring-3 mapping (IEMTLBE_F_NO_MAPPINGR3). /
575	/** @} */
576
577	/** Information returned by PGMPhysNemQueryPageInfo. */
578	typedef struct PGMPHYSNEMPAGEINFO
579	{
580	/** The host physical address of the page, NIL_HCPHYS if invalid page. */
581	RTHCPHYS HCPhys;
582	/** The NEM access mode for the page, NEM_PAGE_PROT_XXX */
583	uint32_t fNemProt : 8;
584	/** The NEM state associated with the PAGE. */
585	uint32_t u2NemState : 2;
586	/** The NEM state associated with the PAGE before pgmPhysPageMakeWritable was called. */
587	uint32_t u2OldNemState : 2;
588	/** Set if the page has handler. */
589	uint32_t fHasHandlers : 1;
590	/** Set if is the zero page backing it. */
591	uint32_t fZeroPage : 1;
592	/** Set if the page has handler. */
593	PGMPAGETYPE enmType;
594	} PGMPHYSNEMPAGEINFO;
595	/** Pointer to page information for NEM. */
596	typedef PGMPHYSNEMPAGEINFO *PPGMPHYSNEMPAGEINFO;
597	/**
598	* Callback for checking that the page is in sync while under the PGM lock.
599	*
600	* NEM passes this callback to PGMPhysNemQueryPageInfo to check that the page is
601	* in-sync between PGM and the native hypervisor API in an atomic fashion.
602	*
603	* @returns VBox status code.
604	* @param pVM The cross context VM structure.
605	* @param pVCpu The cross context per virtual CPU structure. Optional,
606	* see PGMPhysNemQueryPageInfo.
607	* @param GCPhys The guest physical address (not A20 masked).
608	* @param pInfo The page info structure. This function updates the
609	* u2NemState memory and the caller will update the PGMPAGE
610	* copy accordingly.
611	* @param pvUser Callback user argument.
612	*/
613	typedef DECLCALLBACK(int) FNPGMPHYSNEMCHECKPAGE(PVMCC pVM, PVMCPUCC pVCpu, RTGCPHYS GCPhys, PPGMPHYSNEMPAGEINFO pInfo, void *pvUser);
614	/** Pointer to a FNPGMPHYSNEMCHECKPAGE function. */
615	typedef FNPGMPHYSNEMCHECKPAGE *PFNPGMPHYSNEMCHECKPAGE;
616
617	VMM_INT_DECL(int) PGMPhysNemPageInfoChecker(PVMCC pVM, PVMCPUCC pVCpu, RTGCPHYS GCPhys, bool fMakeWritable,
618	PPGMPHYSNEMPAGEINFO pInfo, PFNPGMPHYSNEMCHECKPAGE pfnChecker, void *pvUser);
619
620	/**
621	* Callback for use with PGMPhysNemEnumPagesByState.
622	* @returns VBox status code.
623	* Failure status will stop enumeration immediately and return.
624	* @param pVM The cross context VM structure.
625	* @param pVCpu The cross context per virtual CPU structure. Optional,
626	* see PGMPhysNemEnumPagesByState.
627	* @param GCPhys The guest physical address (not A20 masked).
628	* @param pu2NemState Pointer to variable with the NEM state. This can be
629	* update.
630	* @param pvUser The user argument.
631	*/
632	typedef DECLCALLBACK(int) FNPGMPHYSNEMENUMCALLBACK(PVMCC pVM, PVMCPUCC pVCpu, RTGCPHYS GCPhys, uint8_t pu2NemState, void pvUser);
633	/** Pointer to a FNPGMPHYSNEMENUMCALLBACK function. */
634	typedef FNPGMPHYSNEMENUMCALLBACK *PFNPGMPHYSNEMENUMCALLBACK;
635	VMM_INT_DECL(int) PGMPhysNemEnumPagesByState(PVMCC pVM, PVMCPUCC VCpu, uint8_t uMinState,
636	PFNPGMPHYSNEMENUMCALLBACK pfnCallback, void *pvUser);
637
638
639	#ifdef VBOX_STRICT
640	VMMDECL(unsigned) PGMAssertHandlerAndFlagsInSync(PVM pVM);
641	VMMDECL(unsigned) PGMAssertNoMappingConflicts(PVM pVM);
642	VMMDECL(unsigned) PGMAssertCR3(PVMCC pVM, PVMCPUCC pVCpu, uint64_t cr3, uint64_t cr4);
643	#endif /* VBOX_STRICT */
644
645	#if defined(IN_RC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE)
646	VMMDECL(void) PGMRZDynMapStartAutoSet(PVMCPU pVCpu);
647	VMMDECL(void) PGMRZDynMapReleaseAutoSet(PVMCPU pVCpu);
648	VMMDECL(void) PGMRZDynMapFlushAutoSet(PVMCPU pVCpu);
649	VMMDECL(uint32_t) PGMRZDynMapPushAutoSubset(PVMCPU pVCpu);
650	VMMDECL(void) PGMRZDynMapPopAutoSubset(PVMCPU pVCpu, uint32_t iPrevSubset);
651	#endif
652
653	VMMDECL(int) PGMSetLargePageUsage(PVMCC pVM, bool fUseLargePages);
654
655	/**
656	* Query large page usage state
657	*
658	* @returns 0 - disabled, 1 - enabled
659	* @param pVM The cross context VM structure.
660	*/
661	#define PGMIsUsingLargePages(pVM) ((pVM)->fUseLargePages)
662
663
664	#ifdef IN_RC
665	/** @defgroup grp_pgm_gc The PGM Guest Context API
666	* @{
667	*/
668	VMMRCDECL(int) PGMRCDynMapInit(PVM pVM);
669	/** @} */
670	#endif /* IN_RC */
671
672
673	#ifdef IN_RING0
674	/** @defgroup grp_pgm_r0 The PGM Host Context Ring-0 API
675	* @{
676	*/
677	VMMR0_INT_DECL(int) PGMR0InitPerVMData(PGVM pGVM);
678	VMMR0_INT_DECL(int) PGMR0InitVM(PGVM pGVM);
679	VMMR0_INT_DECL(void) PGMR0CleanupVM(PGVM pGVM);
680	VMMR0_INT_DECL(int) PGMR0PhysAllocateHandyPages(PGVM pGVM, VMCPUID idCpu);
681	VMMR0_INT_DECL(int) PGMR0PhysFlushHandyPages(PGVM pGVM, VMCPUID idCpu);
682	VMMR0_INT_DECL(int) PGMR0PhysAllocateLargeHandyPage(PGVM pGVM, VMCPUID idCpu);
683	VMMR0_INT_DECL(int) PGMR0PhysMMIO2MapKernel(PGVM pGVM, PPDMDEVINS pDevIns, PGMMMIO2HANDLE hMmio2,
684	size_t offSub, size_t cbSub, void **ppvMapping);
685	VMMR0_INT_DECL(int) PGMR0PhysSetupIoMmu(PGVM pGVM);
686	VMMR0DECL(int) PGMR0SharedModuleCheck(PVMCC pVM, PGVM pGVM, VMCPUID idCpu, PGMMSHAREDMODULE pModule,
687	PCRTGCPTR64 paRegionsGCPtrs);
688	VMMR0DECL(int) PGMR0Trap0eHandlerNestedPaging(PGVM pGVM, PGVMCPU pGVCpu, PGMMODE enmShwPagingMode, RTGCUINT uErr,
689	PCPUMCTXCORE pRegFrame, RTGCPHYS pvFault);
690	VMMR0DECL(VBOXSTRICTRC) PGMR0Trap0eHandlerNPMisconfig(PGVM pGVM, PGVMCPU pGVCpu, PGMMODE enmShwPagingMode,
691	PCPUMCTXCORE pRegFrame, RTGCPHYS GCPhysFault, uint32_t uErr);
692	VMMR0_INT_DECL(int) PGMR0PoolGrow(PGVM pGVM);
693
694	# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
695	VMMR0DECL(int) PGMR0DynMapInit(void);
696	VMMR0DECL(void) PGMR0DynMapTerm(void);
697	VMMR0DECL(int) PGMR0DynMapInitVM(PVMCC pVM);
698	VMMR0DECL(void) PGMR0DynMapTermVM(PVMCC pVM);
699	VMMR0DECL(int) PGMR0DynMapAssertIntegrity(void);
700	VMMR0DECL(bool) PGMR0DynMapStartOrMigrateAutoSet(PVMCPUCC pVCpu);
701	VMMR0DECL(void) PGMR0DynMapMigrateAutoSet(PVMCPUCC pVCpu);
702	# endif
703	/** @} */
704	#endif /* IN_RING0 */
705
706
707
708	#ifdef IN_RING3
709	/** @defgroup grp_pgm_r3 The PGM Host Context Ring-3 API
710	* @{
711	*/
712	VMMR3DECL(int) PGMR3Init(PVM pVM);
713	VMMR3DECL(int) PGMR3InitDynMap(PVM pVM);
714	VMMR3DECL(int) PGMR3InitFinalize(PVM pVM);
715	VMMR3_INT_DECL(int) PGMR3InitCompleted(PVM pVM, VMINITCOMPLETED enmWhat);
716	VMMR3DECL(void) PGMR3Relocate(PVM pVM, RTGCINTPTR offDelta);
717	VMMR3DECL(void) PGMR3ResetCpu(PVM pVM, PVMCPU pVCpu);
718	VMMR3_INT_DECL(void) PGMR3Reset(PVM pVM);
719	VMMR3_INT_DECL(void) PGMR3ResetNoMorePhysWritesFlag(PVM pVM);
720	VMMR3_INT_DECL(void) PGMR3MemSetup(PVM pVM, bool fReset);
721	VMMR3DECL(int) PGMR3Term(PVM pVM);
722	VMMR3DECL(int) PGMR3LockCall(PVM pVM);
723
724	VMMR3DECL(int) PGMR3PhysRegisterRam(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, const char *pszDesc);
725	VMMR3DECL(int) PGMR3PhysChangeMemBalloon(PVM pVM, bool fInflate, unsigned cPages, RTGCPHYS *paPhysPage);
726	VMMR3DECL(int) PGMR3PhysWriteProtectRAM(PVM pVM);
727	VMMR3DECL(uint32_t) PGMR3PhysGetRamRangeCount(PVM pVM);
728	VMMR3DECL(int) PGMR3PhysGetRange(PVM pVM, uint32_t iRange, PRTGCPHYS pGCPhysStart, PRTGCPHYS pGCPhysLast,
729	const char *ppszDesc, bool pfIsMmio);
730	VMMR3DECL(int) PGMR3QueryMemoryStats(PUVM pUVM, uint64_t pcbTotalMem, uint64_t pcbPrivateMem, uint64_t pcbSharedMem, uint64_t pcbZeroMem);
731	VMMR3DECL(int) PGMR3QueryGlobalMemoryStats(PUVM pUVM, uint64_t pcbAllocMem, uint64_t pcbFreeMem, uint64_t pcbBallonedMem, uint64_t pcbSharedMem);
732
733	VMMR3DECL(int) PGMR3PhysMMIORegister(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, PGMPHYSHANDLERTYPE hType,
734	RTR3PTR pvUserR3, RTR0PTR pvUserR0, RTRCPTR pvUserRC, const char *pszDesc);
735	VMMR3DECL(int) PGMR3PhysMMIODeregister(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb);
736	VMMR3_INT_DECL(int) PGMR3PhysMmio2Register(PVM pVM, PPDMDEVINS pDevIns, uint32_t iSubDev, uint32_t iRegion, RTGCPHYS cb,
737	uint32_t fFlags, const char pszDesc, void ppv, PGMMMIO2HANDLE phRegion);
738	VMMR3_INT_DECL(int) PGMR3PhysMmio2Deregister(PVM pVM, PPDMDEVINS pDevIns, PGMMMIO2HANDLE hMmio2);
739	VMMR3_INT_DECL(int) PGMR3PhysMmio2Map(PVM pVM, PPDMDEVINS pDevIns, PGMMMIO2HANDLE hMmio2, RTGCPHYS GCPhys);
740	VMMR3_INT_DECL(int) PGMR3PhysMmio2Unmap(PVM pVM, PPDMDEVINS pDevIns, PGMMMIO2HANDLE hMmio2, RTGCPHYS GCPhys);
741	VMMR3_INT_DECL(int) PGMR3PhysMmio2Reduce(PVM pVM, PPDMDEVINS pDevIns, PGMMMIO2HANDLE hMmio2, RTGCPHYS cbRegion);
742	VMMR3_INT_DECL(int) PGMR3PhysMmio2ValidateHandle(PVM pVM, PPDMDEVINS pDevIns, PGMMMIO2HANDLE hMmio2);
743	VMMR3_INT_DECL(RTGCPHYS) PGMR3PhysMmio2GetMappingAddress(PVM pVM, PPDMDEVINS pDevIns, PGMMMIO2HANDLE hMmio2);
744	VMMR3_INT_DECL(int) PGMR3PhysMmio2ChangeRegionNo(PVM pVM, PPDMDEVINS pDevIns, PGMMMIO2HANDLE hMmio2, uint32_t iNewRegion);
745	VMMR3_INT_DECL(int) PGMR3PhysMMIO2GetHCPhys(PVM pVM, PPDMDEVINS pDevIns, uint32_t iSubDev, uint32_t iRegion, RTGCPHYS off, PRTHCPHYS pHCPhys);
746
747
748	/** @name PGMR3PhysRegisterRom flags.
749	* @{ */
750	/** Inidicates that ROM shadowing should be enabled. */
751	#define PGMPHYS_ROM_FLAGS_SHADOWED RT_BIT_32(0)
752	/** Indicates that what pvBinary points to won't go away
753	* and can be used for strictness checks. */
754	#define PGMPHYS_ROM_FLAGS_PERMANENT_BINARY RT_BIT_32(1)
755	/** Indicates that the ROM is allowed to be missing from saved state.
756	* @note This is a hack for EFI, see @bugref{6940} */
757	#define PGMPHYS_ROM_FLAGS_MAYBE_MISSING_FROM_STATE RT_BIT_32(2)
758	/** Valid flags. */
759	#define PGMPHYS_ROM_FLAGS_VALID_MASK UINT32_C(0x00000007)
760	/** @} */
761
762	VMMR3DECL(int) PGMR3PhysRomRegister(PVM pVM, PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTGCPHYS cb,
763	const void pvBinary, uint32_t cbBinary, uint32_t fFlags, const char pszDesc);
764	VMMR3DECL(int) PGMR3PhysRomProtect(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, PGMROMPROT enmProt);
765	VMMR3DECL(int) PGMR3PhysRegister(PVM pVM, void pvRam, RTGCPHYS GCPhys, size_t cb, unsigned fFlags, const SUPPAGE paPages, const char *pszDesc);
766	VMMDECL(void) PGMR3PhysSetA20(PVMCPU pVCpu, bool fEnable);
767	#ifndef PGM_WITHOUT_MAPPINGS
768	/** @name PGMR3MapPT flags.
769	* @{ */
770	/** The mapping may be unmapped later. The default is permanent mappings. */
771	# define PGMR3MAPPT_FLAGS_UNMAPPABLE RT_BIT(0)
772	/** @} */
773	VMMR3DECL(int) PGMR3MapPT(PVM pVM, RTGCPTR GCPtr, uint32_t cb, uint32_t fFlags, PFNPGMRELOCATE pfnRelocate, void pvUser, const char pszDesc);
774	VMMR3DECL(int) PGMR3UnmapPT(PVM pVM, RTGCPTR GCPtr);
775	VMMR3DECL(int) PGMR3FinalizeMappings(PVM pVM);
776	VMMR3DECL(bool) PGMR3MappingsNeedReFixing(PVM pVM);
777	# if defined(VBOX_WITH_RAW_MODE) \|\| HC_ARCH_BITS == 32 /* (latter for 64-bit guests on 32-bit hosts) */
778	VMMR3DECL(int) PGMR3MapIntermediate(PVM pVM, RTUINTPTR Addr, RTHCPHYS HCPhys, unsigned cbPages);
779	# endif
780	VMMR3DECL(int) PGMR3MapRead(PVM pVM, void *pvDst, RTGCPTR GCPtrSrc, size_t cb);
781	#endif /* !PGM_WITHOUT_MAPPINGS */
782	VMMR3DECL(int) PGMR3MappingsSize(PVM pVM, uint32_t *pcb);
783	VMMR3DECL(int) PGMR3MappingsFix(PVM pVM, RTGCPTR GCPtrBase, uint32_t cb);
784	VMMR3DECL(int) PGMR3MappingsUnfix(PVM pVM);
785
786	VMMR3_INT_DECL(int) PGMR3HandlerPhysicalTypeRegisterEx(PVM pVM, PGMPHYSHANDLERKIND enmKind,
787	PFNPGMPHYSHANDLER pfnHandlerR3,
788	R0PTRTYPE(PFNPGMPHYSHANDLER) pfnHandlerR0,
789	R0PTRTYPE(PFNPGMRZPHYSPFHANDLER) pfnPfHandlerR0,
790	const char *pszDesc, PPGMPHYSHANDLERTYPE phType);
791	VMMR3DECL(int) PGMR3HandlerPhysicalTypeRegister(PVM pVM, PGMPHYSHANDLERKIND enmKind,
792	R3PTRTYPE(PFNPGMPHYSHANDLER) pfnHandlerR3,
793	const char pszModR0, const char pszHandlerR0, const char *pszPfHandlerR0,
794	const char pszModRC, const char pszHandlerRC, const char *pszPfHandlerRC,
795	const char *pszDesc,
796	PPGMPHYSHANDLERTYPE phType);
797	VMMR3_INT_DECL(int) PGMR3PoolGrow(PVM pVM, PVMCPU pVCpu);
798
799	VMMR3DECL(int) PGMR3PhysTlbGCPhys2Ptr(PVM pVM, RTGCPHYS GCPhys, bool fWritable, void **ppv);
800	VMMR3DECL(uint8_t) PGMR3PhysReadU8(PVM pVM, RTGCPHYS GCPhys, PGMACCESSORIGIN enmOrigin);
801	VMMR3DECL(uint16_t) PGMR3PhysReadU16(PVM pVM, RTGCPHYS GCPhys, PGMACCESSORIGIN enmOrigin);
802	VMMR3DECL(uint32_t) PGMR3PhysReadU32(PVM pVM, RTGCPHYS GCPhys, PGMACCESSORIGIN enmOrigin);
803	VMMR3DECL(uint64_t) PGMR3PhysReadU64(PVM pVM, RTGCPHYS GCPhys, PGMACCESSORIGIN enmOrigin);
804	VMMR3DECL(void) PGMR3PhysWriteU8(PVM pVM, RTGCPHYS GCPhys, uint8_t Value, PGMACCESSORIGIN enmOrigin);
805	VMMR3DECL(void) PGMR3PhysWriteU16(PVM pVM, RTGCPHYS GCPhys, uint16_t Value, PGMACCESSORIGIN enmOrigin);
806	VMMR3DECL(void) PGMR3PhysWriteU32(PVM pVM, RTGCPHYS GCPhys, uint32_t Value, PGMACCESSORIGIN enmOrigin);
807	VMMR3DECL(void) PGMR3PhysWriteU64(PVM pVM, RTGCPHYS GCPhys, uint64_t Value, PGMACCESSORIGIN enmOrigin);
808	VMMR3DECL(int) PGMR3PhysReadExternal(PVM pVM, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead, PGMACCESSORIGIN enmOrigin);
809	VMMR3DECL(int) PGMR3PhysWriteExternal(PVM pVM, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite, PGMACCESSORIGIN enmOrigin);
810	VMMR3DECL(int) PGMR3PhysGCPhys2CCPtrExternal(PVM pVM, RTGCPHYS GCPhys, void **ppv, PPGMPAGEMAPLOCK pLock);
811	VMMR3DECL(int) PGMR3PhysGCPhys2CCPtrReadOnlyExternal(PVM pVM, RTGCPHYS GCPhys, void const **ppv, PPGMPAGEMAPLOCK pLock);
812	VMMR3DECL(int) PGMR3PhysBulkGCPhys2CCPtrExternal(PVM pVM, uint32_t cPages, PCRTGCPHYS paGCPhysPages,
813	void **papvPages, PPGMPAGEMAPLOCK paLocks);
814	VMMR3DECL(int) PGMR3PhysBulkGCPhys2CCPtrReadOnlyExternal(PVM pVM, uint32_t cPages, PCRTGCPHYS paGCPhysPages,
815	void const **papvPages, PPGMPAGEMAPLOCK paLocks);
816	VMMR3DECL(int) PGMR3PhysChunkMap(PVM pVM, uint32_t idChunk);
817	VMMR3DECL(void) PGMR3PhysChunkInvalidateTLB(PVM pVM);
818	VMMR3DECL(int) PGMR3PhysAllocateHandyPages(PVM pVM);
819	VMMR3DECL(int) PGMR3PhysAllocateLargeHandyPage(PVM pVM, RTGCPHYS GCPhys);
820
821	VMMR3DECL(int) PGMR3CheckIntegrity(PVM pVM);
822
823	VMMR3DECL(int) PGMR3DbgR3Ptr2GCPhys(PUVM pUVM, RTR3PTR R3Ptr, PRTGCPHYS pGCPhys);
824	VMMR3DECL(int) PGMR3DbgR3Ptr2HCPhys(PUVM pUVM, RTR3PTR R3Ptr, PRTHCPHYS pHCPhys);
825	VMMR3DECL(int) PGMR3DbgHCPhys2GCPhys(PUVM pUVM, RTHCPHYS HCPhys, PRTGCPHYS pGCPhys);
826	VMMR3_INT_DECL(int) PGMR3DbgReadGCPhys(PVM pVM, void pvDst, RTGCPHYS GCPhysSrc, size_t cb, uint32_t fFlags, size_t pcbRead);
827	VMMR3_INT_DECL(int) PGMR3DbgWriteGCPhys(PVM pVM, RTGCPHYS GCPhysDst, const void pvSrc, size_t cb, uint32_t fFlags, size_t pcbWritten);
828	VMMR3_INT_DECL(int) PGMR3DbgReadGCPtr(PVM pVM, void pvDst, RTGCPTR GCPtrSrc, size_t cb, uint32_t fFlags, size_t pcbRead);
829	VMMR3_INT_DECL(int) PGMR3DbgWriteGCPtr(PVM pVM, RTGCPTR GCPtrDst, void const pvSrc, size_t cb, uint32_t fFlags, size_t pcbWritten);
830	VMMR3_INT_DECL(int) PGMR3DbgScanPhysical(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cbRange, RTGCPHYS GCPhysAlign, const uint8_t *pabNeedle, size_t cbNeedle, PRTGCPHYS pGCPhysHit);
831	VMMR3_INT_DECL(int) PGMR3DbgScanVirtual(PVM pVM, PVMCPU pVCpu, RTGCPTR GCPtr, RTGCPTR cbRange, RTGCPTR GCPtrAlign, const uint8_t *pabNeedle, size_t cbNeedle, PRTGCUINTPTR pGCPhysHit);
832	VMMR3_INT_DECL(int) PGMR3DumpHierarchyShw(PVM pVM, uint64_t cr3, uint32_t fFlags, uint64_t u64FirstAddr, uint64_t u64LastAddr, uint32_t cMaxDepth, PCDBGFINFOHLP pHlp);
833	VMMR3_INT_DECL(int) PGMR3DumpHierarchyGst(PVM pVM, uint64_t cr3, uint32_t fFlags, RTGCPTR FirstAddr, RTGCPTR LastAddr, uint32_t cMaxDepth, PCDBGFINFOHLP pHlp);
834
835
836	/** @name Page sharing
837	* @{ */
838	VMMR3DECL(int) PGMR3SharedModuleRegister(PVM pVM, VBOXOSFAMILY enmGuestOS, char pszModuleName, char pszVersion,
839	RTGCPTR GCBaseAddr, uint32_t cbModule,
840	uint32_t cRegions, VMMDEVSHAREDREGIONDESC const *paRegions);
841	VMMR3DECL(int) PGMR3SharedModuleUnregister(PVM pVM, char pszModuleName, char pszVersion,
842	RTGCPTR GCBaseAddr, uint32_t cbModule);
843	VMMR3DECL(int) PGMR3SharedModuleCheckAll(PVM pVM);
844	VMMR3DECL(int) PGMR3SharedModuleGetPageState(PVM pVM, RTGCPTR GCPtrPage, bool pfShared, uint64_t pfPageFlags);
845	/** @} */
846
847	/** @} */
848	#endif /* IN_RING3 */
849
850	RT_C_DECLS_END
851
852	/** @} */
853	#endif /* !VBOX_INCLUDED_vmm_pgm_h */
854

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source: vbox/trunk/include/VBox/vmm/pgm.h@ 82555

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