pgm.h@ 91246

Last change on this file since 91246 was 91246, checked in by vboxsync, 3 years ago
VMM/PGM: Some cleanups around large page allocation... bugref:10093
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1	/** @file
2	* PGM - Page Monitor / Monitor.
3	*/
4
5	/*
6	* Copyright (C) 2006-2020 Oracle Corporation
7	*
8	* This file is part of VirtualBox Open Source Edition (OSE), as
9	* available from http://www.virtualbox.org. This file is free software;
10	* you can redistribute it and/or modify it under the terms of the GNU
11	* General Public License (GPL) as published by the Free Software
12	* Foundation, in version 2 as it comes in the "COPYING" file of the
13	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15	*
16	* The contents of this file may alternatively be used under the terms
17	* of the Common Development and Distribution License Version 1.0
18	* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19	* VirtualBox OSE distribution, in which case the provisions of the
20	* CDDL are applicable instead of those of the GPL.
21	*
22	* You may elect to license modified versions of this file under the
23	* terms and conditions of either the GPL or the CDDL or both.
24	*/
25
26	#ifndef VBOX_INCLUDED_vmm_pgm_h
27	#define VBOX_INCLUDED_vmm_pgm_h
28	#ifndef RT_WITHOUT_PRAGMA_ONCE
29	# pragma once
30	#endif
31
32	#include <VBox/types.h>
33	#include <VBox/sup.h>
34	#include <VBox/vmm/vmapi.h>
35	#include <VBox/vmm/gmm.h> /* for PGMMREGISTERSHAREDMODULEREQ */
36	#include <iprt/x86.h>
37	#include <VBox/param.h>
38
39	RT_C_DECLS_BEGIN
40
41	/** @defgroup grp_pgm The Page Monitor / Manager API
42	* @ingroup grp_vmm
43	* @{
44	*/
45
46	/**
47	* FNPGMRELOCATE callback mode.
48	*/
49	typedef enum PGMRELOCATECALL
50	{
51	/** The callback is for checking if the suggested address is suitable. */
52	PGMRELOCATECALL_SUGGEST = 1,
53	/** The callback is for executing the relocation. */
54	PGMRELOCATECALL_RELOCATE
55	} PGMRELOCATECALL;
56
57
58	/** No guest context mappings (might be removed entirely later, if we don't
59	* need it again (see new raw-mode ideas)).
60	* @internal */
61	#define PGM_WITHOUT_MAPPINGS
62
63
64	/**
65	* Callback function which will be called when PGM is trying to find
66	* a new location for the mapping.
67	*
68	* The callback is called in two modes, 1) the check mode and 2) the relocate mode.
69	* In 1) the callback should say if it objects to a suggested new location. If it
70	* accepts the new location, it is called again for doing it's relocation.
71	*
72	*
73	* @returns true if the location is ok.
74	* @returns false if another location should be found.
75	* @param pVM The cross context VM structure.
76	* @param GCPtrOld The old virtual address.
77	* @param GCPtrNew The new virtual address.
78	* @param enmMode Used to indicate the callback mode.
79	* @param pvUser User argument.
80	* @remark The return value is no a failure indicator, it's an acceptance
81	* indicator. Relocation can not fail!
82	*/
83	typedef DECLCALLBACKTYPE(bool, FNPGMRELOCATE,(PVM pVM, RTGCPTR GCPtrOld, RTGCPTR GCPtrNew, PGMRELOCATECALL enmMode, void *pvUser));
84	/** Pointer to a relocation callback function. */
85	typedef FNPGMRELOCATE *PFNPGMRELOCATE;
86
87
88	/**
89	* Memory access origin.
90	*/
91	typedef enum PGMACCESSORIGIN
92	{
93	/** Invalid zero value. */
94	PGMACCESSORIGIN_INVALID = 0,
95	/** IEM is access memory. */
96	PGMACCESSORIGIN_IEM,
97	/** HM is access memory. */
98	PGMACCESSORIGIN_HM,
99	/** Some device is access memory. */
100	PGMACCESSORIGIN_DEVICE,
101	/** Someone debugging is access memory. */
102	PGMACCESSORIGIN_DEBUGGER,
103	/** SELM is access memory. */
104	PGMACCESSORIGIN_SELM,
105	/** FTM is access memory. */
106	PGMACCESSORIGIN_FTM,
107	/** REM is access memory. */
108	PGMACCESSORIGIN_REM,
109	/** IOM is access memory. */
110	PGMACCESSORIGIN_IOM,
111	/** End of valid values. */
112	PGMACCESSORIGIN_END,
113	/** Type size hack. */
114	PGMACCESSORIGIN_32BIT_HACK = 0x7fffffff
115	} PGMACCESSORIGIN;
116
117
118	/**
119	* Physical page access handler kind.
120	*/
121	typedef enum PGMPHYSHANDLERKIND
122	{
123	/** MMIO range. Pages are not present, all access is done in interpreter or recompiler. */
124	PGMPHYSHANDLERKIND_MMIO = 1,
125	/** Handler all write access to a physical page range. */
126	PGMPHYSHANDLERKIND_WRITE,
127	/** Handler all access to a physical page range. */
128	PGMPHYSHANDLERKIND_ALL
129
130	} PGMPHYSHANDLERKIND;
131
132	/**
133	* Guest Access type
134	*/
135	typedef enum PGMACCESSTYPE
136	{
137	/** Read access. */
138	PGMACCESSTYPE_READ = 1,
139	/** Write access. */
140	PGMACCESSTYPE_WRITE
141	} PGMACCESSTYPE;
142
143
144	/** @def PGM_ALL_CB_DECL
145	* Macro for declaring a handler callback for all contexts. The handler
146	* callback is static in ring-3, and exported in RC and R0.
147	* @sa PGM_ALL_CB2_DECL.
148	*/
149	#if defined(IN_RC) \|\| defined(IN_RING0)
150	# ifdef __cplusplus
151	# define PGM_ALL_CB_DECL(type) extern "C" DECLCALLBACK(DECLEXPORT(type))
152	# else
153	# define PGM_ALL_CB_DECL(type) DECLCALLBACK(DECLEXPORT(type))
154	# endif
155	#else
156	# define PGM_ALL_CB_DECL(type) static DECLCALLBACK(type)
157	#endif
158
159	/** @def PGM_ALL_CB2_DECL
160	* Macro for declaring a handler callback for all contexts. The handler
161	* callback is hidden in ring-3, and exported in RC and R0.
162	* @sa PGM_ALL_CB2_DECL.
163	*/
164	#if defined(IN_RC) \|\| defined(IN_RING0)
165	# ifdef __cplusplus
166	# define PGM_ALL_CB2_DECL(type) extern "C" DECLCALLBACK(DECLEXPORT(type))
167	# else
168	# define PGM_ALL_CB2_DECL(type) DECLCALLBACK(DECLEXPORT(type))
169	# endif
170	#else
171	# define PGM_ALL_CB2_DECL(type) DECL_HIDDEN_CALLBACK(type)
172	#endif
173
174	/** @def PGM_ALL_CB2_PROTO
175	* Macro for declaring a handler callback for all contexts. The handler
176	* callback is hidden in ring-3, and exported in RC and R0.
177	* @param fnType The callback function type.
178	* @sa PGM_ALL_CB2_DECL.
179	*/
180	#if defined(IN_RC) \|\| defined(IN_RING0)
181	# ifdef __cplusplus
182	# define PGM_ALL_CB2_PROTO(fnType) extern "C" DECLEXPORT(fnType)
183	# else
184	# define PGM_ALL_CB2_PROTO(fnType) DECLEXPORT(fnType)
185	# endif
186	#else
187	# define PGM_ALL_CB2_PROTO(fnType) DECLHIDDEN(fnType)
188	#endif
189
190
191	/**
192	* \#PF Handler callback for physical access handler ranges in RC and R0.
193	*
194	* @returns Strict VBox status code (appropriate for ring-0 and raw-mode).
195	* @param pVM The cross context VM structure.
196	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
197	* @param uErrorCode CPU Error code.
198	* @param pRegFrame Trap register frame.
199	* NULL on DMA and other non CPU access.
200	* @param pvFault The fault address (cr2).
201	* @param GCPhysFault The GC physical address corresponding to pvFault.
202	* @param pvUser User argument.
203	* @thread EMT(pVCpu)
204	*/
205	typedef DECLCALLBACKTYPE(VBOXSTRICTRC, FNPGMRZPHYSPFHANDLER,(PVMCC pVM, PVMCPUCC pVCpu, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame,
206	RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser));
207	/** Pointer to PGM access callback. */
208	typedef FNPGMRZPHYSPFHANDLER *PFNPGMRZPHYSPFHANDLER;
209
210
211	/**
212	* Access handler callback for physical access handler ranges.
213	*
214	* The handler can not raise any faults, it's mainly for monitoring write access
215	* to certain pages (like MMIO).
216	*
217	* @returns Strict VBox status code in ring-0 and raw-mode context, in ring-3
218	* the only supported informational status code is
219	* VINF_PGM_HANDLER_DO_DEFAULT.
220	* @retval VINF_SUCCESS if the handler have carried out the operation.
221	* @retval VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the
222	* access operation.
223	* @retval VINF_EM_XXX in ring-0 and raw-mode context.
224	*
225	* @param pVM The cross context VM structure.
226	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
227	* @param GCPhys The physical address the guest is writing to.
228	* @param pvPhys The HC mapping of that address.
229	* @param pvBuf What the guest is reading/writing.
230	* @param cbBuf How much it's reading/writing.
231	* @param enmAccessType The access type.
232	* @param enmOrigin The origin of this call.
233	* @param pvUser User argument.
234	* @thread EMT(pVCpu)
235	*/
236	typedef DECLCALLBACKTYPE(VBOXSTRICTRC, FNPGMPHYSHANDLER,(PVMCC pVM, PVMCPUCC pVCpu, RTGCPHYS GCPhys, void *pvPhys,
237	void *pvBuf, size_t cbBuf, PGMACCESSTYPE enmAccessType,
238	PGMACCESSORIGIN enmOrigin, void *pvUser));
239	/** Pointer to PGM access callback. */
240	typedef FNPGMPHYSHANDLER *PFNPGMPHYSHANDLER;
241
242
243	/**
244	* Paging mode.
245	*
246	* @note Part of saved state. Change with extreme care.
247	*/
248	typedef enum PGMMODE
249	{
250	/** The usual invalid value. */
251	PGMMODE_INVALID = 0,
252	/** Real mode. */
253	PGMMODE_REAL,
254	/** Protected mode, no paging. */
255	PGMMODE_PROTECTED,
256	/** 32-bit paging. */
257	PGMMODE_32_BIT,
258	/** PAE paging. */
259	PGMMODE_PAE,
260	/** PAE paging with NX enabled. */
261	PGMMODE_PAE_NX,
262	/** 64-bit AMD paging (long mode). */
263	PGMMODE_AMD64,
264	/** 64-bit AMD paging (long mode) with NX enabled. */
265	PGMMODE_AMD64_NX,
266	/** 32-bit nested paging mode (shadow only; guest physical to host physical). */
267	PGMMODE_NESTED_32BIT,
268	/** PAE nested paging mode (shadow only; guest physical to host physical). */
269	PGMMODE_NESTED_PAE,
270	/** AMD64 nested paging mode (shadow only; guest physical to host physical). */
271	PGMMODE_NESTED_AMD64,
272	/** Extended paging (Intel) mode. */
273	PGMMODE_EPT,
274	/** Special mode used by NEM to indicate no shadow paging necessary. */
275	PGMMODE_NONE,
276	/** The max number of modes */
277	PGMMODE_MAX,
278	/** 32bit hackishness. */
279	PGMMODE_32BIT_HACK = 0x7fffffff
280	} PGMMODE;
281
282	/** Macro for checking if the guest is using paging.
283	* @param enmMode PGMMODE_*.
284	* @remark ASSUMES certain order of the PGMMODE_* values.
285	*/
286	#define PGMMODE_WITH_PAGING(enmMode) ((enmMode) >= PGMMODE_32_BIT)
287
288	/** Macro for checking if it's one of the long mode modes.
289	* @param enmMode PGMMODE_*.
290	*/
291	#define PGMMODE_IS_LONG_MODE(enmMode) ((enmMode) == PGMMODE_AMD64_NX \|\| (enmMode) == PGMMODE_AMD64)
292
293	/** Macro for checking if it's one of the AMD64 nested modes.
294	* @param enmMode PGMMODE_*.
295	*/
296	#define PGMMODE_IS_NESTED(enmMode) ( (enmMode) == PGMMODE_NESTED_32BIT \
297	\|\| (enmMode) == PGMMODE_NESTED_PAE \
298	\|\| (enmMode) == PGMMODE_NESTED_AMD64)
299
300	/**
301	* Is the ROM mapped (true) or is the shadow RAM mapped (false).
302	*
303	* @returns boolean.
304	* @param enmProt The PGMROMPROT value, must be valid.
305	*/
306	#define PGMROMPROT_IS_ROM(enmProt) \
307	( (enmProt) == PGMROMPROT_READ_ROM_WRITE_IGNORE \
308	\|\| (enmProt) == PGMROMPROT_READ_ROM_WRITE_RAM )
309
310
311	VMMDECL(bool) PGMIsLockOwner(PVMCC pVM);
312
313	VMMDECL(int) PGMRegisterStringFormatTypes(void);
314	VMMDECL(void) PGMDeregisterStringFormatTypes(void);
315	VMMDECL(RTHCPHYS) PGMGetHyperCR3(PVMCPU pVCpu);
316	VMMDECL(int) PGMTrap0eHandler(PVMCPUCC pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault);
317	VMMDECL(int) PGMPrefetchPage(PVMCPUCC pVCpu, RTGCPTR GCPtrPage);
318	VMMDECL(int) PGMVerifyAccess(PVMCPUCC pVCpu, RTGCPTR Addr, uint32_t cbSize, uint32_t fAccess);
319	VMMDECL(int) PGMIsValidAccess(PVMCPUCC pVCpu, RTGCPTR Addr, uint32_t cbSize, uint32_t fAccess);
320	VMMDECL(VBOXSTRICTRC) PGMInterpretInstruction(PVMCC pVM, PVMCPUCC pVCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault);
321	#ifndef PGM_WITHOUT_MAPPINGS
322	VMMDECL(int) PGMMap(PVM pVM, RTGCPTR GCPtr, RTHCPHYS HCPhys, uint32_t cbPages, unsigned fFlags);
323	VMMDECL(int) PGMMapGetPage(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys);
324	VMMDECL(int) PGMMapSetPage(PVM pVM, RTGCPTR GCPtr, uint64_t cb, uint64_t fFlags);
325	VMMDECL(int) PGMMapModifyPage(PVM pVM, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask);
326	# ifndef IN_RING0
327	VMMDECL(bool) PGMMapHasConflicts(PVM pVM);
328	# endif
329	# ifdef VBOX_STRICT
330	VMMDECL(void) PGMMapCheck(PVM pVM);
331	# endif
332	#endif /* !PGM_WITHOUT_MAPPINGS */
333	VMMDECL(int) PGMShwGetPage(PVMCPUCC pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys);
334	VMMDECL(int) PGMShwMakePageReadonly(PVMCPUCC pVCpu, RTGCPTR GCPtr, uint32_t fFlags);
335	VMMDECL(int) PGMShwMakePageWritable(PVMCPUCC pVCpu, RTGCPTR GCPtr, uint32_t fFlags);
336	VMMDECL(int) PGMShwMakePageNotPresent(PVMCPUCC pVCpu, RTGCPTR GCPtr, uint32_t fFlags);
337	/** @name Flags for PGMShwMakePageReadonly, PGMShwMakePageWritable and
338	* PGMShwMakePageNotPresent
339	* @{ */
340	/** The call is from an access handler for dealing with the a faulting write
341	* operation. The virtual address is within the same page. */
342	#define PGM_MK_PG_IS_WRITE_FAULT RT_BIT(0)
343	/** The page is an MMIO2. */
344	#define PGM_MK_PG_IS_MMIO2 RT_BIT(1)
345	/** @}*/
346	VMMDECL(int) PGMGstGetPage(PVMCPUCC pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys);
347	VMMDECL(bool) PGMGstIsPagePresent(PVMCPUCC pVCpu, RTGCPTR GCPtr);
348	VMMDECL(int) PGMGstSetPage(PVMCPUCC pVCpu, RTGCPTR GCPtr, size_t cb, uint64_t fFlags);
349	VMMDECL(int) PGMGstModifyPage(PVMCPUCC pVCpu, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask);
350	VMM_INT_DECL(int) PGMGstGetPaePdpes(PVMCPUCC pVCpu, PX86PDPE paPdpes);
351	VMM_INT_DECL(void) PGMGstUpdatePaePdpes(PVMCPUCC pVCpu, PCX86PDPE paPdpes);
352
353	VMMDECL(int) PGMInvalidatePage(PVMCPUCC pVCpu, RTGCPTR GCPtrPage);
354	VMMDECL(int) PGMFlushTLB(PVMCPUCC pVCpu, uint64_t cr3, bool fGlobal);
355	VMMDECL(int) PGMSyncCR3(PVMCPUCC pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal);
356	VMMDECL(int) PGMUpdateCR3(PVMCPUCC pVCpu, uint64_t cr3);
357	VMMDECL(int) PGMChangeMode(PVMCPUCC pVCpu, uint64_t cr0, uint64_t cr4, uint64_t efer);
358	VMM_INT_DECL(int) PGMHCChangeMode(PVMCC pVM, PVMCPUCC pVCpu, PGMMODE enmGuestMode);
359	VMMDECL(void) PGMCr0WpEnabled(PVMCPUCC pVCpu);
360	VMMDECL(PGMMODE) PGMGetGuestMode(PVMCPU pVCpu);
361	VMMDECL(PGMMODE) PGMGetShadowMode(PVMCPU pVCpu);
362	VMMDECL(PGMMODE) PGMGetHostMode(PVM pVM);
363	VMMDECL(const char *) PGMGetModeName(PGMMODE enmMode);
364	VMM_INT_DECL(RTGCPHYS) PGMGetGuestCR3Phys(PVMCPU pVCpu);
365	VMM_INT_DECL(void) PGMNotifyNxeChanged(PVMCPU pVCpu, bool fNxe);
366	VMMDECL(bool) PGMHasDirtyPages(PVM pVM);
367
368	/** PGM physical access handler type registration handle (heap offset, valid
369	* cross contexts without needing fixing up). Callbacks and handler type is
370	* associated with this and it is shared by all handler registrations. */
371	typedef uint32_t PGMPHYSHANDLERTYPE;
372	/** Pointer to a PGM physical handler type registration handle. */
373	typedef PGMPHYSHANDLERTYPE *PPGMPHYSHANDLERTYPE;
374	/** NIL value for PGM physical access handler type handle. */
375	#define NIL_PGMPHYSHANDLERTYPE UINT32_MAX
376	VMMDECL(uint32_t) PGMHandlerPhysicalTypeRelease(PVMCC pVM, PGMPHYSHANDLERTYPE hType);
377	VMMDECL(uint32_t) PGMHandlerPhysicalTypeRetain(PVM pVM, PGMPHYSHANDLERTYPE hType);
378
379	VMMDECL(int) PGMHandlerPhysicalRegister(PVMCC pVM, RTGCPHYS GCPhys, RTGCPHYS GCPhysLast, PGMPHYSHANDLERTYPE hType,
380	RTR3PTR pvUserR3, RTR0PTR pvUserR0, RTRCPTR pvUserRC,
381	R3PTRTYPE(const char *) pszDesc);
382	VMMDECL(int) PGMHandlerPhysicalModify(PVMCC pVM, RTGCPHYS GCPhysCurrent, RTGCPHYS GCPhys, RTGCPHYS GCPhysLast);
383	VMMDECL(int) PGMHandlerPhysicalDeregister(PVMCC pVM, RTGCPHYS GCPhys);
384	VMMDECL(int) PGMHandlerPhysicalChangeUserArgs(PVMCC pVM, RTGCPHYS GCPhys, RTR3PTR pvUserR3, RTR0PTR pvUserR0);
385	VMMDECL(int) PGMHandlerPhysicalSplit(PVMCC pVM, RTGCPHYS GCPhys, RTGCPHYS GCPhysSplit);
386	VMMDECL(int) PGMHandlerPhysicalJoin(PVMCC pVM, RTGCPHYS GCPhys1, RTGCPHYS GCPhys2);
387	VMMDECL(int) PGMHandlerPhysicalPageTempOff(PVMCC pVM, RTGCPHYS GCPhys, RTGCPHYS GCPhysPage);
388	VMMDECL(int) PGMHandlerPhysicalPageAliasMmio2(PVMCC pVM, RTGCPHYS GCPhys, RTGCPHYS GCPhysPage,
389	PPDMDEVINS pDevIns, PGMMMIO2HANDLE hMmio2, RTGCPHYS offMMio2PageRemap);
390	VMMDECL(int) PGMHandlerPhysicalPageAliasHC(PVMCC pVM, RTGCPHYS GCPhys, RTGCPHYS GCPhysPage, RTHCPHYS HCPhysPageRemap);
391	VMMDECL(int) PGMHandlerPhysicalReset(PVMCC pVM, RTGCPHYS GCPhys);
392	VMMDECL(bool) PGMHandlerPhysicalIsRegistered(PVMCC pVM, RTGCPHYS GCPhys);
393
394
395	/**
396	* Page type.
397	*
398	* @remarks This enum has to fit in a 3-bit field (see PGMPAGE::u3Type).
399	* @remarks This is used in the saved state, so changes to it requires bumping
400	* the saved state version.
401	* @todo So, convert to \#defines!
402	*/
403	typedef enum PGMPAGETYPE
404	{
405	/** The usual invalid zero entry. */
406	PGMPAGETYPE_INVALID = 0,
407	/** RAM page. (RWX) */
408	PGMPAGETYPE_RAM,
409	/** MMIO2 page. (RWX) */
410	PGMPAGETYPE_MMIO2,
411	/** MMIO2 page aliased over an MMIO page. (RWX)
412	* See PGMHandlerPhysicalPageAlias(). */
413	PGMPAGETYPE_MMIO2_ALIAS_MMIO,
414	/** Special page aliased over an MMIO page. (RWX)
415	* See PGMHandlerPhysicalPageAliasHC(), but this is generally only used for
416	* VT-x's APIC access page at the moment. Treated as MMIO by everyone except
417	* the shadow paging code. */
418	PGMPAGETYPE_SPECIAL_ALIAS_MMIO,
419	/** Shadowed ROM. (RWX) */
420	PGMPAGETYPE_ROM_SHADOW,
421	/** ROM page. (R-X) */
422	PGMPAGETYPE_ROM,
423	/** MMIO page. (---) */
424	PGMPAGETYPE_MMIO,
425	/** End of valid entries. */
426	PGMPAGETYPE_END
427	} PGMPAGETYPE;
428	AssertCompile(PGMPAGETYPE_END == 8);
429
430	/** @name PGM page type predicates.
431	* @{ */
432	#define PGMPAGETYPE_IS_READABLE(a_enmType) ( (a_enmType) <= PGMPAGETYPE_ROM )
433	#define PGMPAGETYPE_IS_WRITEABLE(a_enmType) ( (a_enmType) <= PGMPAGETYPE_ROM_SHADOW )
434	#define PGMPAGETYPE_IS_RWX(a_enmType) ( (a_enmType) <= PGMPAGETYPE_ROM_SHADOW )
435	#define PGMPAGETYPE_IS_ROX(a_enmType) ( (a_enmType) == PGMPAGETYPE_ROM )
436	#define PGMPAGETYPE_IS_NP(a_enmType) ( (a_enmType) == PGMPAGETYPE_MMIO )
437	/** @} */
438
439
440	VMM_INT_DECL(PGMPAGETYPE) PGMPhysGetPageType(PVMCC pVM, RTGCPHYS GCPhys);
441
442	VMM_INT_DECL(int) PGMPhysGCPhys2HCPhys(PVMCC pVM, RTGCPHYS GCPhys, PRTHCPHYS pHCPhys);
443	VMM_INT_DECL(int) PGMPhysGCPtr2HCPhys(PVMCPUCC pVCpu, RTGCPTR GCPtr, PRTHCPHYS pHCPhys);
444	VMM_INT_DECL(int) PGMPhysGCPhys2CCPtr(PVMCC pVM, RTGCPHYS GCPhys, void **ppv, PPGMPAGEMAPLOCK pLock);
445	VMM_INT_DECL(int) PGMPhysGCPhys2CCPtrReadOnly(PVMCC pVM, RTGCPHYS GCPhys, void const **ppv, PPGMPAGEMAPLOCK pLock);
446	VMM_INT_DECL(int) PGMPhysGCPtr2CCPtr(PVMCPU pVCpu, RTGCPTR GCPtr, void **ppv, PPGMPAGEMAPLOCK pLock);
447	VMM_INT_DECL(int) PGMPhysGCPtr2CCPtrReadOnly(PVMCPUCC pVCpu, RTGCPTR GCPtr, void const **ppv, PPGMPAGEMAPLOCK pLock);
448
449	VMMDECL(bool) PGMPhysIsA20Enabled(PVMCPU pVCpu);
450	VMMDECL(bool) PGMPhysIsGCPhysValid(PVMCC pVM, RTGCPHYS GCPhys);
451	VMMDECL(bool) PGMPhysIsGCPhysNormal(PVMCC pVM, RTGCPHYS GCPhys);
452	VMMDECL(int) PGMPhysGCPtr2GCPhys(PVMCPUCC pVCpu, RTGCPTR GCPtr, PRTGCPHYS pGCPhys);
453	VMMDECL(void) PGMPhysReleasePageMappingLock(PVMCC pVM, PPGMPAGEMAPLOCK pLock);
454	VMMDECL(void) PGMPhysBulkReleasePageMappingLocks(PVMCC pVM, uint32_t cPages, PPGMPAGEMAPLOCK paLock);
455
456	/** @def PGM_PHYS_RW_IS_SUCCESS
457	* Check whether a PGMPhysRead, PGMPhysWrite, PGMPhysReadGCPtr or
458	* PGMPhysWriteGCPtr call completed the given task.
459	*
460	* @returns true if completed, false if not.
461	* @param a_rcStrict The status code.
462	* @sa IOM_SUCCESS
463	*/
464	#ifdef IN_RING3
465	# define PGM_PHYS_RW_IS_SUCCESS(a_rcStrict) \
466	( (a_rcStrict) == VINF_SUCCESS \
467	\|\| (a_rcStrict) == VINF_EM_DBG_STOP \
468	\|\| (a_rcStrict) == VINF_EM_DBG_EVENT \
469	\|\| (a_rcStrict) == VINF_EM_DBG_BREAKPOINT \
470	)
471	#elif defined(IN_RING0)
472	# define PGM_PHYS_RW_IS_SUCCESS(a_rcStrict) \
473	( (a_rcStrict) == VINF_SUCCESS \
474	\|\| (a_rcStrict) == VINF_IOM_R3_MMIO_COMMIT_WRITE \
475	\|\| (a_rcStrict) == VINF_EM_OFF \
476	\|\| (a_rcStrict) == VINF_EM_SUSPEND \
477	\|\| (a_rcStrict) == VINF_EM_RESET \
478	\|\| (a_rcStrict) == VINF_EM_HALT \
479	\|\| (a_rcStrict) == VINF_EM_DBG_STOP \
480	\|\| (a_rcStrict) == VINF_EM_DBG_EVENT \
481	\|\| (a_rcStrict) == VINF_EM_DBG_BREAKPOINT \
482	)
483	#elif defined(IN_RC)
484	# define PGM_PHYS_RW_IS_SUCCESS(a_rcStrict) \
485	( (a_rcStrict) == VINF_SUCCESS \
486	\|\| (a_rcStrict) == VINF_IOM_R3_MMIO_COMMIT_WRITE \
487	\|\| (a_rcStrict) == VINF_EM_OFF \
488	\|\| (a_rcStrict) == VINF_EM_SUSPEND \
489	\|\| (a_rcStrict) == VINF_EM_RESET \
490	\|\| (a_rcStrict) == VINF_EM_HALT \
491	\|\| (a_rcStrict) == VINF_SELM_SYNC_GDT \
492	\|\| (a_rcStrict) == VINF_EM_RAW_EMULATE_INSTR_GDT_FAULT \
493	\|\| (a_rcStrict) == VINF_EM_DBG_STOP \
494	\|\| (a_rcStrict) == VINF_EM_DBG_EVENT \
495	\|\| (a_rcStrict) == VINF_EM_DBG_BREAKPOINT \
496	)
497	#endif
498	/** @def PGM_PHYS_RW_DO_UPDATE_STRICT_RC
499	* Updates the return code with a new result.
500	*
501	* Both status codes must be successes according to PGM_PHYS_RW_IS_SUCCESS.
502	*
503	* @param a_rcStrict The current return code, to be updated.
504	* @param a_rcStrict2 The new return code to merge in.
505	*/
506	#ifdef IN_RING3
507	# define PGM_PHYS_RW_DO_UPDATE_STRICT_RC(a_rcStrict, a_rcStrict2) \
508	do { \
509	Assert(rcStrict == VINF_SUCCESS); \
510	Assert(rcStrict2 == VINF_SUCCESS); \
511	} while (0)
512	#elif defined(IN_RING0)
513	# define PGM_PHYS_RW_DO_UPDATE_STRICT_RC(a_rcStrict, a_rcStrict2) \
514	do { \
515	Assert(PGM_PHYS_RW_IS_SUCCESS(rcStrict)); \
516	Assert(PGM_PHYS_RW_IS_SUCCESS(rcStrict2)); \
517	AssertCompile(VINF_IOM_R3_MMIO_COMMIT_WRITE > VINF_EM_LAST); \
518	if ((a_rcStrict2) == VINF_SUCCESS \|\| (a_rcStrict) == (a_rcStrict2)) \
519	{ /* likely */ } \
520	else if ( (a_rcStrict) == VINF_SUCCESS \
521	\|\| (a_rcStrict) > (a_rcStrict2)) \
522	(a_rcStrict) = (a_rcStrict2); \
523	} while (0)
524	#elif defined(IN_RC)
525	# define PGM_PHYS_RW_DO_UPDATE_STRICT_RC(a_rcStrict, a_rcStrict2) \
526	do { \
527	Assert(PGM_PHYS_RW_IS_SUCCESS(rcStrict)); \
528	Assert(PGM_PHYS_RW_IS_SUCCESS(rcStrict2)); \
529	AssertCompile(VINF_SELM_SYNC_GDT > VINF_EM_LAST); \
530	AssertCompile(VINF_EM_RAW_EMULATE_INSTR_GDT_FAULT > VINF_EM_LAST); \
531	AssertCompile(VINF_EM_RAW_EMULATE_INSTR_GDT_FAULT < VINF_SELM_SYNC_GDT); \
532	AssertCompile(VINF_IOM_R3_MMIO_COMMIT_WRITE > VINF_EM_LAST); \
533	AssertCompile(VINF_IOM_R3_MMIO_COMMIT_WRITE > VINF_SELM_SYNC_GDT); \
534	AssertCompile(VINF_IOM_R3_MMIO_COMMIT_WRITE > VINF_EM_RAW_EMULATE_INSTR_GDT_FAULT); \
535	if ((a_rcStrict2) == VINF_SUCCESS \|\| (a_rcStrict) == (a_rcStrict2)) \
536	{ /* likely */ } \
537	else if ((a_rcStrict) == VINF_SUCCESS) \
538	(a_rcStrict) = (a_rcStrict2); \
539	else if ( ( (a_rcStrict) > (a_rcStrict2) \
540	&& ( (a_rcStrict2) <= VINF_EM_RESET \
541	\|\| (a_rcStrict) != VINF_EM_RAW_EMULATE_INSTR_GDT_FAULT) ) \
542	\|\| ( (a_rcStrict2) == VINF_EM_RAW_EMULATE_INSTR_GDT_FAULT \
543	&& (a_rcStrict) > VINF_EM_RESET) ) \
544	(a_rcStrict) = (a_rcStrict2); \
545	} while (0)
546	#endif
547
548	VMMDECL(VBOXSTRICTRC) PGMPhysRead(PVMCC pVM, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead, PGMACCESSORIGIN enmOrigin);
549	VMMDECL(VBOXSTRICTRC) PGMPhysWrite(PVMCC pVM, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite, PGMACCESSORIGIN enmOrigin);
550	VMMDECL(VBOXSTRICTRC) PGMPhysReadGCPtr(PVMCPUCC pVCpu, void *pvDst, RTGCPTR GCPtrSrc, size_t cb, PGMACCESSORIGIN enmOrigin);
551	VMMDECL(VBOXSTRICTRC) PGMPhysWriteGCPtr(PVMCPUCC pVCpu, RTGCPTR GCPtrDst, const void *pvSrc, size_t cb, PGMACCESSORIGIN enmOrigin);
552
553	VMMDECL(int) PGMPhysSimpleReadGCPhys(PVMCC pVM, void *pvDst, RTGCPHYS GCPhysSrc, size_t cb);
554	VMMDECL(int) PGMPhysSimpleWriteGCPhys(PVMCC pVM, RTGCPHYS GCPhysDst, const void *pvSrc, size_t cb);
555	VMMDECL(int) PGMPhysSimpleReadGCPtr(PVMCPUCC pVCpu, void *pvDst, RTGCPTR GCPtrSrc, size_t cb);
556	VMMDECL(int) PGMPhysSimpleWriteGCPtr(PVMCPUCC pVCpu, RTGCPTR GCPtrDst, const void *pvSrc, size_t cb);
557	VMMDECL(int) PGMPhysSimpleDirtyWriteGCPtr(PVMCPUCC pVCpu, RTGCPTR GCPtrDst, const void *pvSrc, size_t cb);
558	VMMDECL(int) PGMPhysInterpretedRead(PVMCPUCC pVCpu, PCPUMCTXCORE pCtxCore, void *pvDst, RTGCPTR GCPtrSrc, size_t cb);
559	VMMDECL(int) PGMPhysInterpretedReadNoHandlers(PVMCPUCC pVCpu, PCPUMCTXCORE pCtxCore, void *pvDst, RTGCUINTPTR GCPtrSrc, size_t cb, bool fRaiseTrap);
560	VMMDECL(int) PGMPhysInterpretedWriteNoHandlers(PVMCPUCC pVCpu, PCPUMCTXCORE pCtxCore, RTGCPTR GCPtrDst, void const *pvSrc, size_t cb, bool fRaiseTrap);
561
562	VMM_INT_DECL(int) PGMPhysIemGCPhys2Ptr(PVMCC pVM, PVMCPUCC pVCpu, RTGCPHYS GCPhys, bool fWritable, bool fByPassHandlers, void **ppv, PPGMPAGEMAPLOCK pLock);
563	VMM_INT_DECL(int) PGMPhysIemQueryAccess(PVMCC pVM, RTGCPHYS GCPhys, bool fWritable, bool fByPassHandlers);
564	VMM_INT_DECL(int) PGMPhysIemGCPhys2PtrNoLock(PVMCC pVM, PVMCPUCC pVCpu, RTGCPHYS GCPhys, uint64_t const volatile *puTlbPhysRev,
565	#if defined(IN_RC)
566	R3PTRTYPE(uint8_t ) ppb,
567	#else
568	R3R0PTRTYPE(uint8_t ) ppb,
569	#endif
570	uint64_t *pfTlb);
571	/** @name Flags returned by PGMPhysIemGCPhys2PtrNoLock
572	* @{ */
573	#define PGMIEMGCPHYS2PTR_F_NO_WRITE RT_BIT_32(3) /*< Not writable (IEMTLBE_F_PG_NO_WRITE). /
574	#define PGMIEMGCPHYS2PTR_F_NO_READ RT_BIT_32(4) /*< Not readable (IEMTLBE_F_PG_NO_READ). /
575	#define PGMIEMGCPHYS2PTR_F_NO_MAPPINGR3 RT_BIT_32(7) /*< No ring-3 mapping (IEMTLBE_F_NO_MAPPINGR3). /
576	/** @} */
577
578	/** Information returned by PGMPhysNemQueryPageInfo. */
579	typedef struct PGMPHYSNEMPAGEINFO
580	{
581	/** The host physical address of the page, NIL_HCPHYS if invalid page. */
582	RTHCPHYS HCPhys;
583	/** The NEM access mode for the page, NEM_PAGE_PROT_XXX */
584	uint32_t fNemProt : 8;
585	/** The NEM state associated with the PAGE. */
586	uint32_t u2NemState : 2;
587	/** The NEM state associated with the PAGE before pgmPhysPageMakeWritable was called. */
588	uint32_t u2OldNemState : 2;
589	/** Set if the page has handler. */
590	uint32_t fHasHandlers : 1;
591	/** Set if is the zero page backing it. */
592	uint32_t fZeroPage : 1;
593	/** Set if the page has handler. */
594	PGMPAGETYPE enmType;
595	} PGMPHYSNEMPAGEINFO;
596	/** Pointer to page information for NEM. */
597	typedef PGMPHYSNEMPAGEINFO *PPGMPHYSNEMPAGEINFO;
598	/**
599	* Callback for checking that the page is in sync while under the PGM lock.
600	*
601	* NEM passes this callback to PGMPhysNemQueryPageInfo to check that the page is
602	* in-sync between PGM and the native hypervisor API in an atomic fashion.
603	*
604	* @returns VBox status code.
605	* @param pVM The cross context VM structure.
606	* @param pVCpu The cross context per virtual CPU structure. Optional,
607	* see PGMPhysNemQueryPageInfo.
608	* @param GCPhys The guest physical address (not A20 masked).
609	* @param pInfo The page info structure. This function updates the
610	* u2NemState memory and the caller will update the PGMPAGE
611	* copy accordingly.
612	* @param pvUser Callback user argument.
613	*/
614	typedef DECLCALLBACKTYPE(int, FNPGMPHYSNEMCHECKPAGE,(PVMCC pVM, PVMCPUCC pVCpu, RTGCPHYS GCPhys, PPGMPHYSNEMPAGEINFO pInfo, void *pvUser));
615	/** Pointer to a FNPGMPHYSNEMCHECKPAGE function. */
616	typedef FNPGMPHYSNEMCHECKPAGE *PFNPGMPHYSNEMCHECKPAGE;
617
618	VMM_INT_DECL(int) PGMPhysNemPageInfoChecker(PVMCC pVM, PVMCPUCC pVCpu, RTGCPHYS GCPhys, bool fMakeWritable,
619	PPGMPHYSNEMPAGEINFO pInfo, PFNPGMPHYSNEMCHECKPAGE pfnChecker, void *pvUser);
620
621	/**
622	* Callback for use with PGMPhysNemEnumPagesByState.
623	* @returns VBox status code.
624	* Failure status will stop enumeration immediately and return.
625	* @param pVM The cross context VM structure.
626	* @param pVCpu The cross context per virtual CPU structure. Optional,
627	* see PGMPhysNemEnumPagesByState.
628	* @param GCPhys The guest physical address (not A20 masked).
629	* @param pu2NemState Pointer to variable with the NEM state. This can be
630	* update.
631	* @param pvUser The user argument.
632	*/
633	typedef DECLCALLBACKTYPE(int, FNPGMPHYSNEMENUMCALLBACK,(PVMCC pVM, PVMCPUCC pVCpu, RTGCPHYS GCPhys,
634	uint8_t pu2NemState, void pvUser));
635	/** Pointer to a FNPGMPHYSNEMENUMCALLBACK function. */
636	typedef FNPGMPHYSNEMENUMCALLBACK *PFNPGMPHYSNEMENUMCALLBACK;
637	VMM_INT_DECL(int) PGMPhysNemEnumPagesByState(PVMCC pVM, PVMCPUCC VCpu, uint8_t uMinState,
638	PFNPGMPHYSNEMENUMCALLBACK pfnCallback, void *pvUser);
639
640
641	#ifdef VBOX_STRICT
642	VMMDECL(unsigned) PGMAssertHandlerAndFlagsInSync(PVMCC pVM);
643	VMMDECL(unsigned) PGMAssertNoMappingConflicts(PVM pVM);
644	VMMDECL(unsigned) PGMAssertCR3(PVMCC pVM, PVMCPUCC pVCpu, uint64_t cr3, uint64_t cr4);
645	#endif /* VBOX_STRICT */
646
647	VMMDECL(int) PGMSetLargePageUsage(PVMCC pVM, bool fUseLargePages);
648
649	/**
650	* Query large page usage state
651	*
652	* @returns 0 - disabled, 1 - enabled
653	* @param pVM The cross context VM structure.
654	*/
655	#define PGMIsUsingLargePages(pVM) ((pVM)->fUseLargePages)
656
657
658	#ifdef IN_RING0
659	/** @defgroup grp_pgm_r0 The PGM Host Context Ring-0 API
660	* @{
661	*/
662	VMMR0_INT_DECL(int) PGMR0InitPerVMData(PGVM pGVM);
663	VMMR0_INT_DECL(int) PGMR0InitVM(PGVM pGVM);
664	VMMR0_INT_DECL(void) PGMR0CleanupVM(PGVM pGVM);
665	VMMR0_INT_DECL(int) PGMR0PhysAllocateHandyPages(PGVM pGVM, VMCPUID idCpu);
666	VMMR0_INT_DECL(int) PGMR0PhysFlushHandyPages(PGVM pGVM, VMCPUID idCpu);
667	VMMR0_INT_DECL(int) PGMR0PhysAllocateLargeHandyPage(PGVM pGVM, VMCPUID idCpu);
668	VMMR0_INT_DECL(int) PGMR0PhysMMIO2MapKernel(PGVM pGVM, PPDMDEVINS pDevIns, PGMMMIO2HANDLE hMmio2,
669	size_t offSub, size_t cbSub, void **ppvMapping);
670	VMMR0_INT_DECL(int) PGMR0PhysSetupIoMmu(PGVM pGVM);
671	VMMR0DECL(int) PGMR0SharedModuleCheck(PVMCC pVM, PGVM pGVM, VMCPUID idCpu, PGMMSHAREDMODULE pModule,
672	PCRTGCPTR64 paRegionsGCPtrs);
673	VMMR0DECL(int) PGMR0Trap0eHandlerNestedPaging(PGVM pGVM, PGVMCPU pGVCpu, PGMMODE enmShwPagingMode, RTGCUINT uErr,
674	PCPUMCTXCORE pRegFrame, RTGCPHYS pvFault);
675	VMMR0DECL(VBOXSTRICTRC) PGMR0Trap0eHandlerNPMisconfig(PGVM pGVM, PGVMCPU pGVCpu, PGMMODE enmShwPagingMode,
676	PCPUMCTXCORE pRegFrame, RTGCPHYS GCPhysFault, uint32_t uErr);
677	VMMR0_INT_DECL(int) PGMR0PoolGrow(PGVM pGVM, VMCPUID idCpu);
678	/** @} */
679	#endif /* IN_RING0 */
680
681
682
683	#ifdef IN_RING3
684	/** @defgroup grp_pgm_r3 The PGM Host Context Ring-3 API
685	* @{
686	*/
687	VMMR3DECL(int) PGMR3Init(PVM pVM);
688	VMMR3DECL(int) PGMR3InitDynMap(PVM pVM);
689	VMMR3DECL(int) PGMR3InitFinalize(PVM pVM);
690	VMMR3_INT_DECL(int) PGMR3InitCompleted(PVM pVM, VMINITCOMPLETED enmWhat);
691	VMMR3DECL(void) PGMR3Relocate(PVM pVM, RTGCINTPTR offDelta);
692	VMMR3DECL(void) PGMR3ResetCpu(PVM pVM, PVMCPU pVCpu);
693	VMMR3_INT_DECL(void) PGMR3Reset(PVM pVM);
694	VMMR3_INT_DECL(void) PGMR3ResetNoMorePhysWritesFlag(PVM pVM);
695	VMMR3_INT_DECL(void) PGMR3MemSetup(PVM pVM, bool fReset);
696	VMMR3DECL(int) PGMR3Term(PVM pVM);
697
698	VMMR3DECL(int) PGMR3PhysRegisterRam(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, const char *pszDesc);
699	VMMR3DECL(int) PGMR3PhysChangeMemBalloon(PVM pVM, bool fInflate, unsigned cPages, RTGCPHYS *paPhysPage);
700	VMMR3DECL(int) PGMR3PhysWriteProtectRAM(PVM pVM);
701	VMMR3DECL(uint32_t) PGMR3PhysGetRamRangeCount(PVM pVM);
702	VMMR3DECL(int) PGMR3PhysGetRange(PVM pVM, uint32_t iRange, PRTGCPHYS pGCPhysStart, PRTGCPHYS pGCPhysLast,
703	const char *ppszDesc, bool pfIsMmio);
704	VMMR3DECL(int) PGMR3QueryMemoryStats(PUVM pUVM, uint64_t pcbTotalMem, uint64_t pcbPrivateMem, uint64_t pcbSharedMem, uint64_t pcbZeroMem);
705	VMMR3DECL(int) PGMR3QueryGlobalMemoryStats(PUVM pUVM, uint64_t pcbAllocMem, uint64_t pcbFreeMem, uint64_t pcbBallonedMem, uint64_t pcbSharedMem);
706
707	VMMR3DECL(int) PGMR3PhysMMIORegister(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, PGMPHYSHANDLERTYPE hType,
708	RTR3PTR pvUserR3, RTR0PTR pvUserR0, RTRCPTR pvUserRC, const char *pszDesc);
709	VMMR3DECL(int) PGMR3PhysMMIODeregister(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb);
710	VMMR3_INT_DECL(int) PGMR3PhysMmio2Register(PVM pVM, PPDMDEVINS pDevIns, uint32_t iSubDev, uint32_t iRegion, RTGCPHYS cb,
711	uint32_t fFlags, const char pszDesc, void ppv, PGMMMIO2HANDLE phRegion);
712	VMMR3_INT_DECL(int) PGMR3PhysMmio2Deregister(PVM pVM, PPDMDEVINS pDevIns, PGMMMIO2HANDLE hMmio2);
713	VMMR3_INT_DECL(int) PGMR3PhysMmio2Map(PVM pVM, PPDMDEVINS pDevIns, PGMMMIO2HANDLE hMmio2, RTGCPHYS GCPhys);
714	VMMR3_INT_DECL(int) PGMR3PhysMmio2Unmap(PVM pVM, PPDMDEVINS pDevIns, PGMMMIO2HANDLE hMmio2, RTGCPHYS GCPhys);
715	VMMR3_INT_DECL(int) PGMR3PhysMmio2Reduce(PVM pVM, PPDMDEVINS pDevIns, PGMMMIO2HANDLE hMmio2, RTGCPHYS cbRegion);
716	VMMR3_INT_DECL(int) PGMR3PhysMmio2ValidateHandle(PVM pVM, PPDMDEVINS pDevIns, PGMMMIO2HANDLE hMmio2);
717	VMMR3_INT_DECL(RTGCPHYS) PGMR3PhysMmio2GetMappingAddress(PVM pVM, PPDMDEVINS pDevIns, PGMMMIO2HANDLE hMmio2);
718	VMMR3_INT_DECL(int) PGMR3PhysMmio2ChangeRegionNo(PVM pVM, PPDMDEVINS pDevIns, PGMMMIO2HANDLE hMmio2, uint32_t iNewRegion);
719	VMMR3_INT_DECL(int) PGMR3PhysMMIO2GetHCPhys(PVM pVM, PPDMDEVINS pDevIns, uint32_t iSubDev, uint32_t iRegion, RTGCPHYS off, PRTHCPHYS pHCPhys);
720
721
722	/** @name PGMR3PhysRegisterRom flags.
723	* @{ */
724	/** Inidicates that ROM shadowing should be enabled. */
725	#define PGMPHYS_ROM_FLAGS_SHADOWED RT_BIT_32(0)
726	/** Indicates that what pvBinary points to won't go away
727	* and can be used for strictness checks. */
728	#define PGMPHYS_ROM_FLAGS_PERMANENT_BINARY RT_BIT_32(1)
729	/** Indicates that the ROM is allowed to be missing from saved state.
730	* @note This is a hack for EFI, see @bugref{6940} */
731	#define PGMPHYS_ROM_FLAGS_MAYBE_MISSING_FROM_STATE RT_BIT_32(2)
732	/** Valid flags. */
733	#define PGMPHYS_ROM_FLAGS_VALID_MASK UINT32_C(0x00000007)
734	/** @} */
735
736	VMMR3DECL(int) PGMR3PhysRomRegister(PVM pVM, PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTGCPHYS cb,
737	const void pvBinary, uint32_t cbBinary, uint32_t fFlags, const char pszDesc);
738	VMMR3DECL(int) PGMR3PhysRomProtect(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, PGMROMPROT enmProt);
739	VMMR3DECL(int) PGMR3PhysRegister(PVM pVM, void pvRam, RTGCPHYS GCPhys, size_t cb, unsigned fFlags, const SUPPAGE paPages, const char *pszDesc);
740	VMMDECL(void) PGMR3PhysSetA20(PVMCPU pVCpu, bool fEnable);
741	#ifndef PGM_WITHOUT_MAPPINGS
742	/** @name PGMR3MapPT flags.
743	* @{ */
744	/** The mapping may be unmapped later. The default is permanent mappings. */
745	# define PGMR3MAPPT_FLAGS_UNMAPPABLE RT_BIT(0)
746	/** @} */
747	VMMR3DECL(int) PGMR3MapPT(PVM pVM, RTGCPTR GCPtr, uint32_t cb, uint32_t fFlags, PFNPGMRELOCATE pfnRelocate, void pvUser, const char pszDesc);
748	VMMR3DECL(int) PGMR3UnmapPT(PVM pVM, RTGCPTR GCPtr);
749	VMMR3DECL(int) PGMR3FinalizeMappings(PVM pVM);
750	VMMR3DECL(bool) PGMR3MappingsNeedReFixing(PVM pVM);
751	# if defined(VBOX_WITH_RAW_MODE) \|\| HC_ARCH_BITS == 32 /* (latter for 64-bit guests on 32-bit hosts) */
752	VMMR3DECL(int) PGMR3MapIntermediate(PVM pVM, RTUINTPTR Addr, RTHCPHYS HCPhys, unsigned cbPages);
753	# endif
754	VMMR3DECL(int) PGMR3MapRead(PVM pVM, void *pvDst, RTGCPTR GCPtrSrc, size_t cb);
755	#endif /* !PGM_WITHOUT_MAPPINGS */
756	VMMR3DECL(int) PGMR3MappingsSize(PVM pVM, uint32_t *pcb);
757	VMMR3DECL(int) PGMR3MappingsFix(PVM pVM, RTGCPTR GCPtrBase, uint32_t cb);
758	VMMR3DECL(int) PGMR3MappingsUnfix(PVM pVM);
759
760	VMMR3_INT_DECL(int) PGMR3HandlerPhysicalTypeRegisterEx(PVM pVM, PGMPHYSHANDLERKIND enmKind,
761	PFNPGMPHYSHANDLER pfnHandlerR3,
762	R0PTRTYPE(PFNPGMPHYSHANDLER) pfnHandlerR0,
763	R0PTRTYPE(PFNPGMRZPHYSPFHANDLER) pfnPfHandlerR0,
764	const char *pszDesc, PPGMPHYSHANDLERTYPE phType);
765	VMMR3DECL(int) PGMR3HandlerPhysicalTypeRegister(PVM pVM, PGMPHYSHANDLERKIND enmKind,
766	R3PTRTYPE(PFNPGMPHYSHANDLER) pfnHandlerR3,
767	const char pszModR0, const char pszHandlerR0, const char *pszPfHandlerR0,
768	const char pszModRC, const char pszHandlerRC, const char *pszPfHandlerRC,
769	const char *pszDesc,
770	PPGMPHYSHANDLERTYPE phType);
771	VMMR3_INT_DECL(int) PGMR3PoolGrow(PVM pVM, PVMCPU pVCpu);
772
773	VMMR3DECL(int) PGMR3PhysTlbGCPhys2Ptr(PVM pVM, RTGCPHYS GCPhys, bool fWritable, void **ppv);
774	VMMR3DECL(uint8_t) PGMR3PhysReadU8(PVM pVM, RTGCPHYS GCPhys, PGMACCESSORIGIN enmOrigin);
775	VMMR3DECL(uint16_t) PGMR3PhysReadU16(PVM pVM, RTGCPHYS GCPhys, PGMACCESSORIGIN enmOrigin);
776	VMMR3DECL(uint32_t) PGMR3PhysReadU32(PVM pVM, RTGCPHYS GCPhys, PGMACCESSORIGIN enmOrigin);
777	VMMR3DECL(uint64_t) PGMR3PhysReadU64(PVM pVM, RTGCPHYS GCPhys, PGMACCESSORIGIN enmOrigin);
778	VMMR3DECL(void) PGMR3PhysWriteU8(PVM pVM, RTGCPHYS GCPhys, uint8_t Value, PGMACCESSORIGIN enmOrigin);
779	VMMR3DECL(void) PGMR3PhysWriteU16(PVM pVM, RTGCPHYS GCPhys, uint16_t Value, PGMACCESSORIGIN enmOrigin);
780	VMMR3DECL(void) PGMR3PhysWriteU32(PVM pVM, RTGCPHYS GCPhys, uint32_t Value, PGMACCESSORIGIN enmOrigin);
781	VMMR3DECL(void) PGMR3PhysWriteU64(PVM pVM, RTGCPHYS GCPhys, uint64_t Value, PGMACCESSORIGIN enmOrigin);
782	VMMR3DECL(int) PGMR3PhysReadExternal(PVM pVM, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead, PGMACCESSORIGIN enmOrigin);
783	VMMR3DECL(int) PGMR3PhysWriteExternal(PVM pVM, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite, PGMACCESSORIGIN enmOrigin);
784	VMMR3DECL(int) PGMR3PhysGCPhys2CCPtrExternal(PVM pVM, RTGCPHYS GCPhys, void **ppv, PPGMPAGEMAPLOCK pLock);
785	VMMR3DECL(int) PGMR3PhysGCPhys2CCPtrReadOnlyExternal(PVM pVM, RTGCPHYS GCPhys, void const **ppv, PPGMPAGEMAPLOCK pLock);
786	VMMR3DECL(int) PGMR3PhysBulkGCPhys2CCPtrExternal(PVM pVM, uint32_t cPages, PCRTGCPHYS paGCPhysPages,
787	void **papvPages, PPGMPAGEMAPLOCK paLocks);
788	VMMR3DECL(int) PGMR3PhysBulkGCPhys2CCPtrReadOnlyExternal(PVM pVM, uint32_t cPages, PCRTGCPHYS paGCPhysPages,
789	void const **papvPages, PPGMPAGEMAPLOCK paLocks);
790	VMMR3DECL(void) PGMR3PhysChunkInvalidateTLB(PVM pVM);
791	VMMR3DECL(int) PGMR3PhysAllocateHandyPages(PVM pVM);
792	VMMR3_INT_DECL(int) PGMR3PhysAllocateLargePage(PVM pVM, RTGCPHYS GCPhys);
793
794	VMMR3DECL(int) PGMR3CheckIntegrity(PVM pVM);
795
796	VMMR3DECL(int) PGMR3DbgR3Ptr2GCPhys(PUVM pUVM, RTR3PTR R3Ptr, PRTGCPHYS pGCPhys);
797	VMMR3DECL(int) PGMR3DbgR3Ptr2HCPhys(PUVM pUVM, RTR3PTR R3Ptr, PRTHCPHYS pHCPhys);
798	VMMR3DECL(int) PGMR3DbgHCPhys2GCPhys(PUVM pUVM, RTHCPHYS HCPhys, PRTGCPHYS pGCPhys);
799	VMMR3_INT_DECL(int) PGMR3DbgReadGCPhys(PVM pVM, void pvDst, RTGCPHYS GCPhysSrc, size_t cb, uint32_t fFlags, size_t pcbRead);
800	VMMR3_INT_DECL(int) PGMR3DbgWriteGCPhys(PVM pVM, RTGCPHYS GCPhysDst, const void pvSrc, size_t cb, uint32_t fFlags, size_t pcbWritten);
801	VMMR3_INT_DECL(int) PGMR3DbgReadGCPtr(PVM pVM, void pvDst, RTGCPTR GCPtrSrc, size_t cb, uint32_t fFlags, size_t pcbRead);
802	VMMR3_INT_DECL(int) PGMR3DbgWriteGCPtr(PVM pVM, RTGCPTR GCPtrDst, void const pvSrc, size_t cb, uint32_t fFlags, size_t pcbWritten);
803	VMMR3_INT_DECL(int) PGMR3DbgScanPhysical(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cbRange, RTGCPHYS GCPhysAlign, const uint8_t *pabNeedle, size_t cbNeedle, PRTGCPHYS pGCPhysHit);
804	VMMR3_INT_DECL(int) PGMR3DbgScanVirtual(PVM pVM, PVMCPU pVCpu, RTGCPTR GCPtr, RTGCPTR cbRange, RTGCPTR GCPtrAlign, const uint8_t *pabNeedle, size_t cbNeedle, PRTGCUINTPTR pGCPhysHit);
805	VMMR3_INT_DECL(int) PGMR3DumpHierarchyShw(PVM pVM, uint64_t cr3, uint32_t fFlags, uint64_t u64FirstAddr, uint64_t u64LastAddr, uint32_t cMaxDepth, PCDBGFINFOHLP pHlp);
806	VMMR3_INT_DECL(int) PGMR3DumpHierarchyGst(PVM pVM, uint64_t cr3, uint32_t fFlags, RTGCPTR FirstAddr, RTGCPTR LastAddr, uint32_t cMaxDepth, PCDBGFINFOHLP pHlp);
807
808
809	/** @name Page sharing
810	* @{ */
811	VMMR3DECL(int) PGMR3SharedModuleRegister(PVM pVM, VBOXOSFAMILY enmGuestOS, char pszModuleName, char pszVersion,
812	RTGCPTR GCBaseAddr, uint32_t cbModule,
813	uint32_t cRegions, VMMDEVSHAREDREGIONDESC const *paRegions);
814	VMMR3DECL(int) PGMR3SharedModuleUnregister(PVM pVM, char pszModuleName, char pszVersion,
815	RTGCPTR GCBaseAddr, uint32_t cbModule);
816	VMMR3DECL(int) PGMR3SharedModuleCheckAll(PVM pVM);
817	VMMR3DECL(int) PGMR3SharedModuleGetPageState(PVM pVM, RTGCPTR GCPtrPage, bool pfShared, uint64_t pfPageFlags);
818	/** @} */
819
820	/** @} */
821	#endif /* IN_RING3 */
822
823	RT_C_DECLS_END
824
825	/** @} */
826	#endif /* !VBOX_INCLUDED_vmm_pgm_h */
827

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source: vbox/trunk/include/VBox/vmm/pgm.h@ 91246

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