pgm.h@ 92186

Last change on this file since 92186 was 92186, checked in by vboxsync, 3 years ago
VMM: Nested VMX: bugref:10092 Separate the guest's second-level address translation into separate enum and adjust templates accordingly plus other related bits.
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 40.0 KB

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1	/** @file
2	* PGM - Page Monitor / Monitor.
3	*/
4
5	/*
6	* Copyright (C) 2006-2020 Oracle Corporation
7	*
8	* This file is part of VirtualBox Open Source Edition (OSE), as
9	* available from http://www.virtualbox.org. This file is free software;
10	* you can redistribute it and/or modify it under the terms of the GNU
11	* General Public License (GPL) as published by the Free Software
12	* Foundation, in version 2 as it comes in the "COPYING" file of the
13	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15	*
16	* The contents of this file may alternatively be used under the terms
17	* of the Common Development and Distribution License Version 1.0
18	* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19	* VirtualBox OSE distribution, in which case the provisions of the
20	* CDDL are applicable instead of those of the GPL.
21	*
22	* You may elect to license modified versions of this file under the
23	* terms and conditions of either the GPL or the CDDL or both.
24	*/
25
26	#ifndef VBOX_INCLUDED_vmm_pgm_h
27	#define VBOX_INCLUDED_vmm_pgm_h
28	#ifndef RT_WITHOUT_PRAGMA_ONCE
29	# pragma once
30	#endif
31
32	#include <VBox/types.h>
33	#include <VBox/sup.h>
34	#include <VBox/vmm/vmapi.h>
35	#include <VBox/vmm/gmm.h> /* for PGMMREGISTERSHAREDMODULEREQ */
36	#include <iprt/x86.h>
37	#include <VBox/param.h>
38
39	RT_C_DECLS_BEGIN
40
41	/** @defgroup grp_pgm The Page Monitor / Manager API
42	* @ingroup grp_vmm
43	* @{
44	*/
45
46	/**
47	* FNPGMRELOCATE callback mode.
48	*/
49	typedef enum PGMRELOCATECALL
50	{
51	/** The callback is for checking if the suggested address is suitable. */
52	PGMRELOCATECALL_SUGGEST = 1,
53	/** The callback is for executing the relocation. */
54	PGMRELOCATECALL_RELOCATE
55	} PGMRELOCATECALL;
56
57
58	/**
59	* Callback function which will be called when PGM is trying to find
60	* a new location for the mapping.
61	*
62	* The callback is called in two modes, 1) the check mode and 2) the relocate mode.
63	* In 1) the callback should say if it objects to a suggested new location. If it
64	* accepts the new location, it is called again for doing it's relocation.
65	*
66	*
67	* @returns true if the location is ok.
68	* @returns false if another location should be found.
69	* @param pVM The cross context VM structure.
70	* @param GCPtrOld The old virtual address.
71	* @param GCPtrNew The new virtual address.
72	* @param enmMode Used to indicate the callback mode.
73	* @param pvUser User argument.
74	* @remark The return value is no a failure indicator, it's an acceptance
75	* indicator. Relocation can not fail!
76	*/
77	typedef DECLCALLBACKTYPE(bool, FNPGMRELOCATE,(PVM pVM, RTGCPTR GCPtrOld, RTGCPTR GCPtrNew, PGMRELOCATECALL enmMode, void *pvUser));
78	/** Pointer to a relocation callback function. */
79	typedef FNPGMRELOCATE *PFNPGMRELOCATE;
80
81
82	/**
83	* Memory access origin.
84	*/
85	typedef enum PGMACCESSORIGIN
86	{
87	/** Invalid zero value. */
88	PGMACCESSORIGIN_INVALID = 0,
89	/** IEM is access memory. */
90	PGMACCESSORIGIN_IEM,
91	/** HM is access memory. */
92	PGMACCESSORIGIN_HM,
93	/** Some device is access memory. */
94	PGMACCESSORIGIN_DEVICE,
95	/** Someone debugging is access memory. */
96	PGMACCESSORIGIN_DEBUGGER,
97	/** SELM is access memory. */
98	PGMACCESSORIGIN_SELM,
99	/** FTM is access memory. */
100	PGMACCESSORIGIN_FTM,
101	/** REM is access memory. */
102	PGMACCESSORIGIN_REM,
103	/** IOM is access memory. */
104	PGMACCESSORIGIN_IOM,
105	/** End of valid values. */
106	PGMACCESSORIGIN_END,
107	/** Type size hack. */
108	PGMACCESSORIGIN_32BIT_HACK = 0x7fffffff
109	} PGMACCESSORIGIN;
110
111
112	/**
113	* Physical page access handler kind.
114	*/
115	typedef enum PGMPHYSHANDLERKIND
116	{
117	/** MMIO range. Pages are not present, all access is done in interpreter or recompiler. */
118	PGMPHYSHANDLERKIND_MMIO = 1,
119	/** Handler all write access to a physical page range. */
120	PGMPHYSHANDLERKIND_WRITE,
121	/** Handler all access to a physical page range. */
122	PGMPHYSHANDLERKIND_ALL
123
124	} PGMPHYSHANDLERKIND;
125
126	/**
127	* Guest Access type
128	*/
129	typedef enum PGMACCESSTYPE
130	{
131	/** Read access. */
132	PGMACCESSTYPE_READ = 1,
133	/** Write access. */
134	PGMACCESSTYPE_WRITE
135	} PGMACCESSTYPE;
136
137
138	/** @def PGM_ALL_CB_DECL
139	* Macro for declaring a handler callback for all contexts. The handler
140	* callback is static in ring-3, and exported in RC and R0.
141	* @sa PGM_ALL_CB2_DECL.
142	*/
143	#if defined(IN_RC) \|\| defined(IN_RING0)
144	# ifdef __cplusplus
145	# define PGM_ALL_CB_DECL(type) extern "C" DECLCALLBACK(DECLEXPORT(type))
146	# else
147	# define PGM_ALL_CB_DECL(type) DECLCALLBACK(DECLEXPORT(type))
148	# endif
149	#else
150	# define PGM_ALL_CB_DECL(type) static DECLCALLBACK(type)
151	#endif
152
153	/** @def PGM_ALL_CB2_DECL
154	* Macro for declaring a handler callback for all contexts. The handler
155	* callback is hidden in ring-3, and exported in RC and R0.
156	* @sa PGM_ALL_CB2_DECL.
157	*/
158	#if defined(IN_RC) \|\| defined(IN_RING0)
159	# ifdef __cplusplus
160	# define PGM_ALL_CB2_DECL(type) extern "C" DECLCALLBACK(DECLEXPORT(type))
161	# else
162	# define PGM_ALL_CB2_DECL(type) DECLCALLBACK(DECLEXPORT(type))
163	# endif
164	#else
165	# define PGM_ALL_CB2_DECL(type) DECL_HIDDEN_CALLBACK(type)
166	#endif
167
168	/** @def PGM_ALL_CB2_PROTO
169	* Macro for declaring a handler callback for all contexts. The handler
170	* callback is hidden in ring-3, and exported in RC and R0.
171	* @param fnType The callback function type.
172	* @sa PGM_ALL_CB2_DECL.
173	*/
174	#if defined(IN_RC) \|\| defined(IN_RING0)
175	# ifdef __cplusplus
176	# define PGM_ALL_CB2_PROTO(fnType) extern "C" DECLEXPORT(fnType)
177	# else
178	# define PGM_ALL_CB2_PROTO(fnType) DECLEXPORT(fnType)
179	# endif
180	#else
181	# define PGM_ALL_CB2_PROTO(fnType) DECLHIDDEN(fnType)
182	#endif
183
184
185	/**
186	* \#PF Handler callback for physical access handler ranges in RC and R0.
187	*
188	* @returns Strict VBox status code (appropriate for ring-0 and raw-mode).
189	* @param pVM The cross context VM structure.
190	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
191	* @param uErrorCode CPU Error code.
192	* @param pRegFrame Trap register frame.
193	* NULL on DMA and other non CPU access.
194	* @param pvFault The fault address (cr2).
195	* @param GCPhysFault The GC physical address corresponding to pvFault.
196	* @param pvUser User argument.
197	* @thread EMT(pVCpu)
198	*/
199	typedef DECLCALLBACKTYPE(VBOXSTRICTRC, FNPGMRZPHYSPFHANDLER,(PVMCC pVM, PVMCPUCC pVCpu, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame,
200	RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser));
201	/** Pointer to PGM access callback. */
202	typedef FNPGMRZPHYSPFHANDLER *PFNPGMRZPHYSPFHANDLER;
203
204
205	/**
206	* Access handler callback for physical access handler ranges.
207	*
208	* The handler can not raise any faults, it's mainly for monitoring write access
209	* to certain pages (like MMIO).
210	*
211	* @returns Strict VBox status code in ring-0 and raw-mode context, in ring-3
212	* the only supported informational status code is
213	* VINF_PGM_HANDLER_DO_DEFAULT.
214	* @retval VINF_SUCCESS if the handler have carried out the operation.
215	* @retval VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the
216	* access operation.
217	* @retval VINF_EM_XXX in ring-0 and raw-mode context.
218	*
219	* @param pVM The cross context VM structure.
220	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
221	* @param GCPhys The physical address the guest is writing to.
222	* @param pvPhys The HC mapping of that address.
223	* @param pvBuf What the guest is reading/writing.
224	* @param cbBuf How much it's reading/writing.
225	* @param enmAccessType The access type.
226	* @param enmOrigin The origin of this call.
227	* @param pvUser User argument.
228	* @thread EMT(pVCpu)
229	*/
230	typedef DECLCALLBACKTYPE(VBOXSTRICTRC, FNPGMPHYSHANDLER,(PVMCC pVM, PVMCPUCC pVCpu, RTGCPHYS GCPhys, void *pvPhys,
231	void *pvBuf, size_t cbBuf, PGMACCESSTYPE enmAccessType,
232	PGMACCESSORIGIN enmOrigin, void *pvUser));
233	/** Pointer to PGM access callback. */
234	typedef FNPGMPHYSHANDLER *PFNPGMPHYSHANDLER;
235
236
237	/**
238	* Paging mode.
239	*
240	* @note Part of saved state. Change with extreme care.
241	*/
242	typedef enum PGMMODE
243	{
244	/** The usual invalid value. */
245	PGMMODE_INVALID = 0,
246	/** Real mode. */
247	PGMMODE_REAL,
248	/** Protected mode, no paging. */
249	PGMMODE_PROTECTED,
250	/** 32-bit paging. */
251	PGMMODE_32_BIT,
252	/** PAE paging. */
253	PGMMODE_PAE,
254	/** PAE paging with NX enabled. */
255	PGMMODE_PAE_NX,
256	/** 64-bit AMD paging (long mode). */
257	PGMMODE_AMD64,
258	/** 64-bit AMD paging (long mode) with NX enabled. */
259	PGMMODE_AMD64_NX,
260	/** 32-bit nested paging mode (shadow only; guest physical to host physical). */
261	PGMMODE_NESTED_32BIT,
262	/** PAE nested paging mode (shadow only; guest physical to host physical). */
263	PGMMODE_NESTED_PAE,
264	/** AMD64 nested paging mode (shadow only; guest physical to host physical). */
265	PGMMODE_NESTED_AMD64,
266	/** Extended paging (Intel) mode. */
267	PGMMODE_EPT,
268	/** Special mode used by NEM to indicate no shadow paging necessary. */
269	PGMMODE_NONE,
270	/** The max number of modes */
271	PGMMODE_MAX,
272	/** 32bit hackishness. */
273	PGMMODE_32BIT_HACK = 0x7fffffff
274	} PGMMODE;
275
276	/**
277	* Second level address translation mode.
278	*/
279	typedef enum PGMSLAT
280	{
281	/** The usual invalid value. */
282	PGMSLAT_INVALID = 0,
283	/** No second level translation. */
284	PGMSLAT_DIRECT,
285	/** Intel Extended Page Tables (EPT). */
286	PGMSLAT_EPT,
287	/** AMD-V Nested Paging 32-bit. */
288	PGMSLAT_32BIT,
289	/** AMD-V Nested Paging PAE. */
290	PGMSLAT_PAE,
291	/** AMD-V Nested Paging 64-bit. */
292	PGMSLAT_AMD64,
293	/** 32bit hackishness. */
294	PGMSLAT_32BIT_HACK = 0x7fffffff
295	} PGMSLAT;
296
297	/** Macro for checking if the guest is using paging.
298	* @param enmMode PGMMODE_*.
299	* @remark ASSUMES certain order of the PGMMODE_* values.
300	*/
301	#define PGMMODE_WITH_PAGING(enmMode) ((enmMode) >= PGMMODE_32_BIT)
302
303	/** Macro for checking if it's one of the long mode modes.
304	* @param enmMode PGMMODE_*.
305	*/
306	#define PGMMODE_IS_LONG_MODE(enmMode) ((enmMode) == PGMMODE_AMD64_NX \|\| (enmMode) == PGMMODE_AMD64)
307
308	/** Macro for checking if it's one of the AMD64 nested modes.
309	* @param enmMode PGMMODE_*.
310	*/
311	#define PGMMODE_IS_NESTED(enmMode) ( (enmMode) == PGMMODE_NESTED_32BIT \
312	\|\| (enmMode) == PGMMODE_NESTED_PAE \
313	\|\| (enmMode) == PGMMODE_NESTED_AMD64)
314
315	/** Macro for checking if it's one of the PAE modes.
316	* @param enmMode PGMMODE_*.
317	*/
318	#define PGMMODE_IS_PAE(enmMode) ( (enmMode) == PGMMODE_PAE \
319	\|\| (enmMode) == PGMMODE_PAE_NX)
320
321	/**
322	* Is the ROM mapped (true) or is the shadow RAM mapped (false).
323	*
324	* @returns boolean.
325	* @param enmProt The PGMROMPROT value, must be valid.
326	*/
327	#define PGMROMPROT_IS_ROM(enmProt) \
328	( (enmProt) == PGMROMPROT_READ_ROM_WRITE_IGNORE \
329	\|\| (enmProt) == PGMROMPROT_READ_ROM_WRITE_RAM )
330
331
332	VMMDECL(bool) PGMIsLockOwner(PVMCC pVM);
333
334	VMMDECL(int) PGMRegisterStringFormatTypes(void);
335	VMMDECL(void) PGMDeregisterStringFormatTypes(void);
336	VMMDECL(RTHCPHYS) PGMGetHyperCR3(PVMCPU pVCpu);
337	VMMDECL(int) PGMTrap0eHandler(PVMCPUCC pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault);
338	VMMDECL(int) PGMPrefetchPage(PVMCPUCC pVCpu, RTGCPTR GCPtrPage);
339	VMMDECL(int) PGMVerifyAccess(PVMCPUCC pVCpu, RTGCPTR Addr, uint32_t cbSize, uint32_t fAccess);
340	VMMDECL(int) PGMIsValidAccess(PVMCPUCC pVCpu, RTGCPTR Addr, uint32_t cbSize, uint32_t fAccess);
341	VMMDECL(VBOXSTRICTRC) PGMInterpretInstruction(PVMCC pVM, PVMCPUCC pVCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault);
342	VMMDECL(int) PGMShwGetPage(PVMCPUCC pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys);
343	VMMDECL(int) PGMShwMakePageReadonly(PVMCPUCC pVCpu, RTGCPTR GCPtr, uint32_t fFlags);
344	VMMDECL(int) PGMShwMakePageWritable(PVMCPUCC pVCpu, RTGCPTR GCPtr, uint32_t fFlags);
345	VMMDECL(int) PGMShwMakePageNotPresent(PVMCPUCC pVCpu, RTGCPTR GCPtr, uint32_t fFlags);
346	/** @name Flags for PGMShwMakePageReadonly, PGMShwMakePageWritable and
347	* PGMShwMakePageNotPresent
348	* @{ */
349	/** The call is from an access handler for dealing with the a faulting write
350	* operation. The virtual address is within the same page. */
351	#define PGM_MK_PG_IS_WRITE_FAULT RT_BIT(0)
352	/** The page is an MMIO2. */
353	#define PGM_MK_PG_IS_MMIO2 RT_BIT(1)
354	/** @}*/
355	VMMDECL(int) PGMGstGetPage(PVMCPUCC pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys);
356	VMMDECL(bool) PGMGstIsPagePresent(PVMCPUCC pVCpu, RTGCPTR GCPtr);
357	VMMDECL(int) PGMGstSetPage(PVMCPUCC pVCpu, RTGCPTR GCPtr, size_t cb, uint64_t fFlags);
358	VMMDECL(int) PGMGstModifyPage(PVMCPUCC pVCpu, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask);
359	VMM_INT_DECL(bool) PGMGstArePaePdpesValid(PVMCPUCC pVCpu, PCX86PDPE paPaePdpes);
360	VMM_INT_DECL(int) PGMGstMapPaePdpes(PVMCPUCC pVCpu, PCX86PDPE paPaePdpes);
361	VMM_INT_DECL(int) PGMGstMapPaePdpesAtCr3(PVMCPUCC pVCpu, uint64_t cr3);
362
363	VMMDECL(int) PGMInvalidatePage(PVMCPUCC pVCpu, RTGCPTR GCPtrPage);
364	VMMDECL(int) PGMFlushTLB(PVMCPUCC pVCpu, uint64_t cr3, bool fGlobal, bool fPdpesMapped);
365	VMMDECL(int) PGMSyncCR3(PVMCPUCC pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal);
366	VMMDECL(int) PGMUpdateCR3(PVMCPUCC pVCpu, uint64_t cr3, bool fPdpesMapped);
367	VMMDECL(int) PGMChangeMode(PVMCPUCC pVCpu, uint64_t cr0, uint64_t cr4, uint64_t efer);
368	VMM_INT_DECL(int) PGMHCChangeMode(PVMCC pVM, PVMCPUCC pVCpu, PGMMODE enmGuestMode);
369	VMMDECL(void) PGMCr0WpEnabled(PVMCPUCC pVCpu);
370	VMMDECL(PGMMODE) PGMGetGuestMode(PVMCPU pVCpu);
371	VMMDECL(PGMMODE) PGMGetShadowMode(PVMCPU pVCpu);
372	VMMDECL(PGMMODE) PGMGetHostMode(PVM pVM);
373	VMMDECL(const char *) PGMGetModeName(PGMMODE enmMode);
374	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
375	VMM_INT_DECL(const char *) PGMGetSlatModeName(PGMSLAT enmSlatMode);
376	#endif
377	VMM_INT_DECL(RTGCPHYS) PGMGetGuestCR3Phys(PVMCPU pVCpu);
378	VMM_INT_DECL(void) PGMNotifyNxeChanged(PVMCPU pVCpu, bool fNxe);
379	VMMDECL(bool) PGMHasDirtyPages(PVM pVM);
380	VMM_INT_DECL(void) PGMSetGuestEptPtr(PVMCPUCC pVCpu, uint64_t uEptPtr);
381
382	/** PGM physical access handler type registration handle (heap offset, valid
383	* cross contexts without needing fixing up). Callbacks and handler type is
384	* associated with this and it is shared by all handler registrations. */
385	typedef uint32_t PGMPHYSHANDLERTYPE;
386	/** Pointer to a PGM physical handler type registration handle. */
387	typedef PGMPHYSHANDLERTYPE *PPGMPHYSHANDLERTYPE;
388	/** NIL value for PGM physical access handler type handle. */
389	#define NIL_PGMPHYSHANDLERTYPE UINT32_MAX
390	VMMDECL(uint32_t) PGMHandlerPhysicalTypeRelease(PVMCC pVM, PGMPHYSHANDLERTYPE hType);
391	VMMDECL(uint32_t) PGMHandlerPhysicalTypeRetain(PVM pVM, PGMPHYSHANDLERTYPE hType);
392
393	VMMDECL(int) PGMHandlerPhysicalRegister(PVMCC pVM, RTGCPHYS GCPhys, RTGCPHYS GCPhysLast, PGMPHYSHANDLERTYPE hType,
394	RTR3PTR pvUserR3, RTR0PTR pvUserR0, RTRCPTR pvUserRC,
395	R3PTRTYPE(const char *) pszDesc);
396	VMMDECL(int) PGMHandlerPhysicalModify(PVMCC pVM, RTGCPHYS GCPhysCurrent, RTGCPHYS GCPhys, RTGCPHYS GCPhysLast);
397	VMMDECL(int) PGMHandlerPhysicalDeregister(PVMCC pVM, RTGCPHYS GCPhys);
398	VMMDECL(int) PGMHandlerPhysicalChangeUserArgs(PVMCC pVM, RTGCPHYS GCPhys, RTR3PTR pvUserR3, RTR0PTR pvUserR0);
399	VMMDECL(int) PGMHandlerPhysicalSplit(PVMCC pVM, RTGCPHYS GCPhys, RTGCPHYS GCPhysSplit);
400	VMMDECL(int) PGMHandlerPhysicalJoin(PVMCC pVM, RTGCPHYS GCPhys1, RTGCPHYS GCPhys2);
401	VMMDECL(int) PGMHandlerPhysicalPageTempOff(PVMCC pVM, RTGCPHYS GCPhys, RTGCPHYS GCPhysPage);
402	VMMDECL(int) PGMHandlerPhysicalPageAliasMmio2(PVMCC pVM, RTGCPHYS GCPhys, RTGCPHYS GCPhysPage,
403	PPDMDEVINS pDevIns, PGMMMIO2HANDLE hMmio2, RTGCPHYS offMMio2PageRemap);
404	VMMDECL(int) PGMHandlerPhysicalPageAliasHC(PVMCC pVM, RTGCPHYS GCPhys, RTGCPHYS GCPhysPage, RTHCPHYS HCPhysPageRemap);
405	VMMDECL(int) PGMHandlerPhysicalReset(PVMCC pVM, RTGCPHYS GCPhys);
406	VMMDECL(bool) PGMHandlerPhysicalIsRegistered(PVMCC pVM, RTGCPHYS GCPhys);
407
408
409	/**
410	* Page type.
411	*
412	* @remarks This enum has to fit in a 3-bit field (see PGMPAGE::u3Type).
413	* @remarks This is used in the saved state, so changes to it requires bumping
414	* the saved state version.
415	* @todo So, convert to \#defines!
416	*/
417	typedef enum PGMPAGETYPE
418	{
419	/** The usual invalid zero entry. */
420	PGMPAGETYPE_INVALID = 0,
421	/** RAM page. (RWX) */
422	PGMPAGETYPE_RAM,
423	/** MMIO2 page. (RWX) */
424	PGMPAGETYPE_MMIO2,
425	/** MMIO2 page aliased over an MMIO page. (RWX)
426	* See PGMHandlerPhysicalPageAlias(). */
427	PGMPAGETYPE_MMIO2_ALIAS_MMIO,
428	/** Special page aliased over an MMIO page. (RWX)
429	* See PGMHandlerPhysicalPageAliasHC(), but this is generally only used for
430	* VT-x's APIC access page at the moment. Treated as MMIO by everyone except
431	* the shadow paging code. */
432	PGMPAGETYPE_SPECIAL_ALIAS_MMIO,
433	/** Shadowed ROM. (RWX) */
434	PGMPAGETYPE_ROM_SHADOW,
435	/** ROM page. (R-X) */
436	PGMPAGETYPE_ROM,
437	/** MMIO page. (---) */
438	PGMPAGETYPE_MMIO,
439	/** End of valid entries. */
440	PGMPAGETYPE_END
441	} PGMPAGETYPE;
442	AssertCompile(PGMPAGETYPE_END == 8);
443
444	/** @name PGM page type predicates.
445	* @{ */
446	#define PGMPAGETYPE_IS_READABLE(a_enmType) ( (a_enmType) <= PGMPAGETYPE_ROM )
447	#define PGMPAGETYPE_IS_WRITEABLE(a_enmType) ( (a_enmType) <= PGMPAGETYPE_ROM_SHADOW )
448	#define PGMPAGETYPE_IS_RWX(a_enmType) ( (a_enmType) <= PGMPAGETYPE_ROM_SHADOW )
449	#define PGMPAGETYPE_IS_ROX(a_enmType) ( (a_enmType) == PGMPAGETYPE_ROM )
450	#define PGMPAGETYPE_IS_NP(a_enmType) ( (a_enmType) == PGMPAGETYPE_MMIO )
451	/** @} */
452
453
454	VMM_INT_DECL(PGMPAGETYPE) PGMPhysGetPageType(PVMCC pVM, RTGCPHYS GCPhys);
455
456	VMM_INT_DECL(int) PGMPhysGCPhys2HCPhys(PVMCC pVM, RTGCPHYS GCPhys, PRTHCPHYS pHCPhys);
457	VMM_INT_DECL(int) PGMPhysGCPtr2HCPhys(PVMCPUCC pVCpu, RTGCPTR GCPtr, PRTHCPHYS pHCPhys);
458	VMM_INT_DECL(int) PGMPhysGCPhys2CCPtr(PVMCC pVM, RTGCPHYS GCPhys, void **ppv, PPGMPAGEMAPLOCK pLock);
459	VMM_INT_DECL(int) PGMPhysGCPhys2CCPtrReadOnly(PVMCC pVM, RTGCPHYS GCPhys, void const **ppv, PPGMPAGEMAPLOCK pLock);
460	VMM_INT_DECL(int) PGMPhysGCPtr2CCPtr(PVMCPU pVCpu, RTGCPTR GCPtr, void **ppv, PPGMPAGEMAPLOCK pLock);
461	VMM_INT_DECL(int) PGMPhysGCPtr2CCPtrReadOnly(PVMCPUCC pVCpu, RTGCPTR GCPtr, void const **ppv, PPGMPAGEMAPLOCK pLock);
462
463	VMMDECL(bool) PGMPhysIsA20Enabled(PVMCPU pVCpu);
464	VMMDECL(bool) PGMPhysIsGCPhysValid(PVMCC pVM, RTGCPHYS GCPhys);
465	VMMDECL(bool) PGMPhysIsGCPhysNormal(PVMCC pVM, RTGCPHYS GCPhys);
466	VMMDECL(int) PGMPhysGCPtr2GCPhys(PVMCPUCC pVCpu, RTGCPTR GCPtr, PRTGCPHYS pGCPhys);
467	VMMDECL(void) PGMPhysReleasePageMappingLock(PVMCC pVM, PPGMPAGEMAPLOCK pLock);
468	VMMDECL(void) PGMPhysBulkReleasePageMappingLocks(PVMCC pVM, uint32_t cPages, PPGMPAGEMAPLOCK paLock);
469
470	/** @def PGM_PHYS_RW_IS_SUCCESS
471	* Check whether a PGMPhysRead, PGMPhysWrite, PGMPhysReadGCPtr or
472	* PGMPhysWriteGCPtr call completed the given task.
473	*
474	* @returns true if completed, false if not.
475	* @param a_rcStrict The status code.
476	* @sa IOM_SUCCESS
477	*/
478	#ifdef IN_RING3
479	# define PGM_PHYS_RW_IS_SUCCESS(a_rcStrict) \
480	( (a_rcStrict) == VINF_SUCCESS \
481	\|\| (a_rcStrict) == VINF_EM_DBG_STOP \
482	\|\| (a_rcStrict) == VINF_EM_DBG_EVENT \
483	\|\| (a_rcStrict) == VINF_EM_DBG_BREAKPOINT \
484	)
485	#elif defined(IN_RING0)
486	# define PGM_PHYS_RW_IS_SUCCESS(a_rcStrict) \
487	( (a_rcStrict) == VINF_SUCCESS \
488	\|\| (a_rcStrict) == VINF_IOM_R3_MMIO_COMMIT_WRITE \
489	\|\| (a_rcStrict) == VINF_EM_OFF \
490	\|\| (a_rcStrict) == VINF_EM_SUSPEND \
491	\|\| (a_rcStrict) == VINF_EM_RESET \
492	\|\| (a_rcStrict) == VINF_EM_HALT \
493	\|\| (a_rcStrict) == VINF_EM_DBG_STOP \
494	\|\| (a_rcStrict) == VINF_EM_DBG_EVENT \
495	\|\| (a_rcStrict) == VINF_EM_DBG_BREAKPOINT \
496	)
497	#elif defined(IN_RC)
498	# define PGM_PHYS_RW_IS_SUCCESS(a_rcStrict) \
499	( (a_rcStrict) == VINF_SUCCESS \
500	\|\| (a_rcStrict) == VINF_IOM_R3_MMIO_COMMIT_WRITE \
501	\|\| (a_rcStrict) == VINF_EM_OFF \
502	\|\| (a_rcStrict) == VINF_EM_SUSPEND \
503	\|\| (a_rcStrict) == VINF_EM_RESET \
504	\|\| (a_rcStrict) == VINF_EM_HALT \
505	\|\| (a_rcStrict) == VINF_SELM_SYNC_GDT \
506	\|\| (a_rcStrict) == VINF_EM_RAW_EMULATE_INSTR_GDT_FAULT \
507	\|\| (a_rcStrict) == VINF_EM_DBG_STOP \
508	\|\| (a_rcStrict) == VINF_EM_DBG_EVENT \
509	\|\| (a_rcStrict) == VINF_EM_DBG_BREAKPOINT \
510	)
511	#endif
512	/** @def PGM_PHYS_RW_DO_UPDATE_STRICT_RC
513	* Updates the return code with a new result.
514	*
515	* Both status codes must be successes according to PGM_PHYS_RW_IS_SUCCESS.
516	*
517	* @param a_rcStrict The current return code, to be updated.
518	* @param a_rcStrict2 The new return code to merge in.
519	*/
520	#ifdef IN_RING3
521	# define PGM_PHYS_RW_DO_UPDATE_STRICT_RC(a_rcStrict, a_rcStrict2) \
522	do { \
523	Assert(rcStrict == VINF_SUCCESS); \
524	Assert(rcStrict2 == VINF_SUCCESS); \
525	} while (0)
526	#elif defined(IN_RING0)
527	# define PGM_PHYS_RW_DO_UPDATE_STRICT_RC(a_rcStrict, a_rcStrict2) \
528	do { \
529	Assert(PGM_PHYS_RW_IS_SUCCESS(rcStrict)); \
530	Assert(PGM_PHYS_RW_IS_SUCCESS(rcStrict2)); \
531	AssertCompile(VINF_IOM_R3_MMIO_COMMIT_WRITE > VINF_EM_LAST); \
532	if ((a_rcStrict2) == VINF_SUCCESS \|\| (a_rcStrict) == (a_rcStrict2)) \
533	{ /* likely */ } \
534	else if ( (a_rcStrict) == VINF_SUCCESS \
535	\|\| (a_rcStrict) > (a_rcStrict2)) \
536	(a_rcStrict) = (a_rcStrict2); \
537	} while (0)
538	#elif defined(IN_RC)
539	# define PGM_PHYS_RW_DO_UPDATE_STRICT_RC(a_rcStrict, a_rcStrict2) \
540	do { \
541	Assert(PGM_PHYS_RW_IS_SUCCESS(rcStrict)); \
542	Assert(PGM_PHYS_RW_IS_SUCCESS(rcStrict2)); \
543	AssertCompile(VINF_SELM_SYNC_GDT > VINF_EM_LAST); \
544	AssertCompile(VINF_EM_RAW_EMULATE_INSTR_GDT_FAULT > VINF_EM_LAST); \
545	AssertCompile(VINF_EM_RAW_EMULATE_INSTR_GDT_FAULT < VINF_SELM_SYNC_GDT); \
546	AssertCompile(VINF_IOM_R3_MMIO_COMMIT_WRITE > VINF_EM_LAST); \
547	AssertCompile(VINF_IOM_R3_MMIO_COMMIT_WRITE > VINF_SELM_SYNC_GDT); \
548	AssertCompile(VINF_IOM_R3_MMIO_COMMIT_WRITE > VINF_EM_RAW_EMULATE_INSTR_GDT_FAULT); \
549	if ((a_rcStrict2) == VINF_SUCCESS \|\| (a_rcStrict) == (a_rcStrict2)) \
550	{ /* likely */ } \
551	else if ((a_rcStrict) == VINF_SUCCESS) \
552	(a_rcStrict) = (a_rcStrict2); \
553	else if ( ( (a_rcStrict) > (a_rcStrict2) \
554	&& ( (a_rcStrict2) <= VINF_EM_RESET \
555	\|\| (a_rcStrict) != VINF_EM_RAW_EMULATE_INSTR_GDT_FAULT) ) \
556	\|\| ( (a_rcStrict2) == VINF_EM_RAW_EMULATE_INSTR_GDT_FAULT \
557	&& (a_rcStrict) > VINF_EM_RESET) ) \
558	(a_rcStrict) = (a_rcStrict2); \
559	} while (0)
560	#endif
561
562	VMMDECL(VBOXSTRICTRC) PGMPhysRead(PVMCC pVM, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead, PGMACCESSORIGIN enmOrigin);
563	VMMDECL(VBOXSTRICTRC) PGMPhysWrite(PVMCC pVM, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite, PGMACCESSORIGIN enmOrigin);
564	VMMDECL(VBOXSTRICTRC) PGMPhysReadGCPtr(PVMCPUCC pVCpu, void *pvDst, RTGCPTR GCPtrSrc, size_t cb, PGMACCESSORIGIN enmOrigin);
565	VMMDECL(VBOXSTRICTRC) PGMPhysWriteGCPtr(PVMCPUCC pVCpu, RTGCPTR GCPtrDst, const void *pvSrc, size_t cb, PGMACCESSORIGIN enmOrigin);
566
567	VMMDECL(int) PGMPhysSimpleReadGCPhys(PVMCC pVM, void *pvDst, RTGCPHYS GCPhysSrc, size_t cb);
568	VMMDECL(int) PGMPhysSimpleWriteGCPhys(PVMCC pVM, RTGCPHYS GCPhysDst, const void *pvSrc, size_t cb);
569	VMMDECL(int) PGMPhysSimpleReadGCPtr(PVMCPUCC pVCpu, void *pvDst, RTGCPTR GCPtrSrc, size_t cb);
570	VMMDECL(int) PGMPhysSimpleWriteGCPtr(PVMCPUCC pVCpu, RTGCPTR GCPtrDst, const void *pvSrc, size_t cb);
571	VMMDECL(int) PGMPhysSimpleDirtyWriteGCPtr(PVMCPUCC pVCpu, RTGCPTR GCPtrDst, const void *pvSrc, size_t cb);
572	VMMDECL(int) PGMPhysInterpretedRead(PVMCPUCC pVCpu, PCPUMCTXCORE pCtxCore, void *pvDst, RTGCPTR GCPtrSrc, size_t cb);
573	VMMDECL(int) PGMPhysInterpretedReadNoHandlers(PVMCPUCC pVCpu, PCPUMCTXCORE pCtxCore, void *pvDst, RTGCUINTPTR GCPtrSrc, size_t cb, bool fRaiseTrap);
574	VMMDECL(int) PGMPhysInterpretedWriteNoHandlers(PVMCPUCC pVCpu, PCPUMCTXCORE pCtxCore, RTGCPTR GCPtrDst, void const *pvSrc, size_t cb, bool fRaiseTrap);
575
576	VMM_INT_DECL(int) PGMPhysIemGCPhys2Ptr(PVMCC pVM, PVMCPUCC pVCpu, RTGCPHYS GCPhys, bool fWritable, bool fByPassHandlers, void **ppv, PPGMPAGEMAPLOCK pLock);
577	VMM_INT_DECL(int) PGMPhysIemQueryAccess(PVMCC pVM, RTGCPHYS GCPhys, bool fWritable, bool fByPassHandlers);
578	VMM_INT_DECL(int) PGMPhysIemGCPhys2PtrNoLock(PVMCC pVM, PVMCPUCC pVCpu, RTGCPHYS GCPhys, uint64_t const volatile *puTlbPhysRev,
579	#if defined(IN_RC)
580	R3PTRTYPE(uint8_t ) ppb,
581	#else
582	R3R0PTRTYPE(uint8_t ) ppb,
583	#endif
584	uint64_t *pfTlb);
585	/** @name Flags returned by PGMPhysIemGCPhys2PtrNoLock
586	* @{ */
587	#define PGMIEMGCPHYS2PTR_F_NO_WRITE RT_BIT_32(3) /*< Not writable (IEMTLBE_F_PG_NO_WRITE). /
588	#define PGMIEMGCPHYS2PTR_F_NO_READ RT_BIT_32(4) /*< Not readable (IEMTLBE_F_PG_NO_READ). /
589	#define PGMIEMGCPHYS2PTR_F_NO_MAPPINGR3 RT_BIT_32(7) /*< No ring-3 mapping (IEMTLBE_F_NO_MAPPINGR3). /
590	/** @} */
591
592	/** Information returned by PGMPhysNemQueryPageInfo. */
593	typedef struct PGMPHYSNEMPAGEINFO
594	{
595	/** The host physical address of the page, NIL_HCPHYS if invalid page. */
596	RTHCPHYS HCPhys;
597	/** The NEM access mode for the page, NEM_PAGE_PROT_XXX */
598	uint32_t fNemProt : 8;
599	/** The NEM state associated with the PAGE. */
600	uint32_t u2NemState : 2;
601	/** The NEM state associated with the PAGE before pgmPhysPageMakeWritable was called. */
602	uint32_t u2OldNemState : 2;
603	/** Set if the page has handler. */
604	uint32_t fHasHandlers : 1;
605	/** Set if is the zero page backing it. */
606	uint32_t fZeroPage : 1;
607	/** Set if the page has handler. */
608	PGMPAGETYPE enmType;
609	} PGMPHYSNEMPAGEINFO;
610	/** Pointer to page information for NEM. */
611	typedef PGMPHYSNEMPAGEINFO *PPGMPHYSNEMPAGEINFO;
612	/**
613	* Callback for checking that the page is in sync while under the PGM lock.
614	*
615	* NEM passes this callback to PGMPhysNemQueryPageInfo to check that the page is
616	* in-sync between PGM and the native hypervisor API in an atomic fashion.
617	*
618	* @returns VBox status code.
619	* @param pVM The cross context VM structure.
620	* @param pVCpu The cross context per virtual CPU structure. Optional,
621	* see PGMPhysNemQueryPageInfo.
622	* @param GCPhys The guest physical address (not A20 masked).
623	* @param pInfo The page info structure. This function updates the
624	* u2NemState memory and the caller will update the PGMPAGE
625	* copy accordingly.
626	* @param pvUser Callback user argument.
627	*/
628	typedef DECLCALLBACKTYPE(int, FNPGMPHYSNEMCHECKPAGE,(PVMCC pVM, PVMCPUCC pVCpu, RTGCPHYS GCPhys, PPGMPHYSNEMPAGEINFO pInfo, void *pvUser));
629	/** Pointer to a FNPGMPHYSNEMCHECKPAGE function. */
630	typedef FNPGMPHYSNEMCHECKPAGE *PFNPGMPHYSNEMCHECKPAGE;
631
632	VMM_INT_DECL(int) PGMPhysNemPageInfoChecker(PVMCC pVM, PVMCPUCC pVCpu, RTGCPHYS GCPhys, bool fMakeWritable,
633	PPGMPHYSNEMPAGEINFO pInfo, PFNPGMPHYSNEMCHECKPAGE pfnChecker, void *pvUser);
634
635	/**
636	* Callback for use with PGMPhysNemEnumPagesByState.
637	* @returns VBox status code.
638	* Failure status will stop enumeration immediately and return.
639	* @param pVM The cross context VM structure.
640	* @param pVCpu The cross context per virtual CPU structure. Optional,
641	* see PGMPhysNemEnumPagesByState.
642	* @param GCPhys The guest physical address (not A20 masked).
643	* @param pu2NemState Pointer to variable with the NEM state. This can be
644	* update.
645	* @param pvUser The user argument.
646	*/
647	typedef DECLCALLBACKTYPE(int, FNPGMPHYSNEMENUMCALLBACK,(PVMCC pVM, PVMCPUCC pVCpu, RTGCPHYS GCPhys,
648	uint8_t pu2NemState, void pvUser));
649	/** Pointer to a FNPGMPHYSNEMENUMCALLBACK function. */
650	typedef FNPGMPHYSNEMENUMCALLBACK *PFNPGMPHYSNEMENUMCALLBACK;
651	VMM_INT_DECL(int) PGMPhysNemEnumPagesByState(PVMCC pVM, PVMCPUCC VCpu, uint8_t uMinState,
652	PFNPGMPHYSNEMENUMCALLBACK pfnCallback, void *pvUser);
653
654
655	#ifdef VBOX_STRICT
656	VMMDECL(unsigned) PGMAssertHandlerAndFlagsInSync(PVMCC pVM);
657	VMMDECL(unsigned) PGMAssertNoMappingConflicts(PVM pVM);
658	VMMDECL(unsigned) PGMAssertCR3(PVMCC pVM, PVMCPUCC pVCpu, uint64_t cr3, uint64_t cr4);
659	#endif /* VBOX_STRICT */
660
661	VMMDECL(int) PGMSetLargePageUsage(PVMCC pVM, bool fUseLargePages);
662
663	/**
664	* Query large page usage state
665	*
666	* @returns 0 - disabled, 1 - enabled
667	* @param pVM The cross context VM structure.
668	*/
669	#define PGMIsUsingLargePages(pVM) ((pVM)->pgm.s.fUseLargePages)
670
671
672	#ifdef IN_RING0
673	/** @defgroup grp_pgm_r0 The PGM Host Context Ring-0 API
674	* @{
675	*/
676	VMMR0_INT_DECL(int) PGMR0InitPerVMData(PGVM pGVM);
677	VMMR0_INT_DECL(int) PGMR0InitVM(PGVM pGVM);
678	VMMR0_INT_DECL(void) PGMR0CleanupVM(PGVM pGVM);
679	VMMR0_INT_DECL(int) PGMR0PhysAllocateHandyPages(PGVM pGVM, VMCPUID idCpu);
680	VMMR0_INT_DECL(int) PGMR0PhysFlushHandyPages(PGVM pGVM, VMCPUID idCpu);
681	VMMR0_INT_DECL(int) PGMR0PhysAllocateLargeHandyPage(PGVM pGVM, VMCPUID idCpu);
682	VMMR0_INT_DECL(int) PGMR0PhysMMIO2MapKernel(PGVM pGVM, PPDMDEVINS pDevIns, PGMMMIO2HANDLE hMmio2,
683	size_t offSub, size_t cbSub, void **ppvMapping);
684	VMMR0_INT_DECL(int) PGMR0PhysSetupIoMmu(PGVM pGVM);
685	VMMR0DECL(int) PGMR0SharedModuleCheck(PVMCC pVM, PGVM pGVM, VMCPUID idCpu, PGMMSHAREDMODULE pModule,
686	PCRTGCPTR64 paRegionsGCPtrs);
687	VMMR0DECL(int) PGMR0Trap0eHandlerNestedPaging(PGVM pGVM, PGVMCPU pGVCpu, PGMMODE enmShwPagingMode, RTGCUINT uErr,
688	PCPUMCTXCORE pRegFrame, RTGCPHYS pvFault);
689	VMMR0DECL(VBOXSTRICTRC) PGMR0Trap0eHandlerNPMisconfig(PGVM pGVM, PGVMCPU pGVCpu, PGMMODE enmShwPagingMode,
690	PCPUMCTXCORE pRegFrame, RTGCPHYS GCPhysFault, uint32_t uErr);
691	VMMR0_INT_DECL(int) PGMR0PoolGrow(PGVM pGVM, VMCPUID idCpu);
692	/** @} */
693	#endif /* IN_RING0 */
694
695
696
697	#ifdef IN_RING3
698	/** @defgroup grp_pgm_r3 The PGM Host Context Ring-3 API
699	* @{
700	*/
701	VMMR3_INT_DECL(void) PGMR3EnableNemMode(PVM pVM);
702	VMMR3DECL(int) PGMR3Init(PVM pVM);
703	VMMR3DECL(int) PGMR3InitFinalize(PVM pVM);
704	VMMR3_INT_DECL(int) PGMR3InitCompleted(PVM pVM, VMINITCOMPLETED enmWhat);
705	VMMR3DECL(void) PGMR3Relocate(PVM pVM, RTGCINTPTR offDelta);
706	VMMR3DECL(void) PGMR3ResetCpu(PVM pVM, PVMCPU pVCpu);
707	VMMR3_INT_DECL(void) PGMR3Reset(PVM pVM);
708	VMMR3_INT_DECL(void) PGMR3ResetNoMorePhysWritesFlag(PVM pVM);
709	VMMR3_INT_DECL(void) PGMR3MemSetup(PVM pVM, bool fReset);
710	VMMR3DECL(int) PGMR3Term(PVM pVM);
711
712	VMMR3DECL(int) PGMR3PhysRegisterRam(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, const char *pszDesc);
713	VMMR3DECL(int) PGMR3PhysChangeMemBalloon(PVM pVM, bool fInflate, unsigned cPages, RTGCPHYS *paPhysPage);
714	VMMR3DECL(int) PGMR3PhysWriteProtectRAM(PVM pVM);
715	VMMR3DECL(uint32_t) PGMR3PhysGetRamRangeCount(PVM pVM);
716	VMMR3DECL(int) PGMR3PhysGetRange(PVM pVM, uint32_t iRange, PRTGCPHYS pGCPhysStart, PRTGCPHYS pGCPhysLast,
717	const char *ppszDesc, bool pfIsMmio);
718	VMMR3DECL(int) PGMR3QueryMemoryStats(PUVM pUVM, uint64_t pcbTotalMem, uint64_t pcbPrivateMem, uint64_t pcbSharedMem, uint64_t pcbZeroMem);
719	VMMR3DECL(int) PGMR3QueryGlobalMemoryStats(PUVM pUVM, uint64_t pcbAllocMem, uint64_t pcbFreeMem, uint64_t pcbBallonedMem, uint64_t pcbSharedMem);
720
721	VMMR3DECL(int) PGMR3PhysMMIORegister(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, PGMPHYSHANDLERTYPE hType,
722	RTR3PTR pvUserR3, RTR0PTR pvUserR0, RTRCPTR pvUserRC, const char *pszDesc);
723	VMMR3DECL(int) PGMR3PhysMMIODeregister(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb);
724
725	/** @name PGMPHYS_MMIO2_FLAGS_XXX - MMIO2 registration flags.
726	* @see PGMR3PhysMmio2Register, PDMDevHlpMmio2Create
727	* @{ */
728	/** Track dirty pages.
729	* @see PGMR3PhysMmio2QueryAndResetDirtyBitmap(), PGMR3PhysMmio2ControlDirtyPageTracking(). */
730	#define PGMPHYS_MMIO2_FLAGS_TRACK_DIRTY_PAGES RT_BIT_32(0)
731	/** Valid flags. */
732	#define PGMPHYS_MMIO2_FLAGS_VALID_MASK UINT32_C(0x00000001)
733	/** @} */
734
735	VMMR3_INT_DECL(int) PGMR3PhysMmio2Register(PVM pVM, PPDMDEVINS pDevIns, uint32_t iSubDev, uint32_t iRegion, RTGCPHYS cb,
736	uint32_t fFlags, const char pszDesc, void ppv, PGMMMIO2HANDLE phRegion);
737	VMMR3_INT_DECL(int) PGMR3PhysMmio2Deregister(PVM pVM, PPDMDEVINS pDevIns, PGMMMIO2HANDLE hMmio2);
738	VMMR3_INT_DECL(int) PGMR3PhysMmio2Map(PVM pVM, PPDMDEVINS pDevIns, PGMMMIO2HANDLE hMmio2, RTGCPHYS GCPhys);
739	VMMR3_INT_DECL(int) PGMR3PhysMmio2Unmap(PVM pVM, PPDMDEVINS pDevIns, PGMMMIO2HANDLE hMmio2, RTGCPHYS GCPhys);
740	VMMR3_INT_DECL(int) PGMR3PhysMmio2Reduce(PVM pVM, PPDMDEVINS pDevIns, PGMMMIO2HANDLE hMmio2, RTGCPHYS cbRegion);
741	VMMR3_INT_DECL(int) PGMR3PhysMmio2ValidateHandle(PVM pVM, PPDMDEVINS pDevIns, PGMMMIO2HANDLE hMmio2);
742	VMMR3_INT_DECL(RTGCPHYS) PGMR3PhysMmio2GetMappingAddress(PVM pVM, PPDMDEVINS pDevIns, PGMMMIO2HANDLE hMmio2);
743	VMMR3_INT_DECL(int) PGMR3PhysMmio2ChangeRegionNo(PVM pVM, PPDMDEVINS pDevIns, PGMMMIO2HANDLE hMmio2, uint32_t iNewRegion);
744	VMMR3_INT_DECL(int) PGMR3PhysMmio2QueryAndResetDirtyBitmap(PVM pVM, PPDMDEVINS pDevIns, PGMMMIO2HANDLE hMmio2,
745	void *pvBitmap, size_t cbBitmap);
746	VMMR3_INT_DECL(int) PGMR3PhysMmio2ControlDirtyPageTracking(PVM pVM, PPDMDEVINS pDevIns, PGMMMIO2HANDLE hMmio2, bool fEnabled);
747
748	/** @name PGMPHYS_ROM_FLAGS_XXX - ROM registration flags.
749	* @see PGMR3PhysRegisterRom, PDMDevHlpROMRegister
750	* @{ */
751	/** Inidicates that ROM shadowing should be enabled. */
752	#define PGMPHYS_ROM_FLAGS_SHADOWED UINT8_C(0x01)
753	/** Indicates that what pvBinary points to won't go away
754	* and can be used for strictness checks. */
755	#define PGMPHYS_ROM_FLAGS_PERMANENT_BINARY UINT8_C(0x02)
756	/** Indicates that the ROM is allowed to be missing from saved state.
757	* @note This is a hack for EFI, see @bugref{6940} */
758	#define PGMPHYS_ROM_FLAGS_MAYBE_MISSING_FROM_STATE UINT8_C(0x04)
759	/** Valid flags. */
760	#define PGMPHYS_ROM_FLAGS_VALID_MASK UINT8_C(0x07)
761	/** @} */
762
763	VMMR3DECL(int) PGMR3PhysRomRegister(PVM pVM, PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTGCPHYS cb,
764	const void pvBinary, uint32_t cbBinary, uint8_t fFlags, const char pszDesc);
765	VMMR3DECL(int) PGMR3PhysRomProtect(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, PGMROMPROT enmProt);
766	VMMDECL(void) PGMR3PhysSetA20(PVMCPU pVCpu, bool fEnable);
767
768	VMMR3_INT_DECL(int) PGMR3HandlerPhysicalTypeRegisterEx(PVM pVM, PGMPHYSHANDLERKIND enmKind, bool fKeepPgmLock,
769	PFNPGMPHYSHANDLER pfnHandlerR3,
770	R0PTRTYPE(PFNPGMPHYSHANDLER) pfnHandlerR0,
771	R0PTRTYPE(PFNPGMRZPHYSPFHANDLER) pfnPfHandlerR0,
772	const char *pszDesc, PPGMPHYSHANDLERTYPE phType);
773	VMMR3DECL(int) PGMR3HandlerPhysicalTypeRegister(PVM pVM, PGMPHYSHANDLERKIND enmKind, bool fKeepPgmLock,
774	R3PTRTYPE(PFNPGMPHYSHANDLER) pfnHandlerR3,
775	const char pszModR0, const char pszHandlerR0, const char *pszPfHandlerR0,
776	const char pszModRC, const char pszHandlerRC, const char *pszPfHandlerRC,
777	const char *pszDesc,
778	PPGMPHYSHANDLERTYPE phType);
779	VMMR3_INT_DECL(int) PGMR3PoolGrow(PVM pVM, PVMCPU pVCpu);
780
781	VMMR3DECL(int) PGMR3PhysTlbGCPhys2Ptr(PVM pVM, RTGCPHYS GCPhys, bool fWritable, void **ppv);
782	VMMR3DECL(uint8_t) PGMR3PhysReadU8(PVM pVM, RTGCPHYS GCPhys, PGMACCESSORIGIN enmOrigin);
783	VMMR3DECL(uint16_t) PGMR3PhysReadU16(PVM pVM, RTGCPHYS GCPhys, PGMACCESSORIGIN enmOrigin);
784	VMMR3DECL(uint32_t) PGMR3PhysReadU32(PVM pVM, RTGCPHYS GCPhys, PGMACCESSORIGIN enmOrigin);
785	VMMR3DECL(uint64_t) PGMR3PhysReadU64(PVM pVM, RTGCPHYS GCPhys, PGMACCESSORIGIN enmOrigin);
786	VMMR3DECL(void) PGMR3PhysWriteU8(PVM pVM, RTGCPHYS GCPhys, uint8_t Value, PGMACCESSORIGIN enmOrigin);
787	VMMR3DECL(void) PGMR3PhysWriteU16(PVM pVM, RTGCPHYS GCPhys, uint16_t Value, PGMACCESSORIGIN enmOrigin);
788	VMMR3DECL(void) PGMR3PhysWriteU32(PVM pVM, RTGCPHYS GCPhys, uint32_t Value, PGMACCESSORIGIN enmOrigin);
789	VMMR3DECL(void) PGMR3PhysWriteU64(PVM pVM, RTGCPHYS GCPhys, uint64_t Value, PGMACCESSORIGIN enmOrigin);
790	VMMR3DECL(int) PGMR3PhysReadExternal(PVM pVM, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead, PGMACCESSORIGIN enmOrigin);
791	VMMR3DECL(int) PGMR3PhysWriteExternal(PVM pVM, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite, PGMACCESSORIGIN enmOrigin);
792	VMMR3DECL(int) PGMR3PhysGCPhys2CCPtrExternal(PVM pVM, RTGCPHYS GCPhys, void **ppv, PPGMPAGEMAPLOCK pLock);
793	VMMR3DECL(int) PGMR3PhysGCPhys2CCPtrReadOnlyExternal(PVM pVM, RTGCPHYS GCPhys, void const **ppv, PPGMPAGEMAPLOCK pLock);
794	VMMR3DECL(int) PGMR3PhysBulkGCPhys2CCPtrExternal(PVM pVM, uint32_t cPages, PCRTGCPHYS paGCPhysPages,
795	void **papvPages, PPGMPAGEMAPLOCK paLocks);
796	VMMR3DECL(int) PGMR3PhysBulkGCPhys2CCPtrReadOnlyExternal(PVM pVM, uint32_t cPages, PCRTGCPHYS paGCPhysPages,
797	void const **papvPages, PPGMPAGEMAPLOCK paLocks);
798	VMMR3DECL(void) PGMR3PhysChunkInvalidateTLB(PVM pVM);
799	VMMR3DECL(int) PGMR3PhysAllocateHandyPages(PVM pVM);
800	VMMR3_INT_DECL(int) PGMR3PhysAllocateLargePage(PVM pVM, RTGCPHYS GCPhys);
801
802	VMMR3DECL(int) PGMR3CheckIntegrity(PVM pVM);
803
804	VMMR3DECL(int) PGMR3DbgR3Ptr2GCPhys(PUVM pUVM, RTR3PTR R3Ptr, PRTGCPHYS pGCPhys);
805	VMMR3DECL(int) PGMR3DbgR3Ptr2HCPhys(PUVM pUVM, RTR3PTR R3Ptr, PRTHCPHYS pHCPhys);
806	VMMR3DECL(int) PGMR3DbgHCPhys2GCPhys(PUVM pUVM, RTHCPHYS HCPhys, PRTGCPHYS pGCPhys);
807	VMMR3_INT_DECL(int) PGMR3DbgReadGCPhys(PVM pVM, void pvDst, RTGCPHYS GCPhysSrc, size_t cb, uint32_t fFlags, size_t pcbRead);
808	VMMR3_INT_DECL(int) PGMR3DbgWriteGCPhys(PVM pVM, RTGCPHYS GCPhysDst, const void pvSrc, size_t cb, uint32_t fFlags, size_t pcbWritten);
809	VMMR3_INT_DECL(int) PGMR3DbgReadGCPtr(PVM pVM, void pvDst, RTGCPTR GCPtrSrc, size_t cb, uint32_t fFlags, size_t pcbRead);
810	VMMR3_INT_DECL(int) PGMR3DbgWriteGCPtr(PVM pVM, RTGCPTR GCPtrDst, void const pvSrc, size_t cb, uint32_t fFlags, size_t pcbWritten);
811	VMMR3_INT_DECL(int) PGMR3DbgScanPhysical(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cbRange, RTGCPHYS GCPhysAlign, const uint8_t *pabNeedle, size_t cbNeedle, PRTGCPHYS pGCPhysHit);
812	VMMR3_INT_DECL(int) PGMR3DbgScanVirtual(PVM pVM, PVMCPU pVCpu, RTGCPTR GCPtr, RTGCPTR cbRange, RTGCPTR GCPtrAlign, const uint8_t *pabNeedle, size_t cbNeedle, PRTGCUINTPTR pGCPhysHit);
813	VMMR3_INT_DECL(int) PGMR3DumpHierarchyShw(PVM pVM, uint64_t cr3, uint32_t fFlags, uint64_t u64FirstAddr, uint64_t u64LastAddr, uint32_t cMaxDepth, PCDBGFINFOHLP pHlp);
814	VMMR3_INT_DECL(int) PGMR3DumpHierarchyGst(PVM pVM, uint64_t cr3, uint32_t fFlags, RTGCPTR FirstAddr, RTGCPTR LastAddr, uint32_t cMaxDepth, PCDBGFINFOHLP pHlp);
815
816
817	/** @name Page sharing
818	* @{ */
819	VMMR3DECL(int) PGMR3SharedModuleRegister(PVM pVM, VBOXOSFAMILY enmGuestOS, char pszModuleName, char pszVersion,
820	RTGCPTR GCBaseAddr, uint32_t cbModule,
821	uint32_t cRegions, VMMDEVSHAREDREGIONDESC const *paRegions);
822	VMMR3DECL(int) PGMR3SharedModuleUnregister(PVM pVM, char pszModuleName, char pszVersion,
823	RTGCPTR GCBaseAddr, uint32_t cbModule);
824	VMMR3DECL(int) PGMR3SharedModuleCheckAll(PVM pVM);
825	VMMR3DECL(int) PGMR3SharedModuleGetPageState(PVM pVM, RTGCPTR GCPtrPage, bool pfShared, uint64_t pfPageFlags);
826	/** @} */
827
828	/** @} */
829	#endif /* IN_RING3 */
830
831	RT_C_DECLS_END
832
833	/** @} */
834	#endif /* !VBOX_INCLUDED_vmm_pgm_h */
835

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source: vbox/trunk/include/VBox/vmm/pgm.h@ 92186

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