pgm.h@ 92541

Last change on this file since 92541 was 92541, checked in by vboxsync, 3 years ago
VMM: Nested VMX: bugref:10092 Allow forcing mapping/unmapping of CR3 even when the paging mode deosn't actually change. This is required for VMX/SVM guest transitions.
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1	/** @file
2	* PGM - Page Monitor / Monitor.
3	*/
4
5	/*
6	* Copyright (C) 2006-2020 Oracle Corporation
7	*
8	* This file is part of VirtualBox Open Source Edition (OSE), as
9	* available from http://www.virtualbox.org. This file is free software;
10	* you can redistribute it and/or modify it under the terms of the GNU
11	* General Public License (GPL) as published by the Free Software
12	* Foundation, in version 2 as it comes in the "COPYING" file of the
13	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15	*
16	* The contents of this file may alternatively be used under the terms
17	* of the Common Development and Distribution License Version 1.0
18	* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19	* VirtualBox OSE distribution, in which case the provisions of the
20	* CDDL are applicable instead of those of the GPL.
21	*
22	* You may elect to license modified versions of this file under the
23	* terms and conditions of either the GPL or the CDDL or both.
24	*/
25
26	#ifndef VBOX_INCLUDED_vmm_pgm_h
27	#define VBOX_INCLUDED_vmm_pgm_h
28	#ifndef RT_WITHOUT_PRAGMA_ONCE
29	# pragma once
30	#endif
31
32	#include <VBox/types.h>
33	#include <VBox/sup.h>
34	#include <VBox/vmm/vmapi.h>
35	#include <VBox/vmm/gmm.h> /* for PGMMREGISTERSHAREDMODULEREQ */
36	#include <VBox/vmm/hm_vmx.h>
37	#include <iprt/x86.h>
38	#include <VBox/param.h>
39
40	RT_C_DECLS_BEGIN
41
42	/** @defgroup grp_pgm The Page Monitor / Manager API
43	* @ingroup grp_vmm
44	* @{
45	*/
46
47	/**
48	* FNPGMRELOCATE callback mode.
49	*/
50	typedef enum PGMRELOCATECALL
51	{
52	/** The callback is for checking if the suggested address is suitable. */
53	PGMRELOCATECALL_SUGGEST = 1,
54	/** The callback is for executing the relocation. */
55	PGMRELOCATECALL_RELOCATE
56	} PGMRELOCATECALL;
57
58
59	/**
60	* Callback function which will be called when PGM is trying to find
61	* a new location for the mapping.
62	*
63	* The callback is called in two modes, 1) the check mode and 2) the relocate mode.
64	* In 1) the callback should say if it objects to a suggested new location. If it
65	* accepts the new location, it is called again for doing it's relocation.
66	*
67	*
68	* @returns true if the location is ok.
69	* @returns false if another location should be found.
70	* @param pVM The cross context VM structure.
71	* @param GCPtrOld The old virtual address.
72	* @param GCPtrNew The new virtual address.
73	* @param enmMode Used to indicate the callback mode.
74	* @param pvUser User argument.
75	* @remark The return value is no a failure indicator, it's an acceptance
76	* indicator. Relocation can not fail!
77	*/
78	typedef DECLCALLBACKTYPE(bool, FNPGMRELOCATE,(PVM pVM, RTGCPTR GCPtrOld, RTGCPTR GCPtrNew, PGMRELOCATECALL enmMode, void *pvUser));
79	/** Pointer to a relocation callback function. */
80	typedef FNPGMRELOCATE *PFNPGMRELOCATE;
81
82
83	/**
84	* Memory access origin.
85	*/
86	typedef enum PGMACCESSORIGIN
87	{
88	/** Invalid zero value. */
89	PGMACCESSORIGIN_INVALID = 0,
90	/** IEM is access memory. */
91	PGMACCESSORIGIN_IEM,
92	/** HM is access memory. */
93	PGMACCESSORIGIN_HM,
94	/** Some device is access memory. */
95	PGMACCESSORIGIN_DEVICE,
96	/** Someone debugging is access memory. */
97	PGMACCESSORIGIN_DEBUGGER,
98	/** SELM is access memory. */
99	PGMACCESSORIGIN_SELM,
100	/** FTM is access memory. */
101	PGMACCESSORIGIN_FTM,
102	/** REM is access memory. */
103	PGMACCESSORIGIN_REM,
104	/** IOM is access memory. */
105	PGMACCESSORIGIN_IOM,
106	/** End of valid values. */
107	PGMACCESSORIGIN_END,
108	/** Type size hack. */
109	PGMACCESSORIGIN_32BIT_HACK = 0x7fffffff
110	} PGMACCESSORIGIN;
111
112
113	/**
114	* Physical page access handler kind.
115	*/
116	typedef enum PGMPHYSHANDLERKIND
117	{
118	/** MMIO range. Pages are not present, all access is done in interpreter or recompiler. */
119	PGMPHYSHANDLERKIND_MMIO = 1,
120	/** Handler all write access to a physical page range. */
121	PGMPHYSHANDLERKIND_WRITE,
122	/** Handler all access to a physical page range. */
123	PGMPHYSHANDLERKIND_ALL
124
125	} PGMPHYSHANDLERKIND;
126
127	/**
128	* Guest Access type
129	*/
130	typedef enum PGMACCESSTYPE
131	{
132	/** Read access. */
133	PGMACCESSTYPE_READ = 1,
134	/** Write access. */
135	PGMACCESSTYPE_WRITE
136	} PGMACCESSTYPE;
137
138
139	/** @def PGM_ALL_CB_DECL
140	* Macro for declaring a handler callback for all contexts. The handler
141	* callback is static in ring-3, and exported in RC and R0.
142	* @sa PGM_ALL_CB2_DECL.
143	*/
144	#if defined(IN_RC) \|\| defined(IN_RING0)
145	# ifdef __cplusplus
146	# define PGM_ALL_CB_DECL(type) extern "C" DECLCALLBACK(DECLEXPORT(type))
147	# else
148	# define PGM_ALL_CB_DECL(type) DECLCALLBACK(DECLEXPORT(type))
149	# endif
150	#else
151	# define PGM_ALL_CB_DECL(type) static DECLCALLBACK(type)
152	#endif
153
154	/** @def PGM_ALL_CB2_DECL
155	* Macro for declaring a handler callback for all contexts. The handler
156	* callback is hidden in ring-3, and exported in RC and R0.
157	* @sa PGM_ALL_CB2_DECL.
158	*/
159	#if defined(IN_RC) \|\| defined(IN_RING0)
160	# ifdef __cplusplus
161	# define PGM_ALL_CB2_DECL(type) extern "C" DECLCALLBACK(DECLEXPORT(type))
162	# else
163	# define PGM_ALL_CB2_DECL(type) DECLCALLBACK(DECLEXPORT(type))
164	# endif
165	#else
166	# define PGM_ALL_CB2_DECL(type) DECL_HIDDEN_CALLBACK(type)
167	#endif
168
169	/** @def PGM_ALL_CB2_PROTO
170	* Macro for declaring a handler callback for all contexts. The handler
171	* callback is hidden in ring-3, and exported in RC and R0.
172	* @param fnType The callback function type.
173	* @sa PGM_ALL_CB2_DECL.
174	*/
175	#if defined(IN_RC) \|\| defined(IN_RING0)
176	# ifdef __cplusplus
177	# define PGM_ALL_CB2_PROTO(fnType) extern "C" DECLEXPORT(fnType)
178	# else
179	# define PGM_ALL_CB2_PROTO(fnType) DECLEXPORT(fnType)
180	# endif
181	#else
182	# define PGM_ALL_CB2_PROTO(fnType) DECLHIDDEN(fnType)
183	#endif
184
185
186	/**
187	* \#PF Handler callback for physical access handler ranges in RC and R0.
188	*
189	* @returns Strict VBox status code (appropriate for ring-0 and raw-mode).
190	* @param pVM The cross context VM structure.
191	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
192	* @param uErrorCode CPU Error code.
193	* @param pRegFrame Trap register frame.
194	* NULL on DMA and other non CPU access.
195	* @param pvFault The fault address (cr2).
196	* @param GCPhysFault The GC physical address corresponding to pvFault.
197	* @param pvUser User argument.
198	* @thread EMT(pVCpu)
199	*/
200	typedef DECLCALLBACKTYPE(VBOXSTRICTRC, FNPGMRZPHYSPFHANDLER,(PVMCC pVM, PVMCPUCC pVCpu, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame,
201	RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser));
202	/** Pointer to PGM access callback. */
203	typedef FNPGMRZPHYSPFHANDLER *PFNPGMRZPHYSPFHANDLER;
204
205
206	/**
207	* Access handler callback for physical access handler ranges.
208	*
209	* The handler can not raise any faults, it's mainly for monitoring write access
210	* to certain pages (like MMIO).
211	*
212	* @returns Strict VBox status code in ring-0 and raw-mode context, in ring-3
213	* the only supported informational status code is
214	* VINF_PGM_HANDLER_DO_DEFAULT.
215	* @retval VINF_SUCCESS if the handler have carried out the operation.
216	* @retval VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the
217	* access operation.
218	* @retval VINF_EM_XXX in ring-0 and raw-mode context.
219	*
220	* @param pVM The cross context VM structure.
221	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
222	* @param GCPhys The physical address the guest is writing to.
223	* @param pvPhys The HC mapping of that address.
224	* @param pvBuf What the guest is reading/writing.
225	* @param cbBuf How much it's reading/writing.
226	* @param enmAccessType The access type.
227	* @param enmOrigin The origin of this call.
228	* @param pvUser User argument.
229	* @thread EMT(pVCpu)
230	*/
231	typedef DECLCALLBACKTYPE(VBOXSTRICTRC, FNPGMPHYSHANDLER,(PVMCC pVM, PVMCPUCC pVCpu, RTGCPHYS GCPhys, void *pvPhys,
232	void *pvBuf, size_t cbBuf, PGMACCESSTYPE enmAccessType,
233	PGMACCESSORIGIN enmOrigin, void *pvUser));
234	/** Pointer to PGM access callback. */
235	typedef FNPGMPHYSHANDLER *PFNPGMPHYSHANDLER;
236
237
238	/**
239	* Paging mode.
240	*
241	* @note Part of saved state. Change with extreme care.
242	*/
243	typedef enum PGMMODE
244	{
245	/** The usual invalid value. */
246	PGMMODE_INVALID = 0,
247	/** Real mode. */
248	PGMMODE_REAL,
249	/** Protected mode, no paging. */
250	PGMMODE_PROTECTED,
251	/** 32-bit paging. */
252	PGMMODE_32_BIT,
253	/** PAE paging. */
254	PGMMODE_PAE,
255	/** PAE paging with NX enabled. */
256	PGMMODE_PAE_NX,
257	/** 64-bit AMD paging (long mode). */
258	PGMMODE_AMD64,
259	/** 64-bit AMD paging (long mode) with NX enabled. */
260	PGMMODE_AMD64_NX,
261	/** 32-bit nested paging mode (shadow only; guest physical to host physical). */
262	PGMMODE_NESTED_32BIT,
263	/** PAE nested paging mode (shadow only; guest physical to host physical). */
264	PGMMODE_NESTED_PAE,
265	/** AMD64 nested paging mode (shadow only; guest physical to host physical). */
266	PGMMODE_NESTED_AMD64,
267	/** Extended paging (Intel) mode. */
268	PGMMODE_EPT,
269	/** Special mode used by NEM to indicate no shadow paging necessary. */
270	PGMMODE_NONE,
271	/** The max number of modes */
272	PGMMODE_MAX,
273	/** 32bit hackishness. */
274	PGMMODE_32BIT_HACK = 0x7fffffff
275	} PGMMODE;
276
277	/**
278	* Second level address translation (SLAT) mode.
279	*/
280	typedef enum PGMSLAT
281	{
282	/** The usual invalid value. */
283	PGMSLAT_INVALID = 0,
284	/** No second level translation. */
285	PGMSLAT_DIRECT,
286	/** Intel Extended Page Tables (EPT). */
287	PGMSLAT_EPT,
288	/** AMD-V Nested Paging 32-bit. */
289	PGMSLAT_32BIT,
290	/** AMD-V Nested Paging PAE. */
291	PGMSLAT_PAE,
292	/** AMD-V Nested Paging 64-bit. */
293	PGMSLAT_AMD64,
294	/** 32bit hackishness. */
295	PGMSLAT_32BIT_HACK = 0x7fffffff
296	} PGMSLAT;
297
298	/**
299	* SLAT page walk failure type.
300	*/
301	typedef enum PGMSLATFAIL
302	{
303	/** Invalid value. */
304	PGMSLATFAIL_INVALID = 0,
305	/** EPT violation. */
306	PGMSLATFAIL_EPT_VIOLATION,
307	/** EPT violation convertible to \#VE exception. */
308	PGMSLATFAIL_EPT_VIOLATION_CONVERTIBLE,
309	/** EPT misconfiguration. */
310	PGMSLATFAIL_EPT_MISCONFIG,
311	/** 32bit hackishness. */
312	PGMSLATFAIL_32BIT_HACK = 0x7fffffff
313	} PGMSLATFAIL;
314
315	/** @name PGMPTATTRS - PGM page-table attributes.
316	*
317	* This is VirtualBox's combined page table attributes. It combines regular page
318	* table and Intel EPT attributes. It's 64-bit in size so there's ample room for
319	* bits added in the future to EPT or regular page tables (for e.g. Protection Key).
320	*
321	* The following bits map 1:1 (shifted by PGM_PTATTRS_EPT_SHIFT) to the Intel EPT
322	* attributes as these are unique to EPT and fit within 64-bits despite the shift:
323	* - EPT_R : Read access.
324	* - EPT_W : Write access.
325	* - EPT_X_SUPER : Execute or execute for supervisor-mode linear addr access.
326	* - EPT_MEMTYPE : EPT memory type.
327	* - EPT_IGNORE_PAT: Ignore PAT memory type.
328	* - EPT_X_USER : Execute access for user-mode linear addresses.
329	*
330	* For regular page tables, the R bit is always 1 (same as P bit).
331	* For Intel EPT, the EPT_R and EPT_W bits are copied to R and W bits respectively.
332	*
333	* The following EPT attributes are mapped to the following positions because they
334	* exist in the regular page tables at these positions OR are exclusive to EPT and
335	* have been mapped to arbitrarily chosen positions:
336	* - EPT_A : Accessed (EPT bit 8 maps to bit 5).
337	* - EPT_D : Dirty (EPT bit 9 maps to bit 6).
338	* - EPT_SUPER_SHW_STACK : Supervisor Shadow Stack (EPT bit 60 maps to bit 24).
339	* - EPT_SUPPRESS_VE_XCPT: Suppress \#VE exception (EPT bit 63 maps to bit 25).
340	*
341	* Bits 12, 11:9 and 43 are deliberately kept unused (correspond to bit PS and bits
342	* 11:9 in the regular page-table structures and to bit 11 in the EPT structures
343	* respectively) as bit 12 is the page-size bit and bits 11:9 are reserved for
344	* use by software and we may want to use/preserve them in the future.
345	*
346	* @{ */
347	typedef uint64_t PGMPTATTRS;
348	/** Pointer to a PGMPTATTRS type. */
349	typedef PGMPTATTRS *PPGMPTATTRS;
350
351	/** Read bit (always 1 for regular PT, copy of EPT_R for EPT). */
352	#define PGM_PTATTRS_R_SHIFT 0
353	#define PGM_PTATTRS_R_MASK RT_BIT_64(PGM_PTATTRS_R_SHIFT)
354	/** Write access bit (aka read/write bit for regular PT). */
355	#define PGM_PTATTRS_W_SHIFT 1
356	#define PGM_PTATTRS_W_MASK RT_BIT_64(PGM_PTATTRS_W_SHIFT)
357	/** User-mode access bit. */
358	#define PGM_PTATTRS_US_SHIFT 2
359	#define PGM_PTATTRS_US_MASK RT_BIT_64(PGM_PTATTRS_US_SHIFT)
360	/** Write through cache bit. */
361	#define PGM_PTATTRS_PWT_SHIFT 3
362	#define PGM_PTATTRS_PWT_MASK RT_BIT_64(PGM_PTATTRS_PWT_SHIFT)
363	/** Cache disabled bit. */
364	#define PGM_PTATTRS_PCD_SHIFT 4
365	#define PGM_PTATTRS_PCD_MASK RT_BIT_64(PGM_PTATTRS_PCD_SHIFT)
366	/** Accessed bit. */
367	#define PGM_PTATTRS_A_SHIFT 5
368	#define PGM_PTATTRS_A_MASK RT_BIT_64(PGM_PTATTRS_A_SHIFT)
369	/** Dirty bit. */
370	#define PGM_PTATTRS_D_SHIFT 6
371	#define PGM_PTATTRS_D_MASK RT_BIT_64(PGM_PTATTRS_D_SHIFT)
372	/** The PAT bit. */
373	#define PGM_PTATTRS_PAT_SHIFT 7
374	#define PGM_PTATTRS_PAT_MASK RT_BIT_64(PGM_PTATTRS_PAT_SHIFT)
375	/** The global bit. */
376	#define PGM_PTATTRS_G_SHIFT 8
377	#define PGM_PTATTRS_G_MASK RT_BIT_64(PGM_PTATTRS_G_SHIFT)
378	/** Reserved (bits 12:9) unused. */
379	#define PGM_PTATTRS_RSVD_12_9_SHIFT 9
380	#define PGM_PTATTRS_RSVD_12_9_MASK UINT64_C(0x0000000000001e00)
381	/** Read access bit - EPT only. */
382	#define PGM_PTATTRS_EPT_R_SHIFT 13
383	#define PGM_PTATTRS_EPT_R_MASK RT_BIT_64(PGM_PTATTRS_EPT_R_SHIFT)
384	/** Write access bit - EPT only. */
385	#define PGM_PTATTRS_EPT_W_SHIFT 14
386	#define PGM_PTATTRS_EPT_W_MASK RT_BIT_64(PGM_PTATTRS_EPT_W_SHIFT)
387	/** Execute or execute access for supervisor-mode linear addresses - EPT only. */
388	#define PGM_PTATTRS_EPT_X_SUPER_SHIFT 15
389	#define PGM_PTATTRS_EPT_X_SUPER_MASK RT_BIT_64(PGM_PTATTRS_EPT_X_SUPER_SHIFT)
390	/** EPT memory type - EPT only. */
391	#define PGM_PTATTRS_EPT_MEMTYPE_SHIFT 16
392	#define PGM_PTATTRS_EPT_MEMTYPE_MASK UINT64_C(0x0000000000070000)
393	/** Ignore PAT memory type - EPT only. */
394	#define PGM_PTATTRS_EPT_IGNORE_PAT_SHIFT 19
395	#define PGM_PTATTRS_EPT_IGNORE_PAT_MASK RT_BIT_64(PGM_PTATTRS_EPT_IGNORE_PAT_SHIFT)
396	/** Reserved (bits 22:20) unused. */
397	#define PGM_PTATTRS_RSVD_22_20_SHIFT 20
398	#define PGM_PTATTRS_RSVD_22_20_MASK UINT64_C(0x0000000000700000)
399	/** Execute access for user-mode linear addresses - EPT only. */
400	#define PGM_PTATTRS_EPT_X_USER_SHIFT 23
401	#define PGM_PTATTRS_EPT_X_USER_MASK RT_BIT_64(PGM_PTATTRS_EPT_X_USER_SHIFT)
402	/** Reserved (bit 23) - unused. */
403	#define PGM_PTATTRS_RSVD_23_SHIFT 24
404	#define PGM_PTATTRS_RSVD_23_MASK UINT64_C(0x0000000001000000)
405	/** Supervisor shadow stack - EPT only. */
406	#define PGM_PTATTRS_EPT_SUPER_SHW_STACK_SHIFT 25
407	#define PGM_PTATTRS_EPT_SUPER_SHW_STACK_MASK RT_BIT_64(PGM_PTATTRS_EPT_SUPER_SHW_STACK_SHIFT)
408	/** Suppress \#VE exception - EPT only. */
409	#define PGM_PTATTRS_EPT_SUPPRESS_VE_XCPT_SHIFT 26
410	#define PGM_PTATTRS_EPT_SUPPRESS_VE_XCPT_MASK RT_BIT_64(PGM_PTATTRS_EPT_SUPPRESS_VE_XCPT_SHIFT)
411	/** Reserved (bits 62:27) - unused. */
412	#define PGM_PTATTRS_RSVD_62_27_SHIFT 27
413	#define PGM_PTATTRS_RSVD_62_27_MASK UINT64_C(0x7ffffffff8000000)
414	/** No-execute bit. */
415	#define PGM_PTATTRS_NX_SHIFT 63
416	#define PGM_PTATTRS_NX_MASK RT_BIT_64(PGM_PTATTRS_NX_SHIFT)
417
418	RT_BF_ASSERT_COMPILE_CHECKS(PGM_PTATTRS_, UINT64_C(0), UINT64_MAX,
419	(R, W, US, PWT, PCD, A, D, PAT, G, RSVD_12_9, EPT_R, EPT_W, EPT_X_SUPER, EPT_MEMTYPE, EPT_IGNORE_PAT,
420	RSVD_22_20, EPT_X_USER, RSVD_23, EPT_SUPER_SHW_STACK, EPT_SUPPRESS_VE_XCPT, RSVD_62_27, NX));
421
422	/** The bit position where the EPT specific attributes begin. */
423	#define PGM_PTATTRS_EPT_SHIFT PGM_PTATTRS_EPT_R_SHIFT
424	/** The mask of EPT bits (bits 26:ATTR_SHIFT). In the future we might choose to
425	* use higher unused bits for something else, in that case adjust this mask. */
426	#define PGM_PTATTRS_EPT_MASK UINT64_C(0x0000000007ffe000)
427
428	/** The mask of all PGM page attribute bits for regular page-tables. */
429	#define PGM_PTATTRS_PT_VALID_MASK ( PGM_PTATTRS_R_MASK \
430	\| PGM_PTATTRS_W_MASK \
431	\| PGM_PTATTRS_US_MASK \
432	\| PGM_PTATTRS_PWT_MASK \
433	\| PGM_PTATTRS_PCD_MASK \
434	\| PGM_PTATTRS_A_MASK \
435	\| PGM_PTATTRS_D_MASK \
436	\| PGM_PTATTRS_PAT_MASK \
437	\| PGM_PTATTRS_G_MASK \
438	\| PGM_PTATTRS_NX_MASK)
439
440	/** The mask of all PGM page attribute bits for EPT. */
441	#define PGM_PTATTRS_EPT_VALID_MASK ( PGM_PTATTRS_R_MASK \
442	\| PGM_PTATTRS_W_MASK \
443	\| PGM_PTATTRS_A_MASK \
444	\| PGM_PTATTRS_D_MASK \
445	\| PGM_PTATTRS_EPT_R_MASK \
446	\| PGM_PTATTRS_EPT_W_MASK \
447	\| PGM_PTATTRS_EPT_X_SUPER \
448	\| PGM_PTATTRS_EPT_MEMTYPE \
449	\| PGM_PTATTRS_EPT_IGNORE_PAT \
450	\| PGM_PTATTRS_EPT_X_USER \
451	\| PGM_PTATTRS_EPT_SUPER_SHW_STACK \
452	\| PGM_PTATTRS_EPT_SUPPRESS_VE_XCPT)
453
454	/* The mask of all PGM page attribute bits (combined). */
455	#define PGM_PTATTRS_VALID_MASK (PGM_PTATTRS_PT_VALID_MASK \| PGM_PTATTRS_PT_VALID_MASK)
456
457	/* Verify bits match the regular PT bits. */
458	AssertCompile(PGM_PTATTRS_W_SHIFT == X86_PTE_BIT_RW);
459	AssertCompile(PGM_PTATTRS_US_SHIFT == X86_PTE_BIT_US);
460	AssertCompile(PGM_PTATTRS_PWT_SHIFT == X86_PTE_BIT_PWT);
461	AssertCompile(PGM_PTATTRS_PCD_SHIFT == X86_PTE_BIT_PCD);
462	AssertCompile(PGM_PTATTRS_A_SHIFT == X86_PTE_BIT_A);
463	AssertCompile(PGM_PTATTRS_D_SHIFT == X86_PTE_BIT_D);
464	AssertCompile(PGM_PTATTRS_PAT_SHIFT == X86_PTE_BIT_PAT);
465	AssertCompile(PGM_PTATTRS_G_SHIFT == X86_PTE_BIT_G);
466	AssertCompile(PGM_PTATTRS_W_MASK == X86_PTE_RW);
467	AssertCompile(PGM_PTATTRS_US_MASK == X86_PTE_US);
468	AssertCompile(PGM_PTATTRS_PWT_MASK == X86_PTE_PWT);
469	AssertCompile(PGM_PTATTRS_PCD_MASK == X86_PTE_PCD);
470	AssertCompile(PGM_PTATTRS_A_MASK == X86_PTE_A);
471	AssertCompile(PGM_PTATTRS_D_MASK == X86_PTE_D);
472	AssertCompile(PGM_PTATTRS_PAT_MASK == X86_PTE_PAT);
473	AssertCompile(PGM_PTATTRS_G_MASK == X86_PTE_G);
474	AssertCompile(PGM_PTATTRS_NX_MASK == X86_PTE_PAE_NX);
475
476	/* Verify those EPT bits that must map 1:1 (after shifting). */
477	AssertCompile(PGM_PTATTRS_EPT_R_SHIFT - PGM_PTATTRS_EPT_SHIFT == EPT_E_BIT_READ);
478	AssertCompile(PGM_PTATTRS_EPT_W_SHIFT - PGM_PTATTRS_EPT_SHIFT == EPT_E_BIT_WRITE);
479	AssertCompile(PGM_PTATTRS_EPT_X_SUPER_SHIFT - PGM_PTATTRS_EPT_SHIFT == EPT_E_BIT_EXECUTE);
480	AssertCompile(PGM_PTATTRS_EPT_IGNORE_PAT_SHIFT - PGM_PTATTRS_EPT_SHIFT == EPT_E_BIT_IGNORE_PAT);
481	AssertCompile(PGM_PTATTRS_EPT_X_USER_SHIFT - PGM_PTATTRS_EPT_SHIFT == EPT_E_BIT_USER_EXECUTE);
482	/** @} */
483
484
485	/**
486	* Page table walk information.
487	*
488	* This provides extensive information regarding page faults (or EPT
489	* violations/misconfigurations) while traversing page tables.
490	*/
491	typedef struct PGMPTWALK
492	{
493	/** The linear address that is being resolved (input). */
494	RTGCPTR GCPtr;
495
496	/** The second-level physical address (input/output).
497	* @remarks only valid if fIsSlat is set. */
498	RTGCPHYS GCPhysNested;
499
500	/** The physical address that is the result of the walk (output).
501	* @remarks This is page aligned and only valid if fSucceeded is set. */
502	RTGCPHYS GCPhys;
503
504	/** Set if the walk succeeded. */
505	bool fSucceeded;
506	/** Whether this is a second-level address translation. */
507	bool fIsSlat;
508	/** Whether the linear address (GCPtr) caused the second-level
509	* address translation. */
510	bool fIsLinearAddrValid;
511	/** The level problem arrised at.
512	* PTE is level 1, PDE is level 2, PDPE is level 3, PML4 is level 4, CR3 is
513	* level 8. This is 0 on success. */
514	uint8_t uLevel;
515	/** Set if the page isn't present. */
516	bool fNotPresent;
517	/** Encountered a bad physical address. */
518	bool fBadPhysAddr;
519	/** Set if there was reserved bit violations. */
520	bool fRsvdError;
521	/** Set if it involves a big page (2/4 MB). */
522	bool fBigPage;
523	/** Set if it involves a gigantic page (1 GB). */
524	bool fGigantPage;
525	bool afPadding[3];
526	/** The type of SLAT failure. */
527	PGMSLATFAIL enmSlatFail;
528
529	/** The effective attributes, PGM_PTATTRS_XXX. */
530	PGMPTATTRS fEffective;
531	} PGMPTWALK;
532	/** Pointer to page walk information. */
533	typedef PGMPTWALK *PPGMPTWALK;
534	/** Pointer to const page walk information. */
535	typedef PGMPTWALK const *PCPGMPTWALK;
536
537
538	/** Macro for checking if the guest is using paging.
539	* @param enmMode PGMMODE_*.
540	* @remark ASSUMES certain order of the PGMMODE_* values.
541	*/
542	#define PGMMODE_WITH_PAGING(enmMode) ((enmMode) >= PGMMODE_32_BIT)
543
544	/** Macro for checking if it's one of the long mode modes.
545	* @param enmMode PGMMODE_*.
546	*/
547	#define PGMMODE_IS_LONG_MODE(enmMode) ((enmMode) == PGMMODE_AMD64_NX \|\| (enmMode) == PGMMODE_AMD64)
548
549	/** Macro for checking if it's one of the AMD64 nested modes.
550	* @param enmMode PGMMODE_*.
551	*/
552	#define PGMMODE_IS_NESTED(enmMode) ( (enmMode) == PGMMODE_NESTED_32BIT \
553	\|\| (enmMode) == PGMMODE_NESTED_PAE \
554	\|\| (enmMode) == PGMMODE_NESTED_AMD64)
555
556	/** Macro for checking if it's one of the PAE modes.
557	* @param enmMode PGMMODE_*.
558	*/
559	#define PGMMODE_IS_PAE(enmMode) ( (enmMode) == PGMMODE_PAE \
560	\|\| (enmMode) == PGMMODE_PAE_NX)
561
562	/**
563	* Is the ROM mapped (true) or is the shadow RAM mapped (false).
564	*
565	* @returns boolean.
566	* @param enmProt The PGMROMPROT value, must be valid.
567	*/
568	#define PGMROMPROT_IS_ROM(enmProt) \
569	( (enmProt) == PGMROMPROT_READ_ROM_WRITE_IGNORE \
570	\|\| (enmProt) == PGMROMPROT_READ_ROM_WRITE_RAM )
571
572
573	VMMDECL(bool) PGMIsLockOwner(PVMCC pVM);
574
575	VMMDECL(int) PGMRegisterStringFormatTypes(void);
576	VMMDECL(void) PGMDeregisterStringFormatTypes(void);
577	VMMDECL(RTHCPHYS) PGMGetHyperCR3(PVMCPU pVCpu);
578	VMMDECL(int) PGMTrap0eHandler(PVMCPUCC pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault);
579	VMMDECL(int) PGMPrefetchPage(PVMCPUCC pVCpu, RTGCPTR GCPtrPage);
580	VMMDECL(VBOXSTRICTRC) PGMInterpretInstruction(PVMCC pVM, PVMCPUCC pVCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault);
581	VMMDECL(int) PGMShwGetPage(PVMCPUCC pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys);
582	VMMDECL(int) PGMShwMakePageReadonly(PVMCPUCC pVCpu, RTGCPTR GCPtr, uint32_t fFlags);
583	VMMDECL(int) PGMShwMakePageWritable(PVMCPUCC pVCpu, RTGCPTR GCPtr, uint32_t fFlags);
584	VMMDECL(int) PGMShwMakePageNotPresent(PVMCPUCC pVCpu, RTGCPTR GCPtr, uint32_t fFlags);
585	/** @name Flags for PGMShwMakePageReadonly, PGMShwMakePageWritable and
586	* PGMShwMakePageNotPresent
587	* @{ */
588	/** The call is from an access handler for dealing with the a faulting write
589	* operation. The virtual address is within the same page. */
590	#define PGM_MK_PG_IS_WRITE_FAULT RT_BIT(0)
591	/** The page is an MMIO2. */
592	#define PGM_MK_PG_IS_MMIO2 RT_BIT(1)
593	/** @}*/
594	VMMDECL(int) PGMGstGetPage(PVMCPUCC pVCpu, RTGCPTR GCPtr, PPGMPTWALK pWalk);
595	VMMDECL(int) PGMGstSetPage(PVMCPUCC pVCpu, RTGCPTR GCPtr, size_t cb, uint64_t fFlags);
596	VMMDECL(int) PGMGstModifyPage(PVMCPUCC pVCpu, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask);
597	VMM_INT_DECL(bool) PGMGstArePaePdpesValid(PVMCPUCC pVCpu, PCX86PDPE paPaePdpes);
598	VMM_INT_DECL(int) PGMGstMapPaePdpes(PVMCPUCC pVCpu, PCX86PDPE paPaePdpes);
599	VMM_INT_DECL(int) PGMGstMapPaePdpesAtCr3(PVMCPUCC pVCpu, uint64_t cr3);
600
601	VMMDECL(int) PGMInvalidatePage(PVMCPUCC pVCpu, RTGCPTR GCPtrPage);
602	VMMDECL(int) PGMFlushTLB(PVMCPUCC pVCpu, uint64_t cr3, bool fGlobal, bool fPdpesMapped);
603	VMMDECL(int) PGMSyncCR3(PVMCPUCC pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal);
604	VMMDECL(int) PGMUpdateCR3(PVMCPUCC pVCpu, uint64_t cr3, bool fPdpesMapped);
605	VMMDECL(int) PGMChangeMode(PVMCPUCC pVCpu, uint64_t cr0, uint64_t cr4, uint64_t efer, bool fForce);
606	VMM_INT_DECL(int) PGMHCChangeMode(PVMCC pVM, PVMCPUCC pVCpu, PGMMODE enmGuestMode);
607	VMMDECL(void) PGMCr0WpEnabled(PVMCPUCC pVCpu);
608	VMMDECL(PGMMODE) PGMGetGuestMode(PVMCPU pVCpu);
609	VMMDECL(PGMMODE) PGMGetShadowMode(PVMCPU pVCpu);
610	VMMDECL(PGMMODE) PGMGetHostMode(PVM pVM);
611	VMMDECL(const char *) PGMGetModeName(PGMMODE enmMode);
612	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
613	VMM_INT_DECL(const char *) PGMGetSlatModeName(PGMSLAT enmSlatMode);
614	#endif
615	VMM_INT_DECL(RTGCPHYS) PGMGetGuestCR3Phys(PVMCPU pVCpu);
616	VMM_INT_DECL(void) PGMNotifyNxeChanged(PVMCPU pVCpu, bool fNxe);
617	VMMDECL(bool) PGMHasDirtyPages(PVM pVM);
618	VMM_INT_DECL(void) PGMSetGuestEptPtr(PVMCPUCC pVCpu, uint64_t uEptPtr);
619
620	/** PGM physical access handler type registration handle (heap offset, valid
621	* cross contexts without needing fixing up). Callbacks and handler type is
622	* associated with this and it is shared by all handler registrations. */
623	typedef uint32_t PGMPHYSHANDLERTYPE;
624	/** Pointer to a PGM physical handler type registration handle. */
625	typedef PGMPHYSHANDLERTYPE *PPGMPHYSHANDLERTYPE;
626	/** NIL value for PGM physical access handler type handle. */
627	#define NIL_PGMPHYSHANDLERTYPE UINT32_MAX
628	VMMDECL(uint32_t) PGMHandlerPhysicalTypeRelease(PVMCC pVM, PGMPHYSHANDLERTYPE hType);
629	VMMDECL(uint32_t) PGMHandlerPhysicalTypeRetain(PVM pVM, PGMPHYSHANDLERTYPE hType);
630
631	VMMDECL(int) PGMHandlerPhysicalRegister(PVMCC pVM, RTGCPHYS GCPhys, RTGCPHYS GCPhysLast, PGMPHYSHANDLERTYPE hType,
632	RTR3PTR pvUserR3, RTR0PTR pvUserR0, RTRCPTR pvUserRC,
633	R3PTRTYPE(const char *) pszDesc);
634	VMMDECL(int) PGMHandlerPhysicalModify(PVMCC pVM, RTGCPHYS GCPhysCurrent, RTGCPHYS GCPhys, RTGCPHYS GCPhysLast);
635	VMMDECL(int) PGMHandlerPhysicalDeregister(PVMCC pVM, RTGCPHYS GCPhys);
636	VMMDECL(int) PGMHandlerPhysicalChangeUserArgs(PVMCC pVM, RTGCPHYS GCPhys, RTR3PTR pvUserR3, RTR0PTR pvUserR0);
637	VMMDECL(int) PGMHandlerPhysicalSplit(PVMCC pVM, RTGCPHYS GCPhys, RTGCPHYS GCPhysSplit);
638	VMMDECL(int) PGMHandlerPhysicalJoin(PVMCC pVM, RTGCPHYS GCPhys1, RTGCPHYS GCPhys2);
639	VMMDECL(int) PGMHandlerPhysicalPageTempOff(PVMCC pVM, RTGCPHYS GCPhys, RTGCPHYS GCPhysPage);
640	VMMDECL(int) PGMHandlerPhysicalPageAliasMmio2(PVMCC pVM, RTGCPHYS GCPhys, RTGCPHYS GCPhysPage,
641	PPDMDEVINS pDevIns, PGMMMIO2HANDLE hMmio2, RTGCPHYS offMMio2PageRemap);
642	VMMDECL(int) PGMHandlerPhysicalPageAliasHC(PVMCC pVM, RTGCPHYS GCPhys, RTGCPHYS GCPhysPage, RTHCPHYS HCPhysPageRemap);
643	VMMDECL(int) PGMHandlerPhysicalReset(PVMCC pVM, RTGCPHYS GCPhys);
644	VMMDECL(bool) PGMHandlerPhysicalIsRegistered(PVMCC pVM, RTGCPHYS GCPhys);
645
646
647	/**
648	* Page type.
649	*
650	* @remarks This enum has to fit in a 3-bit field (see PGMPAGE::u3Type).
651	* @remarks This is used in the saved state, so changes to it requires bumping
652	* the saved state version.
653	* @todo So, convert to \#defines!
654	*/
655	typedef enum PGMPAGETYPE
656	{
657	/** The usual invalid zero entry. */
658	PGMPAGETYPE_INVALID = 0,
659	/** RAM page. (RWX) */
660	PGMPAGETYPE_RAM,
661	/** MMIO2 page. (RWX) */
662	PGMPAGETYPE_MMIO2,
663	/** MMIO2 page aliased over an MMIO page. (RWX)
664	* See PGMHandlerPhysicalPageAlias(). */
665	PGMPAGETYPE_MMIO2_ALIAS_MMIO,
666	/** Special page aliased over an MMIO page. (RWX)
667	* See PGMHandlerPhysicalPageAliasHC(), but this is generally only used for
668	* VT-x's APIC access page at the moment. Treated as MMIO by everyone except
669	* the shadow paging code. */
670	PGMPAGETYPE_SPECIAL_ALIAS_MMIO,
671	/** Shadowed ROM. (RWX) */
672	PGMPAGETYPE_ROM_SHADOW,
673	/** ROM page. (R-X) */
674	PGMPAGETYPE_ROM,
675	/** MMIO page. (---) */
676	PGMPAGETYPE_MMIO,
677	/** End of valid entries. */
678	PGMPAGETYPE_END
679	} PGMPAGETYPE;
680	AssertCompile(PGMPAGETYPE_END == 8);
681
682	/** @name PGM page type predicates.
683	* @{ */
684	#define PGMPAGETYPE_IS_READABLE(a_enmType) ( (a_enmType) <= PGMPAGETYPE_ROM )
685	#define PGMPAGETYPE_IS_WRITEABLE(a_enmType) ( (a_enmType) <= PGMPAGETYPE_ROM_SHADOW )
686	#define PGMPAGETYPE_IS_RWX(a_enmType) ( (a_enmType) <= PGMPAGETYPE_ROM_SHADOW )
687	#define PGMPAGETYPE_IS_ROX(a_enmType) ( (a_enmType) == PGMPAGETYPE_ROM )
688	#define PGMPAGETYPE_IS_NP(a_enmType) ( (a_enmType) == PGMPAGETYPE_MMIO )
689	/** @} */
690
691
692	VMM_INT_DECL(PGMPAGETYPE) PGMPhysGetPageType(PVMCC pVM, RTGCPHYS GCPhys);
693
694	VMM_INT_DECL(int) PGMPhysGCPhys2HCPhys(PVMCC pVM, RTGCPHYS GCPhys, PRTHCPHYS pHCPhys);
695	VMM_INT_DECL(int) PGMPhysGCPtr2HCPhys(PVMCPUCC pVCpu, RTGCPTR GCPtr, PRTHCPHYS pHCPhys);
696	VMM_INT_DECL(int) PGMPhysGCPhys2CCPtr(PVMCC pVM, RTGCPHYS GCPhys, void **ppv, PPGMPAGEMAPLOCK pLock);
697	VMM_INT_DECL(int) PGMPhysGCPhys2CCPtrReadOnly(PVMCC pVM, RTGCPHYS GCPhys, void const **ppv, PPGMPAGEMAPLOCK pLock);
698	VMM_INT_DECL(int) PGMPhysGCPtr2CCPtr(PVMCPU pVCpu, RTGCPTR GCPtr, void **ppv, PPGMPAGEMAPLOCK pLock);
699	VMM_INT_DECL(int) PGMPhysGCPtr2CCPtrReadOnly(PVMCPUCC pVCpu, RTGCPTR GCPtr, void const **ppv, PPGMPAGEMAPLOCK pLock);
700
701	VMMDECL(bool) PGMPhysIsA20Enabled(PVMCPU pVCpu);
702	VMMDECL(bool) PGMPhysIsGCPhysValid(PVMCC pVM, RTGCPHYS GCPhys);
703	VMMDECL(bool) PGMPhysIsGCPhysNormal(PVMCC pVM, RTGCPHYS GCPhys);
704	VMMDECL(int) PGMPhysGCPtr2GCPhys(PVMCPUCC pVCpu, RTGCPTR GCPtr, PRTGCPHYS pGCPhys);
705	VMMDECL(void) PGMPhysReleasePageMappingLock(PVMCC pVM, PPGMPAGEMAPLOCK pLock);
706	VMMDECL(void) PGMPhysBulkReleasePageMappingLocks(PVMCC pVM, uint32_t cPages, PPGMPAGEMAPLOCK paLock);
707
708	/** @def PGM_PHYS_RW_IS_SUCCESS
709	* Check whether a PGMPhysRead, PGMPhysWrite, PGMPhysReadGCPtr or
710	* PGMPhysWriteGCPtr call completed the given task.
711	*
712	* @returns true if completed, false if not.
713	* @param a_rcStrict The status code.
714	* @sa IOM_SUCCESS
715	*/
716	#ifdef IN_RING3
717	# define PGM_PHYS_RW_IS_SUCCESS(a_rcStrict) \
718	( (a_rcStrict) == VINF_SUCCESS \
719	\|\| (a_rcStrict) == VINF_EM_DBG_STOP \
720	\|\| (a_rcStrict) == VINF_EM_DBG_EVENT \
721	\|\| (a_rcStrict) == VINF_EM_DBG_BREAKPOINT \
722	)
723	#elif defined(IN_RING0)
724	# define PGM_PHYS_RW_IS_SUCCESS(a_rcStrict) \
725	( (a_rcStrict) == VINF_SUCCESS \
726	\|\| (a_rcStrict) == VINF_IOM_R3_MMIO_COMMIT_WRITE \
727	\|\| (a_rcStrict) == VINF_EM_OFF \
728	\|\| (a_rcStrict) == VINF_EM_SUSPEND \
729	\|\| (a_rcStrict) == VINF_EM_RESET \
730	\|\| (a_rcStrict) == VINF_EM_HALT \
731	\|\| (a_rcStrict) == VINF_EM_DBG_STOP \
732	\|\| (a_rcStrict) == VINF_EM_DBG_EVENT \
733	\|\| (a_rcStrict) == VINF_EM_DBG_BREAKPOINT \
734	)
735	#elif defined(IN_RC)
736	# define PGM_PHYS_RW_IS_SUCCESS(a_rcStrict) \
737	( (a_rcStrict) == VINF_SUCCESS \
738	\|\| (a_rcStrict) == VINF_IOM_R3_MMIO_COMMIT_WRITE \
739	\|\| (a_rcStrict) == VINF_EM_OFF \
740	\|\| (a_rcStrict) == VINF_EM_SUSPEND \
741	\|\| (a_rcStrict) == VINF_EM_RESET \
742	\|\| (a_rcStrict) == VINF_EM_HALT \
743	\|\| (a_rcStrict) == VINF_SELM_SYNC_GDT \
744	\|\| (a_rcStrict) == VINF_EM_RAW_EMULATE_INSTR_GDT_FAULT \
745	\|\| (a_rcStrict) == VINF_EM_DBG_STOP \
746	\|\| (a_rcStrict) == VINF_EM_DBG_EVENT \
747	\|\| (a_rcStrict) == VINF_EM_DBG_BREAKPOINT \
748	)
749	#endif
750	/** @def PGM_PHYS_RW_DO_UPDATE_STRICT_RC
751	* Updates the return code with a new result.
752	*
753	* Both status codes must be successes according to PGM_PHYS_RW_IS_SUCCESS.
754	*
755	* @param a_rcStrict The current return code, to be updated.
756	* @param a_rcStrict2 The new return code to merge in.
757	*/
758	#ifdef IN_RING3
759	# define PGM_PHYS_RW_DO_UPDATE_STRICT_RC(a_rcStrict, a_rcStrict2) \
760	do { \
761	Assert(rcStrict == VINF_SUCCESS); \
762	Assert(rcStrict2 == VINF_SUCCESS); \
763	} while (0)
764	#elif defined(IN_RING0)
765	# define PGM_PHYS_RW_DO_UPDATE_STRICT_RC(a_rcStrict, a_rcStrict2) \
766	do { \
767	Assert(PGM_PHYS_RW_IS_SUCCESS(rcStrict)); \
768	Assert(PGM_PHYS_RW_IS_SUCCESS(rcStrict2)); \
769	AssertCompile(VINF_IOM_R3_MMIO_COMMIT_WRITE > VINF_EM_LAST); \
770	if ((a_rcStrict2) == VINF_SUCCESS \|\| (a_rcStrict) == (a_rcStrict2)) \
771	{ /* likely */ } \
772	else if ( (a_rcStrict) == VINF_SUCCESS \
773	\|\| (a_rcStrict) > (a_rcStrict2)) \
774	(a_rcStrict) = (a_rcStrict2); \
775	} while (0)
776	#elif defined(IN_RC)
777	# define PGM_PHYS_RW_DO_UPDATE_STRICT_RC(a_rcStrict, a_rcStrict2) \
778	do { \
779	Assert(PGM_PHYS_RW_IS_SUCCESS(rcStrict)); \
780	Assert(PGM_PHYS_RW_IS_SUCCESS(rcStrict2)); \
781	AssertCompile(VINF_SELM_SYNC_GDT > VINF_EM_LAST); \
782	AssertCompile(VINF_EM_RAW_EMULATE_INSTR_GDT_FAULT > VINF_EM_LAST); \
783	AssertCompile(VINF_EM_RAW_EMULATE_INSTR_GDT_FAULT < VINF_SELM_SYNC_GDT); \
784	AssertCompile(VINF_IOM_R3_MMIO_COMMIT_WRITE > VINF_EM_LAST); \
785	AssertCompile(VINF_IOM_R3_MMIO_COMMIT_WRITE > VINF_SELM_SYNC_GDT); \
786	AssertCompile(VINF_IOM_R3_MMIO_COMMIT_WRITE > VINF_EM_RAW_EMULATE_INSTR_GDT_FAULT); \
787	if ((a_rcStrict2) == VINF_SUCCESS \|\| (a_rcStrict) == (a_rcStrict2)) \
788	{ /* likely */ } \
789	else if ((a_rcStrict) == VINF_SUCCESS) \
790	(a_rcStrict) = (a_rcStrict2); \
791	else if ( ( (a_rcStrict) > (a_rcStrict2) \
792	&& ( (a_rcStrict2) <= VINF_EM_RESET \
793	\|\| (a_rcStrict) != VINF_EM_RAW_EMULATE_INSTR_GDT_FAULT) ) \
794	\|\| ( (a_rcStrict2) == VINF_EM_RAW_EMULATE_INSTR_GDT_FAULT \
795	&& (a_rcStrict) > VINF_EM_RESET) ) \
796	(a_rcStrict) = (a_rcStrict2); \
797	} while (0)
798	#endif
799
800	VMMDECL(VBOXSTRICTRC) PGMPhysRead(PVMCC pVM, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead, PGMACCESSORIGIN enmOrigin);
801	VMMDECL(VBOXSTRICTRC) PGMPhysWrite(PVMCC pVM, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite, PGMACCESSORIGIN enmOrigin);
802	VMMDECL(VBOXSTRICTRC) PGMPhysReadGCPtr(PVMCPUCC pVCpu, void *pvDst, RTGCPTR GCPtrSrc, size_t cb, PGMACCESSORIGIN enmOrigin);
803	VMMDECL(VBOXSTRICTRC) PGMPhysWriteGCPtr(PVMCPUCC pVCpu, RTGCPTR GCPtrDst, const void *pvSrc, size_t cb, PGMACCESSORIGIN enmOrigin);
804
805	VMMDECL(int) PGMPhysSimpleReadGCPhys(PVMCC pVM, void *pvDst, RTGCPHYS GCPhysSrc, size_t cb);
806	VMMDECL(int) PGMPhysSimpleWriteGCPhys(PVMCC pVM, RTGCPHYS GCPhysDst, const void *pvSrc, size_t cb);
807	VMMDECL(int) PGMPhysSimpleReadGCPtr(PVMCPUCC pVCpu, void *pvDst, RTGCPTR GCPtrSrc, size_t cb);
808	VMMDECL(int) PGMPhysSimpleWriteGCPtr(PVMCPUCC pVCpu, RTGCPTR GCPtrDst, const void *pvSrc, size_t cb);
809	VMMDECL(int) PGMPhysSimpleDirtyWriteGCPtr(PVMCPUCC pVCpu, RTGCPTR GCPtrDst, const void *pvSrc, size_t cb);
810
811	VMM_INT_DECL(int) PGMPhysIemGCPhys2Ptr(PVMCC pVM, PVMCPUCC pVCpu, RTGCPHYS GCPhys, bool fWritable, bool fByPassHandlers, void **ppv, PPGMPAGEMAPLOCK pLock);
812	VMM_INT_DECL(int) PGMPhysIemQueryAccess(PVMCC pVM, RTGCPHYS GCPhys, bool fWritable, bool fByPassHandlers);
813	VMM_INT_DECL(int) PGMPhysIemGCPhys2PtrNoLock(PVMCC pVM, PVMCPUCC pVCpu, RTGCPHYS GCPhys, uint64_t const volatile *puTlbPhysRev,
814	#if defined(IN_RC)
815	R3PTRTYPE(uint8_t ) ppb,
816	#else
817	R3R0PTRTYPE(uint8_t ) ppb,
818	#endif
819	uint64_t *pfTlb);
820	/** @name Flags returned by PGMPhysIemGCPhys2PtrNoLock
821	* @{ */
822	#define PGMIEMGCPHYS2PTR_F_NO_WRITE RT_BIT_32(3) /*< Not writable (IEMTLBE_F_PG_NO_WRITE). /
823	#define PGMIEMGCPHYS2PTR_F_NO_READ RT_BIT_32(4) /*< Not readable (IEMTLBE_F_PG_NO_READ). /
824	#define PGMIEMGCPHYS2PTR_F_NO_MAPPINGR3 RT_BIT_32(7) /*< No ring-3 mapping (IEMTLBE_F_NO_MAPPINGR3). /
825	/** @} */
826
827	/** Information returned by PGMPhysNemQueryPageInfo. */
828	typedef struct PGMPHYSNEMPAGEINFO
829	{
830	/** The host physical address of the page, NIL_HCPHYS if invalid page. */
831	RTHCPHYS HCPhys;
832	/** The NEM access mode for the page, NEM_PAGE_PROT_XXX */
833	uint32_t fNemProt : 8;
834	/** The NEM state associated with the PAGE. */
835	uint32_t u2NemState : 2;
836	/** The NEM state associated with the PAGE before pgmPhysPageMakeWritable was called. */
837	uint32_t u2OldNemState : 2;
838	/** Set if the page has handler. */
839	uint32_t fHasHandlers : 1;
840	/** Set if is the zero page backing it. */
841	uint32_t fZeroPage : 1;
842	/** Set if the page has handler. */
843	PGMPAGETYPE enmType;
844	} PGMPHYSNEMPAGEINFO;
845	/** Pointer to page information for NEM. */
846	typedef PGMPHYSNEMPAGEINFO *PPGMPHYSNEMPAGEINFO;
847	/**
848	* Callback for checking that the page is in sync while under the PGM lock.
849	*
850	* NEM passes this callback to PGMPhysNemQueryPageInfo to check that the page is
851	* in-sync between PGM and the native hypervisor API in an atomic fashion.
852	*
853	* @returns VBox status code.
854	* @param pVM The cross context VM structure.
855	* @param pVCpu The cross context per virtual CPU structure. Optional,
856	* see PGMPhysNemQueryPageInfo.
857	* @param GCPhys The guest physical address (not A20 masked).
858	* @param pInfo The page info structure. This function updates the
859	* u2NemState memory and the caller will update the PGMPAGE
860	* copy accordingly.
861	* @param pvUser Callback user argument.
862	*/
863	typedef DECLCALLBACKTYPE(int, FNPGMPHYSNEMCHECKPAGE,(PVMCC pVM, PVMCPUCC pVCpu, RTGCPHYS GCPhys, PPGMPHYSNEMPAGEINFO pInfo, void *pvUser));
864	/** Pointer to a FNPGMPHYSNEMCHECKPAGE function. */
865	typedef FNPGMPHYSNEMCHECKPAGE *PFNPGMPHYSNEMCHECKPAGE;
866
867	VMM_INT_DECL(int) PGMPhysNemPageInfoChecker(PVMCC pVM, PVMCPUCC pVCpu, RTGCPHYS GCPhys, bool fMakeWritable,
868	PPGMPHYSNEMPAGEINFO pInfo, PFNPGMPHYSNEMCHECKPAGE pfnChecker, void *pvUser);
869
870	/**
871	* Callback for use with PGMPhysNemEnumPagesByState.
872	* @returns VBox status code.
873	* Failure status will stop enumeration immediately and return.
874	* @param pVM The cross context VM structure.
875	* @param pVCpu The cross context per virtual CPU structure. Optional,
876	* see PGMPhysNemEnumPagesByState.
877	* @param GCPhys The guest physical address (not A20 masked).
878	* @param pu2NemState Pointer to variable with the NEM state. This can be
879	* update.
880	* @param pvUser The user argument.
881	*/
882	typedef DECLCALLBACKTYPE(int, FNPGMPHYSNEMENUMCALLBACK,(PVMCC pVM, PVMCPUCC pVCpu, RTGCPHYS GCPhys,
883	uint8_t pu2NemState, void pvUser));
884	/** Pointer to a FNPGMPHYSNEMENUMCALLBACK function. */
885	typedef FNPGMPHYSNEMENUMCALLBACK *PFNPGMPHYSNEMENUMCALLBACK;
886	VMM_INT_DECL(int) PGMPhysNemEnumPagesByState(PVMCC pVM, PVMCPUCC VCpu, uint8_t uMinState,
887	PFNPGMPHYSNEMENUMCALLBACK pfnCallback, void *pvUser);
888
889
890	#ifdef VBOX_STRICT
891	VMMDECL(unsigned) PGMAssertHandlerAndFlagsInSync(PVMCC pVM);
892	VMMDECL(unsigned) PGMAssertNoMappingConflicts(PVM pVM);
893	VMMDECL(unsigned) PGMAssertCR3(PVMCC pVM, PVMCPUCC pVCpu, uint64_t cr3, uint64_t cr4);
894	#endif /* VBOX_STRICT */
895
896	VMMDECL(int) PGMSetLargePageUsage(PVMCC pVM, bool fUseLargePages);
897
898	/**
899	* Query large page usage state
900	*
901	* @returns 0 - disabled, 1 - enabled
902	* @param pVM The cross context VM structure.
903	*/
904	#define PGMIsUsingLargePages(pVM) ((pVM)->pgm.s.fUseLargePages)
905
906
907	#ifdef IN_RING0
908	/** @defgroup grp_pgm_r0 The PGM Host Context Ring-0 API
909	* @{
910	*/
911	VMMR0_INT_DECL(int) PGMR0InitPerVMData(PGVM pGVM);
912	VMMR0_INT_DECL(int) PGMR0InitVM(PGVM pGVM);
913	VMMR0_INT_DECL(void) PGMR0CleanupVM(PGVM pGVM);
914	VMMR0_INT_DECL(int) PGMR0PhysAllocateHandyPages(PGVM pGVM, VMCPUID idCpu);
915	VMMR0_INT_DECL(int) PGMR0PhysFlushHandyPages(PGVM pGVM, VMCPUID idCpu);
916	VMMR0_INT_DECL(int) PGMR0PhysAllocateLargePage(PGVM pGVM, VMCPUID idCpu, RTGCPHYS GCPhys);
917	VMMR0_INT_DECL(int) PGMR0PhysMMIO2MapKernel(PGVM pGVM, PPDMDEVINS pDevIns, PGMMMIO2HANDLE hMmio2,
918	size_t offSub, size_t cbSub, void **ppvMapping);
919	VMMR0_INT_DECL(int) PGMR0PhysSetupIoMmu(PGVM pGVM);
920	VMMR0DECL(int) PGMR0SharedModuleCheck(PVMCC pVM, PGVM pGVM, VMCPUID idCpu, PGMMSHAREDMODULE pModule,
921	PCRTGCPTR64 paRegionsGCPtrs);
922	VMMR0DECL(int) PGMR0Trap0eHandlerNestedPaging(PGVM pGVM, PGVMCPU pGVCpu, PGMMODE enmShwPagingMode, RTGCUINT uErr,
923	PCPUMCTXCORE pRegFrame, RTGCPHYS pvFault);
924	VMMR0DECL(VBOXSTRICTRC) PGMR0Trap0eHandlerNPMisconfig(PGVM pGVM, PGVMCPU pGVCpu, PGMMODE enmShwPagingMode,
925	PCPUMCTXCORE pRegFrame, RTGCPHYS GCPhysFault, uint32_t uErr);
926	VMMR0_INT_DECL(int) PGMR0PoolGrow(PGVM pGVM, VMCPUID idCpu);
927	/** @} */
928	#endif /* IN_RING0 */
929
930
931
932	#ifdef IN_RING3
933	/** @defgroup grp_pgm_r3 The PGM Host Context Ring-3 API
934	* @{
935	*/
936	VMMR3_INT_DECL(void) PGMR3EnableNemMode(PVM pVM);
937	VMMR3_INT_DECL(bool) PGMR3IsNemModeEnabled(PVM pVM);
938	VMMR3DECL(int) PGMR3Init(PVM pVM);
939	VMMR3DECL(int) PGMR3InitFinalize(PVM pVM);
940	VMMR3_INT_DECL(int) PGMR3InitCompleted(PVM pVM, VMINITCOMPLETED enmWhat);
941	VMMR3DECL(void) PGMR3Relocate(PVM pVM, RTGCINTPTR offDelta);
942	VMMR3DECL(void) PGMR3ResetCpu(PVM pVM, PVMCPU pVCpu);
943	VMMR3_INT_DECL(void) PGMR3Reset(PVM pVM);
944	VMMR3_INT_DECL(void) PGMR3ResetNoMorePhysWritesFlag(PVM pVM);
945	VMMR3_INT_DECL(void) PGMR3MemSetup(PVM pVM, bool fReset);
946	VMMR3DECL(int) PGMR3Term(PVM pVM);
947
948	VMMR3DECL(int) PGMR3PhysRegisterRam(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, const char *pszDesc);
949	VMMR3DECL(int) PGMR3PhysChangeMemBalloon(PVM pVM, bool fInflate, unsigned cPages, RTGCPHYS *paPhysPage);
950	VMMR3DECL(int) PGMR3PhysWriteProtectRAM(PVM pVM);
951	VMMR3DECL(uint32_t) PGMR3PhysGetRamRangeCount(PVM pVM);
952	VMMR3DECL(int) PGMR3PhysGetRange(PVM pVM, uint32_t iRange, PRTGCPHYS pGCPhysStart, PRTGCPHYS pGCPhysLast,
953	const char *ppszDesc, bool pfIsMmio);
954	VMMR3DECL(int) PGMR3QueryMemoryStats(PUVM pUVM, uint64_t pcbTotalMem, uint64_t pcbPrivateMem, uint64_t pcbSharedMem, uint64_t pcbZeroMem);
955	VMMR3DECL(int) PGMR3QueryGlobalMemoryStats(PUVM pUVM, uint64_t pcbAllocMem, uint64_t pcbFreeMem, uint64_t pcbBallonedMem, uint64_t pcbSharedMem);
956
957	VMMR3DECL(int) PGMR3PhysMMIORegister(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, PGMPHYSHANDLERTYPE hType,
958	RTR3PTR pvUserR3, RTR0PTR pvUserR0, RTRCPTR pvUserRC, const char *pszDesc);
959	VMMR3DECL(int) PGMR3PhysMMIODeregister(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb);
960
961	/** @name PGMPHYS_MMIO2_FLAGS_XXX - MMIO2 registration flags.
962	* @see PGMR3PhysMmio2Register, PDMDevHlpMmio2Create
963	* @{ */
964	/** Track dirty pages.
965	* @see PGMR3PhysMmio2QueryAndResetDirtyBitmap(), PGMR3PhysMmio2ControlDirtyPageTracking(). */
966	#define PGMPHYS_MMIO2_FLAGS_TRACK_DIRTY_PAGES RT_BIT_32(0)
967	/** Valid flags. */
968	#define PGMPHYS_MMIO2_FLAGS_VALID_MASK UINT32_C(0x00000001)
969	/** @} */
970
971	VMMR3_INT_DECL(int) PGMR3PhysMmio2Register(PVM pVM, PPDMDEVINS pDevIns, uint32_t iSubDev, uint32_t iRegion, RTGCPHYS cb,
972	uint32_t fFlags, const char pszDesc, void ppv, PGMMMIO2HANDLE phRegion);
973	VMMR3_INT_DECL(int) PGMR3PhysMmio2Deregister(PVM pVM, PPDMDEVINS pDevIns, PGMMMIO2HANDLE hMmio2);
974	VMMR3_INT_DECL(int) PGMR3PhysMmio2Map(PVM pVM, PPDMDEVINS pDevIns, PGMMMIO2HANDLE hMmio2, RTGCPHYS GCPhys);
975	VMMR3_INT_DECL(int) PGMR3PhysMmio2Unmap(PVM pVM, PPDMDEVINS pDevIns, PGMMMIO2HANDLE hMmio2, RTGCPHYS GCPhys);
976	VMMR3_INT_DECL(int) PGMR3PhysMmio2Reduce(PVM pVM, PPDMDEVINS pDevIns, PGMMMIO2HANDLE hMmio2, RTGCPHYS cbRegion);
977	VMMR3_INT_DECL(int) PGMR3PhysMmio2ValidateHandle(PVM pVM, PPDMDEVINS pDevIns, PGMMMIO2HANDLE hMmio2);
978	VMMR3_INT_DECL(RTGCPHYS) PGMR3PhysMmio2GetMappingAddress(PVM pVM, PPDMDEVINS pDevIns, PGMMMIO2HANDLE hMmio2);
979	VMMR3_INT_DECL(int) PGMR3PhysMmio2ChangeRegionNo(PVM pVM, PPDMDEVINS pDevIns, PGMMMIO2HANDLE hMmio2, uint32_t iNewRegion);
980	VMMR3_INT_DECL(int) PGMR3PhysMmio2QueryAndResetDirtyBitmap(PVM pVM, PPDMDEVINS pDevIns, PGMMMIO2HANDLE hMmio2,
981	void *pvBitmap, size_t cbBitmap);
982	VMMR3_INT_DECL(int) PGMR3PhysMmio2ControlDirtyPageTracking(PVM pVM, PPDMDEVINS pDevIns, PGMMMIO2HANDLE hMmio2, bool fEnabled);
983
984	/** @name PGMPHYS_ROM_FLAGS_XXX - ROM registration flags.
985	* @see PGMR3PhysRegisterRom, PDMDevHlpROMRegister
986	* @{ */
987	/** Inidicates that ROM shadowing should be enabled. */
988	#define PGMPHYS_ROM_FLAGS_SHADOWED UINT8_C(0x01)
989	/** Indicates that what pvBinary points to won't go away
990	* and can be used for strictness checks. */
991	#define PGMPHYS_ROM_FLAGS_PERMANENT_BINARY UINT8_C(0x02)
992	/** Indicates that the ROM is allowed to be missing from saved state.
993	* @note This is a hack for EFI, see @bugref{6940} */
994	#define PGMPHYS_ROM_FLAGS_MAYBE_MISSING_FROM_STATE UINT8_C(0x04)
995	/** Valid flags. */
996	#define PGMPHYS_ROM_FLAGS_VALID_MASK UINT8_C(0x07)
997	/** @} */
998
999	VMMR3DECL(int) PGMR3PhysRomRegister(PVM pVM, PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTGCPHYS cb,
1000	const void pvBinary, uint32_t cbBinary, uint8_t fFlags, const char pszDesc);
1001	VMMR3DECL(int) PGMR3PhysRomProtect(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, PGMROMPROT enmProt);
1002	VMMDECL(void) PGMR3PhysSetA20(PVMCPU pVCpu, bool fEnable);
1003
1004	VMMR3_INT_DECL(int) PGMR3HandlerPhysicalTypeRegisterEx(PVM pVM, PGMPHYSHANDLERKIND enmKind, bool fKeepPgmLock,
1005	PFNPGMPHYSHANDLER pfnHandlerR3,
1006	R0PTRTYPE(PFNPGMPHYSHANDLER) pfnHandlerR0,
1007	R0PTRTYPE(PFNPGMRZPHYSPFHANDLER) pfnPfHandlerR0,
1008	const char *pszDesc, PPGMPHYSHANDLERTYPE phType);
1009	VMMR3DECL(int) PGMR3HandlerPhysicalTypeRegister(PVM pVM, PGMPHYSHANDLERKIND enmKind, bool fKeepPgmLock,
1010	R3PTRTYPE(PFNPGMPHYSHANDLER) pfnHandlerR3,
1011	const char pszModR0, const char pszHandlerR0, const char *pszPfHandlerR0,
1012	const char pszModRC, const char pszHandlerRC, const char *pszPfHandlerRC,
1013	const char *pszDesc,
1014	PPGMPHYSHANDLERTYPE phType);
1015	VMMR3_INT_DECL(int) PGMR3PoolGrow(PVM pVM, PVMCPU pVCpu);
1016
1017	VMMR3DECL(int) PGMR3PhysTlbGCPhys2Ptr(PVM pVM, RTGCPHYS GCPhys, bool fWritable, void **ppv);
1018	VMMR3DECL(uint8_t) PGMR3PhysReadU8(PVM pVM, RTGCPHYS GCPhys, PGMACCESSORIGIN enmOrigin);
1019	VMMR3DECL(uint16_t) PGMR3PhysReadU16(PVM pVM, RTGCPHYS GCPhys, PGMACCESSORIGIN enmOrigin);
1020	VMMR3DECL(uint32_t) PGMR3PhysReadU32(PVM pVM, RTGCPHYS GCPhys, PGMACCESSORIGIN enmOrigin);
1021	VMMR3DECL(uint64_t) PGMR3PhysReadU64(PVM pVM, RTGCPHYS GCPhys, PGMACCESSORIGIN enmOrigin);
1022	VMMR3DECL(void) PGMR3PhysWriteU8(PVM pVM, RTGCPHYS GCPhys, uint8_t Value, PGMACCESSORIGIN enmOrigin);
1023	VMMR3DECL(void) PGMR3PhysWriteU16(PVM pVM, RTGCPHYS GCPhys, uint16_t Value, PGMACCESSORIGIN enmOrigin);
1024	VMMR3DECL(void) PGMR3PhysWriteU32(PVM pVM, RTGCPHYS GCPhys, uint32_t Value, PGMACCESSORIGIN enmOrigin);
1025	VMMR3DECL(void) PGMR3PhysWriteU64(PVM pVM, RTGCPHYS GCPhys, uint64_t Value, PGMACCESSORIGIN enmOrigin);
1026	VMMR3DECL(int) PGMR3PhysReadExternal(PVM pVM, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead, PGMACCESSORIGIN enmOrigin);
1027	VMMR3DECL(int) PGMR3PhysWriteExternal(PVM pVM, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite, PGMACCESSORIGIN enmOrigin);
1028	VMMR3DECL(int) PGMR3PhysGCPhys2CCPtrExternal(PVM pVM, RTGCPHYS GCPhys, void **ppv, PPGMPAGEMAPLOCK pLock);
1029	VMMR3DECL(int) PGMR3PhysGCPhys2CCPtrReadOnlyExternal(PVM pVM, RTGCPHYS GCPhys, void const **ppv, PPGMPAGEMAPLOCK pLock);
1030	VMMR3DECL(int) PGMR3PhysBulkGCPhys2CCPtrExternal(PVM pVM, uint32_t cPages, PCRTGCPHYS paGCPhysPages,
1031	void **papvPages, PPGMPAGEMAPLOCK paLocks);
1032	VMMR3DECL(int) PGMR3PhysBulkGCPhys2CCPtrReadOnlyExternal(PVM pVM, uint32_t cPages, PCRTGCPHYS paGCPhysPages,
1033	void const **papvPages, PPGMPAGEMAPLOCK paLocks);
1034	VMMR3DECL(void) PGMR3PhysChunkInvalidateTLB(PVM pVM);
1035	VMMR3DECL(int) PGMR3PhysAllocateHandyPages(PVM pVM);
1036
1037	VMMR3DECL(int) PGMR3CheckIntegrity(PVM pVM);
1038
1039	VMMR3DECL(int) PGMR3DbgR3Ptr2GCPhys(PUVM pUVM, RTR3PTR R3Ptr, PRTGCPHYS pGCPhys);
1040	VMMR3DECL(int) PGMR3DbgR3Ptr2HCPhys(PUVM pUVM, RTR3PTR R3Ptr, PRTHCPHYS pHCPhys);
1041	VMMR3DECL(int) PGMR3DbgHCPhys2GCPhys(PUVM pUVM, RTHCPHYS HCPhys, PRTGCPHYS pGCPhys);
1042	VMMR3_INT_DECL(int) PGMR3DbgReadGCPhys(PVM pVM, void pvDst, RTGCPHYS GCPhysSrc, size_t cb, uint32_t fFlags, size_t pcbRead);
1043	VMMR3_INT_DECL(int) PGMR3DbgWriteGCPhys(PVM pVM, RTGCPHYS GCPhysDst, const void pvSrc, size_t cb, uint32_t fFlags, size_t pcbWritten);
1044	VMMR3_INT_DECL(int) PGMR3DbgReadGCPtr(PVM pVM, void pvDst, RTGCPTR GCPtrSrc, size_t cb, uint32_t fFlags, size_t pcbRead);
1045	VMMR3_INT_DECL(int) PGMR3DbgWriteGCPtr(PVM pVM, RTGCPTR GCPtrDst, void const pvSrc, size_t cb, uint32_t fFlags, size_t pcbWritten);
1046	VMMR3_INT_DECL(int) PGMR3DbgScanPhysical(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cbRange, RTGCPHYS GCPhysAlign, const uint8_t *pabNeedle, size_t cbNeedle, PRTGCPHYS pGCPhysHit);
1047	VMMR3_INT_DECL(int) PGMR3DbgScanVirtual(PVM pVM, PVMCPU pVCpu, RTGCPTR GCPtr, RTGCPTR cbRange, RTGCPTR GCPtrAlign, const uint8_t *pabNeedle, size_t cbNeedle, PRTGCUINTPTR pGCPhysHit);
1048	VMMR3_INT_DECL(int) PGMR3DumpHierarchyShw(PVM pVM, uint64_t cr3, uint32_t fFlags, uint64_t u64FirstAddr, uint64_t u64LastAddr, uint32_t cMaxDepth, PCDBGFINFOHLP pHlp);
1049	VMMR3_INT_DECL(int) PGMR3DumpHierarchyGst(PVM pVM, uint64_t cr3, uint32_t fFlags, RTGCPTR FirstAddr, RTGCPTR LastAddr, uint32_t cMaxDepth, PCDBGFINFOHLP pHlp);
1050
1051
1052	/** @name Page sharing
1053	* @{ */
1054	VMMR3DECL(int) PGMR3SharedModuleRegister(PVM pVM, VBOXOSFAMILY enmGuestOS, char pszModuleName, char pszVersion,
1055	RTGCPTR GCBaseAddr, uint32_t cbModule,
1056	uint32_t cRegions, VMMDEVSHAREDREGIONDESC const *paRegions);
1057	VMMR3DECL(int) PGMR3SharedModuleUnregister(PVM pVM, char pszModuleName, char pszVersion,
1058	RTGCPTR GCBaseAddr, uint32_t cbModule);
1059	VMMR3DECL(int) PGMR3SharedModuleCheckAll(PVM pVM);
1060	VMMR3DECL(int) PGMR3SharedModuleGetPageState(PVM pVM, RTGCPTR GCPtrPage, bool pfShared, uint64_t pfPageFlags);
1061	/** @} */
1062
1063	/** @} */
1064	#endif /* IN_RING3 */
1065
1066	RT_C_DECLS_END
1067
1068	/** @} */
1069	#endif /* !VBOX_INCLUDED_vmm_pgm_h */
1070

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source: vbox/trunk/include/VBox/vmm/pgm.h@ 92541

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