pgm.h@ 93651

Last change on this file since 93651 was 93651, checked in by vboxsync, 3 years ago
VMM/PGM,*: Split the physical access handler type registration into separate ring-0 and ring-3 steps, expanding the type to 64-bit. [build fixes] bugref:10094
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1	/** @file
2	* PGM - Page Monitor / Monitor.
3	*/
4
5	/*
6	* Copyright (C) 2006-2022 Oracle Corporation
7	*
8	* This file is part of VirtualBox Open Source Edition (OSE), as
9	* available from http://www.virtualbox.org. This file is free software;
10	* you can redistribute it and/or modify it under the terms of the GNU
11	* General Public License (GPL) as published by the Free Software
12	* Foundation, in version 2 as it comes in the "COPYING" file of the
13	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15	*
16	* The contents of this file may alternatively be used under the terms
17	* of the Common Development and Distribution License Version 1.0
18	* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19	* VirtualBox OSE distribution, in which case the provisions of the
20	* CDDL are applicable instead of those of the GPL.
21	*
22	* You may elect to license modified versions of this file under the
23	* terms and conditions of either the GPL or the CDDL or both.
24	*/
25
26	#ifndef VBOX_INCLUDED_vmm_pgm_h
27	#define VBOX_INCLUDED_vmm_pgm_h
28	#ifndef RT_WITHOUT_PRAGMA_ONCE
29	# pragma once
30	#endif
31
32	#include <VBox/types.h>
33	#include <VBox/sup.h>
34	#include <VBox/vmm/vmapi.h>
35	#include <VBox/vmm/gmm.h> /* for PGMMREGISTERSHAREDMODULEREQ */
36	#include <VBox/vmm/hm_vmx.h>
37	#include <iprt/x86.h>
38	#include <VBox/param.h>
39
40	RT_C_DECLS_BEGIN
41
42	/** @defgroup grp_pgm The Page Monitor / Manager API
43	* @ingroup grp_vmm
44	* @{
45	*/
46
47	/**
48	* FNPGMRELOCATE callback mode.
49	*/
50	typedef enum PGMRELOCATECALL
51	{
52	/** The callback is for checking if the suggested address is suitable. */
53	PGMRELOCATECALL_SUGGEST = 1,
54	/** The callback is for executing the relocation. */
55	PGMRELOCATECALL_RELOCATE
56	} PGMRELOCATECALL;
57
58
59	/**
60	* Callback function which will be called when PGM is trying to find
61	* a new location for the mapping.
62	*
63	* The callback is called in two modes, 1) the check mode and 2) the relocate mode.
64	* In 1) the callback should say if it objects to a suggested new location. If it
65	* accepts the new location, it is called again for doing it's relocation.
66	*
67	*
68	* @returns true if the location is ok.
69	* @returns false if another location should be found.
70	* @param pVM The cross context VM structure.
71	* @param GCPtrOld The old virtual address.
72	* @param GCPtrNew The new virtual address.
73	* @param enmMode Used to indicate the callback mode.
74	* @param pvUser User argument.
75	* @remark The return value is no a failure indicator, it's an acceptance
76	* indicator. Relocation can not fail!
77	*/
78	typedef DECLCALLBACKTYPE(bool, FNPGMRELOCATE,(PVM pVM, RTGCPTR GCPtrOld, RTGCPTR GCPtrNew, PGMRELOCATECALL enmMode, void *pvUser));
79	/** Pointer to a relocation callback function. */
80	typedef FNPGMRELOCATE *PFNPGMRELOCATE;
81
82
83	/**
84	* Memory access origin.
85	*/
86	typedef enum PGMACCESSORIGIN
87	{
88	/** Invalid zero value. */
89	PGMACCESSORIGIN_INVALID = 0,
90	/** IEM is access memory. */
91	PGMACCESSORIGIN_IEM,
92	/** HM is access memory. */
93	PGMACCESSORIGIN_HM,
94	/** Some device is access memory. */
95	PGMACCESSORIGIN_DEVICE,
96	/** Someone debugging is access memory. */
97	PGMACCESSORIGIN_DEBUGGER,
98	/** SELM is access memory. */
99	PGMACCESSORIGIN_SELM,
100	/** FTM is access memory. */
101	PGMACCESSORIGIN_FTM,
102	/** REM is access memory. */
103	PGMACCESSORIGIN_REM,
104	/** IOM is access memory. */
105	PGMACCESSORIGIN_IOM,
106	/** End of valid values. */
107	PGMACCESSORIGIN_END,
108	/** Type size hack. */
109	PGMACCESSORIGIN_32BIT_HACK = 0x7fffffff
110	} PGMACCESSORIGIN;
111
112
113	/**
114	* Physical page access handler kind.
115	*/
116	typedef enum PGMPHYSHANDLERKIND
117	{
118	/** Invalid zero value. */
119	PGMPHYSHANDLERKIND_INVALID = 0,
120	/** MMIO range. Pages are not present, all access is done in interpreter or recompiler. */
121	PGMPHYSHANDLERKIND_MMIO,
122	/** Handler all write access to a physical page range. */
123	PGMPHYSHANDLERKIND_WRITE,
124	/** Handler all access to a physical page range. */
125	PGMPHYSHANDLERKIND_ALL,
126	/** End of the valid values. */
127	PGMPHYSHANDLERKIND_END,
128	/** Type size hack. */
129	PGMPHYSHANDLERKIND_32BIT_HACK = 0x7fffffff
130	} PGMPHYSHANDLERKIND;
131
132	/**
133	* Guest Access type
134	*/
135	typedef enum PGMACCESSTYPE
136	{
137	/** Read access. */
138	PGMACCESSTYPE_READ = 1,
139	/** Write access. */
140	PGMACCESSTYPE_WRITE
141	} PGMACCESSTYPE;
142
143
144	/** @def PGM_ALL_CB_DECL
145	* Macro for declaring a handler callback for all contexts. The handler
146	* callback is static in ring-3, and exported in RC and R0.
147	* @sa PGM_ALL_CB2_DECL.
148	*/
149	#if defined(IN_RC) \|\| defined(IN_RING0)
150	# ifdef __cplusplus
151	# define PGM_ALL_CB_DECL(type) extern "C" DECLCALLBACK(DECLEXPORT(type))
152	# else
153	# define PGM_ALL_CB_DECL(type) DECLCALLBACK(DECLEXPORT(type))
154	# endif
155	#else
156	# define PGM_ALL_CB_DECL(type) static DECLCALLBACK(type)
157	#endif
158
159	/** @def PGM_ALL_CB2_DECL
160	* Macro for declaring a handler callback for all contexts. The handler
161	* callback is hidden in ring-3, and exported in RC and R0.
162	* @sa PGM_ALL_CB2_DECL.
163	*/
164	#if defined(IN_RC) \|\| defined(IN_RING0)
165	# ifdef __cplusplus
166	# define PGM_ALL_CB2_DECL(type) extern "C" DECLCALLBACK(DECLEXPORT(type))
167	# else
168	# define PGM_ALL_CB2_DECL(type) DECLCALLBACK(DECLEXPORT(type))
169	# endif
170	#else
171	# define PGM_ALL_CB2_DECL(type) DECL_HIDDEN_CALLBACK(type)
172	#endif
173
174	/** @def PGM_ALL_CB2_PROTO
175	* Macro for declaring a handler callback for all contexts. The handler
176	* callback is hidden in ring-3, and exported in RC and R0.
177	* @param fnType The callback function type.
178	* @sa PGM_ALL_CB2_DECL.
179	*/
180	#if defined(IN_RC) \|\| defined(IN_RING0)
181	# ifdef __cplusplus
182	# define PGM_ALL_CB2_PROTO(fnType) extern "C" DECLEXPORT(fnType)
183	# else
184	# define PGM_ALL_CB2_PROTO(fnType) DECLEXPORT(fnType)
185	# endif
186	#else
187	# define PGM_ALL_CB2_PROTO(fnType) DECLHIDDEN(fnType)
188	#endif
189
190
191	/**
192	* \#PF Handler callback for physical access handler ranges in RC and R0.
193	*
194	* @returns Strict VBox status code (appropriate for ring-0 and raw-mode).
195	* @param pVM The cross context VM structure.
196	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
197	* @param uErrorCode CPU Error code.
198	* @param pRegFrame Trap register frame.
199	* NULL on DMA and other non CPU access.
200	* @param pvFault The fault address (cr2).
201	* @param GCPhysFault The GC physical address corresponding to pvFault.
202	* @param uUser User argument (not a pointer).
203	* @thread EMT(pVCpu)
204	*/
205	typedef DECLCALLBACKTYPE(VBOXSTRICTRC, FNPGMRZPHYSPFHANDLER,(PVMCC pVM, PVMCPUCC pVCpu, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame,
206	RTGCPTR pvFault, RTGCPHYS GCPhysFault, uint64_t uUser));
207	/** Pointer to PGM access callback. */
208	typedef FNPGMRZPHYSPFHANDLER *PFNPGMRZPHYSPFHANDLER;
209
210
211	/**
212	* Access handler callback for physical access handler ranges.
213	*
214	* The handler can not raise any faults, it's mainly for monitoring write access
215	* to certain pages (like MMIO).
216	*
217	* @returns Strict VBox status code in ring-0 and raw-mode context, in ring-3
218	* the only supported informational status code is
219	* VINF_PGM_HANDLER_DO_DEFAULT.
220	* @retval VINF_SUCCESS if the handler have carried out the operation.
221	* @retval VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the
222	* access operation.
223	* @retval VINF_EM_XXX in ring-0 and raw-mode context.
224	*
225	* @param pVM The cross context VM structure.
226	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
227	* @param GCPhys The physical address the guest is writing to.
228	* @param pvPhys The HC mapping of that address.
229	* @param pvBuf What the guest is reading/writing.
230	* @param cbBuf How much it's reading/writing.
231	* @param enmAccessType The access type.
232	* @param enmOrigin The origin of this call.
233	* @param uUser User argument (not a pointer).
234	* @thread EMT(pVCpu)
235	*/
236	typedef DECLCALLBACKTYPE(VBOXSTRICTRC, FNPGMPHYSHANDLER,(PVMCC pVM, PVMCPUCC pVCpu, RTGCPHYS GCPhys, void *pvPhys,
237	void *pvBuf, size_t cbBuf, PGMACCESSTYPE enmAccessType,
238	PGMACCESSORIGIN enmOrigin, uint64_t uUser));
239	/** Pointer to PGM access callback. */
240	typedef FNPGMPHYSHANDLER *PFNPGMPHYSHANDLER;
241
242
243	/**
244	* Paging mode.
245	*
246	* @note Part of saved state. Change with extreme care.
247	*/
248	typedef enum PGMMODE
249	{
250	/** The usual invalid value. */
251	PGMMODE_INVALID = 0,
252	/** Real mode. */
253	PGMMODE_REAL,
254	/** Protected mode, no paging. */
255	PGMMODE_PROTECTED,
256	/** 32-bit paging. */
257	PGMMODE_32_BIT,
258	/** PAE paging. */
259	PGMMODE_PAE,
260	/** PAE paging with NX enabled. */
261	PGMMODE_PAE_NX,
262	/** 64-bit AMD paging (long mode). */
263	PGMMODE_AMD64,
264	/** 64-bit AMD paging (long mode) with NX enabled. */
265	PGMMODE_AMD64_NX,
266	/** 32-bit nested paging mode (shadow only; guest physical to host physical). */
267	PGMMODE_NESTED_32BIT,
268	/** PAE nested paging mode (shadow only; guest physical to host physical). */
269	PGMMODE_NESTED_PAE,
270	/** AMD64 nested paging mode (shadow only; guest physical to host physical). */
271	PGMMODE_NESTED_AMD64,
272	/** Extended paging (Intel) mode. */
273	PGMMODE_EPT,
274	/** Special mode used by NEM to indicate no shadow paging necessary. */
275	PGMMODE_NONE,
276	/** The max number of modes */
277	PGMMODE_MAX,
278	/** 32bit hackishness. */
279	PGMMODE_32BIT_HACK = 0x7fffffff
280	} PGMMODE;
281
282	/**
283	* Second level address translation (SLAT) mode.
284	*/
285	typedef enum PGMSLAT
286	{
287	/** The usual invalid value. */
288	PGMSLAT_INVALID = 0,
289	/** No second level translation. */
290	PGMSLAT_DIRECT,
291	/** Intel Extended Page Tables (EPT). */
292	PGMSLAT_EPT,
293	/** AMD-V Nested Paging 32-bit. */
294	PGMSLAT_32BIT,
295	/** AMD-V Nested Paging PAE. */
296	PGMSLAT_PAE,
297	/** AMD-V Nested Paging 64-bit. */
298	PGMSLAT_AMD64,
299	/** 32bit hackishness. */
300	PGMSLAT_32BIT_HACK = 0x7fffffff
301	} PGMSLAT;
302
303
304	/** @name PGMPTWALK::fFailed flags.
305	* These flags indicate the type of a page-walk failure.
306	* @{
307	*/
308	typedef uint32_t PGMWALKFAIL;
309	/** Regular page fault (MBZ since guest Walk code don't set these explicitly). */
310	#define PGM_WALKFAIL_PAGE_FAULT UINT32_C(0)
311	/** EPT violation - Intel. */
312	#define PGM_WALKFAIL_EPT_VIOLATION RT_BIT_32(0)
313	/** EPT violation, convertible to \#VE exception - Intel. */
314	#define PGM_WALKFAIL_EPT_VIOLATION_CONVERTIBLE RT_BIT_32(1)
315	/** EPT misconfiguration - Intel. */
316	#define PGM_WALKFAIL_EPT_MISCONFIG RT_BIT_32(2)
317
318	/** Mask of all EPT induced page-walk failures - Intel. */
319	#define PGM_WALKFAIL_EPT ( PGM_WALKFAIL_EPT_VIOLATION \
320	\| PGM_WALKFAIL_EPT_VIOLATION_CONVERTIBLE \
321	\| PGM_WALKFAIL_EPT_MISCONFIG)
322	/** @} */
323
324
325	/** @name PGMPTATTRS - PGM page-table attributes.
326	*
327	* This is VirtualBox's combined page table attributes. It combines regular page
328	* table and Intel EPT attributes. It's 64-bit in size so there's ample room for
329	* bits added in the future to EPT or regular page tables (for e.g. Protection Key).
330	*
331	* The following bits map 1:1 (shifted by PGM_PTATTRS_EPT_SHIFT) to the Intel EPT
332	* attributes as these are unique to EPT and fit within 64-bits despite the shift:
333	* - EPT_R : Read access.
334	* - EPT_W : Write access.
335	* - EPT_X_SUPER : Execute or execute for supervisor-mode linear addr access.
336	* - EPT_MEMTYPE : EPT memory type.
337	* - EPT_IGNORE_PAT: Ignore PAT memory type.
338	* - EPT_X_USER : Execute access for user-mode linear addresses.
339	*
340	* For regular page tables, the R bit is always 1 (same as P bit).
341	* For Intel EPT, the EPT_R and EPT_W bits are copied to R and W bits respectively.
342	*
343	* The following EPT attributes are mapped to the following positions because they
344	* exist in the regular page tables at these positions OR are exclusive to EPT and
345	* have been mapped to arbitrarily chosen positions:
346	* - EPT_A : Accessed (EPT bit 8 maps to bit 5).
347	* - EPT_D : Dirty (EPT bit 9 maps to bit 6).
348	* - EPT_SUPER_SHW_STACK : Supervisor Shadow Stack (EPT bit 60 maps to bit 24).
349	* - EPT_SUPPRESS_VE_XCPT: Suppress \#VE exception (EPT bit 63 maps to bit 25).
350	*
351	* Bits 12, 11:9 and 43 are deliberately kept unused (correspond to bit PS and bits
352	* 11:9 in the regular page-table structures and to bit 11 in the EPT structures
353	* respectively) as bit 12 is the page-size bit and bits 11:9 are reserved for
354	* use by software and we may want to use/preserve them in the future.
355	*
356	* @{ */
357	typedef uint64_t PGMPTATTRS;
358	/** Pointer to a PGMPTATTRS type. */
359	typedef PGMPTATTRS *PPGMPTATTRS;
360
361	/** Read bit (always 1 for regular PT, copy of EPT_R for EPT). */
362	#define PGM_PTATTRS_R_SHIFT 0
363	#define PGM_PTATTRS_R_MASK RT_BIT_64(PGM_PTATTRS_R_SHIFT)
364	/** Write access bit (aka read/write bit for regular PT). */
365	#define PGM_PTATTRS_W_SHIFT 1
366	#define PGM_PTATTRS_W_MASK RT_BIT_64(PGM_PTATTRS_W_SHIFT)
367	/** User-mode access bit. */
368	#define PGM_PTATTRS_US_SHIFT 2
369	#define PGM_PTATTRS_US_MASK RT_BIT_64(PGM_PTATTRS_US_SHIFT)
370	/** Write through cache bit. */
371	#define PGM_PTATTRS_PWT_SHIFT 3
372	#define PGM_PTATTRS_PWT_MASK RT_BIT_64(PGM_PTATTRS_PWT_SHIFT)
373	/** Cache disabled bit. */
374	#define PGM_PTATTRS_PCD_SHIFT 4
375	#define PGM_PTATTRS_PCD_MASK RT_BIT_64(PGM_PTATTRS_PCD_SHIFT)
376	/** Accessed bit. */
377	#define PGM_PTATTRS_A_SHIFT 5
378	#define PGM_PTATTRS_A_MASK RT_BIT_64(PGM_PTATTRS_A_SHIFT)
379	/** Dirty bit. */
380	#define PGM_PTATTRS_D_SHIFT 6
381	#define PGM_PTATTRS_D_MASK RT_BIT_64(PGM_PTATTRS_D_SHIFT)
382	/** The PAT bit. */
383	#define PGM_PTATTRS_PAT_SHIFT 7
384	#define PGM_PTATTRS_PAT_MASK RT_BIT_64(PGM_PTATTRS_PAT_SHIFT)
385	/** The global bit. */
386	#define PGM_PTATTRS_G_SHIFT 8
387	#define PGM_PTATTRS_G_MASK RT_BIT_64(PGM_PTATTRS_G_SHIFT)
388	/** Reserved (bits 12:9) unused. */
389	#define PGM_PTATTRS_RSVD_12_9_SHIFT 9
390	#define PGM_PTATTRS_RSVD_12_9_MASK UINT64_C(0x0000000000001e00)
391	/** Read access bit - EPT only. */
392	#define PGM_PTATTRS_EPT_R_SHIFT 13
393	#define PGM_PTATTRS_EPT_R_MASK RT_BIT_64(PGM_PTATTRS_EPT_R_SHIFT)
394	/** Write access bit - EPT only. */
395	#define PGM_PTATTRS_EPT_W_SHIFT 14
396	#define PGM_PTATTRS_EPT_W_MASK RT_BIT_64(PGM_PTATTRS_EPT_W_SHIFT)
397	/** Execute or execute access for supervisor-mode linear addresses - EPT only. */
398	#define PGM_PTATTRS_EPT_X_SUPER_SHIFT 15
399	#define PGM_PTATTRS_EPT_X_SUPER_MASK RT_BIT_64(PGM_PTATTRS_EPT_X_SUPER_SHIFT)
400	/** EPT memory type - EPT only. */
401	#define PGM_PTATTRS_EPT_MEMTYPE_SHIFT 16
402	#define PGM_PTATTRS_EPT_MEMTYPE_MASK UINT64_C(0x0000000000070000)
403	/** Ignore PAT memory type - EPT only. */
404	#define PGM_PTATTRS_EPT_IGNORE_PAT_SHIFT 19
405	#define PGM_PTATTRS_EPT_IGNORE_PAT_MASK RT_BIT_64(PGM_PTATTRS_EPT_IGNORE_PAT_SHIFT)
406	/** Reserved (bits 22:20) unused. */
407	#define PGM_PTATTRS_RSVD_22_20_SHIFT 20
408	#define PGM_PTATTRS_RSVD_22_20_MASK UINT64_C(0x0000000000700000)
409	/** Execute access for user-mode linear addresses - EPT only. */
410	#define PGM_PTATTRS_EPT_X_USER_SHIFT 23
411	#define PGM_PTATTRS_EPT_X_USER_MASK RT_BIT_64(PGM_PTATTRS_EPT_X_USER_SHIFT)
412	/** Reserved (bit 23) - unused. */
413	#define PGM_PTATTRS_RSVD_23_SHIFT 24
414	#define PGM_PTATTRS_RSVD_23_MASK UINT64_C(0x0000000001000000)
415	/** Supervisor shadow stack - EPT only. */
416	#define PGM_PTATTRS_EPT_SUPER_SHW_STACK_SHIFT 25
417	#define PGM_PTATTRS_EPT_SUPER_SHW_STACK_MASK RT_BIT_64(PGM_PTATTRS_EPT_SUPER_SHW_STACK_SHIFT)
418	/** Suppress \#VE exception - EPT only. */
419	#define PGM_PTATTRS_EPT_SUPPRESS_VE_XCPT_SHIFT 26
420	#define PGM_PTATTRS_EPT_SUPPRESS_VE_XCPT_MASK RT_BIT_64(PGM_PTATTRS_EPT_SUPPRESS_VE_XCPT_SHIFT)
421	/** Reserved (bits 62:27) - unused. */
422	#define PGM_PTATTRS_RSVD_62_27_SHIFT 27
423	#define PGM_PTATTRS_RSVD_62_27_MASK UINT64_C(0x7ffffffff8000000)
424	/** No-execute bit. */
425	#define PGM_PTATTRS_NX_SHIFT 63
426	#define PGM_PTATTRS_NX_MASK RT_BIT_64(PGM_PTATTRS_NX_SHIFT)
427
428	RT_BF_ASSERT_COMPILE_CHECKS(PGM_PTATTRS_, UINT64_C(0), UINT64_MAX,
429	(R, W, US, PWT, PCD, A, D, PAT, G, RSVD_12_9, EPT_R, EPT_W, EPT_X_SUPER, EPT_MEMTYPE, EPT_IGNORE_PAT,
430	RSVD_22_20, EPT_X_USER, RSVD_23, EPT_SUPER_SHW_STACK, EPT_SUPPRESS_VE_XCPT, RSVD_62_27, NX));
431
432	/** The bit position where the EPT specific attributes begin. */
433	#define PGM_PTATTRS_EPT_SHIFT PGM_PTATTRS_EPT_R_SHIFT
434	/** The mask of EPT bits (bits 26:ATTR_SHIFT). In the future we might choose to
435	* use higher unused bits for something else, in that case adjust this mask. */
436	#define PGM_PTATTRS_EPT_MASK UINT64_C(0x0000000007ffe000)
437
438	/** The mask of all PGM page attribute bits for regular page-tables. */
439	#define PGM_PTATTRS_PT_VALID_MASK ( PGM_PTATTRS_R_MASK \
440	\| PGM_PTATTRS_W_MASK \
441	\| PGM_PTATTRS_US_MASK \
442	\| PGM_PTATTRS_PWT_MASK \
443	\| PGM_PTATTRS_PCD_MASK \
444	\| PGM_PTATTRS_A_MASK \
445	\| PGM_PTATTRS_D_MASK \
446	\| PGM_PTATTRS_PAT_MASK \
447	\| PGM_PTATTRS_G_MASK \
448	\| PGM_PTATTRS_NX_MASK)
449
450	/** The mask of all PGM page attribute bits for EPT. */
451	#define PGM_PTATTRS_EPT_VALID_MASK ( PGM_PTATTRS_R_MASK \
452	\| PGM_PTATTRS_W_MASK \
453	\| PGM_PTATTRS_A_MASK \
454	\| PGM_PTATTRS_D_MASK \
455	\| PGM_PTATTRS_EPT_R_MASK \
456	\| PGM_PTATTRS_EPT_W_MASK \
457	\| PGM_PTATTRS_EPT_X_SUPER \
458	\| PGM_PTATTRS_EPT_MEMTYPE \
459	\| PGM_PTATTRS_EPT_IGNORE_PAT \
460	\| PGM_PTATTRS_EPT_X_USER \
461	\| PGM_PTATTRS_EPT_SUPER_SHW_STACK \
462	\| PGM_PTATTRS_EPT_SUPPRESS_VE_XCPT)
463
464	/* The mask of all PGM page attribute bits (combined). */
465	#define PGM_PTATTRS_VALID_MASK (PGM_PTATTRS_PT_VALID_MASK \| PGM_PTATTRS_PT_VALID_MASK)
466
467	/* Verify bits match the regular PT bits. */
468	AssertCompile(PGM_PTATTRS_W_SHIFT == X86_PTE_BIT_RW);
469	AssertCompile(PGM_PTATTRS_US_SHIFT == X86_PTE_BIT_US);
470	AssertCompile(PGM_PTATTRS_PWT_SHIFT == X86_PTE_BIT_PWT);
471	AssertCompile(PGM_PTATTRS_PCD_SHIFT == X86_PTE_BIT_PCD);
472	AssertCompile(PGM_PTATTRS_A_SHIFT == X86_PTE_BIT_A);
473	AssertCompile(PGM_PTATTRS_D_SHIFT == X86_PTE_BIT_D);
474	AssertCompile(PGM_PTATTRS_PAT_SHIFT == X86_PTE_BIT_PAT);
475	AssertCompile(PGM_PTATTRS_G_SHIFT == X86_PTE_BIT_G);
476	AssertCompile(PGM_PTATTRS_W_MASK == X86_PTE_RW);
477	AssertCompile(PGM_PTATTRS_US_MASK == X86_PTE_US);
478	AssertCompile(PGM_PTATTRS_PWT_MASK == X86_PTE_PWT);
479	AssertCompile(PGM_PTATTRS_PCD_MASK == X86_PTE_PCD);
480	AssertCompile(PGM_PTATTRS_A_MASK == X86_PTE_A);
481	AssertCompile(PGM_PTATTRS_D_MASK == X86_PTE_D);
482	AssertCompile(PGM_PTATTRS_PAT_MASK == X86_PTE_PAT);
483	AssertCompile(PGM_PTATTRS_G_MASK == X86_PTE_G);
484	AssertCompile(PGM_PTATTRS_NX_MASK == X86_PTE_PAE_NX);
485
486	/* Verify those EPT bits that must map 1:1 (after shifting). */
487	AssertCompile(PGM_PTATTRS_EPT_R_SHIFT - PGM_PTATTRS_EPT_SHIFT == EPT_E_BIT_READ);
488	AssertCompile(PGM_PTATTRS_EPT_W_SHIFT - PGM_PTATTRS_EPT_SHIFT == EPT_E_BIT_WRITE);
489	AssertCompile(PGM_PTATTRS_EPT_X_SUPER_SHIFT - PGM_PTATTRS_EPT_SHIFT == EPT_E_BIT_EXECUTE);
490	AssertCompile(PGM_PTATTRS_EPT_IGNORE_PAT_SHIFT - PGM_PTATTRS_EPT_SHIFT == EPT_E_BIT_IGNORE_PAT);
491	AssertCompile(PGM_PTATTRS_EPT_X_USER_SHIFT - PGM_PTATTRS_EPT_SHIFT == EPT_E_BIT_USER_EXECUTE);
492	/** @} */
493
494
495	/**
496	* Page table walk information.
497	*
498	* This provides extensive information regarding page faults (or EPT
499	* violations/misconfigurations) while traversing page tables.
500	*/
501	typedef struct PGMPTWALK
502	{
503	/** The linear address that is being resolved (input). */
504	RTGCPTR GCPtr;
505
506	/** The second-level physical address (input/output).
507	* @remarks only valid if fIsSlat is set. */
508	RTGCPHYS GCPhysNested;
509
510	/** The physical address that is the result of the walk (output).
511	* @remarks This is page aligned and only valid if fSucceeded is set. */
512	RTGCPHYS GCPhys;
513
514	/** Set if the walk succeeded. */
515	bool fSucceeded;
516	/** Whether this is a second-level address translation. */
517	bool fIsSlat;
518	/** Whether the linear address (GCPtr) caused the second-level
519	* address translation. */
520	bool fIsLinearAddrValid;
521	/** The level problem arrised at.
522	* PTE is level 1, PDE is level 2, PDPE is level 3, PML4 is level 4, CR3 is
523	* level 8. This is 0 on success. */
524	uint8_t uLevel;
525	/** Set if the page isn't present. */
526	bool fNotPresent;
527	/** Encountered a bad physical address. */
528	bool fBadPhysAddr;
529	/** Set if there was reserved bit violations. */
530	bool fRsvdError;
531	/** Set if it involves a big page (2/4 MB). */
532	bool fBigPage;
533	/** Set if it involves a gigantic page (1 GB). */
534	bool fGigantPage;
535	bool afPadding[3];
536	/** Page-walk failure type, PGM_WALKFAIL_XXX. */
537	PGMWALKFAIL fFailed;
538
539	/** The effective page-table attributes, PGM_PTATTRS_XXX. */
540	PGMPTATTRS fEffective;
541	} PGMPTWALK;
542	/** Pointer to page walk information. */
543	typedef PGMPTWALK *PPGMPTWALK;
544	/** Pointer to const page walk information. */
545	typedef PGMPTWALK const *PCPGMPTWALK;
546
547
548	/** Macro for checking if the guest is using paging.
549	* @param enmMode PGMMODE_*.
550	* @remark ASSUMES certain order of the PGMMODE_* values.
551	*/
552	#define PGMMODE_WITH_PAGING(enmMode) ((enmMode) >= PGMMODE_32_BIT)
553
554	/** Macro for checking if it's one of the long mode modes.
555	* @param enmMode PGMMODE_*.
556	*/
557	#define PGMMODE_IS_LONG_MODE(enmMode) ((enmMode) == PGMMODE_AMD64_NX \|\| (enmMode) == PGMMODE_AMD64)
558
559	/** Macro for checking if it's one of the AMD64 nested modes.
560	* @param enmMode PGMMODE_*.
561	*/
562	#define PGMMODE_IS_NESTED(enmMode) ( (enmMode) == PGMMODE_NESTED_32BIT \
563	\|\| (enmMode) == PGMMODE_NESTED_PAE \
564	\|\| (enmMode) == PGMMODE_NESTED_AMD64)
565
566	/** Macro for checking if it's one of the PAE modes.
567	* @param enmMode PGMMODE_*.
568	*/
569	#define PGMMODE_IS_PAE(enmMode) ( (enmMode) == PGMMODE_PAE \
570	\|\| (enmMode) == PGMMODE_PAE_NX)
571
572	/**
573	* Is the ROM mapped (true) or is the shadow RAM mapped (false).
574	*
575	* @returns boolean.
576	* @param enmProt The PGMROMPROT value, must be valid.
577	*/
578	#define PGMROMPROT_IS_ROM(enmProt) \
579	( (enmProt) == PGMROMPROT_READ_ROM_WRITE_IGNORE \
580	\|\| (enmProt) == PGMROMPROT_READ_ROM_WRITE_RAM )
581
582
583	VMMDECL(bool) PGMIsLockOwner(PVMCC pVM);
584
585	VMMDECL(int) PGMRegisterStringFormatTypes(void);
586	VMMDECL(void) PGMDeregisterStringFormatTypes(void);
587	VMMDECL(RTHCPHYS) PGMGetHyperCR3(PVMCPU pVCpu);
588	VMMDECL(int) PGMTrap0eHandler(PVMCPUCC pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault);
589	VMMDECL(int) PGMPrefetchPage(PVMCPUCC pVCpu, RTGCPTR GCPtrPage);
590	VMMDECL(VBOXSTRICTRC) PGMInterpretInstruction(PVMCC pVM, PVMCPUCC pVCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault);
591	VMMDECL(int) PGMShwGetPage(PVMCPUCC pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys);
592	VMMDECL(int) PGMShwMakePageReadonly(PVMCPUCC pVCpu, RTGCPTR GCPtr, uint32_t fFlags);
593	VMMDECL(int) PGMShwMakePageWritable(PVMCPUCC pVCpu, RTGCPTR GCPtr, uint32_t fFlags);
594	VMMDECL(int) PGMShwMakePageNotPresent(PVMCPUCC pVCpu, RTGCPTR GCPtr, uint32_t fFlags);
595	/** @name Flags for PGMShwMakePageReadonly, PGMShwMakePageWritable and
596	* PGMShwMakePageNotPresent
597	* @{ */
598	/** The call is from an access handler for dealing with the a faulting write
599	* operation. The virtual address is within the same page. */
600	#define PGM_MK_PG_IS_WRITE_FAULT RT_BIT(0)
601	/** The page is an MMIO2. */
602	#define PGM_MK_PG_IS_MMIO2 RT_BIT(1)
603	/** @}*/
604	VMMDECL(int) PGMGstGetPage(PVMCPUCC pVCpu, RTGCPTR GCPtr, PPGMPTWALK pWalk);
605	VMMDECL(int) PGMGstModifyPage(PVMCPUCC pVCpu, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask);
606	VMM_INT_DECL(bool) PGMGstArePaePdpesValid(PVMCPUCC pVCpu, PCX86PDPE paPaePdpes);
607	VMM_INT_DECL(int) PGMGstMapPaePdpes(PVMCPUCC pVCpu, PCX86PDPE paPaePdpes);
608	VMM_INT_DECL(int) PGMGstMapPaePdpesAtCr3(PVMCPUCC pVCpu, uint64_t cr3);
609
610	VMMDECL(int) PGMInvalidatePage(PVMCPUCC pVCpu, RTGCPTR GCPtrPage);
611	VMMDECL(int) PGMFlushTLB(PVMCPUCC pVCpu, uint64_t cr3, bool fGlobal);
612	VMMDECL(int) PGMSyncCR3(PVMCPUCC pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal);
613	VMMDECL(int) PGMUpdateCR3(PVMCPUCC pVCpu, uint64_t cr3);
614	VMMDECL(int) PGMChangeMode(PVMCPUCC pVCpu, uint64_t cr0, uint64_t cr4, uint64_t efer, bool fForce);
615	VMM_INT_DECL(int) PGMHCChangeMode(PVMCC pVM, PVMCPUCC pVCpu, PGMMODE enmGuestMode);
616	VMMDECL(void) PGMCr0WpEnabled(PVMCPUCC pVCpu);
617	VMMDECL(PGMMODE) PGMGetGuestMode(PVMCPU pVCpu);
618	VMMDECL(PGMMODE) PGMGetShadowMode(PVMCPU pVCpu);
619	VMMDECL(PGMMODE) PGMGetHostMode(PVM pVM);
620	VMMDECL(const char *) PGMGetModeName(PGMMODE enmMode);
621	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
622	VMM_INT_DECL(const char *) PGMGetSlatModeName(PGMSLAT enmSlatMode);
623	#endif
624	VMM_INT_DECL(RTGCPHYS) PGMGetGuestCR3Phys(PVMCPU pVCpu);
625	VMM_INT_DECL(void) PGMNotifyNxeChanged(PVMCPU pVCpu, bool fNxe);
626	VMMDECL(bool) PGMHasDirtyPages(PVM pVM);
627	VMM_INT_DECL(void) PGMSetGuestEptPtr(PVMCPUCC pVCpu, uint64_t uEptPtr);
628
629	/** PGM physical access handler type registration handle (heap offset, valid
630	* cross contexts without needing fixing up). Callbacks and handler type is
631	* associated with this and it is shared by all handler registrations. */
632	typedef uint64_t PGMPHYSHANDLERTYPE;
633	/** Pointer to a PGM physical handler type registration handle. */
634	typedef PGMPHYSHANDLERTYPE *PPGMPHYSHANDLERTYPE;
635	/** NIL value for PGM physical access handler type handle. */
636	#define NIL_PGMPHYSHANDLERTYPE UINT64_MAX
637	VMMDECL(int) PGMHandlerPhysicalRegister(PVMCC pVM, RTGCPHYS GCPhys, RTGCPHYS GCPhysLast, PGMPHYSHANDLERTYPE hType,
638	uint64_t uUser, R3PTRTYPE(const char *) pszDesc);
639	VMMDECL(int) PGMHandlerPhysicalModify(PVMCC pVM, RTGCPHYS GCPhysCurrent, RTGCPHYS GCPhys, RTGCPHYS GCPhysLast);
640	VMMDECL(int) PGMHandlerPhysicalDeregister(PVMCC pVM, RTGCPHYS GCPhys);
641	VMMDECL(int) PGMHandlerPhysicalChangeUserArg(PVMCC pVM, RTGCPHYS GCPhys, uint64_t uUser);
642	VMMDECL(int) PGMHandlerPhysicalSplit(PVMCC pVM, RTGCPHYS GCPhys, RTGCPHYS GCPhysSplit);
643	VMMDECL(int) PGMHandlerPhysicalJoin(PVMCC pVM, RTGCPHYS GCPhys1, RTGCPHYS GCPhys2);
644	VMMDECL(int) PGMHandlerPhysicalPageTempOff(PVMCC pVM, RTGCPHYS GCPhys, RTGCPHYS GCPhysPage);
645	VMMDECL(int) PGMHandlerPhysicalPageAliasMmio2(PVMCC pVM, RTGCPHYS GCPhys, RTGCPHYS GCPhysPage,
646	PPDMDEVINS pDevIns, PGMMMIO2HANDLE hMmio2, RTGCPHYS offMMio2PageRemap);
647	VMMDECL(int) PGMHandlerPhysicalPageAliasHC(PVMCC pVM, RTGCPHYS GCPhys, RTGCPHYS GCPhysPage, RTHCPHYS HCPhysPageRemap);
648	VMMDECL(int) PGMHandlerPhysicalReset(PVMCC pVM, RTGCPHYS GCPhys);
649	VMMDECL(bool) PGMHandlerPhysicalIsRegistered(PVMCC pVM, RTGCPHYS GCPhys);
650
651	/** @name PGMPHYSHANDLER_F_XXX - flags for PGMR3HandlerPhysicalTypeRegister and PGMR0HandlerPhysicalTypeRegister
652	* @{ */
653	/** Whether to hold the PGM lock while calling the handler or not.
654	* Mainly an optimization for PGM callers. */
655	#define PGMPHYSHANDLER_F_KEEP_PGM_LOCK RT_BIT_32(0)
656	/** The uUser value is a ring-0 device instance index that needs translating
657	* into a PDMDEVINS pointer before calling the handler. This is a hack to make
658	* it possible to use access handlers in devices. */
659	#define PGMPHYSHANDLER_F_R0_DEVINS_IDX RT_BIT_32(1)
660	/** Mask of valid bits. */
661	#define PGMPHYSHANDLER_F_VALID_MASK UINT32_C(3)
662	/** @} */
663
664
665	/**
666	* Page type.
667	*
668	* @remarks This enum has to fit in a 3-bit field (see PGMPAGE::u3Type).
669	* @remarks This is used in the saved state, so changes to it requires bumping
670	* the saved state version.
671	* @todo So, convert to \#defines!
672	*/
673	typedef enum PGMPAGETYPE
674	{
675	/** The usual invalid zero entry. */
676	PGMPAGETYPE_INVALID = 0,
677	/** RAM page. (RWX) */
678	PGMPAGETYPE_RAM,
679	/** MMIO2 page. (RWX) */
680	PGMPAGETYPE_MMIO2,
681	/** MMIO2 page aliased over an MMIO page. (RWX)
682	* See PGMHandlerPhysicalPageAlias(). */
683	PGMPAGETYPE_MMIO2_ALIAS_MMIO,
684	/** Special page aliased over an MMIO page. (RWX)
685	* See PGMHandlerPhysicalPageAliasHC(), but this is generally only used for
686	* VT-x's APIC access page at the moment. Treated as MMIO by everyone except
687	* the shadow paging code. */
688	PGMPAGETYPE_SPECIAL_ALIAS_MMIO,
689	/** Shadowed ROM. (RWX) */
690	PGMPAGETYPE_ROM_SHADOW,
691	/** ROM page. (R-X) */
692	PGMPAGETYPE_ROM,
693	/** MMIO page. (---) */
694	PGMPAGETYPE_MMIO,
695	/** End of valid entries. */
696	PGMPAGETYPE_END
697	} PGMPAGETYPE;
698	AssertCompile(PGMPAGETYPE_END == 8);
699
700	/** @name PGM page type predicates.
701	* @{ */
702	#define PGMPAGETYPE_IS_READABLE(a_enmType) ( (a_enmType) <= PGMPAGETYPE_ROM )
703	#define PGMPAGETYPE_IS_WRITEABLE(a_enmType) ( (a_enmType) <= PGMPAGETYPE_ROM_SHADOW )
704	#define PGMPAGETYPE_IS_RWX(a_enmType) ( (a_enmType) <= PGMPAGETYPE_ROM_SHADOW )
705	#define PGMPAGETYPE_IS_ROX(a_enmType) ( (a_enmType) == PGMPAGETYPE_ROM )
706	#define PGMPAGETYPE_IS_NP(a_enmType) ( (a_enmType) == PGMPAGETYPE_MMIO )
707	/** @} */
708
709
710	VMM_INT_DECL(PGMPAGETYPE) PGMPhysGetPageType(PVMCC pVM, RTGCPHYS GCPhys);
711
712	VMM_INT_DECL(int) PGMPhysGCPhys2HCPhys(PVMCC pVM, RTGCPHYS GCPhys, PRTHCPHYS pHCPhys);
713	VMM_INT_DECL(int) PGMPhysGCPtr2HCPhys(PVMCPUCC pVCpu, RTGCPTR GCPtr, PRTHCPHYS pHCPhys);
714	VMM_INT_DECL(int) PGMPhysGCPhys2CCPtr(PVMCC pVM, RTGCPHYS GCPhys, void **ppv, PPGMPAGEMAPLOCK pLock);
715	VMM_INT_DECL(int) PGMPhysGCPhys2CCPtrReadOnly(PVMCC pVM, RTGCPHYS GCPhys, void const **ppv, PPGMPAGEMAPLOCK pLock);
716	VMM_INT_DECL(int) PGMPhysGCPtr2CCPtr(PVMCPU pVCpu, RTGCPTR GCPtr, void **ppv, PPGMPAGEMAPLOCK pLock);
717	VMM_INT_DECL(int) PGMPhysGCPtr2CCPtrReadOnly(PVMCPUCC pVCpu, RTGCPTR GCPtr, void const **ppv, PPGMPAGEMAPLOCK pLock);
718
719	VMMDECL(bool) PGMPhysIsA20Enabled(PVMCPU pVCpu);
720	VMMDECL(bool) PGMPhysIsGCPhysValid(PVMCC pVM, RTGCPHYS GCPhys);
721	VMMDECL(bool) PGMPhysIsGCPhysNormal(PVMCC pVM, RTGCPHYS GCPhys);
722	VMMDECL(int) PGMPhysGCPtr2GCPhys(PVMCPUCC pVCpu, RTGCPTR GCPtr, PRTGCPHYS pGCPhys);
723	VMMDECL(void) PGMPhysReleasePageMappingLock(PVMCC pVM, PPGMPAGEMAPLOCK pLock);
724	VMMDECL(void) PGMPhysBulkReleasePageMappingLocks(PVMCC pVM, uint32_t cPages, PPGMPAGEMAPLOCK paLock);
725
726	/** @def PGM_PHYS_RW_IS_SUCCESS
727	* Check whether a PGMPhysRead, PGMPhysWrite, PGMPhysReadGCPtr or
728	* PGMPhysWriteGCPtr call completed the given task.
729	*
730	* @returns true if completed, false if not.
731	* @param a_rcStrict The status code.
732	* @sa IOM_SUCCESS
733	*/
734	#ifdef IN_RING3
735	# define PGM_PHYS_RW_IS_SUCCESS(a_rcStrict) \
736	( (a_rcStrict) == VINF_SUCCESS \
737	\|\| (a_rcStrict) == VINF_EM_DBG_STOP \
738	\|\| (a_rcStrict) == VINF_EM_DBG_EVENT \
739	\|\| (a_rcStrict) == VINF_EM_DBG_BREAKPOINT \
740	)
741	#elif defined(IN_RING0)
742	# define PGM_PHYS_RW_IS_SUCCESS(a_rcStrict) \
743	( (a_rcStrict) == VINF_SUCCESS \
744	\|\| (a_rcStrict) == VINF_IOM_R3_MMIO_COMMIT_WRITE \
745	\|\| (a_rcStrict) == VINF_EM_OFF \
746	\|\| (a_rcStrict) == VINF_EM_SUSPEND \
747	\|\| (a_rcStrict) == VINF_EM_RESET \
748	\|\| (a_rcStrict) == VINF_EM_HALT \
749	\|\| (a_rcStrict) == VINF_EM_DBG_STOP \
750	\|\| (a_rcStrict) == VINF_EM_DBG_EVENT \
751	\|\| (a_rcStrict) == VINF_EM_DBG_BREAKPOINT \
752	)
753	#elif defined(IN_RC)
754	# define PGM_PHYS_RW_IS_SUCCESS(a_rcStrict) \
755	( (a_rcStrict) == VINF_SUCCESS \
756	\|\| (a_rcStrict) == VINF_IOM_R3_MMIO_COMMIT_WRITE \
757	\|\| (a_rcStrict) == VINF_EM_OFF \
758	\|\| (a_rcStrict) == VINF_EM_SUSPEND \
759	\|\| (a_rcStrict) == VINF_EM_RESET \
760	\|\| (a_rcStrict) == VINF_EM_HALT \
761	\|\| (a_rcStrict) == VINF_SELM_SYNC_GDT \
762	\|\| (a_rcStrict) == VINF_EM_RAW_EMULATE_INSTR_GDT_FAULT \
763	\|\| (a_rcStrict) == VINF_EM_DBG_STOP \
764	\|\| (a_rcStrict) == VINF_EM_DBG_EVENT \
765	\|\| (a_rcStrict) == VINF_EM_DBG_BREAKPOINT \
766	)
767	#endif
768	/** @def PGM_PHYS_RW_DO_UPDATE_STRICT_RC
769	* Updates the return code with a new result.
770	*
771	* Both status codes must be successes according to PGM_PHYS_RW_IS_SUCCESS.
772	*
773	* @param a_rcStrict The current return code, to be updated.
774	* @param a_rcStrict2 The new return code to merge in.
775	*/
776	#ifdef IN_RING3
777	# define PGM_PHYS_RW_DO_UPDATE_STRICT_RC(a_rcStrict, a_rcStrict2) \
778	do { \
779	Assert(rcStrict == VINF_SUCCESS); \
780	Assert(rcStrict2 == VINF_SUCCESS); \
781	} while (0)
782	#elif defined(IN_RING0)
783	# define PGM_PHYS_RW_DO_UPDATE_STRICT_RC(a_rcStrict, a_rcStrict2) \
784	do { \
785	Assert(PGM_PHYS_RW_IS_SUCCESS(rcStrict)); \
786	Assert(PGM_PHYS_RW_IS_SUCCESS(rcStrict2)); \
787	AssertCompile(VINF_IOM_R3_MMIO_COMMIT_WRITE > VINF_EM_LAST); \
788	if ((a_rcStrict2) == VINF_SUCCESS \|\| (a_rcStrict) == (a_rcStrict2)) \
789	{ /* likely */ } \
790	else if ( (a_rcStrict) == VINF_SUCCESS \
791	\|\| (a_rcStrict) > (a_rcStrict2)) \
792	(a_rcStrict) = (a_rcStrict2); \
793	} while (0)
794	#elif defined(IN_RC)
795	# define PGM_PHYS_RW_DO_UPDATE_STRICT_RC(a_rcStrict, a_rcStrict2) \
796	do { \
797	Assert(PGM_PHYS_RW_IS_SUCCESS(rcStrict)); \
798	Assert(PGM_PHYS_RW_IS_SUCCESS(rcStrict2)); \
799	AssertCompile(VINF_SELM_SYNC_GDT > VINF_EM_LAST); \
800	AssertCompile(VINF_EM_RAW_EMULATE_INSTR_GDT_FAULT > VINF_EM_LAST); \
801	AssertCompile(VINF_EM_RAW_EMULATE_INSTR_GDT_FAULT < VINF_SELM_SYNC_GDT); \
802	AssertCompile(VINF_IOM_R3_MMIO_COMMIT_WRITE > VINF_EM_LAST); \
803	AssertCompile(VINF_IOM_R3_MMIO_COMMIT_WRITE > VINF_SELM_SYNC_GDT); \
804	AssertCompile(VINF_IOM_R3_MMIO_COMMIT_WRITE > VINF_EM_RAW_EMULATE_INSTR_GDT_FAULT); \
805	if ((a_rcStrict2) == VINF_SUCCESS \|\| (a_rcStrict) == (a_rcStrict2)) \
806	{ /* likely */ } \
807	else if ((a_rcStrict) == VINF_SUCCESS) \
808	(a_rcStrict) = (a_rcStrict2); \
809	else if ( ( (a_rcStrict) > (a_rcStrict2) \
810	&& ( (a_rcStrict2) <= VINF_EM_RESET \
811	\|\| (a_rcStrict) != VINF_EM_RAW_EMULATE_INSTR_GDT_FAULT) ) \
812	\|\| ( (a_rcStrict2) == VINF_EM_RAW_EMULATE_INSTR_GDT_FAULT \
813	&& (a_rcStrict) > VINF_EM_RESET) ) \
814	(a_rcStrict) = (a_rcStrict2); \
815	} while (0)
816	#endif
817
818	VMMDECL(VBOXSTRICTRC) PGMPhysRead(PVMCC pVM, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead, PGMACCESSORIGIN enmOrigin);
819	VMMDECL(VBOXSTRICTRC) PGMPhysWrite(PVMCC pVM, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite, PGMACCESSORIGIN enmOrigin);
820	VMMDECL(VBOXSTRICTRC) PGMPhysReadGCPtr(PVMCPUCC pVCpu, void *pvDst, RTGCPTR GCPtrSrc, size_t cb, PGMACCESSORIGIN enmOrigin);
821	VMMDECL(VBOXSTRICTRC) PGMPhysWriteGCPtr(PVMCPUCC pVCpu, RTGCPTR GCPtrDst, const void *pvSrc, size_t cb, PGMACCESSORIGIN enmOrigin);
822
823	VMMDECL(int) PGMPhysSimpleReadGCPhys(PVMCC pVM, void *pvDst, RTGCPHYS GCPhysSrc, size_t cb);
824	VMMDECL(int) PGMPhysSimpleWriteGCPhys(PVMCC pVM, RTGCPHYS GCPhysDst, const void *pvSrc, size_t cb);
825	VMMDECL(int) PGMPhysSimpleReadGCPtr(PVMCPUCC pVCpu, void *pvDst, RTGCPTR GCPtrSrc, size_t cb);
826	VMMDECL(int) PGMPhysSimpleWriteGCPtr(PVMCPUCC pVCpu, RTGCPTR GCPtrDst, const void *pvSrc, size_t cb);
827	VMMDECL(int) PGMPhysSimpleDirtyWriteGCPtr(PVMCPUCC pVCpu, RTGCPTR GCPtrDst, const void *pvSrc, size_t cb);
828
829	VMM_INT_DECL(int) PGMPhysIemGCPhys2Ptr(PVMCC pVM, PVMCPUCC pVCpu, RTGCPHYS GCPhys, bool fWritable, bool fByPassHandlers, void **ppv, PPGMPAGEMAPLOCK pLock);
830	VMM_INT_DECL(int) PGMPhysIemQueryAccess(PVMCC pVM, RTGCPHYS GCPhys, bool fWritable, bool fByPassHandlers);
831	VMM_INT_DECL(int) PGMPhysIemGCPhys2PtrNoLock(PVMCC pVM, PVMCPUCC pVCpu, RTGCPHYS GCPhys, uint64_t const volatile *puTlbPhysRev,
832	#if defined(IN_RC)
833	R3PTRTYPE(uint8_t ) ppb,
834	#else
835	R3R0PTRTYPE(uint8_t ) ppb,
836	#endif
837	uint64_t *pfTlb);
838	/** @name Flags returned by PGMPhysIemGCPhys2PtrNoLock
839	* @{ */
840	#define PGMIEMGCPHYS2PTR_F_NO_WRITE RT_BIT_32(3) /*< Not writable (IEMTLBE_F_PG_NO_WRITE). /
841	#define PGMIEMGCPHYS2PTR_F_NO_READ RT_BIT_32(4) /*< Not readable (IEMTLBE_F_PG_NO_READ). /
842	#define PGMIEMGCPHYS2PTR_F_NO_MAPPINGR3 RT_BIT_32(7) /*< No ring-3 mapping (IEMTLBE_F_NO_MAPPINGR3). /
843	/** @} */
844
845	/** Information returned by PGMPhysNemQueryPageInfo. */
846	typedef struct PGMPHYSNEMPAGEINFO
847	{
848	/** The host physical address of the page, NIL_HCPHYS if invalid page. */
849	RTHCPHYS HCPhys;
850	/** The NEM access mode for the page, NEM_PAGE_PROT_XXX */
851	uint32_t fNemProt : 8;
852	/** The NEM state associated with the PAGE. */
853	uint32_t u2NemState : 2;
854	/** The NEM state associated with the PAGE before pgmPhysPageMakeWritable was called. */
855	uint32_t u2OldNemState : 2;
856	/** Set if the page has handler. */
857	uint32_t fHasHandlers : 1;
858	/** Set if is the zero page backing it. */
859	uint32_t fZeroPage : 1;
860	/** Set if the page has handler. */
861	PGMPAGETYPE enmType;
862	} PGMPHYSNEMPAGEINFO;
863	/** Pointer to page information for NEM. */
864	typedef PGMPHYSNEMPAGEINFO *PPGMPHYSNEMPAGEINFO;
865	/**
866	* Callback for checking that the page is in sync while under the PGM lock.
867	*
868	* NEM passes this callback to PGMPhysNemQueryPageInfo to check that the page is
869	* in-sync between PGM and the native hypervisor API in an atomic fashion.
870	*
871	* @returns VBox status code.
872	* @param pVM The cross context VM structure.
873	* @param pVCpu The cross context per virtual CPU structure. Optional,
874	* see PGMPhysNemQueryPageInfo.
875	* @param GCPhys The guest physical address (not A20 masked).
876	* @param pInfo The page info structure. This function updates the
877	* u2NemState memory and the caller will update the PGMPAGE
878	* copy accordingly.
879	* @param pvUser Callback user argument.
880	*/
881	typedef DECLCALLBACKTYPE(int, FNPGMPHYSNEMCHECKPAGE,(PVMCC pVM, PVMCPUCC pVCpu, RTGCPHYS GCPhys, PPGMPHYSNEMPAGEINFO pInfo, void *pvUser));
882	/** Pointer to a FNPGMPHYSNEMCHECKPAGE function. */
883	typedef FNPGMPHYSNEMCHECKPAGE *PFNPGMPHYSNEMCHECKPAGE;
884
885	VMM_INT_DECL(int) PGMPhysNemPageInfoChecker(PVMCC pVM, PVMCPUCC pVCpu, RTGCPHYS GCPhys, bool fMakeWritable,
886	PPGMPHYSNEMPAGEINFO pInfo, PFNPGMPHYSNEMCHECKPAGE pfnChecker, void *pvUser);
887
888	/**
889	* Callback for use with PGMPhysNemEnumPagesByState.
890	* @returns VBox status code.
891	* Failure status will stop enumeration immediately and return.
892	* @param pVM The cross context VM structure.
893	* @param pVCpu The cross context per virtual CPU structure. Optional,
894	* see PGMPhysNemEnumPagesByState.
895	* @param GCPhys The guest physical address (not A20 masked).
896	* @param pu2NemState Pointer to variable with the NEM state. This can be
897	* update.
898	* @param pvUser The user argument.
899	*/
900	typedef DECLCALLBACKTYPE(int, FNPGMPHYSNEMENUMCALLBACK,(PVMCC pVM, PVMCPUCC pVCpu, RTGCPHYS GCPhys,
901	uint8_t pu2NemState, void pvUser));
902	/** Pointer to a FNPGMPHYSNEMENUMCALLBACK function. */
903	typedef FNPGMPHYSNEMENUMCALLBACK *PFNPGMPHYSNEMENUMCALLBACK;
904	VMM_INT_DECL(int) PGMPhysNemEnumPagesByState(PVMCC pVM, PVMCPUCC VCpu, uint8_t uMinState,
905	PFNPGMPHYSNEMENUMCALLBACK pfnCallback, void *pvUser);
906
907
908	#ifdef VBOX_STRICT
909	VMMDECL(unsigned) PGMAssertHandlerAndFlagsInSync(PVMCC pVM);
910	VMMDECL(unsigned) PGMAssertNoMappingConflicts(PVM pVM);
911	VMMDECL(unsigned) PGMAssertCR3(PVMCC pVM, PVMCPUCC pVCpu, uint64_t cr3, uint64_t cr4);
912	#endif /* VBOX_STRICT */
913
914	VMMDECL(int) PGMSetLargePageUsage(PVMCC pVM, bool fUseLargePages);
915
916	/**
917	* Query large page usage state
918	*
919	* @returns 0 - disabled, 1 - enabled
920	* @param pVM The cross context VM structure.
921	*/
922	#define PGMIsUsingLargePages(pVM) ((pVM)->pgm.s.fUseLargePages)
923
924
925	#ifdef IN_RING0
926	/** @defgroup grp_pgm_r0 The PGM Host Context Ring-0 API
927	* @{
928	*/
929	VMMR0_INT_DECL(int) PGMR0InitPerVMData(PGVM pGVM, RTR0MEMOBJ hMemObj);
930	VMMR0_INT_DECL(int) PGMR0InitVM(PGVM pGVM);
931	VMMR0_INT_DECL(void) PGMR0DoneInitVM(PGVM pGVM);
932	VMMR0_INT_DECL(void) PGMR0CleanupVM(PGVM pGVM);
933	VMMR0_INT_DECL(int) PGMR0PhysAllocateHandyPages(PGVM pGVM, VMCPUID idCpu);
934	VMMR0_INT_DECL(int) PGMR0PhysFlushHandyPages(PGVM pGVM, VMCPUID idCpu);
935	VMMR0_INT_DECL(int) PGMR0PhysAllocateLargePage(PGVM pGVM, VMCPUID idCpu, RTGCPHYS GCPhys);
936	VMMR0_INT_DECL(int) PGMR0PhysMMIO2MapKernel(PGVM pGVM, PPDMDEVINS pDevIns, PGMMMIO2HANDLE hMmio2,
937	size_t offSub, size_t cbSub, void **ppvMapping);
938	VMMR0_INT_DECL(int) PGMR0PhysSetupIoMmu(PGVM pGVM);
939	VMMR0_INT_DECL(int) PGMR0HandlerPhysicalTypeSetUpContext(PGVM pGVM, PGMPHYSHANDLERKIND enmKind, uint32_t fFlags,
940	PFNPGMPHYSHANDLER pfnHandler, PFNPGMRZPHYSPFHANDLER pfnPfHandler,
941	const char *pszDesc, PGMPHYSHANDLERTYPE hType);
942
943	VMMR0DECL(int) PGMR0SharedModuleCheck(PVMCC pVM, PGVM pGVM, VMCPUID idCpu, PGMMSHAREDMODULE pModule,
944	PCRTGCPTR64 paRegionsGCPtrs);
945	VMMR0DECL(int) PGMR0Trap0eHandlerNestedPaging(PGVM pGVM, PGVMCPU pGVCpu, PGMMODE enmShwPagingMode, RTGCUINT uErr,
946	PCPUMCTXCORE pRegFrame, RTGCPHYS pvFault);
947	VMMR0DECL(VBOXSTRICTRC) PGMR0Trap0eHandlerNPMisconfig(PGVM pGVM, PGVMCPU pGVCpu, PGMMODE enmShwPagingMode,
948	PCPUMCTXCORE pRegFrame, RTGCPHYS GCPhysFault, uint32_t uErr);
949	VMMR0_INT_DECL(int) PGMR0PoolGrow(PGVM pGVM, VMCPUID idCpu);
950	/** @} */
951	#endif /* IN_RING0 */
952
953
954
955	#ifdef IN_RING3
956	/** @defgroup grp_pgm_r3 The PGM Host Context Ring-3 API
957	* @{
958	*/
959	VMMR3_INT_DECL(void) PGMR3EnableNemMode(PVM pVM);
960	VMMR3_INT_DECL(bool) PGMR3IsNemModeEnabled(PVM pVM);
961	VMMR3DECL(int) PGMR3Init(PVM pVM);
962	VMMR3DECL(int) PGMR3InitFinalize(PVM pVM);
963	VMMR3_INT_DECL(int) PGMR3InitCompleted(PVM pVM, VMINITCOMPLETED enmWhat);
964	VMMR3DECL(void) PGMR3Relocate(PVM pVM, RTGCINTPTR offDelta);
965	VMMR3DECL(void) PGMR3ResetCpu(PVM pVM, PVMCPU pVCpu);
966	VMMR3_INT_DECL(void) PGMR3Reset(PVM pVM);
967	VMMR3_INT_DECL(void) PGMR3ResetNoMorePhysWritesFlag(PVM pVM);
968	VMMR3_INT_DECL(void) PGMR3MemSetup(PVM pVM, bool fReset);
969	VMMR3DECL(int) PGMR3Term(PVM pVM);
970
971	VMMR3DECL(int) PGMR3PhysRegisterRam(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, const char *pszDesc);
972	VMMR3DECL(int) PGMR3PhysChangeMemBalloon(PVM pVM, bool fInflate, unsigned cPages, RTGCPHYS *paPhysPage);
973	VMMR3DECL(int) PGMR3PhysWriteProtectRAM(PVM pVM);
974	VMMR3DECL(uint32_t) PGMR3PhysGetRamRangeCount(PVM pVM);
975	VMMR3DECL(int) PGMR3PhysGetRange(PVM pVM, uint32_t iRange, PRTGCPHYS pGCPhysStart, PRTGCPHYS pGCPhysLast,
976	const char *ppszDesc, bool pfIsMmio);
977	VMMR3DECL(int) PGMR3QueryMemoryStats(PUVM pUVM, uint64_t pcbTotalMem, uint64_t pcbPrivateMem, uint64_t pcbSharedMem, uint64_t pcbZeroMem);
978	VMMR3DECL(int) PGMR3QueryGlobalMemoryStats(PUVM pUVM, uint64_t pcbAllocMem, uint64_t pcbFreeMem, uint64_t pcbBallonedMem, uint64_t pcbSharedMem);
979
980	VMMR3DECL(int) PGMR3PhysMMIORegister(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, PGMPHYSHANDLERTYPE hType,
981	uint64_t uUser, const char *pszDesc);
982	VMMR3DECL(int) PGMR3PhysMMIODeregister(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb);
983
984	/** @name PGMPHYS_MMIO2_FLAGS_XXX - MMIO2 registration flags.
985	* @see PGMR3PhysMmio2Register, PDMDevHlpMmio2Create
986	* @{ */
987	/** Track dirty pages.
988	* @see PGMR3PhysMmio2QueryAndResetDirtyBitmap(), PGMR3PhysMmio2ControlDirtyPageTracking(). */
989	#define PGMPHYS_MMIO2_FLAGS_TRACK_DIRTY_PAGES RT_BIT_32(0)
990	/** Valid flags. */
991	#define PGMPHYS_MMIO2_FLAGS_VALID_MASK UINT32_C(0x00000001)
992	/** @} */
993
994	VMMR3_INT_DECL(int) PGMR3PhysMmio2Register(PVM pVM, PPDMDEVINS pDevIns, uint32_t iSubDev, uint32_t iRegion, RTGCPHYS cb,
995	uint32_t fFlags, const char pszDesc, void ppv, PGMMMIO2HANDLE phRegion);
996	VMMR3_INT_DECL(int) PGMR3PhysMmio2Deregister(PVM pVM, PPDMDEVINS pDevIns, PGMMMIO2HANDLE hMmio2);
997	VMMR3_INT_DECL(int) PGMR3PhysMmio2Map(PVM pVM, PPDMDEVINS pDevIns, PGMMMIO2HANDLE hMmio2, RTGCPHYS GCPhys);
998	VMMR3_INT_DECL(int) PGMR3PhysMmio2Unmap(PVM pVM, PPDMDEVINS pDevIns, PGMMMIO2HANDLE hMmio2, RTGCPHYS GCPhys);
999	VMMR3_INT_DECL(int) PGMR3PhysMmio2Reduce(PVM pVM, PPDMDEVINS pDevIns, PGMMMIO2HANDLE hMmio2, RTGCPHYS cbRegion);
1000	VMMR3_INT_DECL(int) PGMR3PhysMmio2ValidateHandle(PVM pVM, PPDMDEVINS pDevIns, PGMMMIO2HANDLE hMmio2);
1001	VMMR3_INT_DECL(RTGCPHYS) PGMR3PhysMmio2GetMappingAddress(PVM pVM, PPDMDEVINS pDevIns, PGMMMIO2HANDLE hMmio2);
1002	VMMR3_INT_DECL(int) PGMR3PhysMmio2ChangeRegionNo(PVM pVM, PPDMDEVINS pDevIns, PGMMMIO2HANDLE hMmio2, uint32_t iNewRegion);
1003	VMMR3_INT_DECL(int) PGMR3PhysMmio2QueryAndResetDirtyBitmap(PVM pVM, PPDMDEVINS pDevIns, PGMMMIO2HANDLE hMmio2,
1004	void *pvBitmap, size_t cbBitmap);
1005	VMMR3_INT_DECL(int) PGMR3PhysMmio2ControlDirtyPageTracking(PVM pVM, PPDMDEVINS pDevIns, PGMMMIO2HANDLE hMmio2, bool fEnabled);
1006
1007	/** @name PGMPHYS_ROM_FLAGS_XXX - ROM registration flags.
1008	* @see PGMR3PhysRegisterRom, PDMDevHlpROMRegister
1009	* @{ */
1010	/** Inidicates that ROM shadowing should be enabled. */
1011	#define PGMPHYS_ROM_FLAGS_SHADOWED UINT8_C(0x01)
1012	/** Indicates that what pvBinary points to won't go away
1013	* and can be used for strictness checks. */
1014	#define PGMPHYS_ROM_FLAGS_PERMANENT_BINARY UINT8_C(0x02)
1015	/** Indicates that the ROM is allowed to be missing from saved state.
1016	* @note This is a hack for EFI, see @bugref{6940} */
1017	#define PGMPHYS_ROM_FLAGS_MAYBE_MISSING_FROM_STATE UINT8_C(0x04)
1018	/** Valid flags. */
1019	#define PGMPHYS_ROM_FLAGS_VALID_MASK UINT8_C(0x07)
1020	/** @} */
1021
1022	VMMR3DECL(int) PGMR3PhysRomRegister(PVM pVM, PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTGCPHYS cb,
1023	const void pvBinary, uint32_t cbBinary, uint8_t fFlags, const char pszDesc);
1024	VMMR3DECL(int) PGMR3PhysRomProtect(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, PGMROMPROT enmProt);
1025	VMMDECL(void) PGMR3PhysSetA20(PVMCPU pVCpu, bool fEnable);
1026
1027	VMMR3_INT_DECL(int) PGMR3HandlerPhysicalTypeRegister(PVM pVM, PGMPHYSHANDLERKIND enmKind, uint32_t fFlags,
1028	PFNPGMPHYSHANDLER pfnHandlerR3, const char *pszDesc,
1029	PPGMPHYSHANDLERTYPE phType);
1030
1031	VMMR3_INT_DECL(int) PGMR3PoolGrow(PVM pVM, PVMCPU pVCpu);
1032
1033	VMMR3DECL(int) PGMR3PhysTlbGCPhys2Ptr(PVM pVM, RTGCPHYS GCPhys, bool fWritable, void **ppv);
1034	VMMR3DECL(uint8_t) PGMR3PhysReadU8(PVM pVM, RTGCPHYS GCPhys, PGMACCESSORIGIN enmOrigin);
1035	VMMR3DECL(uint16_t) PGMR3PhysReadU16(PVM pVM, RTGCPHYS GCPhys, PGMACCESSORIGIN enmOrigin);
1036	VMMR3DECL(uint32_t) PGMR3PhysReadU32(PVM pVM, RTGCPHYS GCPhys, PGMACCESSORIGIN enmOrigin);
1037	VMMR3DECL(uint64_t) PGMR3PhysReadU64(PVM pVM, RTGCPHYS GCPhys, PGMACCESSORIGIN enmOrigin);
1038	VMMR3DECL(void) PGMR3PhysWriteU8(PVM pVM, RTGCPHYS GCPhys, uint8_t Value, PGMACCESSORIGIN enmOrigin);
1039	VMMR3DECL(void) PGMR3PhysWriteU16(PVM pVM, RTGCPHYS GCPhys, uint16_t Value, PGMACCESSORIGIN enmOrigin);
1040	VMMR3DECL(void) PGMR3PhysWriteU32(PVM pVM, RTGCPHYS GCPhys, uint32_t Value, PGMACCESSORIGIN enmOrigin);
1041	VMMR3DECL(void) PGMR3PhysWriteU64(PVM pVM, RTGCPHYS GCPhys, uint64_t Value, PGMACCESSORIGIN enmOrigin);
1042	VMMR3DECL(int) PGMR3PhysReadExternal(PVM pVM, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead, PGMACCESSORIGIN enmOrigin);
1043	VMMR3DECL(int) PGMR3PhysWriteExternal(PVM pVM, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite, PGMACCESSORIGIN enmOrigin);
1044	VMMR3DECL(int) PGMR3PhysGCPhys2CCPtrExternal(PVM pVM, RTGCPHYS GCPhys, void **ppv, PPGMPAGEMAPLOCK pLock);
1045	VMMR3DECL(int) PGMR3PhysGCPhys2CCPtrReadOnlyExternal(PVM pVM, RTGCPHYS GCPhys, void const **ppv, PPGMPAGEMAPLOCK pLock);
1046	VMMR3DECL(int) PGMR3PhysBulkGCPhys2CCPtrExternal(PVM pVM, uint32_t cPages, PCRTGCPHYS paGCPhysPages,
1047	void **papvPages, PPGMPAGEMAPLOCK paLocks);
1048	VMMR3DECL(int) PGMR3PhysBulkGCPhys2CCPtrReadOnlyExternal(PVM pVM, uint32_t cPages, PCRTGCPHYS paGCPhysPages,
1049	void const **papvPages, PPGMPAGEMAPLOCK paLocks);
1050	VMMR3DECL(void) PGMR3PhysChunkInvalidateTLB(PVM pVM);
1051	VMMR3DECL(int) PGMR3PhysAllocateHandyPages(PVM pVM);
1052
1053	VMMR3DECL(int) PGMR3CheckIntegrity(PVM pVM);
1054
1055	VMMR3DECL(int) PGMR3DbgR3Ptr2GCPhys(PUVM pUVM, RTR3PTR R3Ptr, PRTGCPHYS pGCPhys);
1056	VMMR3DECL(int) PGMR3DbgR3Ptr2HCPhys(PUVM pUVM, RTR3PTR R3Ptr, PRTHCPHYS pHCPhys);
1057	VMMR3DECL(int) PGMR3DbgHCPhys2GCPhys(PUVM pUVM, RTHCPHYS HCPhys, PRTGCPHYS pGCPhys);
1058	VMMR3_INT_DECL(int) PGMR3DbgReadGCPhys(PVM pVM, void pvDst, RTGCPHYS GCPhysSrc, size_t cb, uint32_t fFlags, size_t pcbRead);
1059	VMMR3_INT_DECL(int) PGMR3DbgWriteGCPhys(PVM pVM, RTGCPHYS GCPhysDst, const void pvSrc, size_t cb, uint32_t fFlags, size_t pcbWritten);
1060	VMMR3_INT_DECL(int) PGMR3DbgReadGCPtr(PVM pVM, void pvDst, RTGCPTR GCPtrSrc, size_t cb, uint32_t fFlags, size_t pcbRead);
1061	VMMR3_INT_DECL(int) PGMR3DbgWriteGCPtr(PVM pVM, RTGCPTR GCPtrDst, void const pvSrc, size_t cb, uint32_t fFlags, size_t pcbWritten);
1062	VMMR3_INT_DECL(int) PGMR3DbgScanPhysical(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cbRange, RTGCPHYS GCPhysAlign, const uint8_t *pabNeedle, size_t cbNeedle, PRTGCPHYS pGCPhysHit);
1063	VMMR3_INT_DECL(int) PGMR3DbgScanVirtual(PVM pVM, PVMCPU pVCpu, RTGCPTR GCPtr, RTGCPTR cbRange, RTGCPTR GCPtrAlign, const uint8_t *pabNeedle, size_t cbNeedle, PRTGCUINTPTR pGCPhysHit);
1064	VMMR3_INT_DECL(int) PGMR3DumpHierarchyShw(PVM pVM, uint64_t cr3, uint32_t fFlags, uint64_t u64FirstAddr, uint64_t u64LastAddr, uint32_t cMaxDepth, PCDBGFINFOHLP pHlp);
1065	VMMR3_INT_DECL(int) PGMR3DumpHierarchyGst(PVM pVM, uint64_t cr3, uint32_t fFlags, RTGCPTR FirstAddr, RTGCPTR LastAddr, uint32_t cMaxDepth, PCDBGFINFOHLP pHlp);
1066
1067
1068	/** @name Page sharing
1069	* @{ */
1070	VMMR3DECL(int) PGMR3SharedModuleRegister(PVM pVM, VBOXOSFAMILY enmGuestOS, char pszModuleName, char pszVersion,
1071	RTGCPTR GCBaseAddr, uint32_t cbModule,
1072	uint32_t cRegions, VMMDEVSHAREDREGIONDESC const *paRegions);
1073	VMMR3DECL(int) PGMR3SharedModuleUnregister(PVM pVM, char pszModuleName, char pszVersion,
1074	RTGCPTR GCBaseAddr, uint32_t cbModule);
1075	VMMR3DECL(int) PGMR3SharedModuleCheckAll(PVM pVM);
1076	VMMR3DECL(int) PGMR3SharedModuleGetPageState(PVM pVM, RTGCPTR GCPtrPage, bool pfShared, uint64_t pfPageFlags);
1077	/** @} */
1078
1079	/** @} */
1080	#endif /* IN_RING3 */
1081
1082	RT_C_DECLS_END
1083
1084	/** @} */
1085	#endif /* !VBOX_INCLUDED_vmm_pgm_h */
1086

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source: vbox/trunk/include/VBox/vmm/pgm.h@ 93651

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