VirtualBox

source: vbox/trunk/include/VBox/vmm/vm.h@ 107288

Last change on this file since 107288 was 107227, checked in by vboxsync, 3 months ago

VMM: Cleaning up ARMv8 / x86 split. jiraref:VBP-1470

  • Property svn:eol-style set to native
  • Property svn:keywords set to Author Date Id Revision
File size: 62.7 KB
Line 
1/** @file
2 * VM - The Virtual Machine, data.
3 */
4
5/*
6 * Copyright (C) 2006-2024 Oracle and/or its affiliates.
7 *
8 * This file is part of VirtualBox base platform packages, as
9 * available from https://www.virtualbox.org.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License
13 * as published by the Free Software Foundation, in version 3 of the
14 * License.
15 *
16 * This program is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, see <https://www.gnu.org/licenses>.
23 *
24 * The contents of this file may alternatively be used under the terms
25 * of the Common Development and Distribution License Version 1.0
26 * (CDDL), a copy of it is provided in the "COPYING.CDDL" file included
27 * in the VirtualBox distribution, in which case the provisions of the
28 * CDDL are applicable instead of those of the GPL.
29 *
30 * You may elect to license modified versions of this file under the
31 * terms and conditions of either the GPL or the CDDL or both.
32 *
33 * SPDX-License-Identifier: GPL-3.0-only OR CDDL-1.0
34 */
35
36#ifndef VBOX_INCLUDED_vmm_vm_h
37#define VBOX_INCLUDED_vmm_vm_h
38#ifndef RT_WITHOUT_PRAGMA_ONCE
39# pragma once
40#endif
41
42#ifndef VBOX_FOR_DTRACE_LIB
43# ifndef USING_VMM_COMMON_DEFS
44# error "Compile job does not include VMM_COMMON_DEFS from src/VBox/VMM/Config.kmk - make sure you really need to include this file!"
45# endif
46# include <iprt/param.h>
47# include <VBox/param.h>
48# include <VBox/types.h>
49# include <VBox/vmm/cpum.h>
50# include <VBox/vmm/stam.h>
51# include <VBox/vmm/vmapi.h>
52# include <VBox/vmm/vmm.h>
53# include <VBox/sup.h>
54#else
55# pragma D depends_on library vbox-types.d
56# pragma D depends_on library CPUMInternal.d
57# define VMM_INCLUDED_SRC_include_CPUMInternal_h
58# define VBOX_VMM_TARGET_AGNOSTIC
59#endif
60
61#if !defined(VBOX_VMM_TARGET_AGNOSTIC) \
62 && !defined(VBOX_VMM_TARGET_X86) \
63 && !defined(VBOX_VMM_TARGET_ARMV8)
64# error "VMM target not defined"
65#endif
66
67
68
69/** @defgroup grp_vm The Virtual Machine
70 * @ingroup grp_vmm
71 * @{
72 */
73
74/**
75 * The state of a Virtual CPU.
76 *
77 * The basic state indicated here is whether the CPU has been started or not. In
78 * addition, there are sub-states when started for assisting scheduling (GVMM
79 * mostly).
80 *
81 * The transition out of the STOPPED state is done by a vmR3PowerOn.
82 * The transition back to the STOPPED state is done by vmR3PowerOff.
83 *
84 * (Alternatively we could let vmR3PowerOn start CPU 0 only and let the SPIP
85 * handling switch on the other CPUs. Then vmR3Reset would stop all but CPU 0.)
86 */
87typedef enum VMCPUSTATE
88{
89 /** The customary invalid zero. */
90 VMCPUSTATE_INVALID = 0,
91
92 /** Virtual CPU has not yet been started. */
93 VMCPUSTATE_STOPPED,
94
95 /** CPU started. */
96 VMCPUSTATE_STARTED,
97 /** CPU started in HM context. */
98 VMCPUSTATE_STARTED_HM,
99 /** Executing guest code and can be poked (RC or STI bits of HM). */
100 VMCPUSTATE_STARTED_EXEC,
101 /** Executing guest code using NEM. */
102 VMCPUSTATE_STARTED_EXEC_NEM,
103 VMCPUSTATE_STARTED_EXEC_NEM_WAIT,
104 VMCPUSTATE_STARTED_EXEC_NEM_CANCELED,
105 /** Halted. */
106 VMCPUSTATE_STARTED_HALTED,
107
108 /** The end of valid virtual CPU states. */
109 VMCPUSTATE_END,
110
111 /** Ensure 32-bit type. */
112 VMCPUSTATE_32BIT_HACK = 0x7fffffff
113} VMCPUSTATE;
114
115/** Enables 64-bit FFs. */
116#define VMCPU_WITH_64_BIT_FFS
117
118
119/**
120 * The cross context virtual CPU structure.
121 *
122 * Run 'kmk run-struct-tests' (from src/VBox/VMM if you like) after updating!
123 */
124typedef struct VMCPU
125{
126 /** @name Volatile per-cpu data.
127 * @{ */
128 /** Per CPU forced action.
129 * See the VMCPU_FF_* \#defines. Updated atomically. */
130#ifdef VMCPU_WITH_64_BIT_FFS
131 uint64_t volatile fLocalForcedActions;
132#else
133 uint32_t volatile fLocalForcedActions;
134 uint32_t fForLocalForcedActionsExpansion;
135#endif
136 /** The CPU state. */
137 VMCPUSTATE volatile enmState;
138
139#ifdef VBOX_VMM_TARGET_ARMV8
140 uint32_t u32Alignment0;
141 /** The number of nano seconds when the vTimer of the associated vCPU is supposed to activate
142 * required to get out of a halt (due to wfi/wfe).
143 *
144 * @note This actually should go into TMCPU but this drags in a whole lot of padding changes
145 * and I'm not sure yet whether this will remain in this form anyway.
146 */
147 uint64_t cNsVTimerActivate;
148 /** Padding up to 64 bytes. */
149 uint8_t abAlignment0[64 - 12 - 8 - 4];
150#else
151 /** Padding up to 64 bytes. */
152 uint8_t abAlignment0[64 - 12];
153#endif
154 /** @} */
155
156 /** IEM part.
157 * @remarks This comes first as it allows the use of 8-bit immediates for the
158 * first 64 bytes of the structure, reducing code size a wee bit. */
159#if defined(VMM_INCLUDED_SRC_include_IEMInternal_h) || defined(VMM_INCLUDED_SRC_include_IEMInternal_armv8_h) /* For PDB hacking. */
160 union VMCPUUNIONIEMFULL
161#else
162 union VMCPUUNIONIEMSTUB
163#endif
164 {
165#if defined(VMM_INCLUDED_SRC_include_IEMInternal_h) || defined(VMM_INCLUDED_SRC_include_IEMInternal_armv8_h)
166 struct IEMCPU s;
167#endif
168 uint8_t padding[ 129984 /* The common base size. */
169#ifdef RT_ARCH_AMD64
170 + 32768 /* For 256 entries per TLBs. */
171#else
172 + 1048576 /* For 8192 entries per TLBs. */
173#endif
174 ]; /* multiple of 64 */
175 } iem;
176
177 /** @name Static per-cpu data.
178 * (Putting this after IEM, hoping that it's less frequently used than it.)
179 * @{ */
180 /** Ring-3 Host Context VM Pointer. */
181 PVMR3 pVMR3;
182 /** Ring-0 Host Context VM Pointer, currently used by VTG/dtrace. */
183 RTR0PTR pVCpuR0ForVtg;
184 /** Raw-mode Context VM Pointer. */
185 uint32_t pVMRC;
186 /** Padding for new raw-mode (long mode). */
187 uint32_t pVMRCPadding;
188 /** Pointer to the ring-3 UVMCPU structure. */
189 PUVMCPU pUVCpu;
190 /** The native thread handle. */
191 RTNATIVETHREAD hNativeThread;
192 /** The native R0 thread handle. (different from the R3 handle!) */
193 RTNATIVETHREAD hNativeThreadR0;
194 /** The IPRT thread handle (for VMMDevTesting). */
195 RTTHREAD hThread;
196 /** The CPU ID.
197 * This is the index into the VM::aCpu array. */
198#ifdef IN_RING0
199 VMCPUID idCpuUnsafe;
200#else
201 VMCPUID idCpu;
202#endif
203
204 /** Align the structures below bit on a 64-byte boundary and make sure it starts
205 * at the same offset in both 64-bit and 32-bit builds.
206 *
207 * @remarks The alignments of the members that are larger than 48 bytes should be
208 * 64-byte for cache line reasons. structs containing small amounts of
209 * data could be lumped together at the end with a < 64 byte padding
210 * following it (to grow into and align the struct size).
211 */
212 uint8_t abAlignment1[64 - 6 * (HC_ARCH_BITS == 32 ? 4 : 8) - 8 - 4];
213 /** @} */
214
215 /** HM part. */
216 union VMCPUUNIONHM
217 {
218#ifdef VMM_INCLUDED_SRC_include_HMInternal_h
219 struct HMCPU s;
220#endif
221 uint8_t padding[9984]; /* multiple of 64 */
222 } hm;
223
224 /** NEM part. */
225 union VMCPUUNIONNEM
226 {
227#ifdef VMM_INCLUDED_SRC_include_NEMInternal_h
228 struct NEMCPU s;
229#endif
230 uint8_t padding[4608]; /* multiple of 64 */
231 } nem;
232
233 /** TRPM part. */
234 union VMCPUUNIONTRPM
235 {
236#ifdef VMM_INCLUDED_SRC_include_TRPMInternal_h
237 struct TRPMCPU s;
238#endif
239 uint8_t padding[128]; /* multiple of 64 */
240 } trpm;
241
242 /** TM part. */
243 union VMCPUUNIONTM
244 {
245#ifdef VMM_INCLUDED_SRC_include_TMInternal_h
246 struct TMCPU s;
247#endif
248 uint8_t padding[5760]; /* multiple of 64 */
249 } tm;
250
251 /** VMM part. */
252 union VMCPUUNIONVMM
253 {
254#ifdef VMM_INCLUDED_SRC_include_VMMInternal_h
255 struct VMMCPU s;
256#endif
257 uint8_t padding[9536]; /* multiple of 64 */
258 } vmm;
259
260 /** PDM part. */
261 union VMCPUUNIONPDM
262 {
263#ifdef VMM_INCLUDED_SRC_include_PDMInternal_h
264 struct PDMCPU s;
265#endif
266 uint8_t padding[256]; /* multiple of 64 */
267 } pdm;
268
269 /** IOM part. */
270 union VMCPUUNIONIOM
271 {
272#ifdef VMM_INCLUDED_SRC_include_IOMInternal_h
273 struct IOMCPU s;
274#endif
275 uint8_t padding[512]; /* multiple of 64 */
276 } iom;
277
278 /** DBGF part.
279 * @todo Combine this with other tiny structures. */
280 union VMCPUUNIONDBGF
281 {
282#ifdef VMM_INCLUDED_SRC_include_DBGFInternal_h
283 struct DBGFCPU s;
284#endif
285 uint8_t padding[512]; /* multiple of 64 */
286 } dbgf;
287
288 /** GIM part. */
289 union VMCPUUNIONGIM
290 {
291#ifdef VMM_INCLUDED_SRC_include_GIMInternal_h
292 struct GIMCPU s;
293#endif
294 uint8_t padding[512]; /* multiple of 64 */
295 } gim;
296
297 /* Interrupt controller, target specific. */
298 RT_GCC_EXTENSION
299 union
300 {
301#if defined(VBOX_VMM_TARGET_ARMV8) || defined(VBOX_VMM_TARGET_AGNOSTIC)
302 /** GIC part. */
303 union
304 {
305# ifdef VMM_INCLUDED_SRC_include_GICInternal_h
306 struct GICCPU s;
307# endif
308 uint8_t padding[3840]; /* multiple of 64 */
309 } gic;
310#endif
311#if defined(VBOX_VMM_TARGET_X86) || defined(VBOX_VMM_TARGET_AGNOSTIC)
312 /** APIC part. */
313 union
314 {
315# ifdef VMM_INCLUDED_SRC_include_APICInternal_h
316 struct APICCPU s;
317# endif
318 uint8_t padding[3840]; /* multiple of 64 */
319 } apic;
320#endif
321 };
322
323 /*
324 * Some less frequently used global members that doesn't need to take up
325 * precious space at the head of the structure.
326 */
327
328 /** Trace groups enable flags. */
329 uint32_t fTraceGroups; /* 64 / 44 */
330 /** Number of collisions hashing the ring-0 EMT handle. */
331 uint8_t cEmtHashCollisions;
332 uint8_t abAdHoc[3];
333 /** Profiling samples for use by ad hoc profiling. */
334 STAMPROFILEADV aStatAdHoc[8]; /* size: 40*8 = 320 */
335
336 /** Align the following members on page boundary. */
337 uint8_t abAlignment2[1848];
338
339 /** PGM part. */
340 union VMCPUUNIONPGM
341 {
342#ifdef VMM_INCLUDED_SRC_include_PGMInternal_h
343 struct PGMCPU s;
344#endif
345 uint8_t padding[36864]; /* multiple of 4096 */
346 } pgm;
347
348 /** CPUM part. */
349 union VMCPUUNIONCPUM
350 {
351#if defined(VMM_INCLUDED_SRC_include_CPUMInternal_h) || defined(VMM_INCLUDED_SRC_include_CPUMInternal_armv8_h)
352 struct CPUMCPU s;
353#endif
354#ifdef VMCPU_INCL_CPUM_GST_CTX
355 /** The guest CPUM context for direct use by execution engines.
356 * This is not for general consumption, but for HM, REM, IEM, and maybe a few
357 * others. The rest will use the function based CPUM API. */
358 CPUMCTX GstCtx;
359#endif
360 uint8_t padding[102400]; /* multiple of 4096 */
361 } cpum;
362
363 /** EM part. */
364 union VMCPUUNIONEM
365 {
366#ifdef VMM_INCLUDED_SRC_include_EMInternal_h
367 struct EMCPU s;
368#endif
369 uint8_t padding[40960]; /* multiple of 4096 */
370 } em;
371 uint8_t abPadding[12288];
372} VMCPU;
373
374
375#ifndef VBOX_FOR_DTRACE_LIB
376# ifndef IN_TSTVMSTRUCT
377/* Make sure the structure size is aligned on a 16384 boundary for arm64 purposes. */
378AssertCompileSizeAlignment(VMCPU, 16384);
379# endif
380
381/** @name Operations on VMCPU::enmState
382 * @{ */
383/** Gets the VMCPU state. */
384#define VMCPU_GET_STATE(pVCpu) ( (pVCpu)->enmState )
385/** Sets the VMCPU state. */
386#define VMCPU_SET_STATE(pVCpu, enmNewState) \
387 ASMAtomicWriteU32((uint32_t volatile *)&(pVCpu)->enmState, (enmNewState))
388/** Cmpares and sets the VMCPU state. */
389#define VMCPU_CMPXCHG_STATE(pVCpu, enmNewState, enmOldState) \
390 ASMAtomicCmpXchgU32((uint32_t volatile *)&(pVCpu)->enmState, (enmNewState), (enmOldState))
391/** Checks the VMCPU state. */
392#ifdef VBOX_STRICT
393# define VMCPU_ASSERT_STATE(pVCpu, enmExpectedState) \
394 do { \
395 VMCPUSTATE enmState = VMCPU_GET_STATE(pVCpu); \
396 AssertMsg(enmState == (enmExpectedState), \
397 ("enmState=%d enmExpectedState=%d idCpu=%u\n", \
398 enmState, enmExpectedState, (pVCpu)->idCpu)); \
399 } while (0)
400
401# define VMCPU_ASSERT_STATE_2(pVCpu, enmExpectedState, a_enmExpectedState2) \
402 do { \
403 VMCPUSTATE enmState = VMCPU_GET_STATE(pVCpu); \
404 AssertMsg( enmState == (enmExpectedState) \
405 || enmState == (a_enmExpectedState2), \
406 ("enmState=%d enmExpectedState=%d enmExpectedState2=%d idCpu=%u\n", \
407 enmState, enmExpectedState, a_enmExpectedState2, (pVCpu)->idCpu)); \
408 } while (0)
409#else
410# define VMCPU_ASSERT_STATE(pVCpu, enmExpectedState) do { } while (0)
411# define VMCPU_ASSERT_STATE_2(pVCpu, enmExpectedState, a_enmExpectedState2) do { } while (0)
412#endif
413/** Tests if the state means that the CPU is started. */
414#define VMCPUSTATE_IS_STARTED(enmState) ( (enmState) > VMCPUSTATE_STOPPED )
415/** Tests if the state means that the CPU is stopped. */
416#define VMCPUSTATE_IS_STOPPED(enmState) ( (enmState) == VMCPUSTATE_STOPPED )
417/** @} */
418
419
420/** The name of the raw-mode context VMM Core module. */
421#define VMMRC_MAIN_MODULE_NAME "VMMRC.rc"
422/** The name of the ring-0 context VMM Core module. */
423#define VMMR0_MAIN_MODULE_NAME "VMMR0.r0"
424
425
426/** VM Forced Action Flags.
427 *
428 * Use the VM_FF_SET() and VM_FF_CLEAR() macros to change the force
429 * action mask of a VM.
430 *
431 * Available VM bits:
432 * 5, 6, 7, 13, 14, 15, 16, 17, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30
433 *
434 *
435 * Available VMCPU bits:
436 * 14, 15, 36 to 63
437 *
438 * @todo If we run low on VMCPU, we may consider merging the SELM bits
439 *
440 * @{
441 */
442/* Bit 0, bit 1: Reserved and must not be reused. The recompiler ASSUMES it
443 can OR the local and global FFs together and keept the two
444 VMCPU_FF_INTERRUPT_XXX flags uncorrupted. */
445/** The virtual sync clock has been stopped, go to TM until it has been
446 * restarted... */
447#define VM_FF_TM_VIRTUAL_SYNC RT_BIT_32(VM_FF_TM_VIRTUAL_SYNC_BIT)
448#define VM_FF_TM_VIRTUAL_SYNC_BIT 2
449/** PDM Queues are pending. */
450#define VM_FF_PDM_QUEUES RT_BIT_32(VM_FF_PDM_QUEUES_BIT)
451/** The bit number for VM_FF_PDM_QUEUES. */
452#define VM_FF_PDM_QUEUES_BIT 3
453/** PDM DMA transfers are pending. */
454#define VM_FF_PDM_DMA RT_BIT_32(VM_FF_PDM_DMA_BIT)
455/** The bit number for VM_FF_PDM_DMA. */
456#define VM_FF_PDM_DMA_BIT 4
457/** This action forces the VM to call DBGF so DBGF can service debugger
458 * requests in the emulation thread.
459 * This action flag stays asserted till DBGF clears it.*/
460#define VM_FF_DBGF RT_BIT_32(VM_FF_DBGF_BIT)
461/** The bit number for VM_FF_DBGF. */
462#define VM_FF_DBGF_BIT 8
463/** This action forces the VM to service pending requests from other
464 * thread or requests which must be executed in another context. */
465#define VM_FF_REQUEST RT_BIT_32(VM_FF_REQUEST_BIT)
466#define VM_FF_REQUEST_BIT 9
467/** Check for VM state changes and take appropriate action. */
468#define VM_FF_CHECK_VM_STATE RT_BIT_32(VM_FF_CHECK_VM_STATE_BIT)
469/** The bit number for VM_FF_CHECK_VM_STATE. */
470#define VM_FF_CHECK_VM_STATE_BIT 10
471/** Reset the VM. (postponed) */
472#define VM_FF_RESET RT_BIT_32(VM_FF_RESET_BIT)
473/** The bit number for VM_FF_RESET. */
474#define VM_FF_RESET_BIT 11
475/** EMT rendezvous in VMM. */
476#define VM_FF_EMT_RENDEZVOUS RT_BIT_32(VM_FF_EMT_RENDEZVOUS_BIT)
477/** The bit number for VM_FF_EMT_RENDEZVOUS. */
478#define VM_FF_EMT_RENDEZVOUS_BIT 12
479
480/** PGM needs to allocate handy pages. */
481#define VM_FF_PGM_NEED_HANDY_PAGES RT_BIT_32(VM_FF_PGM_NEED_HANDY_PAGES_BIT)
482#define VM_FF_PGM_NEED_HANDY_PAGES_BIT 18
483/** PGM is out of memory.
484 * Abandon all loops and code paths which can be resumed and get up to the EM
485 * loops. */
486#define VM_FF_PGM_NO_MEMORY RT_BIT_32(VM_FF_PGM_NO_MEMORY_BIT)
487#define VM_FF_PGM_NO_MEMORY_BIT 19
488 /** PGM is about to perform a lightweight pool flush
489 * Guest SMP: all EMT threads should return to ring 3
490 */
491#define VM_FF_PGM_POOL_FLUSH_PENDING RT_BIT_32(VM_FF_PGM_POOL_FLUSH_PENDING_BIT)
492#define VM_FF_PGM_POOL_FLUSH_PENDING_BIT 20
493/** Suspend the VM - debug only. */
494#define VM_FF_DEBUG_SUSPEND RT_BIT_32(VM_FF_DEBUG_SUSPEND_BIT)
495#define VM_FF_DEBUG_SUSPEND_BIT 31
496
497
498#if defined(VBOX_VMM_TARGET_ARMV8) || defined(VBOX_VMM_TARGET_AGNOSTIC)
499/** This action forces the VM to inject an IRQ into the guest. */
500# define VMCPU_FF_INTERRUPT_IRQ RT_BIT_64(VMCPU_FF_INTERRUPT_IRQ_BIT)
501# define VMCPU_FF_INTERRUPT_IRQ_BIT 0
502/** This action forces the VM to inject an FIQ into the guest. */
503# define VMCPU_FF_INTERRUPT_FIQ RT_BIT_64(VMCPU_FF_INTERRUPT_FIQ_BIT)
504# define VMCPU_FF_INTERRUPT_FIQ_BIT 1
505#endif
506#if defined(VBOX_VMM_TARGET_X86) || defined(VBOX_VMM_TARGET_AGNOSTIC)
507/** This action forces the VM to check any pending interrupts on the APIC. */
508# define VMCPU_FF_INTERRUPT_APIC RT_BIT_64(VMCPU_FF_INTERRUPT_APIC_BIT)
509# define VMCPU_FF_INTERRUPT_APIC_BIT 0
510/** This action forces the VM to check any pending interrups on the PIC. */
511# define VMCPU_FF_INTERRUPT_PIC RT_BIT_64(VMCPU_FF_INTERRUPT_PIC_BIT)
512# define VMCPU_FF_INTERRUPT_PIC_BIT 1
513#endif
514/** This action forces the VM to schedule and run pending timer (TM).
515 * @remarks Don't move - PATM compatibility. */
516#define VMCPU_FF_TIMER RT_BIT_64(VMCPU_FF_TIMER_BIT)
517#define VMCPU_FF_TIMER_BIT 2
518/** This action forces the VM to check any pending NMIs. */
519#define VMCPU_FF_INTERRUPT_NMI RT_BIT_64(VMCPU_FF_INTERRUPT_NMI_BIT)
520#define VMCPU_FF_INTERRUPT_NMI_BIT 3
521/** This action forces the VM to check any pending SMIs. */
522#define VMCPU_FF_INTERRUPT_SMI RT_BIT_64(VMCPU_FF_INTERRUPT_SMI_BIT)
523#define VMCPU_FF_INTERRUPT_SMI_BIT 4
524/** PDM critical section unlocking is pending, process promptly upon return to R3. */
525#define VMCPU_FF_PDM_CRITSECT RT_BIT_64(VMCPU_FF_PDM_CRITSECT_BIT)
526#define VMCPU_FF_PDM_CRITSECT_BIT 5
527/** Special EM internal force flag that is used by EMUnhaltAndWakeUp() to force
528 * the virtual CPU out of the next (/current) halted state. It is not processed
529 * nor cleared by emR3ForcedActions (similar to VMCPU_FF_BLOCK_NMIS), instead it
530 * is cleared the next time EM leaves the HALTED state. */
531#define VMCPU_FF_UNHALT RT_BIT_64(VMCPU_FF_UNHALT_BIT)
532#define VMCPU_FF_UNHALT_BIT 6
533/** Pending IEM action (mask). */
534#define VMCPU_FF_IEM RT_BIT_64(VMCPU_FF_IEM_BIT)
535/** Pending IEM action (bit number). */
536#define VMCPU_FF_IEM_BIT 7
537/** Pending APIC action (bit number). */
538#define VMCPU_FF_UPDATE_APIC_BIT 8
539/** This action forces the VM to update APIC's asynchronously arrived
540 * interrupts as pending interrupts. */
541#define VMCPU_FF_UPDATE_APIC RT_BIT_64(VMCPU_FF_UPDATE_APIC_BIT)
542/** This action forces the VM to service pending requests from other
543 * thread or requests which must be executed in another context. */
544#define VMCPU_FF_REQUEST RT_BIT_64(VMCPU_FF_REQUEST_BIT)
545#define VMCPU_FF_REQUEST_BIT 9
546/** Pending DBGF event (alternative to passing VINF_EM_DBG_EVENT around). */
547#define VMCPU_FF_DBGF RT_BIT_64(VMCPU_FF_DBGF_BIT)
548/** The bit number for VMCPU_FF_DBGF. */
549#define VMCPU_FF_DBGF_BIT 10
550/** Hardware virtualized nested-guest interrupt pending. */
551#define VMCPU_FF_INTERRUPT_NESTED_GUEST RT_BIT_64(VMCPU_FF_INTERRUPT_NESTED_GUEST_BIT)
552#define VMCPU_FF_INTERRUPT_NESTED_GUEST_BIT 11
553/** This action forces PGM to update changes to CR3 when the guest was in HM mode
554 * (when using nested paging). */
555#define VMCPU_FF_HM_UPDATE_CR3 RT_BIT_64(VMCPU_FF_HM_UPDATE_CR3_BIT)
556#define VMCPU_FF_HM_UPDATE_CR3_BIT 12
557#if defined(VBOX_VMM_TARGET_ARMV8) || defined(VBOX_VMM_TARGET_AGNOSTIC)
558# define VMCPU_FF_VTIMER_ACTIVATED RT_BIT_64(VMCPU_FF_VTIMER_ACTIVATED_BIT)
559# define VMCPU_FF_VTIMER_ACTIVATED_BIT 13
560#endif
561#if defined(VBOX_VMM_TARGET_X86) || defined(VBOX_VMM_TARGET_AGNOSTIC)
562/* Bit 13 used to be VMCPU_FF_HM_UPDATE_PAE_PDPES. */
563#endif
564/** This action forces the VM to resync the page tables before going
565 * back to execute guest code. (GLOBAL FLUSH) */
566#define VMCPU_FF_PGM_SYNC_CR3 RT_BIT_64(VMCPU_FF_PGM_SYNC_CR3_BIT)
567#define VMCPU_FF_PGM_SYNC_CR3_BIT 16
568/** Same as VM_FF_PGM_SYNC_CR3 except that global pages can be skipped.
569 * (NON-GLOBAL FLUSH) */
570#define VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL RT_BIT_64(VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL_BIT)
571#define VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL_BIT 17
572/** Check for pending TLB shootdown actions (deprecated)
573 * Reserved for future HM re-use if necessary / safe.
574 * Consumer: HM */
575#define VMCPU_FF_TLB_SHOOTDOWN_UNUSED RT_BIT_64(VMCPU_FF_TLB_SHOOTDOWN_UNUSED_BIT)
576#define VMCPU_FF_TLB_SHOOTDOWN_UNUSED_BIT 18
577/** Check for pending TLB flush action.
578 * Consumer: HM
579 * @todo rename to VMCPU_FF_HM_TLB_FLUSH */
580#define VMCPU_FF_TLB_FLUSH RT_BIT_64(VMCPU_FF_TLB_FLUSH_BIT)
581/** The bit number for VMCPU_FF_TLB_FLUSH. */
582#define VMCPU_FF_TLB_FLUSH_BIT 19
583/* 20 used to be VMCPU_FF_TRPM_SYNC_IDT (raw-mode only). */
584/* 21 used to be VMCPU_FF_SELM_SYNC_TSS (raw-mode only). */
585/* 22 used to be VMCPU_FF_SELM_SYNC_GDT (raw-mode only). */
586/* 23 used to be VMCPU_FF_SELM_SYNC_LDT (raw-mode only). */
587/* 24 used to be VMCPU_FF_INHIBIT_INTERRUPTS, which moved to CPUMCTX::eflags.uBoth in v7.0.4. */
588/* 25 used to be VMCPU_FF_BLOCK_NMIS, which moved to CPUMCTX::eflags.uBoth in v7.0.4. */
589/** Force return to Ring-3. */
590#define VMCPU_FF_TO_R3 RT_BIT_64(VMCPU_FF_TO_R3_BIT)
591#define VMCPU_FF_TO_R3_BIT 28
592/** Force return to ring-3 to service pending I/O or MMIO write.
593 * This is a backup for mechanism VINF_IOM_R3_IOPORT_COMMIT_WRITE and
594 * VINF_IOM_R3_MMIO_COMMIT_WRITE, allowing VINF_EM_DBG_BREAKPOINT and similar
595 * status codes to be propagated at the same time without loss. */
596#define VMCPU_FF_IOM RT_BIT_64(VMCPU_FF_IOM_BIT)
597#define VMCPU_FF_IOM_BIT 29
598/* 30 used to be VMCPU_FF_CPUM */
599/** VMX-preemption timer expired. */
600#define VMCPU_FF_VMX_PREEMPT_TIMER RT_BIT_64(VMCPU_FF_VMX_PREEMPT_TIMER_BIT)
601#define VMCPU_FF_VMX_PREEMPT_TIMER_BIT 31
602/** Pending MTF (Monitor Trap Flag) event. */
603#define VMCPU_FF_VMX_MTF RT_BIT_64(VMCPU_FF_VMX_MTF_BIT)
604#define VMCPU_FF_VMX_MTF_BIT 32
605/** VMX APIC-write emulation pending.
606 * @todo possible candidate for internal EFLAGS, or maybe just a summary bit
607 * (see also VMCPU_FF_VMX_INT_WINDOW). */
608#define VMCPU_FF_VMX_APIC_WRITE RT_BIT_64(VMCPU_FF_VMX_APIC_WRITE_BIT)
609#define VMCPU_FF_VMX_APIC_WRITE_BIT 33
610/** VMX interrupt-window event pending.
611 *
612 * "Pending" is misleading here, it would be better to say that the event need
613 * to be generated at the next opportunity and that this flag causes it to be
614 * polled for on every instruction boundrary and such.
615 *
616 * @todo Change the IEM side of this to not poll but to track down the places
617 * where it can be generated and set an internal EFLAGS bit that causes it
618 * to be checked out when finishing the current instruction. */
619#define VMCPU_FF_VMX_INT_WINDOW RT_BIT_64(VMCPU_FF_VMX_INT_WINDOW_BIT)
620#define VMCPU_FF_VMX_INT_WINDOW_BIT 34
621/** VMX NMI-window event pending.
622 * Same "pending" comment and todo in VMCPU_FF_VMX_INT_WINDOW. */
623#define VMCPU_FF_VMX_NMI_WINDOW RT_BIT_64(VMCPU_FF_VMX_NMI_WINDOW_BIT)
624#define VMCPU_FF_VMX_NMI_WINDOW_BIT 35
625
626
627/** Externally VM forced actions. Used to quit the idle/wait loop. */
628#define VM_FF_EXTERNAL_SUSPENDED_MASK ( VM_FF_CHECK_VM_STATE | VM_FF_DBGF | VM_FF_REQUEST | VM_FF_EMT_RENDEZVOUS )
629/** Externally VMCPU forced actions. Used to quit the idle/wait loop. */
630#define VMCPU_FF_EXTERNAL_SUSPENDED_MASK ( VMCPU_FF_REQUEST | VMCPU_FF_DBGF )
631
632/** Externally forced VM actions. Used to quit the idle/wait loop. */
633#define VM_FF_EXTERNAL_HALTED_MASK ( VM_FF_CHECK_VM_STATE | VM_FF_DBGF | VM_FF_REQUEST \
634 | VM_FF_PDM_QUEUES | VM_FF_PDM_DMA | VM_FF_EMT_RENDEZVOUS )
635
636#ifndef VBOX_VMM_TARGET_AGNOSTIC
637/** Externally forced VMCPU actions. Used to quit the idle/wait loop. */
638# if defined(VBOX_VMM_TARGET_ARMV8)
639# define VMCPU_FF_EXTERNAL_HALTED_MASK ( VMCPU_FF_INTERRUPT_IRQ | VMCPU_FF_INTERRUPT_FIQ \
640 | VMCPU_FF_REQUEST | VMCPU_FF_INTERRUPT_NMI | VMCPU_FF_INTERRUPT_SMI \
641 | VMCPU_FF_UNHALT | VMCPU_FF_TIMER | VMCPU_FF_DBGF \
642 | VMCPU_FF_VTIMER_ACTIVATED)
643# else
644# define VMCPU_FF_EXTERNAL_HALTED_MASK ( VMCPU_FF_UPDATE_APIC | VMCPU_FF_INTERRUPT_APIC | VMCPU_FF_INTERRUPT_PIC \
645 | VMCPU_FF_REQUEST | VMCPU_FF_INTERRUPT_NMI | VMCPU_FF_INTERRUPT_SMI \
646 | VMCPU_FF_UNHALT | VMCPU_FF_TIMER | VMCPU_FF_DBGF \
647 | VMCPU_FF_INTERRUPT_NESTED_GUEST)
648# endif
649#endif
650
651/** High priority VM pre-execution actions. */
652#define VM_FF_HIGH_PRIORITY_PRE_MASK ( VM_FF_CHECK_VM_STATE | VM_FF_DBGF | VM_FF_TM_VIRTUAL_SYNC \
653 | VM_FF_DEBUG_SUSPEND | VM_FF_PGM_NEED_HANDY_PAGES | VM_FF_PGM_NO_MEMORY \
654 | VM_FF_EMT_RENDEZVOUS )
655#ifndef VBOX_VMM_TARGET_AGNOSTIC
656/** High priority VMCPU pre-execution actions. */
657# if defined(VBOX_VMM_TARGET_ARMV8)
658# define VMCPU_FF_HIGH_PRIORITY_PRE_MASK ( VMCPU_FF_TIMER | VMCPU_FF_INTERRUPT_IRQ | VMCPU_FF_INTERRUPT_FIQ \
659 | VMCPU_FF_DBGF )
660# else
661# define VMCPU_FF_HIGH_PRIORITY_PRE_MASK ( VMCPU_FF_TIMER | VMCPU_FF_INTERRUPT_APIC | VMCPU_FF_INTERRUPT_PIC \
662 | VMCPU_FF_UPDATE_APIC | VMCPU_FF_DBGF \
663 | VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL \
664 | VMCPU_FF_INTERRUPT_NESTED_GUEST | VMCPU_FF_VMX_MTF | VMCPU_FF_VMX_APIC_WRITE \
665 | VMCPU_FF_VMX_PREEMPT_TIMER | VMCPU_FF_VMX_NMI_WINDOW | VMCPU_FF_VMX_INT_WINDOW )
666# endif
667#endif
668
669/** High priority VM pre raw-mode execution mask. */
670#define VM_FF_HIGH_PRIORITY_PRE_RAW_MASK ( VM_FF_PGM_NEED_HANDY_PAGES | VM_FF_PGM_NO_MEMORY )
671/** High priority VMCPU pre raw-mode execution mask. */
672#define VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK ( VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL )
673
674/** High priority post-execution actions. */
675#define VM_FF_HIGH_PRIORITY_POST_MASK ( VM_FF_PGM_NO_MEMORY )
676/** High priority post-execution actions. */
677#define VMCPU_FF_HIGH_PRIORITY_POST_MASK ( VMCPU_FF_PDM_CRITSECT | VMCPU_FF_HM_UPDATE_CR3 | VMCPU_FF_IEM | VMCPU_FF_IOM )
678
679/** Normal priority VM post-execution actions. */
680#define VM_FF_NORMAL_PRIORITY_POST_MASK ( VM_FF_CHECK_VM_STATE | VM_FF_DBGF | VM_FF_RESET \
681 | VM_FF_PGM_NO_MEMORY | VM_FF_EMT_RENDEZVOUS)
682/** Normal priority VMCPU post-execution actions. */
683#define VMCPU_FF_NORMAL_PRIORITY_POST_MASK ( VMCPU_FF_DBGF )
684
685/** Normal priority VM actions. */
686#define VM_FF_NORMAL_PRIORITY_MASK ( VM_FF_REQUEST | VM_FF_PDM_QUEUES | VM_FF_PDM_DMA | VM_FF_EMT_RENDEZVOUS)
687/** Normal priority VMCPU actions. */
688#define VMCPU_FF_NORMAL_PRIORITY_MASK ( VMCPU_FF_REQUEST )
689
690/** Flags to clear before resuming guest execution. */
691#define VMCPU_FF_RESUME_GUEST_MASK ( VMCPU_FF_TO_R3 )
692
693
694/** VM flags that cause the REP[|NE|E] STRINS loops to yield immediately. */
695#define VM_FF_HIGH_PRIORITY_POST_REPSTR_MASK ( VM_FF_TM_VIRTUAL_SYNC | VM_FF_PGM_NEED_HANDY_PAGES | VM_FF_PGM_NO_MEMORY \
696 | VM_FF_EMT_RENDEZVOUS | VM_FF_PGM_POOL_FLUSH_PENDING | VM_FF_RESET)
697/** VM flags that cause the REP[|NE|E] STRINS loops to yield. */
698#define VM_FF_YIELD_REPSTR_MASK ( VM_FF_HIGH_PRIORITY_POST_REPSTR_MASK \
699 | VM_FF_PDM_QUEUES | VM_FF_PDM_DMA | VM_FF_DBGF | VM_FF_DEBUG_SUSPEND )
700/** VMCPU flags that cause the REP[|NE|E] STRINS loops to yield immediately. */
701#ifdef IN_RING3
702# define VMCPU_FF_HIGH_PRIORITY_POST_REPSTR_MASK (VMCPU_FF_DBGF | VMCPU_FF_VMX_MTF)
703#else
704# define VMCPU_FF_HIGH_PRIORITY_POST_REPSTR_MASK (VMCPU_FF_TO_R3 | VMCPU_FF_IEM | VMCPU_FF_IOM | VMCPU_FF_DBGF | VMCPU_FF_VMX_MTF)
705#endif
706
707#if defined(VBOX_VMM_TARGET_X86) || defined(VBOX_VMM_TARGET_AGNOSTIC)
708/** VMCPU flags that cause the REP[|NE|E] STRINS loops to yield, interrupts
709 * enabled. */
710# define VMCPU_FF_YIELD_REPSTR_MASK ( VMCPU_FF_HIGH_PRIORITY_POST_REPSTR_MASK \
711 | VMCPU_FF_INTERRUPT_APIC | VMCPU_FF_UPDATE_APIC | VMCPU_FF_INTERRUPT_PIC \
712 | VMCPU_FF_INTERRUPT_NMI | VMCPU_FF_INTERRUPT_SMI | VMCPU_FF_PDM_CRITSECT \
713 | VMCPU_FF_TIMER | VMCPU_FF_REQUEST \
714 | VMCPU_FF_INTERRUPT_NESTED_GUEST )
715/** VMCPU flags that cause the REP[|NE|E] STRINS loops to yield, interrupts
716 * disabled. */
717# define VMCPU_FF_YIELD_REPSTR_NOINT_MASK ( VMCPU_FF_YIELD_REPSTR_MASK \
718 & ~( VMCPU_FF_INTERRUPT_APIC | VMCPU_FF_UPDATE_APIC | VMCPU_FF_INTERRUPT_PIC \
719 | VMCPU_FF_INTERRUPT_NESTED_GUEST) )
720#endif
721
722/** VM Flags that cause the HM loops to go back to ring-3. */
723#define VM_FF_HM_TO_R3_MASK ( VM_FF_TM_VIRTUAL_SYNC | VM_FF_PGM_NEED_HANDY_PAGES | VM_FF_PGM_NO_MEMORY \
724 | VM_FF_PDM_QUEUES | VM_FF_EMT_RENDEZVOUS)
725/** VMCPU Flags that cause the HM loops to go back to ring-3. */
726#define VMCPU_FF_HM_TO_R3_MASK ( VMCPU_FF_TO_R3 | VMCPU_FF_TIMER | VMCPU_FF_PDM_CRITSECT \
727 | VMCPU_FF_IEM | VMCPU_FF_IOM)
728
729/** High priority ring-0 VM pre HM-mode execution mask. */
730#define VM_FF_HP_R0_PRE_HM_MASK (VM_FF_HM_TO_R3_MASK | VM_FF_REQUEST | VM_FF_PGM_POOL_FLUSH_PENDING | VM_FF_PDM_DMA)
731/** High priority ring-0 VMCPU pre HM-mode execution mask. */
732#define VMCPU_FF_HP_R0_PRE_HM_MASK ( VMCPU_FF_HM_TO_R3_MASK | VMCPU_FF_PGM_SYNC_CR3 \
733 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL | VMCPU_FF_REQUEST \
734 | VMCPU_FF_VMX_APIC_WRITE | VMCPU_FF_VMX_MTF | VMCPU_FF_VMX_PREEMPT_TIMER)
735/** High priority ring-0 VM pre HM-mode execution mask, single stepping. */
736#define VM_FF_HP_R0_PRE_HM_STEP_MASK (VM_FF_HP_R0_PRE_HM_MASK & ~( VM_FF_TM_VIRTUAL_SYNC | VM_FF_PDM_QUEUES \
737 | VM_FF_EMT_RENDEZVOUS | VM_FF_REQUEST \
738 | VM_FF_PDM_DMA) )
739/** High priority ring-0 VMCPU pre HM-mode execution mask, single stepping. */
740#define VMCPU_FF_HP_R0_PRE_HM_STEP_MASK (VMCPU_FF_HP_R0_PRE_HM_MASK & ~( VMCPU_FF_TO_R3 | VMCPU_FF_TIMER \
741 | VMCPU_FF_PDM_CRITSECT | VMCPU_FF_REQUEST) )
742
743/** All the VMX nested-guest flags. */
744#define VMCPU_FF_VMX_ALL_MASK ( VMCPU_FF_VMX_PREEMPT_TIMER | VMCPU_FF_VMX_MTF | VMCPU_FF_VMX_APIC_WRITE \
745 | VMCPU_FF_VMX_INT_WINDOW | VMCPU_FF_VMX_NMI_WINDOW )
746
747/** All the forced VM flags. */
748#define VM_FF_ALL_MASK (UINT32_MAX)
749/** All the forced VMCPU flags. */
750#define VMCPU_FF_ALL_MASK ( UINT32_MAX \
751 | VMCPU_FF_VMX_MTF | VMCPU_FF_VMX_APIC_WRITE | VMCPU_FF_VMX_INT_WINDOW \
752 | VMCPU_FF_VMX_NMI_WINDOW )
753
754/** All the forced VM flags except those related to raw-mode and hardware
755 * assisted execution. */
756#define VM_FF_ALL_REM_MASK (~(VM_FF_HIGH_PRIORITY_PRE_RAW_MASK) | VM_FF_PGM_NEED_HANDY_PAGES | VM_FF_PGM_NO_MEMORY)
757/** All the forced VMCPU flags except those related to raw-mode and hardware
758 * assisted execution. */
759#define VMCPU_FF_ALL_REM_MASK (~(VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK | VMCPU_FF_PDM_CRITSECT | VMCPU_FF_TLB_FLUSH))
760
761#ifndef VBOX_FOR_DTRACE_LIB
762AssertCompile( ((VM_FF_HIGH_PRIORITY_POST_REPSTR_MASK | VM_FF_YIELD_REPSTR_MASK)
763 & (VM_FF_HIGH_PRIORITY_PRE_RAW_MASK & ~VM_FF_ALL_REM_MASK)) == 0);
764AssertCompile((VMCPU_FF_HIGH_PRIORITY_POST_REPSTR_MASK & (VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK & ~VMCPU_FF_ALL_REM_MASK)) == 0);
765#endif
766
767/** @} */
768
769/** @def VM_FF_SET
770 * Sets a single force action flag.
771 *
772 * @param pVM The cross context VM structure.
773 * @param fFlag The flag to set.
774 */
775#define VM_FF_SET(pVM, fFlag) do { \
776 AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
777 AssertCompile((fFlag) == RT_BIT_32(fFlag##_BIT)); \
778 ASMAtomicOrU32(&(pVM)->fGlobalForcedActions, (fFlag)); \
779 } while (0)
780
781/** @def VMCPU_FF_SET
782 * Sets a single force action flag for the given VCPU.
783 *
784 * @param pVCpu The cross context virtual CPU structure.
785 * @param fFlag The flag to set.
786 * @sa VMCPU_FF_SET_MASK
787 */
788#ifdef VMCPU_WITH_64_BIT_FFS
789# define VMCPU_FF_SET(pVCpu, fFlag) do { \
790 AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
791 AssertCompile((fFlag) == RT_BIT_64(fFlag##_BIT)); \
792 ASMAtomicBitSet(&(pVCpu)->fLocalForcedActions, fFlag##_BIT); \
793 } while (0)
794#else
795# define VMCPU_FF_SET(pVCpu, fFlag) do { \
796 AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
797 AssertCompile((fFlag) == RT_BIT_32(fFlag##_BIT)); \
798 ASMAtomicOrU32(&(pVCpu)->fLocalForcedActions, (fFlag)); \
799 } while (0)
800#endif
801
802/** @def VMCPU_FF_SET_MASK
803 * Sets a two or more force action flag for the given VCPU.
804 *
805 * @param pVCpu The cross context virtual CPU structure.
806 * @param fFlags The flags to set.
807 * @sa VMCPU_FF_SET
808 */
809#ifdef VMCPU_WITH_64_BIT_FFS
810# if ARCH_BITS > 32
811# define VMCPU_FF_SET_MASK(pVCpu, fFlags) \
812 do { ASMAtomicOrU64(&pVCpu->fLocalForcedActions, (fFlags)); } while (0)
813# else
814# define VMCPU_FF_SET_MASK(pVCpu, fFlags) do { \
815 if (!((fFlags) >> 32)) ASMAtomicOrU32((uint32_t volatile *)&pVCpu->fLocalForcedActions, (uint32_t)(fFlags)); \
816 else ASMAtomicOrU64(&pVCpu->fLocalForcedActions, (fFlags)); \
817 } while (0)
818# endif
819#else
820# define VMCPU_FF_SET_MASK(pVCpu, fFlags) \
821 do { ASMAtomicOrU32(&pVCpu->fLocalForcedActions, (fFlags)); } while (0)
822#endif
823
824/** @def VM_FF_CLEAR
825 * Clears a single force action flag.
826 *
827 * @param pVM The cross context VM structure.
828 * @param fFlag The flag to clear.
829 */
830#define VM_FF_CLEAR(pVM, fFlag) do { \
831 AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
832 AssertCompile((fFlag) == RT_BIT_32(fFlag##_BIT)); \
833 ASMAtomicAndU32(&(pVM)->fGlobalForcedActions, ~(fFlag)); \
834 } while (0)
835
836/** @def VMCPU_FF_CLEAR
837 * Clears a single force action flag for the given VCPU.
838 *
839 * @param pVCpu The cross context virtual CPU structure.
840 * @param fFlag The flag to clear.
841 */
842#ifdef VMCPU_WITH_64_BIT_FFS
843# define VMCPU_FF_CLEAR(pVCpu, fFlag) do { \
844 AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
845 AssertCompile((fFlag) == RT_BIT_64(fFlag##_BIT)); \
846 ASMAtomicBitClear(&(pVCpu)->fLocalForcedActions, fFlag##_BIT); \
847 } while (0)
848#else
849# define VMCPU_FF_CLEAR(pVCpu, fFlag) do { \
850 AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
851 AssertCompile((fFlag) == RT_BIT_32(fFlag##_BIT)); \
852 ASMAtomicAndU32(&(pVCpu)->fLocalForcedActions, ~(fFlag)); \
853 } while (0)
854#endif
855
856/** @def VMCPU_FF_CLEAR_MASK
857 * Clears two or more force action flags for the given VCPU.
858 *
859 * @param pVCpu The cross context virtual CPU structure.
860 * @param fFlags The flags to clear.
861 */
862#ifdef VMCPU_WITH_64_BIT_FFS
863# if ARCH_BITS > 32
864# define VMCPU_FF_CLEAR_MASK(pVCpu, fFlags) \
865 do { ASMAtomicAndU64(&(pVCpu)->fLocalForcedActions, ~(fFlags)); } while (0)
866# else
867# define VMCPU_FF_CLEAR_MASK(pVCpu, fFlags) do { \
868 if (!((fFlags) >> 32)) ASMAtomicAndU32((uint32_t volatile *)&(pVCpu)->fLocalForcedActions, ~(uint32_t)(fFlags)); \
869 else ASMAtomicAndU64(&(pVCpu)->fLocalForcedActions, ~(fFlags)); \
870 } while (0)
871# endif
872#else
873# define VMCPU_FF_CLEAR_MASK(pVCpu, fFlags) \
874 do { ASMAtomicAndU32(&(pVCpu)->fLocalForcedActions, ~(fFlags)); } while (0)
875#endif
876
877/** @def VM_FF_IS_SET
878 * Checks if single a force action flag is set.
879 *
880 * @param pVM The cross context VM structure.
881 * @param fFlag The flag to check.
882 * @sa VM_FF_IS_ANY_SET
883 */
884#if !defined(VBOX_STRICT) || !defined(RT_COMPILER_SUPPORTS_LAMBDA)
885# define VM_FF_IS_SET(pVM, fFlag) RT_BOOL((pVM)->fGlobalForcedActions & (fFlag))
886#else
887# define VM_FF_IS_SET(pVM, fFlag) \
888 ([](PVM a_pVM) -> bool \
889 { \
890 AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
891 AssertCompile((fFlag) == RT_BIT_32(fFlag##_BIT)); \
892 return RT_BOOL(a_pVM->fGlobalForcedActions & (fFlag)); \
893 }(pVM))
894#endif
895
896/** @def VMCPU_FF_IS_SET
897 * Checks if a single force action flag is set for the given VCPU.
898 *
899 * @param pVCpu The cross context virtual CPU structure.
900 * @param fFlag The flag to check.
901 * @sa VMCPU_FF_IS_ANY_SET
902 */
903#if !defined(VBOX_STRICT) || !defined(RT_COMPILER_SUPPORTS_LAMBDA)
904# define VMCPU_FF_IS_SET(pVCpu, fFlag) RT_BOOL((pVCpu)->fLocalForcedActions & (fFlag))
905#else
906# define VMCPU_FF_IS_SET(pVCpu, fFlag) \
907 ([](PCVMCPU a_pVCpu) -> bool \
908 { \
909 AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
910 AssertCompile((fFlag) == RT_BIT_64(fFlag##_BIT)); \
911 return RT_BOOL(a_pVCpu->fLocalForcedActions & (fFlag)); \
912 }(pVCpu))
913#endif
914
915/** @def VM_FF_IS_ANY_SET
916 * Checks if one or more force action in the specified set is pending.
917 *
918 * @param pVM The cross context VM structure.
919 * @param fFlags The flags to check for.
920 * @sa VM_FF_IS_SET
921 */
922#define VM_FF_IS_ANY_SET(pVM, fFlags) RT_BOOL((pVM)->fGlobalForcedActions & (fFlags))
923
924/** @def VMCPU_FF_IS_ANY_SET
925 * Checks if two or more force action flags in the specified set is set for the given VCPU.
926 *
927 * @param pVCpu The cross context virtual CPU structure.
928 * @param fFlags The flags to check for.
929 * @sa VMCPU_FF_IS_SET
930 */
931#define VMCPU_FF_IS_ANY_SET(pVCpu, fFlags) RT_BOOL((pVCpu)->fLocalForcedActions & (fFlags))
932
933/** @def VM_FF_TEST_AND_CLEAR
934 * Checks if one (!) force action in the specified set is pending and clears it atomically
935 *
936 * @returns true if the bit was set.
937 * @returns false if the bit was clear.
938 * @param pVM The cross context VM structure.
939 * @param fFlag Flag constant to check and clear (_BIT is appended).
940 */
941#define VM_FF_TEST_AND_CLEAR(pVM, fFlag) (ASMAtomicBitTestAndClear(&(pVM)->fGlobalForcedActions, fFlag##_BIT))
942
943/** @def VMCPU_FF_TEST_AND_CLEAR
944 * Checks if one (!) force action in the specified set is pending and clears it atomically
945 *
946 * @returns true if the bit was set.
947 * @returns false if the bit was clear.
948 * @param pVCpu The cross context virtual CPU structure.
949 * @param fFlag Flag constant to check and clear (_BIT is appended).
950 */
951#define VMCPU_FF_TEST_AND_CLEAR(pVCpu, fFlag) (ASMAtomicBitTestAndClear(&(pVCpu)->fLocalForcedActions, fFlag##_BIT))
952
953/** @def VM_FF_IS_PENDING_EXCEPT
954 * Checks if one or more force action in the specified set is pending while one
955 * or more other ones are not.
956 *
957 * @param pVM The cross context VM structure.
958 * @param fFlags The flags to check for.
959 * @param fExcpt The flags that should not be set.
960 */
961#define VM_FF_IS_PENDING_EXCEPT(pVM, fFlags, fExcpt) \
962 ( ((pVM)->fGlobalForcedActions & (fFlags)) && !((pVM)->fGlobalForcedActions & (fExcpt)) )
963
964/** @def VM_IS_EMT
965 * Checks if the current thread is the emulation thread (EMT).
966 *
967 * @remark The ring-0 variation will need attention if we expand the ring-0
968 * code to let threads other than EMT mess around with the VM.
969 */
970#ifdef IN_RC
971# define VM_IS_EMT(pVM) true
972#else
973# define VM_IS_EMT(pVM) (VMMGetCpu(pVM) != NULL)
974#endif
975
976/** @def VMCPU_IS_EMT
977 * Checks if the current thread is the emulation thread (EMT) for the specified
978 * virtual CPU.
979 */
980#ifdef IN_RC
981# define VMCPU_IS_EMT(pVCpu) true
982#else
983# define VMCPU_IS_EMT(pVCpu) ((pVCpu) && ((pVCpu) == VMMGetCpu((pVCpu)->CTX_SUFF(pVM))))
984#endif
985
986/** @def VM_ASSERT_EMT
987 * Asserts that the current thread IS the emulation thread (EMT).
988 */
989#ifdef IN_RC
990# define VM_ASSERT_EMT(pVM) Assert(VM_IS_EMT(pVM))
991#elif defined(IN_RING0)
992# define VM_ASSERT_EMT(pVM) Assert(VM_IS_EMT(pVM))
993#else
994# define VM_ASSERT_EMT(pVM) \
995 AssertMsg(VM_IS_EMT(pVM), \
996 ("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd\n", RTThreadNativeSelf(), VMR3GetVMCPUNativeThread(pVM)))
997#endif
998
999/** @def VMCPU_ASSERT_EMT
1000 * Asserts that the current thread IS the emulation thread (EMT) of the
1001 * specified virtual CPU.
1002 */
1003#ifdef IN_RC
1004# define VMCPU_ASSERT_EMT(pVCpu) Assert(VMCPU_IS_EMT(pVCpu))
1005#elif defined(IN_RING0)
1006# define VMCPU_ASSERT_EMT(pVCpu) AssertMsg(VMCPU_IS_EMT(pVCpu), \
1007 ("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd idCpu=%u\n", \
1008 RTThreadNativeSelf(), (pVCpu) ? (pVCpu)->hNativeThreadR0 : 0, \
1009 (pVCpu) ? (pVCpu)->idCpu : 0))
1010#else
1011# define VMCPU_ASSERT_EMT(pVCpu) AssertMsg(VMCPU_IS_EMT(pVCpu), \
1012 ("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd idCpu=%#x\n", \
1013 RTThreadNativeSelf(), (pVCpu)->hNativeThread, (pVCpu)->idCpu))
1014#endif
1015
1016/** @def VM_ASSERT_EMT_RETURN
1017 * Asserts that the current thread IS the emulation thread (EMT) and returns if it isn't.
1018 */
1019#ifdef IN_RC
1020# define VM_ASSERT_EMT_RETURN(pVM, rc) AssertReturn(VM_IS_EMT(pVM), (rc))
1021#elif defined(IN_RING0)
1022# define VM_ASSERT_EMT_RETURN(pVM, rc) AssertReturn(VM_IS_EMT(pVM), (rc))
1023#else
1024# define VM_ASSERT_EMT_RETURN(pVM, rc) \
1025 AssertMsgReturn(VM_IS_EMT(pVM), \
1026 ("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd\n", RTThreadNativeSelf(), VMR3GetVMCPUNativeThread(pVM)), \
1027 (rc))
1028#endif
1029
1030/** @def VMCPU_ASSERT_EMT_RETURN
1031 * Asserts that the current thread IS the emulation thread (EMT) and returns if it isn't.
1032 */
1033#ifdef IN_RC
1034# define VMCPU_ASSERT_EMT_RETURN(pVCpu, rc) AssertReturn(VMCPU_IS_EMT(pVCpu), (rc))
1035#elif defined(IN_RING0)
1036# define VMCPU_ASSERT_EMT_RETURN(pVCpu, rc) AssertReturn(VMCPU_IS_EMT(pVCpu), (rc))
1037#else
1038# define VMCPU_ASSERT_EMT_RETURN(pVCpu, rc) \
1039 AssertMsgReturn(VMCPU_IS_EMT(pVCpu), \
1040 ("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd idCpu=%#x\n", \
1041 RTThreadNativeSelf(), (pVCpu)->hNativeThread, (pVCpu)->idCpu), \
1042 (rc))
1043#endif
1044
1045/** @def VMCPU_ASSERT_EMT_OR_GURU
1046 * Asserts that the current thread IS the emulation thread (EMT) of the
1047 * specified virtual CPU.
1048 */
1049#if defined(IN_RC) || defined(IN_RING0)
1050# define VMCPU_ASSERT_EMT_OR_GURU(pVCpu) Assert( VMCPU_IS_EMT(pVCpu) \
1051 || pVCpu->CTX_SUFF(pVM)->enmVMState == VMSTATE_GURU_MEDITATION \
1052 || pVCpu->CTX_SUFF(pVM)->enmVMState == VMSTATE_GURU_MEDITATION_LS )
1053#else
1054# define VMCPU_ASSERT_EMT_OR_GURU(pVCpu) \
1055 AssertMsg( VMCPU_IS_EMT(pVCpu) \
1056 || pVCpu->CTX_SUFF(pVM)->enmVMState == VMSTATE_GURU_MEDITATION \
1057 || pVCpu->CTX_SUFF(pVM)->enmVMState == VMSTATE_GURU_MEDITATION_LS, \
1058 ("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd idCpu=%#x\n", \
1059 RTThreadNativeSelf(), (pVCpu)->hNativeThread, (pVCpu)->idCpu))
1060#endif
1061
1062/** @def VMCPU_ASSERT_EMT_OR_NOT_RUNNING
1063 * Asserts that the current thread IS the emulation thread (EMT) of the
1064 * specified virtual CPU or the VM is not running.
1065 */
1066#if defined(IN_RC) || defined(IN_RING0)
1067# define VMCPU_ASSERT_EMT_OR_NOT_RUNNING(pVCpu) \
1068 Assert( VMCPU_IS_EMT(pVCpu) \
1069 || !VM_IS_RUNNING_FOR_ASSERTIONS_ONLY((pVCpu)->CTX_SUFF(pVM)) )
1070#else
1071# define VMCPU_ASSERT_EMT_OR_NOT_RUNNING(pVCpu) \
1072 AssertMsg( VMCPU_IS_EMT(pVCpu) \
1073 || !VM_IS_RUNNING_FOR_ASSERTIONS_ONLY((pVCpu)->CTX_SUFF(pVM)), \
1074 ("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd idCpu=%#x\n", \
1075 RTThreadNativeSelf(), (pVCpu)->hNativeThread, (pVCpu)->idCpu))
1076#endif
1077
1078/** @def VMSTATE_IS_RUNNING
1079 * Checks if the given state indicates a running VM.
1080 */
1081#define VMSTATE_IS_RUNNING(a_enmVMState) \
1082 ( (a_enmVMState) == VMSTATE_RUNNING \
1083 || (a_enmVMState) == VMSTATE_RUNNING_LS )
1084
1085/** @def VM_IS_RUNNING_FOR_ASSERTIONS_ONLY
1086 * Checks if the VM is running.
1087 * @note This is only for pure debug assertions. No AssertReturn or similar!
1088 * @sa VMSTATE_IS_RUNNING
1089 */
1090#define VM_IS_RUNNING_FOR_ASSERTIONS_ONLY(pVM) \
1091 ( (pVM)->enmVMState == VMSTATE_RUNNING \
1092 || (pVM)->enmVMState == VMSTATE_RUNNING_LS )
1093
1094
1095/** @def VMSTATE_IS_POWERED_ON
1096 * Checks if the given state indicates the VM is powered on.
1097 *
1098 * @note Excludes all error states, so a powered on VM that hit a fatal error,
1099 * guru meditation, state load failure or similar will not be considered
1100 * powered on by this test.
1101 */
1102#define VMSTATE_IS_POWERED_ON(a_enmVMState) \
1103 ( (a_enmVMState) >= VMSTATE_RESUMING && (a_enmVMState) < VMSTATE_POWERING_OFF )
1104
1105/** @def VM_ASSERT_IS_NOT_RUNNING
1106 * Asserts that the VM is not running.
1107 */
1108#if defined(IN_RC) || defined(IN_RING0)
1109#define VM_ASSERT_IS_NOT_RUNNING(pVM) Assert(!VM_IS_RUNNING_FOR_ASSERTIONS_ONLY(pVM))
1110#else
1111#define VM_ASSERT_IS_NOT_RUNNING(pVM) AssertMsg(!VM_IS_RUNNING_FOR_ASSERTIONS_ONLY(pVM), \
1112 ("VM is running. enmVMState=%d\n", (pVM)->enmVMState))
1113#endif
1114
1115/** @def VM_ASSERT_EMT0
1116 * Asserts that the current thread IS emulation thread \#0 (EMT0).
1117 */
1118#ifdef IN_RING3
1119# define VM_ASSERT_EMT0(a_pVM) VMCPU_ASSERT_EMT((a_pVM)->apCpusR3[0])
1120#else
1121# define VM_ASSERT_EMT0(a_pVM) VMCPU_ASSERT_EMT(&(a_pVM)->aCpus[0])
1122#endif
1123
1124/** @def VM_ASSERT_EMT0_RETURN
1125 * Asserts that the current thread IS emulation thread \#0 (EMT0) and returns if
1126 * it isn't.
1127 */
1128#ifdef IN_RING3
1129# define VM_ASSERT_EMT0_RETURN(pVM, rc) VMCPU_ASSERT_EMT_RETURN((pVM)->apCpusR3[0], (rc))
1130#else
1131# define VM_ASSERT_EMT0_RETURN(pVM, rc) VMCPU_ASSERT_EMT_RETURN(&(pVM)->aCpus[0], (rc))
1132#endif
1133
1134
1135/**
1136 * Asserts that the current thread is NOT the emulation thread.
1137 */
1138#define VM_ASSERT_OTHER_THREAD(pVM) \
1139 AssertMsg(!VM_IS_EMT(pVM), ("Not other thread!!\n"))
1140
1141
1142/** @def VM_ASSERT_STATE
1143 * Asserts a certain VM state.
1144 */
1145#define VM_ASSERT_STATE(pVM, _enmState) \
1146 AssertMsg((pVM)->enmVMState == (_enmState), \
1147 ("state %s, expected %s\n", VMGetStateName((pVM)->enmVMState), VMGetStateName(_enmState)))
1148
1149/** @def VM_ASSERT_STATE_RETURN
1150 * Asserts a certain VM state and returns if it doesn't match.
1151 */
1152#define VM_ASSERT_STATE_RETURN(pVM, _enmState, rc) \
1153 AssertMsgReturn((pVM)->enmVMState == (_enmState), \
1154 ("state %s, expected %s\n", VMGetStateName((pVM)->enmVMState), VMGetStateName(_enmState)), \
1155 (rc))
1156
1157/** @def VM_IS_VALID_EXT
1158 * Asserts a the VM handle is valid for external access, i.e. not being destroy
1159 * or terminated. */
1160#define VM_IS_VALID_EXT(pVM) \
1161 ( RT_VALID_ALIGNED_PTR(pVM, PAGE_SIZE) \
1162 && ( (unsigned)(pVM)->enmVMState < (unsigned)VMSTATE_DESTROYING \
1163 || ( (unsigned)(pVM)->enmVMState == (unsigned)VMSTATE_DESTROYING \
1164 && VM_IS_EMT(pVM))) )
1165
1166/** @def VM_ASSERT_VALID_EXT_RETURN
1167 * Asserts a the VM handle is valid for external access, i.e. not being
1168 * destroy or terminated.
1169 */
1170#define VM_ASSERT_VALID_EXT_RETURN(pVM, rc) \
1171 AssertMsgReturn(VM_IS_VALID_EXT(pVM), \
1172 ("pVM=%p state %s\n", (pVM), RT_VALID_ALIGNED_PTR(pVM, PAGE_SIZE) \
1173 ? VMGetStateName(pVM->enmVMState) : ""), \
1174 (rc))
1175
1176/** @def VMCPU_ASSERT_VALID_EXT_RETURN
1177 * Asserts a the VMCPU handle is valid for external access, i.e. not being
1178 * destroy or terminated.
1179 */
1180#define VMCPU_ASSERT_VALID_EXT_RETURN(pVCpu, rc) \
1181 AssertMsgReturn( RT_VALID_ALIGNED_PTR(pVCpu, 64) \
1182 && RT_VALID_ALIGNED_PTR((pVCpu)->CTX_SUFF(pVM), PAGE_SIZE) \
1183 && (unsigned)(pVCpu)->CTX_SUFF(pVM)->enmVMState < (unsigned)VMSTATE_DESTROYING, \
1184 ("pVCpu=%p pVM=%p state %s\n", (pVCpu), RT_VALID_ALIGNED_PTR(pVCpu, 64) ? (pVCpu)->CTX_SUFF(pVM) : NULL, \
1185 RT_VALID_ALIGNED_PTR(pVCpu, 64) && RT_VALID_ALIGNED_PTR((pVCpu)->CTX_SUFF(pVM), PAGE_SIZE) \
1186 ? VMGetStateName((pVCpu)->pVMR3->enmVMState) : ""), \
1187 (rc))
1188
1189#endif /* !VBOX_FOR_DTRACE_LIB */
1190
1191
1192/**
1193 * Helper that HM and NEM uses for safely modifying VM::bMainExecutionEngine.
1194 *
1195 * ONLY HM and NEM MAY USE THIS!
1196 *
1197 * @param a_pVM The cross context VM structure.
1198 * @param a_bValue The new value.
1199 * @internal
1200 */
1201#define VM_SET_MAIN_EXECUTION_ENGINE(a_pVM, a_bValue) \
1202 do { \
1203 *const_cast<uint8_t *>(&(a_pVM)->bMainExecutionEngine) = (a_bValue); \
1204 ASMCompilerBarrier(); /* just to be on the safe side */ \
1205 } while (0)
1206
1207/**
1208 * Checks whether iem-executes-all-mode is used.
1209 *
1210 * @retval true if IEM is used.
1211 * @retval false if not.
1212 *
1213 * @param a_pVM The cross context VM structure.
1214 * @sa VM_IS_HM_OR_NEM_ENABLED, VM_IS_HM_ENABLED, VM_IS_NEM_ENABLED.
1215 * @internal
1216 */
1217#define VM_IS_EXEC_ENGINE_IEM(a_pVM) ((a_pVM)->bMainExecutionEngine == VM_EXEC_ENGINE_IEM)
1218
1219/**
1220 * Checks whether HM (VT-x/AMD-V) or NEM is being used by this VM.
1221 *
1222 * @retval true if either is used.
1223 * @retval false if software virtualization (raw-mode) is used.
1224 *
1225 * @param a_pVM The cross context VM structure.
1226 * @sa VM_IS_EXEC_ENGINE_IEM, VM_IS_HM_ENABLED, VM_IS_NEM_ENABLED.
1227 * @internal
1228 */
1229#define VM_IS_HM_OR_NEM_ENABLED(a_pVM) ((a_pVM)->bMainExecutionEngine != VM_EXEC_ENGINE_IEM)
1230
1231/**
1232 * Checks whether HM is being used by this VM.
1233 *
1234 * @retval true if HM (VT-x/AMD-v) is used.
1235 * @retval false if not.
1236 *
1237 * @param a_pVM The cross context VM structure.
1238 * @sa VM_IS_NEM_ENABLED, VM_IS_EXEC_ENGINE_IEM, VM_IS_HM_OR_NEM_ENABLED.
1239 * @internal
1240 */
1241#define VM_IS_HM_ENABLED(a_pVM) ((a_pVM)->bMainExecutionEngine == VM_EXEC_ENGINE_HW_VIRT)
1242
1243/**
1244 * Checks whether NEM is being used by this VM.
1245 *
1246 * @retval true if a native hypervisor API is used.
1247 * @retval false if not.
1248 *
1249 * @param a_pVM The cross context VM structure.
1250 * @sa VM_IS_HM_ENABLED, VM_IS_EXEC_ENGINE_IEM, VM_IS_HM_OR_NEM_ENABLED.
1251 * @internal
1252 */
1253#define VM_IS_NEM_ENABLED(a_pVM) ((a_pVM)->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API)
1254
1255
1256/**
1257 * The cross context VM structure.
1258 *
1259 * It contains all the VM data which have to be available in all contexts.
1260 * Even if it contains all the data the idea is to use APIs not to modify all
1261 * the members all around the place. Therefore we make use of unions to hide
1262 * everything which isn't local to the current source module. This means we'll
1263 * have to pay a little bit of attention when adding new members to structures
1264 * in the unions and make sure to keep the padding sizes up to date.
1265 *
1266 * Run 'kmk run-struct-tests' (from src/VBox/VMM if you like) after updating!
1267 */
1268typedef struct VM
1269{
1270 /** The state of the VM.
1271 * This field is read only to everyone except the VM and EM. */
1272 VMSTATE volatile enmVMState;
1273 /** Forced action flags.
1274 * See the VM_FF_* \#defines. Updated atomically.
1275 */
1276 volatile uint32_t fGlobalForcedActions;
1277 /** Pointer to the array of page descriptors for the VM structure allocation. */
1278 R3PTRTYPE(PSUPPAGE) paVMPagesR3;
1279 /** Session handle. For use when calling SUPR0 APIs. */
1280#ifdef IN_RING0
1281 PSUPDRVSESSION pSessionUnsafe;
1282#else
1283 PSUPDRVSESSION pSession;
1284#endif
1285 /** Pointer to the ring-3 VM structure. */
1286 PUVM pUVM;
1287 /** Ring-3 Host Context VM Pointer. */
1288#ifdef IN_RING0
1289 R3PTRTYPE(struct VM *) pVMR3Unsafe;
1290#else
1291 R3PTRTYPE(struct VM *) pVMR3;
1292#endif
1293 /** Ring-0 Host Context VM pointer for making ring-0 calls. */
1294 R0PTRTYPE(struct VM *) pVMR0ForCall;
1295 /** Raw-mode Context VM Pointer. */
1296 uint32_t pVMRC;
1297 /** Padding for new raw-mode (long mode). */
1298 uint32_t pVMRCPadding;
1299
1300 /** The GVM VM handle. Only the GVM should modify this field. */
1301#ifdef IN_RING0
1302 uint32_t hSelfUnsafe;
1303#else
1304 uint32_t hSelf;
1305#endif
1306 /** Number of virtual CPUs. */
1307#ifdef IN_RING0
1308 uint32_t cCpusUnsafe;
1309#else
1310 uint32_t cCpus;
1311#endif
1312 /** CPU excution cap (1-100) */
1313 uint32_t uCpuExecutionCap;
1314
1315 /** Size of the VM structure. */
1316 uint32_t cbSelf;
1317 /** Size of the VMCPU structure. */
1318 uint32_t cbVCpu;
1319 /** Structure version number (TBD). */
1320 uint32_t uStructVersion;
1321
1322 /** @name Various items that are frequently accessed.
1323 * @{ */
1324 /** The main execution engine, VM_EXEC_ENGINE_XXX.
1325 * This is set early during vmR3InitRing3 by HM or NEM. */
1326 uint8_t const bMainExecutionEngine;
1327
1328 /** Hardware VM support is available and enabled.
1329 * Determined very early during init.
1330 * This is placed here for performance reasons.
1331 * @todo obsoleted by bMainExecutionEngine, eliminate. */
1332 bool fHMEnabled;
1333 /** @} */
1334
1335 /** Alignment padding. */
1336 uint8_t uPadding1[6];
1337
1338 /** @name Debugging
1339 * @{ */
1340 /** Ring-3 Host Context VM Pointer. */
1341 R3PTRTYPE(RTTRACEBUF) hTraceBufR3;
1342 /** Ring-0 Host Context VM Pointer. */
1343 R0PTRTYPE(RTTRACEBUF) hTraceBufR0;
1344 /** @} */
1345
1346 /** Max EMT hash lookup collisions (in GVMM). */
1347 uint8_t cMaxEmtHashCollisions;
1348
1349 /** Padding - the unions must be aligned on a 64 bytes boundary. */
1350 uint8_t abAlignment3[HC_ARCH_BITS == 64 ? 23 : 51];
1351
1352 /** CPUM part. */
1353 union
1354 {
1355#if defined(VMM_INCLUDED_SRC_include_CPUMInternal_h) || defined(VMM_INCLUDED_SRC_include_CPUMInternal_armv8_h)
1356 struct CPUM s;
1357#endif
1358#ifdef VBOX_INCLUDED_vmm_cpum_h
1359 /** Read only info exposed about the host and guest CPUs. */
1360 struct
1361 {
1362 /** Padding for hidden fields. */
1363 uint8_t abHidden0[64 + 48];
1364 /** Guest CPU feature information. */
1365 CPUMFEATURES GuestFeatures;
1366 } const ro;
1367#endif
1368 /** @todo this is rather bloated because of static MSR range allocation.
1369 * Probably a good idea to move it to a separate R0 allocation... */
1370 uint8_t padding[8832 + 128*8192 + 0x1d00]; /* multiple of 64 */
1371 } cpum;
1372
1373 /** PGM part.
1374 * @note Aligned on 16384 boundrary for zero and mmio page storage. */
1375 union
1376 {
1377#ifdef VMM_INCLUDED_SRC_include_PGMInternal_h
1378 struct PGM s;
1379#endif
1380 uint8_t padding[129728]; /* multiple of 64 */
1381 } pgm;
1382
1383 /** VMM part. */
1384 union
1385 {
1386#ifdef VMM_INCLUDED_SRC_include_VMMInternal_h
1387 struct VMM s;
1388#endif
1389 uint8_t padding[1600]; /* multiple of 64 */
1390 } vmm;
1391
1392 /** HM part. */
1393 union
1394 {
1395#ifdef VMM_INCLUDED_SRC_include_HMInternal_h
1396 struct HM s;
1397#endif
1398 uint8_t padding[5504]; /* multiple of 64 */
1399 } hm;
1400
1401 /** TRPM part. */
1402 union
1403 {
1404#ifdef VMM_INCLUDED_SRC_include_TRPMInternal_h
1405 struct TRPM s;
1406#endif
1407 uint8_t padding[2048]; /* multiple of 64 */
1408 } trpm;
1409
1410 /** SELM part. */
1411 union
1412 {
1413#ifdef VMM_INCLUDED_SRC_include_SELMInternal_h
1414 struct SELM s;
1415#endif
1416 uint8_t padding[768]; /* multiple of 64 */
1417 } selm;
1418
1419 /** MM part. */
1420 union
1421 {
1422#ifdef VMM_INCLUDED_SRC_include_MMInternal_h
1423 struct MM s;
1424#endif
1425 uint8_t padding[192]; /* multiple of 64 */
1426 } mm;
1427
1428 /** PDM part. */
1429 union
1430 {
1431#ifdef VMM_INCLUDED_SRC_include_PDMInternal_h
1432 struct PDM s;
1433#endif
1434 uint8_t padding[22784]; /* multiple of 64 */
1435 } pdm;
1436
1437 /** IOM part. */
1438 union
1439 {
1440#ifdef VMM_INCLUDED_SRC_include_IOMInternal_h
1441 struct IOM s;
1442#endif
1443 uint8_t padding[1152]; /* multiple of 64 */
1444 } iom;
1445
1446 /** EM part. */
1447 union
1448 {
1449#ifdef VMM_INCLUDED_SRC_include_EMInternal_h
1450 struct EM s;
1451#endif
1452 uint8_t padding[256]; /* multiple of 64 */
1453 } em;
1454
1455 /** NEM part. */
1456 union
1457 {
1458#ifdef VMM_INCLUDED_SRC_include_NEMInternal_h
1459 struct NEM s;
1460#endif
1461 uint8_t padding[4608]; /* multiple of 64 */
1462 } nem;
1463
1464 /** TM part. */
1465 union
1466 {
1467#ifdef VMM_INCLUDED_SRC_include_TMInternal_h
1468 struct TM s;
1469#endif
1470 uint8_t padding[10112]; /* multiple of 64 */
1471 } tm;
1472
1473 /** DBGF part. */
1474 union
1475 {
1476#ifdef VMM_INCLUDED_SRC_include_DBGFInternal_h
1477 struct DBGF s;
1478#endif
1479#ifdef VBOX_INCLUDED_vmm_dbgf_h
1480 /** Read only info exposed about interrupt breakpoints and selected events. */
1481 struct
1482 {
1483 /** Bitmap of enabled hardware interrupt breakpoints. */
1484 uint32_t bmHardIntBreakpoints[256 / 32];
1485 /** Bitmap of enabled software interrupt breakpoints. */
1486 uint32_t bmSoftIntBreakpoints[256 / 32];
1487 /** Bitmap of selected events.
1488 * This includes non-selectable events too for simplicity, we maintain the
1489 * state for some of these, as it may come in handy. */
1490 uint64_t bmSelectedEvents[(DBGFEVENT_END + 63) / 64];
1491 /** Enabled hardware interrupt breakpoints. */
1492 uint32_t cHardIntBreakpoints;
1493 /** Enabled software interrupt breakpoints. */
1494 uint32_t cSoftIntBreakpoints;
1495 /** The number of selected events. */
1496 uint32_t cSelectedEvents;
1497 /** The number of enabled hardware breakpoints. */
1498 uint8_t cEnabledHwBreakpoints;
1499 /** The number of enabled hardware I/O breakpoints. */
1500 uint8_t cEnabledHwIoBreakpoints;
1501 uint8_t au8Alignment1[2]; /**< Alignment padding. */
1502 /** The number of enabled software breakpoints. */
1503 uint32_t volatile cEnabledSwBreakpoints;
1504 } const ro;
1505#endif
1506 uint8_t padding[2432]; /* multiple of 64 */
1507 } dbgf;
1508
1509 /** SSM part. */
1510 union
1511 {
1512#ifdef VMM_INCLUDED_SRC_include_SSMInternal_h
1513 struct SSM s;
1514#endif
1515 uint8_t padding[128]; /* multiple of 64 */
1516 } ssm;
1517
1518 union
1519 {
1520#ifdef VMM_INCLUDED_SRC_include_GIMInternal_h
1521 struct GIM s;
1522#endif
1523 uint8_t padding[448]; /* multiple of 64 */
1524 } gim;
1525
1526 /** Interrupt controller, target specific. */
1527 RT_GCC_EXTENSION
1528 union
1529 {
1530#if defined(VBOX_VMM_TARGET_ARMV8) || defined(VBOX_VMM_TARGET_AGNOSTIC)
1531 union
1532 {
1533# ifdef VMM_INCLUDED_SRC_include_GICInternal_h
1534 struct GIC s;
1535# endif
1536 uint8_t padding[128]; /* multiple of 8 */
1537 } gic;
1538#endif
1539#if defined(VBOX_VMM_TARGET_X86) || defined(VBOX_VMM_TARGET_AGNOSTIC)
1540 union
1541 {
1542# ifdef VMM_INCLUDED_SRC_include_APICInternal_h
1543 struct APIC s;
1544# endif
1545 uint8_t padding[128]; /* multiple of 8 */
1546 } apic;
1547#endif
1548 };
1549
1550 /* ---- begin small stuff ---- */
1551
1552 /** VM part. */
1553 union
1554 {
1555#ifdef VMM_INCLUDED_SRC_include_VMInternal_h
1556 struct VMINT s;
1557#endif
1558 uint8_t padding[32]; /* multiple of 8 */
1559 } vm;
1560
1561 /** CFGM part. */
1562 union
1563 {
1564#ifdef VMM_INCLUDED_SRC_include_CFGMInternal_h
1565 struct CFGM s;
1566#endif
1567 uint8_t padding[8]; /* multiple of 8 */
1568 } cfgm;
1569
1570 /** IEM part. */
1571 union
1572 {
1573#ifdef VMM_INCLUDED_SRC_include_IEMInternal_h
1574 struct IEM s;
1575#endif
1576 uint8_t padding[16]; /* multiple of 8 */
1577 } iem;
1578
1579 /** Statistics for ring-0 only components. */
1580 struct
1581 {
1582 /** GMMR0 stats. */
1583 struct
1584 {
1585 /** Chunk TLB hits. */
1586 uint64_t cChunkTlbHits;
1587 /** Chunk TLB misses. */
1588 uint64_t cChunkTlbMisses;
1589 } gmm;
1590 uint64_t au64Padding[6]; /* probably more comming here... */
1591 } R0Stats;
1592
1593 union
1594 {
1595#ifdef VMM_INCLUDED_SRC_include_GCMInternal_h
1596 struct GCM s;
1597#endif
1598 uint8_t padding[8]; /* multiple of 8 */
1599 } gcm;
1600
1601 /** Padding for aligning the structure size on a page boundrary. */
1602 uint8_t abAlignment2[0x3900 - sizeof(PVMCPUR3) * VMM_MAX_CPU_COUNT];
1603
1604 /* ---- end small stuff ---- */
1605
1606 /** Array of VMCPU ring-3 pointers. */
1607 PVMCPUR3 apCpusR3[VMM_MAX_CPU_COUNT];
1608
1609 /* This point is aligned on a 16384 boundrary (for arm64 purposes). */
1610} VM;
1611#ifndef VBOX_FOR_DTRACE_LIB
1612//AssertCompileSizeAlignment(VM, 16384);
1613#endif
1614
1615
1616#ifdef IN_RC
1617RT_C_DECLS_BEGIN
1618
1619/** The VM structure.
1620 * This is imported from the VMMRCBuiltin module, i.e. it's a one of those magic
1621 * globals which we should avoid using.
1622 */
1623extern DECLIMPORT(VM) g_VM;
1624
1625/** The VMCPU structure for virtual CPU \#0.
1626 * This is imported from the VMMRCBuiltin module, i.e. it's a one of those magic
1627 * globals which we should avoid using.
1628 */
1629extern DECLIMPORT(VMCPU) g_VCpu0;
1630
1631RT_C_DECLS_END
1632#endif
1633
1634/** @} */
1635
1636#endif /* !VBOX_INCLUDED_vmm_vm_h */
1637
Note: See TracBrowser for help on using the repository browser.

© 2024 Oracle Support Privacy / Do Not Sell My Info Terms of Use Trademark Policy Automated Access Etiquette