VirtualBox

source: vbox/trunk/include/VBox/vmm/vm.h@ 72903

Last change on this file since 72903 was 72569, checked in by vboxsync, 7 years ago

EM,IEM,NEM: Started working on optimizing adjacent exits using IEM. Keep track of frequent exits, after 256 hits do a trial run in IEM to look for adjacent exits. Proof of concept using CPUID in NEMR3/win. bugref:9044

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1/** @file
2 * VM - The Virtual Machine, data.
3 */
4
5/*
6 * Copyright (C) 2006-2017 Oracle Corporation
7 *
8 * This file is part of VirtualBox Open Source Edition (OSE), as
9 * available from http://www.virtualbox.org. This file is free software;
10 * you can redistribute it and/or modify it under the terms of the GNU
11 * General Public License (GPL) as published by the Free Software
12 * Foundation, in version 2 as it comes in the "COPYING" file of the
13 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15 *
16 * The contents of this file may alternatively be used under the terms
17 * of the Common Development and Distribution License Version 1.0
18 * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19 * VirtualBox OSE distribution, in which case the provisions of the
20 * CDDL are applicable instead of those of the GPL.
21 *
22 * You may elect to license modified versions of this file under the
23 * terms and conditions of either the GPL or the CDDL or both.
24 */
25
26#ifndef ___VBox_vmm_vm_h
27#define ___VBox_vmm_vm_h
28
29#ifndef VBOX_FOR_DTRACE_LIB
30# include <iprt/param.h>
31# include <VBox/types.h>
32# include <VBox/vmm/cpum.h>
33# include <VBox/vmm/stam.h>
34# include <VBox/vmm/vmapi.h>
35# include <VBox/vmm/vmm.h>
36# include <VBox/sup.h>
37#else
38# pragma D depends_on library vbox-types.d
39# pragma D depends_on library CPUMInternal.d
40# define ___CPUMInternal_h
41#endif
42
43
44
45/** @defgroup grp_vm The Virtual Machine
46 * @ingroup grp_vmm
47 * @{
48 */
49
50/**
51 * The state of a Virtual CPU.
52 *
53 * The basic state indicated here is whether the CPU has been started or not. In
54 * addition, there are sub-states when started for assisting scheduling (GVMM
55 * mostly).
56 *
57 * The transition out of the STOPPED state is done by a vmR3PowerOn.
58 * The transition back to the STOPPED state is done by vmR3PowerOff.
59 *
60 * (Alternatively we could let vmR3PowerOn start CPU 0 only and let the SPIP
61 * handling switch on the other CPUs. Then vmR3Reset would stop all but CPU 0.)
62 */
63typedef enum VMCPUSTATE
64{
65 /** The customary invalid zero. */
66 VMCPUSTATE_INVALID = 0,
67
68 /** Virtual CPU has not yet been started. */
69 VMCPUSTATE_STOPPED,
70
71 /** CPU started. */
72 VMCPUSTATE_STARTED,
73 /** CPU started in HM context. */
74 VMCPUSTATE_STARTED_HM,
75 /** Executing guest code and can be poked (RC or STI bits of HM). */
76 VMCPUSTATE_STARTED_EXEC,
77 /** Executing guest code in the recompiler. */
78 VMCPUSTATE_STARTED_EXEC_REM,
79 /** Executing guest code using NEM. */
80 VMCPUSTATE_STARTED_EXEC_NEM,
81 VMCPUSTATE_STARTED_EXEC_NEM_WAIT,
82 VMCPUSTATE_STARTED_EXEC_NEM_CANCELED,
83 /** Halted. */
84 VMCPUSTATE_STARTED_HALTED,
85
86 /** The end of valid virtual CPU states. */
87 VMCPUSTATE_END,
88
89 /** Ensure 32-bit type. */
90 VMCPUSTATE_32BIT_HACK = 0x7fffffff
91} VMCPUSTATE;
92
93
94/**
95 * The cross context virtual CPU structure.
96 *
97 * Run 'kmk run-struct-tests' (from src/VBox/VMM if you like) after updating!
98 */
99typedef struct VMCPU
100{
101 /** Per CPU forced action.
102 * See the VMCPU_FF_* \#defines. Updated atomically. */
103 uint32_t volatile fLocalForcedActions; /* 0 */
104 /** The CPU state. */
105 VMCPUSTATE volatile enmState; /* 4 */
106
107 /** Pointer to the ring-3 UVMCPU structure. */
108 PUVMCPU pUVCpu; /* 8 */
109 /** Ring-3 Host Context VM Pointer. */
110 PVMR3 pVMR3; /* 16 / 12 */
111 /** Ring-0 Host Context VM Pointer. */
112 PVMR0 pVMR0; /* 24 / 16 */
113 /** Raw-mode Context VM Pointer. */
114 PVMRC pVMRC; /* 32 / 20 */
115 /** The CPU ID.
116 * This is the index into the VM::aCpu array. */
117 VMCPUID idCpu; /* 36 / 24 */
118 /** The native thread handle. */
119 RTNATIVETHREAD hNativeThread; /* 40 / 28 */
120 /** The native R0 thread handle. (different from the R3 handle!) */
121 RTNATIVETHREAD hNativeThreadR0; /* 48 / 32 */
122 /** Which host CPU ID is this EMT running on.
123 * Only valid when in RC or HMR0 with scheduling disabled. */
124 RTCPUID volatile idHostCpu; /* 56 / 36 */
125 /** The CPU set index corresponding to idHostCpu, UINT32_MAX if not valid.
126 * @remarks Best to make sure iHostCpuSet shares cache line with idHostCpu! */
127 uint32_t volatile iHostCpuSet; /* 60 / 40 */
128
129#if HC_ARCH_BITS == 32
130 /** Align the structures below bit on a 64-byte boundary and make sure it starts
131 * at the same offset in both 64-bit and 32-bit builds.
132 *
133 * @remarks The alignments of the members that are larger than 48 bytes should be
134 * 64-byte for cache line reasons. structs containing small amounts of
135 * data could be lumped together at the end with a < 64 byte padding
136 * following it (to grow into and align the struct size).
137 */
138 uint8_t abAlignment1[HC_ARCH_BITS == 64 ? 0 : 20];
139#endif
140
141 /** IEM part.
142 * @remarks This comes first as it allows the use of 8-bit immediates for the
143 * first 64 bytes of the structure, reducing code size a wee bit. */
144#ifdef ___IEMInternal_h /* For PDB hacking. */
145 union VMCPUUNIONIEMFULL
146#else
147 union VMCPUUNIONIEMSTUB
148#endif
149 {
150#ifdef ___IEMInternal_h
151 struct IEMCPU s;
152#endif
153 uint8_t padding[18496]; /* multiple of 64 */
154 } iem;
155
156 /** HM part. */
157 union VMCPUUNIONHM
158 {
159#ifdef ___HMInternal_h
160 struct HMCPU s;
161#endif
162 uint8_t padding[5888]; /* multiple of 64 */
163 } hm;
164
165 /** NEM part. */
166 union VMCPUUNIONNEM
167 {
168#ifdef ___NEMInternal_h
169 struct NEMCPU s;
170#endif
171 uint8_t padding[512]; /* multiple of 64 */
172 } nem;
173
174 /** TRPM part. */
175 union VMCPUUNIONTRPM
176 {
177#ifdef ___TRPMInternal_h
178 struct TRPMCPU s;
179#endif
180 uint8_t padding[128]; /* multiple of 64 */
181 } trpm;
182
183 /** TM part. */
184 union VMCPUUNIONTM
185 {
186#ifdef ___TMInternal_h
187 struct TMCPU s;
188#endif
189 uint8_t padding[384]; /* multiple of 64 */
190 } tm;
191
192 /** VMM part. */
193 union VMCPUUNIONVMM
194 {
195#ifdef ___VMMInternal_h
196 struct VMMCPU s;
197#endif
198 uint8_t padding[704]; /* multiple of 64 */
199 } vmm;
200
201 /** PDM part. */
202 union VMCPUUNIONPDM
203 {
204#ifdef ___PDMInternal_h
205 struct PDMCPU s;
206#endif
207 uint8_t padding[256]; /* multiple of 64 */
208 } pdm;
209
210 /** IOM part. */
211 union VMCPUUNIONIOM
212 {
213#ifdef ___IOMInternal_h
214 struct IOMCPU s;
215#endif
216 uint8_t padding[512]; /* multiple of 64 */
217 } iom;
218
219 /** DBGF part.
220 * @todo Combine this with other tiny structures. */
221 union VMCPUUNIONDBGF
222 {
223#ifdef ___DBGFInternal_h
224 struct DBGFCPU s;
225#endif
226 uint8_t padding[256]; /* multiple of 64 */
227 } dbgf;
228
229 /** GIM part. */
230 union VMCPUUNIONGIM
231 {
232#ifdef ___GIMInternal_h
233 struct GIMCPU s;
234#endif
235 uint8_t padding[512]; /* multiple of 64 */
236 } gim;
237
238 /** APIC part. */
239 union VMCPUUNIONAPIC
240 {
241#ifdef ___APICInternal_h
242 struct APICCPU s;
243#endif
244 uint8_t padding[1792]; /* multiple of 64 */
245 } apic;
246
247 /*
248 * Some less frequently used global members that doesn't need to take up
249 * precious space at the head of the structure.
250 */
251
252 /** Trace groups enable flags. */
253 uint32_t fTraceGroups; /* 64 / 44 */
254 /** State data for use by ad hoc profiling. */
255 uint32_t uAdHoc;
256 /** Profiling samples for use by ad hoc profiling. */
257 STAMPROFILEADV aStatAdHoc[8]; /* size: 40*8 = 320 */
258
259 /** Align the following members on page boundary. */
260 uint8_t abAlignment2[2936];
261
262 /** PGM part. */
263 union VMCPUUNIONPGM
264 {
265#ifdef ___PGMInternal_h
266 struct PGMCPU s;
267#endif
268 uint8_t padding[4096]; /* multiple of 4096 */
269 } pgm;
270
271 /** CPUM part. */
272 union VMCPUUNIONCPUM
273 {
274#ifdef ___CPUMInternal_h
275 struct CPUMCPU s;
276#endif
277#ifdef VMCPU_INCL_CPUM_GST_CTX
278 /** The guest CPUM context for direct use by execution engines.
279 * This is not for general consumption, but for HM, REM, IEM, and maybe a few
280 * others. The rest will use the function based CPUM API. */
281 CPUMCTX GstCtx;
282#endif
283 uint8_t padding[4096]; /* multiple of 4096 */
284 } cpum;
285
286 /** EM part. */
287 union VMCPUUNIONEM
288 {
289#ifdef ___EMInternal_h
290 struct EMCPU s;
291#endif
292 uint8_t padding[40960]; /* multiple of 4096 */
293 } em;
294} VMCPU;
295
296
297#ifndef VBOX_FOR_DTRACE_LIB
298
299/** @name Operations on VMCPU::enmState
300 * @{ */
301/** Gets the VMCPU state. */
302#define VMCPU_GET_STATE(pVCpu) ( (pVCpu)->enmState )
303/** Sets the VMCPU state. */
304#define VMCPU_SET_STATE(pVCpu, enmNewState) \
305 ASMAtomicWriteU32((uint32_t volatile *)&(pVCpu)->enmState, (enmNewState))
306/** Cmpares and sets the VMCPU state. */
307#define VMCPU_CMPXCHG_STATE(pVCpu, enmNewState, enmOldState) \
308 ASMAtomicCmpXchgU32((uint32_t volatile *)&(pVCpu)->enmState, (enmNewState), (enmOldState))
309/** Checks the VMCPU state. */
310#ifdef VBOX_STRICT
311# define VMCPU_ASSERT_STATE(pVCpu, enmExpectedState) \
312 do { \
313 VMCPUSTATE enmState = VMCPU_GET_STATE(pVCpu); \
314 AssertMsg(enmState == (enmExpectedState), \
315 ("enmState=%d enmExpectedState=%d idCpu=%u\n", \
316 enmState, enmExpectedState, (pVCpu)->idCpu)); \
317 } while (0)
318#else
319# define VMCPU_ASSERT_STATE(pVCpu, enmExpectedState) do { } while (0)
320#endif
321/** Tests if the state means that the CPU is started. */
322#define VMCPUSTATE_IS_STARTED(enmState) ( (enmState) > VMCPUSTATE_STOPPED )
323/** Tests if the state means that the CPU is stopped. */
324#define VMCPUSTATE_IS_STOPPED(enmState) ( (enmState) == VMCPUSTATE_STOPPED )
325/** @} */
326
327
328/** The name of the raw-mode context VMM Core module. */
329#define VMMRC_MAIN_MODULE_NAME "VMMRC.rc"
330/** The name of the ring-0 context VMM Core module. */
331#define VMMR0_MAIN_MODULE_NAME "VMMR0.r0"
332
333/**
334 * Wrapper macro for avoiding too much \#ifdef VBOX_WITH_RAW_MODE.
335 */
336#ifdef VBOX_WITH_RAW_MODE
337# define VM_WHEN_RAW_MODE(a_WithExpr, a_WithoutExpr) a_WithExpr
338#else
339# define VM_WHEN_RAW_MODE(a_WithExpr, a_WithoutExpr) a_WithoutExpr
340#endif
341
342
343/** VM Forced Action Flags.
344 *
345 * Use the VM_FF_SET() and VM_FF_CLEAR() macros to change the force
346 * action mask of a VM.
347 *
348 * Available VM bits:
349 * 0, 1, 5, 6, 7, 13, 14, 15, 16, 17, 21, 22, 23, 24, 25, 26, 27, 28, 30
350 *
351 *
352 * Available VMCPU bits:
353 * 11, 14, 15, 31
354 *
355 * @todo If we run low on VMCPU, we may consider merging the SELM bits
356 *
357 * @{
358 */
359/** The virtual sync clock has been stopped, go to TM until it has been
360 * restarted... */
361#define VM_FF_TM_VIRTUAL_SYNC RT_BIT_32(2)
362/** PDM Queues are pending. */
363#define VM_FF_PDM_QUEUES RT_BIT_32(VM_FF_PDM_QUEUES_BIT)
364/** The bit number for VM_FF_PDM_QUEUES. */
365#define VM_FF_PDM_QUEUES_BIT 3
366/** PDM DMA transfers are pending. */
367#define VM_FF_PDM_DMA RT_BIT_32(VM_FF_PDM_DMA_BIT)
368/** The bit number for VM_FF_PDM_DMA. */
369#define VM_FF_PDM_DMA_BIT 4
370/** This action forces the VM to call DBGF so DBGF can service debugger
371 * requests in the emulation thread.
372 * This action flag stays asserted till DBGF clears it.*/
373#define VM_FF_DBGF RT_BIT_32(VM_FF_DBGF_BIT)
374/** The bit number for VM_FF_DBGF. */
375#define VM_FF_DBGF_BIT 8
376/** This action forces the VM to service pending requests from other
377 * thread or requests which must be executed in another context. */
378#define VM_FF_REQUEST RT_BIT_32(9)
379/** Check for VM state changes and take appropriate action. */
380#define VM_FF_CHECK_VM_STATE RT_BIT_32(VM_FF_CHECK_VM_STATE_BIT)
381/** The bit number for VM_FF_CHECK_VM_STATE. */
382#define VM_FF_CHECK_VM_STATE_BIT 10
383/** Reset the VM. (postponed) */
384#define VM_FF_RESET RT_BIT_32(VM_FF_RESET_BIT)
385/** The bit number for VM_FF_RESET. */
386#define VM_FF_RESET_BIT 11
387/** EMT rendezvous in VMM. */
388#define VM_FF_EMT_RENDEZVOUS RT_BIT_32(VM_FF_EMT_RENDEZVOUS_BIT)
389/** The bit number for VM_FF_EMT_RENDEZVOUS. */
390#define VM_FF_EMT_RENDEZVOUS_BIT 12
391
392/** PGM needs to allocate handy pages. */
393#define VM_FF_PGM_NEED_HANDY_PAGES RT_BIT_32(18)
394/** PGM is out of memory.
395 * Abandon all loops and code paths which can be resumed and get up to the EM
396 * loops. */
397#define VM_FF_PGM_NO_MEMORY RT_BIT_32(19)
398 /** PGM is about to perform a lightweight pool flush
399 * Guest SMP: all EMT threads should return to ring 3
400 */
401#define VM_FF_PGM_POOL_FLUSH_PENDING RT_BIT_32(20)
402/** REM needs to be informed about handler changes. */
403#define VM_FF_REM_HANDLER_NOTIFY RT_BIT_32(VM_FF_REM_HANDLER_NOTIFY_BIT)
404/** The bit number for VM_FF_REM_HANDLER_NOTIFY. */
405#define VM_FF_REM_HANDLER_NOTIFY_BIT 29
406/** Suspend the VM - debug only. */
407#define VM_FF_DEBUG_SUSPEND RT_BIT_32(31)
408
409
410/** This action forces the VM to check any pending interrupts on the APIC. */
411#define VMCPU_FF_INTERRUPT_APIC RT_BIT_32(0)
412/** This action forces the VM to check any pending interrups on the PIC. */
413#define VMCPU_FF_INTERRUPT_PIC RT_BIT_32(1)
414/** This action forces the VM to schedule and run pending timer (TM).
415 * @remarks Don't move - PATM compatibility. */
416#define VMCPU_FF_TIMER RT_BIT_32(2)
417/** This action forces the VM to check any pending NMIs. */
418#define VMCPU_FF_INTERRUPT_NMI_BIT 3
419#define VMCPU_FF_INTERRUPT_NMI RT_BIT_32(VMCPU_FF_INTERRUPT_NMI_BIT)
420/** This action forces the VM to check any pending SMIs. */
421#define VMCPU_FF_INTERRUPT_SMI_BIT 4
422#define VMCPU_FF_INTERRUPT_SMI RT_BIT_32(VMCPU_FF_INTERRUPT_SMI_BIT)
423/** PDM critical section unlocking is pending, process promptly upon return to R3. */
424#define VMCPU_FF_PDM_CRITSECT RT_BIT_32(5)
425/** Special EM internal force flag that is used by EMUnhaltAndWakeUp() to force
426 * the virtual CPU out of the next (/current) halted state. It is not processed
427 * nor cleared by emR3ForcedActions (similar to VMCPU_FF_BLOCK_NMIS), instead it
428 * is cleared the next time EM leaves the HALTED state. */
429#define VMCPU_FF_UNHALT RT_BIT_32(6)
430/** Pending IEM action (bit number). */
431#define VMCPU_FF_IEM_BIT 7
432/** Pending IEM action (mask). */
433#define VMCPU_FF_IEM RT_BIT_32(VMCPU_FF_IEM_BIT)
434/** Pending APIC action (bit number). */
435#define VMCPU_FF_UPDATE_APIC_BIT 8
436/** This action forces the VM to update APIC's asynchronously arrived
437 * interrupts as pending interrupts. */
438#define VMCPU_FF_UPDATE_APIC RT_BIT_32(VMCPU_FF_UPDATE_APIC_BIT)
439/** This action forces the VM to service pending requests from other
440 * thread or requests which must be executed in another context. */
441#define VMCPU_FF_REQUEST RT_BIT_32(9)
442/** Pending DBGF event (alternative to passing VINF_EM_DBG_EVENT around). */
443#define VMCPU_FF_DBGF RT_BIT_32(VMCPU_FF_DBGF_BIT)
444/** The bit number for VMCPU_FF_DBGF. */
445#define VMCPU_FF_DBGF_BIT 10
446/** This action forces the VM to service any pending updates to CR3 (used only
447 * by HM). */
448#define VMCPU_FF_HM_UPDATE_CR3 RT_BIT_32(12)
449/** This action forces the VM to service any pending updates to PAE PDPEs (used
450 * only by HM). */
451#define VMCPU_FF_HM_UPDATE_PAE_PDPES RT_BIT_32(13)
452/** This action forces the VM to resync the page tables before going
453 * back to execute guest code. (GLOBAL FLUSH) */
454#define VMCPU_FF_PGM_SYNC_CR3 RT_BIT_32(16)
455/** Same as VM_FF_PGM_SYNC_CR3 except that global pages can be skipped.
456 * (NON-GLOBAL FLUSH) */
457#define VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL RT_BIT_32(17)
458/** Check for pending TLB shootdown actions (deprecated)
459 * Reserved for furture HM re-use if necessary / safe.
460 * Consumer: HM */
461#define VMCPU_FF_TLB_SHOOTDOWN_UNUSED RT_BIT_32(18)
462/** Check for pending TLB flush action.
463 * Consumer: HM
464 * @todo rename to VMCPU_FF_HM_TLB_FLUSH */
465#define VMCPU_FF_TLB_FLUSH RT_BIT_32(VMCPU_FF_TLB_FLUSH_BIT)
466/** The bit number for VMCPU_FF_TLB_FLUSH. */
467#define VMCPU_FF_TLB_FLUSH_BIT 19
468#ifdef VBOX_WITH_RAW_MODE
469/** Check the interrupt and trap gates */
470# define VMCPU_FF_TRPM_SYNC_IDT RT_BIT_32(20)
471/** Check Guest's TSS ring 0 stack */
472# define VMCPU_FF_SELM_SYNC_TSS RT_BIT_32(21)
473/** Check Guest's GDT table */
474# define VMCPU_FF_SELM_SYNC_GDT RT_BIT_32(22)
475/** Check Guest's LDT table */
476# define VMCPU_FF_SELM_SYNC_LDT RT_BIT_32(23)
477#endif /* VBOX_WITH_RAW_MODE */
478/** Inhibit interrupts pending. See EMGetInhibitInterruptsPC(). */
479#define VMCPU_FF_INHIBIT_INTERRUPTS RT_BIT_32(24)
480/** Block injection of non-maskable interrupts to the guest. */
481#define VMCPU_FF_BLOCK_NMIS RT_BIT_32(25)
482#ifdef VBOX_WITH_RAW_MODE
483/** CSAM needs to scan the page that's being executed */
484# define VMCPU_FF_CSAM_SCAN_PAGE RT_BIT_32(26)
485/** CSAM needs to do some homework. */
486# define VMCPU_FF_CSAM_PENDING_ACTION RT_BIT_32(27)
487#endif /* VBOX_WITH_RAW_MODE */
488/** Force return to Ring-3. */
489#define VMCPU_FF_TO_R3 RT_BIT_32(28)
490/** Force return to ring-3 to service pending I/O or MMIO write.
491 * This is a backup for mechanism VINF_IOM_R3_IOPORT_COMMIT_WRITE and
492 * VINF_IOM_R3_MMIO_COMMIT_WRITE, allowing VINF_EM_DBG_BREAKPOINT and similar
493 * status codes to be propagated at the same time without loss. */
494#define VMCPU_FF_IOM RT_BIT_32(29)
495#ifdef VBOX_WITH_RAW_MODE
496/** CPUM need to adjust CR0.TS/EM before executing raw-mode code again. */
497# define VMCPU_FF_CPUM RT_BIT_32(VMCPU_FF_CPUM_BIT)
498/** The bit number for VMCPU_FF_CPUM. */
499# define VMCPU_FF_CPUM_BIT 30
500#endif /* VBOX_WITH_RAW_MODE */
501/** Hardware virtualized nested-guest interrupt pending. */
502#define VMCPU_FF_INTERRUPT_NESTED_GUEST RT_BIT_32(31)
503
504/** Externally VM forced actions. Used to quit the idle/wait loop. */
505#define VM_FF_EXTERNAL_SUSPENDED_MASK ( VM_FF_CHECK_VM_STATE | VM_FF_DBGF | VM_FF_REQUEST | VM_FF_EMT_RENDEZVOUS )
506/** Externally VMCPU forced actions. Used to quit the idle/wait loop. */
507#define VMCPU_FF_EXTERNAL_SUSPENDED_MASK ( VMCPU_FF_REQUEST | VMCPU_FF_DBGF )
508
509/** Externally forced VM actions. Used to quit the idle/wait loop. */
510#define VM_FF_EXTERNAL_HALTED_MASK ( VM_FF_CHECK_VM_STATE | VM_FF_DBGF | VM_FF_REQUEST \
511 | VM_FF_PDM_QUEUES | VM_FF_PDM_DMA | VM_FF_EMT_RENDEZVOUS )
512/** Externally forced VMCPU actions. Used to quit the idle/wait loop. */
513#define VMCPU_FF_EXTERNAL_HALTED_MASK ( VMCPU_FF_UPDATE_APIC | VMCPU_FF_INTERRUPT_APIC | VMCPU_FF_INTERRUPT_PIC \
514 | VMCPU_FF_REQUEST | VMCPU_FF_INTERRUPT_NMI | VMCPU_FF_INTERRUPT_SMI \
515 | VMCPU_FF_UNHALT | VMCPU_FF_TIMER | VMCPU_FF_DBGF )
516
517/** High priority VM pre-execution actions. */
518#define VM_FF_HIGH_PRIORITY_PRE_MASK ( VM_FF_CHECK_VM_STATE | VM_FF_DBGF | VM_FF_TM_VIRTUAL_SYNC \
519 | VM_FF_DEBUG_SUSPEND | VM_FF_PGM_NEED_HANDY_PAGES | VM_FF_PGM_NO_MEMORY \
520 | VM_FF_EMT_RENDEZVOUS )
521/** High priority VMCPU pre-execution actions. */
522#define VMCPU_FF_HIGH_PRIORITY_PRE_MASK ( VMCPU_FF_TIMER | VMCPU_FF_INTERRUPT_APIC | VMCPU_FF_INTERRUPT_PIC \
523 | VMCPU_FF_UPDATE_APIC | VMCPU_FF_INHIBIT_INTERRUPTS | VMCPU_FF_DBGF \
524 | VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL \
525 | VM_WHEN_RAW_MODE( VMCPU_FF_SELM_SYNC_TSS | VMCPU_FF_TRPM_SYNC_IDT \
526 | VMCPU_FF_SELM_SYNC_GDT | VMCPU_FF_SELM_SYNC_LDT, 0 ) )
527
528/** High priority VM pre raw-mode execution mask. */
529#define VM_FF_HIGH_PRIORITY_PRE_RAW_MASK ( VM_FF_PGM_NEED_HANDY_PAGES | VM_FF_PGM_NO_MEMORY )
530/** High priority VMCPU pre raw-mode execution mask. */
531#define VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK ( VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL \
532 | VMCPU_FF_INHIBIT_INTERRUPTS \
533 | VM_WHEN_RAW_MODE( VMCPU_FF_SELM_SYNC_TSS | VMCPU_FF_TRPM_SYNC_IDT \
534 | VMCPU_FF_SELM_SYNC_GDT | VMCPU_FF_SELM_SYNC_LDT, 0) )
535
536/** High priority post-execution actions. */
537#define VM_FF_HIGH_PRIORITY_POST_MASK ( VM_FF_PGM_NO_MEMORY )
538/** High priority post-execution actions. */
539#define VMCPU_FF_HIGH_PRIORITY_POST_MASK ( VMCPU_FF_PDM_CRITSECT | VM_WHEN_RAW_MODE(VMCPU_FF_CSAM_PENDING_ACTION, 0) \
540 | VMCPU_FF_HM_UPDATE_CR3 | VMCPU_FF_HM_UPDATE_PAE_PDPES \
541 | VMCPU_FF_IEM | VMCPU_FF_IOM )
542
543/** Normal priority VM post-execution actions. */
544#define VM_FF_NORMAL_PRIORITY_POST_MASK ( VM_FF_CHECK_VM_STATE | VM_FF_DBGF | VM_FF_RESET \
545 | VM_FF_PGM_NO_MEMORY | VM_FF_EMT_RENDEZVOUS)
546/** Normal priority VMCPU post-execution actions. */
547#define VMCPU_FF_NORMAL_PRIORITY_POST_MASK ( VM_WHEN_RAW_MODE(VMCPU_FF_CSAM_SCAN_PAGE, 0) | VMCPU_FF_DBGF )
548
549/** Normal priority VM actions. */
550#define VM_FF_NORMAL_PRIORITY_MASK ( VM_FF_REQUEST | VM_FF_PDM_QUEUES | VM_FF_PDM_DMA \
551 | VM_FF_REM_HANDLER_NOTIFY | VM_FF_EMT_RENDEZVOUS)
552/** Normal priority VMCPU actions. */
553#define VMCPU_FF_NORMAL_PRIORITY_MASK ( VMCPU_FF_REQUEST )
554
555/** Flags to clear before resuming guest execution. */
556#define VMCPU_FF_RESUME_GUEST_MASK ( VMCPU_FF_TO_R3 )
557
558
559/** VM flags that cause the REP[|NE|E] STRINS loops to yield immediately. */
560#define VM_FF_HIGH_PRIORITY_POST_REPSTR_MASK ( VM_FF_TM_VIRTUAL_SYNC | VM_FF_PGM_NEED_HANDY_PAGES | VM_FF_PGM_NO_MEMORY \
561 | VM_FF_EMT_RENDEZVOUS | VM_FF_PGM_POOL_FLUSH_PENDING | VM_FF_RESET)
562/** VM flags that cause the REP[|NE|E] STRINS loops to yield. */
563#define VM_FF_YIELD_REPSTR_MASK ( VM_FF_HIGH_PRIORITY_POST_REPSTR_MASK \
564 | VM_FF_PDM_QUEUES | VM_FF_PDM_DMA | VM_FF_DBGF | VM_FF_DEBUG_SUSPEND )
565/** VMCPU flags that cause the REP[|NE|E] STRINS loops to yield immediately. */
566#ifdef IN_RING3
567# define VMCPU_FF_HIGH_PRIORITY_POST_REPSTR_MASK ( VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL | VMCPU_FF_DBGF )
568#else
569# define VMCPU_FF_HIGH_PRIORITY_POST_REPSTR_MASK ( VMCPU_FF_TO_R3 | VMCPU_FF_IEM | VMCPU_FF_IOM | VMCPU_FF_PGM_SYNC_CR3 \
570 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL | VMCPU_FF_DBGF )
571#endif
572/** VMCPU flags that cause the REP[|NE|E] STRINS loops to yield, interrupts
573 * enabled. */
574#define VMCPU_FF_YIELD_REPSTR_MASK ( VMCPU_FF_HIGH_PRIORITY_POST_REPSTR_MASK \
575 | VMCPU_FF_INTERRUPT_APIC | VMCPU_FF_UPDATE_APIC | VMCPU_FF_INTERRUPT_PIC \
576 | VMCPU_FF_INTERRUPT_NMI | VMCPU_FF_INTERRUPT_SMI | VMCPU_FF_PDM_CRITSECT \
577 | VMCPU_FF_TIMER | VMCPU_FF_REQUEST )
578/** VMCPU flags that cause the REP[|NE|E] STRINS loops to yield, interrupts
579 * disabled. */
580#define VMCPU_FF_YIELD_REPSTR_NOINT_MASK ( VMCPU_FF_YIELD_REPSTR_MASK \
581 & ~(VMCPU_FF_INTERRUPT_APIC | VMCPU_FF_UPDATE_APIC | VMCPU_FF_INTERRUPT_PIC) )
582
583/** VM Flags that cause the HM loops to go back to ring-3. */
584#define VM_FF_HM_TO_R3_MASK ( VM_FF_TM_VIRTUAL_SYNC | VM_FF_PGM_NEED_HANDY_PAGES | VM_FF_PGM_NO_MEMORY \
585 | VM_FF_PDM_QUEUES | VM_FF_EMT_RENDEZVOUS)
586/** VMCPU Flags that cause the HM loops to go back to ring-3. */
587#define VMCPU_FF_HM_TO_R3_MASK ( VMCPU_FF_TO_R3 | VMCPU_FF_TIMER | VMCPU_FF_PDM_CRITSECT \
588 | VMCPU_FF_IEM | VMCPU_FF_IOM)
589
590/** High priority ring-0 VM pre HM-mode execution mask. */
591#define VM_FF_HP_R0_PRE_HM_MASK (VM_FF_HM_TO_R3_MASK | VM_FF_REQUEST | VM_FF_PGM_POOL_FLUSH_PENDING | VM_FF_PDM_DMA)
592/** High priority ring-0 VMCPU pre HM-mode execution mask. */
593#define VMCPU_FF_HP_R0_PRE_HM_MASK ( VMCPU_FF_HM_TO_R3_MASK | VMCPU_FF_PGM_SYNC_CR3 \
594 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL | VMCPU_FF_REQUEST)
595/** High priority ring-0 VM pre HM-mode execution mask, single stepping. */
596#define VM_FF_HP_R0_PRE_HM_STEP_MASK (VM_FF_HP_R0_PRE_HM_MASK & ~( VM_FF_TM_VIRTUAL_SYNC | VM_FF_PDM_QUEUES \
597 | VM_FF_EMT_RENDEZVOUS | VM_FF_REQUEST \
598 | VM_FF_PDM_DMA) )
599/** High priority ring-0 VMCPU pre HM-mode execution mask, single stepping. */
600#define VMCPU_FF_HP_R0_PRE_HM_STEP_MASK (VMCPU_FF_HP_R0_PRE_HM_MASK & ~( VMCPU_FF_TO_R3 | VMCPU_FF_TIMER \
601 | VMCPU_FF_PDM_CRITSECT | VMCPU_FF_REQUEST) )
602
603/** All the forced VM flags. */
604#define VM_FF_ALL_MASK (UINT32_MAX)
605/** All the forced VMCPU flags. */
606#define VMCPU_FF_ALL_MASK (UINT32_MAX)
607
608/** All the forced VM flags except those related to raw-mode and hardware
609 * assisted execution. */
610#define VM_FF_ALL_REM_MASK (~(VM_FF_HIGH_PRIORITY_PRE_RAW_MASK) | VM_FF_PGM_NEED_HANDY_PAGES | VM_FF_PGM_NO_MEMORY)
611/** All the forced VMCPU flags except those related to raw-mode and hardware
612 * assisted execution. */
613#define VMCPU_FF_ALL_REM_MASK (~( VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK | VMCPU_FF_PDM_CRITSECT \
614 | VMCPU_FF_TLB_FLUSH | VM_WHEN_RAW_MODE(VMCPU_FF_CSAM_PENDING_ACTION, 0) ))
615/** @} */
616
617/** @def VM_FF_SET
618 * Sets a force action flag.
619 *
620 * @param pVM The cross context VM structure.
621 * @param fFlag The flag to set.
622 */
623#if 1
624# define VM_FF_SET(pVM, fFlag) ASMAtomicOrU32(&(pVM)->fGlobalForcedActions, (fFlag))
625#else
626# define VM_FF_SET(pVM, fFlag) \
627 do { ASMAtomicOrU32(&(pVM)->fGlobalForcedActions, (fFlag)); \
628 RTLogPrintf("VM_FF_SET : %08x %s - %s(%d) %s\n", (pVM)->fGlobalForcedActions, #fFlag, __FILE__, __LINE__, __FUNCTION__); \
629 } while (0)
630#endif
631
632/** @def VMCPU_FF_SET
633 * Sets a force action flag for the given VCPU.
634 *
635 * @param pVCpu The cross context virtual CPU structure.
636 * @param fFlag The flag to set.
637 */
638#define VMCPU_FF_SET(pVCpu, fFlag) ASMAtomicOrU32(&(pVCpu)->fLocalForcedActions, (fFlag))
639
640/** @def VM_FF_CLEAR
641 * Clears a force action flag.
642 *
643 * @param pVM The cross context VM structure.
644 * @param fFlag The flag to clear.
645 */
646#if 1
647# define VM_FF_CLEAR(pVM, fFlag) ASMAtomicAndU32(&(pVM)->fGlobalForcedActions, ~(fFlag))
648#else
649# define VM_FF_CLEAR(pVM, fFlag) \
650 do { ASMAtomicAndU32(&(pVM)->fGlobalForcedActions, ~(fFlag)); \
651 RTLogPrintf("VM_FF_CLEAR: %08x %s - %s(%d) %s\n", (pVM)->fGlobalForcedActions, #fFlag, __FILE__, __LINE__, __FUNCTION__); \
652 } while (0)
653#endif
654
655/** @def VMCPU_FF_CLEAR
656 * Clears a force action flag for the given VCPU.
657 *
658 * @param pVCpu The cross context virtual CPU structure.
659 * @param fFlag The flag to clear.
660 */
661#define VMCPU_FF_CLEAR(pVCpu, fFlag) ASMAtomicAndU32(&(pVCpu)->fLocalForcedActions, ~(fFlag))
662
663/** @def VM_FF_IS_SET
664 * Checks if a force action flag is set.
665 *
666 * @param pVM The cross context VM structure.
667 * @param fFlag The flag to check.
668 */
669#define VM_FF_IS_SET(pVM, fFlag) (((pVM)->fGlobalForcedActions & (fFlag)) == (fFlag))
670
671/** @def VMCPU_FF_IS_SET
672 * Checks if a force action flag is set for the given VCPU.
673 *
674 * @param pVCpu The cross context virtual CPU structure.
675 * @param fFlag The flag to check.
676 */
677#define VMCPU_FF_IS_SET(pVCpu, fFlag) (((pVCpu)->fLocalForcedActions & (fFlag)) == (fFlag))
678
679/** @def VM_FF_IS_PENDING
680 * Checks if one or more force action in the specified set is pending.
681 *
682 * @param pVM The cross context VM structure.
683 * @param fFlags The flags to check for.
684 */
685#define VM_FF_IS_PENDING(pVM, fFlags) RT_BOOL((pVM)->fGlobalForcedActions & (fFlags))
686
687/** @def VM_FF_TEST_AND_CLEAR
688 * Checks if one (!) force action in the specified set is pending and clears it atomically
689 *
690 * @returns true if the bit was set.
691 * @returns false if the bit was clear.
692 * @param pVM The cross context VM structure.
693 * @param iBit Bit position to check and clear
694 */
695#define VM_FF_TEST_AND_CLEAR(pVM, iBit) (ASMAtomicBitTestAndClear(&(pVM)->fGlobalForcedActions, iBit##_BIT))
696
697/** @def VMCPU_FF_TEST_AND_CLEAR
698 * Checks if one (!) force action in the specified set is pending and clears it atomically
699 *
700 * @returns true if the bit was set.
701 * @returns false if the bit was clear.
702 * @param pVCpu The cross context virtual CPU structure.
703 * @param iBit Bit position to check and clear
704 */
705#define VMCPU_FF_TEST_AND_CLEAR(pVCpu, iBit) (ASMAtomicBitTestAndClear(&(pVCpu)->fLocalForcedActions, iBit##_BIT))
706
707/** @def VMCPU_FF_IS_PENDING
708 * Checks if one or more force action in the specified set is pending for the given VCPU.
709 *
710 * @param pVCpu The cross context virtual CPU structure.
711 * @param fFlags The flags to check for.
712 */
713#define VMCPU_FF_IS_PENDING(pVCpu, fFlags) RT_BOOL((pVCpu)->fLocalForcedActions & (fFlags))
714
715/** @def VM_FF_IS_PENDING_EXCEPT
716 * Checks if one or more force action in the specified set is pending while one
717 * or more other ones are not.
718 *
719 * @param pVM The cross context VM structure.
720 * @param fFlags The flags to check for.
721 * @param fExcpt The flags that should not be set.
722 */
723#define VM_FF_IS_PENDING_EXCEPT(pVM, fFlags, fExcpt) ( ((pVM)->fGlobalForcedActions & (fFlags)) && !((pVM)->fGlobalForcedActions & (fExcpt)) )
724
725/** @def VMCPU_FF_IS_PENDING_EXCEPT
726 * Checks if one or more force action in the specified set is pending for the given
727 * VCPU while one or more other ones are not.
728 *
729 * @param pVCpu The cross context virtual CPU structure.
730 * @param fFlags The flags to check for.
731 * @param fExcpt The flags that should not be set.
732 */
733#define VMCPU_FF_IS_PENDING_EXCEPT(pVCpu, fFlags, fExcpt) ( ((pVCpu)->fLocalForcedActions & (fFlags)) && !((pVCpu)->fLocalForcedActions & (fExcpt)) )
734
735/** @def VM_IS_EMT
736 * Checks if the current thread is the emulation thread (EMT).
737 *
738 * @remark The ring-0 variation will need attention if we expand the ring-0
739 * code to let threads other than EMT mess around with the VM.
740 */
741#ifdef IN_RC
742# define VM_IS_EMT(pVM) true
743#else
744# define VM_IS_EMT(pVM) (VMMGetCpu(pVM) != NULL)
745#endif
746
747/** @def VMCPU_IS_EMT
748 * Checks if the current thread is the emulation thread (EMT) for the specified
749 * virtual CPU.
750 */
751#ifdef IN_RC
752# define VMCPU_IS_EMT(pVCpu) true
753#else
754# define VMCPU_IS_EMT(pVCpu) ((pVCpu) && ((pVCpu) == VMMGetCpu((pVCpu)->CTX_SUFF(pVM))))
755#endif
756
757/** @def VM_ASSERT_EMT
758 * Asserts that the current thread IS the emulation thread (EMT).
759 */
760#ifdef IN_RC
761# define VM_ASSERT_EMT(pVM) Assert(VM_IS_EMT(pVM))
762#elif defined(IN_RING0)
763# define VM_ASSERT_EMT(pVM) Assert(VM_IS_EMT(pVM))
764#else
765# define VM_ASSERT_EMT(pVM) \
766 AssertMsg(VM_IS_EMT(pVM), \
767 ("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd\n", RTThreadNativeSelf(), VMR3GetVMCPUNativeThread(pVM)))
768#endif
769
770/** @def VMCPU_ASSERT_EMT
771 * Asserts that the current thread IS the emulation thread (EMT) of the
772 * specified virtual CPU.
773 */
774#ifdef IN_RC
775# define VMCPU_ASSERT_EMT(pVCpu) Assert(VMCPU_IS_EMT(pVCpu))
776#elif defined(IN_RING0)
777# define VMCPU_ASSERT_EMT(pVCpu) AssertMsg(VMCPU_IS_EMT(pVCpu), \
778 ("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd idCpu=%u\n", \
779 RTThreadNativeSelf(), (pVCpu) ? (pVCpu)->hNativeThreadR0 : 0, \
780 (pVCpu) ? (pVCpu)->idCpu : 0))
781#else
782# define VMCPU_ASSERT_EMT(pVCpu) AssertMsg(VMCPU_IS_EMT(pVCpu), \
783 ("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd idCpu=%#x\n", \
784 RTThreadNativeSelf(), (pVCpu)->hNativeThread, (pVCpu)->idCpu))
785#endif
786
787/** @def VM_ASSERT_EMT_RETURN
788 * Asserts that the current thread IS the emulation thread (EMT) and returns if it isn't.
789 */
790#ifdef IN_RC
791# define VM_ASSERT_EMT_RETURN(pVM, rc) AssertReturn(VM_IS_EMT(pVM), (rc))
792#elif defined(IN_RING0)
793# define VM_ASSERT_EMT_RETURN(pVM, rc) AssertReturn(VM_IS_EMT(pVM), (rc))
794#else
795# define VM_ASSERT_EMT_RETURN(pVM, rc) \
796 AssertMsgReturn(VM_IS_EMT(pVM), \
797 ("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd\n", RTThreadNativeSelf(), VMR3GetVMCPUNativeThread(pVM)), \
798 (rc))
799#endif
800
801/** @def VMCPU_ASSERT_EMT_RETURN
802 * Asserts that the current thread IS the emulation thread (EMT) and returns if it isn't.
803 */
804#ifdef IN_RC
805# define VMCPU_ASSERT_EMT_RETURN(pVCpu, rc) AssertReturn(VMCPU_IS_EMT(pVCpu), (rc))
806#elif defined(IN_RING0)
807# define VMCPU_ASSERT_EMT_RETURN(pVCpu, rc) AssertReturn(VMCPU_IS_EMT(pVCpu), (rc))
808#else
809# define VMCPU_ASSERT_EMT_RETURN(pVCpu, rc) \
810 AssertMsgReturn(VMCPU_IS_EMT(pVCpu), \
811 ("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd idCpu=%#x\n", \
812 RTThreadNativeSelf(), (pVCpu)->hNativeThread, (pVCpu)->idCpu), \
813 (rc))
814#endif
815
816/** @def VMCPU_ASSERT_EMT_OR_GURU
817 * Asserts that the current thread IS the emulation thread (EMT) of the
818 * specified virtual CPU.
819 */
820#if defined(IN_RC) || defined(IN_RING0)
821# define VMCPU_ASSERT_EMT_OR_GURU(pVCpu) Assert( VMCPU_IS_EMT(pVCpu) \
822 || pVCpu->CTX_SUFF(pVM)->enmVMState == VMSTATE_GURU_MEDITATION \
823 || pVCpu->CTX_SUFF(pVM)->enmVMState == VMSTATE_GURU_MEDITATION_LS )
824#else
825# define VMCPU_ASSERT_EMT_OR_GURU(pVCpu) \
826 AssertMsg( VMCPU_IS_EMT(pVCpu) \
827 || pVCpu->CTX_SUFF(pVM)->enmVMState == VMSTATE_GURU_MEDITATION \
828 || pVCpu->CTX_SUFF(pVM)->enmVMState == VMSTATE_GURU_MEDITATION_LS, \
829 ("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd idCpu=%#x\n", \
830 RTThreadNativeSelf(), (pVCpu)->hNativeThread, (pVCpu)->idCpu))
831#endif
832
833/** @def VMCPU_ASSERT_EMT_OR_NOT_RUNNING
834 * Asserts that the current thread IS the emulation thread (EMT) of the
835 * specified virtual CPU or the VM is not running.
836 */
837#if defined(IN_RC) || defined(IN_RING0)
838# define VMCPU_ASSERT_EMT_OR_NOT_RUNNING(pVCpu) \
839 Assert( VMCPU_IS_EMT(pVCpu) \
840 || !VM_IS_RUNNING_FOR_ASSERTIONS_ONLY((pVCpu)->CTX_SUFF(pVM)) )
841#else
842# define VMCPU_ASSERT_EMT_OR_NOT_RUNNING(pVCpu) \
843 AssertMsg( VMCPU_IS_EMT(pVCpu) \
844 || !VM_IS_RUNNING_FOR_ASSERTIONS_ONLY((pVCpu)->CTX_SUFF(pVM)), \
845 ("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd idCpu=%#x\n", \
846 RTThreadNativeSelf(), (pVCpu)->hNativeThread, (pVCpu)->idCpu))
847#endif
848
849/** @def VM_IS_RUNNING_FOR_ASSERTIONS_ONLY
850 * Checks if the the VM is running.
851 * @note Thie is only for pure debug assertions. No AssertReturn or similar!
852 */
853#define VM_IS_RUNNING_FOR_ASSERTIONS_ONLY(pVM) \
854 ( (pVM)->enmVMState == VMSTATE_RUNNING \
855 || (pVM)->enmVMState == VMSTATE_RUNNING_LS \
856 || (pVM)->enmVMState == VMSTATE_RUNNING_FT )
857
858/** @def VM_ASSERT_IS_NOT_RUNNING
859 * Asserts that the VM is not running.
860 */
861#if defined(IN_RC) || defined(IN_RING0)
862#define VM_ASSERT_IS_NOT_RUNNING(pVM) Assert(!VM_IS_RUNNING_FOR_ASSERTIONS_ONLY(pVM))
863#else
864#define VM_ASSERT_IS_NOT_RUNNING(pVM) AssertMsg(!VM_IS_RUNNING_FOR_ASSERTIONS_ONLY(pVM), \
865 ("VM is running. enmVMState=%d\n", (pVM)->enmVMState))
866#endif
867
868/** @def VM_ASSERT_EMT0
869 * Asserts that the current thread IS emulation thread \#0 (EMT0).
870 */
871#define VM_ASSERT_EMT0(pVM) VMCPU_ASSERT_EMT(&(pVM)->aCpus[0])
872
873/** @def VM_ASSERT_EMT0_RETURN
874 * Asserts that the current thread IS emulation thread \#0 (EMT0) and returns if
875 * it isn't.
876 */
877#define VM_ASSERT_EMT0_RETURN(pVM, rc) VMCPU_ASSERT_EMT_RETURN(&(pVM)->aCpus[0], (rc))
878
879
880/**
881 * Asserts that the current thread is NOT the emulation thread.
882 */
883#define VM_ASSERT_OTHER_THREAD(pVM) \
884 AssertMsg(!VM_IS_EMT(pVM), ("Not other thread!!\n"))
885
886
887/** @def VM_ASSERT_STATE
888 * Asserts a certain VM state.
889 */
890#define VM_ASSERT_STATE(pVM, _enmState) \
891 AssertMsg((pVM)->enmVMState == (_enmState), \
892 ("state %s, expected %s\n", VMGetStateName((pVM)->enmVMState), VMGetStateName(_enmState)))
893
894/** @def VM_ASSERT_STATE_RETURN
895 * Asserts a certain VM state and returns if it doesn't match.
896 */
897#define VM_ASSERT_STATE_RETURN(pVM, _enmState, rc) \
898 AssertMsgReturn((pVM)->enmVMState == (_enmState), \
899 ("state %s, expected %s\n", VMGetStateName((pVM)->enmVMState), VMGetStateName(_enmState)), \
900 (rc))
901
902/** @def VM_IS_VALID_EXT
903 * Asserts a the VM handle is valid for external access, i.e. not being destroy
904 * or terminated. */
905#define VM_IS_VALID_EXT(pVM) \
906 ( RT_VALID_ALIGNED_PTR(pVM, PAGE_SIZE) \
907 && ( (unsigned)(pVM)->enmVMState < (unsigned)VMSTATE_DESTROYING \
908 || ( (unsigned)(pVM)->enmVMState == (unsigned)VMSTATE_DESTROYING \
909 && VM_IS_EMT(pVM))) )
910
911/** @def VM_ASSERT_VALID_EXT_RETURN
912 * Asserts a the VM handle is valid for external access, i.e. not being
913 * destroy or terminated.
914 */
915#define VM_ASSERT_VALID_EXT_RETURN(pVM, rc) \
916 AssertMsgReturn(VM_IS_VALID_EXT(pVM), \
917 ("pVM=%p state %s\n", (pVM), RT_VALID_ALIGNED_PTR(pVM, PAGE_SIZE) \
918 ? VMGetStateName(pVM->enmVMState) : ""), \
919 (rc))
920
921/** @def VMCPU_ASSERT_VALID_EXT_RETURN
922 * Asserts a the VMCPU handle is valid for external access, i.e. not being
923 * destroy or terminated.
924 */
925#define VMCPU_ASSERT_VALID_EXT_RETURN(pVCpu, rc) \
926 AssertMsgReturn( RT_VALID_ALIGNED_PTR(pVCpu, 64) \
927 && RT_VALID_ALIGNED_PTR((pVCpu)->CTX_SUFF(pVM), PAGE_SIZE) \
928 && (unsigned)(pVCpu)->CTX_SUFF(pVM)->enmVMState < (unsigned)VMSTATE_DESTROYING, \
929 ("pVCpu=%p pVM=%p state %s\n", (pVCpu), RT_VALID_ALIGNED_PTR(pVCpu, 64) ? (pVCpu)->CTX_SUFF(pVM) : NULL, \
930 RT_VALID_ALIGNED_PTR(pVCpu, 64) && RT_VALID_ALIGNED_PTR((pVCpu)->CTX_SUFF(pVM), PAGE_SIZE) \
931 ? VMGetStateName((pVCpu)->pVMR3->enmVMState) : ""), \
932 (rc))
933
934#endif /* !VBOX_FOR_DTRACE_LIB */
935
936
937/**
938 * Helper that HM and NEM uses for safely modifying VM::bMainExecutionEngine.
939 *
940 * ONLY HM and NEM MAY USE THIS!
941 *
942 * @param a_pVM The cross context VM structure.
943 * @param a_bValue The new value.
944 * @internal
945 */
946#define VM_SET_MAIN_EXECUTION_ENGINE(a_pVM, a_bValue) \
947 do { \
948 *const_cast<uint8_t *>(&(a_pVM)->bMainExecutionEngine) = (a_bValue); \
949 ASMCompilerBarrier(); /* just to be on the safe side */ \
950 } while (0)
951
952/**
953 * Checks whether raw-mode is used.
954 *
955 * @retval true if either is used.
956 * @retval false if software virtualization (raw-mode) is used.
957 *
958 * @param a_pVM The cross context VM structure.
959 * @sa VM_IS_HM_OR_NEM_ENABLED, VM_IS_HM_ENABLED, VM_IS_NEM_ENABLED.
960 * @internal
961 */
962#ifdef VBOX_WITH_RAW_MODE
963# define VM_IS_RAW_MODE_ENABLED(a_pVM) ((a_pVM)->bMainExecutionEngine == VM_EXEC_ENGINE_RAW_MODE)
964#else
965# define VM_IS_RAW_MODE_ENABLED(a_pVM) (false)
966#endif
967
968/**
969 * Checks whether HM (VT-x/AMD-V) or NEM is being used by this VM.
970 *
971 * @retval true if either is used.
972 * @retval false if software virtualization (raw-mode) is used.
973 *
974 * @param a_pVM The cross context VM structure.
975 * @sa VM_IS_RAW_MODE_ENABLED, VM_IS_HM_ENABLED, VM_IS_NEM_ENABLED.
976 * @internal
977 */
978#define VM_IS_HM_OR_NEM_ENABLED(a_pVM) ((a_pVM)->bMainExecutionEngine != VM_EXEC_ENGINE_RAW_MODE)
979
980/**
981 * Checks whether HM is being used by this VM.
982 *
983 * @retval true if HM (VT-x/AMD-v) is used.
984 * @retval false if not.
985 *
986 * @param a_pVM The cross context VM structure.
987 * @sa VM_IS_NEM_ENABLED, VM_IS_RAW_MODE_ENABLED, VM_IS_HM_OR_NEM_ENABLED.
988 * @internal
989 */
990#define VM_IS_HM_ENABLED(a_pVM) ((a_pVM)->bMainExecutionEngine == VM_EXEC_ENGINE_HW_VIRT)
991
992/**
993 * Checks whether NEM is being used by this VM.
994 *
995 * @retval true if a native hypervisor API is used.
996 * @retval false if not.
997 *
998 * @param a_pVM The cross context VM structure.
999 * @sa VM_IS_HM_ENABLED, VM_IS_RAW_MODE_ENABLED, VM_IS_HM_OR_NEM_ENABLED.
1000 * @internal
1001 */
1002#define VM_IS_NEM_ENABLED(a_pVM) ((a_pVM)->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API)
1003
1004
1005/**
1006 * The cross context VM structure.
1007 *
1008 * It contains all the VM data which have to be available in all contexts.
1009 * Even if it contains all the data the idea is to use APIs not to modify all
1010 * the members all around the place. Therefore we make use of unions to hide
1011 * everything which isn't local to the current source module. This means we'll
1012 * have to pay a little bit of attention when adding new members to structures
1013 * in the unions and make sure to keep the padding sizes up to date.
1014 *
1015 * Run 'kmk run-struct-tests' (from src/VBox/VMM if you like) after updating!
1016 */
1017typedef struct VM
1018{
1019 /** The state of the VM.
1020 * This field is read only to everyone except the VM and EM. */
1021 VMSTATE volatile enmVMState;
1022 /** Forced action flags.
1023 * See the VM_FF_* \#defines. Updated atomically.
1024 */
1025 volatile uint32_t fGlobalForcedActions;
1026 /** Pointer to the array of page descriptors for the VM structure allocation. */
1027 R3PTRTYPE(PSUPPAGE) paVMPagesR3;
1028 /** Session handle. For use when calling SUPR0 APIs. */
1029 PSUPDRVSESSION pSession;
1030 /** Pointer to the ring-3 VM structure. */
1031 PUVM pUVM;
1032 /** Ring-3 Host Context VM Pointer. */
1033 R3PTRTYPE(struct VM *) pVMR3;
1034 /** Ring-0 Host Context VM Pointer. */
1035 R0PTRTYPE(struct VM *) pVMR0;
1036 /** Raw-mode Context VM Pointer. */
1037 RCPTRTYPE(struct VM *) pVMRC;
1038
1039 /** The GVM VM handle. Only the GVM should modify this field. */
1040 uint32_t hSelf;
1041 /** Number of virtual CPUs. */
1042 uint32_t cCpus;
1043 /** CPU excution cap (1-100) */
1044 uint32_t uCpuExecutionCap;
1045
1046 /** Size of the VM structure including the VMCPU array. */
1047 uint32_t cbSelf;
1048
1049 /** Offset to the VMCPU array starting from beginning of this structure. */
1050 uint32_t offVMCPU;
1051
1052 /**
1053 * VMMSwitcher assembly entry point returning to host context.
1054 *
1055 * Depending on how the host handles the rc status given in @a eax, this may
1056 * return and let the caller resume whatever it was doing prior to the call.
1057 *
1058 *
1059 * @param eax The return code, register.
1060 * @remark Assume interrupts disabled.
1061 * @remark This method pointer lives here because TRPM needs it.
1062 */
1063 RTRCPTR pfnVMMRCToHostAsm/*(int32_t eax)*/;
1064
1065 /**
1066 * VMMSwitcher assembly entry point returning to host context without saving the
1067 * raw-mode context (hyper) registers.
1068 *
1069 * Unlike pfnVMMRC2HCAsm, this will not return to the caller. Instead it
1070 * expects the caller to save a RC context in CPUM where one might return if the
1071 * return code indicate that this is possible.
1072 *
1073 * This method pointer lives here because TRPM needs it.
1074 *
1075 * @param eax The return code, register.
1076 * @remark Assume interrupts disabled.
1077 * @remark This method pointer lives here because TRPM needs it.
1078 */
1079 RTRCPTR pfnVMMRCToHostAsmNoReturn/*(int32_t eax)*/;
1080
1081 /** @name Various items that are frequently accessed.
1082 * @{ */
1083 /** The main execution engine, VM_EXEC_ENGINE_XXX.
1084 * This is set early during vmR3InitRing3 by HM or NEM. */
1085 uint8_t const bMainExecutionEngine;
1086
1087 /** Whether to recompile user mode code or run it raw/hm/nem.
1088 * In non-raw-mode both fRecompileUser and fRecompileSupervisor must be set
1089 * to recompiler stuff. */
1090 bool fRecompileUser;
1091 /** Whether to recompile supervisor mode code or run it raw/hm/nem.
1092 * In non-raw-mode both fRecompileUser and fRecompileSupervisor must be set
1093 * to recompiler stuff. */
1094 bool fRecompileSupervisor;
1095 /** Whether raw mode supports ring-1 code or not.
1096 * This will be cleared when not in raw-mode. */
1097 bool fRawRing1Enabled;
1098 /** PATM enabled flag.
1099 * This is placed here for performance reasons.
1100 * This will be cleared when not in raw-mode. */
1101 bool fPATMEnabled;
1102 /** CSAM enabled flag.
1103 * This is placed here for performance reasons.
1104 * This will be cleared when not in raw-mode. */
1105 bool fCSAMEnabled;
1106
1107 /** Hardware VM support is available and enabled.
1108 * Determined very early during init.
1109 * This is placed here for performance reasons.
1110 * @todo obsoleted by bMainExecutionEngine, eliminate. */
1111 bool fHMEnabled;
1112 /** Hardware VM support requires a minimal raw-mode context.
1113 * This is never set on 64-bit hosts, only 32-bit hosts requires it. */
1114 bool fHMNeedRawModeCtx;
1115
1116 /** Set when this VM is the master FT node.
1117 * @todo This doesn't need to be here, FTM should store it in it's own
1118 * structures instead. */
1119 bool fFaultTolerantMaster;
1120 /** Large page enabled flag.
1121 * @todo This doesn't need to be here, PGM should store it in it's own
1122 * structures instead. */
1123 bool fUseLargePages;
1124 /** @} */
1125
1126 /** Alignment padding. */
1127 uint8_t uPadding1[2];
1128
1129 /** @name Debugging
1130 * @{ */
1131 /** Raw-mode Context VM Pointer. */
1132 RCPTRTYPE(RTTRACEBUF) hTraceBufRC;
1133 /** Ring-3 Host Context VM Pointer. */
1134 R3PTRTYPE(RTTRACEBUF) hTraceBufR3;
1135 /** Ring-0 Host Context VM Pointer. */
1136 R0PTRTYPE(RTTRACEBUF) hTraceBufR0;
1137 /** @} */
1138
1139#if HC_ARCH_BITS == 32
1140 /** Alignment padding. */
1141 uint32_t uPadding2;
1142#endif
1143
1144 /** @name Switcher statistics (remove)
1145 * @{ */
1146 /** Profiling the total time from Qemu to GC. */
1147 STAMPROFILEADV StatTotalQemuToGC;
1148 /** Profiling the total time from GC to Qemu. */
1149 STAMPROFILEADV StatTotalGCToQemu;
1150 /** Profiling the total time spent in GC. */
1151 STAMPROFILEADV StatTotalInGC;
1152 /** Profiling the total time spent not in Qemu. */
1153 STAMPROFILEADV StatTotalInQemu;
1154 /** Profiling the VMMSwitcher code for going to GC. */
1155 STAMPROFILEADV StatSwitcherToGC;
1156 /** Profiling the VMMSwitcher code for going to HC. */
1157 STAMPROFILEADV StatSwitcherToHC;
1158 STAMPROFILEADV StatSwitcherSaveRegs;
1159 STAMPROFILEADV StatSwitcherSysEnter;
1160 STAMPROFILEADV StatSwitcherDebug;
1161 STAMPROFILEADV StatSwitcherCR0;
1162 STAMPROFILEADV StatSwitcherCR4;
1163 STAMPROFILEADV StatSwitcherJmpCR3;
1164 STAMPROFILEADV StatSwitcherRstrRegs;
1165 STAMPROFILEADV StatSwitcherLgdt;
1166 STAMPROFILEADV StatSwitcherLidt;
1167 STAMPROFILEADV StatSwitcherLldt;
1168 STAMPROFILEADV StatSwitcherTSS;
1169 /** @} */
1170
1171 /** Padding - the unions must be aligned on a 64 bytes boundary and the unions
1172 * must start at the same offset on both 64-bit and 32-bit hosts. */
1173 uint8_t abAlignment3[(HC_ARCH_BITS == 32 ? 24 : 0) + 40];
1174
1175 /** CPUM part. */
1176 union
1177 {
1178#ifdef ___CPUMInternal_h
1179 struct CPUM s;
1180#endif
1181#ifdef ___VBox_vmm_cpum_h
1182 /** Read only info exposed about the host and guest CPUs. */
1183 struct
1184 {
1185 /** Padding for hidden fields. */
1186 uint8_t abHidden0[64];
1187 /** Host CPU feature information. */
1188 CPUMFEATURES HostFeatures;
1189 /** Guest CPU feature information. */
1190 CPUMFEATURES GuestFeatures;
1191 } const ro;
1192#endif
1193 uint8_t padding[1536]; /* multiple of 64 */
1194 } cpum;
1195
1196 /** VMM part. */
1197 union
1198 {
1199#ifdef ___VMMInternal_h
1200 struct VMM s;
1201#endif
1202 uint8_t padding[1600]; /* multiple of 64 */
1203 } vmm;
1204
1205 /** PGM part. */
1206 union
1207 {
1208#ifdef ___PGMInternal_h
1209 struct PGM s;
1210#endif
1211 uint8_t padding[4096*2+6080]; /* multiple of 64 */
1212 } pgm;
1213
1214 /** HM part. */
1215 union
1216 {
1217#ifdef ___HMInternal_h
1218 struct HM s;
1219#endif
1220 uint8_t padding[5440]; /* multiple of 64 */
1221 } hm;
1222
1223 /** TRPM part. */
1224 union
1225 {
1226#ifdef ___TRPMInternal_h
1227 struct TRPM s;
1228#endif
1229 uint8_t padding[5248]; /* multiple of 64 */
1230 } trpm;
1231
1232 /** SELM part. */
1233 union
1234 {
1235#ifdef ___SELMInternal_h
1236 struct SELM s;
1237#endif
1238 uint8_t padding[768]; /* multiple of 64 */
1239 } selm;
1240
1241 /** MM part. */
1242 union
1243 {
1244#ifdef ___MMInternal_h
1245 struct MM s;
1246#endif
1247 uint8_t padding[192]; /* multiple of 64 */
1248 } mm;
1249
1250 /** PDM part. */
1251 union
1252 {
1253#ifdef ___PDMInternal_h
1254 struct PDM s;
1255#endif
1256 uint8_t padding[1920]; /* multiple of 64 */
1257 } pdm;
1258
1259 /** IOM part. */
1260 union
1261 {
1262#ifdef ___IOMInternal_h
1263 struct IOM s;
1264#endif
1265 uint8_t padding[896]; /* multiple of 64 */
1266 } iom;
1267
1268 /** EM part. */
1269 union
1270 {
1271#ifdef ___EMInternal_h
1272 struct EM s;
1273#endif
1274 uint8_t padding[256]; /* multiple of 64 */
1275 } em;
1276
1277 /** NEM part. */
1278 union
1279 {
1280#ifdef ___NEMInternal_h
1281 struct NEM s;
1282#endif
1283 uint8_t padding[128]; /* multiple of 64 */
1284 } nem;
1285
1286 /** TM part. */
1287 union
1288 {
1289#ifdef ___TMInternal_h
1290 struct TM s;
1291#endif
1292 uint8_t padding[2496]; /* multiple of 64 */
1293 } tm;
1294
1295 /** DBGF part. */
1296 union
1297 {
1298#ifdef ___DBGFInternal_h
1299 struct DBGF s;
1300#endif
1301#ifdef ___VBox_vmm_dbgf_h
1302 /** Read only info exposed about interrupt breakpoints and selected events. */
1303 struct
1304 {
1305 /** Bitmap of enabled hardware interrupt breakpoints. */
1306 uint32_t bmHardIntBreakpoints[256 / 32];
1307 /** Bitmap of enabled software interrupt breakpoints. */
1308 uint32_t bmSoftIntBreakpoints[256 / 32];
1309 /** Bitmap of selected events.
1310 * This includes non-selectable events too for simplicity, we maintain the
1311 * state for some of these, as it may come in handy. */
1312 uint64_t bmSelectedEvents[(DBGFEVENT_END + 63) / 64];
1313 /** Enabled hardware interrupt breakpoints. */
1314 uint32_t cHardIntBreakpoints;
1315 /** Enabled software interrupt breakpoints. */
1316 uint32_t cSoftIntBreakpoints;
1317 /** The number of selected events. */
1318 uint32_t cSelectedEvents;
1319 /** The number of enabled hardware breakpoints. */
1320 uint8_t cEnabledHwBreakpoints;
1321 /** The number of enabled hardware I/O breakpoints. */
1322 uint8_t cEnabledHwIoBreakpoints;
1323 /** The number of enabled INT3 breakpoints. */
1324 uint8_t cEnabledInt3Breakpoints;
1325 uint8_t abPadding[1]; /**< Unused padding space up for grabs. */
1326 } const ro;
1327#endif
1328 uint8_t padding[2368]; /* multiple of 64 */
1329 } dbgf;
1330
1331 /** SSM part. */
1332 union
1333 {
1334#ifdef ___SSMInternal_h
1335 struct SSM s;
1336#endif
1337 uint8_t padding[128]; /* multiple of 64 */
1338 } ssm;
1339
1340 /** FTM part. */
1341 union
1342 {
1343#ifdef ___FTMInternal_h
1344 struct FTM s;
1345#endif
1346 uint8_t padding[512]; /* multiple of 64 */
1347 } ftm;
1348
1349#ifdef VBOX_WITH_RAW_MODE
1350 /** PATM part. */
1351 union
1352 {
1353# ifdef ___PATMInternal_h
1354 struct PATM s;
1355# endif
1356 uint8_t padding[768]; /* multiple of 64 */
1357 } patm;
1358
1359 /** CSAM part. */
1360 union
1361 {
1362# ifdef ___CSAMInternal_h
1363 struct CSAM s;
1364# endif
1365 uint8_t padding[1088]; /* multiple of 64 */
1366 } csam;
1367#endif
1368
1369#ifdef VBOX_WITH_REM
1370 /** REM part. */
1371 union
1372 {
1373# ifdef ___REMInternal_h
1374 struct REM s;
1375# endif
1376 uint8_t padding[0x11100]; /* multiple of 64 */
1377 } rem;
1378#endif
1379
1380 union
1381 {
1382#ifdef ___GIMInternal_h
1383 struct GIM s;
1384#endif
1385 uint8_t padding[448]; /* multiple of 64 */
1386 } gim;
1387
1388 union
1389 {
1390#ifdef ___APICInternal_h
1391 struct APIC s;
1392#endif
1393 uint8_t padding[128]; /* multiple of 8 */
1394 } apic;
1395
1396 /* ---- begin small stuff ---- */
1397
1398 /** VM part. */
1399 union
1400 {
1401#ifdef ___VMInternal_h
1402 struct VMINT s;
1403#endif
1404 uint8_t padding[24]; /* multiple of 8 */
1405 } vm;
1406
1407 /** CFGM part. */
1408 union
1409 {
1410#ifdef ___CFGMInternal_h
1411 struct CFGM s;
1412#endif
1413 uint8_t padding[8]; /* multiple of 8 */
1414 } cfgm;
1415
1416 /** Padding for aligning the cpu array on a page boundary. */
1417#if defined(VBOX_WITH_REM) && defined(VBOX_WITH_RAW_MODE)
1418 uint8_t abAlignment2[3742];
1419#elif defined(VBOX_WITH_REM) && !defined(VBOX_WITH_RAW_MODE)
1420 uint8_t abAlignment2[1502];
1421#elif !defined(VBOX_WITH_REM) && defined(VBOX_WITH_RAW_MODE)
1422 uint8_t abAlignment2[3998];
1423#else
1424 uint8_t abAlignment2[1758];
1425#endif
1426
1427 /* ---- end small stuff ---- */
1428
1429 /** VMCPU array for the configured number of virtual CPUs.
1430 * Must be aligned on a page boundary for TLB hit reasons as well as
1431 * alignment of VMCPU members. */
1432 VMCPU aCpus[1];
1433} VM;
1434
1435
1436#ifdef IN_RC
1437RT_C_DECLS_BEGIN
1438
1439/** The VM structure.
1440 * This is imported from the VMMRCBuiltin module, i.e. it's a one of those magic
1441 * globals which we should avoid using.
1442 */
1443extern DECLIMPORT(VM) g_VM;
1444
1445RT_C_DECLS_END
1446#endif
1447
1448/** @} */
1449
1450#endif
1451
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