vm.h@ 74797

Last change on this file since 74797 was 74797, checked in by vboxsync, 6 years ago
vm.h/mac: Make space for larger fLocalForcedActions. bugref:9180
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 58.7 KB

Line
1	/** @file
2	* VM - The Virtual Machine, data.
3	*/
4
5	/*
6	* Copyright (C) 2006-2017 Oracle Corporation
7	*
8	* This file is part of VirtualBox Open Source Edition (OSE), as
9	* available from http://www.virtualbox.org. This file is free software;
10	* you can redistribute it and/or modify it under the terms of the GNU
11	* General Public License (GPL) as published by the Free Software
12	* Foundation, in version 2 as it comes in the "COPYING" file of the
13	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15	*
16	* The contents of this file may alternatively be used under the terms
17	* of the Common Development and Distribution License Version 1.0
18	* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19	* VirtualBox OSE distribution, in which case the provisions of the
20	* CDDL are applicable instead of those of the GPL.
21	*
22	* You may elect to license modified versions of this file under the
23	* terms and conditions of either the GPL or the CDDL or both.
24	*/
25
26	#ifndef ___VBox_vmm_vm_h
27	#define ___VBox_vmm_vm_h
28
29	#ifndef VBOX_FOR_DTRACE_LIB
30	# include <iprt/param.h>
31	# include <VBox/types.h>
32	# include <VBox/vmm/cpum.h>
33	# include <VBox/vmm/stam.h>
34	# include <VBox/vmm/vmapi.h>
35	# include <VBox/vmm/vmm.h>
36	# include <VBox/sup.h>
37	#else
38	# pragma D depends_on library vbox-types.d
39	# pragma D depends_on library CPUMInternal.d
40	# define ___CPUMInternal_h
41	#endif
42
43
44
45	/** @defgroup grp_vm The Virtual Machine
46	* @ingroup grp_vmm
47	* @{
48	*/
49
50	/**
51	* The state of a Virtual CPU.
52	*
53	* The basic state indicated here is whether the CPU has been started or not. In
54	* addition, there are sub-states when started for assisting scheduling (GVMM
55	* mostly).
56	*
57	* The transition out of the STOPPED state is done by a vmR3PowerOn.
58	* The transition back to the STOPPED state is done by vmR3PowerOff.
59	*
60	* (Alternatively we could let vmR3PowerOn start CPU 0 only and let the SPIP
61	* handling switch on the other CPUs. Then vmR3Reset would stop all but CPU 0.)
62	*/
63	typedef enum VMCPUSTATE
64	{
65	/** The customary invalid zero. */
66	VMCPUSTATE_INVALID = 0,
67
68	/** Virtual CPU has not yet been started. */
69	VMCPUSTATE_STOPPED,
70
71	/** CPU started. */
72	VMCPUSTATE_STARTED,
73	/** CPU started in HM context. */
74	VMCPUSTATE_STARTED_HM,
75	/** Executing guest code and can be poked (RC or STI bits of HM). */
76	VMCPUSTATE_STARTED_EXEC,
77	/** Executing guest code in the recompiler. */
78	VMCPUSTATE_STARTED_EXEC_REM,
79	/** Executing guest code using NEM. */
80	VMCPUSTATE_STARTED_EXEC_NEM,
81	VMCPUSTATE_STARTED_EXEC_NEM_WAIT,
82	VMCPUSTATE_STARTED_EXEC_NEM_CANCELED,
83	/** Halted. */
84	VMCPUSTATE_STARTED_HALTED,
85
86	/** The end of valid virtual CPU states. */
87	VMCPUSTATE_END,
88
89	/** Ensure 32-bit type. */
90	VMCPUSTATE_32BIT_HACK = 0x7fffffff
91	} VMCPUSTATE;
92
93
94	/**
95	* The cross context virtual CPU structure.
96	*
97	* Run 'kmk run-struct-tests' (from src/VBox/VMM if you like) after updating!
98	*/
99	typedef struct VMCPU
100	{
101	/** @name Volatile per-cpu data.
102	* @{ */
103	/** Per CPU forced action.
104	* See the VMCPU_FF_* \#defines. Updated atomically. */
105	uint32_t volatile fLocalForcedActions;
106	uint32_t fForLocalForcedActionsExpansion;
107	/** The CPU state. */
108	VMCPUSTATE volatile enmState;
109
110	/** Which host CPU ID is this EMT running on.
111	* Only valid when in RC or HMR0 with scheduling disabled. */
112	RTCPUID volatile idHostCpu;
113	/** The CPU set index corresponding to idHostCpu, UINT32_MAX if not valid.
114	* @remarks Best to make sure iHostCpuSet shares cache line with idHostCpu! */
115	uint32_t volatile iHostCpuSet;
116	/** Padding up to 64 bytes. */
117	uint8_t abAlignment0[64 - 20];
118	/** @} */
119
120	/** IEM part.
121	* @remarks This comes first as it allows the use of 8-bit immediates for the
122	* first 64 bytes of the structure, reducing code size a wee bit. */
123	#ifdef ___IEMInternal_h /* For PDB hacking. */
124	union VMCPUUNIONIEMFULL
125	#else
126	union VMCPUUNIONIEMSTUB
127	#endif
128	{
129	#ifdef ___IEMInternal_h
130	struct IEMCPU s;
131	#endif
132	uint8_t padding[18496]; /* multiple of 64 */
133	} iem;
134
135	/** @name Static per-cpu data.
136	* (Putting this after IEM, hoping that it's less frequently used than it.)
137	* @{ */
138	/** The CPU ID.
139	* This is the index into the VM::aCpu array. */
140	VMCPUID idCpu;
141	/** Raw-mode Context VM Pointer. */
142	PVMRC pVMRC;
143	/** Ring-3 Host Context VM Pointer. */
144	PVMR3 pVMR3;
145	/** Ring-0 Host Context VM Pointer. */
146	PVMR0 pVMR0;
147	/** Pointer to the ring-3 UVMCPU structure. */
148	PUVMCPU pUVCpu;
149	/** The native thread handle. */
150	RTNATIVETHREAD hNativeThread;
151	/** The native R0 thread handle. (different from the R3 handle!) */
152	RTNATIVETHREAD hNativeThreadR0;
153	/** Align the structures below bit on a 64-byte boundary and make sure it starts
154	* at the same offset in both 64-bit and 32-bit builds.
155	*
156	* @remarks The alignments of the members that are larger than 48 bytes should be
157	* 64-byte for cache line reasons. structs containing small amounts of
158	* data could be lumped together at the end with a < 64 byte padding
159	* following it (to grow into and align the struct size).
160	*/
161	uint8_t abAlignment1[64 - 4 - 4 - 5 * (HC_ARCH_BITS == 64 ? 8 : 4)];
162	/** @} */
163
164	/** HM part. */
165	union VMCPUUNIONHM
166	{
167	#ifdef ___HMInternal_h
168	struct HMCPU s;
169	#endif
170	uint8_t padding[5888]; /* multiple of 64 */
171	} hm;
172
173	/** NEM part. */
174	union VMCPUUNIONNEM
175	{
176	#ifdef ___NEMInternal_h
177	struct NEMCPU s;
178	#endif
179	uint8_t padding[512]; /* multiple of 64 */
180	} nem;
181
182	/** TRPM part. */
183	union VMCPUUNIONTRPM
184	{
185	#ifdef ___TRPMInternal_h
186	struct TRPMCPU s;
187	#endif
188	uint8_t padding[128]; /* multiple of 64 */
189	} trpm;
190
191	/** TM part. */
192	union VMCPUUNIONTM
193	{
194	#ifdef ___TMInternal_h
195	struct TMCPU s;
196	#endif
197	uint8_t padding[384]; /* multiple of 64 */
198	} tm;
199
200	/** VMM part. */
201	union VMCPUUNIONVMM
202	{
203	#ifdef ___VMMInternal_h
204	struct VMMCPU s;
205	#endif
206	uint8_t padding[768]; /* multiple of 64 */
207	} vmm;
208
209	/** PDM part. */
210	union VMCPUUNIONPDM
211	{
212	#ifdef ___PDMInternal_h
213	struct PDMCPU s;
214	#endif
215	uint8_t padding[256]; /* multiple of 64 */
216	} pdm;
217
218	/** IOM part. */
219	union VMCPUUNIONIOM
220	{
221	#ifdef ___IOMInternal_h
222	struct IOMCPU s;
223	#endif
224	uint8_t padding[512]; /* multiple of 64 */
225	} iom;
226
227	/** DBGF part.
228	* @todo Combine this with other tiny structures. */
229	union VMCPUUNIONDBGF
230	{
231	#ifdef ___DBGFInternal_h
232	struct DBGFCPU s;
233	#endif
234	uint8_t padding[256]; /* multiple of 64 */
235	} dbgf;
236
237	/** GIM part. */
238	union VMCPUUNIONGIM
239	{
240	#ifdef ___GIMInternal_h
241	struct GIMCPU s;
242	#endif
243	uint8_t padding[512]; /* multiple of 64 */
244	} gim;
245
246	/** APIC part. */
247	union VMCPUUNIONAPIC
248	{
249	#ifdef ___APICInternal_h
250	struct APICCPU s;
251	#endif
252	uint8_t padding[1792]; /* multiple of 64 */
253	} apic;
254
255	/*
256	* Some less frequently used global members that doesn't need to take up
257	* precious space at the head of the structure.
258	*/
259
260	/** Trace groups enable flags. */
261	uint32_t fTraceGroups; /* 64 / 44 */
262	/** State data for use by ad hoc profiling. */
263	uint32_t uAdHoc;
264	/** Profiling samples for use by ad hoc profiling. */
265	STAMPROFILEADV aStatAdHoc[8]; /* size: 408 = 320 /
266
267	/** Align the following members on page boundary. */
268	uint8_t abAlignment2[2808];
269
270	/** PGM part. */
271	union VMCPUUNIONPGM
272	{
273	#ifdef ___PGMInternal_h
274	struct PGMCPU s;
275	#endif
276	uint8_t padding[4096]; /* multiple of 4096 */
277	} pgm;
278
279	/** CPUM part. */
280	union VMCPUUNIONCPUM
281	{
282	#ifdef ___CPUMInternal_h
283	struct CPUMCPU s;
284	#endif
285	#ifdef VMCPU_INCL_CPUM_GST_CTX
286	/** The guest CPUM context for direct use by execution engines.
287	* This is not for general consumption, but for HM, REM, IEM, and maybe a few
288	* others. The rest will use the function based CPUM API. */
289	CPUMCTX GstCtx;
290	#endif
291	uint8_t padding[4096]; /* multiple of 4096 */
292	} cpum;
293
294	/** EM part. */
295	union VMCPUUNIONEM
296	{
297	#ifdef ___EMInternal_h
298	struct EMCPU s;
299	#endif
300	uint8_t padding[40960]; /* multiple of 4096 */
301	} em;
302	} VMCPU;
303
304
305	#ifndef VBOX_FOR_DTRACE_LIB
306
307	/** @name Operations on VMCPU::enmState
308	* @{ */
309	/** Gets the VMCPU state. */
310	#define VMCPU_GET_STATE(pVCpu) ( (pVCpu)->enmState )
311	/** Sets the VMCPU state. */
312	#define VMCPU_SET_STATE(pVCpu, enmNewState) \
313	ASMAtomicWriteU32((uint32_t volatile *)&(pVCpu)->enmState, (enmNewState))
314	/** Cmpares and sets the VMCPU state. */
315	#define VMCPU_CMPXCHG_STATE(pVCpu, enmNewState, enmOldState) \
316	ASMAtomicCmpXchgU32((uint32_t volatile *)&(pVCpu)->enmState, (enmNewState), (enmOldState))
317	/** Checks the VMCPU state. */
318	#ifdef VBOX_STRICT
319	# define VMCPU_ASSERT_STATE(pVCpu, enmExpectedState) \
320	do { \
321	VMCPUSTATE enmState = VMCPU_GET_STATE(pVCpu); \
322	AssertMsg(enmState == (enmExpectedState), \
323	("enmState=%d enmExpectedState=%d idCpu=%u\n", \
324	enmState, enmExpectedState, (pVCpu)->idCpu)); \
325	} while (0)
326	#else
327	# define VMCPU_ASSERT_STATE(pVCpu, enmExpectedState) do { } while (0)
328	#endif
329	/** Tests if the state means that the CPU is started. */
330	#define VMCPUSTATE_IS_STARTED(enmState) ( (enmState) > VMCPUSTATE_STOPPED )
331	/** Tests if the state means that the CPU is stopped. */
332	#define VMCPUSTATE_IS_STOPPED(enmState) ( (enmState) == VMCPUSTATE_STOPPED )
333	/** @} */
334
335
336	/** The name of the raw-mode context VMM Core module. */
337	#define VMMRC_MAIN_MODULE_NAME "VMMRC.rc"
338	/** The name of the ring-0 context VMM Core module. */
339	#define VMMR0_MAIN_MODULE_NAME "VMMR0.r0"
340
341	/**
342	* Wrapper macro for avoiding too much \#ifdef VBOX_WITH_RAW_MODE.
343	*/
344	#ifdef VBOX_WITH_RAW_MODE
345	# define VM_WHEN_RAW_MODE(a_WithExpr, a_WithoutExpr) a_WithExpr
346	#else
347	# define VM_WHEN_RAW_MODE(a_WithExpr, a_WithoutExpr) a_WithoutExpr
348	#endif
349
350
351	/** VM Forced Action Flags.
352	*
353	* Use the VM_FF_SET() and VM_FF_CLEAR() macros to change the force
354	* action mask of a VM.
355	*
356	* Available VM bits:
357	* 0, 1, 5, 6, 7, 13, 14, 15, 16, 17, 21, 22, 23, 24, 25, 26, 27, 28, 30
358	*
359	*
360	* Available VMCPU bits:
361	* 14, 15
362	*
363	* @todo If we run low on VMCPU, we may consider merging the SELM bits
364	*
365	* @{
366	*/
367	/** The virtual sync clock has been stopped, go to TM until it has been
368	* restarted... */
369	#define VM_FF_TM_VIRTUAL_SYNC RT_BIT_32(VM_FF_TM_VIRTUAL_SYNC_BIT)
370	#define VM_FF_TM_VIRTUAL_SYNC_BIT 2
371	/** PDM Queues are pending. */
372	#define VM_FF_PDM_QUEUES RT_BIT_32(VM_FF_PDM_QUEUES_BIT)
373	/** The bit number for VM_FF_PDM_QUEUES. */
374	#define VM_FF_PDM_QUEUES_BIT 3
375	/** PDM DMA transfers are pending. */
376	#define VM_FF_PDM_DMA RT_BIT_32(VM_FF_PDM_DMA_BIT)
377	/** The bit number for VM_FF_PDM_DMA. */
378	#define VM_FF_PDM_DMA_BIT 4
379	/** This action forces the VM to call DBGF so DBGF can service debugger
380	* requests in the emulation thread.
381	* This action flag stays asserted till DBGF clears it.*/
382	#define VM_FF_DBGF RT_BIT_32(VM_FF_DBGF_BIT)
383	/** The bit number for VM_FF_DBGF. */
384	#define VM_FF_DBGF_BIT 8
385	/** This action forces the VM to service pending requests from other
386	* thread or requests which must be executed in another context. */
387	#define VM_FF_REQUEST RT_BIT_32(VM_FF_REQUEST_BIT)
388	#define VM_FF_REQUEST_BIT 9
389	/** Check for VM state changes and take appropriate action. */
390	#define VM_FF_CHECK_VM_STATE RT_BIT_32(VM_FF_CHECK_VM_STATE_BIT)
391	/** The bit number for VM_FF_CHECK_VM_STATE. */
392	#define VM_FF_CHECK_VM_STATE_BIT 10
393	/** Reset the VM. (postponed) */
394	#define VM_FF_RESET RT_BIT_32(VM_FF_RESET_BIT)
395	/** The bit number for VM_FF_RESET. */
396	#define VM_FF_RESET_BIT 11
397	/** EMT rendezvous in VMM. */
398	#define VM_FF_EMT_RENDEZVOUS RT_BIT_32(VM_FF_EMT_RENDEZVOUS_BIT)
399	/** The bit number for VM_FF_EMT_RENDEZVOUS. */
400	#define VM_FF_EMT_RENDEZVOUS_BIT 12
401
402	/** PGM needs to allocate handy pages. */
403	#define VM_FF_PGM_NEED_HANDY_PAGES RT_BIT_32(VM_FF_PGM_NEED_HANDY_PAGES_BIT)
404	#define VM_FF_PGM_NEED_HANDY_PAGES_BIT 18
405	/** PGM is out of memory.
406	* Abandon all loops and code paths which can be resumed and get up to the EM
407	* loops. */
408	#define VM_FF_PGM_NO_MEMORY RT_BIT_32(VM_FF_PGM_NO_MEMORY_BIT)
409	#define VM_FF_PGM_NO_MEMORY_BIT 19
410	/** PGM is about to perform a lightweight pool flush
411	* Guest SMP: all EMT threads should return to ring 3
412	*/
413	#define VM_FF_PGM_POOL_FLUSH_PENDING RT_BIT_32(VM_FF_PGM_POOL_FLUSH_PENDING_BIT)
414	#define VM_FF_PGM_POOL_FLUSH_PENDING_BIT 20
415	/** REM needs to be informed about handler changes. */
416	#define VM_FF_REM_HANDLER_NOTIFY RT_BIT_32(VM_FF_REM_HANDLER_NOTIFY_BIT)
417	/** The bit number for VM_FF_REM_HANDLER_NOTIFY. */
418	#define VM_FF_REM_HANDLER_NOTIFY_BIT 29
419	/** Suspend the VM - debug only. */
420	#define VM_FF_DEBUG_SUSPEND RT_BIT_32(VM_FF_DEBUG_SUSPEND_BIT)
421	#define VM_FF_DEBUG_SUSPEND_BIT 31
422
423
424	/** This action forces the VM to check any pending interrupts on the APIC. */
425	#define VMCPU_FF_INTERRUPT_APIC RT_BIT_32(VMCPU_FF_INTERRUPT_APIC_BIT)
426	#define VMCPU_FF_INTERRUPT_APIC_BIT 0
427	/** This action forces the VM to check any pending interrups on the PIC. */
428	#define VMCPU_FF_INTERRUPT_PIC RT_BIT_32(VMCPU_FF_INTERRUPT_PIC_BIT)
429	#define VMCPU_FF_INTERRUPT_PIC_BIT 1
430	/** This action forces the VM to schedule and run pending timer (TM).
431	* @remarks Don't move - PATM compatibility. */
432	#define VMCPU_FF_TIMER RT_BIT_32(VMCPU_FF_TIMER_BIT)
433	#define VMCPU_FF_TIMER_BIT 2
434	/** This action forces the VM to check any pending NMIs. */
435	#define VMCPU_FF_INTERRUPT_NMI RT_BIT_32(VMCPU_FF_INTERRUPT_NMI_BIT)
436	#define VMCPU_FF_INTERRUPT_NMI_BIT 3
437	/** This action forces the VM to check any pending SMIs. */
438	#define VMCPU_FF_INTERRUPT_SMI RT_BIT_32(VMCPU_FF_INTERRUPT_SMI_BIT)
439	#define VMCPU_FF_INTERRUPT_SMI_BIT 4
440	/** PDM critical section unlocking is pending, process promptly upon return to R3. */
441	#define VMCPU_FF_PDM_CRITSECT RT_BIT_32(VMCPU_FF_PDM_CRITSECT_BIT)
442	#define VMCPU_FF_PDM_CRITSECT_BIT 5
443	/** Special EM internal force flag that is used by EMUnhaltAndWakeUp() to force
444	* the virtual CPU out of the next (/current) halted state. It is not processed
445	* nor cleared by emR3ForcedActions (similar to VMCPU_FF_BLOCK_NMIS), instead it
446	* is cleared the next time EM leaves the HALTED state. */
447	#define VMCPU_FF_UNHALT RT_BIT_32(VMCPU_FF_UNHALT_BIT)
448	#define VMCPU_FF_UNHALT_BIT 6
449	/** Pending IEM action (mask). */
450	#define VMCPU_FF_IEM RT_BIT_32(VMCPU_FF_IEM_BIT)
451	/** Pending IEM action (bit number). */
452	#define VMCPU_FF_IEM_BIT 7
453	/** Pending APIC action (bit number). */
454	#define VMCPU_FF_UPDATE_APIC_BIT 8
455	/** This action forces the VM to update APIC's asynchronously arrived
456	* interrupts as pending interrupts. */
457	#define VMCPU_FF_UPDATE_APIC RT_BIT_32(VMCPU_FF_UPDATE_APIC_BIT)
458	/** This action forces the VM to service pending requests from other
459	* thread or requests which must be executed in another context. */
460	#define VMCPU_FF_REQUEST RT_BIT_32(VMCPU_FF_REQUEST_BIT)
461	#define VMCPU_FF_REQUEST_BIT 9
462	/** Pending DBGF event (alternative to passing VINF_EM_DBG_EVENT around). */
463	#define VMCPU_FF_DBGF RT_BIT_32(VMCPU_FF_DBGF_BIT)
464	/** The bit number for VMCPU_FF_DBGF. */
465	#define VMCPU_FF_DBGF_BIT 10
466	/** Pending MTF (Monitor Trap Flag) event - Intel only. */
467	#define VMCPU_FF_MTF RT_BIT_32(VMCPU_FF_MTF_BIT)
468	/** The bit number for VMCPU_FF_MTF. */
469	#define VMCPU_FF_MTF_BIT 11
470	/** This action forces the VM to service any pending updates to CR3 (used only
471	* by HM). */
472	#define VMCPU_FF_HM_UPDATE_CR3 RT_BIT_32(VMCPU_FF_HM_UPDATE_CR3_BIT)
473	#define VMCPU_FF_HM_UPDATE_CR3_BIT 12
474	/** This action forces the VM to service any pending updates to PAE PDPEs (used
475	* only by HM). */
476	#define VMCPU_FF_HM_UPDATE_PAE_PDPES RT_BIT_32(VMCPU_FF_HM_UPDATE_PAE_PDPES_BIT)
477	#define VMCPU_FF_HM_UPDATE_PAE_PDPES_BIT 13
478	/** This action forces the VM to resync the page tables before going
479	* back to execute guest code. (GLOBAL FLUSH) */
480	#define VMCPU_FF_PGM_SYNC_CR3 RT_BIT_32(VMCPU_FF_PGM_SYNC_CR3_BIT)
481	#define VMCPU_FF_PGM_SYNC_CR3_BIT 16
482	/** Same as VM_FF_PGM_SYNC_CR3 except that global pages can be skipped.
483	* (NON-GLOBAL FLUSH) */
484	#define VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL RT_BIT_32(VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL_BIT)
485	#define VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL_BIT 17
486	/** Check for pending TLB shootdown actions (deprecated)
487	* Reserved for furture HM re-use if necessary / safe.
488	* Consumer: HM */
489	#define VMCPU_FF_TLB_SHOOTDOWN_UNUSED RT_BIT_32(VMCPU_FF_TLB_SHOOTDOWN_UNUSED_BIT)
490	#define VMCPU_FF_TLB_SHOOTDOWN_UNUSED_BIT 18
491	/** Check for pending TLB flush action.
492	* Consumer: HM
493	* @todo rename to VMCPU_FF_HM_TLB_FLUSH */
494	#define VMCPU_FF_TLB_FLUSH RT_BIT_32(VMCPU_FF_TLB_FLUSH_BIT)
495	/** The bit number for VMCPU_FF_TLB_FLUSH. */
496	#define VMCPU_FF_TLB_FLUSH_BIT 19
497	#ifdef VBOX_WITH_RAW_MODE
498	/** Check the interrupt and trap gates */
499	# define VMCPU_FF_TRPM_SYNC_IDT RT_BIT_32(VMCPU_FF_TRPM_SYNC_IDT_BIT)
500	# define VMCPU_FF_TRPM_SYNC_IDT_BIT 20
501	/** Check Guest's TSS ring 0 stack */
502	# define VMCPU_FF_SELM_SYNC_TSS RT_BIT_32(VMCPU_FF_SELM_SYNC_TSS_BIT)
503	# define VMCPU_FF_SELM_SYNC_TSS_BIT 21
504	/** Check Guest's GDT table */
505	# define VMCPU_FF_SELM_SYNC_GDT RT_BIT_32(VMCPU_FF_SELM_SYNC_GDT_BIT)
506	# define VMCPU_FF_SELM_SYNC_GDT_BIT 22
507	/** Check Guest's LDT table */
508	# define VMCPU_FF_SELM_SYNC_LDT RT_BIT_32(VMCPU_FF_SELM_SYNC_LDT_BIT)
509	# define VMCPU_FF_SELM_SYNC_LDT_BIT 23
510	#endif /* VBOX_WITH_RAW_MODE */
511	/** Inhibit interrupts pending. See EMGetInhibitInterruptsPC(). */
512	#define VMCPU_FF_INHIBIT_INTERRUPTS RT_BIT_32(VMCPU_FF_INHIBIT_INTERRUPTS_BIT)
513	#define VMCPU_FF_INHIBIT_INTERRUPTS_BIT 24
514	/** Block injection of non-maskable interrupts to the guest. */
515	#define VMCPU_FF_BLOCK_NMIS RT_BIT_32(VMCPU_FF_BLOCK_NMIS_BIT)
516	#define VMCPU_FF_BLOCK_NMIS_BIT 25
517	#ifdef VBOX_WITH_RAW_MODE
518	/** CSAM needs to scan the page that's being executed */
519	# define VMCPU_FF_CSAM_SCAN_PAGE RT_BIT_32(VMCPU_FF_CSAM_SCAN_PAGE_BIT)
520	# define VMCPU_FF_CSAM_SCAN_PAGE_BIT 26
521	/** CSAM needs to do some homework. */
522	# define VMCPU_FF_CSAM_PENDING_ACTION RT_BIT_32(VMCPU_FF_CSAM_PENDING_ACTION_BIT)
523	# define VMCPU_FF_CSAM_PENDING_ACTION_BIT 27
524	#endif /* VBOX_WITH_RAW_MODE */
525	/** Force return to Ring-3. */
526	#define VMCPU_FF_TO_R3 RT_BIT_32(VMCPU_FF_TO_R3_BIT)
527	#define VMCPU_FF_TO_R3_BIT 28
528	/** Force return to ring-3 to service pending I/O or MMIO write.
529	* This is a backup for mechanism VINF_IOM_R3_IOPORT_COMMIT_WRITE and
530	* VINF_IOM_R3_MMIO_COMMIT_WRITE, allowing VINF_EM_DBG_BREAKPOINT and similar
531	* status codes to be propagated at the same time without loss. */
532	#define VMCPU_FF_IOM RT_BIT_32(VMCPU_FF_IOM_BIT)
533	#define VMCPU_FF_IOM_BIT 29
534	#ifdef VBOX_WITH_RAW_MODE
535	/** CPUM need to adjust CR0.TS/EM before executing raw-mode code again. */
536	# define VMCPU_FF_CPUM RT_BIT_32(VMCPU_FF_CPUM_BIT)
537	/** The bit number for VMCPU_FF_CPUM. */
538	# define VMCPU_FF_CPUM_BIT 30
539	#endif /* VBOX_WITH_RAW_MODE */
540	/** Hardware virtualized nested-guest interrupt pending. */
541	#define VMCPU_FF_INTERRUPT_NESTED_GUEST RT_BIT_32(VMCPU_FF_INTERRUPT_NESTED_GUEST_BIT)
542	#define VMCPU_FF_INTERRUPT_NESTED_GUEST_BIT 31
543
544
545	/** Externally VM forced actions. Used to quit the idle/wait loop. */
546	#define VM_FF_EXTERNAL_SUSPENDED_MASK ( VM_FF_CHECK_VM_STATE \| VM_FF_DBGF \| VM_FF_REQUEST \| VM_FF_EMT_RENDEZVOUS )
547	/** Externally VMCPU forced actions. Used to quit the idle/wait loop. */
548	#define VMCPU_FF_EXTERNAL_SUSPENDED_MASK ( VMCPU_FF_REQUEST \| VMCPU_FF_DBGF )
549
550	/** Externally forced VM actions. Used to quit the idle/wait loop. */
551	#define VM_FF_EXTERNAL_HALTED_MASK ( VM_FF_CHECK_VM_STATE \| VM_FF_DBGF \| VM_FF_REQUEST \
552	\| VM_FF_PDM_QUEUES \| VM_FF_PDM_DMA \| VM_FF_EMT_RENDEZVOUS )
553	/** Externally forced VMCPU actions. Used to quit the idle/wait loop. */
554	#define VMCPU_FF_EXTERNAL_HALTED_MASK ( VMCPU_FF_UPDATE_APIC \| VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC \
555	\| VMCPU_FF_REQUEST \| VMCPU_FF_INTERRUPT_NMI \| VMCPU_FF_INTERRUPT_SMI \
556	\| VMCPU_FF_UNHALT \| VMCPU_FF_TIMER \| VMCPU_FF_DBGF )
557
558	/** High priority VM pre-execution actions. */
559	#define VM_FF_HIGH_PRIORITY_PRE_MASK ( VM_FF_CHECK_VM_STATE \| VM_FF_DBGF \| VM_FF_TM_VIRTUAL_SYNC \
560	\| VM_FF_DEBUG_SUSPEND \| VM_FF_PGM_NEED_HANDY_PAGES \| VM_FF_PGM_NO_MEMORY \
561	\| VM_FF_EMT_RENDEZVOUS )
562	/** High priority VMCPU pre-execution actions. */
563	#define VMCPU_FF_HIGH_PRIORITY_PRE_MASK ( VMCPU_FF_TIMER \| VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC \
564	\| VMCPU_FF_UPDATE_APIC \| VMCPU_FF_INHIBIT_INTERRUPTS \| VMCPU_FF_DBGF \
565	\| VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL \
566	\| VM_WHEN_RAW_MODE( VMCPU_FF_SELM_SYNC_TSS \| VMCPU_FF_TRPM_SYNC_IDT \
567	\| VMCPU_FF_SELM_SYNC_GDT \| VMCPU_FF_SELM_SYNC_LDT, 0 ) )
568
569	/** High priority VM pre raw-mode execution mask. */
570	#define VM_FF_HIGH_PRIORITY_PRE_RAW_MASK ( VM_FF_PGM_NEED_HANDY_PAGES \| VM_FF_PGM_NO_MEMORY )
571	/** High priority VMCPU pre raw-mode execution mask. */
572	#define VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK ( VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL \
573	\| VMCPU_FF_INHIBIT_INTERRUPTS \
574	\| VM_WHEN_RAW_MODE( VMCPU_FF_SELM_SYNC_TSS \| VMCPU_FF_TRPM_SYNC_IDT \
575	\| VMCPU_FF_SELM_SYNC_GDT \| VMCPU_FF_SELM_SYNC_LDT, 0) )
576
577	/** High priority post-execution actions. */
578	#define VM_FF_HIGH_PRIORITY_POST_MASK ( VM_FF_PGM_NO_MEMORY )
579	/** High priority post-execution actions. */
580	#define VMCPU_FF_HIGH_PRIORITY_POST_MASK ( VMCPU_FF_PDM_CRITSECT \| VM_WHEN_RAW_MODE(VMCPU_FF_CSAM_PENDING_ACTION, 0) \
581	\| VMCPU_FF_HM_UPDATE_CR3 \| VMCPU_FF_HM_UPDATE_PAE_PDPES \
582	\| VMCPU_FF_IEM \| VMCPU_FF_IOM )
583
584	/** Normal priority VM post-execution actions. */
585	#define VM_FF_NORMAL_PRIORITY_POST_MASK ( VM_FF_CHECK_VM_STATE \| VM_FF_DBGF \| VM_FF_RESET \
586	\| VM_FF_PGM_NO_MEMORY \| VM_FF_EMT_RENDEZVOUS)
587	/** Normal priority VMCPU post-execution actions. */
588	#define VMCPU_FF_NORMAL_PRIORITY_POST_MASK ( VM_WHEN_RAW_MODE(VMCPU_FF_CSAM_SCAN_PAGE, 0) \| VMCPU_FF_DBGF )
589
590	/** Normal priority VM actions. */
591	#define VM_FF_NORMAL_PRIORITY_MASK ( VM_FF_REQUEST \| VM_FF_PDM_QUEUES \| VM_FF_PDM_DMA \
592	\| VM_FF_REM_HANDLER_NOTIFY \| VM_FF_EMT_RENDEZVOUS)
593	/** Normal priority VMCPU actions. */
594	#define VMCPU_FF_NORMAL_PRIORITY_MASK ( VMCPU_FF_REQUEST )
595
596	/** Flags to clear before resuming guest execution. */
597	#define VMCPU_FF_RESUME_GUEST_MASK ( VMCPU_FF_TO_R3 )
598
599
600	/** VM flags that cause the REP[\|NE\|E] STRINS loops to yield immediately. */
601	#define VM_FF_HIGH_PRIORITY_POST_REPSTR_MASK ( VM_FF_TM_VIRTUAL_SYNC \| VM_FF_PGM_NEED_HANDY_PAGES \| VM_FF_PGM_NO_MEMORY \
602	\| VM_FF_EMT_RENDEZVOUS \| VM_FF_PGM_POOL_FLUSH_PENDING \| VM_FF_RESET)
603	/** VM flags that cause the REP[\|NE\|E] STRINS loops to yield. */
604	#define VM_FF_YIELD_REPSTR_MASK ( VM_FF_HIGH_PRIORITY_POST_REPSTR_MASK \
605	\| VM_FF_PDM_QUEUES \| VM_FF_PDM_DMA \| VM_FF_DBGF \| VM_FF_DEBUG_SUSPEND )
606	/** VMCPU flags that cause the REP[\|NE\|E] STRINS loops to yield immediately. */
607	#ifdef IN_RING3
608	# define VMCPU_FF_HIGH_PRIORITY_POST_REPSTR_MASK ( VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL \| VMCPU_FF_DBGF )
609	#else
610	# define VMCPU_FF_HIGH_PRIORITY_POST_REPSTR_MASK ( VMCPU_FF_TO_R3 \| VMCPU_FF_IEM \| VMCPU_FF_IOM \| VMCPU_FF_PGM_SYNC_CR3 \
611	\| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL \| VMCPU_FF_DBGF )
612	#endif
613	/** VMCPU flags that cause the REP[\|NE\|E] STRINS loops to yield, interrupts
614	* enabled. */
615	#define VMCPU_FF_YIELD_REPSTR_MASK ( VMCPU_FF_HIGH_PRIORITY_POST_REPSTR_MASK \
616	\| VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_UPDATE_APIC \| VMCPU_FF_INTERRUPT_PIC \
617	\| VMCPU_FF_INTERRUPT_NMI \| VMCPU_FF_INTERRUPT_SMI \| VMCPU_FF_PDM_CRITSECT \
618	\| VMCPU_FF_TIMER \| VMCPU_FF_REQUEST )
619	/** VMCPU flags that cause the REP[\|NE\|E] STRINS loops to yield, interrupts
620	* disabled. */
621	#define VMCPU_FF_YIELD_REPSTR_NOINT_MASK ( VMCPU_FF_YIELD_REPSTR_MASK \
622	& ~(VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_UPDATE_APIC \| VMCPU_FF_INTERRUPT_PIC) )
623
624	/** VM Flags that cause the HM loops to go back to ring-3. */
625	#define VM_FF_HM_TO_R3_MASK ( VM_FF_TM_VIRTUAL_SYNC \| VM_FF_PGM_NEED_HANDY_PAGES \| VM_FF_PGM_NO_MEMORY \
626	\| VM_FF_PDM_QUEUES \| VM_FF_EMT_RENDEZVOUS)
627	/** VMCPU Flags that cause the HM loops to go back to ring-3. */
628	#define VMCPU_FF_HM_TO_R3_MASK ( VMCPU_FF_TO_R3 \| VMCPU_FF_TIMER \| VMCPU_FF_PDM_CRITSECT \
629	\| VMCPU_FF_IEM \| VMCPU_FF_IOM)
630
631	/** High priority ring-0 VM pre HM-mode execution mask. */
632	#define VM_FF_HP_R0_PRE_HM_MASK (VM_FF_HM_TO_R3_MASK \| VM_FF_REQUEST \| VM_FF_PGM_POOL_FLUSH_PENDING \| VM_FF_PDM_DMA)
633	/** High priority ring-0 VMCPU pre HM-mode execution mask. */
634	#define VMCPU_FF_HP_R0_PRE_HM_MASK ( VMCPU_FF_HM_TO_R3_MASK \| VMCPU_FF_PGM_SYNC_CR3 \
635	\| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL \| VMCPU_FF_REQUEST)
636	/** High priority ring-0 VM pre HM-mode execution mask, single stepping. */
637	#define VM_FF_HP_R0_PRE_HM_STEP_MASK (VM_FF_HP_R0_PRE_HM_MASK & ~( VM_FF_TM_VIRTUAL_SYNC \| VM_FF_PDM_QUEUES \
638	\| VM_FF_EMT_RENDEZVOUS \| VM_FF_REQUEST \
639	\| VM_FF_PDM_DMA) )
640	/** High priority ring-0 VMCPU pre HM-mode execution mask, single stepping. */
641	#define VMCPU_FF_HP_R0_PRE_HM_STEP_MASK (VMCPU_FF_HP_R0_PRE_HM_MASK & ~( VMCPU_FF_TO_R3 \| VMCPU_FF_TIMER \
642	\| VMCPU_FF_PDM_CRITSECT \| VMCPU_FF_REQUEST) )
643
644	/** All the forced VM flags. */
645	#define VM_FF_ALL_MASK (UINT32_MAX)
646	/** All the forced VMCPU flags. */
647	#define VMCPU_FF_ALL_MASK (UINT32_MAX)
648
649	/** All the forced VM flags except those related to raw-mode and hardware
650	* assisted execution. */
651	#define VM_FF_ALL_REM_MASK (~(VM_FF_HIGH_PRIORITY_PRE_RAW_MASK) \| VM_FF_PGM_NEED_HANDY_PAGES \| VM_FF_PGM_NO_MEMORY)
652	/** All the forced VMCPU flags except those related to raw-mode and hardware
653	* assisted execution. */
654	#define VMCPU_FF_ALL_REM_MASK (~( VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK \| VMCPU_FF_PDM_CRITSECT \
655	\| VMCPU_FF_TLB_FLUSH \| VM_WHEN_RAW_MODE(VMCPU_FF_CSAM_PENDING_ACTION, 0) ))
656	/** @} */
657
658	/** @def VM_FF_SET
659	* Sets a single force action flag.
660	*
661	* @param pVM The cross context VM structure.
662	* @param fFlag The flag to set.
663	*/
664	#define VM_FF_SET(pVM, fFlag) do { \
665	AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
666	AssertCompile((fFlag) == RT_BIT_32(fFlag##_BIT)); \
667	ASMAtomicOrU32(&(pVM)->fGlobalForcedActions, (fFlag)); \
668	} while (0)
669
670	/** @def VMCPU_FF_SET
671	* Sets a single force action flag for the given VCPU.
672	*
673	* @param pVCpu The cross context virtual CPU structure.
674	* @param fFlag The flag to set.
675	* @sa VMCPU_FF_SET_MASK
676	*/
677	#define VMCPU_FF_SET(pVCpu, fFlag) do { \
678	AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
679	AssertCompile((fFlag) == RT_BIT_32(fFlag##_BIT)); \
680	ASMAtomicOrU32(&(pVCpu)->fLocalForcedActions, (fFlag)); \
681	} while (0)
682
683	/** @def VMCPU_FF_SET_MASK
684	* Sets a two or more force action flag for the given VCPU.
685	*
686	* @param pVCpu The cross context virtual CPU structure.
687	* @param fFlags The flags to set.
688	* @sa VMCPU_FF_SET
689	*/
690	#define VMCPU_FF_SET_MASK(a_pVCpu, fFlags) \
691	do { ASMAtomicOrU32(&a_pVCpu->fLocalForcedActions, (fFlags)); } while (0)
692
693	/** @def VM_FF_CLEAR
694	* Clears a single force action flag.
695	*
696	* @param pVM The cross context VM structure.
697	* @param fFlag The flag to clear.
698	*/
699	#define VM_FF_CLEAR(pVM, fFlag) do { \
700	AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
701	AssertCompile((fFlag) == RT_BIT_32(fFlag##_BIT)); \
702	ASMAtomicAndU32(&(pVM)->fGlobalForcedActions, ~(fFlag)); \
703	} while (0)
704
705	/** @def VMCPU_FF_CLEAR
706	* Clears a single force action flag for the given VCPU.
707	*
708	* @param pVCpu The cross context virtual CPU structure.
709	* @param fFlag The flag to clear.
710	*/
711	#define VMCPU_FF_CLEAR(pVCpu, fFlag) do { \
712	AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
713	AssertCompile((fFlag) == RT_BIT_32(fFlag##_BIT)); \
714	ASMAtomicAndU32(&(pVCpu)->fLocalForcedActions, ~(fFlag)); \
715	} while (0)
716
717	/** @def VMCPU_FF_CLEAR_MASK
718	* Clears two or more force action flags for the given VCPU.
719	*
720	* @param pVCpu The cross context virtual CPU structure.
721	* @param fFlags The flags to clear.
722	*/
723	#define VMCPU_FF_CLEAR_MASK(pVCpu, fFlags) \
724	do { ASMAtomicAndU32(&(pVCpu)->fLocalForcedActions, ~(fFlags)); } while (0)
725
726	/** @def VM_FF_IS_SET
727	* Checks if single a force action flag is set.
728	*
729	* @param pVM The cross context VM structure.
730	* @param fFlag The flag to check.
731	* @sa VM_FF_IS_ANY_SET
732	*/
733	#if !defined(VBOX_STRICT) \|\| !defined(RT_COMPILER_SUPPORTS_LAMBDA)
734	# define VM_FF_IS_SET(pVM, fFlag) (((pVM)->fGlobalForcedActions & (fFlag)) == (fFlag))
735	#else
736	# define VM_FF_IS_SET(pVM, fFlag) \
737	([](PVM a_pVM) -> bool \
738	{ \
739	AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
740	AssertCompile((fFlag) == RT_BIT_32(fFlag##_BIT)); \
741	return (a_pVM->fGlobalForcedActions & (fFlag)) == (fFlag); \
742	}(pVM))
743	#endif
744
745	/** @def VMCPU_FF_IS_SET
746	* Checks if a single force action flag is set for the given VCPU.
747	*
748	* @param pVCpu The cross context virtual CPU structure.
749	* @param fFlag The flag to check.
750	* @sa VMCPU_FF_IS_ANY_SET
751	*/
752	#if !defined(VBOX_STRICT) \|\| !defined(RT_COMPILER_SUPPORTS_LAMBDA)
753	# define VMCPU_FF_IS_SET(pVCpu, fFlag) (((pVCpu)->fLocalForcedActions & (fFlag)) == (fFlag))
754	#else
755	# define VMCPU_FF_IS_SET(pVCpu, fFlag) \
756	([](PVMCPU a_pVCpu) -> bool \
757	{ \
758	AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
759	AssertCompile((fFlag) == RT_BIT_32(fFlag##_BIT)); \
760	return (a_pVCpu->fLocalForcedActions & (fFlag)) == (fFlag); \
761	}(pVCpu))
762	#endif
763
764	/** @def VM_FF_IS_ANY_SET
765	* Checks if one or more force action in the specified set is pending.
766	*
767	* @param pVM The cross context VM structure.
768	* @param fFlags The flags to check for.
769	* @sa VM_FF_IS_SET
770	*/
771	#define VM_FF_IS_ANY_SET(pVM, fFlags) RT_BOOL((pVM)->fGlobalForcedActions & (fFlags))
772
773	/** @def VMCPU_FF_IS_ANY_SET
774	* Checks if two or more force action flags in the specified set is set for the given VCPU.
775	*
776	* @param pVCpu The cross context virtual CPU structure.
777	* @param fFlags The flags to check for.
778	* @sa VMCPU_FF_IS_SET
779	*/
780	#define VMCPU_FF_IS_ANY_SET(pVCpu, fFlags) RT_BOOL((pVCpu)->fLocalForcedActions & (fFlags))
781
782	/** @def VM_FF_TEST_AND_CLEAR
783	* Checks if one (!) force action in the specified set is pending and clears it atomically
784	*
785	* @returns true if the bit was set.
786	* @returns false if the bit was clear.
787	* @param pVM The cross context VM structure.
788	* @param fFlag Flag constant to check and clear (_BIT is appended).
789	*/
790	#define VM_FF_TEST_AND_CLEAR(pVM, fFlag) (ASMAtomicBitTestAndClear(&(pVM)->fGlobalForcedActions, fFlag##_BIT))
791
792	/** @def VMCPU_FF_TEST_AND_CLEAR
793	* Checks if one (!) force action in the specified set is pending and clears it atomically
794	*
795	* @returns true if the bit was set.
796	* @returns false if the bit was clear.
797	* @param pVCpu The cross context virtual CPU structure.
798	* @param fFlag Flag constant to check and clear (_BIT is appended).
799	*/
800	#define VMCPU_FF_TEST_AND_CLEAR(pVCpu, fFlag) (ASMAtomicBitTestAndClear(&(pVCpu)->fLocalForcedActions, fFlag##_BIT))
801
802	/** @def VM_FF_IS_PENDING_EXCEPT
803	* Checks if one or more force action in the specified set is pending while one
804	* or more other ones are not.
805	*
806	* @param pVM The cross context VM structure.
807	* @param fFlags The flags to check for.
808	* @param fExcpt The flags that should not be set.
809	*/
810	#define VM_FF_IS_PENDING_EXCEPT(pVM, fFlags, fExcpt) \
811	( ((pVM)->fGlobalForcedActions & (fFlags)) && !((pVM)->fGlobalForcedActions & (fExcpt)) )
812
813	/** @def VM_IS_EMT
814	* Checks if the current thread is the emulation thread (EMT).
815	*
816	* @remark The ring-0 variation will need attention if we expand the ring-0
817	* code to let threads other than EMT mess around with the VM.
818	*/
819	#ifdef IN_RC
820	# define VM_IS_EMT(pVM) true
821	#else
822	# define VM_IS_EMT(pVM) (VMMGetCpu(pVM) != NULL)
823	#endif
824
825	/** @def VMCPU_IS_EMT
826	* Checks if the current thread is the emulation thread (EMT) for the specified
827	* virtual CPU.
828	*/
829	#ifdef IN_RC
830	# define VMCPU_IS_EMT(pVCpu) true
831	#else
832	# define VMCPU_IS_EMT(pVCpu) ((pVCpu) && ((pVCpu) == VMMGetCpu((pVCpu)->CTX_SUFF(pVM))))
833	#endif
834
835	/** @def VM_ASSERT_EMT
836	* Asserts that the current thread IS the emulation thread (EMT).
837	*/
838	#ifdef IN_RC
839	# define VM_ASSERT_EMT(pVM) Assert(VM_IS_EMT(pVM))
840	#elif defined(IN_RING0)
841	# define VM_ASSERT_EMT(pVM) Assert(VM_IS_EMT(pVM))
842	#else
843	# define VM_ASSERT_EMT(pVM) \
844	AssertMsg(VM_IS_EMT(pVM), \
845	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd\n", RTThreadNativeSelf(), VMR3GetVMCPUNativeThread(pVM)))
846	#endif
847
848	/** @def VMCPU_ASSERT_EMT
849	* Asserts that the current thread IS the emulation thread (EMT) of the
850	* specified virtual CPU.
851	*/
852	#ifdef IN_RC
853	# define VMCPU_ASSERT_EMT(pVCpu) Assert(VMCPU_IS_EMT(pVCpu))
854	#elif defined(IN_RING0)
855	# define VMCPU_ASSERT_EMT(pVCpu) AssertMsg(VMCPU_IS_EMT(pVCpu), \
856	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd idCpu=%u\n", \
857	RTThreadNativeSelf(), (pVCpu) ? (pVCpu)->hNativeThreadR0 : 0, \
858	(pVCpu) ? (pVCpu)->idCpu : 0))
859	#else
860	# define VMCPU_ASSERT_EMT(pVCpu) AssertMsg(VMCPU_IS_EMT(pVCpu), \
861	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd idCpu=%#x\n", \
862	RTThreadNativeSelf(), (pVCpu)->hNativeThread, (pVCpu)->idCpu))
863	#endif
864
865	/** @def VM_ASSERT_EMT_RETURN
866	* Asserts that the current thread IS the emulation thread (EMT) and returns if it isn't.
867	*/
868	#ifdef IN_RC
869	# define VM_ASSERT_EMT_RETURN(pVM, rc) AssertReturn(VM_IS_EMT(pVM), (rc))
870	#elif defined(IN_RING0)
871	# define VM_ASSERT_EMT_RETURN(pVM, rc) AssertReturn(VM_IS_EMT(pVM), (rc))
872	#else
873	# define VM_ASSERT_EMT_RETURN(pVM, rc) \
874	AssertMsgReturn(VM_IS_EMT(pVM), \
875	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd\n", RTThreadNativeSelf(), VMR3GetVMCPUNativeThread(pVM)), \
876	(rc))
877	#endif
878
879	/** @def VMCPU_ASSERT_EMT_RETURN
880	* Asserts that the current thread IS the emulation thread (EMT) and returns if it isn't.
881	*/
882	#ifdef IN_RC
883	# define VMCPU_ASSERT_EMT_RETURN(pVCpu, rc) AssertReturn(VMCPU_IS_EMT(pVCpu), (rc))
884	#elif defined(IN_RING0)
885	# define VMCPU_ASSERT_EMT_RETURN(pVCpu, rc) AssertReturn(VMCPU_IS_EMT(pVCpu), (rc))
886	#else
887	# define VMCPU_ASSERT_EMT_RETURN(pVCpu, rc) \
888	AssertMsgReturn(VMCPU_IS_EMT(pVCpu), \
889	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd idCpu=%#x\n", \
890	RTThreadNativeSelf(), (pVCpu)->hNativeThread, (pVCpu)->idCpu), \
891	(rc))
892	#endif
893
894	/** @def VMCPU_ASSERT_EMT_OR_GURU
895	* Asserts that the current thread IS the emulation thread (EMT) of the
896	* specified virtual CPU.
897	*/
898	#if defined(IN_RC) \|\| defined(IN_RING0)
899	# define VMCPU_ASSERT_EMT_OR_GURU(pVCpu) Assert( VMCPU_IS_EMT(pVCpu) \
900	\|\| pVCpu->CTX_SUFF(pVM)->enmVMState == VMSTATE_GURU_MEDITATION \
901	\|\| pVCpu->CTX_SUFF(pVM)->enmVMState == VMSTATE_GURU_MEDITATION_LS )
902	#else
903	# define VMCPU_ASSERT_EMT_OR_GURU(pVCpu) \
904	AssertMsg( VMCPU_IS_EMT(pVCpu) \
905	\|\| pVCpu->CTX_SUFF(pVM)->enmVMState == VMSTATE_GURU_MEDITATION \
906	\|\| pVCpu->CTX_SUFF(pVM)->enmVMState == VMSTATE_GURU_MEDITATION_LS, \
907	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd idCpu=%#x\n", \
908	RTThreadNativeSelf(), (pVCpu)->hNativeThread, (pVCpu)->idCpu))
909	#endif
910
911	/** @def VMCPU_ASSERT_EMT_OR_NOT_RUNNING
912	* Asserts that the current thread IS the emulation thread (EMT) of the
913	* specified virtual CPU or the VM is not running.
914	*/
915	#if defined(IN_RC) \|\| defined(IN_RING0)
916	# define VMCPU_ASSERT_EMT_OR_NOT_RUNNING(pVCpu) \
917	Assert( VMCPU_IS_EMT(pVCpu) \
918	\|\| !VM_IS_RUNNING_FOR_ASSERTIONS_ONLY((pVCpu)->CTX_SUFF(pVM)) )
919	#else
920	# define VMCPU_ASSERT_EMT_OR_NOT_RUNNING(pVCpu) \
921	AssertMsg( VMCPU_IS_EMT(pVCpu) \
922	\|\| !VM_IS_RUNNING_FOR_ASSERTIONS_ONLY((pVCpu)->CTX_SUFF(pVM)), \
923	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd idCpu=%#x\n", \
924	RTThreadNativeSelf(), (pVCpu)->hNativeThread, (pVCpu)->idCpu))
925	#endif
926
927	/** @def VMSTATE_IS_RUNNING
928	* Checks if the given state indicates a running VM.
929	*/
930	#define VMSTATE_IS_RUNNING(a_enmVMState) \
931	( (enmVMState) == VMSTATE_RUNNING \
932	\|\| (enmVMState) == VMSTATE_RUNNING_LS \
933	\|\| (enmVMState) == VMSTATE_RUNNING_FT )
934
935	/** @def VM_IS_RUNNING_FOR_ASSERTIONS_ONLY
936	* Checks if the VM is running.
937	* @note This is only for pure debug assertions. No AssertReturn or similar!
938	* @sa VMSTATE_IS_RUNNING
939	*/
940	#define VM_IS_RUNNING_FOR_ASSERTIONS_ONLY(pVM) \
941	( (pVM)->enmVMState == VMSTATE_RUNNING \
942	\|\| (pVM)->enmVMState == VMSTATE_RUNNING_LS \
943	\|\| (pVM)->enmVMState == VMSTATE_RUNNING_FT )
944
945	/** @def VM_ASSERT_IS_NOT_RUNNING
946	* Asserts that the VM is not running.
947	*/
948	#if defined(IN_RC) \|\| defined(IN_RING0)
949	#define VM_ASSERT_IS_NOT_RUNNING(pVM) Assert(!VM_IS_RUNNING_FOR_ASSERTIONS_ONLY(pVM))
950	#else
951	#define VM_ASSERT_IS_NOT_RUNNING(pVM) AssertMsg(!VM_IS_RUNNING_FOR_ASSERTIONS_ONLY(pVM), \
952	("VM is running. enmVMState=%d\n", (pVM)->enmVMState))
953	#endif
954
955	/** @def VM_ASSERT_EMT0
956	* Asserts that the current thread IS emulation thread \#0 (EMT0).
957	*/
958	#define VM_ASSERT_EMT0(pVM) VMCPU_ASSERT_EMT(&(pVM)->aCpus[0])
959
960	/** @def VM_ASSERT_EMT0_RETURN
961	* Asserts that the current thread IS emulation thread \#0 (EMT0) and returns if
962	* it isn't.
963	*/
964	#define VM_ASSERT_EMT0_RETURN(pVM, rc) VMCPU_ASSERT_EMT_RETURN(&(pVM)->aCpus[0], (rc))
965
966
967	/**
968	* Asserts that the current thread is NOT the emulation thread.
969	*/
970	#define VM_ASSERT_OTHER_THREAD(pVM) \
971	AssertMsg(!VM_IS_EMT(pVM), ("Not other thread!!\n"))
972
973
974	/** @def VM_ASSERT_STATE
975	* Asserts a certain VM state.
976	*/
977	#define VM_ASSERT_STATE(pVM, _enmState) \
978	AssertMsg((pVM)->enmVMState == (_enmState), \
979	("state %s, expected %s\n", VMGetStateName((pVM)->enmVMState), VMGetStateName(_enmState)))
980
981	/** @def VM_ASSERT_STATE_RETURN
982	* Asserts a certain VM state and returns if it doesn't match.
983	*/
984	#define VM_ASSERT_STATE_RETURN(pVM, _enmState, rc) \
985	AssertMsgReturn((pVM)->enmVMState == (_enmState), \
986	("state %s, expected %s\n", VMGetStateName((pVM)->enmVMState), VMGetStateName(_enmState)), \
987	(rc))
988
989	/** @def VM_IS_VALID_EXT
990	* Asserts a the VM handle is valid for external access, i.e. not being destroy
991	* or terminated. */
992	#define VM_IS_VALID_EXT(pVM) \
993	( RT_VALID_ALIGNED_PTR(pVM, PAGE_SIZE) \
994	&& ( (unsigned)(pVM)->enmVMState < (unsigned)VMSTATE_DESTROYING \
995	\|\| ( (unsigned)(pVM)->enmVMState == (unsigned)VMSTATE_DESTROYING \
996	&& VM_IS_EMT(pVM))) )
997
998	/** @def VM_ASSERT_VALID_EXT_RETURN
999	* Asserts a the VM handle is valid for external access, i.e. not being
1000	* destroy or terminated.
1001	*/
1002	#define VM_ASSERT_VALID_EXT_RETURN(pVM, rc) \
1003	AssertMsgReturn(VM_IS_VALID_EXT(pVM), \
1004	("pVM=%p state %s\n", (pVM), RT_VALID_ALIGNED_PTR(pVM, PAGE_SIZE) \
1005	? VMGetStateName(pVM->enmVMState) : ""), \
1006	(rc))
1007
1008	/** @def VMCPU_ASSERT_VALID_EXT_RETURN
1009	* Asserts a the VMCPU handle is valid for external access, i.e. not being
1010	* destroy or terminated.
1011	*/
1012	#define VMCPU_ASSERT_VALID_EXT_RETURN(pVCpu, rc) \
1013	AssertMsgReturn( RT_VALID_ALIGNED_PTR(pVCpu, 64) \
1014	&& RT_VALID_ALIGNED_PTR((pVCpu)->CTX_SUFF(pVM), PAGE_SIZE) \
1015	&& (unsigned)(pVCpu)->CTX_SUFF(pVM)->enmVMState < (unsigned)VMSTATE_DESTROYING, \
1016	("pVCpu=%p pVM=%p state %s\n", (pVCpu), RT_VALID_ALIGNED_PTR(pVCpu, 64) ? (pVCpu)->CTX_SUFF(pVM) : NULL, \
1017	RT_VALID_ALIGNED_PTR(pVCpu, 64) && RT_VALID_ALIGNED_PTR((pVCpu)->CTX_SUFF(pVM), PAGE_SIZE) \
1018	? VMGetStateName((pVCpu)->pVMR3->enmVMState) : ""), \
1019	(rc))
1020
1021	#endif /* !VBOX_FOR_DTRACE_LIB */
1022
1023
1024	/**
1025	* Helper that HM and NEM uses for safely modifying VM::bMainExecutionEngine.
1026	*
1027	* ONLY HM and NEM MAY USE THIS!
1028	*
1029	* @param a_pVM The cross context VM structure.
1030	* @param a_bValue The new value.
1031	* @internal
1032	*/
1033	#define VM_SET_MAIN_EXECUTION_ENGINE(a_pVM, a_bValue) \
1034	do { \
1035	const_cast<uint8_t >(&(a_pVM)->bMainExecutionEngine) = (a_bValue); \
1036	ASMCompilerBarrier(); /* just to be on the safe side */ \
1037	} while (0)
1038
1039	/**
1040	* Checks whether raw-mode is used.
1041	*
1042	* @retval true if either is used.
1043	* @retval false if software virtualization (raw-mode) is used.
1044	*
1045	* @param a_pVM The cross context VM structure.
1046	* @sa VM_IS_HM_OR_NEM_ENABLED, VM_IS_HM_ENABLED, VM_IS_NEM_ENABLED.
1047	* @internal
1048	*/
1049	#ifdef VBOX_WITH_RAW_MODE
1050	# define VM_IS_RAW_MODE_ENABLED(a_pVM) ((a_pVM)->bMainExecutionEngine == VM_EXEC_ENGINE_RAW_MODE)
1051	#else
1052	# define VM_IS_RAW_MODE_ENABLED(a_pVM) (false)
1053	#endif
1054
1055	/**
1056	* Checks whether HM (VT-x/AMD-V) or NEM is being used by this VM.
1057	*
1058	* @retval true if either is used.
1059	* @retval false if software virtualization (raw-mode) is used.
1060	*
1061	* @param a_pVM The cross context VM structure.
1062	* @sa VM_IS_RAW_MODE_ENABLED, VM_IS_HM_ENABLED, VM_IS_NEM_ENABLED.
1063	* @internal
1064	*/
1065	#define VM_IS_HM_OR_NEM_ENABLED(a_pVM) ((a_pVM)->bMainExecutionEngine != VM_EXEC_ENGINE_RAW_MODE)
1066
1067	/**
1068	* Checks whether HM is being used by this VM.
1069	*
1070	* @retval true if HM (VT-x/AMD-v) is used.
1071	* @retval false if not.
1072	*
1073	* @param a_pVM The cross context VM structure.
1074	* @sa VM_IS_NEM_ENABLED, VM_IS_RAW_MODE_ENABLED, VM_IS_HM_OR_NEM_ENABLED.
1075	* @internal
1076	*/
1077	#define VM_IS_HM_ENABLED(a_pVM) ((a_pVM)->bMainExecutionEngine == VM_EXEC_ENGINE_HW_VIRT)
1078
1079	/**
1080	* Checks whether NEM is being used by this VM.
1081	*
1082	* @retval true if a native hypervisor API is used.
1083	* @retval false if not.
1084	*
1085	* @param a_pVM The cross context VM structure.
1086	* @sa VM_IS_HM_ENABLED, VM_IS_RAW_MODE_ENABLED, VM_IS_HM_OR_NEM_ENABLED.
1087	* @internal
1088	*/
1089	#define VM_IS_NEM_ENABLED(a_pVM) ((a_pVM)->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API)
1090
1091
1092	/**
1093	* The cross context VM structure.
1094	*
1095	* It contains all the VM data which have to be available in all contexts.
1096	* Even if it contains all the data the idea is to use APIs not to modify all
1097	* the members all around the place. Therefore we make use of unions to hide
1098	* everything which isn't local to the current source module. This means we'll
1099	* have to pay a little bit of attention when adding new members to structures
1100	* in the unions and make sure to keep the padding sizes up to date.
1101	*
1102	* Run 'kmk run-struct-tests' (from src/VBox/VMM if you like) after updating!
1103	*/
1104	typedef struct VM
1105	{
1106	/** The state of the VM.
1107	* This field is read only to everyone except the VM and EM. */
1108	VMSTATE volatile enmVMState;
1109	/** Forced action flags.
1110	* See the VM_FF_* \#defines. Updated atomically.
1111	*/
1112	volatile uint32_t fGlobalForcedActions;
1113	/** Pointer to the array of page descriptors for the VM structure allocation. */
1114	R3PTRTYPE(PSUPPAGE) paVMPagesR3;
1115	/** Session handle. For use when calling SUPR0 APIs. */
1116	PSUPDRVSESSION pSession;
1117	/** Pointer to the ring-3 VM structure. */
1118	PUVM pUVM;
1119	/** Ring-3 Host Context VM Pointer. */
1120	R3PTRTYPE(struct VM *) pVMR3;
1121	/** Ring-0 Host Context VM Pointer. */
1122	R0PTRTYPE(struct VM *) pVMR0;
1123	/** Raw-mode Context VM Pointer. */
1124	RCPTRTYPE(struct VM *) pVMRC;
1125
1126	/** The GVM VM handle. Only the GVM should modify this field. */
1127	uint32_t hSelf;
1128	/** Number of virtual CPUs. */
1129	uint32_t cCpus;
1130	/** CPU excution cap (1-100) */
1131	uint32_t uCpuExecutionCap;
1132
1133	/** Size of the VM structure including the VMCPU array. */
1134	uint32_t cbSelf;
1135
1136	/** Offset to the VMCPU array starting from beginning of this structure. */
1137	uint32_t offVMCPU;
1138
1139	/**
1140	* VMMSwitcher assembly entry point returning to host context.
1141	*
1142	* Depending on how the host handles the rc status given in @a eax, this may
1143	* return and let the caller resume whatever it was doing prior to the call.
1144	*
1145	*
1146	* @param eax The return code, register.
1147	* @remark Assume interrupts disabled.
1148	* @remark This method pointer lives here because TRPM needs it.
1149	*/
1150	RTRCPTR pfnVMMRCToHostAsm/(int32_t eax)/;
1151
1152	/**
1153	* VMMSwitcher assembly entry point returning to host context without saving the
1154	* raw-mode context (hyper) registers.
1155	*
1156	* Unlike pfnVMMRC2HCAsm, this will not return to the caller. Instead it
1157	* expects the caller to save a RC context in CPUM where one might return if the
1158	* return code indicate that this is possible.
1159	*
1160	* This method pointer lives here because TRPM needs it.
1161	*
1162	* @param eax The return code, register.
1163	* @remark Assume interrupts disabled.
1164	* @remark This method pointer lives here because TRPM needs it.
1165	*/
1166	RTRCPTR pfnVMMRCToHostAsmNoReturn/(int32_t eax)/;
1167
1168	/** @name Various items that are frequently accessed.
1169	* @{ */
1170	/** The main execution engine, VM_EXEC_ENGINE_XXX.
1171	* This is set early during vmR3InitRing3 by HM or NEM. */
1172	uint8_t const bMainExecutionEngine;
1173
1174	/** Whether to recompile user mode code or run it raw/hm/nem.
1175	* In non-raw-mode both fRecompileUser and fRecompileSupervisor must be set
1176	* to recompiler stuff. */
1177	bool fRecompileUser;
1178	/** Whether to recompile supervisor mode code or run it raw/hm/nem.
1179	* In non-raw-mode both fRecompileUser and fRecompileSupervisor must be set
1180	* to recompiler stuff. */
1181	bool fRecompileSupervisor;
1182	/** Whether raw mode supports ring-1 code or not.
1183	* This will be cleared when not in raw-mode. */
1184	bool fRawRing1Enabled;
1185	/** PATM enabled flag.
1186	* This is placed here for performance reasons.
1187	* This will be cleared when not in raw-mode. */
1188	bool fPATMEnabled;
1189	/** CSAM enabled flag.
1190	* This is placed here for performance reasons.
1191	* This will be cleared when not in raw-mode. */
1192	bool fCSAMEnabled;
1193
1194	/** Hardware VM support is available and enabled.
1195	* Determined very early during init.
1196	* This is placed here for performance reasons.
1197	* @todo obsoleted by bMainExecutionEngine, eliminate. */
1198	bool fHMEnabled;
1199	/** Hardware VM support requires a minimal raw-mode context.
1200	* This is never set on 64-bit hosts, only 32-bit hosts requires it. */
1201	bool fHMNeedRawModeCtx;
1202
1203	/** Set when this VM is the master FT node.
1204	* @todo This doesn't need to be here, FTM should store it in it's own
1205	* structures instead. */
1206	bool fFaultTolerantMaster;
1207	/** Large page enabled flag.
1208	* @todo This doesn't need to be here, PGM should store it in it's own
1209	* structures instead. */
1210	bool fUseLargePages;
1211	/** @} */
1212
1213	/** Alignment padding. */
1214	uint8_t uPadding1[2];
1215
1216	/** @name Debugging
1217	* @{ */
1218	/** Raw-mode Context VM Pointer. */
1219	RCPTRTYPE(RTTRACEBUF) hTraceBufRC;
1220	/** Ring-3 Host Context VM Pointer. */
1221	R3PTRTYPE(RTTRACEBUF) hTraceBufR3;
1222	/** Ring-0 Host Context VM Pointer. */
1223	R0PTRTYPE(RTTRACEBUF) hTraceBufR0;
1224	/** @} */
1225
1226	#if HC_ARCH_BITS == 32
1227	/** Alignment padding. */
1228	uint32_t uPadding2;
1229	#endif
1230
1231	/** @name Switcher statistics (remove)
1232	* @{ */
1233	/** Profiling the total time from Qemu to GC. */
1234	STAMPROFILEADV StatTotalQemuToGC;
1235	/** Profiling the total time from GC to Qemu. */
1236	STAMPROFILEADV StatTotalGCToQemu;
1237	/** Profiling the total time spent in GC. */
1238	STAMPROFILEADV StatTotalInGC;
1239	/** Profiling the total time spent not in Qemu. */
1240	STAMPROFILEADV StatTotalInQemu;
1241	/** Profiling the VMMSwitcher code for going to GC. */
1242	STAMPROFILEADV StatSwitcherToGC;
1243	/** Profiling the VMMSwitcher code for going to HC. */
1244	STAMPROFILEADV StatSwitcherToHC;
1245	STAMPROFILEADV StatSwitcherSaveRegs;
1246	STAMPROFILEADV StatSwitcherSysEnter;
1247	STAMPROFILEADV StatSwitcherDebug;
1248	STAMPROFILEADV StatSwitcherCR0;
1249	STAMPROFILEADV StatSwitcherCR4;
1250	STAMPROFILEADV StatSwitcherJmpCR3;
1251	STAMPROFILEADV StatSwitcherRstrRegs;
1252	STAMPROFILEADV StatSwitcherLgdt;
1253	STAMPROFILEADV StatSwitcherLidt;
1254	STAMPROFILEADV StatSwitcherLldt;
1255	STAMPROFILEADV StatSwitcherTSS;
1256	/** @} */
1257
1258	/** Padding - the unions must be aligned on a 64 bytes boundary and the unions
1259	* must start at the same offset on both 64-bit and 32-bit hosts. */
1260	uint8_t abAlignment3[(HC_ARCH_BITS == 32 ? 24 : 0) + 40];
1261
1262	/** CPUM part. */
1263	union
1264	{
1265	#ifdef ___CPUMInternal_h
1266	struct CPUM s;
1267	#endif
1268	#ifdef ___VBox_vmm_cpum_h
1269	/** Read only info exposed about the host and guest CPUs. */
1270	struct
1271	{
1272	/** Padding for hidden fields. */
1273	uint8_t abHidden0[64];
1274	/** Host CPU feature information. */
1275	CPUMFEATURES HostFeatures;
1276	/** Guest CPU feature information. */
1277	CPUMFEATURES GuestFeatures;
1278	} const ro;
1279	#endif
1280	uint8_t padding[1536]; /* multiple of 64 */
1281	} cpum;
1282
1283	/** VMM part. */
1284	union
1285	{
1286	#ifdef ___VMMInternal_h
1287	struct VMM s;
1288	#endif
1289	uint8_t padding[1600]; /* multiple of 64 */
1290	} vmm;
1291
1292	/** PGM part. */
1293	union
1294	{
1295	#ifdef ___PGMInternal_h
1296	struct PGM s;
1297	#endif
1298	uint8_t padding[40962+6080]; / multiple of 64 */
1299	} pgm;
1300
1301	/** HM part. */
1302	union
1303	{
1304	#ifdef ___HMInternal_h
1305	struct HM s;
1306	#endif
1307	uint8_t padding[5440]; /* multiple of 64 */
1308	} hm;
1309
1310	/** TRPM part. */
1311	union
1312	{
1313	#ifdef ___TRPMInternal_h
1314	struct TRPM s;
1315	#endif
1316	uint8_t padding[5248]; /* multiple of 64 */
1317	} trpm;
1318
1319	/** SELM part. */
1320	union
1321	{
1322	#ifdef ___SELMInternal_h
1323	struct SELM s;
1324	#endif
1325	uint8_t padding[768]; /* multiple of 64 */
1326	} selm;
1327
1328	/** MM part. */
1329	union
1330	{
1331	#ifdef ___MMInternal_h
1332	struct MM s;
1333	#endif
1334	uint8_t padding[192]; /* multiple of 64 */
1335	} mm;
1336
1337	/** PDM part. */
1338	union
1339	{
1340	#ifdef ___PDMInternal_h
1341	struct PDM s;
1342	#endif
1343	uint8_t padding[1920]; /* multiple of 64 */
1344	} pdm;
1345
1346	/** IOM part. */
1347	union
1348	{
1349	#ifdef ___IOMInternal_h
1350	struct IOM s;
1351	#endif
1352	uint8_t padding[896]; /* multiple of 64 */
1353	} iom;
1354
1355	/** EM part. */
1356	union
1357	{
1358	#ifdef ___EMInternal_h
1359	struct EM s;
1360	#endif
1361	uint8_t padding[256]; /* multiple of 64 */
1362	} em;
1363
1364	/** NEM part. */
1365	union
1366	{
1367	#ifdef ___NEMInternal_h
1368	struct NEM s;
1369	#endif
1370	uint8_t padding[128]; /* multiple of 64 */
1371	} nem;
1372
1373	/** TM part. */
1374	union
1375	{
1376	#ifdef ___TMInternal_h
1377	struct TM s;
1378	#endif
1379	uint8_t padding[2496]; /* multiple of 64 */
1380	} tm;
1381
1382	/** DBGF part. */
1383	union
1384	{
1385	#ifdef ___DBGFInternal_h
1386	struct DBGF s;
1387	#endif
1388	#ifdef ___VBox_vmm_dbgf_h
1389	/** Read only info exposed about interrupt breakpoints and selected events. */
1390	struct
1391	{
1392	/** Bitmap of enabled hardware interrupt breakpoints. */
1393	uint32_t bmHardIntBreakpoints[256 / 32];
1394	/** Bitmap of enabled software interrupt breakpoints. */
1395	uint32_t bmSoftIntBreakpoints[256 / 32];
1396	/** Bitmap of selected events.
1397	* This includes non-selectable events too for simplicity, we maintain the
1398	* state for some of these, as it may come in handy. */
1399	uint64_t bmSelectedEvents[(DBGFEVENT_END + 63) / 64];
1400	/** Enabled hardware interrupt breakpoints. */
1401	uint32_t cHardIntBreakpoints;
1402	/** Enabled software interrupt breakpoints. */
1403	uint32_t cSoftIntBreakpoints;
1404	/** The number of selected events. */
1405	uint32_t cSelectedEvents;
1406	/** The number of enabled hardware breakpoints. */
1407	uint8_t cEnabledHwBreakpoints;
1408	/** The number of enabled hardware I/O breakpoints. */
1409	uint8_t cEnabledHwIoBreakpoints;
1410	/** The number of enabled INT3 breakpoints. */
1411	uint8_t cEnabledInt3Breakpoints;
1412	uint8_t abPadding[1]; /*< Unused padding space up for grabs. /
1413	} const ro;
1414	#endif
1415	uint8_t padding[2432]; /* multiple of 64 */
1416	} dbgf;
1417
1418	/** SSM part. */
1419	union
1420	{
1421	#ifdef ___SSMInternal_h
1422	struct SSM s;
1423	#endif
1424	uint8_t padding[128]; /* multiple of 64 */
1425	} ssm;
1426
1427	/** FTM part. */
1428	union
1429	{
1430	#ifdef ___FTMInternal_h
1431	struct FTM s;
1432	#endif
1433	uint8_t padding[512]; /* multiple of 64 */
1434	} ftm;
1435
1436	#ifdef VBOX_WITH_RAW_MODE
1437	/** PATM part. */
1438	union
1439	{
1440	# ifdef ___PATMInternal_h
1441	struct PATM s;
1442	# endif
1443	uint8_t padding[768]; /* multiple of 64 */
1444	} patm;
1445
1446	/** CSAM part. */
1447	union
1448	{
1449	# ifdef ___CSAMInternal_h
1450	struct CSAM s;
1451	# endif
1452	uint8_t padding[1088]; /* multiple of 64 */
1453	} csam;
1454	#endif
1455
1456	#ifdef VBOX_WITH_REM
1457	/** REM part. */
1458	union
1459	{
1460	# ifdef ___REMInternal_h
1461	struct REM s;
1462	# endif
1463	uint8_t padding[0x11100]; /* multiple of 64 */
1464	} rem;
1465	#endif
1466
1467	union
1468	{
1469	#ifdef ___GIMInternal_h
1470	struct GIM s;
1471	#endif
1472	uint8_t padding[448]; /* multiple of 64 */
1473	} gim;
1474
1475	union
1476	{
1477	#ifdef ___APICInternal_h
1478	struct APIC s;
1479	#endif
1480	uint8_t padding[128]; /* multiple of 8 */
1481	} apic;
1482
1483	/* ---- begin small stuff ---- */
1484
1485	/** VM part. */
1486	union
1487	{
1488	#ifdef ___VMInternal_h
1489	struct VMINT s;
1490	#endif
1491	uint8_t padding[32]; /* multiple of 8 */
1492	} vm;
1493
1494	/** CFGM part. */
1495	union
1496	{
1497	#ifdef ___CFGMInternal_h
1498	struct CFGM s;
1499	#endif
1500	uint8_t padding[8]; /* multiple of 8 */
1501	} cfgm;
1502
1503	/** Padding for aligning the cpu array on a page boundary. */
1504	#if defined(VBOX_WITH_REM) && defined(VBOX_WITH_RAW_MODE)
1505	uint8_t abAlignment2[3670];
1506	#elif defined(VBOX_WITH_REM) && !defined(VBOX_WITH_RAW_MODE)
1507	uint8_t abAlignment2[1430];
1508	#elif !defined(VBOX_WITH_REM) && defined(VBOX_WITH_RAW_MODE)
1509	uint8_t abAlignment2[3926];
1510	#else
1511	uint8_t abAlignment2[1686];
1512	#endif
1513
1514	/* ---- end small stuff ---- */
1515
1516	/** VMCPU array for the configured number of virtual CPUs.
1517	* Must be aligned on a page boundary for TLB hit reasons as well as
1518	* alignment of VMCPU members. */
1519	VMCPU aCpus[1];
1520	} VM;
1521
1522
1523	#ifdef IN_RC
1524	RT_C_DECLS_BEGIN
1525
1526	/** The VM structure.
1527	* This is imported from the VMMRCBuiltin module, i.e. it's a one of those magic
1528	* globals which we should avoid using.
1529	*/
1530	extern DECLIMPORT(VM) g_VM;
1531
1532	RT_C_DECLS_END
1533	#endif
1534
1535	/** @} */
1536
1537	#endif
1538

Note: See TracBrowser for help on using the repository browser.

source: vbox/trunk/include/VBox/vmm/vm.h@ 74797

Download in other formats: