vm.h@ 74817

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vm.h: doxygen fix. bugref:9180
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1	/** @file
2	* VM - The Virtual Machine, data.
3	*/
4
5	/*
6	* Copyright (C) 2006-2017 Oracle Corporation
7	*
8	* This file is part of VirtualBox Open Source Edition (OSE), as
9	* available from http://www.virtualbox.org. This file is free software;
10	* you can redistribute it and/or modify it under the terms of the GNU
11	* General Public License (GPL) as published by the Free Software
12	* Foundation, in version 2 as it comes in the "COPYING" file of the
13	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15	*
16	* The contents of this file may alternatively be used under the terms
17	* of the Common Development and Distribution License Version 1.0
18	* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19	* VirtualBox OSE distribution, in which case the provisions of the
20	* CDDL are applicable instead of those of the GPL.
21	*
22	* You may elect to license modified versions of this file under the
23	* terms and conditions of either the GPL or the CDDL or both.
24	*/
25
26	#ifndef ___VBox_vmm_vm_h
27	#define ___VBox_vmm_vm_h
28
29	#ifndef VBOX_FOR_DTRACE_LIB
30	# include <iprt/param.h>
31	# include <VBox/types.h>
32	# include <VBox/vmm/cpum.h>
33	# include <VBox/vmm/stam.h>
34	# include <VBox/vmm/vmapi.h>
35	# include <VBox/vmm/vmm.h>
36	# include <VBox/sup.h>
37	#else
38	# pragma D depends_on library vbox-types.d
39	# pragma D depends_on library CPUMInternal.d
40	# define ___CPUMInternal_h
41	#endif
42
43
44
45	/** @defgroup grp_vm The Virtual Machine
46	* @ingroup grp_vmm
47	* @{
48	*/
49
50	/**
51	* The state of a Virtual CPU.
52	*
53	* The basic state indicated here is whether the CPU has been started or not. In
54	* addition, there are sub-states when started for assisting scheduling (GVMM
55	* mostly).
56	*
57	* The transition out of the STOPPED state is done by a vmR3PowerOn.
58	* The transition back to the STOPPED state is done by vmR3PowerOff.
59	*
60	* (Alternatively we could let vmR3PowerOn start CPU 0 only and let the SPIP
61	* handling switch on the other CPUs. Then vmR3Reset would stop all but CPU 0.)
62	*/
63	typedef enum VMCPUSTATE
64	{
65	/** The customary invalid zero. */
66	VMCPUSTATE_INVALID = 0,
67
68	/** Virtual CPU has not yet been started. */
69	VMCPUSTATE_STOPPED,
70
71	/** CPU started. */
72	VMCPUSTATE_STARTED,
73	/** CPU started in HM context. */
74	VMCPUSTATE_STARTED_HM,
75	/** Executing guest code and can be poked (RC or STI bits of HM). */
76	VMCPUSTATE_STARTED_EXEC,
77	/** Executing guest code in the recompiler. */
78	VMCPUSTATE_STARTED_EXEC_REM,
79	/** Executing guest code using NEM. */
80	VMCPUSTATE_STARTED_EXEC_NEM,
81	VMCPUSTATE_STARTED_EXEC_NEM_WAIT,
82	VMCPUSTATE_STARTED_EXEC_NEM_CANCELED,
83	/** Halted. */
84	VMCPUSTATE_STARTED_HALTED,
85
86	/** The end of valid virtual CPU states. */
87	VMCPUSTATE_END,
88
89	/** Ensure 32-bit type. */
90	VMCPUSTATE_32BIT_HACK = 0x7fffffff
91	} VMCPUSTATE;
92
93
94	/**
95	* The cross context virtual CPU structure.
96	*
97	* Run 'kmk run-struct-tests' (from src/VBox/VMM if you like) after updating!
98	*/
99	typedef struct VMCPU
100	{
101	/** @name Volatile per-cpu data.
102	* @{ */
103	/** Per CPU forced action.
104	* See the VMCPU_FF_* \#defines. Updated atomically. */
105	#ifdef VMCPU_WITH_64_BIT_FFS
106	uint64_t volatile fLocalForcedActions;
107	#else
108	uint32_t volatile fLocalForcedActions;
109	uint32_t fForLocalForcedActionsExpansion;
110	#endif
111	/** The CPU state. */
112	VMCPUSTATE volatile enmState;
113
114	/** Which host CPU ID is this EMT running on.
115	* Only valid when in RC or HMR0 with scheduling disabled. */
116	RTCPUID volatile idHostCpu;
117	/** The CPU set index corresponding to idHostCpu, UINT32_MAX if not valid.
118	* @remarks Best to make sure iHostCpuSet shares cache line with idHostCpu! */
119	uint32_t volatile iHostCpuSet;
120	/** Padding up to 64 bytes. */
121	uint8_t abAlignment0[64 - 20];
122	/** @} */
123
124	/** IEM part.
125	* @remarks This comes first as it allows the use of 8-bit immediates for the
126	* first 64 bytes of the structure, reducing code size a wee bit. */
127	#ifdef ___IEMInternal_h /* For PDB hacking. */
128	union VMCPUUNIONIEMFULL
129	#else
130	union VMCPUUNIONIEMSTUB
131	#endif
132	{
133	#ifdef ___IEMInternal_h
134	struct IEMCPU s;
135	#endif
136	uint8_t padding[18496]; /* multiple of 64 */
137	} iem;
138
139	/** @name Static per-cpu data.
140	* (Putting this after IEM, hoping that it's less frequently used than it.)
141	* @{ */
142	/** The CPU ID.
143	* This is the index into the VM::aCpu array. */
144	VMCPUID idCpu;
145	/** Raw-mode Context VM Pointer. */
146	PVMRC pVMRC;
147	/** Ring-3 Host Context VM Pointer. */
148	PVMR3 pVMR3;
149	/** Ring-0 Host Context VM Pointer. */
150	PVMR0 pVMR0;
151	/** Pointer to the ring-3 UVMCPU structure. */
152	PUVMCPU pUVCpu;
153	/** The native thread handle. */
154	RTNATIVETHREAD hNativeThread;
155	/** The native R0 thread handle. (different from the R3 handle!) */
156	RTNATIVETHREAD hNativeThreadR0;
157	/** Align the structures below bit on a 64-byte boundary and make sure it starts
158	* at the same offset in both 64-bit and 32-bit builds.
159	*
160	* @remarks The alignments of the members that are larger than 48 bytes should be
161	* 64-byte for cache line reasons. structs containing small amounts of
162	* data could be lumped together at the end with a < 64 byte padding
163	* following it (to grow into and align the struct size).
164	*/
165	uint8_t abAlignment1[64 - 4 - 4 - 5 * (HC_ARCH_BITS == 64 ? 8 : 4)];
166	/** @} */
167
168	/** HM part. */
169	union VMCPUUNIONHM
170	{
171	#ifdef ___HMInternal_h
172	struct HMCPU s;
173	#endif
174	uint8_t padding[5888]; /* multiple of 64 */
175	} hm;
176
177	/** NEM part. */
178	union VMCPUUNIONNEM
179	{
180	#ifdef ___NEMInternal_h
181	struct NEMCPU s;
182	#endif
183	uint8_t padding[512]; /* multiple of 64 */
184	} nem;
185
186	/** TRPM part. */
187	union VMCPUUNIONTRPM
188	{
189	#ifdef ___TRPMInternal_h
190	struct TRPMCPU s;
191	#endif
192	uint8_t padding[128]; /* multiple of 64 */
193	} trpm;
194
195	/** TM part. */
196	union VMCPUUNIONTM
197	{
198	#ifdef ___TMInternal_h
199	struct TMCPU s;
200	#endif
201	uint8_t padding[384]; /* multiple of 64 */
202	} tm;
203
204	/** VMM part. */
205	union VMCPUUNIONVMM
206	{
207	#ifdef ___VMMInternal_h
208	struct VMMCPU s;
209	#endif
210	uint8_t padding[768]; /* multiple of 64 */
211	} vmm;
212
213	/** PDM part. */
214	union VMCPUUNIONPDM
215	{
216	#ifdef ___PDMInternal_h
217	struct PDMCPU s;
218	#endif
219	uint8_t padding[256]; /* multiple of 64 */
220	} pdm;
221
222	/** IOM part. */
223	union VMCPUUNIONIOM
224	{
225	#ifdef ___IOMInternal_h
226	struct IOMCPU s;
227	#endif
228	uint8_t padding[512]; /* multiple of 64 */
229	} iom;
230
231	/** DBGF part.
232	* @todo Combine this with other tiny structures. */
233	union VMCPUUNIONDBGF
234	{
235	#ifdef ___DBGFInternal_h
236	struct DBGFCPU s;
237	#endif
238	uint8_t padding[256]; /* multiple of 64 */
239	} dbgf;
240
241	/** GIM part. */
242	union VMCPUUNIONGIM
243	{
244	#ifdef ___GIMInternal_h
245	struct GIMCPU s;
246	#endif
247	uint8_t padding[512]; /* multiple of 64 */
248	} gim;
249
250	/** APIC part. */
251	union VMCPUUNIONAPIC
252	{
253	#ifdef ___APICInternal_h
254	struct APICCPU s;
255	#endif
256	uint8_t padding[1792]; /* multiple of 64 */
257	} apic;
258
259	/*
260	* Some less frequently used global members that doesn't need to take up
261	* precious space at the head of the structure.
262	*/
263
264	/** Trace groups enable flags. */
265	uint32_t fTraceGroups; /* 64 / 44 */
266	/** State data for use by ad hoc profiling. */
267	uint32_t uAdHoc;
268	/** Profiling samples for use by ad hoc profiling. */
269	STAMPROFILEADV aStatAdHoc[8]; /* size: 408 = 320 /
270
271	/** Align the following members on page boundary. */
272	uint8_t abAlignment2[2808];
273
274	/** PGM part. */
275	union VMCPUUNIONPGM
276	{
277	#ifdef ___PGMInternal_h
278	struct PGMCPU s;
279	#endif
280	uint8_t padding[4096]; /* multiple of 4096 */
281	} pgm;
282
283	/** CPUM part. */
284	union VMCPUUNIONCPUM
285	{
286	#ifdef ___CPUMInternal_h
287	struct CPUMCPU s;
288	#endif
289	#ifdef VMCPU_INCL_CPUM_GST_CTX
290	/** The guest CPUM context for direct use by execution engines.
291	* This is not for general consumption, but for HM, REM, IEM, and maybe a few
292	* others. The rest will use the function based CPUM API. */
293	CPUMCTX GstCtx;
294	#endif
295	uint8_t padding[4096]; /* multiple of 4096 */
296	} cpum;
297
298	/** EM part. */
299	union VMCPUUNIONEM
300	{
301	#ifdef ___EMInternal_h
302	struct EMCPU s;
303	#endif
304	uint8_t padding[40960]; /* multiple of 4096 */
305	} em;
306	} VMCPU;
307
308
309	#ifndef VBOX_FOR_DTRACE_LIB
310
311	/** @name Operations on VMCPU::enmState
312	* @{ */
313	/** Gets the VMCPU state. */
314	#define VMCPU_GET_STATE(pVCpu) ( (pVCpu)->enmState )
315	/** Sets the VMCPU state. */
316	#define VMCPU_SET_STATE(pVCpu, enmNewState) \
317	ASMAtomicWriteU32((uint32_t volatile *)&(pVCpu)->enmState, (enmNewState))
318	/** Cmpares and sets the VMCPU state. */
319	#define VMCPU_CMPXCHG_STATE(pVCpu, enmNewState, enmOldState) \
320	ASMAtomicCmpXchgU32((uint32_t volatile *)&(pVCpu)->enmState, (enmNewState), (enmOldState))
321	/** Checks the VMCPU state. */
322	#ifdef VBOX_STRICT
323	# define VMCPU_ASSERT_STATE(pVCpu, enmExpectedState) \
324	do { \
325	VMCPUSTATE enmState = VMCPU_GET_STATE(pVCpu); \
326	AssertMsg(enmState == (enmExpectedState), \
327	("enmState=%d enmExpectedState=%d idCpu=%u\n", \
328	enmState, enmExpectedState, (pVCpu)->idCpu)); \
329	} while (0)
330	#else
331	# define VMCPU_ASSERT_STATE(pVCpu, enmExpectedState) do { } while (0)
332	#endif
333	/** Tests if the state means that the CPU is started. */
334	#define VMCPUSTATE_IS_STARTED(enmState) ( (enmState) > VMCPUSTATE_STOPPED )
335	/** Tests if the state means that the CPU is stopped. */
336	#define VMCPUSTATE_IS_STOPPED(enmState) ( (enmState) == VMCPUSTATE_STOPPED )
337	/** @} */
338
339
340	/** The name of the raw-mode context VMM Core module. */
341	#define VMMRC_MAIN_MODULE_NAME "VMMRC.rc"
342	/** The name of the ring-0 context VMM Core module. */
343	#define VMMR0_MAIN_MODULE_NAME "VMMR0.r0"
344
345	/**
346	* Wrapper macro for avoiding too much \#ifdef VBOX_WITH_RAW_MODE.
347	*/
348	#ifdef VBOX_WITH_RAW_MODE
349	# define VM_WHEN_RAW_MODE(a_WithExpr, a_WithoutExpr) a_WithExpr
350	#else
351	# define VM_WHEN_RAW_MODE(a_WithExpr, a_WithoutExpr) a_WithoutExpr
352	#endif
353
354
355	/** VM Forced Action Flags.
356	*
357	* Use the VM_FF_SET() and VM_FF_CLEAR() macros to change the force
358	* action mask of a VM.
359	*
360	* Available VM bits:
361	* 0, 1, 5, 6, 7, 13, 14, 15, 16, 17, 21, 22, 23, 24, 25, 26, 27, 28, 30
362	*
363	*
364	* Available VMCPU bits:
365	* 14, 15
366	*
367	* @todo If we run low on VMCPU, we may consider merging the SELM bits
368	*
369	* @{
370	*/
371	/** The virtual sync clock has been stopped, go to TM until it has been
372	* restarted... */
373	#define VM_FF_TM_VIRTUAL_SYNC RT_BIT_32(VM_FF_TM_VIRTUAL_SYNC_BIT)
374	#define VM_FF_TM_VIRTUAL_SYNC_BIT 2
375	/** PDM Queues are pending. */
376	#define VM_FF_PDM_QUEUES RT_BIT_32(VM_FF_PDM_QUEUES_BIT)
377	/** The bit number for VM_FF_PDM_QUEUES. */
378	#define VM_FF_PDM_QUEUES_BIT 3
379	/** PDM DMA transfers are pending. */
380	#define VM_FF_PDM_DMA RT_BIT_32(VM_FF_PDM_DMA_BIT)
381	/** The bit number for VM_FF_PDM_DMA. */
382	#define VM_FF_PDM_DMA_BIT 4
383	/** This action forces the VM to call DBGF so DBGF can service debugger
384	* requests in the emulation thread.
385	* This action flag stays asserted till DBGF clears it.*/
386	#define VM_FF_DBGF RT_BIT_32(VM_FF_DBGF_BIT)
387	/** The bit number for VM_FF_DBGF. */
388	#define VM_FF_DBGF_BIT 8
389	/** This action forces the VM to service pending requests from other
390	* thread or requests which must be executed in another context. */
391	#define VM_FF_REQUEST RT_BIT_32(VM_FF_REQUEST_BIT)
392	#define VM_FF_REQUEST_BIT 9
393	/** Check for VM state changes and take appropriate action. */
394	#define VM_FF_CHECK_VM_STATE RT_BIT_32(VM_FF_CHECK_VM_STATE_BIT)
395	/** The bit number for VM_FF_CHECK_VM_STATE. */
396	#define VM_FF_CHECK_VM_STATE_BIT 10
397	/** Reset the VM. (postponed) */
398	#define VM_FF_RESET RT_BIT_32(VM_FF_RESET_BIT)
399	/** The bit number for VM_FF_RESET. */
400	#define VM_FF_RESET_BIT 11
401	/** EMT rendezvous in VMM. */
402	#define VM_FF_EMT_RENDEZVOUS RT_BIT_32(VM_FF_EMT_RENDEZVOUS_BIT)
403	/** The bit number for VM_FF_EMT_RENDEZVOUS. */
404	#define VM_FF_EMT_RENDEZVOUS_BIT 12
405
406	/** PGM needs to allocate handy pages. */
407	#define VM_FF_PGM_NEED_HANDY_PAGES RT_BIT_32(VM_FF_PGM_NEED_HANDY_PAGES_BIT)
408	#define VM_FF_PGM_NEED_HANDY_PAGES_BIT 18
409	/** PGM is out of memory.
410	* Abandon all loops and code paths which can be resumed and get up to the EM
411	* loops. */
412	#define VM_FF_PGM_NO_MEMORY RT_BIT_32(VM_FF_PGM_NO_MEMORY_BIT)
413	#define VM_FF_PGM_NO_MEMORY_BIT 19
414	/** PGM is about to perform a lightweight pool flush
415	* Guest SMP: all EMT threads should return to ring 3
416	*/
417	#define VM_FF_PGM_POOL_FLUSH_PENDING RT_BIT_32(VM_FF_PGM_POOL_FLUSH_PENDING_BIT)
418	#define VM_FF_PGM_POOL_FLUSH_PENDING_BIT 20
419	/** REM needs to be informed about handler changes. */
420	#define VM_FF_REM_HANDLER_NOTIFY RT_BIT_32(VM_FF_REM_HANDLER_NOTIFY_BIT)
421	/** The bit number for VM_FF_REM_HANDLER_NOTIFY. */
422	#define VM_FF_REM_HANDLER_NOTIFY_BIT 29
423	/** Suspend the VM - debug only. */
424	#define VM_FF_DEBUG_SUSPEND RT_BIT_32(VM_FF_DEBUG_SUSPEND_BIT)
425	#define VM_FF_DEBUG_SUSPEND_BIT 31
426
427
428	/** This action forces the VM to check any pending interrupts on the APIC. */
429	#define VMCPU_FF_INTERRUPT_APIC RT_BIT_32(VMCPU_FF_INTERRUPT_APIC_BIT)
430	#define VMCPU_FF_INTERRUPT_APIC_BIT 0
431	/** This action forces the VM to check any pending interrups on the PIC. */
432	#define VMCPU_FF_INTERRUPT_PIC RT_BIT_32(VMCPU_FF_INTERRUPT_PIC_BIT)
433	#define VMCPU_FF_INTERRUPT_PIC_BIT 1
434	/** This action forces the VM to schedule and run pending timer (TM).
435	* @remarks Don't move - PATM compatibility. */
436	#define VMCPU_FF_TIMER RT_BIT_32(VMCPU_FF_TIMER_BIT)
437	#define VMCPU_FF_TIMER_BIT 2
438	/** This action forces the VM to check any pending NMIs. */
439	#define VMCPU_FF_INTERRUPT_NMI RT_BIT_32(VMCPU_FF_INTERRUPT_NMI_BIT)
440	#define VMCPU_FF_INTERRUPT_NMI_BIT 3
441	/** This action forces the VM to check any pending SMIs. */
442	#define VMCPU_FF_INTERRUPT_SMI RT_BIT_32(VMCPU_FF_INTERRUPT_SMI_BIT)
443	#define VMCPU_FF_INTERRUPT_SMI_BIT 4
444	/** PDM critical section unlocking is pending, process promptly upon return to R3. */
445	#define VMCPU_FF_PDM_CRITSECT RT_BIT_32(VMCPU_FF_PDM_CRITSECT_BIT)
446	#define VMCPU_FF_PDM_CRITSECT_BIT 5
447	/** Special EM internal force flag that is used by EMUnhaltAndWakeUp() to force
448	* the virtual CPU out of the next (/current) halted state. It is not processed
449	* nor cleared by emR3ForcedActions (similar to VMCPU_FF_BLOCK_NMIS), instead it
450	* is cleared the next time EM leaves the HALTED state. */
451	#define VMCPU_FF_UNHALT RT_BIT_32(VMCPU_FF_UNHALT_BIT)
452	#define VMCPU_FF_UNHALT_BIT 6
453	/** Pending IEM action (mask). */
454	#define VMCPU_FF_IEM RT_BIT_32(VMCPU_FF_IEM_BIT)
455	/** Pending IEM action (bit number). */
456	#define VMCPU_FF_IEM_BIT 7
457	/** Pending APIC action (bit number). */
458	#define VMCPU_FF_UPDATE_APIC_BIT 8
459	/** This action forces the VM to update APIC's asynchronously arrived
460	* interrupts as pending interrupts. */
461	#define VMCPU_FF_UPDATE_APIC RT_BIT_32(VMCPU_FF_UPDATE_APIC_BIT)
462	/** This action forces the VM to service pending requests from other
463	* thread or requests which must be executed in another context. */
464	#define VMCPU_FF_REQUEST RT_BIT_32(VMCPU_FF_REQUEST_BIT)
465	#define VMCPU_FF_REQUEST_BIT 9
466	/** Pending DBGF event (alternative to passing VINF_EM_DBG_EVENT around). */
467	#define VMCPU_FF_DBGF RT_BIT_32(VMCPU_FF_DBGF_BIT)
468	/** The bit number for VMCPU_FF_DBGF. */
469	#define VMCPU_FF_DBGF_BIT 10
470	/** Pending MTF (Monitor Trap Flag) event - Intel only. */
471	#define VMCPU_FF_MTF RT_BIT_32(VMCPU_FF_MTF_BIT)
472	/** The bit number for VMCPU_FF_MTF. */
473	#define VMCPU_FF_MTF_BIT 11
474	/** This action forces the VM to service any pending updates to CR3 (used only
475	* by HM). */
476	#define VMCPU_FF_HM_UPDATE_CR3 RT_BIT_32(VMCPU_FF_HM_UPDATE_CR3_BIT)
477	#define VMCPU_FF_HM_UPDATE_CR3_BIT 12
478	/** This action forces the VM to service any pending updates to PAE PDPEs (used
479	* only by HM). */
480	#define VMCPU_FF_HM_UPDATE_PAE_PDPES RT_BIT_32(VMCPU_FF_HM_UPDATE_PAE_PDPES_BIT)
481	#define VMCPU_FF_HM_UPDATE_PAE_PDPES_BIT 13
482	/** This action forces the VM to resync the page tables before going
483	* back to execute guest code. (GLOBAL FLUSH) */
484	#define VMCPU_FF_PGM_SYNC_CR3 RT_BIT_32(VMCPU_FF_PGM_SYNC_CR3_BIT)
485	#define VMCPU_FF_PGM_SYNC_CR3_BIT 16
486	/** Same as VM_FF_PGM_SYNC_CR3 except that global pages can be skipped.
487	* (NON-GLOBAL FLUSH) */
488	#define VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL RT_BIT_32(VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL_BIT)
489	#define VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL_BIT 17
490	/** Check for pending TLB shootdown actions (deprecated)
491	* Reserved for furture HM re-use if necessary / safe.
492	* Consumer: HM */
493	#define VMCPU_FF_TLB_SHOOTDOWN_UNUSED RT_BIT_32(VMCPU_FF_TLB_SHOOTDOWN_UNUSED_BIT)
494	#define VMCPU_FF_TLB_SHOOTDOWN_UNUSED_BIT 18
495	/** Check for pending TLB flush action.
496	* Consumer: HM
497	* @todo rename to VMCPU_FF_HM_TLB_FLUSH */
498	#define VMCPU_FF_TLB_FLUSH RT_BIT_32(VMCPU_FF_TLB_FLUSH_BIT)
499	/** The bit number for VMCPU_FF_TLB_FLUSH. */
500	#define VMCPU_FF_TLB_FLUSH_BIT 19
501	#ifdef VBOX_WITH_RAW_MODE
502	/** Check the interrupt and trap gates */
503	# define VMCPU_FF_TRPM_SYNC_IDT RT_BIT_32(VMCPU_FF_TRPM_SYNC_IDT_BIT)
504	# define VMCPU_FF_TRPM_SYNC_IDT_BIT 20
505	/** Check Guest's TSS ring 0 stack */
506	# define VMCPU_FF_SELM_SYNC_TSS RT_BIT_32(VMCPU_FF_SELM_SYNC_TSS_BIT)
507	# define VMCPU_FF_SELM_SYNC_TSS_BIT 21
508	/** Check Guest's GDT table */
509	# define VMCPU_FF_SELM_SYNC_GDT RT_BIT_32(VMCPU_FF_SELM_SYNC_GDT_BIT)
510	# define VMCPU_FF_SELM_SYNC_GDT_BIT 22
511	/** Check Guest's LDT table */
512	# define VMCPU_FF_SELM_SYNC_LDT RT_BIT_32(VMCPU_FF_SELM_SYNC_LDT_BIT)
513	# define VMCPU_FF_SELM_SYNC_LDT_BIT 23
514	#endif /* VBOX_WITH_RAW_MODE */
515	/** Inhibit interrupts pending. See EMGetInhibitInterruptsPC(). */
516	#define VMCPU_FF_INHIBIT_INTERRUPTS RT_BIT_32(VMCPU_FF_INHIBIT_INTERRUPTS_BIT)
517	#define VMCPU_FF_INHIBIT_INTERRUPTS_BIT 24
518	/** Block injection of non-maskable interrupts to the guest. */
519	#define VMCPU_FF_BLOCK_NMIS RT_BIT_32(VMCPU_FF_BLOCK_NMIS_BIT)
520	#define VMCPU_FF_BLOCK_NMIS_BIT 25
521	#ifdef VBOX_WITH_RAW_MODE
522	/** CSAM needs to scan the page that's being executed */
523	# define VMCPU_FF_CSAM_SCAN_PAGE RT_BIT_32(VMCPU_FF_CSAM_SCAN_PAGE_BIT)
524	# define VMCPU_FF_CSAM_SCAN_PAGE_BIT 26
525	/** CSAM needs to do some homework. */
526	# define VMCPU_FF_CSAM_PENDING_ACTION RT_BIT_32(VMCPU_FF_CSAM_PENDING_ACTION_BIT)
527	# define VMCPU_FF_CSAM_PENDING_ACTION_BIT 27
528	#endif /* VBOX_WITH_RAW_MODE */
529	/** Force return to Ring-3. */
530	#define VMCPU_FF_TO_R3 RT_BIT_32(VMCPU_FF_TO_R3_BIT)
531	#define VMCPU_FF_TO_R3_BIT 28
532	/** Force return to ring-3 to service pending I/O or MMIO write.
533	* This is a backup for mechanism VINF_IOM_R3_IOPORT_COMMIT_WRITE and
534	* VINF_IOM_R3_MMIO_COMMIT_WRITE, allowing VINF_EM_DBG_BREAKPOINT and similar
535	* status codes to be propagated at the same time without loss. */
536	#define VMCPU_FF_IOM RT_BIT_32(VMCPU_FF_IOM_BIT)
537	#define VMCPU_FF_IOM_BIT 29
538	#ifdef VBOX_WITH_RAW_MODE
539	/** CPUM need to adjust CR0.TS/EM before executing raw-mode code again. */
540	# define VMCPU_FF_CPUM RT_BIT_32(VMCPU_FF_CPUM_BIT)
541	/** The bit number for VMCPU_FF_CPUM. */
542	# define VMCPU_FF_CPUM_BIT 30
543	#endif /* VBOX_WITH_RAW_MODE */
544	/** Hardware virtualized nested-guest interrupt pending. */
545	#define VMCPU_FF_INTERRUPT_NESTED_GUEST RT_BIT_32(VMCPU_FF_INTERRUPT_NESTED_GUEST_BIT)
546	#define VMCPU_FF_INTERRUPT_NESTED_GUEST_BIT 31
547
548
549	/** Externally VM forced actions. Used to quit the idle/wait loop. */
550	#define VM_FF_EXTERNAL_SUSPENDED_MASK ( VM_FF_CHECK_VM_STATE \| VM_FF_DBGF \| VM_FF_REQUEST \| VM_FF_EMT_RENDEZVOUS )
551	/** Externally VMCPU forced actions. Used to quit the idle/wait loop. */
552	#define VMCPU_FF_EXTERNAL_SUSPENDED_MASK ( VMCPU_FF_REQUEST \| VMCPU_FF_DBGF )
553
554	/** Externally forced VM actions. Used to quit the idle/wait loop. */
555	#define VM_FF_EXTERNAL_HALTED_MASK ( VM_FF_CHECK_VM_STATE \| VM_FF_DBGF \| VM_FF_REQUEST \
556	\| VM_FF_PDM_QUEUES \| VM_FF_PDM_DMA \| VM_FF_EMT_RENDEZVOUS )
557	/** Externally forced VMCPU actions. Used to quit the idle/wait loop. */
558	#define VMCPU_FF_EXTERNAL_HALTED_MASK ( VMCPU_FF_UPDATE_APIC \| VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC \
559	\| VMCPU_FF_REQUEST \| VMCPU_FF_INTERRUPT_NMI \| VMCPU_FF_INTERRUPT_SMI \
560	\| VMCPU_FF_UNHALT \| VMCPU_FF_TIMER \| VMCPU_FF_DBGF )
561
562	/** High priority VM pre-execution actions. */
563	#define VM_FF_HIGH_PRIORITY_PRE_MASK ( VM_FF_CHECK_VM_STATE \| VM_FF_DBGF \| VM_FF_TM_VIRTUAL_SYNC \
564	\| VM_FF_DEBUG_SUSPEND \| VM_FF_PGM_NEED_HANDY_PAGES \| VM_FF_PGM_NO_MEMORY \
565	\| VM_FF_EMT_RENDEZVOUS )
566	/** High priority VMCPU pre-execution actions. */
567	#define VMCPU_FF_HIGH_PRIORITY_PRE_MASK ( VMCPU_FF_TIMER \| VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC \
568	\| VMCPU_FF_UPDATE_APIC \| VMCPU_FF_INHIBIT_INTERRUPTS \| VMCPU_FF_DBGF \
569	\| VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL \
570	\| VM_WHEN_RAW_MODE( VMCPU_FF_SELM_SYNC_TSS \| VMCPU_FF_TRPM_SYNC_IDT \
571	\| VMCPU_FF_SELM_SYNC_GDT \| VMCPU_FF_SELM_SYNC_LDT, 0 ) )
572
573	/** High priority VM pre raw-mode execution mask. */
574	#define VM_FF_HIGH_PRIORITY_PRE_RAW_MASK ( VM_FF_PGM_NEED_HANDY_PAGES \| VM_FF_PGM_NO_MEMORY )
575	/** High priority VMCPU pre raw-mode execution mask. */
576	#define VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK ( VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL \
577	\| VMCPU_FF_INHIBIT_INTERRUPTS \
578	\| VM_WHEN_RAW_MODE( VMCPU_FF_SELM_SYNC_TSS \| VMCPU_FF_TRPM_SYNC_IDT \
579	\| VMCPU_FF_SELM_SYNC_GDT \| VMCPU_FF_SELM_SYNC_LDT, 0) )
580
581	/** High priority post-execution actions. */
582	#define VM_FF_HIGH_PRIORITY_POST_MASK ( VM_FF_PGM_NO_MEMORY )
583	/** High priority post-execution actions. */
584	#define VMCPU_FF_HIGH_PRIORITY_POST_MASK ( VMCPU_FF_PDM_CRITSECT \| VM_WHEN_RAW_MODE(VMCPU_FF_CSAM_PENDING_ACTION, 0) \
585	\| VMCPU_FF_HM_UPDATE_CR3 \| VMCPU_FF_HM_UPDATE_PAE_PDPES \
586	\| VMCPU_FF_IEM \| VMCPU_FF_IOM )
587
588	/** Normal priority VM post-execution actions. */
589	#define VM_FF_NORMAL_PRIORITY_POST_MASK ( VM_FF_CHECK_VM_STATE \| VM_FF_DBGF \| VM_FF_RESET \
590	\| VM_FF_PGM_NO_MEMORY \| VM_FF_EMT_RENDEZVOUS)
591	/** Normal priority VMCPU post-execution actions. */
592	#define VMCPU_FF_NORMAL_PRIORITY_POST_MASK ( VM_WHEN_RAW_MODE(VMCPU_FF_CSAM_SCAN_PAGE, 0) \| VMCPU_FF_DBGF )
593
594	/** Normal priority VM actions. */
595	#define VM_FF_NORMAL_PRIORITY_MASK ( VM_FF_REQUEST \| VM_FF_PDM_QUEUES \| VM_FF_PDM_DMA \
596	\| VM_FF_REM_HANDLER_NOTIFY \| VM_FF_EMT_RENDEZVOUS)
597	/** Normal priority VMCPU actions. */
598	#define VMCPU_FF_NORMAL_PRIORITY_MASK ( VMCPU_FF_REQUEST )
599
600	/** Flags to clear before resuming guest execution. */
601	#define VMCPU_FF_RESUME_GUEST_MASK ( VMCPU_FF_TO_R3 )
602
603
604	/** VM flags that cause the REP[\|NE\|E] STRINS loops to yield immediately. */
605	#define VM_FF_HIGH_PRIORITY_POST_REPSTR_MASK ( VM_FF_TM_VIRTUAL_SYNC \| VM_FF_PGM_NEED_HANDY_PAGES \| VM_FF_PGM_NO_MEMORY \
606	\| VM_FF_EMT_RENDEZVOUS \| VM_FF_PGM_POOL_FLUSH_PENDING \| VM_FF_RESET)
607	/** VM flags that cause the REP[\|NE\|E] STRINS loops to yield. */
608	#define VM_FF_YIELD_REPSTR_MASK ( VM_FF_HIGH_PRIORITY_POST_REPSTR_MASK \
609	\| VM_FF_PDM_QUEUES \| VM_FF_PDM_DMA \| VM_FF_DBGF \| VM_FF_DEBUG_SUSPEND )
610	/** VMCPU flags that cause the REP[\|NE\|E] STRINS loops to yield immediately. */
611	#ifdef IN_RING3
612	# define VMCPU_FF_HIGH_PRIORITY_POST_REPSTR_MASK ( VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL \| VMCPU_FF_DBGF )
613	#else
614	# define VMCPU_FF_HIGH_PRIORITY_POST_REPSTR_MASK ( VMCPU_FF_TO_R3 \| VMCPU_FF_IEM \| VMCPU_FF_IOM \| VMCPU_FF_PGM_SYNC_CR3 \
615	\| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL \| VMCPU_FF_DBGF )
616	#endif
617	/** VMCPU flags that cause the REP[\|NE\|E] STRINS loops to yield, interrupts
618	* enabled. */
619	#define VMCPU_FF_YIELD_REPSTR_MASK ( VMCPU_FF_HIGH_PRIORITY_POST_REPSTR_MASK \
620	\| VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_UPDATE_APIC \| VMCPU_FF_INTERRUPT_PIC \
621	\| VMCPU_FF_INTERRUPT_NMI \| VMCPU_FF_INTERRUPT_SMI \| VMCPU_FF_PDM_CRITSECT \
622	\| VMCPU_FF_TIMER \| VMCPU_FF_REQUEST )
623	/** VMCPU flags that cause the REP[\|NE\|E] STRINS loops to yield, interrupts
624	* disabled. */
625	#define VMCPU_FF_YIELD_REPSTR_NOINT_MASK ( VMCPU_FF_YIELD_REPSTR_MASK \
626	& ~(VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_UPDATE_APIC \| VMCPU_FF_INTERRUPT_PIC) )
627
628	/** VM Flags that cause the HM loops to go back to ring-3. */
629	#define VM_FF_HM_TO_R3_MASK ( VM_FF_TM_VIRTUAL_SYNC \| VM_FF_PGM_NEED_HANDY_PAGES \| VM_FF_PGM_NO_MEMORY \
630	\| VM_FF_PDM_QUEUES \| VM_FF_EMT_RENDEZVOUS)
631	/** VMCPU Flags that cause the HM loops to go back to ring-3. */
632	#define VMCPU_FF_HM_TO_R3_MASK ( VMCPU_FF_TO_R3 \| VMCPU_FF_TIMER \| VMCPU_FF_PDM_CRITSECT \
633	\| VMCPU_FF_IEM \| VMCPU_FF_IOM)
634
635	/** High priority ring-0 VM pre HM-mode execution mask. */
636	#define VM_FF_HP_R0_PRE_HM_MASK (VM_FF_HM_TO_R3_MASK \| VM_FF_REQUEST \| VM_FF_PGM_POOL_FLUSH_PENDING \| VM_FF_PDM_DMA)
637	/** High priority ring-0 VMCPU pre HM-mode execution mask. */
638	#define VMCPU_FF_HP_R0_PRE_HM_MASK ( VMCPU_FF_HM_TO_R3_MASK \| VMCPU_FF_PGM_SYNC_CR3 \
639	\| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL \| VMCPU_FF_REQUEST)
640	/** High priority ring-0 VM pre HM-mode execution mask, single stepping. */
641	#define VM_FF_HP_R0_PRE_HM_STEP_MASK (VM_FF_HP_R0_PRE_HM_MASK & ~( VM_FF_TM_VIRTUAL_SYNC \| VM_FF_PDM_QUEUES \
642	\| VM_FF_EMT_RENDEZVOUS \| VM_FF_REQUEST \
643	\| VM_FF_PDM_DMA) )
644	/** High priority ring-0 VMCPU pre HM-mode execution mask, single stepping. */
645	#define VMCPU_FF_HP_R0_PRE_HM_STEP_MASK (VMCPU_FF_HP_R0_PRE_HM_MASK & ~( VMCPU_FF_TO_R3 \| VMCPU_FF_TIMER \
646	\| VMCPU_FF_PDM_CRITSECT \| VMCPU_FF_REQUEST) )
647
648	/** All the forced VM flags. */
649	#define VM_FF_ALL_MASK (UINT32_MAX)
650	/** All the forced VMCPU flags. */
651	#define VMCPU_FF_ALL_MASK (UINT32_MAX)
652
653	/** All the forced VM flags except those related to raw-mode and hardware
654	* assisted execution. */
655	#define VM_FF_ALL_REM_MASK (~(VM_FF_HIGH_PRIORITY_PRE_RAW_MASK) \| VM_FF_PGM_NEED_HANDY_PAGES \| VM_FF_PGM_NO_MEMORY)
656	/** All the forced VMCPU flags except those related to raw-mode and hardware
657	* assisted execution. */
658	#define VMCPU_FF_ALL_REM_MASK (~( VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK \| VMCPU_FF_PDM_CRITSECT \
659	\| VMCPU_FF_TLB_FLUSH \| VM_WHEN_RAW_MODE(VMCPU_FF_CSAM_PENDING_ACTION, 0) ))
660	/** @} */
661
662	/** @def VM_FF_SET
663	* Sets a single force action flag.
664	*
665	* @param pVM The cross context VM structure.
666	* @param fFlag The flag to set.
667	*/
668	#define VM_FF_SET(pVM, fFlag) do { \
669	AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
670	AssertCompile((fFlag) == RT_BIT_32(fFlag##_BIT)); \
671	ASMAtomicOrU32(&(pVM)->fGlobalForcedActions, (fFlag)); \
672	} while (0)
673
674	/** @def VMCPU_FF_SET
675	* Sets a single force action flag for the given VCPU.
676	*
677	* @param pVCpu The cross context virtual CPU structure.
678	* @param fFlag The flag to set.
679	* @sa VMCPU_FF_SET_MASK
680	*/
681	#ifdef VMCPU_WITH_64_BIT_FFS
682	# define VMCPU_FF_SET(pVCpu, fFlag) do { \
683	AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
684	AssertCompile((fFlag) == RT_BIT_32(fFlag##_BIT)); \
685	ASMAtomicBitSet(&(pVCpu)->fLocalForcedActions, fFlag##_BIT); \
686	} while (0)
687	#else
688	# define VMCPU_FF_SET(pVCpu, fFlag) do { \
689	AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
690	AssertCompile((fFlag) == RT_BIT_32(fFlag##_BIT)); \
691	ASMAtomicOrU32(&(pVCpu)->fLocalForcedActions, (fFlag)); \
692	} while (0)
693	#endif
694
695	/** @def VMCPU_FF_SET_MASK
696	* Sets a two or more force action flag for the given VCPU.
697	*
698	* @param pVCpu The cross context virtual CPU structure.
699	* @param fFlags The flags to set.
700	* @sa VMCPU_FF_SET
701	*/
702	#ifdef VMCPU_WITH_64_BIT_FFS
703	# if ARCH_BITS > 32
704	# define VMCPU_FF_SET_MASK(pVCpu, fFlags) \
705	do { ASMAtomicOrU64(&pVCpu->fLocalForcedActions, (fFlags)); } while (0)
706	# else
707	# define VMCPU_FF_SET_MASK(pVCpu, fFlags) do { \
708	if (!((fFlags) >> 32)) ASMAtomicOrU32((uint32_t volatile *)&pVCpu->fLocalForcedActions, (uint32_t)(fFlags)); \
709	else ASMAtomicOrU64(&pVCpu->fLocalForcedActions, (fFlags)); \
710	} while (0)
711	# endif
712	#else
713	# define VMCPU_FF_SET_MASK(pVCpu, fFlags) \
714	do { ASMAtomicOrU32(&pVCpu->fLocalForcedActions, (fFlags)); } while (0)
715	#endif
716
717	/** @def VM_FF_CLEAR
718	* Clears a single force action flag.
719	*
720	* @param pVM The cross context VM structure.
721	* @param fFlag The flag to clear.
722	*/
723	#define VM_FF_CLEAR(pVM, fFlag) do { \
724	AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
725	AssertCompile((fFlag) == RT_BIT_32(fFlag##_BIT)); \
726	ASMAtomicAndU32(&(pVM)->fGlobalForcedActions, ~(fFlag)); \
727	} while (0)
728
729	/** @def VMCPU_FF_CLEAR
730	* Clears a single force action flag for the given VCPU.
731	*
732	* @param pVCpu The cross context virtual CPU structure.
733	* @param fFlag The flag to clear.
734	*/
735	#ifdef VMCPU_WITH_64_BIT_FFS
736	# define VMCPU_FF_CLEAR(pVCpu, fFlag) do { \
737	AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
738	AssertCompile((fFlag) == RT_BIT_32(fFlag##_BIT)); \
739	ASMAtomicBitClear(&(pVCpu)->fLocalForcedActions, fFlag##_BIT); \
740	} while (0)
741	#else
742	# define VMCPU_FF_CLEAR(pVCpu, fFlag) do { \
743	AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
744	AssertCompile((fFlag) == RT_BIT_32(fFlag##_BIT)); \
745	ASMAtomicAndU32(&(pVCpu)->fLocalForcedActions, ~(fFlag)); \
746	} while (0)
747	#endif
748
749	/** @def VMCPU_FF_CLEAR_MASK
750	* Clears two or more force action flags for the given VCPU.
751	*
752	* @param pVCpu The cross context virtual CPU structure.
753	* @param fFlags The flags to clear.
754	*/
755	#ifdef VMCPU_WITH_64_BIT_FFS
756	# if ARCH_BITS > 32
757	# define VMCPU_FF_CLEAR_MASK(pVCpu, fFlags) \
758	do { ASMAtomicAndU64(&(pVCpu)->fLocalForcedActions, ~(fFlags)); } while (0)
759	# else
760	# define VMCPU_FF_CLEAR_MASK(pVCpu, fFlags) do { \
761	if (!((fFlags) >> 32)) ASMAtomicAndU32((uint32_t volatile *)&(pVCpu)->fLocalForcedActions, ~(uint32_t)(fFlags)); \
762	else ASMAtomicAndU64(&(pVCpu)->fLocalForcedActions, ~(fFlags)); \
763	} while (0)
764	# endif
765	#else
766	# define VMCPU_FF_CLEAR_MASK(pVCpu, fFlags) \
767	do { ASMAtomicAndU32(&(pVCpu)->fLocalForcedActions, ~(fFlags)); } while (0)
768	#endif
769
770	/** @def VM_FF_IS_SET
771	* Checks if single a force action flag is set.
772	*
773	* @param pVM The cross context VM structure.
774	* @param fFlag The flag to check.
775	* @sa VM_FF_IS_ANY_SET
776	*/
777	#if !defined(VBOX_STRICT) \|\| !defined(RT_COMPILER_SUPPORTS_LAMBDA)
778	# define VM_FF_IS_SET(pVM, fFlag) RT_BOOL((pVM)->fGlobalForcedActions & (fFlag))
779	#else
780	# define VM_FF_IS_SET(pVM, fFlag) \
781	([](PVM a_pVM) -> bool \
782	{ \
783	AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
784	AssertCompile((fFlag) == RT_BIT_32(fFlag##_BIT)); \
785	return RT_BOOL(a_pVM->fGlobalForcedActions & (fFlag)); \
786	}(pVM))
787	#endif
788
789	/** @def VMCPU_FF_IS_SET
790	* Checks if a single force action flag is set for the given VCPU.
791	*
792	* @param pVCpu The cross context virtual CPU structure.
793	* @param fFlag The flag to check.
794	* @sa VMCPU_FF_IS_ANY_SET
795	*/
796	#if !defined(VBOX_STRICT) \|\| !defined(RT_COMPILER_SUPPORTS_LAMBDA)
797	# define VMCPU_FF_IS_SET(pVCpu, fFlag) RT_BOOL((pVCpu)->fLocalForcedActions & (fFlag))
798	#else
799	# define VMCPU_FF_IS_SET(pVCpu, fFlag) \
800	([](PVMCPU a_pVCpu) -> bool \
801	{ \
802	AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
803	AssertCompile((fFlag) == RT_BIT_32(fFlag##_BIT)); \
804	return RT_BOOL(a_pVCpu->fLocalForcedActions & (fFlag)); \
805	}(pVCpu))
806	#endif
807
808	/** @def VM_FF_IS_ANY_SET
809	* Checks if one or more force action in the specified set is pending.
810	*
811	* @param pVM The cross context VM structure.
812	* @param fFlags The flags to check for.
813	* @sa VM_FF_IS_SET
814	*/
815	#define VM_FF_IS_ANY_SET(pVM, fFlags) RT_BOOL((pVM)->fGlobalForcedActions & (fFlags))
816
817	/** @def VMCPU_FF_IS_ANY_SET
818	* Checks if two or more force action flags in the specified set is set for the given VCPU.
819	*
820	* @param pVCpu The cross context virtual CPU structure.
821	* @param fFlags The flags to check for.
822	* @sa VMCPU_FF_IS_SET
823	*/
824	#define VMCPU_FF_IS_ANY_SET(pVCpu, fFlags) RT_BOOL((pVCpu)->fLocalForcedActions & (fFlags))
825
826	/** @def VM_FF_TEST_AND_CLEAR
827	* Checks if one (!) force action in the specified set is pending and clears it atomically
828	*
829	* @returns true if the bit was set.
830	* @returns false if the bit was clear.
831	* @param pVM The cross context VM structure.
832	* @param fFlag Flag constant to check and clear (_BIT is appended).
833	*/
834	#define VM_FF_TEST_AND_CLEAR(pVM, fFlag) (ASMAtomicBitTestAndClear(&(pVM)->fGlobalForcedActions, fFlag##_BIT))
835
836	/** @def VMCPU_FF_TEST_AND_CLEAR
837	* Checks if one (!) force action in the specified set is pending and clears it atomically
838	*
839	* @returns true if the bit was set.
840	* @returns false if the bit was clear.
841	* @param pVCpu The cross context virtual CPU structure.
842	* @param fFlag Flag constant to check and clear (_BIT is appended).
843	*/
844	#define VMCPU_FF_TEST_AND_CLEAR(pVCpu, fFlag) (ASMAtomicBitTestAndClear(&(pVCpu)->fLocalForcedActions, fFlag##_BIT))
845
846	/** @def VM_FF_IS_PENDING_EXCEPT
847	* Checks if one or more force action in the specified set is pending while one
848	* or more other ones are not.
849	*
850	* @param pVM The cross context VM structure.
851	* @param fFlags The flags to check for.
852	* @param fExcpt The flags that should not be set.
853	*/
854	#define VM_FF_IS_PENDING_EXCEPT(pVM, fFlags, fExcpt) \
855	( ((pVM)->fGlobalForcedActions & (fFlags)) && !((pVM)->fGlobalForcedActions & (fExcpt)) )
856
857	/** @def VM_IS_EMT
858	* Checks if the current thread is the emulation thread (EMT).
859	*
860	* @remark The ring-0 variation will need attention if we expand the ring-0
861	* code to let threads other than EMT mess around with the VM.
862	*/
863	#ifdef IN_RC
864	# define VM_IS_EMT(pVM) true
865	#else
866	# define VM_IS_EMT(pVM) (VMMGetCpu(pVM) != NULL)
867	#endif
868
869	/** @def VMCPU_IS_EMT
870	* Checks if the current thread is the emulation thread (EMT) for the specified
871	* virtual CPU.
872	*/
873	#ifdef IN_RC
874	# define VMCPU_IS_EMT(pVCpu) true
875	#else
876	# define VMCPU_IS_EMT(pVCpu) ((pVCpu) && ((pVCpu) == VMMGetCpu((pVCpu)->CTX_SUFF(pVM))))
877	#endif
878
879	/** @def VM_ASSERT_EMT
880	* Asserts that the current thread IS the emulation thread (EMT).
881	*/
882	#ifdef IN_RC
883	# define VM_ASSERT_EMT(pVM) Assert(VM_IS_EMT(pVM))
884	#elif defined(IN_RING0)
885	# define VM_ASSERT_EMT(pVM) Assert(VM_IS_EMT(pVM))
886	#else
887	# define VM_ASSERT_EMT(pVM) \
888	AssertMsg(VM_IS_EMT(pVM), \
889	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd\n", RTThreadNativeSelf(), VMR3GetVMCPUNativeThread(pVM)))
890	#endif
891
892	/** @def VMCPU_ASSERT_EMT
893	* Asserts that the current thread IS the emulation thread (EMT) of the
894	* specified virtual CPU.
895	*/
896	#ifdef IN_RC
897	# define VMCPU_ASSERT_EMT(pVCpu) Assert(VMCPU_IS_EMT(pVCpu))
898	#elif defined(IN_RING0)
899	# define VMCPU_ASSERT_EMT(pVCpu) AssertMsg(VMCPU_IS_EMT(pVCpu), \
900	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd idCpu=%u\n", \
901	RTThreadNativeSelf(), (pVCpu) ? (pVCpu)->hNativeThreadR0 : 0, \
902	(pVCpu) ? (pVCpu)->idCpu : 0))
903	#else
904	# define VMCPU_ASSERT_EMT(pVCpu) AssertMsg(VMCPU_IS_EMT(pVCpu), \
905	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd idCpu=%#x\n", \
906	RTThreadNativeSelf(), (pVCpu)->hNativeThread, (pVCpu)->idCpu))
907	#endif
908
909	/** @def VM_ASSERT_EMT_RETURN
910	* Asserts that the current thread IS the emulation thread (EMT) and returns if it isn't.
911	*/
912	#ifdef IN_RC
913	# define VM_ASSERT_EMT_RETURN(pVM, rc) AssertReturn(VM_IS_EMT(pVM), (rc))
914	#elif defined(IN_RING0)
915	# define VM_ASSERT_EMT_RETURN(pVM, rc) AssertReturn(VM_IS_EMT(pVM), (rc))
916	#else
917	# define VM_ASSERT_EMT_RETURN(pVM, rc) \
918	AssertMsgReturn(VM_IS_EMT(pVM), \
919	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd\n", RTThreadNativeSelf(), VMR3GetVMCPUNativeThread(pVM)), \
920	(rc))
921	#endif
922
923	/** @def VMCPU_ASSERT_EMT_RETURN
924	* Asserts that the current thread IS the emulation thread (EMT) and returns if it isn't.
925	*/
926	#ifdef IN_RC
927	# define VMCPU_ASSERT_EMT_RETURN(pVCpu, rc) AssertReturn(VMCPU_IS_EMT(pVCpu), (rc))
928	#elif defined(IN_RING0)
929	# define VMCPU_ASSERT_EMT_RETURN(pVCpu, rc) AssertReturn(VMCPU_IS_EMT(pVCpu), (rc))
930	#else
931	# define VMCPU_ASSERT_EMT_RETURN(pVCpu, rc) \
932	AssertMsgReturn(VMCPU_IS_EMT(pVCpu), \
933	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd idCpu=%#x\n", \
934	RTThreadNativeSelf(), (pVCpu)->hNativeThread, (pVCpu)->idCpu), \
935	(rc))
936	#endif
937
938	/** @def VMCPU_ASSERT_EMT_OR_GURU
939	* Asserts that the current thread IS the emulation thread (EMT) of the
940	* specified virtual CPU.
941	*/
942	#if defined(IN_RC) \|\| defined(IN_RING0)
943	# define VMCPU_ASSERT_EMT_OR_GURU(pVCpu) Assert( VMCPU_IS_EMT(pVCpu) \
944	\|\| pVCpu->CTX_SUFF(pVM)->enmVMState == VMSTATE_GURU_MEDITATION \
945	\|\| pVCpu->CTX_SUFF(pVM)->enmVMState == VMSTATE_GURU_MEDITATION_LS )
946	#else
947	# define VMCPU_ASSERT_EMT_OR_GURU(pVCpu) \
948	AssertMsg( VMCPU_IS_EMT(pVCpu) \
949	\|\| pVCpu->CTX_SUFF(pVM)->enmVMState == VMSTATE_GURU_MEDITATION \
950	\|\| pVCpu->CTX_SUFF(pVM)->enmVMState == VMSTATE_GURU_MEDITATION_LS, \
951	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd idCpu=%#x\n", \
952	RTThreadNativeSelf(), (pVCpu)->hNativeThread, (pVCpu)->idCpu))
953	#endif
954
955	/** @def VMCPU_ASSERT_EMT_OR_NOT_RUNNING
956	* Asserts that the current thread IS the emulation thread (EMT) of the
957	* specified virtual CPU or the VM is not running.
958	*/
959	#if defined(IN_RC) \|\| defined(IN_RING0)
960	# define VMCPU_ASSERT_EMT_OR_NOT_RUNNING(pVCpu) \
961	Assert( VMCPU_IS_EMT(pVCpu) \
962	\|\| !VM_IS_RUNNING_FOR_ASSERTIONS_ONLY((pVCpu)->CTX_SUFF(pVM)) )
963	#else
964	# define VMCPU_ASSERT_EMT_OR_NOT_RUNNING(pVCpu) \
965	AssertMsg( VMCPU_IS_EMT(pVCpu) \
966	\|\| !VM_IS_RUNNING_FOR_ASSERTIONS_ONLY((pVCpu)->CTX_SUFF(pVM)), \
967	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd idCpu=%#x\n", \
968	RTThreadNativeSelf(), (pVCpu)->hNativeThread, (pVCpu)->idCpu))
969	#endif
970
971	/** @def VMSTATE_IS_RUNNING
972	* Checks if the given state indicates a running VM.
973	*/
974	#define VMSTATE_IS_RUNNING(a_enmVMState) \
975	( (enmVMState) == VMSTATE_RUNNING \
976	\|\| (enmVMState) == VMSTATE_RUNNING_LS \
977	\|\| (enmVMState) == VMSTATE_RUNNING_FT )
978
979	/** @def VM_IS_RUNNING_FOR_ASSERTIONS_ONLY
980	* Checks if the VM is running.
981	* @note This is only for pure debug assertions. No AssertReturn or similar!
982	* @sa VMSTATE_IS_RUNNING
983	*/
984	#define VM_IS_RUNNING_FOR_ASSERTIONS_ONLY(pVM) \
985	( (pVM)->enmVMState == VMSTATE_RUNNING \
986	\|\| (pVM)->enmVMState == VMSTATE_RUNNING_LS \
987	\|\| (pVM)->enmVMState == VMSTATE_RUNNING_FT )
988
989	/** @def VM_ASSERT_IS_NOT_RUNNING
990	* Asserts that the VM is not running.
991	*/
992	#if defined(IN_RC) \|\| defined(IN_RING0)
993	#define VM_ASSERT_IS_NOT_RUNNING(pVM) Assert(!VM_IS_RUNNING_FOR_ASSERTIONS_ONLY(pVM))
994	#else
995	#define VM_ASSERT_IS_NOT_RUNNING(pVM) AssertMsg(!VM_IS_RUNNING_FOR_ASSERTIONS_ONLY(pVM), \
996	("VM is running. enmVMState=%d\n", (pVM)->enmVMState))
997	#endif
998
999	/** @def VM_ASSERT_EMT0
1000	* Asserts that the current thread IS emulation thread \#0 (EMT0).
1001	*/
1002	#define VM_ASSERT_EMT0(pVM) VMCPU_ASSERT_EMT(&(pVM)->aCpus[0])
1003
1004	/** @def VM_ASSERT_EMT0_RETURN
1005	* Asserts that the current thread IS emulation thread \#0 (EMT0) and returns if
1006	* it isn't.
1007	*/
1008	#define VM_ASSERT_EMT0_RETURN(pVM, rc) VMCPU_ASSERT_EMT_RETURN(&(pVM)->aCpus[0], (rc))
1009
1010
1011	/**
1012	* Asserts that the current thread is NOT the emulation thread.
1013	*/
1014	#define VM_ASSERT_OTHER_THREAD(pVM) \
1015	AssertMsg(!VM_IS_EMT(pVM), ("Not other thread!!\n"))
1016
1017
1018	/** @def VM_ASSERT_STATE
1019	* Asserts a certain VM state.
1020	*/
1021	#define VM_ASSERT_STATE(pVM, _enmState) \
1022	AssertMsg((pVM)->enmVMState == (_enmState), \
1023	("state %s, expected %s\n", VMGetStateName((pVM)->enmVMState), VMGetStateName(_enmState)))
1024
1025	/** @def VM_ASSERT_STATE_RETURN
1026	* Asserts a certain VM state and returns if it doesn't match.
1027	*/
1028	#define VM_ASSERT_STATE_RETURN(pVM, _enmState, rc) \
1029	AssertMsgReturn((pVM)->enmVMState == (_enmState), \
1030	("state %s, expected %s\n", VMGetStateName((pVM)->enmVMState), VMGetStateName(_enmState)), \
1031	(rc))
1032
1033	/** @def VM_IS_VALID_EXT
1034	* Asserts a the VM handle is valid for external access, i.e. not being destroy
1035	* or terminated. */
1036	#define VM_IS_VALID_EXT(pVM) \
1037	( RT_VALID_ALIGNED_PTR(pVM, PAGE_SIZE) \
1038	&& ( (unsigned)(pVM)->enmVMState < (unsigned)VMSTATE_DESTROYING \
1039	\|\| ( (unsigned)(pVM)->enmVMState == (unsigned)VMSTATE_DESTROYING \
1040	&& VM_IS_EMT(pVM))) )
1041
1042	/** @def VM_ASSERT_VALID_EXT_RETURN
1043	* Asserts a the VM handle is valid for external access, i.e. not being
1044	* destroy or terminated.
1045	*/
1046	#define VM_ASSERT_VALID_EXT_RETURN(pVM, rc) \
1047	AssertMsgReturn(VM_IS_VALID_EXT(pVM), \
1048	("pVM=%p state %s\n", (pVM), RT_VALID_ALIGNED_PTR(pVM, PAGE_SIZE) \
1049	? VMGetStateName(pVM->enmVMState) : ""), \
1050	(rc))
1051
1052	/** @def VMCPU_ASSERT_VALID_EXT_RETURN
1053	* Asserts a the VMCPU handle is valid for external access, i.e. not being
1054	* destroy or terminated.
1055	*/
1056	#define VMCPU_ASSERT_VALID_EXT_RETURN(pVCpu, rc) \
1057	AssertMsgReturn( RT_VALID_ALIGNED_PTR(pVCpu, 64) \
1058	&& RT_VALID_ALIGNED_PTR((pVCpu)->CTX_SUFF(pVM), PAGE_SIZE) \
1059	&& (unsigned)(pVCpu)->CTX_SUFF(pVM)->enmVMState < (unsigned)VMSTATE_DESTROYING, \
1060	("pVCpu=%p pVM=%p state %s\n", (pVCpu), RT_VALID_ALIGNED_PTR(pVCpu, 64) ? (pVCpu)->CTX_SUFF(pVM) : NULL, \
1061	RT_VALID_ALIGNED_PTR(pVCpu, 64) && RT_VALID_ALIGNED_PTR((pVCpu)->CTX_SUFF(pVM), PAGE_SIZE) \
1062	? VMGetStateName((pVCpu)->pVMR3->enmVMState) : ""), \
1063	(rc))
1064
1065	#endif /* !VBOX_FOR_DTRACE_LIB */
1066
1067
1068	/**
1069	* Helper that HM and NEM uses for safely modifying VM::bMainExecutionEngine.
1070	*
1071	* ONLY HM and NEM MAY USE THIS!
1072	*
1073	* @param a_pVM The cross context VM structure.
1074	* @param a_bValue The new value.
1075	* @internal
1076	*/
1077	#define VM_SET_MAIN_EXECUTION_ENGINE(a_pVM, a_bValue) \
1078	do { \
1079	const_cast<uint8_t >(&(a_pVM)->bMainExecutionEngine) = (a_bValue); \
1080	ASMCompilerBarrier(); /* just to be on the safe side */ \
1081	} while (0)
1082
1083	/**
1084	* Checks whether raw-mode is used.
1085	*
1086	* @retval true if either is used.
1087	* @retval false if software virtualization (raw-mode) is used.
1088	*
1089	* @param a_pVM The cross context VM structure.
1090	* @sa VM_IS_HM_OR_NEM_ENABLED, VM_IS_HM_ENABLED, VM_IS_NEM_ENABLED.
1091	* @internal
1092	*/
1093	#ifdef VBOX_WITH_RAW_MODE
1094	# define VM_IS_RAW_MODE_ENABLED(a_pVM) ((a_pVM)->bMainExecutionEngine == VM_EXEC_ENGINE_RAW_MODE)
1095	#else
1096	# define VM_IS_RAW_MODE_ENABLED(a_pVM) (false)
1097	#endif
1098
1099	/**
1100	* Checks whether HM (VT-x/AMD-V) or NEM is being used by this VM.
1101	*
1102	* @retval true if either is used.
1103	* @retval false if software virtualization (raw-mode) is used.
1104	*
1105	* @param a_pVM The cross context VM structure.
1106	* @sa VM_IS_RAW_MODE_ENABLED, VM_IS_HM_ENABLED, VM_IS_NEM_ENABLED.
1107	* @internal
1108	*/
1109	#define VM_IS_HM_OR_NEM_ENABLED(a_pVM) ((a_pVM)->bMainExecutionEngine != VM_EXEC_ENGINE_RAW_MODE)
1110
1111	/**
1112	* Checks whether HM is being used by this VM.
1113	*
1114	* @retval true if HM (VT-x/AMD-v) is used.
1115	* @retval false if not.
1116	*
1117	* @param a_pVM The cross context VM structure.
1118	* @sa VM_IS_NEM_ENABLED, VM_IS_RAW_MODE_ENABLED, VM_IS_HM_OR_NEM_ENABLED.
1119	* @internal
1120	*/
1121	#define VM_IS_HM_ENABLED(a_pVM) ((a_pVM)->bMainExecutionEngine == VM_EXEC_ENGINE_HW_VIRT)
1122
1123	/**
1124	* Checks whether NEM is being used by this VM.
1125	*
1126	* @retval true if a native hypervisor API is used.
1127	* @retval false if not.
1128	*
1129	* @param a_pVM The cross context VM structure.
1130	* @sa VM_IS_HM_ENABLED, VM_IS_RAW_MODE_ENABLED, VM_IS_HM_OR_NEM_ENABLED.
1131	* @internal
1132	*/
1133	#define VM_IS_NEM_ENABLED(a_pVM) ((a_pVM)->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API)
1134
1135
1136	/**
1137	* The cross context VM structure.
1138	*
1139	* It contains all the VM data which have to be available in all contexts.
1140	* Even if it contains all the data the idea is to use APIs not to modify all
1141	* the members all around the place. Therefore we make use of unions to hide
1142	* everything which isn't local to the current source module. This means we'll
1143	* have to pay a little bit of attention when adding new members to structures
1144	* in the unions and make sure to keep the padding sizes up to date.
1145	*
1146	* Run 'kmk run-struct-tests' (from src/VBox/VMM if you like) after updating!
1147	*/
1148	typedef struct VM
1149	{
1150	/** The state of the VM.
1151	* This field is read only to everyone except the VM and EM. */
1152	VMSTATE volatile enmVMState;
1153	/** Forced action flags.
1154	* See the VM_FF_* \#defines. Updated atomically.
1155	*/
1156	volatile uint32_t fGlobalForcedActions;
1157	/** Pointer to the array of page descriptors for the VM structure allocation. */
1158	R3PTRTYPE(PSUPPAGE) paVMPagesR3;
1159	/** Session handle. For use when calling SUPR0 APIs. */
1160	PSUPDRVSESSION pSession;
1161	/** Pointer to the ring-3 VM structure. */
1162	PUVM pUVM;
1163	/** Ring-3 Host Context VM Pointer. */
1164	R3PTRTYPE(struct VM *) pVMR3;
1165	/** Ring-0 Host Context VM Pointer. */
1166	R0PTRTYPE(struct VM *) pVMR0;
1167	/** Raw-mode Context VM Pointer. */
1168	RCPTRTYPE(struct VM *) pVMRC;
1169
1170	/** The GVM VM handle. Only the GVM should modify this field. */
1171	uint32_t hSelf;
1172	/** Number of virtual CPUs. */
1173	uint32_t cCpus;
1174	/** CPU excution cap (1-100) */
1175	uint32_t uCpuExecutionCap;
1176
1177	/** Size of the VM structure including the VMCPU array. */
1178	uint32_t cbSelf;
1179
1180	/** Offset to the VMCPU array starting from beginning of this structure. */
1181	uint32_t offVMCPU;
1182
1183	/**
1184	* VMMSwitcher assembly entry point returning to host context.
1185	*
1186	* Depending on how the host handles the rc status given in @a eax, this may
1187	* return and let the caller resume whatever it was doing prior to the call.
1188	*
1189	*
1190	* @param eax The return code, register.
1191	* @remark Assume interrupts disabled.
1192	* @remark This method pointer lives here because TRPM needs it.
1193	*/
1194	RTRCPTR pfnVMMRCToHostAsm/(int32_t eax)/;
1195
1196	/**
1197	* VMMSwitcher assembly entry point returning to host context without saving the
1198	* raw-mode context (hyper) registers.
1199	*
1200	* Unlike pfnVMMRC2HCAsm, this will not return to the caller. Instead it
1201	* expects the caller to save a RC context in CPUM where one might return if the
1202	* return code indicate that this is possible.
1203	*
1204	* This method pointer lives here because TRPM needs it.
1205	*
1206	* @param eax The return code, register.
1207	* @remark Assume interrupts disabled.
1208	* @remark This method pointer lives here because TRPM needs it.
1209	*/
1210	RTRCPTR pfnVMMRCToHostAsmNoReturn/(int32_t eax)/;
1211
1212	/** @name Various items that are frequently accessed.
1213	* @{ */
1214	/** The main execution engine, VM_EXEC_ENGINE_XXX.
1215	* This is set early during vmR3InitRing3 by HM or NEM. */
1216	uint8_t const bMainExecutionEngine;
1217
1218	/** Whether to recompile user mode code or run it raw/hm/nem.
1219	* In non-raw-mode both fRecompileUser and fRecompileSupervisor must be set
1220	* to recompiler stuff. */
1221	bool fRecompileUser;
1222	/** Whether to recompile supervisor mode code or run it raw/hm/nem.
1223	* In non-raw-mode both fRecompileUser and fRecompileSupervisor must be set
1224	* to recompiler stuff. */
1225	bool fRecompileSupervisor;
1226	/** Whether raw mode supports ring-1 code or not.
1227	* This will be cleared when not in raw-mode. */
1228	bool fRawRing1Enabled;
1229	/** PATM enabled flag.
1230	* This is placed here for performance reasons.
1231	* This will be cleared when not in raw-mode. */
1232	bool fPATMEnabled;
1233	/** CSAM enabled flag.
1234	* This is placed here for performance reasons.
1235	* This will be cleared when not in raw-mode. */
1236	bool fCSAMEnabled;
1237
1238	/** Hardware VM support is available and enabled.
1239	* Determined very early during init.
1240	* This is placed here for performance reasons.
1241	* @todo obsoleted by bMainExecutionEngine, eliminate. */
1242	bool fHMEnabled;
1243	/** Hardware VM support requires a minimal raw-mode context.
1244	* This is never set on 64-bit hosts, only 32-bit hosts requires it. */
1245	bool fHMNeedRawModeCtx;
1246
1247	/** Set when this VM is the master FT node.
1248	* @todo This doesn't need to be here, FTM should store it in it's own
1249	* structures instead. */
1250	bool fFaultTolerantMaster;
1251	/** Large page enabled flag.
1252	* @todo This doesn't need to be here, PGM should store it in it's own
1253	* structures instead. */
1254	bool fUseLargePages;
1255	/** @} */
1256
1257	/** Alignment padding. */
1258	uint8_t uPadding1[2];
1259
1260	/** @name Debugging
1261	* @{ */
1262	/** Raw-mode Context VM Pointer. */
1263	RCPTRTYPE(RTTRACEBUF) hTraceBufRC;
1264	/** Ring-3 Host Context VM Pointer. */
1265	R3PTRTYPE(RTTRACEBUF) hTraceBufR3;
1266	/** Ring-0 Host Context VM Pointer. */
1267	R0PTRTYPE(RTTRACEBUF) hTraceBufR0;
1268	/** @} */
1269
1270	#if HC_ARCH_BITS == 32
1271	/** Alignment padding. */
1272	uint32_t uPadding2;
1273	#endif
1274
1275	/** @name Switcher statistics (remove)
1276	* @{ */
1277	/** Profiling the total time from Qemu to GC. */
1278	STAMPROFILEADV StatTotalQemuToGC;
1279	/** Profiling the total time from GC to Qemu. */
1280	STAMPROFILEADV StatTotalGCToQemu;
1281	/** Profiling the total time spent in GC. */
1282	STAMPROFILEADV StatTotalInGC;
1283	/** Profiling the total time spent not in Qemu. */
1284	STAMPROFILEADV StatTotalInQemu;
1285	/** Profiling the VMMSwitcher code for going to GC. */
1286	STAMPROFILEADV StatSwitcherToGC;
1287	/** Profiling the VMMSwitcher code for going to HC. */
1288	STAMPROFILEADV StatSwitcherToHC;
1289	STAMPROFILEADV StatSwitcherSaveRegs;
1290	STAMPROFILEADV StatSwitcherSysEnter;
1291	STAMPROFILEADV StatSwitcherDebug;
1292	STAMPROFILEADV StatSwitcherCR0;
1293	STAMPROFILEADV StatSwitcherCR4;
1294	STAMPROFILEADV StatSwitcherJmpCR3;
1295	STAMPROFILEADV StatSwitcherRstrRegs;
1296	STAMPROFILEADV StatSwitcherLgdt;
1297	STAMPROFILEADV StatSwitcherLidt;
1298	STAMPROFILEADV StatSwitcherLldt;
1299	STAMPROFILEADV StatSwitcherTSS;
1300	/** @} */
1301
1302	/** Padding - the unions must be aligned on a 64 bytes boundary and the unions
1303	* must start at the same offset on both 64-bit and 32-bit hosts. */
1304	uint8_t abAlignment3[(HC_ARCH_BITS == 32 ? 24 : 0) + 40];
1305
1306	/** CPUM part. */
1307	union
1308	{
1309	#ifdef ___CPUMInternal_h
1310	struct CPUM s;
1311	#endif
1312	#ifdef ___VBox_vmm_cpum_h
1313	/** Read only info exposed about the host and guest CPUs. */
1314	struct
1315	{
1316	/** Padding for hidden fields. */
1317	uint8_t abHidden0[64];
1318	/** Host CPU feature information. */
1319	CPUMFEATURES HostFeatures;
1320	/** Guest CPU feature information. */
1321	CPUMFEATURES GuestFeatures;
1322	} const ro;
1323	#endif
1324	uint8_t padding[1536]; /* multiple of 64 */
1325	} cpum;
1326
1327	/** VMM part. */
1328	union
1329	{
1330	#ifdef ___VMMInternal_h
1331	struct VMM s;
1332	#endif
1333	uint8_t padding[1600]; /* multiple of 64 */
1334	} vmm;
1335
1336	/** PGM part. */
1337	union
1338	{
1339	#ifdef ___PGMInternal_h
1340	struct PGM s;
1341	#endif
1342	uint8_t padding[40962+6080]; / multiple of 64 */
1343	} pgm;
1344
1345	/** HM part. */
1346	union
1347	{
1348	#ifdef ___HMInternal_h
1349	struct HM s;
1350	#endif
1351	uint8_t padding[5440]; /* multiple of 64 */
1352	} hm;
1353
1354	/** TRPM part. */
1355	union
1356	{
1357	#ifdef ___TRPMInternal_h
1358	struct TRPM s;
1359	#endif
1360	uint8_t padding[5248]; /* multiple of 64 */
1361	} trpm;
1362
1363	/** SELM part. */
1364	union
1365	{
1366	#ifdef ___SELMInternal_h
1367	struct SELM s;
1368	#endif
1369	uint8_t padding[768]; /* multiple of 64 */
1370	} selm;
1371
1372	/** MM part. */
1373	union
1374	{
1375	#ifdef ___MMInternal_h
1376	struct MM s;
1377	#endif
1378	uint8_t padding[192]; /* multiple of 64 */
1379	} mm;
1380
1381	/** PDM part. */
1382	union
1383	{
1384	#ifdef ___PDMInternal_h
1385	struct PDM s;
1386	#endif
1387	uint8_t padding[1920]; /* multiple of 64 */
1388	} pdm;
1389
1390	/** IOM part. */
1391	union
1392	{
1393	#ifdef ___IOMInternal_h
1394	struct IOM s;
1395	#endif
1396	uint8_t padding[896]; /* multiple of 64 */
1397	} iom;
1398
1399	/** EM part. */
1400	union
1401	{
1402	#ifdef ___EMInternal_h
1403	struct EM s;
1404	#endif
1405	uint8_t padding[256]; /* multiple of 64 */
1406	} em;
1407
1408	/** NEM part. */
1409	union
1410	{
1411	#ifdef ___NEMInternal_h
1412	struct NEM s;
1413	#endif
1414	uint8_t padding[128]; /* multiple of 64 */
1415	} nem;
1416
1417	/** TM part. */
1418	union
1419	{
1420	#ifdef ___TMInternal_h
1421	struct TM s;
1422	#endif
1423	uint8_t padding[2496]; /* multiple of 64 */
1424	} tm;
1425
1426	/** DBGF part. */
1427	union
1428	{
1429	#ifdef ___DBGFInternal_h
1430	struct DBGF s;
1431	#endif
1432	#ifdef ___VBox_vmm_dbgf_h
1433	/** Read only info exposed about interrupt breakpoints and selected events. */
1434	struct
1435	{
1436	/** Bitmap of enabled hardware interrupt breakpoints. */
1437	uint32_t bmHardIntBreakpoints[256 / 32];
1438	/** Bitmap of enabled software interrupt breakpoints. */
1439	uint32_t bmSoftIntBreakpoints[256 / 32];
1440	/** Bitmap of selected events.
1441	* This includes non-selectable events too for simplicity, we maintain the
1442	* state for some of these, as it may come in handy. */
1443	uint64_t bmSelectedEvents[(DBGFEVENT_END + 63) / 64];
1444	/** Enabled hardware interrupt breakpoints. */
1445	uint32_t cHardIntBreakpoints;
1446	/** Enabled software interrupt breakpoints. */
1447	uint32_t cSoftIntBreakpoints;
1448	/** The number of selected events. */
1449	uint32_t cSelectedEvents;
1450	/** The number of enabled hardware breakpoints. */
1451	uint8_t cEnabledHwBreakpoints;
1452	/** The number of enabled hardware I/O breakpoints. */
1453	uint8_t cEnabledHwIoBreakpoints;
1454	/** The number of enabled INT3 breakpoints. */
1455	uint8_t cEnabledInt3Breakpoints;
1456	uint8_t abPadding[1]; /*< Unused padding space up for grabs. /
1457	} const ro;
1458	#endif
1459	uint8_t padding[2432]; /* multiple of 64 */
1460	} dbgf;
1461
1462	/** SSM part. */
1463	union
1464	{
1465	#ifdef ___SSMInternal_h
1466	struct SSM s;
1467	#endif
1468	uint8_t padding[128]; /* multiple of 64 */
1469	} ssm;
1470
1471	/** FTM part. */
1472	union
1473	{
1474	#ifdef ___FTMInternal_h
1475	struct FTM s;
1476	#endif
1477	uint8_t padding[512]; /* multiple of 64 */
1478	} ftm;
1479
1480	#ifdef VBOX_WITH_RAW_MODE
1481	/** PATM part. */
1482	union
1483	{
1484	# ifdef ___PATMInternal_h
1485	struct PATM s;
1486	# endif
1487	uint8_t padding[768]; /* multiple of 64 */
1488	} patm;
1489
1490	/** CSAM part. */
1491	union
1492	{
1493	# ifdef ___CSAMInternal_h
1494	struct CSAM s;
1495	# endif
1496	uint8_t padding[1088]; /* multiple of 64 */
1497	} csam;
1498	#endif
1499
1500	#ifdef VBOX_WITH_REM
1501	/** REM part. */
1502	union
1503	{
1504	# ifdef ___REMInternal_h
1505	struct REM s;
1506	# endif
1507	uint8_t padding[0x11100]; /* multiple of 64 */
1508	} rem;
1509	#endif
1510
1511	union
1512	{
1513	#ifdef ___GIMInternal_h
1514	struct GIM s;
1515	#endif
1516	uint8_t padding[448]; /* multiple of 64 */
1517	} gim;
1518
1519	union
1520	{
1521	#ifdef ___APICInternal_h
1522	struct APIC s;
1523	#endif
1524	uint8_t padding[128]; /* multiple of 8 */
1525	} apic;
1526
1527	/* ---- begin small stuff ---- */
1528
1529	/** VM part. */
1530	union
1531	{
1532	#ifdef ___VMInternal_h
1533	struct VMINT s;
1534	#endif
1535	uint8_t padding[32]; /* multiple of 8 */
1536	} vm;
1537
1538	/** CFGM part. */
1539	union
1540	{
1541	#ifdef ___CFGMInternal_h
1542	struct CFGM s;
1543	#endif
1544	uint8_t padding[8]; /* multiple of 8 */
1545	} cfgm;
1546
1547	/** Padding for aligning the cpu array on a page boundary. */
1548	#if defined(VBOX_WITH_REM) && defined(VBOX_WITH_RAW_MODE)
1549	uint8_t abAlignment2[3670];
1550	#elif defined(VBOX_WITH_REM) && !defined(VBOX_WITH_RAW_MODE)
1551	uint8_t abAlignment2[1430];
1552	#elif !defined(VBOX_WITH_REM) && defined(VBOX_WITH_RAW_MODE)
1553	uint8_t abAlignment2[3926];
1554	#else
1555	uint8_t abAlignment2[1686];
1556	#endif
1557
1558	/* ---- end small stuff ---- */
1559
1560	/** VMCPU array for the configured number of virtual CPUs.
1561	* Must be aligned on a page boundary for TLB hit reasons as well as
1562	* alignment of VMCPU members. */
1563	VMCPU aCpus[1];
1564	} VM;
1565
1566
1567	#ifdef IN_RC
1568	RT_C_DECLS_BEGIN
1569
1570	/** The VM structure.
1571	* This is imported from the VMMRCBuiltin module, i.e. it's a one of those magic
1572	* globals which we should avoid using.
1573	*/
1574	extern DECLIMPORT(VM) g_VM;
1575
1576	RT_C_DECLS_END
1577	#endif
1578
1579	/** @} */
1580
1581	#endif
1582

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source: vbox/trunk/include/VBox/vmm/vm.h@ 74817

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