vm.h@ 78425

Last change on this file since 78425 was 77610, checked in by vboxsync, 6 years ago
VMM/EM, VMM/IEM: Nested VMX: bugref:9180 Implemented NMI-exiting, NMI-window and virtual-NMI support. Moved VMCPU_FF_VMX_APIC_WRITE to high-priority post mask. Fixed calling iemMemRollback in IEMExecDecodedXXX for VMX instructions. Clear all VMX force-flags in common VM-exit handler rather than in the specific handler, esp since multiple of them may be active at the time of VM-exit.
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1	/** @file
2	* VM - The Virtual Machine, data.
3	*/
4
5	/*
6	* Copyright (C) 2006-2019 Oracle Corporation
7	*
8	* This file is part of VirtualBox Open Source Edition (OSE), as
9	* available from http://www.virtualbox.org. This file is free software;
10	* you can redistribute it and/or modify it under the terms of the GNU
11	* General Public License (GPL) as published by the Free Software
12	* Foundation, in version 2 as it comes in the "COPYING" file of the
13	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15	*
16	* The contents of this file may alternatively be used under the terms
17	* of the Common Development and Distribution License Version 1.0
18	* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19	* VirtualBox OSE distribution, in which case the provisions of the
20	* CDDL are applicable instead of those of the GPL.
21	*
22	* You may elect to license modified versions of this file under the
23	* terms and conditions of either the GPL or the CDDL or both.
24	*/
25
26	#ifndef VBOX_INCLUDED_vmm_vm_h
27	#define VBOX_INCLUDED_vmm_vm_h
28	#ifndef RT_WITHOUT_PRAGMA_ONCE
29	# pragma once
30	#endif
31
32	#ifndef VBOX_FOR_DTRACE_LIB
33	# include <iprt/param.h>
34	# include <VBox/types.h>
35	# include <VBox/vmm/cpum.h>
36	# include <VBox/vmm/stam.h>
37	# include <VBox/vmm/vmapi.h>
38	# include <VBox/vmm/vmm.h>
39	# include <VBox/sup.h>
40	#else
41	# pragma D depends_on library vbox-types.d
42	# pragma D depends_on library CPUMInternal.d
43	# define VMM_INCLUDED_SRC_include_CPUMInternal_h
44	#endif
45
46
47
48	/** @defgroup grp_vm The Virtual Machine
49	* @ingroup grp_vmm
50	* @{
51	*/
52
53	/**
54	* The state of a Virtual CPU.
55	*
56	* The basic state indicated here is whether the CPU has been started or not. In
57	* addition, there are sub-states when started for assisting scheduling (GVMM
58	* mostly).
59	*
60	* The transition out of the STOPPED state is done by a vmR3PowerOn.
61	* The transition back to the STOPPED state is done by vmR3PowerOff.
62	*
63	* (Alternatively we could let vmR3PowerOn start CPU 0 only and let the SPIP
64	* handling switch on the other CPUs. Then vmR3Reset would stop all but CPU 0.)
65	*/
66	typedef enum VMCPUSTATE
67	{
68	/** The customary invalid zero. */
69	VMCPUSTATE_INVALID = 0,
70
71	/** Virtual CPU has not yet been started. */
72	VMCPUSTATE_STOPPED,
73
74	/** CPU started. */
75	VMCPUSTATE_STARTED,
76	/** CPU started in HM context. */
77	VMCPUSTATE_STARTED_HM,
78	/** Executing guest code and can be poked (RC or STI bits of HM). */
79	VMCPUSTATE_STARTED_EXEC,
80	/** Executing guest code in the recompiler. */
81	VMCPUSTATE_STARTED_EXEC_REM,
82	/** Executing guest code using NEM. */
83	VMCPUSTATE_STARTED_EXEC_NEM,
84	VMCPUSTATE_STARTED_EXEC_NEM_WAIT,
85	VMCPUSTATE_STARTED_EXEC_NEM_CANCELED,
86	/** Halted. */
87	VMCPUSTATE_STARTED_HALTED,
88
89	/** The end of valid virtual CPU states. */
90	VMCPUSTATE_END,
91
92	/** Ensure 32-bit type. */
93	VMCPUSTATE_32BIT_HACK = 0x7fffffff
94	} VMCPUSTATE;
95
96	/** Enables 64-bit FFs. */
97	#define VMCPU_WITH_64_BIT_FFS
98
99
100	/**
101	* The cross context virtual CPU structure.
102	*
103	* Run 'kmk run-struct-tests' (from src/VBox/VMM if you like) after updating!
104	*/
105	typedef struct VMCPU
106	{
107	/** @name Volatile per-cpu data.
108	* @{ */
109	/** Per CPU forced action.
110	* See the VMCPU_FF_* \#defines. Updated atomically. */
111	#ifdef VMCPU_WITH_64_BIT_FFS
112	uint64_t volatile fLocalForcedActions;
113	#else
114	uint32_t volatile fLocalForcedActions;
115	uint32_t fForLocalForcedActionsExpansion;
116	#endif
117	/** The CPU state. */
118	VMCPUSTATE volatile enmState;
119
120	/** Which host CPU ID is this EMT running on.
121	* Only valid when in RC or HMR0 with scheduling disabled. */
122	RTCPUID volatile idHostCpu;
123	/** The CPU set index corresponding to idHostCpu, UINT32_MAX if not valid.
124	* @remarks Best to make sure iHostCpuSet shares cache line with idHostCpu! */
125	uint32_t volatile iHostCpuSet;
126	/** Padding up to 64 bytes. */
127	uint8_t abAlignment0[64 - 20];
128	/** @} */
129
130	/** IEM part.
131	* @remarks This comes first as it allows the use of 8-bit immediates for the
132	* first 64 bytes of the structure, reducing code size a wee bit. */
133	#ifdef VMM_INCLUDED_SRC_include_IEMInternal_h /* For PDB hacking. */
134	union VMCPUUNIONIEMFULL
135	#else
136	union VMCPUUNIONIEMSTUB
137	#endif
138	{
139	#ifdef VMM_INCLUDED_SRC_include_IEMInternal_h
140	struct IEMCPU s;
141	#endif
142	uint8_t padding[18496]; /* multiple of 64 */
143	} iem;
144
145	/** @name Static per-cpu data.
146	* (Putting this after IEM, hoping that it's less frequently used than it.)
147	* @{ */
148	/** The CPU ID.
149	* This is the index into the VM::aCpu array. */
150	VMCPUID idCpu;
151	/** Raw-mode Context VM Pointer. */
152	PVMRC pVMRC;
153	/** Ring-3 Host Context VM Pointer. */
154	PVMR3 pVMR3;
155	/** Ring-0 Host Context VM Pointer. */
156	PVMR0 pVMR0;
157	/** Pointer to the ring-3 UVMCPU structure. */
158	PUVMCPU pUVCpu;
159	/** The native thread handle. */
160	RTNATIVETHREAD hNativeThread;
161	/** The native R0 thread handle. (different from the R3 handle!) */
162	RTNATIVETHREAD hNativeThreadR0;
163	/** Align the structures below bit on a 64-byte boundary and make sure it starts
164	* at the same offset in both 64-bit and 32-bit builds.
165	*
166	* @remarks The alignments of the members that are larger than 48 bytes should be
167	* 64-byte for cache line reasons. structs containing small amounts of
168	* data could be lumped together at the end with a < 64 byte padding
169	* following it (to grow into and align the struct size).
170	*/
171	uint8_t abAlignment1[64 - 4 - 4 - 5 * (HC_ARCH_BITS == 64 ? 8 : 4)];
172	/** @} */
173
174	/** HM part. */
175	union VMCPUUNIONHM
176	{
177	#ifdef VMM_INCLUDED_SRC_include_HMInternal_h
178	struct HMCPU s;
179	#endif
180	uint8_t padding[5888]; /* multiple of 64 */
181	} hm;
182
183	/** NEM part. */
184	union VMCPUUNIONNEM
185	{
186	#ifdef VMM_INCLUDED_SRC_include_NEMInternal_h
187	struct NEMCPU s;
188	#endif
189	uint8_t padding[512]; /* multiple of 64 */
190	} nem;
191
192	/** TRPM part. */
193	union VMCPUUNIONTRPM
194	{
195	#ifdef VMM_INCLUDED_SRC_include_TRPMInternal_h
196	struct TRPMCPU s;
197	#endif
198	uint8_t padding[128]; /* multiple of 64 */
199	} trpm;
200
201	/** TM part. */
202	union VMCPUUNIONTM
203	{
204	#ifdef VMM_INCLUDED_SRC_include_TMInternal_h
205	struct TMCPU s;
206	#endif
207	uint8_t padding[384]; /* multiple of 64 */
208	} tm;
209
210	/** VMM part. */
211	union VMCPUUNIONVMM
212	{
213	#ifdef VMM_INCLUDED_SRC_include_VMMInternal_h
214	struct VMMCPU s;
215	#endif
216	uint8_t padding[896]; /* multiple of 64 */
217	} vmm;
218
219	/** PDM part. */
220	union VMCPUUNIONPDM
221	{
222	#ifdef VMM_INCLUDED_SRC_include_PDMInternal_h
223	struct PDMCPU s;
224	#endif
225	uint8_t padding[256]; /* multiple of 64 */
226	} pdm;
227
228	/** IOM part. */
229	union VMCPUUNIONIOM
230	{
231	#ifdef VMM_INCLUDED_SRC_include_IOMInternal_h
232	struct IOMCPU s;
233	#endif
234	uint8_t padding[512]; /* multiple of 64 */
235	} iom;
236
237	/** DBGF part.
238	* @todo Combine this with other tiny structures. */
239	union VMCPUUNIONDBGF
240	{
241	#ifdef VMM_INCLUDED_SRC_include_DBGFInternal_h
242	struct DBGFCPU s;
243	#endif
244	uint8_t padding[256]; /* multiple of 64 */
245	} dbgf;
246
247	/** GIM part. */
248	union VMCPUUNIONGIM
249	{
250	#ifdef VMM_INCLUDED_SRC_include_GIMInternal_h
251	struct GIMCPU s;
252	#endif
253	uint8_t padding[512]; /* multiple of 64 */
254	} gim;
255
256	/** APIC part. */
257	union VMCPUUNIONAPIC
258	{
259	#ifdef VMM_INCLUDED_SRC_include_APICInternal_h
260	struct APICCPU s;
261	#endif
262	uint8_t padding[1792]; /* multiple of 64 */
263	} apic;
264
265	/*
266	* Some less frequently used global members that doesn't need to take up
267	* precious space at the head of the structure.
268	*/
269
270	/** Trace groups enable flags. */
271	uint32_t fTraceGroups; /* 64 / 44 */
272	/** State data for use by ad hoc profiling. */
273	uint32_t uAdHoc;
274	/** Profiling samples for use by ad hoc profiling. */
275	STAMPROFILEADV aStatAdHoc[8]; /* size: 408 = 320 /
276
277	/** Align the following members on page boundary. */
278	uint8_t abAlignment2[2680];
279
280	/** PGM part. */
281	union VMCPUUNIONPGM
282	{
283	#ifdef VMM_INCLUDED_SRC_include_PGMInternal_h
284	struct PGMCPU s;
285	#endif
286	uint8_t padding[4096]; /* multiple of 4096 */
287	} pgm;
288
289	/** CPUM part. */
290	union VMCPUUNIONCPUM
291	{
292	#ifdef VMM_INCLUDED_SRC_include_CPUMInternal_h
293	struct CPUMCPU s;
294	#endif
295	#ifdef VMCPU_INCL_CPUM_GST_CTX
296	/** The guest CPUM context for direct use by execution engines.
297	* This is not for general consumption, but for HM, REM, IEM, and maybe a few
298	* others. The rest will use the function based CPUM API. */
299	CPUMCTX GstCtx;
300	#endif
301	uint8_t padding[4096]; /* multiple of 4096 */
302	} cpum;
303
304	/** EM part. */
305	union VMCPUUNIONEM
306	{
307	#ifdef VMM_INCLUDED_SRC_include_EMInternal_h
308	struct EMCPU s;
309	#endif
310	uint8_t padding[40960]; /* multiple of 4096 */
311	} em;
312	} VMCPU;
313
314
315	#ifndef VBOX_FOR_DTRACE_LIB
316
317	/** @name Operations on VMCPU::enmState
318	* @{ */
319	/** Gets the VMCPU state. */
320	#define VMCPU_GET_STATE(pVCpu) ( (pVCpu)->enmState )
321	/** Sets the VMCPU state. */
322	#define VMCPU_SET_STATE(pVCpu, enmNewState) \
323	ASMAtomicWriteU32((uint32_t volatile *)&(pVCpu)->enmState, (enmNewState))
324	/** Cmpares and sets the VMCPU state. */
325	#define VMCPU_CMPXCHG_STATE(pVCpu, enmNewState, enmOldState) \
326	ASMAtomicCmpXchgU32((uint32_t volatile *)&(pVCpu)->enmState, (enmNewState), (enmOldState))
327	/** Checks the VMCPU state. */
328	#ifdef VBOX_STRICT
329	# define VMCPU_ASSERT_STATE(pVCpu, enmExpectedState) \
330	do { \
331	VMCPUSTATE enmState = VMCPU_GET_STATE(pVCpu); \
332	AssertMsg(enmState == (enmExpectedState), \
333	("enmState=%d enmExpectedState=%d idCpu=%u\n", \
334	enmState, enmExpectedState, (pVCpu)->idCpu)); \
335	} while (0)
336	#else
337	# define VMCPU_ASSERT_STATE(pVCpu, enmExpectedState) do { } while (0)
338	#endif
339	/** Tests if the state means that the CPU is started. */
340	#define VMCPUSTATE_IS_STARTED(enmState) ( (enmState) > VMCPUSTATE_STOPPED )
341	/** Tests if the state means that the CPU is stopped. */
342	#define VMCPUSTATE_IS_STOPPED(enmState) ( (enmState) == VMCPUSTATE_STOPPED )
343	/** @} */
344
345
346	/** The name of the raw-mode context VMM Core module. */
347	#define VMMRC_MAIN_MODULE_NAME "VMMRC.rc"
348	/** The name of the ring-0 context VMM Core module. */
349	#define VMMR0_MAIN_MODULE_NAME "VMMR0.r0"
350
351	/**
352	* Wrapper macro for avoiding too much \#ifdef VBOX_WITH_RAW_MODE.
353	*/
354	#ifdef VBOX_WITH_RAW_MODE
355	# define VM_WHEN_RAW_MODE(a_WithExpr, a_WithoutExpr) a_WithExpr
356	#else
357	# define VM_WHEN_RAW_MODE(a_WithExpr, a_WithoutExpr) a_WithoutExpr
358	#endif
359
360
361	/** VM Forced Action Flags.
362	*
363	* Use the VM_FF_SET() and VM_FF_CLEAR() macros to change the force
364	* action mask of a VM.
365	*
366	* Available VM bits:
367	* 0, 1, 5, 6, 7, 13, 14, 15, 16, 17, 21, 22, 23, 24, 25, 26, 27, 28, 30
368	*
369	*
370	* Available VMCPU bits:
371	* 14, 15, 36 to 63
372	*
373	* @todo If we run low on VMCPU, we may consider merging the SELM bits
374	*
375	* @{
376	*/
377	/** The virtual sync clock has been stopped, go to TM until it has been
378	* restarted... */
379	#define VM_FF_TM_VIRTUAL_SYNC RT_BIT_32(VM_FF_TM_VIRTUAL_SYNC_BIT)
380	#define VM_FF_TM_VIRTUAL_SYNC_BIT 2
381	/** PDM Queues are pending. */
382	#define VM_FF_PDM_QUEUES RT_BIT_32(VM_FF_PDM_QUEUES_BIT)
383	/** The bit number for VM_FF_PDM_QUEUES. */
384	#define VM_FF_PDM_QUEUES_BIT 3
385	/** PDM DMA transfers are pending. */
386	#define VM_FF_PDM_DMA RT_BIT_32(VM_FF_PDM_DMA_BIT)
387	/** The bit number for VM_FF_PDM_DMA. */
388	#define VM_FF_PDM_DMA_BIT 4
389	/** This action forces the VM to call DBGF so DBGF can service debugger
390	* requests in the emulation thread.
391	* This action flag stays asserted till DBGF clears it.*/
392	#define VM_FF_DBGF RT_BIT_32(VM_FF_DBGF_BIT)
393	/** The bit number for VM_FF_DBGF. */
394	#define VM_FF_DBGF_BIT 8
395	/** This action forces the VM to service pending requests from other
396	* thread or requests which must be executed in another context. */
397	#define VM_FF_REQUEST RT_BIT_32(VM_FF_REQUEST_BIT)
398	#define VM_FF_REQUEST_BIT 9
399	/** Check for VM state changes and take appropriate action. */
400	#define VM_FF_CHECK_VM_STATE RT_BIT_32(VM_FF_CHECK_VM_STATE_BIT)
401	/** The bit number for VM_FF_CHECK_VM_STATE. */
402	#define VM_FF_CHECK_VM_STATE_BIT 10
403	/** Reset the VM. (postponed) */
404	#define VM_FF_RESET RT_BIT_32(VM_FF_RESET_BIT)
405	/** The bit number for VM_FF_RESET. */
406	#define VM_FF_RESET_BIT 11
407	/** EMT rendezvous in VMM. */
408	#define VM_FF_EMT_RENDEZVOUS RT_BIT_32(VM_FF_EMT_RENDEZVOUS_BIT)
409	/** The bit number for VM_FF_EMT_RENDEZVOUS. */
410	#define VM_FF_EMT_RENDEZVOUS_BIT 12
411
412	/** PGM needs to allocate handy pages. */
413	#define VM_FF_PGM_NEED_HANDY_PAGES RT_BIT_32(VM_FF_PGM_NEED_HANDY_PAGES_BIT)
414	#define VM_FF_PGM_NEED_HANDY_PAGES_BIT 18
415	/** PGM is out of memory.
416	* Abandon all loops and code paths which can be resumed and get up to the EM
417	* loops. */
418	#define VM_FF_PGM_NO_MEMORY RT_BIT_32(VM_FF_PGM_NO_MEMORY_BIT)
419	#define VM_FF_PGM_NO_MEMORY_BIT 19
420	/** PGM is about to perform a lightweight pool flush
421	* Guest SMP: all EMT threads should return to ring 3
422	*/
423	#define VM_FF_PGM_POOL_FLUSH_PENDING RT_BIT_32(VM_FF_PGM_POOL_FLUSH_PENDING_BIT)
424	#define VM_FF_PGM_POOL_FLUSH_PENDING_BIT 20
425	/** REM needs to be informed about handler changes. */
426	#define VM_FF_REM_HANDLER_NOTIFY RT_BIT_32(VM_FF_REM_HANDLER_NOTIFY_BIT)
427	/** The bit number for VM_FF_REM_HANDLER_NOTIFY. */
428	#define VM_FF_REM_HANDLER_NOTIFY_BIT 29
429	/** Suspend the VM - debug only. */
430	#define VM_FF_DEBUG_SUSPEND RT_BIT_32(VM_FF_DEBUG_SUSPEND_BIT)
431	#define VM_FF_DEBUG_SUSPEND_BIT 31
432
433
434	/** This action forces the VM to check any pending interrupts on the APIC. */
435	#define VMCPU_FF_INTERRUPT_APIC RT_BIT_64(VMCPU_FF_INTERRUPT_APIC_BIT)
436	#define VMCPU_FF_INTERRUPT_APIC_BIT 0
437	/** This action forces the VM to check any pending interrups on the PIC. */
438	#define VMCPU_FF_INTERRUPT_PIC RT_BIT_64(VMCPU_FF_INTERRUPT_PIC_BIT)
439	#define VMCPU_FF_INTERRUPT_PIC_BIT 1
440	/** This action forces the VM to schedule and run pending timer (TM).
441	* @remarks Don't move - PATM compatibility. */
442	#define VMCPU_FF_TIMER RT_BIT_64(VMCPU_FF_TIMER_BIT)
443	#define VMCPU_FF_TIMER_BIT 2
444	/** This action forces the VM to check any pending NMIs. */
445	#define VMCPU_FF_INTERRUPT_NMI RT_BIT_64(VMCPU_FF_INTERRUPT_NMI_BIT)
446	#define VMCPU_FF_INTERRUPT_NMI_BIT 3
447	/** This action forces the VM to check any pending SMIs. */
448	#define VMCPU_FF_INTERRUPT_SMI RT_BIT_64(VMCPU_FF_INTERRUPT_SMI_BIT)
449	#define VMCPU_FF_INTERRUPT_SMI_BIT 4
450	/** PDM critical section unlocking is pending, process promptly upon return to R3. */
451	#define VMCPU_FF_PDM_CRITSECT RT_BIT_64(VMCPU_FF_PDM_CRITSECT_BIT)
452	#define VMCPU_FF_PDM_CRITSECT_BIT 5
453	/** Special EM internal force flag that is used by EMUnhaltAndWakeUp() to force
454	* the virtual CPU out of the next (/current) halted state. It is not processed
455	* nor cleared by emR3ForcedActions (similar to VMCPU_FF_BLOCK_NMIS), instead it
456	* is cleared the next time EM leaves the HALTED state. */
457	#define VMCPU_FF_UNHALT RT_BIT_64(VMCPU_FF_UNHALT_BIT)
458	#define VMCPU_FF_UNHALT_BIT 6
459	/** Pending IEM action (mask). */
460	#define VMCPU_FF_IEM RT_BIT_64(VMCPU_FF_IEM_BIT)
461	/** Pending IEM action (bit number). */
462	#define VMCPU_FF_IEM_BIT 7
463	/** Pending APIC action (bit number). */
464	#define VMCPU_FF_UPDATE_APIC_BIT 8
465	/** This action forces the VM to update APIC's asynchronously arrived
466	* interrupts as pending interrupts. */
467	#define VMCPU_FF_UPDATE_APIC RT_BIT_64(VMCPU_FF_UPDATE_APIC_BIT)
468	/** This action forces the VM to service pending requests from other
469	* thread or requests which must be executed in another context. */
470	#define VMCPU_FF_REQUEST RT_BIT_64(VMCPU_FF_REQUEST_BIT)
471	#define VMCPU_FF_REQUEST_BIT 9
472	/** Pending DBGF event (alternative to passing VINF_EM_DBG_EVENT around). */
473	#define VMCPU_FF_DBGF RT_BIT_64(VMCPU_FF_DBGF_BIT)
474	/** The bit number for VMCPU_FF_DBGF. */
475	#define VMCPU_FF_DBGF_BIT 10
476	/** This action forces the VM to service any pending updates to CR3 (used only
477	* by HM). */
478	/** Hardware virtualized nested-guest interrupt pending. */
479	#define VMCPU_FF_INTERRUPT_NESTED_GUEST RT_BIT_64(VMCPU_FF_INTERRUPT_NESTED_GUEST_BIT)
480	#define VMCPU_FF_INTERRUPT_NESTED_GUEST_BIT 11
481	#define VMCPU_FF_HM_UPDATE_CR3 RT_BIT_64(VMCPU_FF_HM_UPDATE_CR3_BIT)
482	#define VMCPU_FF_HM_UPDATE_CR3_BIT 12
483	/** This action forces the VM to service any pending updates to PAE PDPEs (used
484	* only by HM). */
485	#define VMCPU_FF_HM_UPDATE_PAE_PDPES RT_BIT_64(VMCPU_FF_HM_UPDATE_PAE_PDPES_BIT)
486	#define VMCPU_FF_HM_UPDATE_PAE_PDPES_BIT 13
487	/** This action forces the VM to resync the page tables before going
488	* back to execute guest code. (GLOBAL FLUSH) */
489	#define VMCPU_FF_PGM_SYNC_CR3 RT_BIT_64(VMCPU_FF_PGM_SYNC_CR3_BIT)
490	#define VMCPU_FF_PGM_SYNC_CR3_BIT 16
491	/** Same as VM_FF_PGM_SYNC_CR3 except that global pages can be skipped.
492	* (NON-GLOBAL FLUSH) */
493	#define VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL RT_BIT_64(VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL_BIT)
494	#define VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL_BIT 17
495	/** Check for pending TLB shootdown actions (deprecated)
496	* Reserved for furture HM re-use if necessary / safe.
497	* Consumer: HM */
498	#define VMCPU_FF_TLB_SHOOTDOWN_UNUSED RT_BIT_64(VMCPU_FF_TLB_SHOOTDOWN_UNUSED_BIT)
499	#define VMCPU_FF_TLB_SHOOTDOWN_UNUSED_BIT 18
500	/** Check for pending TLB flush action.
501	* Consumer: HM
502	* @todo rename to VMCPU_FF_HM_TLB_FLUSH */
503	#define VMCPU_FF_TLB_FLUSH RT_BIT_64(VMCPU_FF_TLB_FLUSH_BIT)
504	/** The bit number for VMCPU_FF_TLB_FLUSH. */
505	#define VMCPU_FF_TLB_FLUSH_BIT 19
506	#ifdef VBOX_WITH_RAW_MODE
507	/** Check the interrupt and trap gates */
508	# define VMCPU_FF_TRPM_SYNC_IDT RT_BIT_64(VMCPU_FF_TRPM_SYNC_IDT_BIT)
509	# define VMCPU_FF_TRPM_SYNC_IDT_BIT 20
510	/** Check Guest's TSS ring 0 stack */
511	# define VMCPU_FF_SELM_SYNC_TSS RT_BIT_64(VMCPU_FF_SELM_SYNC_TSS_BIT)
512	# define VMCPU_FF_SELM_SYNC_TSS_BIT 21
513	/** Check Guest's GDT table */
514	# define VMCPU_FF_SELM_SYNC_GDT RT_BIT_64(VMCPU_FF_SELM_SYNC_GDT_BIT)
515	# define VMCPU_FF_SELM_SYNC_GDT_BIT 22
516	/** Check Guest's LDT table */
517	# define VMCPU_FF_SELM_SYNC_LDT RT_BIT_64(VMCPU_FF_SELM_SYNC_LDT_BIT)
518	# define VMCPU_FF_SELM_SYNC_LDT_BIT 23
519	#endif /* VBOX_WITH_RAW_MODE */
520	/** Inhibit interrupts pending. See EMGetInhibitInterruptsPC(). */
521	#define VMCPU_FF_INHIBIT_INTERRUPTS RT_BIT_64(VMCPU_FF_INHIBIT_INTERRUPTS_BIT)
522	#define VMCPU_FF_INHIBIT_INTERRUPTS_BIT 24
523	/** Block injection of non-maskable interrupts to the guest. */
524	#define VMCPU_FF_BLOCK_NMIS RT_BIT_64(VMCPU_FF_BLOCK_NMIS_BIT)
525	#define VMCPU_FF_BLOCK_NMIS_BIT 25
526	#ifdef VBOX_WITH_RAW_MODE
527	/** CSAM needs to scan the page that's being executed */
528	# define VMCPU_FF_CSAM_SCAN_PAGE RT_BIT_64(VMCPU_FF_CSAM_SCAN_PAGE_BIT)
529	# define VMCPU_FF_CSAM_SCAN_PAGE_BIT 26
530	/** CSAM needs to do some homework. */
531	# define VMCPU_FF_CSAM_PENDING_ACTION RT_BIT_64(VMCPU_FF_CSAM_PENDING_ACTION_BIT)
532	# define VMCPU_FF_CSAM_PENDING_ACTION_BIT 27
533	#endif /* VBOX_WITH_RAW_MODE */
534	/** Force return to Ring-3. */
535	#define VMCPU_FF_TO_R3 RT_BIT_64(VMCPU_FF_TO_R3_BIT)
536	#define VMCPU_FF_TO_R3_BIT 28
537	/** Force return to ring-3 to service pending I/O or MMIO write.
538	* This is a backup for mechanism VINF_IOM_R3_IOPORT_COMMIT_WRITE and
539	* VINF_IOM_R3_MMIO_COMMIT_WRITE, allowing VINF_EM_DBG_BREAKPOINT and similar
540	* status codes to be propagated at the same time without loss. */
541	#define VMCPU_FF_IOM RT_BIT_64(VMCPU_FF_IOM_BIT)
542	#define VMCPU_FF_IOM_BIT 29
543	#ifdef VBOX_WITH_RAW_MODE
544	/** CPUM need to adjust CR0.TS/EM before executing raw-mode code again. */
545	# define VMCPU_FF_CPUM RT_BIT_64(VMCPU_FF_CPUM_BIT)
546	/** The bit number for VMCPU_FF_CPUM. */
547	# define VMCPU_FF_CPUM_BIT 30
548	#endif /* VBOX_WITH_RAW_MODE */
549	/** VMX-preemption timer in effect. */
550	#define VMCPU_FF_VMX_PREEMPT_TIMER RT_BIT_64(VMCPU_FF_VMX_PREEMPT_TIMER_BIT)
551	#define VMCPU_FF_VMX_PREEMPT_TIMER_BIT 31
552	/** Pending MTF (Monitor Trap Flag) event. */
553	#define VMCPU_FF_VMX_MTF RT_BIT_64(VMCPU_FF_VMX_MTF_BIT)
554	#define VMCPU_FF_VMX_MTF_BIT 32
555	/** VMX APIC-write emulation pending. */
556	#define VMCPU_FF_VMX_APIC_WRITE RT_BIT_64(VMCPU_FF_VMX_APIC_WRITE_BIT)
557	#define VMCPU_FF_VMX_APIC_WRITE_BIT 33
558	/** VMX interrupt-window event pending. */
559	#define VMCPU_FF_VMX_INT_WINDOW RT_BIT_64(VMCPU_FF_VMX_INT_WINDOW_BIT)
560	#define VMCPU_FF_VMX_INT_WINDOW_BIT 34
561	/** VMX NMI-window event pending. */
562	#define VMCPU_FF_VMX_NMI_WINDOW RT_BIT_64(VMCPU_FF_VMX_NMI_WINDOW_BIT)
563	#define VMCPU_FF_VMX_NMI_WINDOW_BIT 35
564
565
566	/** Externally VM forced actions. Used to quit the idle/wait loop. */
567	#define VM_FF_EXTERNAL_SUSPENDED_MASK ( VM_FF_CHECK_VM_STATE \| VM_FF_DBGF \| VM_FF_REQUEST \| VM_FF_EMT_RENDEZVOUS )
568	/** Externally VMCPU forced actions. Used to quit the idle/wait loop. */
569	#define VMCPU_FF_EXTERNAL_SUSPENDED_MASK ( VMCPU_FF_REQUEST \| VMCPU_FF_DBGF )
570
571	/** Externally forced VM actions. Used to quit the idle/wait loop. */
572	#define VM_FF_EXTERNAL_HALTED_MASK ( VM_FF_CHECK_VM_STATE \| VM_FF_DBGF \| VM_FF_REQUEST \
573	\| VM_FF_PDM_QUEUES \| VM_FF_PDM_DMA \| VM_FF_EMT_RENDEZVOUS )
574	/** Externally forced VMCPU actions. Used to quit the idle/wait loop. */
575	#define VMCPU_FF_EXTERNAL_HALTED_MASK ( VMCPU_FF_UPDATE_APIC \| VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC \
576	\| VMCPU_FF_REQUEST \| VMCPU_FF_INTERRUPT_NMI \| VMCPU_FF_INTERRUPT_SMI \
577	\| VMCPU_FF_UNHALT \| VMCPU_FF_TIMER \| VMCPU_FF_DBGF \
578	\| VMCPU_FF_INTERRUPT_NESTED_GUEST)
579
580	/** High priority VM pre-execution actions. */
581	#define VM_FF_HIGH_PRIORITY_PRE_MASK ( VM_FF_CHECK_VM_STATE \| VM_FF_DBGF \| VM_FF_TM_VIRTUAL_SYNC \
582	\| VM_FF_DEBUG_SUSPEND \| VM_FF_PGM_NEED_HANDY_PAGES \| VM_FF_PGM_NO_MEMORY \
583	\| VM_FF_EMT_RENDEZVOUS )
584	/** High priority VMCPU pre-execution actions. */
585	#define VMCPU_FF_HIGH_PRIORITY_PRE_MASK ( VMCPU_FF_TIMER \| VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC \
586	\| VMCPU_FF_UPDATE_APIC \| VMCPU_FF_INHIBIT_INTERRUPTS \| VMCPU_FF_DBGF \
587	\| VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL \
588	\| VMCPU_FF_INTERRUPT_NESTED_GUEST \| VMCPU_FF_VMX_MTF \| VMCPU_FF_VMX_APIC_WRITE \
589	\| VMCPU_FF_VMX_PREEMPT_TIMER \| VMCPU_FF_VMX_NMI_WINDOW \| VMCPU_FF_VMX_INT_WINDOW \
590	\| VM_WHEN_RAW_MODE( VMCPU_FF_SELM_SYNC_TSS \| VMCPU_FF_TRPM_SYNC_IDT \
591	\| VMCPU_FF_SELM_SYNC_GDT \| VMCPU_FF_SELM_SYNC_LDT, 0 ) )
592
593	/** High priority VM pre raw-mode execution mask. */
594	#define VM_FF_HIGH_PRIORITY_PRE_RAW_MASK ( VM_FF_PGM_NEED_HANDY_PAGES \| VM_FF_PGM_NO_MEMORY )
595	/** High priority VMCPU pre raw-mode execution mask. */
596	#define VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK ( VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL \
597	\| VMCPU_FF_INHIBIT_INTERRUPTS \
598	\| VM_WHEN_RAW_MODE( VMCPU_FF_SELM_SYNC_TSS \| VMCPU_FF_TRPM_SYNC_IDT \
599	\| VMCPU_FF_SELM_SYNC_GDT \| VMCPU_FF_SELM_SYNC_LDT, 0) )
600
601	/** High priority post-execution actions. */
602	#define VM_FF_HIGH_PRIORITY_POST_MASK ( VM_FF_PGM_NO_MEMORY )
603	/** High priority post-execution actions. */
604	#define VMCPU_FF_HIGH_PRIORITY_POST_MASK ( VMCPU_FF_PDM_CRITSECT \| VM_WHEN_RAW_MODE(VMCPU_FF_CSAM_PENDING_ACTION, 0) \
605	\| VMCPU_FF_HM_UPDATE_CR3 \| VMCPU_FF_HM_UPDATE_PAE_PDPES \
606	\| VMCPU_FF_IEM \| VMCPU_FF_IOM )
607
608	/** Normal priority VM post-execution actions. */
609	#define VM_FF_NORMAL_PRIORITY_POST_MASK ( VM_FF_CHECK_VM_STATE \| VM_FF_DBGF \| VM_FF_RESET \
610	\| VM_FF_PGM_NO_MEMORY \| VM_FF_EMT_RENDEZVOUS)
611	/** Normal priority VMCPU post-execution actions. */
612	#define VMCPU_FF_NORMAL_PRIORITY_POST_MASK ( VM_WHEN_RAW_MODE(VMCPU_FF_CSAM_SCAN_PAGE, 0) \| VMCPU_FF_DBGF )
613
614	/** Normal priority VM actions. */
615	#define VM_FF_NORMAL_PRIORITY_MASK ( VM_FF_REQUEST \| VM_FF_PDM_QUEUES \| VM_FF_PDM_DMA \
616	\| VM_FF_REM_HANDLER_NOTIFY \| VM_FF_EMT_RENDEZVOUS)
617	/** Normal priority VMCPU actions. */
618	#define VMCPU_FF_NORMAL_PRIORITY_MASK ( VMCPU_FF_REQUEST )
619
620	/** Flags to clear before resuming guest execution. */
621	#define VMCPU_FF_RESUME_GUEST_MASK ( VMCPU_FF_TO_R3 )
622
623
624	/** VM flags that cause the REP[\|NE\|E] STRINS loops to yield immediately. */
625	#define VM_FF_HIGH_PRIORITY_POST_REPSTR_MASK ( VM_FF_TM_VIRTUAL_SYNC \| VM_FF_PGM_NEED_HANDY_PAGES \| VM_FF_PGM_NO_MEMORY \
626	\| VM_FF_EMT_RENDEZVOUS \| VM_FF_PGM_POOL_FLUSH_PENDING \| VM_FF_RESET)
627	/** VM flags that cause the REP[\|NE\|E] STRINS loops to yield. */
628	#define VM_FF_YIELD_REPSTR_MASK ( VM_FF_HIGH_PRIORITY_POST_REPSTR_MASK \
629	\| VM_FF_PDM_QUEUES \| VM_FF_PDM_DMA \| VM_FF_DBGF \| VM_FF_DEBUG_SUSPEND )
630	/** VMCPU flags that cause the REP[\|NE\|E] STRINS loops to yield immediately. */
631	#ifdef IN_RING3
632	# define VMCPU_FF_HIGH_PRIORITY_POST_REPSTR_MASK ( VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL \| VMCPU_FF_DBGF \
633	\| VMCPU_FF_VMX_MTF )
634	#else
635	# define VMCPU_FF_HIGH_PRIORITY_POST_REPSTR_MASK ( VMCPU_FF_TO_R3 \| VMCPU_FF_IEM \| VMCPU_FF_IOM \| VMCPU_FF_PGM_SYNC_CR3 \
636	\| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL \| VMCPU_FF_DBGF \| VMCPU_FF_VMX_MTF )
637	#endif
638	/** VMCPU flags that cause the REP[\|NE\|E] STRINS loops to yield, interrupts
639	* enabled. */
640	#define VMCPU_FF_YIELD_REPSTR_MASK ( VMCPU_FF_HIGH_PRIORITY_POST_REPSTR_MASK \
641	\| VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_UPDATE_APIC \| VMCPU_FF_INTERRUPT_PIC \
642	\| VMCPU_FF_INTERRUPT_NMI \| VMCPU_FF_INTERRUPT_SMI \| VMCPU_FF_PDM_CRITSECT \
643	\| VMCPU_FF_TIMER \| VMCPU_FF_REQUEST \
644	\| VMCPU_FF_INTERRUPT_NESTED_GUEST )
645	/** VMCPU flags that cause the REP[\|NE\|E] STRINS loops to yield, interrupts
646	* disabled. */
647	#define VMCPU_FF_YIELD_REPSTR_NOINT_MASK ( VMCPU_FF_YIELD_REPSTR_MASK \
648	& ~( VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_UPDATE_APIC \| VMCPU_FF_INTERRUPT_PIC \
649	\| VMCPU_FF_INTERRUPT_NESTED_GUEST) )
650
651	/** VM Flags that cause the HM loops to go back to ring-3. */
652	#define VM_FF_HM_TO_R3_MASK ( VM_FF_TM_VIRTUAL_SYNC \| VM_FF_PGM_NEED_HANDY_PAGES \| VM_FF_PGM_NO_MEMORY \
653	\| VM_FF_PDM_QUEUES \| VM_FF_EMT_RENDEZVOUS)
654	/** VMCPU Flags that cause the HM loops to go back to ring-3. */
655	#define VMCPU_FF_HM_TO_R3_MASK ( VMCPU_FF_TO_R3 \| VMCPU_FF_TIMER \| VMCPU_FF_PDM_CRITSECT \
656	\| VMCPU_FF_IEM \| VMCPU_FF_IOM)
657
658	/** High priority ring-0 VM pre HM-mode execution mask. */
659	#define VM_FF_HP_R0_PRE_HM_MASK (VM_FF_HM_TO_R3_MASK \| VM_FF_REQUEST \| VM_FF_PGM_POOL_FLUSH_PENDING \| VM_FF_PDM_DMA)
660	/** High priority ring-0 VMCPU pre HM-mode execution mask. */
661	#define VMCPU_FF_HP_R0_PRE_HM_MASK ( VMCPU_FF_HM_TO_R3_MASK \| VMCPU_FF_PGM_SYNC_CR3 \
662	\| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL \| VMCPU_FF_REQUEST)
663	/** High priority ring-0 VM pre HM-mode execution mask, single stepping. */
664	#define VM_FF_HP_R0_PRE_HM_STEP_MASK (VM_FF_HP_R0_PRE_HM_MASK & ~( VM_FF_TM_VIRTUAL_SYNC \| VM_FF_PDM_QUEUES \
665	\| VM_FF_EMT_RENDEZVOUS \| VM_FF_REQUEST \
666	\| VM_FF_PDM_DMA) )
667	/** High priority ring-0 VMCPU pre HM-mode execution mask, single stepping. */
668	#define VMCPU_FF_HP_R0_PRE_HM_STEP_MASK (VMCPU_FF_HP_R0_PRE_HM_MASK & ~( VMCPU_FF_TO_R3 \| VMCPU_FF_TIMER \
669	\| VMCPU_FF_PDM_CRITSECT \| VMCPU_FF_REQUEST) )
670
671	/** All the forced VM flags. */
672	#define VM_FF_ALL_MASK (UINT32_MAX)
673	/** All the forced VMCPU flags. */
674	#define VMCPU_FF_ALL_MASK (UINT32_MAX)
675
676	/** All the forced VM flags except those related to raw-mode and hardware
677	* assisted execution. */
678	#define VM_FF_ALL_REM_MASK (~(VM_FF_HIGH_PRIORITY_PRE_RAW_MASK) \| VM_FF_PGM_NEED_HANDY_PAGES \| VM_FF_PGM_NO_MEMORY)
679	/** All the forced VMCPU flags except those related to raw-mode and hardware
680	* assisted execution. */
681	#define VMCPU_FF_ALL_REM_MASK (~( VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK \| VMCPU_FF_PDM_CRITSECT \
682	\| VMCPU_FF_TLB_FLUSH \| VM_WHEN_RAW_MODE(VMCPU_FF_CSAM_PENDING_ACTION, 0) ))
683	/** @} */
684
685	/** @def VM_FF_SET
686	* Sets a single force action flag.
687	*
688	* @param pVM The cross context VM structure.
689	* @param fFlag The flag to set.
690	*/
691	#define VM_FF_SET(pVM, fFlag) do { \
692	AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
693	AssertCompile((fFlag) == RT_BIT_32(fFlag##_BIT)); \
694	ASMAtomicOrU32(&(pVM)->fGlobalForcedActions, (fFlag)); \
695	} while (0)
696
697	/** @def VMCPU_FF_SET
698	* Sets a single force action flag for the given VCPU.
699	*
700	* @param pVCpu The cross context virtual CPU structure.
701	* @param fFlag The flag to set.
702	* @sa VMCPU_FF_SET_MASK
703	*/
704	#ifdef VMCPU_WITH_64_BIT_FFS
705	# define VMCPU_FF_SET(pVCpu, fFlag) do { \
706	AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
707	AssertCompile((fFlag) == RT_BIT_64(fFlag##_BIT)); \
708	ASMAtomicBitSet(&(pVCpu)->fLocalForcedActions, fFlag##_BIT); \
709	} while (0)
710	#else
711	# define VMCPU_FF_SET(pVCpu, fFlag) do { \
712	AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
713	AssertCompile((fFlag) == RT_BIT_32(fFlag##_BIT)); \
714	ASMAtomicOrU32(&(pVCpu)->fLocalForcedActions, (fFlag)); \
715	} while (0)
716	#endif
717
718	/** @def VMCPU_FF_SET_MASK
719	* Sets a two or more force action flag for the given VCPU.
720	*
721	* @param pVCpu The cross context virtual CPU structure.
722	* @param fFlags The flags to set.
723	* @sa VMCPU_FF_SET
724	*/
725	#ifdef VMCPU_WITH_64_BIT_FFS
726	# if ARCH_BITS > 32
727	# define VMCPU_FF_SET_MASK(pVCpu, fFlags) \
728	do { ASMAtomicOrU64(&pVCpu->fLocalForcedActions, (fFlags)); } while (0)
729	# else
730	# define VMCPU_FF_SET_MASK(pVCpu, fFlags) do { \
731	if (!((fFlags) >> 32)) ASMAtomicOrU32((uint32_t volatile *)&pVCpu->fLocalForcedActions, (uint32_t)(fFlags)); \
732	else ASMAtomicOrU64(&pVCpu->fLocalForcedActions, (fFlags)); \
733	} while (0)
734	# endif
735	#else
736	# define VMCPU_FF_SET_MASK(pVCpu, fFlags) \
737	do { ASMAtomicOrU32(&pVCpu->fLocalForcedActions, (fFlags)); } while (0)
738	#endif
739
740	/** @def VM_FF_CLEAR
741	* Clears a single force action flag.
742	*
743	* @param pVM The cross context VM structure.
744	* @param fFlag The flag to clear.
745	*/
746	#define VM_FF_CLEAR(pVM, fFlag) do { \
747	AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
748	AssertCompile((fFlag) == RT_BIT_32(fFlag##_BIT)); \
749	ASMAtomicAndU32(&(pVM)->fGlobalForcedActions, ~(fFlag)); \
750	} while (0)
751
752	/** @def VMCPU_FF_CLEAR
753	* Clears a single force action flag for the given VCPU.
754	*
755	* @param pVCpu The cross context virtual CPU structure.
756	* @param fFlag The flag to clear.
757	*/
758	#ifdef VMCPU_WITH_64_BIT_FFS
759	# define VMCPU_FF_CLEAR(pVCpu, fFlag) do { \
760	AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
761	AssertCompile((fFlag) == RT_BIT_64(fFlag##_BIT)); \
762	ASMAtomicBitClear(&(pVCpu)->fLocalForcedActions, fFlag##_BIT); \
763	} while (0)
764	#else
765	# define VMCPU_FF_CLEAR(pVCpu, fFlag) do { \
766	AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
767	AssertCompile((fFlag) == RT_BIT_32(fFlag##_BIT)); \
768	ASMAtomicAndU32(&(pVCpu)->fLocalForcedActions, ~(fFlag)); \
769	} while (0)
770	#endif
771
772	/** @def VMCPU_FF_CLEAR_MASK
773	* Clears two or more force action flags for the given VCPU.
774	*
775	* @param pVCpu The cross context virtual CPU structure.
776	* @param fFlags The flags to clear.
777	*/
778	#ifdef VMCPU_WITH_64_BIT_FFS
779	# if ARCH_BITS > 32
780	# define VMCPU_FF_CLEAR_MASK(pVCpu, fFlags) \
781	do { ASMAtomicAndU64(&(pVCpu)->fLocalForcedActions, ~(fFlags)); } while (0)
782	# else
783	# define VMCPU_FF_CLEAR_MASK(pVCpu, fFlags) do { \
784	if (!((fFlags) >> 32)) ASMAtomicAndU32((uint32_t volatile *)&(pVCpu)->fLocalForcedActions, ~(uint32_t)(fFlags)); \
785	else ASMAtomicAndU64(&(pVCpu)->fLocalForcedActions, ~(fFlags)); \
786	} while (0)
787	# endif
788	#else
789	# define VMCPU_FF_CLEAR_MASK(pVCpu, fFlags) \
790	do { ASMAtomicAndU32(&(pVCpu)->fLocalForcedActions, ~(fFlags)); } while (0)
791	#endif
792
793	/** @def VM_FF_IS_SET
794	* Checks if single a force action flag is set.
795	*
796	* @param pVM The cross context VM structure.
797	* @param fFlag The flag to check.
798	* @sa VM_FF_IS_ANY_SET
799	*/
800	#if !defined(VBOX_STRICT) \|\| !defined(RT_COMPILER_SUPPORTS_LAMBDA)
801	# define VM_FF_IS_SET(pVM, fFlag) RT_BOOL((pVM)->fGlobalForcedActions & (fFlag))
802	#else
803	# define VM_FF_IS_SET(pVM, fFlag) \
804	([](PVM a_pVM) -> bool \
805	{ \
806	AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
807	AssertCompile((fFlag) == RT_BIT_32(fFlag##_BIT)); \
808	return RT_BOOL(a_pVM->fGlobalForcedActions & (fFlag)); \
809	}(pVM))
810	#endif
811
812	/** @def VMCPU_FF_IS_SET
813	* Checks if a single force action flag is set for the given VCPU.
814	*
815	* @param pVCpu The cross context virtual CPU structure.
816	* @param fFlag The flag to check.
817	* @sa VMCPU_FF_IS_ANY_SET
818	*/
819	#if !defined(VBOX_STRICT) \|\| !defined(RT_COMPILER_SUPPORTS_LAMBDA)
820	# define VMCPU_FF_IS_SET(pVCpu, fFlag) RT_BOOL((pVCpu)->fLocalForcedActions & (fFlag))
821	#else
822	# define VMCPU_FF_IS_SET(pVCpu, fFlag) \
823	([](PVMCPU a_pVCpu) -> bool \
824	{ \
825	AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
826	AssertCompile((fFlag) == RT_BIT_64(fFlag##_BIT)); \
827	return RT_BOOL(a_pVCpu->fLocalForcedActions & (fFlag)); \
828	}(pVCpu))
829	#endif
830
831	/** @def VM_FF_IS_ANY_SET
832	* Checks if one or more force action in the specified set is pending.
833	*
834	* @param pVM The cross context VM structure.
835	* @param fFlags The flags to check for.
836	* @sa VM_FF_IS_SET
837	*/
838	#define VM_FF_IS_ANY_SET(pVM, fFlags) RT_BOOL((pVM)->fGlobalForcedActions & (fFlags))
839
840	/** @def VMCPU_FF_IS_ANY_SET
841	* Checks if two or more force action flags in the specified set is set for the given VCPU.
842	*
843	* @param pVCpu The cross context virtual CPU structure.
844	* @param fFlags The flags to check for.
845	* @sa VMCPU_FF_IS_SET
846	*/
847	#define VMCPU_FF_IS_ANY_SET(pVCpu, fFlags) RT_BOOL((pVCpu)->fLocalForcedActions & (fFlags))
848
849	/** @def VM_FF_TEST_AND_CLEAR
850	* Checks if one (!) force action in the specified set is pending and clears it atomically
851	*
852	* @returns true if the bit was set.
853	* @returns false if the bit was clear.
854	* @param pVM The cross context VM structure.
855	* @param fFlag Flag constant to check and clear (_BIT is appended).
856	*/
857	#define VM_FF_TEST_AND_CLEAR(pVM, fFlag) (ASMAtomicBitTestAndClear(&(pVM)->fGlobalForcedActions, fFlag##_BIT))
858
859	/** @def VMCPU_FF_TEST_AND_CLEAR
860	* Checks if one (!) force action in the specified set is pending and clears it atomically
861	*
862	* @returns true if the bit was set.
863	* @returns false if the bit was clear.
864	* @param pVCpu The cross context virtual CPU structure.
865	* @param fFlag Flag constant to check and clear (_BIT is appended).
866	*/
867	#define VMCPU_FF_TEST_AND_CLEAR(pVCpu, fFlag) (ASMAtomicBitTestAndClear(&(pVCpu)->fLocalForcedActions, fFlag##_BIT))
868
869	/** @def VM_FF_IS_PENDING_EXCEPT
870	* Checks if one or more force action in the specified set is pending while one
871	* or more other ones are not.
872	*
873	* @param pVM The cross context VM structure.
874	* @param fFlags The flags to check for.
875	* @param fExcpt The flags that should not be set.
876	*/
877	#define VM_FF_IS_PENDING_EXCEPT(pVM, fFlags, fExcpt) \
878	( ((pVM)->fGlobalForcedActions & (fFlags)) && !((pVM)->fGlobalForcedActions & (fExcpt)) )
879
880	/** @def VM_IS_EMT
881	* Checks if the current thread is the emulation thread (EMT).
882	*
883	* @remark The ring-0 variation will need attention if we expand the ring-0
884	* code to let threads other than EMT mess around with the VM.
885	*/
886	#ifdef IN_RC
887	# define VM_IS_EMT(pVM) true
888	#else
889	# define VM_IS_EMT(pVM) (VMMGetCpu(pVM) != NULL)
890	#endif
891
892	/** @def VMCPU_IS_EMT
893	* Checks if the current thread is the emulation thread (EMT) for the specified
894	* virtual CPU.
895	*/
896	#ifdef IN_RC
897	# define VMCPU_IS_EMT(pVCpu) true
898	#else
899	# define VMCPU_IS_EMT(pVCpu) ((pVCpu) && ((pVCpu) == VMMGetCpu((pVCpu)->CTX_SUFF(pVM))))
900	#endif
901
902	/** @def VM_ASSERT_EMT
903	* Asserts that the current thread IS the emulation thread (EMT).
904	*/
905	#ifdef IN_RC
906	# define VM_ASSERT_EMT(pVM) Assert(VM_IS_EMT(pVM))
907	#elif defined(IN_RING0)
908	# define VM_ASSERT_EMT(pVM) Assert(VM_IS_EMT(pVM))
909	#else
910	# define VM_ASSERT_EMT(pVM) \
911	AssertMsg(VM_IS_EMT(pVM), \
912	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd\n", RTThreadNativeSelf(), VMR3GetVMCPUNativeThread(pVM)))
913	#endif
914
915	/** @def VMCPU_ASSERT_EMT
916	* Asserts that the current thread IS the emulation thread (EMT) of the
917	* specified virtual CPU.
918	*/
919	#ifdef IN_RC
920	# define VMCPU_ASSERT_EMT(pVCpu) Assert(VMCPU_IS_EMT(pVCpu))
921	#elif defined(IN_RING0)
922	# define VMCPU_ASSERT_EMT(pVCpu) AssertMsg(VMCPU_IS_EMT(pVCpu), \
923	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd idCpu=%u\n", \
924	RTThreadNativeSelf(), (pVCpu) ? (pVCpu)->hNativeThreadR0 : 0, \
925	(pVCpu) ? (pVCpu)->idCpu : 0))
926	#else
927	# define VMCPU_ASSERT_EMT(pVCpu) AssertMsg(VMCPU_IS_EMT(pVCpu), \
928	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd idCpu=%#x\n", \
929	RTThreadNativeSelf(), (pVCpu)->hNativeThread, (pVCpu)->idCpu))
930	#endif
931
932	/** @def VM_ASSERT_EMT_RETURN
933	* Asserts that the current thread IS the emulation thread (EMT) and returns if it isn't.
934	*/
935	#ifdef IN_RC
936	# define VM_ASSERT_EMT_RETURN(pVM, rc) AssertReturn(VM_IS_EMT(pVM), (rc))
937	#elif defined(IN_RING0)
938	# define VM_ASSERT_EMT_RETURN(pVM, rc) AssertReturn(VM_IS_EMT(pVM), (rc))
939	#else
940	# define VM_ASSERT_EMT_RETURN(pVM, rc) \
941	AssertMsgReturn(VM_IS_EMT(pVM), \
942	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd\n", RTThreadNativeSelf(), VMR3GetVMCPUNativeThread(pVM)), \
943	(rc))
944	#endif
945
946	/** @def VMCPU_ASSERT_EMT_RETURN
947	* Asserts that the current thread IS the emulation thread (EMT) and returns if it isn't.
948	*/
949	#ifdef IN_RC
950	# define VMCPU_ASSERT_EMT_RETURN(pVCpu, rc) AssertReturn(VMCPU_IS_EMT(pVCpu), (rc))
951	#elif defined(IN_RING0)
952	# define VMCPU_ASSERT_EMT_RETURN(pVCpu, rc) AssertReturn(VMCPU_IS_EMT(pVCpu), (rc))
953	#else
954	# define VMCPU_ASSERT_EMT_RETURN(pVCpu, rc) \
955	AssertMsgReturn(VMCPU_IS_EMT(pVCpu), \
956	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd idCpu=%#x\n", \
957	RTThreadNativeSelf(), (pVCpu)->hNativeThread, (pVCpu)->idCpu), \
958	(rc))
959	#endif
960
961	/** @def VMCPU_ASSERT_EMT_OR_GURU
962	* Asserts that the current thread IS the emulation thread (EMT) of the
963	* specified virtual CPU.
964	*/
965	#if defined(IN_RC) \|\| defined(IN_RING0)
966	# define VMCPU_ASSERT_EMT_OR_GURU(pVCpu) Assert( VMCPU_IS_EMT(pVCpu) \
967	\|\| pVCpu->CTX_SUFF(pVM)->enmVMState == VMSTATE_GURU_MEDITATION \
968	\|\| pVCpu->CTX_SUFF(pVM)->enmVMState == VMSTATE_GURU_MEDITATION_LS )
969	#else
970	# define VMCPU_ASSERT_EMT_OR_GURU(pVCpu) \
971	AssertMsg( VMCPU_IS_EMT(pVCpu) \
972	\|\| pVCpu->CTX_SUFF(pVM)->enmVMState == VMSTATE_GURU_MEDITATION \
973	\|\| pVCpu->CTX_SUFF(pVM)->enmVMState == VMSTATE_GURU_MEDITATION_LS, \
974	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd idCpu=%#x\n", \
975	RTThreadNativeSelf(), (pVCpu)->hNativeThread, (pVCpu)->idCpu))
976	#endif
977
978	/** @def VMCPU_ASSERT_EMT_OR_NOT_RUNNING
979	* Asserts that the current thread IS the emulation thread (EMT) of the
980	* specified virtual CPU or the VM is not running.
981	*/
982	#if defined(IN_RC) \|\| defined(IN_RING0)
983	# define VMCPU_ASSERT_EMT_OR_NOT_RUNNING(pVCpu) \
984	Assert( VMCPU_IS_EMT(pVCpu) \
985	\|\| !VM_IS_RUNNING_FOR_ASSERTIONS_ONLY((pVCpu)->CTX_SUFF(pVM)) )
986	#else
987	# define VMCPU_ASSERT_EMT_OR_NOT_RUNNING(pVCpu) \
988	AssertMsg( VMCPU_IS_EMT(pVCpu) \
989	\|\| !VM_IS_RUNNING_FOR_ASSERTIONS_ONLY((pVCpu)->CTX_SUFF(pVM)), \
990	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd idCpu=%#x\n", \
991	RTThreadNativeSelf(), (pVCpu)->hNativeThread, (pVCpu)->idCpu))
992	#endif
993
994	/** @def VMSTATE_IS_RUNNING
995	* Checks if the given state indicates a running VM.
996	*/
997	#define VMSTATE_IS_RUNNING(a_enmVMState) \
998	( (enmVMState) == VMSTATE_RUNNING \
999	\|\| (enmVMState) == VMSTATE_RUNNING_LS \
1000	\|\| (enmVMState) == VMSTATE_RUNNING_FT )
1001
1002	/** @def VM_IS_RUNNING_FOR_ASSERTIONS_ONLY
1003	* Checks if the VM is running.
1004	* @note This is only for pure debug assertions. No AssertReturn or similar!
1005	* @sa VMSTATE_IS_RUNNING
1006	*/
1007	#define VM_IS_RUNNING_FOR_ASSERTIONS_ONLY(pVM) \
1008	( (pVM)->enmVMState == VMSTATE_RUNNING \
1009	\|\| (pVM)->enmVMState == VMSTATE_RUNNING_LS \
1010	\|\| (pVM)->enmVMState == VMSTATE_RUNNING_FT )
1011
1012	/** @def VM_ASSERT_IS_NOT_RUNNING
1013	* Asserts that the VM is not running.
1014	*/
1015	#if defined(IN_RC) \|\| defined(IN_RING0)
1016	#define VM_ASSERT_IS_NOT_RUNNING(pVM) Assert(!VM_IS_RUNNING_FOR_ASSERTIONS_ONLY(pVM))
1017	#else
1018	#define VM_ASSERT_IS_NOT_RUNNING(pVM) AssertMsg(!VM_IS_RUNNING_FOR_ASSERTIONS_ONLY(pVM), \
1019	("VM is running. enmVMState=%d\n", (pVM)->enmVMState))
1020	#endif
1021
1022	/** @def VM_ASSERT_EMT0
1023	* Asserts that the current thread IS emulation thread \#0 (EMT0).
1024	*/
1025	#define VM_ASSERT_EMT0(pVM) VMCPU_ASSERT_EMT(&(pVM)->aCpus[0])
1026
1027	/** @def VM_ASSERT_EMT0_RETURN
1028	* Asserts that the current thread IS emulation thread \#0 (EMT0) and returns if
1029	* it isn't.
1030	*/
1031	#define VM_ASSERT_EMT0_RETURN(pVM, rc) VMCPU_ASSERT_EMT_RETURN(&(pVM)->aCpus[0], (rc))
1032
1033
1034	/**
1035	* Asserts that the current thread is NOT the emulation thread.
1036	*/
1037	#define VM_ASSERT_OTHER_THREAD(pVM) \
1038	AssertMsg(!VM_IS_EMT(pVM), ("Not other thread!!\n"))
1039
1040
1041	/** @def VM_ASSERT_STATE
1042	* Asserts a certain VM state.
1043	*/
1044	#define VM_ASSERT_STATE(pVM, _enmState) \
1045	AssertMsg((pVM)->enmVMState == (_enmState), \
1046	("state %s, expected %s\n", VMGetStateName((pVM)->enmVMState), VMGetStateName(_enmState)))
1047
1048	/** @def VM_ASSERT_STATE_RETURN
1049	* Asserts a certain VM state and returns if it doesn't match.
1050	*/
1051	#define VM_ASSERT_STATE_RETURN(pVM, _enmState, rc) \
1052	AssertMsgReturn((pVM)->enmVMState == (_enmState), \
1053	("state %s, expected %s\n", VMGetStateName((pVM)->enmVMState), VMGetStateName(_enmState)), \
1054	(rc))
1055
1056	/** @def VM_IS_VALID_EXT
1057	* Asserts a the VM handle is valid for external access, i.e. not being destroy
1058	* or terminated. */
1059	#define VM_IS_VALID_EXT(pVM) \
1060	( RT_VALID_ALIGNED_PTR(pVM, PAGE_SIZE) \
1061	&& ( (unsigned)(pVM)->enmVMState < (unsigned)VMSTATE_DESTROYING \
1062	\|\| ( (unsigned)(pVM)->enmVMState == (unsigned)VMSTATE_DESTROYING \
1063	&& VM_IS_EMT(pVM))) )
1064
1065	/** @def VM_ASSERT_VALID_EXT_RETURN
1066	* Asserts a the VM handle is valid for external access, i.e. not being
1067	* destroy or terminated.
1068	*/
1069	#define VM_ASSERT_VALID_EXT_RETURN(pVM, rc) \
1070	AssertMsgReturn(VM_IS_VALID_EXT(pVM), \
1071	("pVM=%p state %s\n", (pVM), RT_VALID_ALIGNED_PTR(pVM, PAGE_SIZE) \
1072	? VMGetStateName(pVM->enmVMState) : ""), \
1073	(rc))
1074
1075	/** @def VMCPU_ASSERT_VALID_EXT_RETURN
1076	* Asserts a the VMCPU handle is valid for external access, i.e. not being
1077	* destroy or terminated.
1078	*/
1079	#define VMCPU_ASSERT_VALID_EXT_RETURN(pVCpu, rc) \
1080	AssertMsgReturn( RT_VALID_ALIGNED_PTR(pVCpu, 64) \
1081	&& RT_VALID_ALIGNED_PTR((pVCpu)->CTX_SUFF(pVM), PAGE_SIZE) \
1082	&& (unsigned)(pVCpu)->CTX_SUFF(pVM)->enmVMState < (unsigned)VMSTATE_DESTROYING, \
1083	("pVCpu=%p pVM=%p state %s\n", (pVCpu), RT_VALID_ALIGNED_PTR(pVCpu, 64) ? (pVCpu)->CTX_SUFF(pVM) : NULL, \
1084	RT_VALID_ALIGNED_PTR(pVCpu, 64) && RT_VALID_ALIGNED_PTR((pVCpu)->CTX_SUFF(pVM), PAGE_SIZE) \
1085	? VMGetStateName((pVCpu)->pVMR3->enmVMState) : ""), \
1086	(rc))
1087
1088	#endif /* !VBOX_FOR_DTRACE_LIB */
1089
1090
1091	/**
1092	* Helper that HM and NEM uses for safely modifying VM::bMainExecutionEngine.
1093	*
1094	* ONLY HM and NEM MAY USE THIS!
1095	*
1096	* @param a_pVM The cross context VM structure.
1097	* @param a_bValue The new value.
1098	* @internal
1099	*/
1100	#define VM_SET_MAIN_EXECUTION_ENGINE(a_pVM, a_bValue) \
1101	do { \
1102	const_cast<uint8_t >(&(a_pVM)->bMainExecutionEngine) = (a_bValue); \
1103	ASMCompilerBarrier(); /* just to be on the safe side */ \
1104	} while (0)
1105
1106	/**
1107	* Checks whether raw-mode is used.
1108	*
1109	* @retval true if either is used.
1110	* @retval false if software virtualization (raw-mode) is used.
1111	*
1112	* @param a_pVM The cross context VM structure.
1113	* @sa VM_IS_HM_OR_NEM_ENABLED, VM_IS_HM_ENABLED, VM_IS_NEM_ENABLED.
1114	* @internal
1115	*/
1116	#ifdef VBOX_WITH_RAW_MODE
1117	# define VM_IS_RAW_MODE_ENABLED(a_pVM) ((a_pVM)->bMainExecutionEngine == VM_EXEC_ENGINE_RAW_MODE)
1118	#else
1119	# define VM_IS_RAW_MODE_ENABLED(a_pVM) (false)
1120	#endif
1121
1122	/**
1123	* Checks whether HM (VT-x/AMD-V) or NEM is being used by this VM.
1124	*
1125	* @retval true if either is used.
1126	* @retval false if software virtualization (raw-mode) is used.
1127	*
1128	* @param a_pVM The cross context VM structure.
1129	* @sa VM_IS_RAW_MODE_ENABLED, VM_IS_HM_ENABLED, VM_IS_NEM_ENABLED.
1130	* @internal
1131	*/
1132	#define VM_IS_HM_OR_NEM_ENABLED(a_pVM) ((a_pVM)->bMainExecutionEngine != VM_EXEC_ENGINE_RAW_MODE)
1133
1134	/**
1135	* Checks whether HM is being used by this VM.
1136	*
1137	* @retval true if HM (VT-x/AMD-v) is used.
1138	* @retval false if not.
1139	*
1140	* @param a_pVM The cross context VM structure.
1141	* @sa VM_IS_NEM_ENABLED, VM_IS_RAW_MODE_ENABLED, VM_IS_HM_OR_NEM_ENABLED.
1142	* @internal
1143	*/
1144	#define VM_IS_HM_ENABLED(a_pVM) ((a_pVM)->bMainExecutionEngine == VM_EXEC_ENGINE_HW_VIRT)
1145
1146	/**
1147	* Checks whether NEM is being used by this VM.
1148	*
1149	* @retval true if a native hypervisor API is used.
1150	* @retval false if not.
1151	*
1152	* @param a_pVM The cross context VM structure.
1153	* @sa VM_IS_HM_ENABLED, VM_IS_RAW_MODE_ENABLED, VM_IS_HM_OR_NEM_ENABLED.
1154	* @internal
1155	*/
1156	#define VM_IS_NEM_ENABLED(a_pVM) ((a_pVM)->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API)
1157
1158
1159	/**
1160	* The cross context VM structure.
1161	*
1162	* It contains all the VM data which have to be available in all contexts.
1163	* Even if it contains all the data the idea is to use APIs not to modify all
1164	* the members all around the place. Therefore we make use of unions to hide
1165	* everything which isn't local to the current source module. This means we'll
1166	* have to pay a little bit of attention when adding new members to structures
1167	* in the unions and make sure to keep the padding sizes up to date.
1168	*
1169	* Run 'kmk run-struct-tests' (from src/VBox/VMM if you like) after updating!
1170	*/
1171	typedef struct VM
1172	{
1173	/** The state of the VM.
1174	* This field is read only to everyone except the VM and EM. */
1175	VMSTATE volatile enmVMState;
1176	/** Forced action flags.
1177	* See the VM_FF_* \#defines. Updated atomically.
1178	*/
1179	volatile uint32_t fGlobalForcedActions;
1180	/** Pointer to the array of page descriptors for the VM structure allocation. */
1181	R3PTRTYPE(PSUPPAGE) paVMPagesR3;
1182	/** Session handle. For use when calling SUPR0 APIs. */
1183	PSUPDRVSESSION pSession;
1184	/** Pointer to the ring-3 VM structure. */
1185	PUVM pUVM;
1186	/** Ring-3 Host Context VM Pointer. */
1187	R3PTRTYPE(struct VM *) pVMR3;
1188	/** Ring-0 Host Context VM Pointer. */
1189	R0PTRTYPE(struct VM *) pVMR0;
1190	/** Raw-mode Context VM Pointer. */
1191	RCPTRTYPE(struct VM *) pVMRC;
1192
1193	/** The GVM VM handle. Only the GVM should modify this field. */
1194	uint32_t hSelf;
1195	/** Number of virtual CPUs. */
1196	uint32_t cCpus;
1197	/** CPU excution cap (1-100) */
1198	uint32_t uCpuExecutionCap;
1199
1200	/** Size of the VM structure including the VMCPU array. */
1201	uint32_t cbSelf;
1202
1203	/** Offset to the VMCPU array starting from beginning of this structure. */
1204	uint32_t offVMCPU;
1205
1206	/**
1207	* VMMSwitcher assembly entry point returning to host context.
1208	*
1209	* Depending on how the host handles the rc status given in @a eax, this may
1210	* return and let the caller resume whatever it was doing prior to the call.
1211	*
1212	*
1213	* @param eax The return code, register.
1214	* @remark Assume interrupts disabled.
1215	* @remark This method pointer lives here because TRPM needs it.
1216	*/
1217	RTRCPTR pfnVMMRCToHostAsm/(int32_t eax)/;
1218
1219	/**
1220	* VMMSwitcher assembly entry point returning to host context without saving the
1221	* raw-mode context (hyper) registers.
1222	*
1223	* Unlike pfnVMMRC2HCAsm, this will not return to the caller. Instead it
1224	* expects the caller to save a RC context in CPUM where one might return if the
1225	* return code indicate that this is possible.
1226	*
1227	* This method pointer lives here because TRPM needs it.
1228	*
1229	* @param eax The return code, register.
1230	* @remark Assume interrupts disabled.
1231	* @remark This method pointer lives here because TRPM needs it.
1232	*/
1233	RTRCPTR pfnVMMRCToHostAsmNoReturn/(int32_t eax)/;
1234
1235	/** @name Various items that are frequently accessed.
1236	* @{ */
1237	/** The main execution engine, VM_EXEC_ENGINE_XXX.
1238	* This is set early during vmR3InitRing3 by HM or NEM. */
1239	uint8_t const bMainExecutionEngine;
1240
1241	/** Whether to recompile user mode code or run it raw/hm/nem.
1242	* In non-raw-mode both fRecompileUser and fRecompileSupervisor must be set
1243	* to recompiler stuff. */
1244	bool fRecompileUser;
1245	/** Whether to recompile supervisor mode code or run it raw/hm/nem.
1246	* In non-raw-mode both fRecompileUser and fRecompileSupervisor must be set
1247	* to recompiler stuff. */
1248	bool fRecompileSupervisor;
1249	/** Whether raw mode supports ring-1 code or not.
1250	* This will be cleared when not in raw-mode. */
1251	bool fRawRing1Enabled;
1252	/** PATM enabled flag.
1253	* This is placed here for performance reasons.
1254	* This will be cleared when not in raw-mode. */
1255	bool fPATMEnabled;
1256	/** CSAM enabled flag.
1257	* This is placed here for performance reasons.
1258	* This will be cleared when not in raw-mode. */
1259	bool fCSAMEnabled;
1260
1261	/** Hardware VM support is available and enabled.
1262	* Determined very early during init.
1263	* This is placed here for performance reasons.
1264	* @todo obsoleted by bMainExecutionEngine, eliminate. */
1265	bool fHMEnabled;
1266	/** Hardware VM support requires a minimal raw-mode context.
1267	* This is never set on 64-bit hosts, only 32-bit hosts requires it. */
1268	bool fHMNeedRawModeCtx;
1269
1270	/** Set when this VM is the master FT node.
1271	* @todo This doesn't need to be here, FTM should store it in it's own
1272	* structures instead. */
1273	bool fFaultTolerantMaster;
1274	/** Large page enabled flag.
1275	* @todo This doesn't need to be here, PGM should store it in it's own
1276	* structures instead. */
1277	bool fUseLargePages;
1278	/** @} */
1279
1280	/** Alignment padding. */
1281	uint8_t uPadding1[2];
1282
1283	/** @name Debugging
1284	* @{ */
1285	/** Raw-mode Context VM Pointer. */
1286	RCPTRTYPE(RTTRACEBUF) hTraceBufRC;
1287	/** Ring-3 Host Context VM Pointer. */
1288	R3PTRTYPE(RTTRACEBUF) hTraceBufR3;
1289	/** Ring-0 Host Context VM Pointer. */
1290	R0PTRTYPE(RTTRACEBUF) hTraceBufR0;
1291	/** @} */
1292
1293	#if HC_ARCH_BITS == 32
1294	/** Alignment padding. */
1295	uint32_t uPadding2;
1296	#endif
1297
1298	/** @name Switcher statistics (remove)
1299	* @{ */
1300	/** Profiling the total time from Qemu to GC. */
1301	STAMPROFILEADV StatTotalQemuToGC;
1302	/** Profiling the total time from GC to Qemu. */
1303	STAMPROFILEADV StatTotalGCToQemu;
1304	/** Profiling the total time spent in GC. */
1305	STAMPROFILEADV StatTotalInGC;
1306	/** Profiling the total time spent not in Qemu. */
1307	STAMPROFILEADV StatTotalInQemu;
1308	/** Profiling the VMMSwitcher code for going to GC. */
1309	STAMPROFILEADV StatSwitcherToGC;
1310	/** Profiling the VMMSwitcher code for going to HC. */
1311	STAMPROFILEADV StatSwitcherToHC;
1312	STAMPROFILEADV StatSwitcherSaveRegs;
1313	STAMPROFILEADV StatSwitcherSysEnter;
1314	STAMPROFILEADV StatSwitcherDebug;
1315	STAMPROFILEADV StatSwitcherCR0;
1316	STAMPROFILEADV StatSwitcherCR4;
1317	STAMPROFILEADV StatSwitcherJmpCR3;
1318	STAMPROFILEADV StatSwitcherRstrRegs;
1319	STAMPROFILEADV StatSwitcherLgdt;
1320	STAMPROFILEADV StatSwitcherLidt;
1321	STAMPROFILEADV StatSwitcherLldt;
1322	STAMPROFILEADV StatSwitcherTSS;
1323	/** @} */
1324
1325	/** Padding - the unions must be aligned on a 64 bytes boundary and the unions
1326	* must start at the same offset on both 64-bit and 32-bit hosts. */
1327	uint8_t abAlignment3[(HC_ARCH_BITS == 32 ? 24 : 0) + 40];
1328
1329	/** CPUM part. */
1330	union
1331	{
1332	#ifdef VMM_INCLUDED_SRC_include_CPUMInternal_h
1333	struct CPUM s;
1334	#endif
1335	#ifdef VBOX_INCLUDED_vmm_cpum_h
1336	/** Read only info exposed about the host and guest CPUs. */
1337	struct
1338	{
1339	/** Padding for hidden fields. */
1340	uint8_t abHidden0[64];
1341	/** Host CPU feature information. */
1342	CPUMFEATURES HostFeatures;
1343	/** Guest CPU feature information. */
1344	CPUMFEATURES GuestFeatures;
1345	} const ro;
1346	#endif
1347	uint8_t padding[1536]; /* multiple of 64 */
1348	} cpum;
1349
1350	/** VMM part. */
1351	union
1352	{
1353	#ifdef VMM_INCLUDED_SRC_include_VMMInternal_h
1354	struct VMM s;
1355	#endif
1356	uint8_t padding[1600]; /* multiple of 64 */
1357	} vmm;
1358
1359	/** PGM part. */
1360	union
1361	{
1362	#ifdef VMM_INCLUDED_SRC_include_PGMInternal_h
1363	struct PGM s;
1364	#endif
1365	uint8_t padding[40962+6080]; / multiple of 64 */
1366	} pgm;
1367
1368	/** HM part. */
1369	union
1370	{
1371	#ifdef VMM_INCLUDED_SRC_include_HMInternal_h
1372	struct HM s;
1373	#endif
1374	uint8_t padding[5440]; /* multiple of 64 */
1375	} hm;
1376
1377	/** TRPM part. */
1378	union
1379	{
1380	#ifdef VMM_INCLUDED_SRC_include_TRPMInternal_h
1381	struct TRPM s;
1382	#endif
1383	uint8_t padding[5248]; /* multiple of 64 */
1384	} trpm;
1385
1386	/** SELM part. */
1387	union
1388	{
1389	#ifdef VMM_INCLUDED_SRC_include_SELMInternal_h
1390	struct SELM s;
1391	#endif
1392	uint8_t padding[768]; /* multiple of 64 */
1393	} selm;
1394
1395	/** MM part. */
1396	union
1397	{
1398	#ifdef VMM_INCLUDED_SRC_include_MMInternal_h
1399	struct MM s;
1400	#endif
1401	uint8_t padding[192]; /* multiple of 64 */
1402	} mm;
1403
1404	/** PDM part. */
1405	union
1406	{
1407	#ifdef VMM_INCLUDED_SRC_include_PDMInternal_h
1408	struct PDM s;
1409	#endif
1410	uint8_t padding[1920]; /* multiple of 64 */
1411	} pdm;
1412
1413	/** IOM part. */
1414	union
1415	{
1416	#ifdef VMM_INCLUDED_SRC_include_IOMInternal_h
1417	struct IOM s;
1418	#endif
1419	uint8_t padding[896]; /* multiple of 64 */
1420	} iom;
1421
1422	/** EM part. */
1423	union
1424	{
1425	#ifdef VMM_INCLUDED_SRC_include_EMInternal_h
1426	struct EM s;
1427	#endif
1428	uint8_t padding[256]; /* multiple of 64 */
1429	} em;
1430
1431	/** NEM part. */
1432	union
1433	{
1434	#ifdef VMM_INCLUDED_SRC_include_NEMInternal_h
1435	struct NEM s;
1436	#endif
1437	uint8_t padding[128]; /* multiple of 64 */
1438	} nem;
1439
1440	/** TM part. */
1441	union
1442	{
1443	#ifdef VMM_INCLUDED_SRC_include_TMInternal_h
1444	struct TM s;
1445	#endif
1446	uint8_t padding[2496]; /* multiple of 64 */
1447	} tm;
1448
1449	/** DBGF part. */
1450	union
1451	{
1452	#ifdef VMM_INCLUDED_SRC_include_DBGFInternal_h
1453	struct DBGF s;
1454	#endif
1455	#ifdef VBOX_INCLUDED_vmm_dbgf_h
1456	/** Read only info exposed about interrupt breakpoints and selected events. */
1457	struct
1458	{
1459	/** Bitmap of enabled hardware interrupt breakpoints. */
1460	uint32_t bmHardIntBreakpoints[256 / 32];
1461	/** Bitmap of enabled software interrupt breakpoints. */
1462	uint32_t bmSoftIntBreakpoints[256 / 32];
1463	/** Bitmap of selected events.
1464	* This includes non-selectable events too for simplicity, we maintain the
1465	* state for some of these, as it may come in handy. */
1466	uint64_t bmSelectedEvents[(DBGFEVENT_END + 63) / 64];
1467	/** Enabled hardware interrupt breakpoints. */
1468	uint32_t cHardIntBreakpoints;
1469	/** Enabled software interrupt breakpoints. */
1470	uint32_t cSoftIntBreakpoints;
1471	/** The number of selected events. */
1472	uint32_t cSelectedEvents;
1473	/** The number of enabled hardware breakpoints. */
1474	uint8_t cEnabledHwBreakpoints;
1475	/** The number of enabled hardware I/O breakpoints. */
1476	uint8_t cEnabledHwIoBreakpoints;
1477	/** The number of enabled INT3 breakpoints. */
1478	uint8_t cEnabledInt3Breakpoints;
1479	uint8_t abPadding[1]; /*< Unused padding space up for grabs. /
1480	} const ro;
1481	#endif
1482	uint8_t padding[2432]; /* multiple of 64 */
1483	} dbgf;
1484
1485	/** SSM part. */
1486	union
1487	{
1488	#ifdef VMM_INCLUDED_SRC_include_SSMInternal_h
1489	struct SSM s;
1490	#endif
1491	uint8_t padding[128]; /* multiple of 64 */
1492	} ssm;
1493
1494	/** FTM part. */
1495	union
1496	{
1497	#ifdef VMM_INCLUDED_SRC_include_FTMInternal_h
1498	struct FTM s;
1499	#endif
1500	uint8_t padding[512]; /* multiple of 64 */
1501	} ftm;
1502
1503	#ifdef VBOX_WITH_RAW_MODE
1504	/** PATM part. */
1505	union
1506	{
1507	# ifdef VMM_INCLUDED_SRC_include_PATMInternal_h
1508	struct PATM s;
1509	# endif
1510	uint8_t padding[768]; /* multiple of 64 */
1511	} patm;
1512
1513	/** CSAM part. */
1514	union
1515	{
1516	# ifdef VMM_INCLUDED_SRC_include_CSAMInternal_h
1517	struct CSAM s;
1518	# endif
1519	uint8_t padding[1088]; /* multiple of 64 */
1520	} csam;
1521	#endif
1522
1523	#ifdef VBOX_WITH_REM
1524	/** REM part. */
1525	union
1526	{
1527	# ifdef VMM_INCLUDED_SRC_include_REMInternal_h
1528	struct REM s;
1529	# endif
1530	uint8_t padding[0x11100]; /* multiple of 64 */
1531	} rem;
1532	#endif
1533
1534	union
1535	{
1536	#ifdef VMM_INCLUDED_SRC_include_GIMInternal_h
1537	struct GIM s;
1538	#endif
1539	uint8_t padding[448]; /* multiple of 64 */
1540	} gim;
1541
1542	union
1543	{
1544	#ifdef VMM_INCLUDED_SRC_include_APICInternal_h
1545	struct APIC s;
1546	#endif
1547	uint8_t padding[128]; /* multiple of 8 */
1548	} apic;
1549
1550	/* ---- begin small stuff ---- */
1551
1552	/** VM part. */
1553	union
1554	{
1555	#ifdef VMM_INCLUDED_SRC_include_VMInternal_h
1556	struct VMINT s;
1557	#endif
1558	uint8_t padding[32]; /* multiple of 8 */
1559	} vm;
1560
1561	/** CFGM part. */
1562	union
1563	{
1564	#ifdef VMM_INCLUDED_SRC_include_CFGMInternal_h
1565	struct CFGM s;
1566	#endif
1567	uint8_t padding[8]; /* multiple of 8 */
1568	} cfgm;
1569
1570	/** Padding for aligning the cpu array on a page boundary. */
1571	#if defined(VBOX_WITH_REM) && defined(VBOX_WITH_RAW_MODE)
1572	uint8_t abAlignment2[3670];
1573	#elif defined(VBOX_WITH_REM) && !defined(VBOX_WITH_RAW_MODE)
1574	uint8_t abAlignment2[1430];
1575	#elif !defined(VBOX_WITH_REM) && defined(VBOX_WITH_RAW_MODE)
1576	uint8_t abAlignment2[3926];
1577	#else
1578	uint8_t abAlignment2[1686];
1579	#endif
1580
1581	/* ---- end small stuff ---- */
1582
1583	/** VMCPU array for the configured number of virtual CPUs.
1584	* Must be aligned on a page boundary for TLB hit reasons as well as
1585	* alignment of VMCPU members. */
1586	VMCPU aCpus[1];
1587	} VM;
1588
1589
1590	#ifdef IN_RC
1591	RT_C_DECLS_BEGIN
1592
1593	/** The VM structure.
1594	* This is imported from the VMMRCBuiltin module, i.e. it's a one of those magic
1595	* globals which we should avoid using.
1596	*/
1597	extern DECLIMPORT(VM) g_VM;
1598
1599	RT_C_DECLS_END
1600	#endif
1601
1602	/** @} */
1603
1604	#endif /* !VBOX_INCLUDED_vmm_vm_h */
1605

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source: vbox/trunk/include/VBox/vmm/vm.h@ 78425

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