vm.h@ 105076

Last change on this file since 105076 was 105076, checked in by vboxsync, 5 months ago
VMM/IEM: Increased the TLB size from 256 to 1024 entries. bugref:10687
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1	/** @file
2	* VM - The Virtual Machine, data.
3	*/
4
5	/*
6	* Copyright (C) 2006-2023 Oracle and/or its affiliates.
7	*
8	* This file is part of VirtualBox base platform packages, as
9	* available from https://www.virtualbox.org.
10	*
11	* This program is free software; you can redistribute it and/or
12	* modify it under the terms of the GNU General Public License
13	* as published by the Free Software Foundation, in version 3 of the
14	* License.
15	*
16	* This program is distributed in the hope that it will be useful, but
17	* WITHOUT ANY WARRANTY; without even the implied warranty of
18	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19	* General Public License for more details.
20	*
21	* You should have received a copy of the GNU General Public License
22	* along with this program; if not, see <https://www.gnu.org/licenses>.
23	*
24	* The contents of this file may alternatively be used under the terms
25	* of the Common Development and Distribution License Version 1.0
26	* (CDDL), a copy of it is provided in the "COPYING.CDDL" file included
27	* in the VirtualBox distribution, in which case the provisions of the
28	* CDDL are applicable instead of those of the GPL.
29	*
30	* You may elect to license modified versions of this file under the
31	* terms and conditions of either the GPL or the CDDL or both.
32	*
33	* SPDX-License-Identifier: GPL-3.0-only OR CDDL-1.0
34	*/
35
36	#ifndef VBOX_INCLUDED_vmm_vm_h
37	#define VBOX_INCLUDED_vmm_vm_h
38	#ifndef RT_WITHOUT_PRAGMA_ONCE
39	# pragma once
40	#endif
41
42	#ifndef VBOX_FOR_DTRACE_LIB
43	# ifndef USING_VMM_COMMON_DEFS
44	# error "Compile job does not include VMM_COMMON_DEFS from src/VBox/VMM/Config.kmk - make sure you really need to include this file!"
45	# endif
46	# include <iprt/param.h>
47	# include <VBox/param.h>
48	# include <VBox/types.h>
49	# include <VBox/vmm/cpum.h>
50	# include <VBox/vmm/stam.h>
51	# include <VBox/vmm/vmapi.h>
52	# include <VBox/vmm/vmm.h>
53	# include <VBox/sup.h>
54	#else
55	# pragma D depends_on library vbox-types.d
56	# pragma D depends_on library CPUMInternal.d
57	# define VMM_INCLUDED_SRC_include_CPUMInternal_h
58	#endif
59
60
61
62	/** @defgroup grp_vm The Virtual Machine
63	* @ingroup grp_vmm
64	* @{
65	*/
66
67	/**
68	* The state of a Virtual CPU.
69	*
70	* The basic state indicated here is whether the CPU has been started or not. In
71	* addition, there are sub-states when started for assisting scheduling (GVMM
72	* mostly).
73	*
74	* The transition out of the STOPPED state is done by a vmR3PowerOn.
75	* The transition back to the STOPPED state is done by vmR3PowerOff.
76	*
77	* (Alternatively we could let vmR3PowerOn start CPU 0 only and let the SPIP
78	* handling switch on the other CPUs. Then vmR3Reset would stop all but CPU 0.)
79	*/
80	typedef enum VMCPUSTATE
81	{
82	/** The customary invalid zero. */
83	VMCPUSTATE_INVALID = 0,
84
85	/** Virtual CPU has not yet been started. */
86	VMCPUSTATE_STOPPED,
87
88	/** CPU started. */
89	VMCPUSTATE_STARTED,
90	/** CPU started in HM context. */
91	VMCPUSTATE_STARTED_HM,
92	/** Executing guest code and can be poked (RC or STI bits of HM). */
93	VMCPUSTATE_STARTED_EXEC,
94	/** Executing guest code using NEM. */
95	VMCPUSTATE_STARTED_EXEC_NEM,
96	VMCPUSTATE_STARTED_EXEC_NEM_WAIT,
97	VMCPUSTATE_STARTED_EXEC_NEM_CANCELED,
98	/** Halted. */
99	VMCPUSTATE_STARTED_HALTED,
100
101	/** The end of valid virtual CPU states. */
102	VMCPUSTATE_END,
103
104	/** Ensure 32-bit type. */
105	VMCPUSTATE_32BIT_HACK = 0x7fffffff
106	} VMCPUSTATE;
107
108	/** Enables 64-bit FFs. */
109	#define VMCPU_WITH_64_BIT_FFS
110
111
112	/**
113	* The cross context virtual CPU structure.
114	*
115	* Run 'kmk run-struct-tests' (from src/VBox/VMM if you like) after updating!
116	*/
117	typedef struct VMCPU
118	{
119	/** @name Volatile per-cpu data.
120	* @{ */
121	/** Per CPU forced action.
122	* See the VMCPU_FF_* \#defines. Updated atomically. */
123	#ifdef VMCPU_WITH_64_BIT_FFS
124	uint64_t volatile fLocalForcedActions;
125	#else
126	uint32_t volatile fLocalForcedActions;
127	uint32_t fForLocalForcedActionsExpansion;
128	#endif
129	/** The CPU state. */
130	VMCPUSTATE volatile enmState;
131
132	#if defined(VBOX_VMM_TARGET_ARMV8)
133	uint32_t u32Alignment0;
134	/** The number of nano seconds when the vTimer of the associated vCPU is supposed to activate
135	* required to get out of a halt (due to wfi/wfe).
136	*
137	* @note This actually should go into TMCPU but this drags in a whole lot of padding changes
138	* and I'm not sure yet whether this will remain in this form anyway.
139	*/
140	uint64_t cNsVTimerActivate;
141	/** Padding up to 64 bytes. */
142	uint8_t abAlignment0[64 - 12 - 8 - 4];
143	#else
144	/** Padding up to 64 bytes. */
145	uint8_t abAlignment0[64 - 12];
146	#endif
147	/** @} */
148
149	/** IEM part.
150	* @remarks This comes first as it allows the use of 8-bit immediates for the
151	* first 64 bytes of the structure, reducing code size a wee bit. */
152	#if defined(VMM_INCLUDED_SRC_include_IEMInternal_h) \|\| defined(VMM_INCLUDED_SRC_include_IEMInternal_armv8_h) /* For PDB hacking. */
153	union VMCPUUNIONIEMFULL
154	#else
155	union VMCPUUNIONIEMSTUB
156	#endif
157	{
158	#if defined(VMM_INCLUDED_SRC_include_IEMInternal_h) \|\| defined(VMM_INCLUDED_SRC_include_IEMInternal_armv8_h)
159	struct IEMCPU s;
160	#endif
161	uint8_t padding[244672]; /* multiple of 64 */
162	} iem;
163
164	/** @name Static per-cpu data.
165	* (Putting this after IEM, hoping that it's less frequently used than it.)
166	* @{ */
167	/** Ring-3 Host Context VM Pointer. */
168	PVMR3 pVMR3;
169	/** Ring-0 Host Context VM Pointer, currently used by VTG/dtrace. */
170	RTR0PTR pVCpuR0ForVtg;
171	/** Raw-mode Context VM Pointer. */
172	uint32_t pVMRC;
173	/** Padding for new raw-mode (long mode). */
174	uint32_t pVMRCPadding;
175	/** Pointer to the ring-3 UVMCPU structure. */
176	PUVMCPU pUVCpu;
177	/** The native thread handle. */
178	RTNATIVETHREAD hNativeThread;
179	/** The native R0 thread handle. (different from the R3 handle!) */
180	RTNATIVETHREAD hNativeThreadR0;
181	/** The IPRT thread handle (for VMMDevTesting). */
182	RTTHREAD hThread;
183	/** The CPU ID.
184	* This is the index into the VM::aCpu array. */
185	#ifdef IN_RING0
186	VMCPUID idCpuUnsafe;
187	#else
188	VMCPUID idCpu;
189	#endif
190
191	/** Align the structures below bit on a 64-byte boundary and make sure it starts
192	* at the same offset in both 64-bit and 32-bit builds.
193	*
194	* @remarks The alignments of the members that are larger than 48 bytes should be
195	* 64-byte for cache line reasons. structs containing small amounts of
196	* data could be lumped together at the end with a < 64 byte padding
197	* following it (to grow into and align the struct size).
198	*/
199	uint8_t abAlignment1[64 - 6 * (HC_ARCH_BITS == 32 ? 4 : 8) - 8 - 4];
200	/** @} */
201
202	/** HM part. */
203	union VMCPUUNIONHM
204	{
205	#ifdef VMM_INCLUDED_SRC_include_HMInternal_h
206	struct HMCPU s;
207	#endif
208	uint8_t padding[9984]; /* multiple of 64 */
209	} hm;
210
211	/** NEM part. */
212	union VMCPUUNIONNEM
213	{
214	#ifdef VMM_INCLUDED_SRC_include_NEMInternal_h
215	struct NEMCPU s;
216	#endif
217	uint8_t padding[4608]; /* multiple of 64 */
218	} nem;
219
220	/** TRPM part. */
221	union VMCPUUNIONTRPM
222	{
223	#ifdef VMM_INCLUDED_SRC_include_TRPMInternal_h
224	struct TRPMCPU s;
225	#endif
226	uint8_t padding[128]; /* multiple of 64 */
227	} trpm;
228
229	/** TM part. */
230	union VMCPUUNIONTM
231	{
232	#ifdef VMM_INCLUDED_SRC_include_TMInternal_h
233	struct TMCPU s;
234	#endif
235	uint8_t padding[5760]; /* multiple of 64 */
236	} tm;
237
238	/** VMM part. */
239	union VMCPUUNIONVMM
240	{
241	#ifdef VMM_INCLUDED_SRC_include_VMMInternal_h
242	struct VMMCPU s;
243	#endif
244	uint8_t padding[9536]; /* multiple of 64 */
245	} vmm;
246
247	/** PDM part. */
248	union VMCPUUNIONPDM
249	{
250	#ifdef VMM_INCLUDED_SRC_include_PDMInternal_h
251	struct PDMCPU s;
252	#endif
253	uint8_t padding[256]; /* multiple of 64 */
254	} pdm;
255
256	/** IOM part. */
257	union VMCPUUNIONIOM
258	{
259	#ifdef VMM_INCLUDED_SRC_include_IOMInternal_h
260	struct IOMCPU s;
261	#endif
262	uint8_t padding[512]; /* multiple of 64 */
263	} iom;
264
265	/** DBGF part.
266	* @todo Combine this with other tiny structures. */
267	union VMCPUUNIONDBGF
268	{
269	#ifdef VMM_INCLUDED_SRC_include_DBGFInternal_h
270	struct DBGFCPU s;
271	#endif
272	uint8_t padding[512]; /* multiple of 64 */
273	} dbgf;
274
275	/** GIM part. */
276	union VMCPUUNIONGIM
277	{
278	#ifdef VMM_INCLUDED_SRC_include_GIMInternal_h
279	struct GIMCPU s;
280	#endif
281	uint8_t padding[512]; /* multiple of 64 */
282	} gim;
283
284	#if defined(VBOX_VMM_TARGET_ARMV8)
285	/** GIC part. */
286	union VMCPUUNIONGIC
287	{
288	# ifdef VMM_INCLUDED_SRC_include_GICInternal_h
289	struct GICCPU s;
290	# endif
291	uint8_t padding[3840]; /* multiple of 64 */
292	} gic;
293	#else
294	/** APIC part. */
295	union VMCPUUNIONAPIC
296	{
297	# ifdef VMM_INCLUDED_SRC_include_APICInternal_h
298	struct APICCPU s;
299	# endif
300	uint8_t padding[3840]; /* multiple of 64 */
301	} apic;
302	#endif
303
304	/*
305	* Some less frequently used global members that doesn't need to take up
306	* precious space at the head of the structure.
307	*/
308
309	/** Trace groups enable flags. */
310	uint32_t fTraceGroups; /* 64 / 44 */
311	/** Number of collisions hashing the ring-0 EMT handle. */
312	uint8_t cEmtHashCollisions;
313	uint8_t abAdHoc[3];
314	/** Profiling samples for use by ad hoc profiling. */
315	STAMPROFILEADV aStatAdHoc[8]; /* size: 408 = 320 /
316
317	/** Align the following members on page boundary. */
318	uint8_t abAlignment2[1848];
319
320	/** PGM part. */
321	union VMCPUUNIONPGM
322	{
323	#ifdef VMM_INCLUDED_SRC_include_PGMInternal_h
324	struct PGMCPU s;
325	#endif
326	uint8_t padding[36864]; /* multiple of 4096 */
327	} pgm;
328
329	/** CPUM part. */
330	union VMCPUUNIONCPUM
331	{
332	#if defined(VMM_INCLUDED_SRC_include_CPUMInternal_h) \|\| defined(VMM_INCLUDED_SRC_include_CPUMInternal_armv8_h)
333	struct CPUMCPU s;
334	#endif
335	#ifdef VMCPU_INCL_CPUM_GST_CTX
336	/** The guest CPUM context for direct use by execution engines.
337	* This is not for general consumption, but for HM, REM, IEM, and maybe a few
338	* others. The rest will use the function based CPUM API. */
339	CPUMCTX GstCtx;
340	#endif
341	uint8_t padding[102400]; /* multiple of 4096 */
342	} cpum;
343
344	/** EM part. */
345	union VMCPUUNIONEM
346	{
347	#ifdef VMM_INCLUDED_SRC_include_EMInternal_h
348	struct EMCPU s;
349	#endif
350	uint8_t padding[40960]; /* multiple of 4096 */
351	} em;
352	uint8_t abPadding[12288];
353	} VMCPU;
354
355
356	#ifndef VBOX_FOR_DTRACE_LIB
357	# ifndef IN_TSTVMSTRUCT
358	/* Make sure the structure size is aligned on a 16384 boundary for arm64 purposes. */
359	AssertCompileSizeAlignment(VMCPU, 16384);
360	# endif
361
362	/** @name Operations on VMCPU::enmState
363	* @{ */
364	/** Gets the VMCPU state. */
365	#define VMCPU_GET_STATE(pVCpu) ( (pVCpu)->enmState )
366	/** Sets the VMCPU state. */
367	#define VMCPU_SET_STATE(pVCpu, enmNewState) \
368	ASMAtomicWriteU32((uint32_t volatile *)&(pVCpu)->enmState, (enmNewState))
369	/** Cmpares and sets the VMCPU state. */
370	#define VMCPU_CMPXCHG_STATE(pVCpu, enmNewState, enmOldState) \
371	ASMAtomicCmpXchgU32((uint32_t volatile *)&(pVCpu)->enmState, (enmNewState), (enmOldState))
372	/** Checks the VMCPU state. */
373	#ifdef VBOX_STRICT
374	# define VMCPU_ASSERT_STATE(pVCpu, enmExpectedState) \
375	do { \
376	VMCPUSTATE enmState = VMCPU_GET_STATE(pVCpu); \
377	AssertMsg(enmState == (enmExpectedState), \
378	("enmState=%d enmExpectedState=%d idCpu=%u\n", \
379	enmState, enmExpectedState, (pVCpu)->idCpu)); \
380	} while (0)
381
382	# define VMCPU_ASSERT_STATE_2(pVCpu, enmExpectedState, a_enmExpectedState2) \
383	do { \
384	VMCPUSTATE enmState = VMCPU_GET_STATE(pVCpu); \
385	AssertMsg( enmState == (enmExpectedState) \
386	\|\| enmState == (a_enmExpectedState2), \
387	("enmState=%d enmExpectedState=%d enmExpectedState2=%d idCpu=%u\n", \
388	enmState, enmExpectedState, a_enmExpectedState2, (pVCpu)->idCpu)); \
389	} while (0)
390	#else
391	# define VMCPU_ASSERT_STATE(pVCpu, enmExpectedState) do { } while (0)
392	# define VMCPU_ASSERT_STATE_2(pVCpu, enmExpectedState, a_enmExpectedState2) do { } while (0)
393	#endif
394	/** Tests if the state means that the CPU is started. */
395	#define VMCPUSTATE_IS_STARTED(enmState) ( (enmState) > VMCPUSTATE_STOPPED )
396	/** Tests if the state means that the CPU is stopped. */
397	#define VMCPUSTATE_IS_STOPPED(enmState) ( (enmState) == VMCPUSTATE_STOPPED )
398	/** @} */
399
400
401	/** The name of the raw-mode context VMM Core module. */
402	#define VMMRC_MAIN_MODULE_NAME "VMMRC.rc"
403	/** The name of the ring-0 context VMM Core module. */
404	#define VMMR0_MAIN_MODULE_NAME "VMMR0.r0"
405
406
407	/** VM Forced Action Flags.
408	*
409	* Use the VM_FF_SET() and VM_FF_CLEAR() macros to change the force
410	* action mask of a VM.
411	*
412	* Available VM bits:
413	* 0, 1, 5, 6, 7, 13, 14, 15, 16, 17, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30
414	*
415	*
416	* Available VMCPU bits:
417	* 14, 15, 36 to 63
418	*
419	* @todo If we run low on VMCPU, we may consider merging the SELM bits
420	*
421	* @{
422	*/
423	/** The virtual sync clock has been stopped, go to TM until it has been
424	* restarted... */
425	#define VM_FF_TM_VIRTUAL_SYNC RT_BIT_32(VM_FF_TM_VIRTUAL_SYNC_BIT)
426	#define VM_FF_TM_VIRTUAL_SYNC_BIT 2
427	/** PDM Queues are pending. */
428	#define VM_FF_PDM_QUEUES RT_BIT_32(VM_FF_PDM_QUEUES_BIT)
429	/** The bit number for VM_FF_PDM_QUEUES. */
430	#define VM_FF_PDM_QUEUES_BIT 3
431	/** PDM DMA transfers are pending. */
432	#define VM_FF_PDM_DMA RT_BIT_32(VM_FF_PDM_DMA_BIT)
433	/** The bit number for VM_FF_PDM_DMA. */
434	#define VM_FF_PDM_DMA_BIT 4
435	/** This action forces the VM to call DBGF so DBGF can service debugger
436	* requests in the emulation thread.
437	* This action flag stays asserted till DBGF clears it.*/
438	#define VM_FF_DBGF RT_BIT_32(VM_FF_DBGF_BIT)
439	/** The bit number for VM_FF_DBGF. */
440	#define VM_FF_DBGF_BIT 8
441	/** This action forces the VM to service pending requests from other
442	* thread or requests which must be executed in another context. */
443	#define VM_FF_REQUEST RT_BIT_32(VM_FF_REQUEST_BIT)
444	#define VM_FF_REQUEST_BIT 9
445	/** Check for VM state changes and take appropriate action. */
446	#define VM_FF_CHECK_VM_STATE RT_BIT_32(VM_FF_CHECK_VM_STATE_BIT)
447	/** The bit number for VM_FF_CHECK_VM_STATE. */
448	#define VM_FF_CHECK_VM_STATE_BIT 10
449	/** Reset the VM. (postponed) */
450	#define VM_FF_RESET RT_BIT_32(VM_FF_RESET_BIT)
451	/** The bit number for VM_FF_RESET. */
452	#define VM_FF_RESET_BIT 11
453	/** EMT rendezvous in VMM. */
454	#define VM_FF_EMT_RENDEZVOUS RT_BIT_32(VM_FF_EMT_RENDEZVOUS_BIT)
455	/** The bit number for VM_FF_EMT_RENDEZVOUS. */
456	#define VM_FF_EMT_RENDEZVOUS_BIT 12
457
458	/** PGM needs to allocate handy pages. */
459	#define VM_FF_PGM_NEED_HANDY_PAGES RT_BIT_32(VM_FF_PGM_NEED_HANDY_PAGES_BIT)
460	#define VM_FF_PGM_NEED_HANDY_PAGES_BIT 18
461	/** PGM is out of memory.
462	* Abandon all loops and code paths which can be resumed and get up to the EM
463	* loops. */
464	#define VM_FF_PGM_NO_MEMORY RT_BIT_32(VM_FF_PGM_NO_MEMORY_BIT)
465	#define VM_FF_PGM_NO_MEMORY_BIT 19
466	/** PGM is about to perform a lightweight pool flush
467	* Guest SMP: all EMT threads should return to ring 3
468	*/
469	#define VM_FF_PGM_POOL_FLUSH_PENDING RT_BIT_32(VM_FF_PGM_POOL_FLUSH_PENDING_BIT)
470	#define VM_FF_PGM_POOL_FLUSH_PENDING_BIT 20
471	/** Suspend the VM - debug only. */
472	#define VM_FF_DEBUG_SUSPEND RT_BIT_32(VM_FF_DEBUG_SUSPEND_BIT)
473	#define VM_FF_DEBUG_SUSPEND_BIT 31
474
475
476	#if defined(VBOX_VMM_TARGET_ARMV8)
477	/** This action forces the VM to inject an IRQ into the guest. */
478	# define VMCPU_FF_INTERRUPT_IRQ RT_BIT_64(VMCPU_FF_INTERRUPT_IRQ_BIT)
479	# define VMCPU_FF_INTERRUPT_IRQ_BIT 0
480	/** This action forces the VM to inject an FIQ into the guest. */
481	# define VMCPU_FF_INTERRUPT_FIQ RT_BIT_64(VMCPU_FF_INTERRUPT_FIQ_BIT)
482	# define VMCPU_FF_INTERRUPT_FIQ_BIT 1
483	#else
484	/** This action forces the VM to check any pending interrupts on the APIC. */
485	# define VMCPU_FF_INTERRUPT_APIC RT_BIT_64(VMCPU_FF_INTERRUPT_APIC_BIT)
486	# define VMCPU_FF_INTERRUPT_APIC_BIT 0
487	/** This action forces the VM to check any pending interrups on the PIC. */
488	# define VMCPU_FF_INTERRUPT_PIC RT_BIT_64(VMCPU_FF_INTERRUPT_PIC_BIT)
489	# define VMCPU_FF_INTERRUPT_PIC_BIT 1
490	#endif
491	/** This action forces the VM to schedule and run pending timer (TM).
492	* @remarks Don't move - PATM compatibility. */
493	#define VMCPU_FF_TIMER RT_BIT_64(VMCPU_FF_TIMER_BIT)
494	#define VMCPU_FF_TIMER_BIT 2
495	/** This action forces the VM to check any pending NMIs. */
496	#define VMCPU_FF_INTERRUPT_NMI RT_BIT_64(VMCPU_FF_INTERRUPT_NMI_BIT)
497	#define VMCPU_FF_INTERRUPT_NMI_BIT 3
498	/** This action forces the VM to check any pending SMIs. */
499	#define VMCPU_FF_INTERRUPT_SMI RT_BIT_64(VMCPU_FF_INTERRUPT_SMI_BIT)
500	#define VMCPU_FF_INTERRUPT_SMI_BIT 4
501	/** PDM critical section unlocking is pending, process promptly upon return to R3. */
502	#define VMCPU_FF_PDM_CRITSECT RT_BIT_64(VMCPU_FF_PDM_CRITSECT_BIT)
503	#define VMCPU_FF_PDM_CRITSECT_BIT 5
504	/** Special EM internal force flag that is used by EMUnhaltAndWakeUp() to force
505	* the virtual CPU out of the next (/current) halted state. It is not processed
506	* nor cleared by emR3ForcedActions (similar to VMCPU_FF_BLOCK_NMIS), instead it
507	* is cleared the next time EM leaves the HALTED state. */
508	#define VMCPU_FF_UNHALT RT_BIT_64(VMCPU_FF_UNHALT_BIT)
509	#define VMCPU_FF_UNHALT_BIT 6
510	/** Pending IEM action (mask). */
511	#define VMCPU_FF_IEM RT_BIT_64(VMCPU_FF_IEM_BIT)
512	/** Pending IEM action (bit number). */
513	#define VMCPU_FF_IEM_BIT 7
514	/** Pending APIC action (bit number). */
515	#define VMCPU_FF_UPDATE_APIC_BIT 8
516	/** This action forces the VM to update APIC's asynchronously arrived
517	* interrupts as pending interrupts. */
518	#define VMCPU_FF_UPDATE_APIC RT_BIT_64(VMCPU_FF_UPDATE_APIC_BIT)
519	/** This action forces the VM to service pending requests from other
520	* thread or requests which must be executed in another context. */
521	#define VMCPU_FF_REQUEST RT_BIT_64(VMCPU_FF_REQUEST_BIT)
522	#define VMCPU_FF_REQUEST_BIT 9
523	/** Pending DBGF event (alternative to passing VINF_EM_DBG_EVENT around). */
524	#define VMCPU_FF_DBGF RT_BIT_64(VMCPU_FF_DBGF_BIT)
525	/** The bit number for VMCPU_FF_DBGF. */
526	#define VMCPU_FF_DBGF_BIT 10
527	/** Hardware virtualized nested-guest interrupt pending. */
528	#define VMCPU_FF_INTERRUPT_NESTED_GUEST RT_BIT_64(VMCPU_FF_INTERRUPT_NESTED_GUEST_BIT)
529	#define VMCPU_FF_INTERRUPT_NESTED_GUEST_BIT 11
530	/** This action forces PGM to update changes to CR3 when the guest was in HM mode
531	* (when using nested paging). */
532	#define VMCPU_FF_HM_UPDATE_CR3 RT_BIT_64(VMCPU_FF_HM_UPDATE_CR3_BIT)
533	#define VMCPU_FF_HM_UPDATE_CR3_BIT 12
534	#if defined(VBOX_VMM_TARGET_ARMV8)
535	# define VMCPU_FF_VTIMER_ACTIVATED RT_BIT_64(VMCPU_FF_VTIMER_ACTIVATED_BIT)
536	# define VMCPU_FF_VTIMER_ACTIVATED_BIT 13
537	#else
538	/* Bit 13 used to be VMCPU_FF_HM_UPDATE_PAE_PDPES. */
539	#endif
540	/** This action forces the VM to resync the page tables before going
541	* back to execute guest code. (GLOBAL FLUSH) */
542	#define VMCPU_FF_PGM_SYNC_CR3 RT_BIT_64(VMCPU_FF_PGM_SYNC_CR3_BIT)
543	#define VMCPU_FF_PGM_SYNC_CR3_BIT 16
544	/** Same as VM_FF_PGM_SYNC_CR3 except that global pages can be skipped.
545	* (NON-GLOBAL FLUSH) */
546	#define VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL RT_BIT_64(VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL_BIT)
547	#define VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL_BIT 17
548	/** Check for pending TLB shootdown actions (deprecated)
549	* Reserved for future HM re-use if necessary / safe.
550	* Consumer: HM */
551	#define VMCPU_FF_TLB_SHOOTDOWN_UNUSED RT_BIT_64(VMCPU_FF_TLB_SHOOTDOWN_UNUSED_BIT)
552	#define VMCPU_FF_TLB_SHOOTDOWN_UNUSED_BIT 18
553	/** Check for pending TLB flush action.
554	* Consumer: HM
555	* @todo rename to VMCPU_FF_HM_TLB_FLUSH */
556	#define VMCPU_FF_TLB_FLUSH RT_BIT_64(VMCPU_FF_TLB_FLUSH_BIT)
557	/** The bit number for VMCPU_FF_TLB_FLUSH. */
558	#define VMCPU_FF_TLB_FLUSH_BIT 19
559	/* 20 used to be VMCPU_FF_TRPM_SYNC_IDT (raw-mode only). */
560	/* 21 used to be VMCPU_FF_SELM_SYNC_TSS (raw-mode only). */
561	/* 22 used to be VMCPU_FF_SELM_SYNC_GDT (raw-mode only). */
562	/* 23 used to be VMCPU_FF_SELM_SYNC_LDT (raw-mode only). */
563	/* 24 used to be VMCPU_FF_INHIBIT_INTERRUPTS, which moved to CPUMCTX::eflags.uBoth in v7.0.4. */
564	/* 25 used to be VMCPU_FF_BLOCK_NMIS, which moved to CPUMCTX::eflags.uBoth in v7.0.4. */
565	/** Force return to Ring-3. */
566	#define VMCPU_FF_TO_R3 RT_BIT_64(VMCPU_FF_TO_R3_BIT)
567	#define VMCPU_FF_TO_R3_BIT 28
568	/** Force return to ring-3 to service pending I/O or MMIO write.
569	* This is a backup for mechanism VINF_IOM_R3_IOPORT_COMMIT_WRITE and
570	* VINF_IOM_R3_MMIO_COMMIT_WRITE, allowing VINF_EM_DBG_BREAKPOINT and similar
571	* status codes to be propagated at the same time without loss. */
572	#define VMCPU_FF_IOM RT_BIT_64(VMCPU_FF_IOM_BIT)
573	#define VMCPU_FF_IOM_BIT 29
574	/* 30 used to be VMCPU_FF_CPUM */
575	/** VMX-preemption timer expired. */
576	#define VMCPU_FF_VMX_PREEMPT_TIMER RT_BIT_64(VMCPU_FF_VMX_PREEMPT_TIMER_BIT)
577	#define VMCPU_FF_VMX_PREEMPT_TIMER_BIT 31
578	/** Pending MTF (Monitor Trap Flag) event. */
579	#define VMCPU_FF_VMX_MTF RT_BIT_64(VMCPU_FF_VMX_MTF_BIT)
580	#define VMCPU_FF_VMX_MTF_BIT 32
581	/** VMX APIC-write emulation pending.
582	* @todo possible candidate for internal EFLAGS, or maybe just a summary bit
583	* (see also VMCPU_FF_VMX_INT_WINDOW). */
584	#define VMCPU_FF_VMX_APIC_WRITE RT_BIT_64(VMCPU_FF_VMX_APIC_WRITE_BIT)
585	#define VMCPU_FF_VMX_APIC_WRITE_BIT 33
586	/** VMX interrupt-window event pending.
587	*
588	* "Pending" is misleading here, it would be better to say that the event need
589	* to be generated at the next opportunity and that this flag causes it to be
590	* polled for on every instruction boundrary and such.
591	*
592	* @todo Change the IEM side of this to not poll but to track down the places
593	* where it can be generated and set an internal EFLAGS bit that causes it
594	* to be checked out when finishing the current instruction. */
595	#define VMCPU_FF_VMX_INT_WINDOW RT_BIT_64(VMCPU_FF_VMX_INT_WINDOW_BIT)
596	#define VMCPU_FF_VMX_INT_WINDOW_BIT 34
597	/** VMX NMI-window event pending.
598	* Same "pending" comment and todo in VMCPU_FF_VMX_INT_WINDOW. */
599	#define VMCPU_FF_VMX_NMI_WINDOW RT_BIT_64(VMCPU_FF_VMX_NMI_WINDOW_BIT)
600	#define VMCPU_FF_VMX_NMI_WINDOW_BIT 35
601
602
603	/** Externally VM forced actions. Used to quit the idle/wait loop. */
604	#define VM_FF_EXTERNAL_SUSPENDED_MASK ( VM_FF_CHECK_VM_STATE \| VM_FF_DBGF \| VM_FF_REQUEST \| VM_FF_EMT_RENDEZVOUS )
605	/** Externally VMCPU forced actions. Used to quit the idle/wait loop. */
606	#define VMCPU_FF_EXTERNAL_SUSPENDED_MASK ( VMCPU_FF_REQUEST \| VMCPU_FF_DBGF )
607
608	/** Externally forced VM actions. Used to quit the idle/wait loop. */
609	#define VM_FF_EXTERNAL_HALTED_MASK ( VM_FF_CHECK_VM_STATE \| VM_FF_DBGF \| VM_FF_REQUEST \
610	\| VM_FF_PDM_QUEUES \| VM_FF_PDM_DMA \| VM_FF_EMT_RENDEZVOUS )
611	/** Externally forced VMCPU actions. Used to quit the idle/wait loop. */
612	#if defined(VBOX_VMM_TARGET_ARMV8)
613	# define VMCPU_FF_EXTERNAL_HALTED_MASK ( VMCPU_FF_INTERRUPT_IRQ \| VMCPU_FF_INTERRUPT_FIQ \
614	\| VMCPU_FF_REQUEST \| VMCPU_FF_INTERRUPT_NMI \| VMCPU_FF_INTERRUPT_SMI \
615	\| VMCPU_FF_UNHALT \| VMCPU_FF_TIMER \| VMCPU_FF_DBGF \
616	\| VMCPU_FF_VTIMER_ACTIVATED)
617	#else
618	# define VMCPU_FF_EXTERNAL_HALTED_MASK ( VMCPU_FF_UPDATE_APIC \| VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC \
619	\| VMCPU_FF_REQUEST \| VMCPU_FF_INTERRUPT_NMI \| VMCPU_FF_INTERRUPT_SMI \
620	\| VMCPU_FF_UNHALT \| VMCPU_FF_TIMER \| VMCPU_FF_DBGF \
621	\| VMCPU_FF_INTERRUPT_NESTED_GUEST)
622	#endif
623
624	/** High priority VM pre-execution actions. */
625	#define VM_FF_HIGH_PRIORITY_PRE_MASK ( VM_FF_CHECK_VM_STATE \| VM_FF_DBGF \| VM_FF_TM_VIRTUAL_SYNC \
626	\| VM_FF_DEBUG_SUSPEND \| VM_FF_PGM_NEED_HANDY_PAGES \| VM_FF_PGM_NO_MEMORY \
627	\| VM_FF_EMT_RENDEZVOUS )
628	/** High priority VMCPU pre-execution actions. */
629	#if defined(VBOX_VMM_TARGET_ARMV8)
630	# define VMCPU_FF_HIGH_PRIORITY_PRE_MASK ( VMCPU_FF_TIMER \| VMCPU_FF_INTERRUPT_IRQ \| VMCPU_FF_INTERRUPT_FIQ \
631	\| VMCPU_FF_DBGF )
632	#else
633	# define VMCPU_FF_HIGH_PRIORITY_PRE_MASK ( VMCPU_FF_TIMER \| VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC \
634	\| VMCPU_FF_UPDATE_APIC \| VMCPU_FF_DBGF \
635	\| VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL \
636	\| VMCPU_FF_INTERRUPT_NESTED_GUEST \| VMCPU_FF_VMX_MTF \| VMCPU_FF_VMX_APIC_WRITE \
637	\| VMCPU_FF_VMX_PREEMPT_TIMER \| VMCPU_FF_VMX_NMI_WINDOW \| VMCPU_FF_VMX_INT_WINDOW )
638	#endif
639
640	/** High priority VM pre raw-mode execution mask. */
641	#define VM_FF_HIGH_PRIORITY_PRE_RAW_MASK ( VM_FF_PGM_NEED_HANDY_PAGES \| VM_FF_PGM_NO_MEMORY )
642	/** High priority VMCPU pre raw-mode execution mask. */
643	#define VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK ( VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL )
644
645	/** High priority post-execution actions. */
646	#define VM_FF_HIGH_PRIORITY_POST_MASK ( VM_FF_PGM_NO_MEMORY )
647	/** High priority post-execution actions. */
648	#define VMCPU_FF_HIGH_PRIORITY_POST_MASK ( VMCPU_FF_PDM_CRITSECT \| VMCPU_FF_HM_UPDATE_CR3 \| VMCPU_FF_IEM \| VMCPU_FF_IOM )
649
650	/** Normal priority VM post-execution actions. */
651	#define VM_FF_NORMAL_PRIORITY_POST_MASK ( VM_FF_CHECK_VM_STATE \| VM_FF_DBGF \| VM_FF_RESET \
652	\| VM_FF_PGM_NO_MEMORY \| VM_FF_EMT_RENDEZVOUS)
653	/** Normal priority VMCPU post-execution actions. */
654	#define VMCPU_FF_NORMAL_PRIORITY_POST_MASK ( VMCPU_FF_DBGF )
655
656	/** Normal priority VM actions. */
657	#define VM_FF_NORMAL_PRIORITY_MASK ( VM_FF_REQUEST \| VM_FF_PDM_QUEUES \| VM_FF_PDM_DMA \| VM_FF_EMT_RENDEZVOUS)
658	/** Normal priority VMCPU actions. */
659	#define VMCPU_FF_NORMAL_PRIORITY_MASK ( VMCPU_FF_REQUEST )
660
661	/** Flags to clear before resuming guest execution. */
662	#define VMCPU_FF_RESUME_GUEST_MASK ( VMCPU_FF_TO_R3 )
663
664
665	/** VM flags that cause the REP[\|NE\|E] STRINS loops to yield immediately. */
666	#define VM_FF_HIGH_PRIORITY_POST_REPSTR_MASK ( VM_FF_TM_VIRTUAL_SYNC \| VM_FF_PGM_NEED_HANDY_PAGES \| VM_FF_PGM_NO_MEMORY \
667	\| VM_FF_EMT_RENDEZVOUS \| VM_FF_PGM_POOL_FLUSH_PENDING \| VM_FF_RESET)
668	/** VM flags that cause the REP[\|NE\|E] STRINS loops to yield. */
669	#define VM_FF_YIELD_REPSTR_MASK ( VM_FF_HIGH_PRIORITY_POST_REPSTR_MASK \
670	\| VM_FF_PDM_QUEUES \| VM_FF_PDM_DMA \| VM_FF_DBGF \| VM_FF_DEBUG_SUSPEND )
671	/** VMCPU flags that cause the REP[\|NE\|E] STRINS loops to yield immediately. */
672	#ifdef IN_RING3
673	# define VMCPU_FF_HIGH_PRIORITY_POST_REPSTR_MASK (VMCPU_FF_DBGF \| VMCPU_FF_VMX_MTF)
674	#else
675	# define VMCPU_FF_HIGH_PRIORITY_POST_REPSTR_MASK (VMCPU_FF_TO_R3 \| VMCPU_FF_IEM \| VMCPU_FF_IOM \| VMCPU_FF_DBGF \| VMCPU_FF_VMX_MTF)
676	#endif
677
678	#if !defined(VBOX_VMM_TARGET_ARMV8)
679	/** VMCPU flags that cause the REP[\|NE\|E] STRINS loops to yield, interrupts
680	* enabled. */
681	# define VMCPU_FF_YIELD_REPSTR_MASK ( VMCPU_FF_HIGH_PRIORITY_POST_REPSTR_MASK \
682	\| VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_UPDATE_APIC \| VMCPU_FF_INTERRUPT_PIC \
683	\| VMCPU_FF_INTERRUPT_NMI \| VMCPU_FF_INTERRUPT_SMI \| VMCPU_FF_PDM_CRITSECT \
684	\| VMCPU_FF_TIMER \| VMCPU_FF_REQUEST \
685	\| VMCPU_FF_INTERRUPT_NESTED_GUEST )
686	/** VMCPU flags that cause the REP[\|NE\|E] STRINS loops to yield, interrupts
687	* disabled. */
688	# define VMCPU_FF_YIELD_REPSTR_NOINT_MASK ( VMCPU_FF_YIELD_REPSTR_MASK \
689	& ~( VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_UPDATE_APIC \| VMCPU_FF_INTERRUPT_PIC \
690	\| VMCPU_FF_INTERRUPT_NESTED_GUEST) )
691	#endif
692
693	/** VM Flags that cause the HM loops to go back to ring-3. */
694	#define VM_FF_HM_TO_R3_MASK ( VM_FF_TM_VIRTUAL_SYNC \| VM_FF_PGM_NEED_HANDY_PAGES \| VM_FF_PGM_NO_MEMORY \
695	\| VM_FF_PDM_QUEUES \| VM_FF_EMT_RENDEZVOUS)
696	/** VMCPU Flags that cause the HM loops to go back to ring-3. */
697	#define VMCPU_FF_HM_TO_R3_MASK ( VMCPU_FF_TO_R3 \| VMCPU_FF_TIMER \| VMCPU_FF_PDM_CRITSECT \
698	\| VMCPU_FF_IEM \| VMCPU_FF_IOM)
699
700	/** High priority ring-0 VM pre HM-mode execution mask. */
701	#define VM_FF_HP_R0_PRE_HM_MASK (VM_FF_HM_TO_R3_MASK \| VM_FF_REQUEST \| VM_FF_PGM_POOL_FLUSH_PENDING \| VM_FF_PDM_DMA)
702	/** High priority ring-0 VMCPU pre HM-mode execution mask. */
703	#define VMCPU_FF_HP_R0_PRE_HM_MASK ( VMCPU_FF_HM_TO_R3_MASK \| VMCPU_FF_PGM_SYNC_CR3 \
704	\| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL \| VMCPU_FF_REQUEST \
705	\| VMCPU_FF_VMX_APIC_WRITE \| VMCPU_FF_VMX_MTF \| VMCPU_FF_VMX_PREEMPT_TIMER)
706	/** High priority ring-0 VM pre HM-mode execution mask, single stepping. */
707	#define VM_FF_HP_R0_PRE_HM_STEP_MASK (VM_FF_HP_R0_PRE_HM_MASK & ~( VM_FF_TM_VIRTUAL_SYNC \| VM_FF_PDM_QUEUES \
708	\| VM_FF_EMT_RENDEZVOUS \| VM_FF_REQUEST \
709	\| VM_FF_PDM_DMA) )
710	/** High priority ring-0 VMCPU pre HM-mode execution mask, single stepping. */
711	#define VMCPU_FF_HP_R0_PRE_HM_STEP_MASK (VMCPU_FF_HP_R0_PRE_HM_MASK & ~( VMCPU_FF_TO_R3 \| VMCPU_FF_TIMER \
712	\| VMCPU_FF_PDM_CRITSECT \| VMCPU_FF_REQUEST) )
713
714	/** All the VMX nested-guest flags. */
715	#define VMCPU_FF_VMX_ALL_MASK ( VMCPU_FF_VMX_PREEMPT_TIMER \| VMCPU_FF_VMX_MTF \| VMCPU_FF_VMX_APIC_WRITE \
716	\| VMCPU_FF_VMX_INT_WINDOW \| VMCPU_FF_VMX_NMI_WINDOW )
717
718	/** All the forced VM flags. */
719	#define VM_FF_ALL_MASK (UINT32_MAX)
720	/** All the forced VMCPU flags. */
721	#define VMCPU_FF_ALL_MASK ( UINT32_MAX \
722	\| VMCPU_FF_VMX_MTF \| VMCPU_FF_VMX_APIC_WRITE \| VMCPU_FF_VMX_INT_WINDOW \
723	\| VMCPU_FF_VMX_NMI_WINDOW )
724
725	/** All the forced VM flags except those related to raw-mode and hardware
726	* assisted execution. */
727	#define VM_FF_ALL_REM_MASK (~(VM_FF_HIGH_PRIORITY_PRE_RAW_MASK) \| VM_FF_PGM_NEED_HANDY_PAGES \| VM_FF_PGM_NO_MEMORY)
728	/** All the forced VMCPU flags except those related to raw-mode and hardware
729	* assisted execution. */
730	#define VMCPU_FF_ALL_REM_MASK (~(VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK \| VMCPU_FF_PDM_CRITSECT \| VMCPU_FF_TLB_FLUSH))
731
732	#ifndef VBOX_FOR_DTRACE_LIB
733	AssertCompile( ((VM_FF_HIGH_PRIORITY_POST_REPSTR_MASK \| VM_FF_YIELD_REPSTR_MASK)
734	& (VM_FF_HIGH_PRIORITY_PRE_RAW_MASK & ~VM_FF_ALL_REM_MASK)) == 0);
735	AssertCompile((VMCPU_FF_HIGH_PRIORITY_POST_REPSTR_MASK & (VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK & ~VMCPU_FF_ALL_REM_MASK)) == 0);
736	#endif
737
738	/** @} */
739
740	/** @def VM_FF_SET
741	* Sets a single force action flag.
742	*
743	* @param pVM The cross context VM structure.
744	* @param fFlag The flag to set.
745	*/
746	#define VM_FF_SET(pVM, fFlag) do { \
747	AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
748	AssertCompile((fFlag) == RT_BIT_32(fFlag##_BIT)); \
749	ASMAtomicOrU32(&(pVM)->fGlobalForcedActions, (fFlag)); \
750	} while (0)
751
752	/** @def VMCPU_FF_SET
753	* Sets a single force action flag for the given VCPU.
754	*
755	* @param pVCpu The cross context virtual CPU structure.
756	* @param fFlag The flag to set.
757	* @sa VMCPU_FF_SET_MASK
758	*/
759	#ifdef VMCPU_WITH_64_BIT_FFS
760	# define VMCPU_FF_SET(pVCpu, fFlag) do { \
761	AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
762	AssertCompile((fFlag) == RT_BIT_64(fFlag##_BIT)); \
763	ASMAtomicBitSet(&(pVCpu)->fLocalForcedActions, fFlag##_BIT); \
764	} while (0)
765	#else
766	# define VMCPU_FF_SET(pVCpu, fFlag) do { \
767	AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
768	AssertCompile((fFlag) == RT_BIT_32(fFlag##_BIT)); \
769	ASMAtomicOrU32(&(pVCpu)->fLocalForcedActions, (fFlag)); \
770	} while (0)
771	#endif
772
773	/** @def VMCPU_FF_SET_MASK
774	* Sets a two or more force action flag for the given VCPU.
775	*
776	* @param pVCpu The cross context virtual CPU structure.
777	* @param fFlags The flags to set.
778	* @sa VMCPU_FF_SET
779	*/
780	#ifdef VMCPU_WITH_64_BIT_FFS
781	# if ARCH_BITS > 32
782	# define VMCPU_FF_SET_MASK(pVCpu, fFlags) \
783	do { ASMAtomicOrU64(&pVCpu->fLocalForcedActions, (fFlags)); } while (0)
784	# else
785	# define VMCPU_FF_SET_MASK(pVCpu, fFlags) do { \
786	if (!((fFlags) >> 32)) ASMAtomicOrU32((uint32_t volatile *)&pVCpu->fLocalForcedActions, (uint32_t)(fFlags)); \
787	else ASMAtomicOrU64(&pVCpu->fLocalForcedActions, (fFlags)); \
788	} while (0)
789	# endif
790	#else
791	# define VMCPU_FF_SET_MASK(pVCpu, fFlags) \
792	do { ASMAtomicOrU32(&pVCpu->fLocalForcedActions, (fFlags)); } while (0)
793	#endif
794
795	/** @def VM_FF_CLEAR
796	* Clears a single force action flag.
797	*
798	* @param pVM The cross context VM structure.
799	* @param fFlag The flag to clear.
800	*/
801	#define VM_FF_CLEAR(pVM, fFlag) do { \
802	AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
803	AssertCompile((fFlag) == RT_BIT_32(fFlag##_BIT)); \
804	ASMAtomicAndU32(&(pVM)->fGlobalForcedActions, ~(fFlag)); \
805	} while (0)
806
807	/** @def VMCPU_FF_CLEAR
808	* Clears a single force action flag for the given VCPU.
809	*
810	* @param pVCpu The cross context virtual CPU structure.
811	* @param fFlag The flag to clear.
812	*/
813	#ifdef VMCPU_WITH_64_BIT_FFS
814	# define VMCPU_FF_CLEAR(pVCpu, fFlag) do { \
815	AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
816	AssertCompile((fFlag) == RT_BIT_64(fFlag##_BIT)); \
817	ASMAtomicBitClear(&(pVCpu)->fLocalForcedActions, fFlag##_BIT); \
818	} while (0)
819	#else
820	# define VMCPU_FF_CLEAR(pVCpu, fFlag) do { \
821	AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
822	AssertCompile((fFlag) == RT_BIT_32(fFlag##_BIT)); \
823	ASMAtomicAndU32(&(pVCpu)->fLocalForcedActions, ~(fFlag)); \
824	} while (0)
825	#endif
826
827	/** @def VMCPU_FF_CLEAR_MASK
828	* Clears two or more force action flags for the given VCPU.
829	*
830	* @param pVCpu The cross context virtual CPU structure.
831	* @param fFlags The flags to clear.
832	*/
833	#ifdef VMCPU_WITH_64_BIT_FFS
834	# if ARCH_BITS > 32
835	# define VMCPU_FF_CLEAR_MASK(pVCpu, fFlags) \
836	do { ASMAtomicAndU64(&(pVCpu)->fLocalForcedActions, ~(fFlags)); } while (0)
837	# else
838	# define VMCPU_FF_CLEAR_MASK(pVCpu, fFlags) do { \
839	if (!((fFlags) >> 32)) ASMAtomicAndU32((uint32_t volatile *)&(pVCpu)->fLocalForcedActions, ~(uint32_t)(fFlags)); \
840	else ASMAtomicAndU64(&(pVCpu)->fLocalForcedActions, ~(fFlags)); \
841	} while (0)
842	# endif
843	#else
844	# define VMCPU_FF_CLEAR_MASK(pVCpu, fFlags) \
845	do { ASMAtomicAndU32(&(pVCpu)->fLocalForcedActions, ~(fFlags)); } while (0)
846	#endif
847
848	/** @def VM_FF_IS_SET
849	* Checks if single a force action flag is set.
850	*
851	* @param pVM The cross context VM structure.
852	* @param fFlag The flag to check.
853	* @sa VM_FF_IS_ANY_SET
854	*/
855	#if !defined(VBOX_STRICT) \|\| !defined(RT_COMPILER_SUPPORTS_LAMBDA)
856	# define VM_FF_IS_SET(pVM, fFlag) RT_BOOL((pVM)->fGlobalForcedActions & (fFlag))
857	#else
858	# define VM_FF_IS_SET(pVM, fFlag) \
859	([](PVM a_pVM) -> bool \
860	{ \
861	AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
862	AssertCompile((fFlag) == RT_BIT_32(fFlag##_BIT)); \
863	return RT_BOOL(a_pVM->fGlobalForcedActions & (fFlag)); \
864	}(pVM))
865	#endif
866
867	/** @def VMCPU_FF_IS_SET
868	* Checks if a single force action flag is set for the given VCPU.
869	*
870	* @param pVCpu The cross context virtual CPU structure.
871	* @param fFlag The flag to check.
872	* @sa VMCPU_FF_IS_ANY_SET
873	*/
874	#if !defined(VBOX_STRICT) \|\| !defined(RT_COMPILER_SUPPORTS_LAMBDA)
875	# define VMCPU_FF_IS_SET(pVCpu, fFlag) RT_BOOL((pVCpu)->fLocalForcedActions & (fFlag))
876	#else
877	# define VMCPU_FF_IS_SET(pVCpu, fFlag) \
878	([](PCVMCPU a_pVCpu) -> bool \
879	{ \
880	AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
881	AssertCompile((fFlag) == RT_BIT_64(fFlag##_BIT)); \
882	return RT_BOOL(a_pVCpu->fLocalForcedActions & (fFlag)); \
883	}(pVCpu))
884	#endif
885
886	/** @def VM_FF_IS_ANY_SET
887	* Checks if one or more force action in the specified set is pending.
888	*
889	* @param pVM The cross context VM structure.
890	* @param fFlags The flags to check for.
891	* @sa VM_FF_IS_SET
892	*/
893	#define VM_FF_IS_ANY_SET(pVM, fFlags) RT_BOOL((pVM)->fGlobalForcedActions & (fFlags))
894
895	/** @def VMCPU_FF_IS_ANY_SET
896	* Checks if two or more force action flags in the specified set is set for the given VCPU.
897	*
898	* @param pVCpu The cross context virtual CPU structure.
899	* @param fFlags The flags to check for.
900	* @sa VMCPU_FF_IS_SET
901	*/
902	#define VMCPU_FF_IS_ANY_SET(pVCpu, fFlags) RT_BOOL((pVCpu)->fLocalForcedActions & (fFlags))
903
904	/** @def VM_FF_TEST_AND_CLEAR
905	* Checks if one (!) force action in the specified set is pending and clears it atomically
906	*
907	* @returns true if the bit was set.
908	* @returns false if the bit was clear.
909	* @param pVM The cross context VM structure.
910	* @param fFlag Flag constant to check and clear (_BIT is appended).
911	*/
912	#define VM_FF_TEST_AND_CLEAR(pVM, fFlag) (ASMAtomicBitTestAndClear(&(pVM)->fGlobalForcedActions, fFlag##_BIT))
913
914	/** @def VMCPU_FF_TEST_AND_CLEAR
915	* Checks if one (!) force action in the specified set is pending and clears it atomically
916	*
917	* @returns true if the bit was set.
918	* @returns false if the bit was clear.
919	* @param pVCpu The cross context virtual CPU structure.
920	* @param fFlag Flag constant to check and clear (_BIT is appended).
921	*/
922	#define VMCPU_FF_TEST_AND_CLEAR(pVCpu, fFlag) (ASMAtomicBitTestAndClear(&(pVCpu)->fLocalForcedActions, fFlag##_BIT))
923
924	/** @def VM_FF_IS_PENDING_EXCEPT
925	* Checks if one or more force action in the specified set is pending while one
926	* or more other ones are not.
927	*
928	* @param pVM The cross context VM structure.
929	* @param fFlags The flags to check for.
930	* @param fExcpt The flags that should not be set.
931	*/
932	#define VM_FF_IS_PENDING_EXCEPT(pVM, fFlags, fExcpt) \
933	( ((pVM)->fGlobalForcedActions & (fFlags)) && !((pVM)->fGlobalForcedActions & (fExcpt)) )
934
935	/** @def VM_IS_EMT
936	* Checks if the current thread is the emulation thread (EMT).
937	*
938	* @remark The ring-0 variation will need attention if we expand the ring-0
939	* code to let threads other than EMT mess around with the VM.
940	*/
941	#ifdef IN_RC
942	# define VM_IS_EMT(pVM) true
943	#else
944	# define VM_IS_EMT(pVM) (VMMGetCpu(pVM) != NULL)
945	#endif
946
947	/** @def VMCPU_IS_EMT
948	* Checks if the current thread is the emulation thread (EMT) for the specified
949	* virtual CPU.
950	*/
951	#ifdef IN_RC
952	# define VMCPU_IS_EMT(pVCpu) true
953	#else
954	# define VMCPU_IS_EMT(pVCpu) ((pVCpu) && ((pVCpu) == VMMGetCpu((pVCpu)->CTX_SUFF(pVM))))
955	#endif
956
957	/** @def VM_ASSERT_EMT
958	* Asserts that the current thread IS the emulation thread (EMT).
959	*/
960	#ifdef IN_RC
961	# define VM_ASSERT_EMT(pVM) Assert(VM_IS_EMT(pVM))
962	#elif defined(IN_RING0)
963	# define VM_ASSERT_EMT(pVM) Assert(VM_IS_EMT(pVM))
964	#else
965	# define VM_ASSERT_EMT(pVM) \
966	AssertMsg(VM_IS_EMT(pVM), \
967	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd\n", RTThreadNativeSelf(), VMR3GetVMCPUNativeThread(pVM)))
968	#endif
969
970	/** @def VMCPU_ASSERT_EMT
971	* Asserts that the current thread IS the emulation thread (EMT) of the
972	* specified virtual CPU.
973	*/
974	#ifdef IN_RC
975	# define VMCPU_ASSERT_EMT(pVCpu) Assert(VMCPU_IS_EMT(pVCpu))
976	#elif defined(IN_RING0)
977	# define VMCPU_ASSERT_EMT(pVCpu) AssertMsg(VMCPU_IS_EMT(pVCpu), \
978	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd idCpu=%u\n", \
979	RTThreadNativeSelf(), (pVCpu) ? (pVCpu)->hNativeThreadR0 : 0, \
980	(pVCpu) ? (pVCpu)->idCpu : 0))
981	#else
982	# define VMCPU_ASSERT_EMT(pVCpu) AssertMsg(VMCPU_IS_EMT(pVCpu), \
983	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd idCpu=%#x\n", \
984	RTThreadNativeSelf(), (pVCpu)->hNativeThread, (pVCpu)->idCpu))
985	#endif
986
987	/** @def VM_ASSERT_EMT_RETURN
988	* Asserts that the current thread IS the emulation thread (EMT) and returns if it isn't.
989	*/
990	#ifdef IN_RC
991	# define VM_ASSERT_EMT_RETURN(pVM, rc) AssertReturn(VM_IS_EMT(pVM), (rc))
992	#elif defined(IN_RING0)
993	# define VM_ASSERT_EMT_RETURN(pVM, rc) AssertReturn(VM_IS_EMT(pVM), (rc))
994	#else
995	# define VM_ASSERT_EMT_RETURN(pVM, rc) \
996	AssertMsgReturn(VM_IS_EMT(pVM), \
997	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd\n", RTThreadNativeSelf(), VMR3GetVMCPUNativeThread(pVM)), \
998	(rc))
999	#endif
1000
1001	/** @def VMCPU_ASSERT_EMT_RETURN
1002	* Asserts that the current thread IS the emulation thread (EMT) and returns if it isn't.
1003	*/
1004	#ifdef IN_RC
1005	# define VMCPU_ASSERT_EMT_RETURN(pVCpu, rc) AssertReturn(VMCPU_IS_EMT(pVCpu), (rc))
1006	#elif defined(IN_RING0)
1007	# define VMCPU_ASSERT_EMT_RETURN(pVCpu, rc) AssertReturn(VMCPU_IS_EMT(pVCpu), (rc))
1008	#else
1009	# define VMCPU_ASSERT_EMT_RETURN(pVCpu, rc) \
1010	AssertMsgReturn(VMCPU_IS_EMT(pVCpu), \
1011	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd idCpu=%#x\n", \
1012	RTThreadNativeSelf(), (pVCpu)->hNativeThread, (pVCpu)->idCpu), \
1013	(rc))
1014	#endif
1015
1016	/** @def VMCPU_ASSERT_EMT_OR_GURU
1017	* Asserts that the current thread IS the emulation thread (EMT) of the
1018	* specified virtual CPU.
1019	*/
1020	#if defined(IN_RC) \|\| defined(IN_RING0)
1021	# define VMCPU_ASSERT_EMT_OR_GURU(pVCpu) Assert( VMCPU_IS_EMT(pVCpu) \
1022	\|\| pVCpu->CTX_SUFF(pVM)->enmVMState == VMSTATE_GURU_MEDITATION \
1023	\|\| pVCpu->CTX_SUFF(pVM)->enmVMState == VMSTATE_GURU_MEDITATION_LS )
1024	#else
1025	# define VMCPU_ASSERT_EMT_OR_GURU(pVCpu) \
1026	AssertMsg( VMCPU_IS_EMT(pVCpu) \
1027	\|\| pVCpu->CTX_SUFF(pVM)->enmVMState == VMSTATE_GURU_MEDITATION \
1028	\|\| pVCpu->CTX_SUFF(pVM)->enmVMState == VMSTATE_GURU_MEDITATION_LS, \
1029	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd idCpu=%#x\n", \
1030	RTThreadNativeSelf(), (pVCpu)->hNativeThread, (pVCpu)->idCpu))
1031	#endif
1032
1033	/** @def VMCPU_ASSERT_EMT_OR_NOT_RUNNING
1034	* Asserts that the current thread IS the emulation thread (EMT) of the
1035	* specified virtual CPU or the VM is not running.
1036	*/
1037	#if defined(IN_RC) \|\| defined(IN_RING0)
1038	# define VMCPU_ASSERT_EMT_OR_NOT_RUNNING(pVCpu) \
1039	Assert( VMCPU_IS_EMT(pVCpu) \
1040	\|\| !VM_IS_RUNNING_FOR_ASSERTIONS_ONLY((pVCpu)->CTX_SUFF(pVM)) )
1041	#else
1042	# define VMCPU_ASSERT_EMT_OR_NOT_RUNNING(pVCpu) \
1043	AssertMsg( VMCPU_IS_EMT(pVCpu) \
1044	\|\| !VM_IS_RUNNING_FOR_ASSERTIONS_ONLY((pVCpu)->CTX_SUFF(pVM)), \
1045	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd idCpu=%#x\n", \
1046	RTThreadNativeSelf(), (pVCpu)->hNativeThread, (pVCpu)->idCpu))
1047	#endif
1048
1049	/** @def VMSTATE_IS_RUNNING
1050	* Checks if the given state indicates a running VM.
1051	*/
1052	#define VMSTATE_IS_RUNNING(a_enmVMState) \
1053	( (a_enmVMState) == VMSTATE_RUNNING \
1054	\|\| (a_enmVMState) == VMSTATE_RUNNING_LS )
1055
1056	/** @def VM_IS_RUNNING_FOR_ASSERTIONS_ONLY
1057	* Checks if the VM is running.
1058	* @note This is only for pure debug assertions. No AssertReturn or similar!
1059	* @sa VMSTATE_IS_RUNNING
1060	*/
1061	#define VM_IS_RUNNING_FOR_ASSERTIONS_ONLY(pVM) \
1062	( (pVM)->enmVMState == VMSTATE_RUNNING \
1063	\|\| (pVM)->enmVMState == VMSTATE_RUNNING_LS )
1064
1065
1066	/** @def VMSTATE_IS_POWERED_ON
1067	* Checks if the given state indicates the VM is powered on.
1068	*
1069	* @note Excludes all error states, so a powered on VM that hit a fatal error,
1070	* guru meditation, state load failure or similar will not be considered
1071	* powered on by this test.
1072	*/
1073	#define VMSTATE_IS_POWERED_ON(a_enmVMState) \
1074	( (a_enmVMState) >= VMSTATE_RESUMING && (a_enmVMState) < VMSTATE_POWERING_OFF )
1075
1076	/** @def VM_ASSERT_IS_NOT_RUNNING
1077	* Asserts that the VM is not running.
1078	*/
1079	#if defined(IN_RC) \|\| defined(IN_RING0)
1080	#define VM_ASSERT_IS_NOT_RUNNING(pVM) Assert(!VM_IS_RUNNING_FOR_ASSERTIONS_ONLY(pVM))
1081	#else
1082	#define VM_ASSERT_IS_NOT_RUNNING(pVM) AssertMsg(!VM_IS_RUNNING_FOR_ASSERTIONS_ONLY(pVM), \
1083	("VM is running. enmVMState=%d\n", (pVM)->enmVMState))
1084	#endif
1085
1086	/** @def VM_ASSERT_EMT0
1087	* Asserts that the current thread IS emulation thread \#0 (EMT0).
1088	*/
1089	#ifdef IN_RING3
1090	# define VM_ASSERT_EMT0(a_pVM) VMCPU_ASSERT_EMT((a_pVM)->apCpusR3[0])
1091	#else
1092	# define VM_ASSERT_EMT0(a_pVM) VMCPU_ASSERT_EMT(&(a_pVM)->aCpus[0])
1093	#endif
1094
1095	/** @def VM_ASSERT_EMT0_RETURN
1096	* Asserts that the current thread IS emulation thread \#0 (EMT0) and returns if
1097	* it isn't.
1098	*/
1099	#ifdef IN_RING3
1100	# define VM_ASSERT_EMT0_RETURN(pVM, rc) VMCPU_ASSERT_EMT_RETURN((pVM)->apCpusR3[0], (rc))
1101	#else
1102	# define VM_ASSERT_EMT0_RETURN(pVM, rc) VMCPU_ASSERT_EMT_RETURN(&(pVM)->aCpus[0], (rc))
1103	#endif
1104
1105
1106	/**
1107	* Asserts that the current thread is NOT the emulation thread.
1108	*/
1109	#define VM_ASSERT_OTHER_THREAD(pVM) \
1110	AssertMsg(!VM_IS_EMT(pVM), ("Not other thread!!\n"))
1111
1112
1113	/** @def VM_ASSERT_STATE
1114	* Asserts a certain VM state.
1115	*/
1116	#define VM_ASSERT_STATE(pVM, _enmState) \
1117	AssertMsg((pVM)->enmVMState == (_enmState), \
1118	("state %s, expected %s\n", VMGetStateName((pVM)->enmVMState), VMGetStateName(_enmState)))
1119
1120	/** @def VM_ASSERT_STATE_RETURN
1121	* Asserts a certain VM state and returns if it doesn't match.
1122	*/
1123	#define VM_ASSERT_STATE_RETURN(pVM, _enmState, rc) \
1124	AssertMsgReturn((pVM)->enmVMState == (_enmState), \
1125	("state %s, expected %s\n", VMGetStateName((pVM)->enmVMState), VMGetStateName(_enmState)), \
1126	(rc))
1127
1128	/** @def VM_IS_VALID_EXT
1129	* Asserts a the VM handle is valid for external access, i.e. not being destroy
1130	* or terminated. */
1131	#define VM_IS_VALID_EXT(pVM) \
1132	( RT_VALID_ALIGNED_PTR(pVM, PAGE_SIZE) \
1133	&& ( (unsigned)(pVM)->enmVMState < (unsigned)VMSTATE_DESTROYING \
1134	\|\| ( (unsigned)(pVM)->enmVMState == (unsigned)VMSTATE_DESTROYING \
1135	&& VM_IS_EMT(pVM))) )
1136
1137	/** @def VM_ASSERT_VALID_EXT_RETURN
1138	* Asserts a the VM handle is valid for external access, i.e. not being
1139	* destroy or terminated.
1140	*/
1141	#define VM_ASSERT_VALID_EXT_RETURN(pVM, rc) \
1142	AssertMsgReturn(VM_IS_VALID_EXT(pVM), \
1143	("pVM=%p state %s\n", (pVM), RT_VALID_ALIGNED_PTR(pVM, PAGE_SIZE) \
1144	? VMGetStateName(pVM->enmVMState) : ""), \
1145	(rc))
1146
1147	/** @def VMCPU_ASSERT_VALID_EXT_RETURN
1148	* Asserts a the VMCPU handle is valid for external access, i.e. not being
1149	* destroy or terminated.
1150	*/
1151	#define VMCPU_ASSERT_VALID_EXT_RETURN(pVCpu, rc) \
1152	AssertMsgReturn( RT_VALID_ALIGNED_PTR(pVCpu, 64) \
1153	&& RT_VALID_ALIGNED_PTR((pVCpu)->CTX_SUFF(pVM), PAGE_SIZE) \
1154	&& (unsigned)(pVCpu)->CTX_SUFF(pVM)->enmVMState < (unsigned)VMSTATE_DESTROYING, \
1155	("pVCpu=%p pVM=%p state %s\n", (pVCpu), RT_VALID_ALIGNED_PTR(pVCpu, 64) ? (pVCpu)->CTX_SUFF(pVM) : NULL, \
1156	RT_VALID_ALIGNED_PTR(pVCpu, 64) && RT_VALID_ALIGNED_PTR((pVCpu)->CTX_SUFF(pVM), PAGE_SIZE) \
1157	? VMGetStateName((pVCpu)->pVMR3->enmVMState) : ""), \
1158	(rc))
1159
1160	#endif /* !VBOX_FOR_DTRACE_LIB */
1161
1162
1163	/**
1164	* Helper that HM and NEM uses for safely modifying VM::bMainExecutionEngine.
1165	*
1166	* ONLY HM and NEM MAY USE THIS!
1167	*
1168	* @param a_pVM The cross context VM structure.
1169	* @param a_bValue The new value.
1170	* @internal
1171	*/
1172	#define VM_SET_MAIN_EXECUTION_ENGINE(a_pVM, a_bValue) \
1173	do { \
1174	const_cast<uint8_t >(&(a_pVM)->bMainExecutionEngine) = (a_bValue); \
1175	ASMCompilerBarrier(); /* just to be on the safe side */ \
1176	} while (0)
1177
1178	/**
1179	* Checks whether iem-executes-all-mode is used.
1180	*
1181	* @retval true if IEM is used.
1182	* @retval false if not.
1183	*
1184	* @param a_pVM The cross context VM structure.
1185	* @sa VM_IS_HM_OR_NEM_ENABLED, VM_IS_HM_ENABLED, VM_IS_NEM_ENABLED.
1186	* @internal
1187	*/
1188	#define VM_IS_EXEC_ENGINE_IEM(a_pVM) ((a_pVM)->bMainExecutionEngine == VM_EXEC_ENGINE_IEM)
1189
1190	/**
1191	* Checks whether HM (VT-x/AMD-V) or NEM is being used by this VM.
1192	*
1193	* @retval true if either is used.
1194	* @retval false if software virtualization (raw-mode) is used.
1195	*
1196	* @param a_pVM The cross context VM structure.
1197	* @sa VM_IS_EXEC_ENGINE_IEM, VM_IS_HM_ENABLED, VM_IS_NEM_ENABLED.
1198	* @internal
1199	*/
1200	#define VM_IS_HM_OR_NEM_ENABLED(a_pVM) ((a_pVM)->bMainExecutionEngine != VM_EXEC_ENGINE_IEM)
1201
1202	/**
1203	* Checks whether HM is being used by this VM.
1204	*
1205	* @retval true if HM (VT-x/AMD-v) is used.
1206	* @retval false if not.
1207	*
1208	* @param a_pVM The cross context VM structure.
1209	* @sa VM_IS_NEM_ENABLED, VM_IS_EXEC_ENGINE_IEM, VM_IS_HM_OR_NEM_ENABLED.
1210	* @internal
1211	*/
1212	#define VM_IS_HM_ENABLED(a_pVM) ((a_pVM)->bMainExecutionEngine == VM_EXEC_ENGINE_HW_VIRT)
1213
1214	/**
1215	* Checks whether NEM is being used by this VM.
1216	*
1217	* @retval true if a native hypervisor API is used.
1218	* @retval false if not.
1219	*
1220	* @param a_pVM The cross context VM structure.
1221	* @sa VM_IS_HM_ENABLED, VM_IS_EXEC_ENGINE_IEM, VM_IS_HM_OR_NEM_ENABLED.
1222	* @internal
1223	*/
1224	#define VM_IS_NEM_ENABLED(a_pVM) ((a_pVM)->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API)
1225
1226
1227	/**
1228	* The cross context VM structure.
1229	*
1230	* It contains all the VM data which have to be available in all contexts.
1231	* Even if it contains all the data the idea is to use APIs not to modify all
1232	* the members all around the place. Therefore we make use of unions to hide
1233	* everything which isn't local to the current source module. This means we'll
1234	* have to pay a little bit of attention when adding new members to structures
1235	* in the unions and make sure to keep the padding sizes up to date.
1236	*
1237	* Run 'kmk run-struct-tests' (from src/VBox/VMM if you like) after updating!
1238	*/
1239	typedef struct VM
1240	{
1241	/** The state of the VM.
1242	* This field is read only to everyone except the VM and EM. */
1243	VMSTATE volatile enmVMState;
1244	/** Forced action flags.
1245	* See the VM_FF_* \#defines. Updated atomically.
1246	*/
1247	volatile uint32_t fGlobalForcedActions;
1248	/** Pointer to the array of page descriptors for the VM structure allocation. */
1249	R3PTRTYPE(PSUPPAGE) paVMPagesR3;
1250	/** Session handle. For use when calling SUPR0 APIs. */
1251	#ifdef IN_RING0
1252	PSUPDRVSESSION pSessionUnsafe;
1253	#else
1254	PSUPDRVSESSION pSession;
1255	#endif
1256	/** Pointer to the ring-3 VM structure. */
1257	PUVM pUVM;
1258	/** Ring-3 Host Context VM Pointer. */
1259	#ifdef IN_RING0
1260	R3PTRTYPE(struct VM *) pVMR3Unsafe;
1261	#else
1262	R3PTRTYPE(struct VM *) pVMR3;
1263	#endif
1264	/** Ring-0 Host Context VM pointer for making ring-0 calls. */
1265	R0PTRTYPE(struct VM *) pVMR0ForCall;
1266	/** Raw-mode Context VM Pointer. */
1267	uint32_t pVMRC;
1268	/** Padding for new raw-mode (long mode). */
1269	uint32_t pVMRCPadding;
1270
1271	/** The GVM VM handle. Only the GVM should modify this field. */
1272	#ifdef IN_RING0
1273	uint32_t hSelfUnsafe;
1274	#else
1275	uint32_t hSelf;
1276	#endif
1277	/** Number of virtual CPUs. */
1278	#ifdef IN_RING0
1279	uint32_t cCpusUnsafe;
1280	#else
1281	uint32_t cCpus;
1282	#endif
1283	/** CPU excution cap (1-100) */
1284	uint32_t uCpuExecutionCap;
1285
1286	/** Size of the VM structure. */
1287	uint32_t cbSelf;
1288	/** Size of the VMCPU structure. */
1289	uint32_t cbVCpu;
1290	/** Structure version number (TBD). */
1291	uint32_t uStructVersion;
1292
1293	/** @name Various items that are frequently accessed.
1294	* @{ */
1295	/** The main execution engine, VM_EXEC_ENGINE_XXX.
1296	* This is set early during vmR3InitRing3 by HM or NEM. */
1297	uint8_t const bMainExecutionEngine;
1298
1299	/** Hardware VM support is available and enabled.
1300	* Determined very early during init.
1301	* This is placed here for performance reasons.
1302	* @todo obsoleted by bMainExecutionEngine, eliminate. */
1303	bool fHMEnabled;
1304	/** @} */
1305
1306	/** Alignment padding. */
1307	uint8_t uPadding1[6];
1308
1309	/** @name Debugging
1310	* @{ */
1311	/** Ring-3 Host Context VM Pointer. */
1312	R3PTRTYPE(RTTRACEBUF) hTraceBufR3;
1313	/** Ring-0 Host Context VM Pointer. */
1314	R0PTRTYPE(RTTRACEBUF) hTraceBufR0;
1315	/** @} */
1316
1317	/** Max EMT hash lookup collisions (in GVMM). */
1318	uint8_t cMaxEmtHashCollisions;
1319
1320	/** Padding - the unions must be aligned on a 64 bytes boundary. */
1321	uint8_t abAlignment3[HC_ARCH_BITS == 64 ? 23 : 51];
1322
1323	/** CPUM part. */
1324	union
1325	{
1326	#if defined(VMM_INCLUDED_SRC_include_CPUMInternal_h) \|\| defined(VMM_INCLUDED_SRC_include_CPUMInternal_armv8_h)
1327	struct CPUM s;
1328	#endif
1329	#ifdef VBOX_INCLUDED_vmm_cpum_h
1330	/** Read only info exposed about the host and guest CPUs. */
1331	struct
1332	{
1333	/** Padding for hidden fields. */
1334	uint8_t abHidden0[64 + 48];
1335	/** Guest CPU feature information. */
1336	CPUMFEATURES GuestFeatures;
1337	} const ro;
1338	#endif
1339	/** @todo this is rather bloated because of static MSR range allocation.
1340	* Probably a good idea to move it to a separate R0 allocation... */
1341	uint8_t padding[8832 + 1288192 + 0x1d00]; / multiple of 64 */
1342	} cpum;
1343
1344	/** PGM part.
1345	* @note Aligned on 16384 boundrary for zero and mmio page storage. */
1346	union
1347	{
1348	#ifdef VMM_INCLUDED_SRC_include_PGMInternal_h
1349	struct PGM s;
1350	#endif
1351	uint8_t padding[129728]; /* multiple of 64 */
1352	} pgm;
1353
1354	/** VMM part. */
1355	union
1356	{
1357	#ifdef VMM_INCLUDED_SRC_include_VMMInternal_h
1358	struct VMM s;
1359	#endif
1360	uint8_t padding[1600]; /* multiple of 64 */
1361	} vmm;
1362
1363	/** HM part. */
1364	union
1365	{
1366	#ifdef VMM_INCLUDED_SRC_include_HMInternal_h
1367	struct HM s;
1368	#endif
1369	uint8_t padding[5504]; /* multiple of 64 */
1370	} hm;
1371
1372	/** TRPM part. */
1373	union
1374	{
1375	#ifdef VMM_INCLUDED_SRC_include_TRPMInternal_h
1376	struct TRPM s;
1377	#endif
1378	uint8_t padding[2048]; /* multiple of 64 */
1379	} trpm;
1380
1381	/** SELM part. */
1382	union
1383	{
1384	#ifdef VMM_INCLUDED_SRC_include_SELMInternal_h
1385	struct SELM s;
1386	#endif
1387	uint8_t padding[768]; /* multiple of 64 */
1388	} selm;
1389
1390	/** MM part. */
1391	union
1392	{
1393	#ifdef VMM_INCLUDED_SRC_include_MMInternal_h
1394	struct MM s;
1395	#endif
1396	uint8_t padding[192]; /* multiple of 64 */
1397	} mm;
1398
1399	/** PDM part. */
1400	union
1401	{
1402	#ifdef VMM_INCLUDED_SRC_include_PDMInternal_h
1403	struct PDM s;
1404	#endif
1405	uint8_t padding[22400]; /* multiple of 64 */
1406	} pdm;
1407
1408	/** IOM part. */
1409	union
1410	{
1411	#ifdef VMM_INCLUDED_SRC_include_IOMInternal_h
1412	struct IOM s;
1413	#endif
1414	uint8_t padding[1152]; /* multiple of 64 */
1415	} iom;
1416
1417	/** EM part. */
1418	union
1419	{
1420	#ifdef VMM_INCLUDED_SRC_include_EMInternal_h
1421	struct EM s;
1422	#endif
1423	uint8_t padding[256]; /* multiple of 64 */
1424	} em;
1425
1426	/** NEM part. */
1427	union
1428	{
1429	#ifdef VMM_INCLUDED_SRC_include_NEMInternal_h
1430	struct NEM s;
1431	#endif
1432	uint8_t padding[4608]; /* multiple of 64 */
1433	} nem;
1434
1435	/** TM part. */
1436	union
1437	{
1438	#ifdef VMM_INCLUDED_SRC_include_TMInternal_h
1439	struct TM s;
1440	#endif
1441	uint8_t padding[10112]; /* multiple of 64 */
1442	} tm;
1443
1444	/** DBGF part. */
1445	union
1446	{
1447	#ifdef VMM_INCLUDED_SRC_include_DBGFInternal_h
1448	struct DBGF s;
1449	#endif
1450	#ifdef VBOX_INCLUDED_vmm_dbgf_h
1451	/** Read only info exposed about interrupt breakpoints and selected events. */
1452	struct
1453	{
1454	/** Bitmap of enabled hardware interrupt breakpoints. */
1455	uint32_t bmHardIntBreakpoints[256 / 32];
1456	/** Bitmap of enabled software interrupt breakpoints. */
1457	uint32_t bmSoftIntBreakpoints[256 / 32];
1458	/** Bitmap of selected events.
1459	* This includes non-selectable events too for simplicity, we maintain the
1460	* state for some of these, as it may come in handy. */
1461	uint64_t bmSelectedEvents[(DBGFEVENT_END + 63) / 64];
1462	/** Enabled hardware interrupt breakpoints. */
1463	uint32_t cHardIntBreakpoints;
1464	/** Enabled software interrupt breakpoints. */
1465	uint32_t cSoftIntBreakpoints;
1466	/** The number of selected events. */
1467	uint32_t cSelectedEvents;
1468	/** The number of enabled hardware breakpoints. */
1469	uint8_t cEnabledHwBreakpoints;
1470	/** The number of enabled hardware I/O breakpoints. */
1471	uint8_t cEnabledHwIoBreakpoints;
1472	uint8_t au8Alignment1[2]; /*< Alignment padding. /
1473	/** The number of enabled INT3 breakpoints. */
1474	uint32_t volatile cEnabledInt3Breakpoints;
1475	} const ro;
1476	#endif
1477	uint8_t padding[2432]; /* multiple of 64 */
1478	} dbgf;
1479
1480	/** SSM part. */
1481	union
1482	{
1483	#ifdef VMM_INCLUDED_SRC_include_SSMInternal_h
1484	struct SSM s;
1485	#endif
1486	uint8_t padding[128]; /* multiple of 64 */
1487	} ssm;
1488
1489	union
1490	{
1491	#ifdef VMM_INCLUDED_SRC_include_GIMInternal_h
1492	struct GIM s;
1493	#endif
1494	uint8_t padding[448]; /* multiple of 64 */
1495	} gim;
1496
1497	#if defined(VBOX_VMM_TARGET_ARMV8)
1498	union
1499	{
1500	# ifdef VMM_INCLUDED_SRC_include_GICInternal_h
1501	struct GIC s;
1502	# endif
1503	uint8_t padding[128]; /* multiple of 8 */
1504	} gic;
1505	#else
1506	union
1507	{
1508	# ifdef VMM_INCLUDED_SRC_include_APICInternal_h
1509	struct APIC s;
1510	# endif
1511	uint8_t padding[128]; /* multiple of 8 */
1512	} apic;
1513	#endif
1514
1515	/* ---- begin small stuff ---- */
1516
1517	/** VM part. */
1518	union
1519	{
1520	#ifdef VMM_INCLUDED_SRC_include_VMInternal_h
1521	struct VMINT s;
1522	#endif
1523	uint8_t padding[32]; /* multiple of 8 */
1524	} vm;
1525
1526	/** CFGM part. */
1527	union
1528	{
1529	#ifdef VMM_INCLUDED_SRC_include_CFGMInternal_h
1530	struct CFGM s;
1531	#endif
1532	uint8_t padding[8]; /* multiple of 8 */
1533	} cfgm;
1534
1535	/** IEM part. */
1536	union
1537	{
1538	#ifdef VMM_INCLUDED_SRC_include_IEMInternal_h
1539	struct IEM s;
1540	#endif
1541	uint8_t padding[16]; /* multiple of 8 */
1542	} iem;
1543
1544	/** Statistics for ring-0 only components. */
1545	struct
1546	{
1547	/** GMMR0 stats. */
1548	struct
1549	{
1550	/** Chunk TLB hits. */
1551	uint64_t cChunkTlbHits;
1552	/** Chunk TLB misses. */
1553	uint64_t cChunkTlbMisses;
1554	} gmm;
1555	uint64_t au64Padding[6]; /* probably more comming here... */
1556	} R0Stats;
1557
1558	union
1559	{
1560	#ifdef VMM_INCLUDED_SRC_include_GCMInternal_h
1561	struct GCM s;
1562	#endif
1563	uint8_t padding[8]; /* multiple of 8 */
1564	} gcm;
1565
1566	/** Padding for aligning the structure size on a page boundrary. */
1567	uint8_t abAlignment2[0x3A80 - sizeof(PVMCPUR3) * VMM_MAX_CPU_COUNT];
1568
1569	/* ---- end small stuff ---- */
1570
1571	/** Array of VMCPU ring-3 pointers. */
1572	PVMCPUR3 apCpusR3[VMM_MAX_CPU_COUNT];
1573
1574	/* This point is aligned on a 16384 boundrary (for arm64 purposes). */
1575	} VM;
1576	#ifndef VBOX_FOR_DTRACE_LIB
1577	//AssertCompileSizeAlignment(VM, 16384);
1578	#endif
1579
1580
1581	#ifdef IN_RC
1582	RT_C_DECLS_BEGIN
1583
1584	/** The VM structure.
1585	* This is imported from the VMMRCBuiltin module, i.e. it's a one of those magic
1586	* globals which we should avoid using.
1587	*/
1588	extern DECLIMPORT(VM) g_VM;
1589
1590	/** The VMCPU structure for virtual CPU \#0.
1591	* This is imported from the VMMRCBuiltin module, i.e. it's a one of those magic
1592	* globals which we should avoid using.
1593	*/
1594	extern DECLIMPORT(VMCPU) g_VCpu0;
1595
1596	RT_C_DECLS_END
1597	#endif
1598
1599	/** @} */
1600
1601	#endif /* !VBOX_INCLUDED_vmm_vm_h */
1602

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source: vbox/trunk/include/VBox/vmm/vm.h@ 105076

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