vm.h@ 107894

Last change on this file since 107894 was 107894, checked in by vboxsync, 5 weeks ago
VMM: Check the target platform arch in VM_ASSERT_VALID_EXT_RETURN, VMCPU_ASSERT_VALID_EXT_RETURN and friends. jiraref:VBP-1470
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1	/** @file
2	* VM - The Virtual Machine, data.
3	*/
4
5	/*
6	* Copyright (C) 2006-2024 Oracle and/or its affiliates.
7	*
8	* This file is part of VirtualBox base platform packages, as
9	* available from https://www.virtualbox.org.
10	*
11	* This program is free software; you can redistribute it and/or
12	* modify it under the terms of the GNU General Public License
13	* as published by the Free Software Foundation, in version 3 of the
14	* License.
15	*
16	* This program is distributed in the hope that it will be useful, but
17	* WITHOUT ANY WARRANTY; without even the implied warranty of
18	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19	* General Public License for more details.
20	*
21	* You should have received a copy of the GNU General Public License
22	* along with this program; if not, see <https://www.gnu.org/licenses>.
23	*
24	* The contents of this file may alternatively be used under the terms
25	* of the Common Development and Distribution License Version 1.0
26	* (CDDL), a copy of it is provided in the "COPYING.CDDL" file included
27	* in the VirtualBox distribution, in which case the provisions of the
28	* CDDL are applicable instead of those of the GPL.
29	*
30	* You may elect to license modified versions of this file under the
31	* terms and conditions of either the GPL or the CDDL or both.
32	*
33	* SPDX-License-Identifier: GPL-3.0-only OR CDDL-1.0
34	*/
35
36	#ifndef VBOX_INCLUDED_vmm_vm_h
37	#define VBOX_INCLUDED_vmm_vm_h
38	#ifndef RT_WITHOUT_PRAGMA_ONCE
39	# pragma once
40	#endif
41
42	#ifndef VBOX_FOR_DTRACE_LIB
43	# ifndef USING_VMM_COMMON_DEFS
44	# error "Compile job does not include VMM_COMMON_DEFS from src/VBox/VMM/Config.kmk - make sure you really need to include this file!"
45	# endif
46	# include <iprt/param.h>
47	# include <VBox/param.h>
48	# include <VBox/types.h>
49	# include <VBox/vmm/cpum.h>
50	# include <VBox/vmm/stam.h>
51	# include <VBox/vmm/vmapi.h>
52	# include <VBox/vmm/vmm.h>
53	# include <VBox/sup.h>
54	#else
55	# pragma D depends_on library vbox-types.d
56	# pragma D depends_on library CPUMInternal.d
57	# define VMM_INCLUDED_SRC_include_CPUMInternal_h
58	# define VBOX_VMM_TARGET_AGNOSTIC
59	#endif
60
61	#if !defined(VBOX_VMM_TARGET_AGNOSTIC) \
62	&& !defined(VBOX_VMM_TARGET_X86) \
63	&& !defined(VBOX_VMM_TARGET_ARMV8)
64	# error "VMM target not defined"
65	#endif
66
67
68
69	/** @defgroup grp_vm The Virtual Machine
70	* @ingroup grp_vmm
71	* @{
72	*/
73
74	/**
75	* The state of a Virtual CPU.
76	*
77	* The basic state indicated here is whether the CPU has been started or not. In
78	* addition, there are sub-states when started for assisting scheduling (GVMM
79	* mostly).
80	*
81	* The transition out of the STOPPED state is done by a vmR3PowerOn.
82	* The transition back to the STOPPED state is done by vmR3PowerOff.
83	*
84	* (Alternatively we could let vmR3PowerOn start CPU 0 only and let the SPIP
85	* handling switch on the other CPUs. Then vmR3Reset would stop all but CPU 0.)
86	*/
87	typedef enum VMCPUSTATE
88	{
89	/** The customary invalid zero. */
90	VMCPUSTATE_INVALID = 0,
91
92	/** Virtual CPU has not yet been started. */
93	VMCPUSTATE_STOPPED,
94
95	/** CPU started. */
96	VMCPUSTATE_STARTED,
97	/** CPU started in HM context. */
98	VMCPUSTATE_STARTED_HM,
99	/** Executing guest code and can be poked (RC or STI bits of HM). */
100	VMCPUSTATE_STARTED_EXEC,
101	/** Executing guest code using NEM. */
102	VMCPUSTATE_STARTED_EXEC_NEM,
103	VMCPUSTATE_STARTED_EXEC_NEM_WAIT,
104	VMCPUSTATE_STARTED_EXEC_NEM_CANCELED,
105	/** Halted. */
106	VMCPUSTATE_STARTED_HALTED,
107
108	/** The end of valid virtual CPU states. */
109	VMCPUSTATE_END,
110
111	/** Ensure 32-bit type. */
112	VMCPUSTATE_32BIT_HACK = 0x7fffffff
113	} VMCPUSTATE;
114
115	/** Enables 64-bit FFs. */
116	#define VMCPU_WITH_64_BIT_FFS
117
118
119	/**
120	* The cross context virtual CPU structure.
121	*
122	* Run 'kmk run-struct-tests' (from src/VBox/VMM if you like) after updating!
123	*/
124	typedef struct VMCPU
125	{
126	/** @name Volatile per-cpu data.
127	* @{ */
128	/** Per CPU forced action.
129	* See the VMCPU_FF_* \#defines. Updated atomically. */
130	#ifdef VMCPU_WITH_64_BIT_FFS
131	uint64_t volatile fLocalForcedActions;
132	#else
133	uint32_t volatile fLocalForcedActions;
134	uint32_t fForLocalForcedActionsExpansion;
135	#endif
136	/** The CPU state. */
137	VMCPUSTATE volatile enmState;
138
139	#ifdef VBOX_VMM_TARGET_ARMV8
140	uint32_t u32Alignment0;
141	/** The number of nano seconds when the vTimer of the associated vCPU is supposed to activate
142	* required to get out of a halt (due to wfi/wfe).
143	*
144	* @note This actually should go into TMCPU but this drags in a whole lot of padding changes
145	* and I'm not sure yet whether this will remain in this form anyway.
146	*/
147	uint64_t cNsVTimerActivate;
148	/** Padding up to 64 bytes. */
149	uint8_t abAlignment0[64 - 12 - 8 - 4];
150	#else
151	/** Padding up to 64 bytes. */
152	uint8_t abAlignment0[64 - 12];
153	#endif
154	/** @} */
155
156	/** IEM part.
157	* @remarks This comes first as it allows the use of 8-bit immediates for the
158	* first 64 bytes of the structure, reducing code size a wee bit. */
159	#if defined(VMM_INCLUDED_SRC_include_IEMInternal_h) \|\| defined(VMM_INCLUDED_SRC_include_IEMInternal_armv8_h) /* For PDB hacking. */
160	union VMCPUUNIONIEMFULL
161	#else
162	union VMCPUUNIONIEMSTUB
163	#endif
164	{
165	#if defined(VMM_INCLUDED_SRC_include_IEMInternal_h) \|\| defined(VMM_INCLUDED_SRC_include_IEMInternal_armv8_h)
166	struct IEMCPU s;
167	#endif
168	uint8_t padding[ 129984 /* The common base size. */
169	#ifdef RT_ARCH_AMD64
170	+ 32768 /* For 256 entries per TLBs. */
171	#else
172	+ 1048576 /* For 8192 entries per TLBs. */
173	#endif
174	]; /* multiple of 64 */
175	} iem;
176
177	/** @name Static per-cpu data.
178	* (Putting this after IEM, hoping that it's less frequently used than it.)
179	* @{ */
180	/** Ring-3 Host Context VM Pointer. */
181	PVMR3 pVMR3;
182	/** Ring-0 Host Context VM Pointer, currently used by VTG/dtrace. */
183	RTR0PTR pVCpuR0ForVtg;
184	/** Raw-mode Context VM Pointer. */
185	uint32_t pVMRC;
186	/** Padding for new raw-mode (long mode). */
187	uint32_t pVMRCPadding;
188	/** Pointer to the ring-3 UVMCPU structure. */
189	PUVMCPU pUVCpu;
190	/** The native thread handle. */
191	RTNATIVETHREAD hNativeThread;
192	/** The native R0 thread handle. (different from the R3 handle!) */
193	RTNATIVETHREAD hNativeThreadR0;
194	/** The IPRT thread handle (for VMMDevTesting). */
195	RTTHREAD hThread;
196	/** The CPU ID.
197	* This is the index into the VM::aCpu array. */
198	#ifdef IN_RING0
199	VMCPUID idCpuUnsafe;
200	#else
201	VMCPUID idCpu;
202	#endif
203	/** The VM target platform architecture.
204	* Same as VM::enmTarget, GVM::enmTarget and GVMCPU::enmTarget. */
205	#ifdef IN_RING0
206	VMTARGET enmTargetUnsafe;
207	#else
208	VMTARGET enmTarget;
209	#endif
210
211	#if HC_ARCH_BITS != 64
212	/** Align the structures below bit on a 64-byte boundary and make sure it starts
213	* at the same offset in both 64-bit and 32-bit builds.
214	*
215	* @remarks The alignments of the members that are larger than 48 bytes should be
216	* 64-byte for cache line reasons. structs containing small amounts of
217	* data could be lumped together at the end with a < 64 byte padding
218	* following it (to grow into and align the struct size).
219	*/
220	uint8_t abAlignment1[64 - 6 * (HC_ARCH_BITS == 32 ? 4 : 8) - 8 - 4 - 4];
221	#endif
222	/** @} */
223
224	/** HM part. */
225	union VMCPUUNIONHM
226	{
227	#ifdef VMM_INCLUDED_SRC_include_HMInternal_h
228	struct HMCPU s;
229	#endif
230	uint8_t padding[9984]; /* multiple of 64 */
231	} hm;
232
233	/** NEM part. */
234	union VMCPUUNIONNEM
235	{
236	#ifdef VMM_INCLUDED_SRC_include_NEMInternal_h
237	struct NEMCPU s;
238	#endif
239	uint8_t padding[4608]; /* multiple of 64 */
240	} nem;
241
242	/** TRPM part. */
243	union VMCPUUNIONTRPM
244	{
245	#ifdef VMM_INCLUDED_SRC_include_TRPMInternal_h
246	struct TRPMCPU s;
247	#endif
248	uint8_t padding[128]; /* multiple of 64 */
249	} trpm;
250
251	/** TM part. */
252	union VMCPUUNIONTM
253	{
254	#ifdef VMM_INCLUDED_SRC_include_TMInternal_h
255	struct TMCPU s;
256	#endif
257	uint8_t padding[5760]; /* multiple of 64 */
258	} tm;
259
260	/** VMM part. */
261	union VMCPUUNIONVMM
262	{
263	#ifdef VMM_INCLUDED_SRC_include_VMMInternal_h
264	struct VMMCPU s;
265	#endif
266	uint8_t padding[9536]; /* multiple of 64 */
267	} vmm;
268
269	/** PDM part. */
270	union VMCPUUNIONPDM
271	{
272	#ifdef VMM_INCLUDED_SRC_include_PDMInternal_h
273	struct PDMCPU s;
274	#endif
275	uint8_t padding[256]; /* multiple of 64 */
276	} pdm;
277
278	/** IOM part. */
279	union VMCPUUNIONIOM
280	{
281	#ifdef VMM_INCLUDED_SRC_include_IOMInternal_h
282	struct IOMCPU s;
283	#endif
284	uint8_t padding[512]; /* multiple of 64 */
285	} iom;
286
287	/** DBGF part.
288	* @todo Combine this with other tiny structures. */
289	union VMCPUUNIONDBGF
290	{
291	#ifdef VMM_INCLUDED_SRC_include_DBGFInternal_h
292	struct DBGFCPU s;
293	#endif
294	uint8_t padding[512]; /* multiple of 64 */
295	} dbgf;
296
297	/** GIM part. */
298	union VMCPUUNIONGIM
299	{
300	#ifdef VMM_INCLUDED_SRC_include_GIMInternal_h
301	struct GIMCPU s;
302	#endif
303	uint8_t padding[512]; /* multiple of 64 */
304	} gim;
305
306	/* Interrupt controller, target specific. */
307	RT_GCC_EXTENSION
308	union
309	{
310	#if defined(VBOX_VMM_TARGET_ARMV8) \|\| defined(VBOX_VMM_TARGET_AGNOSTIC)
311	/** GIC part. */
312	union
313	{
314	# ifdef VMM_INCLUDED_SRC_include_GICInternal_h
315	struct GICCPU s;
316	# endif
317	uint8_t padding[3840]; /* multiple of 64 */
318	} gic;
319	#endif
320	#if defined(VBOX_VMM_TARGET_X86) \|\| defined(VBOX_VMM_TARGET_AGNOSTIC)
321	/** APIC part. */
322	union
323	{
324	# ifdef VMM_INCLUDED_SRC_include_APICInternal_h
325	struct APICCPU s;
326	# endif
327	uint8_t padding[3840]; /* multiple of 64 */
328	} apic;
329	#endif
330	};
331
332	/*
333	* Some less frequently used global members that doesn't need to take up
334	* precious space at the head of the structure.
335	*/
336
337	/** Trace groups enable flags. */
338	uint32_t fTraceGroups; /* 64 / 44 */
339	/** Number of collisions hashing the ring-0 EMT handle. */
340	uint8_t cEmtHashCollisions;
341	uint8_t abAdHoc[3];
342	/** Profiling samples for use by ad hoc profiling. */
343	STAMPROFILEADV aStatAdHoc[8]; /* size: 408 = 320 /
344
345	/** Align the following members on page boundary. */
346	uint8_t abAlignment2[1848];
347
348	/** PGM part. */
349	union VMCPUUNIONPGM
350	{
351	#ifdef VMM_INCLUDED_SRC_include_PGMInternal_h
352	struct PGMCPU s;
353	#endif
354	uint8_t padding[36864]; /* multiple of 4096 */
355	} pgm;
356
357	/** CPUM part. */
358	union VMCPUUNIONCPUM
359	{
360	#if defined(VMM_INCLUDED_SRC_include_CPUMInternal_h) \|\| defined(VMM_INCLUDED_SRC_include_CPUMInternal_armv8_h)
361	struct CPUMCPU s;
362	#endif
363	#ifdef VMCPU_INCL_CPUM_GST_CTX
364	/** The guest CPUM context for direct use by execution engines.
365	* This is not for general consumption, but for HM, REM, IEM, and maybe a few
366	* others. The rest will use the function based CPUM API. */
367	CPUMCTX GstCtx;
368	#endif
369	uint8_t padding[102400]; /* multiple of 4096 */
370	} cpum;
371
372	/** EM part. */
373	union VMCPUUNIONEM
374	{
375	#ifdef VMM_INCLUDED_SRC_include_EMInternal_h
376	struct EMCPU s;
377	#endif
378	uint8_t padding[40960]; /* multiple of 4096 */
379	} em;
380	uint8_t abPadding[12288];
381	} VMCPU;
382
383
384	#ifndef VBOX_FOR_DTRACE_LIB
385	# ifndef IN_TSTVMSTRUCT
386	/* Make sure the structure size is aligned on a 16384 boundary for arm64 purposes. */
387	AssertCompileSizeAlignment(VMCPU, 16384);
388	# endif
389
390	/** @name Operations on VMCPU::enmState
391	* @{ */
392	/** Gets the VMCPU state. */
393	#define VMCPU_GET_STATE(pVCpu) ( (pVCpu)->enmState )
394	/** Sets the VMCPU state. */
395	#define VMCPU_SET_STATE(pVCpu, enmNewState) \
396	ASMAtomicWriteU32((uint32_t volatile *)&(pVCpu)->enmState, (enmNewState))
397	/** Cmpares and sets the VMCPU state. */
398	#define VMCPU_CMPXCHG_STATE(pVCpu, enmNewState, enmOldState) \
399	ASMAtomicCmpXchgU32((uint32_t volatile *)&(pVCpu)->enmState, (enmNewState), (enmOldState))
400	/** Checks the VMCPU state. */
401	#ifdef VBOX_STRICT
402	# define VMCPU_ASSERT_STATE(pVCpu, enmExpectedState) \
403	do { \
404	VMCPUSTATE enmState = VMCPU_GET_STATE(pVCpu); \
405	AssertMsg(enmState == (enmExpectedState), \
406	("enmState=%d enmExpectedState=%d idCpu=%u\n", \
407	enmState, enmExpectedState, (pVCpu)->idCpu)); \
408	} while (0)
409
410	# define VMCPU_ASSERT_STATE_2(pVCpu, enmExpectedState, a_enmExpectedState2) \
411	do { \
412	VMCPUSTATE enmState = VMCPU_GET_STATE(pVCpu); \
413	AssertMsg( enmState == (enmExpectedState) \
414	\|\| enmState == (a_enmExpectedState2), \
415	("enmState=%d enmExpectedState=%d enmExpectedState2=%d idCpu=%u\n", \
416	enmState, enmExpectedState, a_enmExpectedState2, (pVCpu)->idCpu)); \
417	} while (0)
418	#else
419	# define VMCPU_ASSERT_STATE(pVCpu, enmExpectedState) do { } while (0)
420	# define VMCPU_ASSERT_STATE_2(pVCpu, enmExpectedState, a_enmExpectedState2) do { } while (0)
421	#endif
422	/** Tests if the state means that the CPU is started. */
423	#define VMCPUSTATE_IS_STARTED(enmState) ( (enmState) > VMCPUSTATE_STOPPED )
424	/** Tests if the state means that the CPU is stopped. */
425	#define VMCPUSTATE_IS_STOPPED(enmState) ( (enmState) == VMCPUSTATE_STOPPED )
426	/** @} */
427
428
429	/** The name of the raw-mode context VMM Core module. */
430	#define VMMRC_MAIN_MODULE_NAME "VMMRC.rc"
431	/** The name of the ring-0 context VMM Core module. */
432	#define VMMR0_MAIN_MODULE_NAME "VMMR0.r0"
433
434
435	/** VM Forced Action Flags.
436	*
437	* Use the VM_FF_SET() and VM_FF_CLEAR() macros to change the force
438	* action mask of a VM.
439	*
440	* Available VM bits:
441	* 5, 6, 7, 13, 14, 15, 16, 17, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30
442	*
443	*
444	* Available VMCPU bits:
445	* 14, 15, 36 to 63
446	*
447	* @todo If we run low on VMCPU, we may consider merging the SELM bits
448	*
449	* @{
450	*/
451	/* Bit 0, bit 1: Reserved and must not be reused. The recompiler ASSUMES it
452	can OR the local and global FFs together and keept the two
453	VMCPU_FF_INTERRUPT_XXX flags uncorrupted. */
454	/** The virtual sync clock has been stopped, go to TM until it has been
455	* restarted... */
456	#define VM_FF_TM_VIRTUAL_SYNC RT_BIT_32(VM_FF_TM_VIRTUAL_SYNC_BIT)
457	#define VM_FF_TM_VIRTUAL_SYNC_BIT 2
458	/** PDM Queues are pending. */
459	#define VM_FF_PDM_QUEUES RT_BIT_32(VM_FF_PDM_QUEUES_BIT)
460	/** The bit number for VM_FF_PDM_QUEUES. */
461	#define VM_FF_PDM_QUEUES_BIT 3
462	/** PDM DMA transfers are pending. */
463	#define VM_FF_PDM_DMA RT_BIT_32(VM_FF_PDM_DMA_BIT)
464	/** The bit number for VM_FF_PDM_DMA. */
465	#define VM_FF_PDM_DMA_BIT 4
466	/** This action forces the VM to call DBGF so DBGF can service debugger
467	* requests in the emulation thread.
468	* This action flag stays asserted till DBGF clears it.*/
469	#define VM_FF_DBGF RT_BIT_32(VM_FF_DBGF_BIT)
470	/** The bit number for VM_FF_DBGF. */
471	#define VM_FF_DBGF_BIT 8
472	/** This action forces the VM to service pending requests from other
473	* thread or requests which must be executed in another context. */
474	#define VM_FF_REQUEST RT_BIT_32(VM_FF_REQUEST_BIT)
475	#define VM_FF_REQUEST_BIT 9
476	/** Check for VM state changes and take appropriate action. */
477	#define VM_FF_CHECK_VM_STATE RT_BIT_32(VM_FF_CHECK_VM_STATE_BIT)
478	/** The bit number for VM_FF_CHECK_VM_STATE. */
479	#define VM_FF_CHECK_VM_STATE_BIT 10
480	/** Reset the VM. (postponed) */
481	#define VM_FF_RESET RT_BIT_32(VM_FF_RESET_BIT)
482	/** The bit number for VM_FF_RESET. */
483	#define VM_FF_RESET_BIT 11
484	/** EMT rendezvous in VMM. */
485	#define VM_FF_EMT_RENDEZVOUS RT_BIT_32(VM_FF_EMT_RENDEZVOUS_BIT)
486	/** The bit number for VM_FF_EMT_RENDEZVOUS. */
487	#define VM_FF_EMT_RENDEZVOUS_BIT 12
488
489	/** PGM needs to allocate handy pages. */
490	#define VM_FF_PGM_NEED_HANDY_PAGES RT_BIT_32(VM_FF_PGM_NEED_HANDY_PAGES_BIT)
491	#define VM_FF_PGM_NEED_HANDY_PAGES_BIT 18
492	/** PGM is out of memory.
493	* Abandon all loops and code paths which can be resumed and get up to the EM
494	* loops. */
495	#define VM_FF_PGM_NO_MEMORY RT_BIT_32(VM_FF_PGM_NO_MEMORY_BIT)
496	#define VM_FF_PGM_NO_MEMORY_BIT 19
497	/** PGM is about to perform a lightweight pool flush
498	* Guest SMP: all EMT threads should return to ring 3
499	*/
500	#define VM_FF_PGM_POOL_FLUSH_PENDING RT_BIT_32(VM_FF_PGM_POOL_FLUSH_PENDING_BIT)
501	#define VM_FF_PGM_POOL_FLUSH_PENDING_BIT 20
502	/** Suspend the VM - debug only. */
503	#define VM_FF_DEBUG_SUSPEND RT_BIT_32(VM_FF_DEBUG_SUSPEND_BIT)
504	#define VM_FF_DEBUG_SUSPEND_BIT 31
505
506
507	#if defined(VBOX_VMM_TARGET_ARMV8) \|\| defined(VBOX_VMM_TARGET_AGNOSTIC)
508	/** This action forces the VM to inject an IRQ into the guest. */
509	# define VMCPU_FF_INTERRUPT_IRQ RT_BIT_64(VMCPU_FF_INTERRUPT_IRQ_BIT)
510	# define VMCPU_FF_INTERRUPT_IRQ_BIT 0
511	/** This action forces the VM to inject an FIQ into the guest. */
512	# define VMCPU_FF_INTERRUPT_FIQ RT_BIT_64(VMCPU_FF_INTERRUPT_FIQ_BIT)
513	# define VMCPU_FF_INTERRUPT_FIQ_BIT 1
514	#endif
515	#if defined(VBOX_VMM_TARGET_X86) \|\| defined(VBOX_VMM_TARGET_AGNOSTIC)
516	/** This action forces the VM to check any pending interrupts on the APIC. */
517	# define VMCPU_FF_INTERRUPT_APIC RT_BIT_64(VMCPU_FF_INTERRUPT_APIC_BIT)
518	# define VMCPU_FF_INTERRUPT_APIC_BIT 0
519	/** This action forces the VM to check any pending interrups on the PIC. */
520	# define VMCPU_FF_INTERRUPT_PIC RT_BIT_64(VMCPU_FF_INTERRUPT_PIC_BIT)
521	# define VMCPU_FF_INTERRUPT_PIC_BIT 1
522	#endif
523	/** This action forces the VM to schedule and run pending timer (TM).
524	* @remarks Don't move - PATM compatibility. */
525	#define VMCPU_FF_TIMER RT_BIT_64(VMCPU_FF_TIMER_BIT)
526	#define VMCPU_FF_TIMER_BIT 2
527	/** This action forces the VM to check any pending NMIs. */
528	#define VMCPU_FF_INTERRUPT_NMI RT_BIT_64(VMCPU_FF_INTERRUPT_NMI_BIT)
529	#define VMCPU_FF_INTERRUPT_NMI_BIT 3
530	/** This action forces the VM to check any pending SMIs. */
531	#define VMCPU_FF_INTERRUPT_SMI RT_BIT_64(VMCPU_FF_INTERRUPT_SMI_BIT)
532	#define VMCPU_FF_INTERRUPT_SMI_BIT 4
533	/** PDM critical section unlocking is pending, process promptly upon return to R3. */
534	#define VMCPU_FF_PDM_CRITSECT RT_BIT_64(VMCPU_FF_PDM_CRITSECT_BIT)
535	#define VMCPU_FF_PDM_CRITSECT_BIT 5
536	/** Special EM internal force flag that is used by EMUnhaltAndWakeUp() to force
537	* the virtual CPU out of the next (/current) halted state. It is not processed
538	* nor cleared by emR3ForcedActions (similar to VMCPU_FF_BLOCK_NMIS), instead it
539	* is cleared the next time EM leaves the HALTED state. */
540	#define VMCPU_FF_UNHALT RT_BIT_64(VMCPU_FF_UNHALT_BIT)
541	#define VMCPU_FF_UNHALT_BIT 6
542	/** Pending IEM action (mask). */
543	#define VMCPU_FF_IEM RT_BIT_64(VMCPU_FF_IEM_BIT)
544	/** Pending IEM action (bit number). */
545	#define VMCPU_FF_IEM_BIT 7
546	/** Pending APIC action (bit number). */
547	#define VMCPU_FF_UPDATE_APIC_BIT 8
548	/** This action forces the VM to update APIC's asynchronously arrived
549	* interrupts as pending interrupts. */
550	#define VMCPU_FF_UPDATE_APIC RT_BIT_64(VMCPU_FF_UPDATE_APIC_BIT)
551	/** This action forces the VM to service pending requests from other
552	* thread or requests which must be executed in another context. */
553	#define VMCPU_FF_REQUEST RT_BIT_64(VMCPU_FF_REQUEST_BIT)
554	#define VMCPU_FF_REQUEST_BIT 9
555	/** Pending DBGF event (alternative to passing VINF_EM_DBG_EVENT around). */
556	#define VMCPU_FF_DBGF RT_BIT_64(VMCPU_FF_DBGF_BIT)
557	/** The bit number for VMCPU_FF_DBGF. */
558	#define VMCPU_FF_DBGF_BIT 10
559	/** Hardware virtualized nested-guest interrupt pending. */
560	#define VMCPU_FF_INTERRUPT_NESTED_GUEST RT_BIT_64(VMCPU_FF_INTERRUPT_NESTED_GUEST_BIT)
561	#define VMCPU_FF_INTERRUPT_NESTED_GUEST_BIT 11
562	/** This action forces PGM to update changes to CR3 when the guest was in HM mode
563	* (when using nested paging). */
564	#define VMCPU_FF_HM_UPDATE_CR3 RT_BIT_64(VMCPU_FF_HM_UPDATE_CR3_BIT)
565	#define VMCPU_FF_HM_UPDATE_CR3_BIT 12
566	#if defined(VBOX_VMM_TARGET_ARMV8) \|\| defined(VBOX_VMM_TARGET_AGNOSTIC)
567	# define VMCPU_FF_VTIMER_ACTIVATED RT_BIT_64(VMCPU_FF_VTIMER_ACTIVATED_BIT)
568	# define VMCPU_FF_VTIMER_ACTIVATED_BIT 13
569	#endif
570	#if defined(VBOX_VMM_TARGET_X86) \|\| defined(VBOX_VMM_TARGET_AGNOSTIC)
571	/* Bit 13 used to be VMCPU_FF_HM_UPDATE_PAE_PDPES. */
572	#endif
573	/** This action forces the VM to resync the page tables before going
574	* back to execute guest code. (GLOBAL FLUSH) */
575	#define VMCPU_FF_PGM_SYNC_CR3 RT_BIT_64(VMCPU_FF_PGM_SYNC_CR3_BIT)
576	#define VMCPU_FF_PGM_SYNC_CR3_BIT 16
577	/** Same as VM_FF_PGM_SYNC_CR3 except that global pages can be skipped.
578	* (NON-GLOBAL FLUSH) */
579	#define VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL RT_BIT_64(VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL_BIT)
580	#define VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL_BIT 17
581	/** Check for pending TLB shootdown actions (deprecated)
582	* Reserved for future HM re-use if necessary / safe.
583	* Consumer: HM */
584	#define VMCPU_FF_TLB_SHOOTDOWN_UNUSED RT_BIT_64(VMCPU_FF_TLB_SHOOTDOWN_UNUSED_BIT)
585	#define VMCPU_FF_TLB_SHOOTDOWN_UNUSED_BIT 18
586	/** Check for pending TLB flush action.
587	* Consumer: HM
588	* @todo rename to VMCPU_FF_HM_TLB_FLUSH */
589	#define VMCPU_FF_TLB_FLUSH RT_BIT_64(VMCPU_FF_TLB_FLUSH_BIT)
590	/** The bit number for VMCPU_FF_TLB_FLUSH. */
591	#define VMCPU_FF_TLB_FLUSH_BIT 19
592	/* 20 used to be VMCPU_FF_TRPM_SYNC_IDT (raw-mode only). */
593	/* 21 used to be VMCPU_FF_SELM_SYNC_TSS (raw-mode only). */
594	/* 22 used to be VMCPU_FF_SELM_SYNC_GDT (raw-mode only). */
595	/* 23 used to be VMCPU_FF_SELM_SYNC_LDT (raw-mode only). */
596	/* 24 used to be VMCPU_FF_INHIBIT_INTERRUPTS, which moved to CPUMCTX::eflags.uBoth in v7.0.4. */
597	/* 25 used to be VMCPU_FF_BLOCK_NMIS, which moved to CPUMCTX::eflags.uBoth in v7.0.4. */
598	/** Force return to Ring-3. */
599	#define VMCPU_FF_TO_R3 RT_BIT_64(VMCPU_FF_TO_R3_BIT)
600	#define VMCPU_FF_TO_R3_BIT 28
601	/** Force return to ring-3 to service pending I/O or MMIO write.
602	* This is a backup for mechanism VINF_IOM_R3_IOPORT_COMMIT_WRITE and
603	* VINF_IOM_R3_MMIO_COMMIT_WRITE, allowing VINF_EM_DBG_BREAKPOINT and similar
604	* status codes to be propagated at the same time without loss. */
605	#define VMCPU_FF_IOM RT_BIT_64(VMCPU_FF_IOM_BIT)
606	#define VMCPU_FF_IOM_BIT 29
607	/* 30 used to be VMCPU_FF_CPUM */
608	/** VMX-preemption timer expired. */
609	#define VMCPU_FF_VMX_PREEMPT_TIMER RT_BIT_64(VMCPU_FF_VMX_PREEMPT_TIMER_BIT)
610	#define VMCPU_FF_VMX_PREEMPT_TIMER_BIT 31
611	/** Pending MTF (Monitor Trap Flag) event. */
612	#define VMCPU_FF_VMX_MTF RT_BIT_64(VMCPU_FF_VMX_MTF_BIT)
613	#define VMCPU_FF_VMX_MTF_BIT 32
614	/** VMX APIC-write emulation pending.
615	* @todo possible candidate for internal EFLAGS, or maybe just a summary bit
616	* (see also VMCPU_FF_VMX_INT_WINDOW). */
617	#define VMCPU_FF_VMX_APIC_WRITE RT_BIT_64(VMCPU_FF_VMX_APIC_WRITE_BIT)
618	#define VMCPU_FF_VMX_APIC_WRITE_BIT 33
619	/** VMX interrupt-window event pending.
620	*
621	* "Pending" is misleading here, it would be better to say that the event need
622	* to be generated at the next opportunity and that this flag causes it to be
623	* polled for on every instruction boundrary and such.
624	*
625	* @todo Change the IEM side of this to not poll but to track down the places
626	* where it can be generated and set an internal EFLAGS bit that causes it
627	* to be checked out when finishing the current instruction. */
628	#define VMCPU_FF_VMX_INT_WINDOW RT_BIT_64(VMCPU_FF_VMX_INT_WINDOW_BIT)
629	#define VMCPU_FF_VMX_INT_WINDOW_BIT 34
630	/** VMX NMI-window event pending.
631	* Same "pending" comment and todo in VMCPU_FF_VMX_INT_WINDOW. */
632	#define VMCPU_FF_VMX_NMI_WINDOW RT_BIT_64(VMCPU_FF_VMX_NMI_WINDOW_BIT)
633	#define VMCPU_FF_VMX_NMI_WINDOW_BIT 35
634
635
636	/** Externally VM forced actions. Used to quit the idle/wait loop. */
637	#define VM_FF_EXTERNAL_SUSPENDED_MASK ( VM_FF_CHECK_VM_STATE \| VM_FF_DBGF \| VM_FF_REQUEST \| VM_FF_EMT_RENDEZVOUS )
638	/** Externally VMCPU forced actions. Used to quit the idle/wait loop. */
639	#define VMCPU_FF_EXTERNAL_SUSPENDED_MASK ( VMCPU_FF_REQUEST \| VMCPU_FF_DBGF )
640
641	/** Externally forced VM actions. Used to quit the idle/wait loop. */
642	#define VM_FF_EXTERNAL_HALTED_MASK ( VM_FF_CHECK_VM_STATE \| VM_FF_DBGF \| VM_FF_REQUEST \
643	\| VM_FF_PDM_QUEUES \| VM_FF_PDM_DMA \| VM_FF_EMT_RENDEZVOUS )
644
645	#ifndef VBOX_VMM_TARGET_AGNOSTIC
646	/** Externally forced VMCPU actions. Used to quit the idle/wait loop. */
647	# if defined(VBOX_VMM_TARGET_ARMV8)
648	# define VMCPU_FF_EXTERNAL_HALTED_MASK ( VMCPU_FF_INTERRUPT_IRQ \| VMCPU_FF_INTERRUPT_FIQ \
649	\| VMCPU_FF_REQUEST \| VMCPU_FF_INTERRUPT_NMI \| VMCPU_FF_INTERRUPT_SMI \
650	\| VMCPU_FF_UNHALT \| VMCPU_FF_TIMER \| VMCPU_FF_DBGF \
651	\| VMCPU_FF_VTIMER_ACTIVATED)
652	# else
653	# define VMCPU_FF_EXTERNAL_HALTED_MASK ( VMCPU_FF_UPDATE_APIC \| VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC \
654	\| VMCPU_FF_REQUEST \| VMCPU_FF_INTERRUPT_NMI \| VMCPU_FF_INTERRUPT_SMI \
655	\| VMCPU_FF_UNHALT \| VMCPU_FF_TIMER \| VMCPU_FF_DBGF \
656	\| VMCPU_FF_INTERRUPT_NESTED_GUEST)
657	# endif
658	#endif
659
660	/** High priority VM pre-execution actions. */
661	#define VM_FF_HIGH_PRIORITY_PRE_MASK ( VM_FF_CHECK_VM_STATE \| VM_FF_DBGF \| VM_FF_TM_VIRTUAL_SYNC \
662	\| VM_FF_DEBUG_SUSPEND \| VM_FF_PGM_NEED_HANDY_PAGES \| VM_FF_PGM_NO_MEMORY \
663	\| VM_FF_EMT_RENDEZVOUS )
664	#ifndef VBOX_VMM_TARGET_AGNOSTIC
665	/** High priority VMCPU pre-execution actions. */
666	# if defined(VBOX_VMM_TARGET_ARMV8)
667	# define VMCPU_FF_HIGH_PRIORITY_PRE_MASK ( VMCPU_FF_TIMER \| VMCPU_FF_INTERRUPT_IRQ \| VMCPU_FF_INTERRUPT_FIQ \
668	\| VMCPU_FF_DBGF )
669	# else
670	# define VMCPU_FF_HIGH_PRIORITY_PRE_MASK ( VMCPU_FF_TIMER \| VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC \
671	\| VMCPU_FF_UPDATE_APIC \| VMCPU_FF_DBGF \
672	\| VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL \
673	\| VMCPU_FF_INTERRUPT_NESTED_GUEST \| VMCPU_FF_VMX_MTF \| VMCPU_FF_VMX_APIC_WRITE \
674	\| VMCPU_FF_VMX_PREEMPT_TIMER \| VMCPU_FF_VMX_NMI_WINDOW \| VMCPU_FF_VMX_INT_WINDOW )
675	# endif
676	#endif
677
678	/** High priority VM pre raw-mode execution mask. */
679	#define VM_FF_HIGH_PRIORITY_PRE_RAW_MASK ( VM_FF_PGM_NEED_HANDY_PAGES \| VM_FF_PGM_NO_MEMORY )
680	/** High priority VMCPU pre raw-mode execution mask. */
681	#define VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK ( VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL )
682
683	/** High priority post-execution actions. */
684	#define VM_FF_HIGH_PRIORITY_POST_MASK ( VM_FF_PGM_NO_MEMORY )
685	/** High priority post-execution actions. */
686	#define VMCPU_FF_HIGH_PRIORITY_POST_MASK ( VMCPU_FF_PDM_CRITSECT \| VMCPU_FF_HM_UPDATE_CR3 \| VMCPU_FF_IEM \| VMCPU_FF_IOM )
687
688	/** Normal priority VM post-execution actions. */
689	#define VM_FF_NORMAL_PRIORITY_POST_MASK ( VM_FF_CHECK_VM_STATE \| VM_FF_DBGF \| VM_FF_RESET \
690	\| VM_FF_PGM_NO_MEMORY \| VM_FF_EMT_RENDEZVOUS)
691	/** Normal priority VMCPU post-execution actions. */
692	#define VMCPU_FF_NORMAL_PRIORITY_POST_MASK ( VMCPU_FF_DBGF )
693
694	/** Normal priority VM actions. */
695	#define VM_FF_NORMAL_PRIORITY_MASK ( VM_FF_REQUEST \| VM_FF_PDM_QUEUES \| VM_FF_PDM_DMA \| VM_FF_EMT_RENDEZVOUS)
696	/** Normal priority VMCPU actions. */
697	#define VMCPU_FF_NORMAL_PRIORITY_MASK ( VMCPU_FF_REQUEST )
698
699	/** Flags to clear before resuming guest execution. */
700	#define VMCPU_FF_RESUME_GUEST_MASK ( VMCPU_FF_TO_R3 )
701
702
703	/** VM flags that cause the REP[\|NE\|E] STRINS loops to yield immediately. */
704	#define VM_FF_HIGH_PRIORITY_POST_REPSTR_MASK ( VM_FF_TM_VIRTUAL_SYNC \| VM_FF_PGM_NEED_HANDY_PAGES \| VM_FF_PGM_NO_MEMORY \
705	\| VM_FF_EMT_RENDEZVOUS \| VM_FF_PGM_POOL_FLUSH_PENDING \| VM_FF_RESET)
706	/** VM flags that cause the REP[\|NE\|E] STRINS loops to yield. */
707	#define VM_FF_YIELD_REPSTR_MASK ( VM_FF_HIGH_PRIORITY_POST_REPSTR_MASK \
708	\| VM_FF_PDM_QUEUES \| VM_FF_PDM_DMA \| VM_FF_DBGF \| VM_FF_DEBUG_SUSPEND )
709	/** VMCPU flags that cause the REP[\|NE\|E] STRINS loops to yield immediately. */
710	#ifdef IN_RING3
711	# define VMCPU_FF_HIGH_PRIORITY_POST_REPSTR_MASK (VMCPU_FF_DBGF \| VMCPU_FF_VMX_MTF)
712	#else
713	# define VMCPU_FF_HIGH_PRIORITY_POST_REPSTR_MASK (VMCPU_FF_TO_R3 \| VMCPU_FF_IEM \| VMCPU_FF_IOM \| VMCPU_FF_DBGF \| VMCPU_FF_VMX_MTF)
714	#endif
715
716	#if defined(VBOX_VMM_TARGET_X86) \|\| defined(VBOX_VMM_TARGET_AGNOSTIC)
717	/** VMCPU flags that cause the REP[\|NE\|E] STRINS loops to yield, interrupts
718	* enabled. */
719	# define VMCPU_FF_YIELD_REPSTR_MASK ( VMCPU_FF_HIGH_PRIORITY_POST_REPSTR_MASK \
720	\| VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_UPDATE_APIC \| VMCPU_FF_INTERRUPT_PIC \
721	\| VMCPU_FF_INTERRUPT_NMI \| VMCPU_FF_INTERRUPT_SMI \| VMCPU_FF_PDM_CRITSECT \
722	\| VMCPU_FF_TIMER \| VMCPU_FF_REQUEST \
723	\| VMCPU_FF_INTERRUPT_NESTED_GUEST )
724	/** VMCPU flags that cause the REP[\|NE\|E] STRINS loops to yield, interrupts
725	* disabled. */
726	# define VMCPU_FF_YIELD_REPSTR_NOINT_MASK ( VMCPU_FF_YIELD_REPSTR_MASK \
727	& ~( VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_UPDATE_APIC \| VMCPU_FF_INTERRUPT_PIC \
728	\| VMCPU_FF_INTERRUPT_NESTED_GUEST) )
729	#endif
730
731	/** VM Flags that cause the HM loops to go back to ring-3. */
732	#define VM_FF_HM_TO_R3_MASK ( VM_FF_TM_VIRTUAL_SYNC \| VM_FF_PGM_NEED_HANDY_PAGES \| VM_FF_PGM_NO_MEMORY \
733	\| VM_FF_PDM_QUEUES \| VM_FF_EMT_RENDEZVOUS)
734	/** VMCPU Flags that cause the HM loops to go back to ring-3. */
735	#define VMCPU_FF_HM_TO_R3_MASK ( VMCPU_FF_TO_R3 \| VMCPU_FF_TIMER \| VMCPU_FF_PDM_CRITSECT \
736	\| VMCPU_FF_IEM \| VMCPU_FF_IOM)
737
738	/** High priority ring-0 VM pre HM-mode execution mask. */
739	#define VM_FF_HP_R0_PRE_HM_MASK (VM_FF_HM_TO_R3_MASK \| VM_FF_REQUEST \| VM_FF_PGM_POOL_FLUSH_PENDING \| VM_FF_PDM_DMA)
740	/** High priority ring-0 VMCPU pre HM-mode execution mask. */
741	#define VMCPU_FF_HP_R0_PRE_HM_MASK ( VMCPU_FF_HM_TO_R3_MASK \| VMCPU_FF_PGM_SYNC_CR3 \
742	\| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL \| VMCPU_FF_REQUEST \
743	\| VMCPU_FF_VMX_APIC_WRITE \| VMCPU_FF_VMX_MTF \| VMCPU_FF_VMX_PREEMPT_TIMER)
744	/** High priority ring-0 VM pre HM-mode execution mask, single stepping. */
745	#define VM_FF_HP_R0_PRE_HM_STEP_MASK (VM_FF_HP_R0_PRE_HM_MASK & ~( VM_FF_TM_VIRTUAL_SYNC \| VM_FF_PDM_QUEUES \
746	\| VM_FF_EMT_RENDEZVOUS \| VM_FF_REQUEST \
747	\| VM_FF_PDM_DMA) )
748	/** High priority ring-0 VMCPU pre HM-mode execution mask, single stepping. */
749	#define VMCPU_FF_HP_R0_PRE_HM_STEP_MASK (VMCPU_FF_HP_R0_PRE_HM_MASK & ~( VMCPU_FF_TO_R3 \| VMCPU_FF_TIMER \
750	\| VMCPU_FF_PDM_CRITSECT \| VMCPU_FF_REQUEST) )
751
752	/** All the VMX nested-guest flags. */
753	#define VMCPU_FF_VMX_ALL_MASK ( VMCPU_FF_VMX_PREEMPT_TIMER \| VMCPU_FF_VMX_MTF \| VMCPU_FF_VMX_APIC_WRITE \
754	\| VMCPU_FF_VMX_INT_WINDOW \| VMCPU_FF_VMX_NMI_WINDOW )
755
756	/** All the forced VM flags. */
757	#define VM_FF_ALL_MASK (UINT32_MAX)
758	/** All the forced VMCPU flags. */
759	#define VMCPU_FF_ALL_MASK ( UINT32_MAX \
760	\| VMCPU_FF_VMX_MTF \| VMCPU_FF_VMX_APIC_WRITE \| VMCPU_FF_VMX_INT_WINDOW \
761	\| VMCPU_FF_VMX_NMI_WINDOW )
762
763	/** All the forced VM flags except those related to raw-mode and hardware
764	* assisted execution. */
765	#define VM_FF_ALL_REM_MASK (~(VM_FF_HIGH_PRIORITY_PRE_RAW_MASK) \| VM_FF_PGM_NEED_HANDY_PAGES \| VM_FF_PGM_NO_MEMORY)
766	/** All the forced VMCPU flags except those related to raw-mode and hardware
767	* assisted execution. */
768	#define VMCPU_FF_ALL_REM_MASK (~(VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK \| VMCPU_FF_PDM_CRITSECT \| VMCPU_FF_TLB_FLUSH))
769
770	#ifndef VBOX_FOR_DTRACE_LIB
771	AssertCompile( ((VM_FF_HIGH_PRIORITY_POST_REPSTR_MASK \| VM_FF_YIELD_REPSTR_MASK)
772	& (VM_FF_HIGH_PRIORITY_PRE_RAW_MASK & ~VM_FF_ALL_REM_MASK)) == 0);
773	AssertCompile((VMCPU_FF_HIGH_PRIORITY_POST_REPSTR_MASK & (VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK & ~VMCPU_FF_ALL_REM_MASK)) == 0);
774	#endif
775
776	/** @} */
777
778	/** @def VM_FF_SET
779	* Sets a single force action flag.
780	*
781	* @param pVM The cross context VM structure.
782	* @param fFlag The flag to set.
783	*/
784	#define VM_FF_SET(pVM, fFlag) do { \
785	AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
786	AssertCompile((fFlag) == RT_BIT_32(fFlag##_BIT)); \
787	ASMAtomicOrU32(&(pVM)->fGlobalForcedActions, (fFlag)); \
788	} while (0)
789
790	/** @def VMCPU_FF_SET
791	* Sets a single force action flag for the given VCPU.
792	*
793	* @param pVCpu The cross context virtual CPU structure.
794	* @param fFlag The flag to set.
795	* @sa VMCPU_FF_SET_MASK
796	*/
797	#ifdef VMCPU_WITH_64_BIT_FFS
798	# define VMCPU_FF_SET(pVCpu, fFlag) do { \
799	AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
800	AssertCompile((fFlag) == RT_BIT_64(fFlag##_BIT)); \
801	ASMAtomicBitSet(&(pVCpu)->fLocalForcedActions, fFlag##_BIT); \
802	} while (0)
803	#else
804	# define VMCPU_FF_SET(pVCpu, fFlag) do { \
805	AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
806	AssertCompile((fFlag) == RT_BIT_32(fFlag##_BIT)); \
807	ASMAtomicOrU32(&(pVCpu)->fLocalForcedActions, (fFlag)); \
808	} while (0)
809	#endif
810
811	/** @def VMCPU_FF_SET_MASK
812	* Sets a two or more force action flag for the given VCPU.
813	*
814	* @param pVCpu The cross context virtual CPU structure.
815	* @param fFlags The flags to set.
816	* @sa VMCPU_FF_SET
817	*/
818	#ifdef VMCPU_WITH_64_BIT_FFS
819	# if ARCH_BITS > 32
820	# define VMCPU_FF_SET_MASK(pVCpu, fFlags) \
821	do { ASMAtomicOrU64(&pVCpu->fLocalForcedActions, (fFlags)); } while (0)
822	# else
823	# define VMCPU_FF_SET_MASK(pVCpu, fFlags) do { \
824	if (!((fFlags) >> 32)) ASMAtomicOrU32((uint32_t volatile *)&pVCpu->fLocalForcedActions, (uint32_t)(fFlags)); \
825	else ASMAtomicOrU64(&pVCpu->fLocalForcedActions, (fFlags)); \
826	} while (0)
827	# endif
828	#else
829	# define VMCPU_FF_SET_MASK(pVCpu, fFlags) \
830	do { ASMAtomicOrU32(&pVCpu->fLocalForcedActions, (fFlags)); } while (0)
831	#endif
832
833	/** @def VM_FF_CLEAR
834	* Clears a single force action flag.
835	*
836	* @param pVM The cross context VM structure.
837	* @param fFlag The flag to clear.
838	*/
839	#define VM_FF_CLEAR(pVM, fFlag) do { \
840	AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
841	AssertCompile((fFlag) == RT_BIT_32(fFlag##_BIT)); \
842	ASMAtomicAndU32(&(pVM)->fGlobalForcedActions, ~(fFlag)); \
843	} while (0)
844
845	/** @def VMCPU_FF_CLEAR
846	* Clears a single force action flag for the given VCPU.
847	*
848	* @param pVCpu The cross context virtual CPU structure.
849	* @param fFlag The flag to clear.
850	*/
851	#ifdef VMCPU_WITH_64_BIT_FFS
852	# define VMCPU_FF_CLEAR(pVCpu, fFlag) do { \
853	AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
854	AssertCompile((fFlag) == RT_BIT_64(fFlag##_BIT)); \
855	ASMAtomicBitClear(&(pVCpu)->fLocalForcedActions, fFlag##_BIT); \
856	} while (0)
857	#else
858	# define VMCPU_FF_CLEAR(pVCpu, fFlag) do { \
859	AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
860	AssertCompile((fFlag) == RT_BIT_32(fFlag##_BIT)); \
861	ASMAtomicAndU32(&(pVCpu)->fLocalForcedActions, ~(fFlag)); \
862	} while (0)
863	#endif
864
865	/** @def VMCPU_FF_CLEAR_MASK
866	* Clears two or more force action flags for the given VCPU.
867	*
868	* @param pVCpu The cross context virtual CPU structure.
869	* @param fFlags The flags to clear.
870	*/
871	#ifdef VMCPU_WITH_64_BIT_FFS
872	# if ARCH_BITS > 32
873	# define VMCPU_FF_CLEAR_MASK(pVCpu, fFlags) \
874	do { ASMAtomicAndU64(&(pVCpu)->fLocalForcedActions, ~(fFlags)); } while (0)
875	# else
876	# define VMCPU_FF_CLEAR_MASK(pVCpu, fFlags) do { \
877	if (!((fFlags) >> 32)) ASMAtomicAndU32((uint32_t volatile *)&(pVCpu)->fLocalForcedActions, ~(uint32_t)(fFlags)); \
878	else ASMAtomicAndU64(&(pVCpu)->fLocalForcedActions, ~(fFlags)); \
879	} while (0)
880	# endif
881	#else
882	# define VMCPU_FF_CLEAR_MASK(pVCpu, fFlags) \
883	do { ASMAtomicAndU32(&(pVCpu)->fLocalForcedActions, ~(fFlags)); } while (0)
884	#endif
885
886	/** @def VM_FF_IS_SET
887	* Checks if single a force action flag is set.
888	*
889	* @param pVM The cross context VM structure.
890	* @param fFlag The flag to check.
891	* @sa VM_FF_IS_ANY_SET
892	*/
893	#if !defined(VBOX_STRICT) \|\| !defined(RT_COMPILER_SUPPORTS_LAMBDA)
894	# define VM_FF_IS_SET(pVM, fFlag) RT_BOOL((pVM)->fGlobalForcedActions & (fFlag))
895	#else
896	# define VM_FF_IS_SET(pVM, fFlag) \
897	([](PVM a_pVM) -> bool \
898	{ \
899	AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
900	AssertCompile((fFlag) == RT_BIT_32(fFlag##_BIT)); \
901	return RT_BOOL(a_pVM->fGlobalForcedActions & (fFlag)); \
902	}(pVM))
903	#endif
904
905	/** @def VMCPU_FF_IS_SET
906	* Checks if a single force action flag is set for the given VCPU.
907	*
908	* @param pVCpu The cross context virtual CPU structure.
909	* @param fFlag The flag to check.
910	* @sa VMCPU_FF_IS_ANY_SET
911	*/
912	#if !defined(VBOX_STRICT) \|\| !defined(RT_COMPILER_SUPPORTS_LAMBDA)
913	# define VMCPU_FF_IS_SET(pVCpu, fFlag) RT_BOOL((pVCpu)->fLocalForcedActions & (fFlag))
914	#else
915	# define VMCPU_FF_IS_SET(pVCpu, fFlag) \
916	([](PCVMCPU a_pVCpu) -> bool \
917	{ \
918	AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
919	AssertCompile((fFlag) == RT_BIT_64(fFlag##_BIT)); \
920	return RT_BOOL(a_pVCpu->fLocalForcedActions & (fFlag)); \
921	}(pVCpu))
922	#endif
923
924	/** @def VM_FF_IS_ANY_SET
925	* Checks if one or more force action in the specified set is pending.
926	*
927	* @param pVM The cross context VM structure.
928	* @param fFlags The flags to check for.
929	* @sa VM_FF_IS_SET
930	*/
931	#define VM_FF_IS_ANY_SET(pVM, fFlags) RT_BOOL((pVM)->fGlobalForcedActions & (fFlags))
932
933	/** @def VMCPU_FF_IS_ANY_SET
934	* Checks if two or more force action flags in the specified set is set for the given VCPU.
935	*
936	* @param pVCpu The cross context virtual CPU structure.
937	* @param fFlags The flags to check for.
938	* @sa VMCPU_FF_IS_SET
939	*/
940	#define VMCPU_FF_IS_ANY_SET(pVCpu, fFlags) RT_BOOL((pVCpu)->fLocalForcedActions & (fFlags))
941
942	/** @def VM_FF_TEST_AND_CLEAR
943	* Checks if one (!) force action in the specified set is pending and clears it atomically
944	*
945	* @returns true if the bit was set.
946	* @returns false if the bit was clear.
947	* @param pVM The cross context VM structure.
948	* @param fFlag Flag constant to check and clear (_BIT is appended).
949	*/
950	#define VM_FF_TEST_AND_CLEAR(pVM, fFlag) (ASMAtomicBitTestAndClear(&(pVM)->fGlobalForcedActions, fFlag##_BIT))
951
952	/** @def VMCPU_FF_TEST_AND_CLEAR
953	* Checks if one (!) force action in the specified set is pending and clears it atomically
954	*
955	* @returns true if the bit was set.
956	* @returns false if the bit was clear.
957	* @param pVCpu The cross context virtual CPU structure.
958	* @param fFlag Flag constant to check and clear (_BIT is appended).
959	*/
960	#define VMCPU_FF_TEST_AND_CLEAR(pVCpu, fFlag) (ASMAtomicBitTestAndClear(&(pVCpu)->fLocalForcedActions, fFlag##_BIT))
961
962	/** @def VM_FF_IS_PENDING_EXCEPT
963	* Checks if one or more force action in the specified set is pending while one
964	* or more other ones are not.
965	*
966	* @param pVM The cross context VM structure.
967	* @param fFlags The flags to check for.
968	* @param fExcpt The flags that should not be set.
969	*/
970	#define VM_FF_IS_PENDING_EXCEPT(pVM, fFlags, fExcpt) \
971	( ((pVM)->fGlobalForcedActions & (fFlags)) && !((pVM)->fGlobalForcedActions & (fExcpt)) )
972
973	/** @def VM_IS_EMT
974	* Checks if the current thread is the emulation thread (EMT).
975	*
976	* @remark The ring-0 variation will need attention if we expand the ring-0
977	* code to let threads other than EMT mess around with the VM.
978	*/
979	#ifdef IN_RC
980	# define VM_IS_EMT(pVM) true
981	#else
982	# define VM_IS_EMT(pVM) (VMMGetCpu(pVM) != NULL)
983	#endif
984
985	/** @def VMCPU_IS_EMT
986	* Checks if the current thread is the emulation thread (EMT) for the specified
987	* virtual CPU.
988	*/
989	#ifdef IN_RC
990	# define VMCPU_IS_EMT(pVCpu) true
991	#else
992	# define VMCPU_IS_EMT(pVCpu) ((pVCpu) && ((pVCpu) == VMMGetCpu((pVCpu)->CTX_SUFF(pVM))))
993	#endif
994
995	/** @def VM_ASSERT_EMT
996	* Asserts that the current thread IS the emulation thread (EMT).
997	*/
998	#ifdef IN_RC
999	# define VM_ASSERT_EMT(pVM) Assert(VM_IS_EMT(pVM))
1000	#elif defined(IN_RING0)
1001	# define VM_ASSERT_EMT(pVM) Assert(VM_IS_EMT(pVM))
1002	#else
1003	# define VM_ASSERT_EMT(pVM) \
1004	AssertMsg(VM_IS_EMT(pVM), \
1005	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd\n", RTThreadNativeSelf(), VMR3GetVMCPUNativeThread(pVM)))
1006	#endif
1007
1008	/** @def VMCPU_ASSERT_EMT
1009	* Asserts that the current thread IS the emulation thread (EMT) of the
1010	* specified virtual CPU.
1011	*/
1012	#ifdef IN_RC
1013	# define VMCPU_ASSERT_EMT(pVCpu) Assert(VMCPU_IS_EMT(pVCpu))
1014	#elif defined(IN_RING0)
1015	# define VMCPU_ASSERT_EMT(pVCpu) AssertMsg(VMCPU_IS_EMT(pVCpu), \
1016	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd idCpu=%u\n", \
1017	RTThreadNativeSelf(), (pVCpu) ? (pVCpu)->hNativeThreadR0 : 0, \
1018	(pVCpu) ? (pVCpu)->idCpu : 0))
1019	#else
1020	# define VMCPU_ASSERT_EMT(pVCpu) AssertMsg(VMCPU_IS_EMT(pVCpu), \
1021	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd idCpu=%#x\n", \
1022	RTThreadNativeSelf(), (pVCpu)->hNativeThread, (pVCpu)->idCpu))
1023	#endif
1024
1025	/** @def VM_ASSERT_EMT_RETURN
1026	* Asserts that the current thread IS the emulation thread (EMT) and returns if it isn't.
1027	*/
1028	#ifdef IN_RC
1029	# define VM_ASSERT_EMT_RETURN(pVM, rc) AssertReturn(VM_IS_EMT(pVM), (rc))
1030	#elif defined(IN_RING0)
1031	# define VM_ASSERT_EMT_RETURN(pVM, rc) AssertReturn(VM_IS_EMT(pVM), (rc))
1032	#else
1033	# define VM_ASSERT_EMT_RETURN(pVM, rc) \
1034	AssertMsgReturn(VM_IS_EMT(pVM), \
1035	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd\n", RTThreadNativeSelf(), VMR3GetVMCPUNativeThread(pVM)), \
1036	(rc))
1037	#endif
1038
1039	/** @def VMCPU_ASSERT_EMT_RETURN
1040	* Asserts that the current thread IS the emulation thread (EMT) and returns if it isn't.
1041	*/
1042	#ifdef IN_RC
1043	# define VMCPU_ASSERT_EMT_RETURN(pVCpu, rc) AssertReturn(VMCPU_IS_EMT(pVCpu), (rc))
1044	#elif defined(IN_RING0)
1045	# define VMCPU_ASSERT_EMT_RETURN(pVCpu, rc) AssertReturn(VMCPU_IS_EMT(pVCpu), (rc))
1046	#else
1047	# define VMCPU_ASSERT_EMT_RETURN(pVCpu, rc) \
1048	AssertMsgReturn(VMCPU_IS_EMT(pVCpu), \
1049	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd idCpu=%#x\n", \
1050	RTThreadNativeSelf(), (pVCpu)->hNativeThread, (pVCpu)->idCpu), \
1051	(rc))
1052	#endif
1053
1054	/** @def VMCPU_ASSERT_EMT_OR_GURU
1055	* Asserts that the current thread IS the emulation thread (EMT) of the
1056	* specified virtual CPU.
1057	*/
1058	#if defined(IN_RC) \|\| defined(IN_RING0)
1059	# define VMCPU_ASSERT_EMT_OR_GURU(pVCpu) Assert( VMCPU_IS_EMT(pVCpu) \
1060	\|\| pVCpu->CTX_SUFF(pVM)->enmVMState == VMSTATE_GURU_MEDITATION \
1061	\|\| pVCpu->CTX_SUFF(pVM)->enmVMState == VMSTATE_GURU_MEDITATION_LS )
1062	#else
1063	# define VMCPU_ASSERT_EMT_OR_GURU(pVCpu) \
1064	AssertMsg( VMCPU_IS_EMT(pVCpu) \
1065	\|\| pVCpu->CTX_SUFF(pVM)->enmVMState == VMSTATE_GURU_MEDITATION \
1066	\|\| pVCpu->CTX_SUFF(pVM)->enmVMState == VMSTATE_GURU_MEDITATION_LS, \
1067	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd idCpu=%#x\n", \
1068	RTThreadNativeSelf(), (pVCpu)->hNativeThread, (pVCpu)->idCpu))
1069	#endif
1070
1071	/** @def VMCPU_ASSERT_EMT_OR_NOT_RUNNING
1072	* Asserts that the current thread IS the emulation thread (EMT) of the
1073	* specified virtual CPU or the VM is not running.
1074	*/
1075	#if defined(IN_RC) \|\| defined(IN_RING0)
1076	# define VMCPU_ASSERT_EMT_OR_NOT_RUNNING(pVCpu) \
1077	Assert( VMCPU_IS_EMT(pVCpu) \
1078	\|\| !VM_IS_RUNNING_FOR_ASSERTIONS_ONLY((pVCpu)->CTX_SUFF(pVM)) )
1079	#else
1080	# define VMCPU_ASSERT_EMT_OR_NOT_RUNNING(pVCpu) \
1081	AssertMsg( VMCPU_IS_EMT(pVCpu) \
1082	\|\| !VM_IS_RUNNING_FOR_ASSERTIONS_ONLY((pVCpu)->CTX_SUFF(pVM)), \
1083	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd idCpu=%#x\n", \
1084	RTThreadNativeSelf(), (pVCpu)->hNativeThread, (pVCpu)->idCpu))
1085	#endif
1086
1087	/** @def VMSTATE_IS_RUNNING
1088	* Checks if the given state indicates a running VM.
1089	*/
1090	#define VMSTATE_IS_RUNNING(a_enmVMState) \
1091	( (a_enmVMState) == VMSTATE_RUNNING \
1092	\|\| (a_enmVMState) == VMSTATE_RUNNING_LS )
1093
1094	/** @def VM_IS_RUNNING_FOR_ASSERTIONS_ONLY
1095	* Checks if the VM is running.
1096	* @note This is only for pure debug assertions. No AssertReturn or similar!
1097	* @sa VMSTATE_IS_RUNNING
1098	*/
1099	#define VM_IS_RUNNING_FOR_ASSERTIONS_ONLY(pVM) \
1100	( (pVM)->enmVMState == VMSTATE_RUNNING \
1101	\|\| (pVM)->enmVMState == VMSTATE_RUNNING_LS )
1102
1103
1104	/** @def VMSTATE_IS_POWERED_ON
1105	* Checks if the given state indicates the VM is powered on.
1106	*
1107	* @note Excludes all error states, so a powered on VM that hit a fatal error,
1108	* guru meditation, state load failure or similar will not be considered
1109	* powered on by this test.
1110	*/
1111	#define VMSTATE_IS_POWERED_ON(a_enmVMState) \
1112	( (a_enmVMState) >= VMSTATE_RESUMING && (a_enmVMState) < VMSTATE_POWERING_OFF )
1113
1114	/** @def VM_ASSERT_IS_NOT_RUNNING
1115	* Asserts that the VM is not running.
1116	*/
1117	#if defined(IN_RC) \|\| defined(IN_RING0)
1118	#define VM_ASSERT_IS_NOT_RUNNING(pVM) Assert(!VM_IS_RUNNING_FOR_ASSERTIONS_ONLY(pVM))
1119	#else
1120	#define VM_ASSERT_IS_NOT_RUNNING(pVM) AssertMsg(!VM_IS_RUNNING_FOR_ASSERTIONS_ONLY(pVM), \
1121	("VM is running. enmVMState=%d\n", (pVM)->enmVMState))
1122	#endif
1123
1124	/** @def VM_ASSERT_EMT0
1125	* Asserts that the current thread IS emulation thread \#0 (EMT0).
1126	*/
1127	#ifdef IN_RING3
1128	# define VM_ASSERT_EMT0(a_pVM) VMCPU_ASSERT_EMT((a_pVM)->apCpusR3[0])
1129	#else
1130	# define VM_ASSERT_EMT0(a_pVM) VMCPU_ASSERT_EMT(&(a_pVM)->aCpus[0])
1131	#endif
1132
1133	/** @def VM_ASSERT_EMT0_RETURN
1134	* Asserts that the current thread IS emulation thread \#0 (EMT0) and returns if
1135	* it isn't.
1136	*/
1137	#ifdef IN_RING3
1138	# define VM_ASSERT_EMT0_RETURN(pVM, rc) VMCPU_ASSERT_EMT_RETURN((pVM)->apCpusR3[0], (rc))
1139	#else
1140	# define VM_ASSERT_EMT0_RETURN(pVM, rc) VMCPU_ASSERT_EMT_RETURN(&(pVM)->aCpus[0], (rc))
1141	#endif
1142
1143
1144	/**
1145	* Asserts that the current thread is NOT the emulation thread.
1146	*/
1147	#define VM_ASSERT_OTHER_THREAD(pVM) \
1148	AssertMsg(!VM_IS_EMT(pVM), ("Not other thread!!\n"))
1149
1150
1151	/** @def VM_ASSERT_STATE
1152	* Asserts a certain VM state.
1153	*/
1154	#define VM_ASSERT_STATE(pVM, _enmState) \
1155	AssertMsg((pVM)->enmVMState == (_enmState), \
1156	("state %s, expected %s\n", VMGetStateName((pVM)->enmVMState), VMGetStateName(_enmState)))
1157
1158	/** @def VM_ASSERT_STATE_RETURN
1159	* Asserts a certain VM state and returns if it doesn't match.
1160	*/
1161	#define VM_ASSERT_STATE_RETURN(pVM, _enmState, rc) \
1162	AssertMsgReturn((pVM)->enmVMState == (_enmState), \
1163	("state %s, expected %s\n", VMGetStateName((pVM)->enmVMState), VMGetStateName(_enmState)), \
1164	(rc))
1165
1166	/** @def VM_IS_VALID_EXT
1167	* Check that a VM handle is valid for external access, i.e. not being destroy
1168	* or terminated and matching the target platform architecture (ring-3). */
1169	#ifdef VMTARGET_DEFAULT
1170	# define VM_IS_VALID_EXT(pVM) \
1171	( RT_VALID_ALIGNED_PTR(pVM, PAGE_SIZE) \
1172	&& ( (unsigned)(pVM)->enmVMState < (unsigned)VMSTATE_DESTROYING \
1173	\|\| ( (unsigned)(pVM)->enmVMState == (unsigned)VMSTATE_DESTROYING \
1174	&& VM_IS_EMT(pVM))) \
1175	&& (pVM)->enmTarget != VMTARGET_DEFAULT)
1176	#else
1177	# define VM_IS_VALID_EXT(pVM) \
1178	( RT_VALID_ALIGNED_PTR(pVM, PAGE_SIZE) \
1179	&& ( (unsigned)(pVM)->enmVMState < (unsigned)VMSTATE_DESTROYING \
1180	\|\| ( (unsigned)(pVM)->enmVMState == (unsigned)VMSTATE_DESTROYING \
1181	&& VM_IS_EMT(pVM))) )
1182	#endif
1183
1184	/** @def VM_ASSERT_VALID_EXT_RETURN
1185	* Asserts that a VM handle is valid for external access, i.e. not being destroy
1186	* or terminated.
1187	*/
1188	#define VM_ASSERT_VALID_EXT_RETURN(pVM, rc) \
1189	AssertMsgReturn(VM_IS_VALID_EXT(pVM), \
1190	("pVM=%p state %s enmTarget=%#x\n", (pVM), RT_VALID_ALIGNED_PTR(pVM, PAGE_SIZE) \
1191	? VMGetStateName(pVM->enmVMState) : "", (pVM)->enmTarget), \
1192	(rc))
1193
1194	/** @def VMCPU_IS_VALID_EXT
1195	* Checks that a VMCPU handle is valid for external access, i.e. not being
1196	* destroy or terminated and matching the target platform architecture (r3). */
1197	#ifdef VMTARGET_DEFAULT
1198	# define VMCPU_IS_VALID_EXT(a_pVCpu) \
1199	( RT_VALID_ALIGNED_PTR(a_pVCpu, 64) \
1200	&& RT_VALID_ALIGNED_PTR((a_pVCpu)->CTX_SUFF(pVM), PAGE_SIZE) \
1201	&& (unsigned)(a_pVCpu)->CTX_SUFF(pVM)->enmVMState < (unsigned)VMSTATE_DESTROYING \
1202	&& (pVM)->enmTarget != VMTARGET_DEFAULT)
1203	#else
1204	# define VMCPU_IS_VALID_EXT(a_pVCpu) \
1205	( RT_VALID_ALIGNED_PTR(a_pVCpu, 64) \
1206	&& RT_VALID_ALIGNED_PTR((a_pVCpu)->CTX_SUFF(pVM), PAGE_SIZE) \
1207	&& (unsigned)(a_pVCpu)->CTX_SUFF(pVM)->enmVMState < (unsigned)VMSTATE_DESTROYING)
1208	#endif
1209
1210	/** @def VMCPU_ASSERT_VALID_EXT_RETURN
1211	* Asserts that a VMCPU handle is valid for external access, i.e. not being
1212	* destroy or terminated and matching the target platform architecutre (r3).
1213	*/
1214	#define VMCPU_ASSERT_VALID_EXT_RETURN(pVCpu, rc) \
1215	AssertMsgReturn(VMCPU_IS_VALID_EXT(pVCpu), \
1216	("pVCpu=%p pVM=%p state %s enmTarget=%#x\n", (pVCpu), \
1217	RT_VALID_ALIGNED_PTR(pVCpu, 64) ? (pVCpu)->CTX_SUFF(pVM) : NULL, \
1218	RT_VALID_ALIGNED_PTR(pVCpu, 64) && RT_VALID_ALIGNED_PTR((pVCpu)->CTX_SUFF(pVM), PAGE_SIZE) \
1219	? VMGetStateName((pVCpu)->pVMR3->enmVMState) : "", (pVCpu)->enmTarget), \
1220	(rc))
1221
1222	#endif /* !VBOX_FOR_DTRACE_LIB */
1223
1224
1225	/**
1226	* Helper that HM and NEM uses for safely modifying VM::bMainExecutionEngine.
1227	*
1228	* ONLY HM and NEM MAY USE THIS!
1229	*
1230	* @param a_pVM The cross context VM structure.
1231	* @param a_bValue The new value.
1232	* @internal
1233	*/
1234	#define VM_SET_MAIN_EXECUTION_ENGINE(a_pVM, a_bValue) \
1235	do { \
1236	const_cast<uint8_t >(&(a_pVM)->bMainExecutionEngine) = (a_bValue); \
1237	ASMCompilerBarrier(); /* just to be on the safe side */ \
1238	} while (0)
1239
1240	/**
1241	* Checks whether iem-executes-all-mode is used.
1242	*
1243	* @retval true if IEM is used.
1244	* @retval false if not.
1245	*
1246	* @param a_pVM The cross context VM structure.
1247	* @sa VM_IS_HM_OR_NEM_ENABLED, VM_IS_HM_ENABLED, VM_IS_NEM_ENABLED.
1248	* @internal
1249	*/
1250	#define VM_IS_EXEC_ENGINE_IEM(a_pVM) ((a_pVM)->bMainExecutionEngine == VM_EXEC_ENGINE_IEM)
1251
1252	/**
1253	* Checks whether HM (VT-x/AMD-V) or NEM is being used by this VM.
1254	*
1255	* @retval true if either is used.
1256	* @retval false if software virtualization (raw-mode) is used.
1257	*
1258	* @param a_pVM The cross context VM structure.
1259	* @sa VM_IS_EXEC_ENGINE_IEM, VM_IS_HM_ENABLED, VM_IS_NEM_ENABLED.
1260	* @internal
1261	*/
1262	#define VM_IS_HM_OR_NEM_ENABLED(a_pVM) ((a_pVM)->bMainExecutionEngine != VM_EXEC_ENGINE_IEM)
1263
1264	/**
1265	* Checks whether HM is being used by this VM.
1266	*
1267	* @retval true if HM (VT-x/AMD-v) is used.
1268	* @retval false if not.
1269	*
1270	* @param a_pVM The cross context VM structure.
1271	* @sa VM_IS_NEM_ENABLED, VM_IS_EXEC_ENGINE_IEM, VM_IS_HM_OR_NEM_ENABLED.
1272	* @internal
1273	*/
1274	#define VM_IS_HM_ENABLED(a_pVM) ((a_pVM)->bMainExecutionEngine == VM_EXEC_ENGINE_HW_VIRT)
1275
1276	/**
1277	* Checks whether NEM is being used by this VM.
1278	*
1279	* @retval true if a native hypervisor API is used.
1280	* @retval false if not.
1281	*
1282	* @param a_pVM The cross context VM structure.
1283	* @sa VM_IS_HM_ENABLED, VM_IS_EXEC_ENGINE_IEM, VM_IS_HM_OR_NEM_ENABLED.
1284	* @internal
1285	*/
1286	#define VM_IS_NEM_ENABLED(a_pVM) ((a_pVM)->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API)
1287
1288
1289	/**
1290	* The cross context VM structure.
1291	*
1292	* It contains all the VM data which have to be available in all contexts.
1293	* Even if it contains all the data the idea is to use APIs not to modify all
1294	* the members all around the place. Therefore we make use of unions to hide
1295	* everything which isn't local to the current source module. This means we'll
1296	* have to pay a little bit of attention when adding new members to structures
1297	* in the unions and make sure to keep the padding sizes up to date.
1298	*
1299	* Run 'kmk run-struct-tests' (from src/VBox/VMM if you like) after updating!
1300	*/
1301	typedef struct VM
1302	{
1303	/** The state of the VM.
1304	* This field is read only to everyone except the VM and EM. */
1305	VMSTATE volatile enmVMState;
1306	/** Forced action flags.
1307	* See the VM_FF_* \#defines. Updated atomically.
1308	*/
1309	volatile uint32_t fGlobalForcedActions;
1310	/** Pointer to the array of page descriptors for the VM structure allocation. */
1311	R3PTRTYPE(PSUPPAGE) paVMPagesR3;
1312	/** Session handle. For use when calling SUPR0 APIs. */
1313	#ifdef IN_RING0
1314	PSUPDRVSESSION pSessionUnsafe;
1315	#else
1316	PSUPDRVSESSION pSession;
1317	#endif
1318	/** Pointer to the ring-3 VM structure. */
1319	PUVM pUVM;
1320	/** Ring-3 Host Context VM Pointer. */
1321	#ifdef IN_RING0
1322	R3PTRTYPE(struct VM *) pVMR3Unsafe;
1323	#else
1324	R3PTRTYPE(struct VM *) pVMR3;
1325	#endif
1326	/** Ring-0 Host Context VM pointer for making ring-0 calls. */
1327	R0PTRTYPE(struct VM *) pVMR0ForCall;
1328	/** Raw-mode Context VM Pointer. */
1329	uint32_t pVMRC;
1330	/** Padding for new raw-mode (long mode). */
1331	uint32_t pVMRCPadding;
1332
1333	/** The GVM VM handle. Only the GVM should modify this field. */
1334	#ifdef IN_RING0
1335	uint32_t hSelfUnsafe;
1336	#else
1337	uint32_t hSelf;
1338	#endif
1339	/** Number of virtual CPUs. */
1340	#ifdef IN_RING0
1341	uint32_t cCpusUnsafe;
1342	#else
1343	uint32_t cCpus;
1344	#endif
1345	/** The VM target platform architecture. */
1346	#ifdef IN_RING0
1347	VMTARGET enmTargetUnsafe;
1348	#else
1349	VMTARGET enmTarget;
1350	#endif
1351	/** CPU excution cap (1-100) */
1352	uint32_t uCpuExecutionCap;
1353
1354	/** Size of the VM structure. */
1355	uint32_t cbSelf;
1356	/** Size of the VMCPU structure. */
1357	uint32_t cbVCpu;
1358	/** Structure version number (TBD). */
1359	uint32_t uStructVersion;
1360
1361	/** @name Various items that are frequently accessed.
1362	* @{ */
1363	/** The main execution engine, VM_EXEC_ENGINE_XXX.
1364	* This is set early during vmR3InitRing3 by HM or NEM. */
1365	uint8_t const bMainExecutionEngine;
1366
1367	/** Hardware VM support is available and enabled.
1368	* Determined very early during init.
1369	* This is placed here for performance reasons.
1370	* @todo obsoleted by bMainExecutionEngine, eliminate. */
1371	bool fHMEnabled;
1372	/** @} */
1373
1374	/** Alignment padding. */
1375	uint8_t uPadding1[2];
1376
1377	/** @name Debugging
1378	* @{ */
1379	/** Ring-3 Host Context VM Pointer. */
1380	R3PTRTYPE(RTTRACEBUF) hTraceBufR3;
1381	/** Ring-0 Host Context VM Pointer. */
1382	R0PTRTYPE(RTTRACEBUF) hTraceBufR0;
1383	/** @} */
1384
1385	/** Max EMT hash lookup collisions (in GVMM). */
1386	uint8_t cMaxEmtHashCollisions;
1387
1388	/** Padding - the unions must be aligned on a 64 bytes boundary. */
1389	uint8_t abAlignment3[HC_ARCH_BITS == 64 ? 23 : 51];
1390
1391	/** CPUM part. */
1392	union
1393	{
1394	#if defined(VMM_INCLUDED_SRC_include_CPUMInternal_h) \|\| defined(VMM_INCLUDED_SRC_include_CPUMInternal_armv8_h)
1395	struct CPUM s;
1396	#endif
1397	#ifdef VBOX_INCLUDED_vmm_cpum_h
1398	/** Read only info exposed about the host and guest CPUs. */
1399	struct
1400	{
1401	/** Guest CPU feature information. */
1402	CPUMFEATURES GuestFeatures;
1403	} const ro;
1404	#endif
1405	/** @todo this is rather bloated because of static MSR range allocation.
1406	* Probably a good idea to move it to a separate R0 allocation... */
1407	uint8_t padding[8832 + 1288192 + 0x1d00]; / multiple of 64 */
1408	} cpum;
1409
1410	/** PGM part.
1411	* @note Aligned on 16384 boundrary for zero and mmio page storage. */
1412	union
1413	{
1414	#ifdef VMM_INCLUDED_SRC_include_PGMInternal_h
1415	struct PGM s;
1416	#endif
1417	uint8_t padding[129728]; /* multiple of 64 */
1418	} pgm;
1419
1420	/** VMM part. */
1421	union
1422	{
1423	#ifdef VMM_INCLUDED_SRC_include_VMMInternal_h
1424	struct VMM s;
1425	#endif
1426	uint8_t padding[1600]; /* multiple of 64 */
1427	} vmm;
1428
1429	/** HM part. */
1430	union
1431	{
1432	#ifdef VMM_INCLUDED_SRC_include_HMInternal_h
1433	struct HM s;
1434	#endif
1435	uint8_t padding[5504]; /* multiple of 64 */
1436	} hm;
1437
1438	/** TRPM part. */
1439	union
1440	{
1441	#ifdef VMM_INCLUDED_SRC_include_TRPMInternal_h
1442	struct TRPM s;
1443	#endif
1444	uint8_t padding[2048]; /* multiple of 64 */
1445	} trpm;
1446
1447	/** SELM part. */
1448	union
1449	{
1450	#ifdef VMM_INCLUDED_SRC_include_SELMInternal_h
1451	struct SELM s;
1452	#endif
1453	uint8_t padding[768]; /* multiple of 64 */
1454	} selm;
1455
1456	/** MM part. */
1457	union
1458	{
1459	#ifdef VMM_INCLUDED_SRC_include_MMInternal_h
1460	struct MM s;
1461	#endif
1462	uint8_t padding[192]; /* multiple of 64 */
1463	} mm;
1464
1465	/** PDM part. */
1466	union
1467	{
1468	#ifdef VMM_INCLUDED_SRC_include_PDMInternal_h
1469	struct PDM s;
1470	#endif
1471	uint8_t padding[22784]; /* multiple of 64 */
1472	} pdm;
1473
1474	/** IOM part. */
1475	union
1476	{
1477	#ifdef VMM_INCLUDED_SRC_include_IOMInternal_h
1478	struct IOM s;
1479	#endif
1480	uint8_t padding[1152]; /* multiple of 64 */
1481	} iom;
1482
1483	/** EM part. */
1484	union
1485	{
1486	#ifdef VMM_INCLUDED_SRC_include_EMInternal_h
1487	struct EM s;
1488	#endif
1489	uint8_t padding[256]; /* multiple of 64 */
1490	} em;
1491
1492	/** NEM part. */
1493	union
1494	{
1495	#ifdef VMM_INCLUDED_SRC_include_NEMInternal_h
1496	struct NEM s;
1497	#endif
1498	uint8_t padding[4608]; /* multiple of 64 */
1499	} nem;
1500
1501	/** TM part. */
1502	union
1503	{
1504	#ifdef VMM_INCLUDED_SRC_include_TMInternal_h
1505	struct TM s;
1506	#endif
1507	uint8_t padding[10112]; /* multiple of 64 */
1508	} tm;
1509
1510	/** DBGF part. */
1511	union
1512	{
1513	#ifdef VMM_INCLUDED_SRC_include_DBGFInternal_h
1514	struct DBGF s;
1515	#endif
1516	#ifdef VBOX_INCLUDED_vmm_dbgf_h
1517	/** Read only info exposed about interrupt breakpoints and selected events. */
1518	struct
1519	{
1520	/** Bitmap of enabled hardware interrupt breakpoints. */
1521	uint32_t bmHardIntBreakpoints[256 / 32];
1522	/** Bitmap of enabled software interrupt breakpoints. */
1523	uint32_t bmSoftIntBreakpoints[256 / 32];
1524	/** Bitmap of selected events.
1525	* This includes non-selectable events too for simplicity, we maintain the
1526	* state for some of these, as it may come in handy. */
1527	uint64_t bmSelectedEvents[(DBGFEVENT_END + 63) / 64];
1528	/** Enabled hardware interrupt breakpoints. */
1529	uint32_t cHardIntBreakpoints;
1530	/** Enabled software interrupt breakpoints. */
1531	uint32_t cSoftIntBreakpoints;
1532	/** The number of selected events. */
1533	uint32_t cSelectedEvents;
1534	/** The number of enabled hardware breakpoints. */
1535	uint8_t cEnabledHwBreakpoints;
1536	/** The number of enabled hardware I/O breakpoints. */
1537	uint8_t cEnabledHwIoBreakpoints;
1538	uint8_t au8Alignment1[2]; /*< Alignment padding. /
1539	/** The number of enabled software breakpoints. */
1540	uint32_t volatile cEnabledSwBreakpoints;
1541	} const ro;
1542	#endif
1543	uint8_t padding[2432]; /* multiple of 64 */
1544	} dbgf;
1545
1546	/** SSM part. */
1547	union
1548	{
1549	#ifdef VMM_INCLUDED_SRC_include_SSMInternal_h
1550	struct SSM s;
1551	#endif
1552	uint8_t padding[128]; /* multiple of 64 */
1553	} ssm;
1554
1555	union
1556	{
1557	#ifdef VMM_INCLUDED_SRC_include_GIMInternal_h
1558	struct GIM s;
1559	#endif
1560	uint8_t padding[448]; /* multiple of 64 */
1561	} gim;
1562
1563	/** Interrupt controller, target specific. */
1564	RT_GCC_EXTENSION
1565	union
1566	{
1567	#if defined(VBOX_VMM_TARGET_ARMV8) \|\| defined(VBOX_VMM_TARGET_AGNOSTIC)
1568	union
1569	{
1570	# ifdef VMM_INCLUDED_SRC_include_GICInternal_h
1571	struct GIC s;
1572	# endif
1573	uint8_t padding[128]; /* multiple of 8 */
1574	} gic;
1575	#endif
1576	#if defined(VBOX_VMM_TARGET_X86) \|\| defined(VBOX_VMM_TARGET_AGNOSTIC)
1577	union
1578	{
1579	# ifdef VMM_INCLUDED_SRC_include_APICInternal_h
1580	struct APIC s;
1581	# endif
1582	uint8_t padding[128]; /* multiple of 8 */
1583	} apic;
1584	#endif
1585	};
1586
1587	/* ---- begin small stuff ---- */
1588
1589	/** VM part. */
1590	union
1591	{
1592	#ifdef VMM_INCLUDED_SRC_include_VMInternal_h
1593	struct VMINT s;
1594	#endif
1595	uint8_t padding[32]; /* multiple of 8 */
1596	} vm;
1597
1598	/** CFGM part. */
1599	union
1600	{
1601	#ifdef VMM_INCLUDED_SRC_include_CFGMInternal_h
1602	struct CFGM s;
1603	#endif
1604	uint8_t padding[8]; /* multiple of 8 */
1605	} cfgm;
1606
1607	/** IEM part. */
1608	union
1609	{
1610	#ifdef VMM_INCLUDED_SRC_include_IEMInternal_h
1611	struct IEM s;
1612	#endif
1613	uint8_t padding[16]; /* multiple of 8 */
1614	} iem;
1615
1616	/** Statistics for ring-0 only components. */
1617	struct
1618	{
1619	/** GMMR0 stats. */
1620	struct
1621	{
1622	/** Chunk TLB hits. */
1623	uint64_t cChunkTlbHits;
1624	/** Chunk TLB misses. */
1625	uint64_t cChunkTlbMisses;
1626	} gmm;
1627	uint64_t au64Padding[6]; /* probably more comming here... */
1628	} R0Stats;
1629
1630	union
1631	{
1632	#ifdef VMM_INCLUDED_SRC_include_GCMInternal_h
1633	struct GCM s;
1634	#endif
1635	uint8_t padding[8]; /* multiple of 8 */
1636	} gcm;
1637
1638	/** Padding for aligning the structure size on a page boundrary. */
1639	uint8_t abAlignment2[0x3900 - sizeof(PVMCPUR3) * VMM_MAX_CPU_COUNT];
1640
1641	/* ---- end small stuff ---- */
1642
1643	/** Array of VMCPU ring-3 pointers. */
1644	PVMCPUR3 apCpusR3[VMM_MAX_CPU_COUNT];
1645
1646	/* This point is aligned on a 16384 boundrary (for arm64 purposes). */
1647	} VM;
1648	#ifndef VBOX_FOR_DTRACE_LIB
1649	//AssertCompileSizeAlignment(VM, 16384);
1650	#endif
1651
1652
1653	#ifdef IN_RC
1654	RT_C_DECLS_BEGIN
1655
1656	/** The VM structure.
1657	* This is imported from the VMMRCBuiltin module, i.e. it's a one of those magic
1658	* globals which we should avoid using.
1659	*/
1660	extern DECLIMPORT(VM) g_VM;
1661
1662	/** The VMCPU structure for virtual CPU \#0.
1663	* This is imported from the VMMRCBuiltin module, i.e. it's a one of those magic
1664	* globals which we should avoid using.
1665	*/
1666	extern DECLIMPORT(VMCPU) g_VCpu0;
1667
1668	RT_C_DECLS_END
1669	#endif
1670
1671	/** @} */
1672
1673	#endif /* !VBOX_INCLUDED_vmm_vm_h */
1674

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source: vbox/trunk/include/VBox/vmm/vm.h@ 107894

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