vm.h@ 36448

Last change on this file since 36448 was 36448, checked in by vboxsync, 14 years ago
PCI: refactoring, further IOMMU work
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1	/** @file
2	* VM - The Virtual Machine, data.
3	*/
4
5	/*
6	* Copyright (C) 2006-2010 Oracle Corporation
7	*
8	* This file is part of VirtualBox Open Source Edition (OSE), as
9	* available from http://www.virtualbox.org. This file is free software;
10	* you can redistribute it and/or modify it under the terms of the GNU
11	* General Public License (GPL) as published by the Free Software
12	* Foundation, in version 2 as it comes in the "COPYING" file of the
13	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15	*
16	* The contents of this file may alternatively be used under the terms
17	* of the Common Development and Distribution License Version 1.0
18	* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19	* VirtualBox OSE distribution, in which case the provisions of the
20	* CDDL are applicable instead of those of the GPL.
21	*
22	* You may elect to license modified versions of this file under the
23	* terms and conditions of either the GPL or the CDDL or both.
24	*/
25
26	#ifndef ___VBox_vmm_vm_h
27	#define ___VBox_vmm_vm_h
28
29	#include <VBox/types.h>
30	#include <VBox/vmm/cpum.h>
31	#include <VBox/vmm/stam.h>
32	#include <VBox/vmm/vmapi.h>
33	#include <VBox/vmm/vmm.h>
34	#include <VBox/sup.h>
35
36
37	/** @defgroup grp_vm The Virtual Machine
38	* @{
39	*/
40
41	/**
42	* The state of a Virtual CPU.
43	*
44	* The basic state indicated here is whether the CPU has been started or not. In
45	* addition, there are sub-states when started for assisting scheduling (GVMM
46	* mostly).
47	*
48	* The transision out of the STOPPED state is done by a vmR3PowerOn.
49	* The transision back to the STOPPED state is done by vmR3PowerOff.
50	*
51	* (Alternatively we could let vmR3PowerOn start CPU 0 only and let the SPIP
52	* handling switch on the other CPUs. Then vmR3Reset would stop all but CPU 0.)
53	*/
54	typedef enum VMCPUSTATE
55	{
56	/** The customary invalid zero. */
57	VMCPUSTATE_INVALID = 0,
58
59	/** Virtual CPU has not yet been started. */
60	VMCPUSTATE_STOPPED,
61
62	/** CPU started. */
63	VMCPUSTATE_STARTED,
64	/** Executing guest code and can be poked. */
65	VMCPUSTATE_STARTED_EXEC,
66	/** Executing guest code in the recompiler. */
67	VMCPUSTATE_STARTED_EXEC_REM,
68	/** Halted. */
69	VMCPUSTATE_STARTED_HALTED,
70
71	/** The end of valid virtual CPU states. */
72	VMCPUSTATE_END,
73
74	/** Ensure 32-bit type. */
75	VMCPUSTATE_32BIT_HACK = 0x7fffffff
76	} VMCPUSTATE;
77
78
79	/**
80	* Per virtual CPU data.
81	*/
82	typedef struct VMCPU
83	{
84	/** Per CPU forced action.
85	* See the VMCPU_FF_* \#defines. Updated atomically. */
86	uint32_t volatile fLocalForcedActions;
87	/** The CPU state. */
88	VMCPUSTATE volatile enmState;
89
90	/** Pointer to the ring-3 UVMCPU structure. */
91	PUVMCPU pUVCpu;
92	/** Ring-3 Host Context VM Pointer. */
93	PVMR3 pVMR3;
94	/** Ring-0 Host Context VM Pointer. */
95	PVMR0 pVMR0;
96	/** Alignment padding. */
97	RTR0PTR pvR0Padding;
98	/** Raw-mode Context VM Pointer. */
99	PVMRC pVMRC;
100	/** The CPU ID.
101	* This is the index into the VM::aCpu array. */
102	VMCPUID idCpu;
103	/** The native thread handle. */
104	RTNATIVETHREAD hNativeThread;
105	/** The native R0 thread handle. (different from the R3 handle!) */
106	RTNATIVETHREAD hNativeThreadR0;
107	/** Which host CPU ID is this EMT running on.
108	* Only valid when in RC or HWACCMR0 with scheduling disabled. */
109	RTCPUID volatile idHostCpu;
110	/** State data for use by ad hoc profiling. */
111	uint32_t uAdHoc;
112	/** Profiling samples for use by ad hoc profiling. */
113	STAMPROFILEADV aStatAdHoc[8];
114
115	/** Align the next bit on a 64-byte boundary and make sure it starts at the same
116	* offset in both 64-bit and 32-bit builds.
117	*
118	* @remarks The alignments of the members that are larger than 48 bytes should be
119	* 64-byte for cache line reasons. structs containing small amounts of
120	* data could be lumped together at the end with a < 64 byte padding
121	* following it (to grow into and align the struct size).
122	* */
123	uint8_t abAlignment1[HC_ARCH_BITS == 32 ? 16+64 : 56];
124
125	/** CPUM part. */
126	union
127	{
128	#ifdef ___CPUMInternal_h
129	struct CPUMCPU s;
130	#endif
131	uint8_t padding[3456]; /* multiple of 64 */
132	} cpum;
133
134	/** HWACCM part. */
135	union
136	{
137	#ifdef ___HWACCMInternal_h
138	struct HWACCMCPU s;
139	#endif
140	uint8_t padding[5312]; /* multiple of 64 */
141	} hwaccm;
142
143	/** EM part. */
144	union
145	{
146	#ifdef ___EMInternal_h
147	struct EMCPU s;
148	#endif
149	uint8_t padding[1472]; /* multiple of 64 */
150	} em;
151
152	/** TRPM part. */
153	union
154	{
155	#ifdef ___TRPMInternal_h
156	struct TRPMCPU s;
157	#endif
158	uint8_t padding[128]; /* multiple of 64 */
159	} trpm;
160
161	/** TM part. */
162	union
163	{
164	#ifdef ___TMInternal_h
165	struct TMCPU s;
166	#endif
167	uint8_t padding[384]; /* multiple of 64 */
168	} tm;
169
170	/** VMM part. */
171	union
172	{
173	#ifdef ___VMMInternal_h
174	struct VMMCPU s;
175	#endif
176	uint8_t padding[384]; /* multiple of 64 */
177	} vmm;
178
179	/** PDM part. */
180	union
181	{
182	#ifdef ___PDMInternal_h
183	struct PDMCPU s;
184	#endif
185	uint8_t padding[128]; /* multiple of 64 */
186	} pdm;
187
188	/** IOM part. */
189	union
190	{
191	#ifdef ___IOMInternal_h
192	struct IOMCPU s;
193	#endif
194	uint8_t padding[512]; /* multiple of 64 */
195	} iom;
196
197	/** DBGF part.
198	* @todo Combine this with other tiny structures. */
199	union
200	{
201	#ifdef ___DBGFInternal_h
202	struct DBGFCPU s;
203	#endif
204	uint8_t padding[64]; /* multiple of 64 */
205	} dbgf;
206
207	#if 0
208	/** Align the following members on page boundary. */
209	uint8_t abAlignment2[32];
210	#endif
211
212	/** PGM part. */
213	union
214	{
215	#ifdef ___PGMInternal_h
216	struct PGMCPU s;
217	#endif
218	uint8_t padding[4096]; /* multiple of 4096 */
219	} pgm;
220
221	} VMCPU;
222
223
224	/** @name Operations on VMCPU::enmState
225	* @{ */
226	/** Gets the VMCPU state. */
227	#define VMCPU_GET_STATE(pVCpu) ( (pVCpu)->enmState )
228	/** Sets the VMCPU state. */
229	#define VMCPU_SET_STATE(pVCpu, enmNewState) \
230	ASMAtomicWriteU32((uint32_t volatile *)&(pVCpu)->enmState, (enmNewState))
231	/** Cmpares and sets the VMCPU state. */
232	#define VMCPU_CMPXCHG_STATE(pVCpu, enmNewState, enmOldState) \
233	ASMAtomicCmpXchgU32((uint32_t volatile *)&(pVCpu)->enmState, (enmNewState), (enmOldState))
234	/** Checks the VMCPU state. */
235	#define VMCPU_ASSERT_STATE(pVCpu, enmExpectedState) \
236	do { \
237	VMCPUSTATE enmState = VMCPU_GET_STATE(pVCpu); \
238	AssertMsg(enmState == (enmExpectedState), \
239	("enmState=%d enmExpectedState=%d idCpu=%u\n", \
240	enmState, enmExpectedState, (pVCpu)->idCpu)); \
241	} while (0)
242	/** Tests if the state means that the CPU is started. */
243	#define VMCPUSTATE_IS_STARTED(enmState) ( (enmState) > VMCPUSTATE_STOPPED )
244	/** Tests if the state means that the CPU is stopped. */
245	#define VMCPUSTATE_IS_STOPPED(enmState) ( (enmState) == VMCPUSTATE_STOPPED )
246	/** @} */
247
248
249	/** The name of the Guest Context VMM Core module. */
250	#define VMMGC_MAIN_MODULE_NAME "VMMGC.gc"
251	/** The name of the Ring 0 Context VMM Core module. */
252	#define VMMR0_MAIN_MODULE_NAME "VMMR0.r0"
253
254	/** VM Forced Action Flags.
255	*
256	* Use the VM_FF_SET() and VM_FF_CLEAR() macros to change the force
257	* action mask of a VM.
258	*
259	* @{
260	*/
261	/** The virtual sync clock has been stopped, go to TM until it has been
262	* restarted... */
263	#define VM_FF_TM_VIRTUAL_SYNC RT_BIT_32(2)
264	/** PDM Queues are pending. */
265	#define VM_FF_PDM_QUEUES RT_BIT_32(VM_FF_PDM_QUEUES_BIT)
266	/** The bit number for VM_FF_PDM_QUEUES. */
267	#define VM_FF_PDM_QUEUES_BIT 3
268	/** PDM DMA transfers are pending. */
269	#define VM_FF_PDM_DMA RT_BIT_32(VM_FF_PDM_DMA_BIT)
270	/** The bit number for VM_FF_PDM_DMA. */
271	#define VM_FF_PDM_DMA_BIT 4
272	/** This action forces the VM to call DBGF so DBGF can service debugger
273	* requests in the emulation thread.
274	* This action flag stays asserted till DBGF clears it.*/
275	#define VM_FF_DBGF RT_BIT_32(VM_FF_DBGF_BIT)
276	/** The bit number for VM_FF_DBGF. */
277	#define VM_FF_DBGF_BIT 8
278	/** This action forces the VM to service pending requests from other
279	* thread or requests which must be executed in another context. */
280	#define VM_FF_REQUEST RT_BIT_32(9)
281	/** Check for VM state changes and take appropriate action. */
282	#define VM_FF_CHECK_VM_STATE RT_BIT_32(VM_FF_CHECK_VM_STATE_BIT)
283	/** The bit number for VM_FF_CHECK_VM_STATE. */
284	#define VM_FF_CHECK_VM_STATE_BIT 10
285	/** Reset the VM. (postponed) */
286	#define VM_FF_RESET RT_BIT_32(VM_FF_RESET_BIT)
287	/** The bit number for VM_FF_RESET. */
288	#define VM_FF_RESET_BIT 11
289	/** EMT rendezvous in VMM. */
290	#define VM_FF_EMT_RENDEZVOUS RT_BIT_32(VM_FF_EMT_RENDEZVOUS_BIT)
291	/** The bit number for VM_FF_EMT_RENDEZVOUS. */
292	#define VM_FF_EMT_RENDEZVOUS_BIT 12
293
294	/** PGM needs to allocate handy pages. */
295	#define VM_FF_PGM_NEED_HANDY_PAGES RT_BIT_32(18)
296	/** PGM is out of memory.
297	* Abandon all loops and code paths which can be resumed and get up to the EM
298	* loops. */
299	#define VM_FF_PGM_NO_MEMORY RT_BIT_32(19)
300	/** PGM is about to perform a lightweight pool flush
301	* Guest SMP: all EMT threads should return to ring 3
302	*/
303	#define VM_FF_PGM_POOL_FLUSH_PENDING RT_BIT_32(20)
304	/** REM needs to be informed about handler changes. */
305	#define VM_FF_REM_HANDLER_NOTIFY RT_BIT_32(VM_FF_REM_HANDLER_NOTIFY_BIT)
306	/** The bit number for VM_FF_REM_HANDLER_NOTIFY. */
307	#define VM_FF_REM_HANDLER_NOTIFY_BIT 29
308	/** Suspend the VM - debug only. */
309	#define VM_FF_DEBUG_SUSPEND RT_BIT_32(31)
310
311
312	/** This action forces the VM to check any pending interrups on the APIC. */
313	#define VMCPU_FF_INTERRUPT_APIC RT_BIT_32(0)
314	/** This action forces the VM to check any pending interrups on the PIC. */
315	#define VMCPU_FF_INTERRUPT_PIC RT_BIT_32(1)
316	/** This action forces the VM to schedule and run pending timer (TM).
317	* @remarks Don't move - PATM compatibility. */
318	#define VMCPU_FF_TIMER RT_BIT_32(2)
319	/** This action forces the VM to check any pending NMIs. */
320	#define VMCPU_FF_INTERRUPT_NMI_BIT 3
321	#define VMCPU_FF_INTERRUPT_NMI RT_BIT_32(VMCPU_FF_INTERRUPT_NMI_BIT)
322	/** This action forces the VM to check any pending SMIs. */
323	#define VMCPU_FF_INTERRUPT_SMI_BIT 4
324	#define VMCPU_FF_INTERRUPT_SMI RT_BIT_32(VMCPU_FF_INTERRUPT_SMI_BIT)
325	/** PDM critical section unlocking is pending, process promptly upon return to R3. */
326	#define VMCPU_FF_PDM_CRITSECT RT_BIT_32(5)
327	/** This action forces the VM to service pending requests from other
328	* thread or requests which must be executed in another context. */
329	#define VMCPU_FF_REQUEST RT_BIT_32(9)
330	/** This action forces the VM to resync the page tables before going
331	* back to execute guest code. (GLOBAL FLUSH) */
332	#define VMCPU_FF_PGM_SYNC_CR3 RT_BIT_32(16)
333	/** Same as VM_FF_PGM_SYNC_CR3 except that global pages can be skipped.
334	* (NON-GLOBAL FLUSH) */
335	#define VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL RT_BIT_32(17)
336	/** Check for pending TLB shootdown actions.
337	* Consumer: HWACCM
338	* @todo rename to VMCPU_FF_HWACCM_TLB_SHOOTDOWN */
339	#define VMCPU_FF_TLB_SHOOTDOWN RT_BIT_32(18)
340	/** Check for pending TLB flush action.
341	* Consumer: HWACCM
342	* @todo rename to VMCPU_FF_HWACCM_TLB_FLUSH */
343	#define VMCPU_FF_TLB_FLUSH RT_BIT_32(VMCPU_FF_TLB_FLUSH_BIT)
344	/** The bit number for VMCPU_FF_TLB_FLUSH. */
345	#define VMCPU_FF_TLB_FLUSH_BIT 19
346	/** Check the interrupt and trap gates */
347	#define VMCPU_FF_TRPM_SYNC_IDT RT_BIT_32(20)
348	/** Check Guest's TSS ring 0 stack */
349	#define VMCPU_FF_SELM_SYNC_TSS RT_BIT_32(21)
350	/** Check Guest's GDT table */
351	#define VMCPU_FF_SELM_SYNC_GDT RT_BIT_32(22)
352	/** Check Guest's LDT table */
353	#define VMCPU_FF_SELM_SYNC_LDT RT_BIT_32(23)
354	/** Inhibit interrupts pending. See EMGetInhibitInterruptsPC(). */
355	#define VMCPU_FF_INHIBIT_INTERRUPTS RT_BIT_32(24)
356	/** CSAM needs to scan the page that's being executed */
357	#define VMCPU_FF_CSAM_SCAN_PAGE RT_BIT_32(26)
358	/** CSAM needs to do some homework. */
359	#define VMCPU_FF_CSAM_PENDING_ACTION RT_BIT_32(27)
360	/** Force return to Ring-3. */
361	#define VMCPU_FF_TO_R3 RT_BIT_32(28)
362
363	/** Externally VM forced actions. Used to quit the idle/wait loop. */
364	#define VM_FF_EXTERNAL_SUSPENDED_MASK (VM_FF_CHECK_VM_STATE \| VM_FF_DBGF \| VM_FF_REQUEST \| VM_FF_EMT_RENDEZVOUS)
365	/** Externally VMCPU forced actions. Used to quit the idle/wait loop. */
366	#define VMCPU_FF_EXTERNAL_SUSPENDED_MASK (VMCPU_FF_REQUEST)
367
368	/** Externally forced VM actions. Used to quit the idle/wait loop. */
369	#define VM_FF_EXTERNAL_HALTED_MASK ( VM_FF_CHECK_VM_STATE \| VM_FF_DBGF \| VM_FF_REQUEST \
370	\| VM_FF_PDM_QUEUES \| VM_FF_PDM_DMA \| VM_FF_EMT_RENDEZVOUS)
371	/** Externally forced VMCPU actions. Used to quit the idle/wait loop. */
372	#define VMCPU_FF_EXTERNAL_HALTED_MASK (VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC \| VMCPU_FF_REQUEST \| VMCPU_FF_TIMER)
373
374	/** High priority VM pre-execution actions. */
375	#define VM_FF_HIGH_PRIORITY_PRE_MASK ( VM_FF_CHECK_VM_STATE \| VM_FF_DBGF \| VM_FF_TM_VIRTUAL_SYNC \
376	\| VM_FF_DEBUG_SUSPEND \| VM_FF_PGM_NEED_HANDY_PAGES \| VM_FF_PGM_NO_MEMORY \| VM_FF_EMT_RENDEZVOUS)
377	/** High priority VMCPU pre-execution actions. */
378	#define VMCPU_FF_HIGH_PRIORITY_PRE_MASK ( VMCPU_FF_TIMER \| VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC \| VMCPU_FF_PGM_SYNC_CR3 \
379	\| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL \| VMCPU_FF_SELM_SYNC_TSS \| VMCPU_FF_TRPM_SYNC_IDT \
380	\| VMCPU_FF_SELM_SYNC_GDT \| VMCPU_FF_SELM_SYNC_LDT \| VMCPU_FF_INHIBIT_INTERRUPTS)
381
382	/** High priority VM pre raw-mode execution mask. */
383	#define VM_FF_HIGH_PRIORITY_PRE_RAW_MASK (VM_FF_PGM_NEED_HANDY_PAGES \| VM_FF_PGM_NO_MEMORY)
384	/** High priority VMCPU pre raw-mode execution mask. */
385	#define VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK ( VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL \| VMCPU_FF_SELM_SYNC_TSS \| VMCPU_FF_TRPM_SYNC_IDT \
386	\| VMCPU_FF_SELM_SYNC_GDT \| VMCPU_FF_SELM_SYNC_LDT \| VMCPU_FF_INHIBIT_INTERRUPTS)
387
388	/** High priority post-execution actions. */
389	#define VM_FF_HIGH_PRIORITY_POST_MASK (VM_FF_PGM_NO_MEMORY)
390	/** High priority post-execution actions. */
391	#define VMCPU_FF_HIGH_PRIORITY_POST_MASK (VMCPU_FF_PDM_CRITSECT\|VMCPU_FF_CSAM_PENDING_ACTION)
392
393	/** Normal priority VM post-execution actions. */
394	#define VM_FF_NORMAL_PRIORITY_POST_MASK ( VM_FF_CHECK_VM_STATE \| VM_FF_DBGF \| VM_FF_RESET \
395	\| VM_FF_PGM_NO_MEMORY \| VM_FF_EMT_RENDEZVOUS)
396	/** Normal priority VMCPU post-execution actions. */
397	#define VMCPU_FF_NORMAL_PRIORITY_POST_MASK (VMCPU_FF_CSAM_SCAN_PAGE)
398
399	/** Normal priority VM actions. */
400	#define VM_FF_NORMAL_PRIORITY_MASK (VM_FF_REQUEST \| VM_FF_PDM_QUEUES \| VM_FF_PDM_DMA \| VM_FF_REM_HANDLER_NOTIFY \| VM_FF_EMT_RENDEZVOUS)
401	/** Normal priority VMCPU actions. */
402	#define VMCPU_FF_NORMAL_PRIORITY_MASK (VMCPU_FF_REQUEST)
403
404	/** Flags to clear before resuming guest execution. */
405	#define VMCPU_FF_RESUME_GUEST_MASK (VMCPU_FF_TO_R3)
406
407	/** VM Flags that cause the HWACCM loops to go back to ring-3. */
408	#define VM_FF_HWACCM_TO_R3_MASK (VM_FF_TM_VIRTUAL_SYNC \| VM_FF_PGM_NEED_HANDY_PAGES \| VM_FF_PGM_NO_MEMORY \| VM_FF_PDM_QUEUES \| VM_FF_EMT_RENDEZVOUS)
409	/** VMCPU Flags that cause the HWACCM loops to go back to ring-3. */
410	#define VMCPU_FF_HWACCM_TO_R3_MASK (VMCPU_FF_TO_R3 \| VMCPU_FF_TIMER)
411
412	/** All the forced VM flags. */
413	#define VM_FF_ALL_MASK (~0U)
414	/** All the forced VMCPU flags. */
415	#define VMCPU_FF_ALL_MASK (~0U)
416
417	/** All the forced VM flags except those related to raw-mode and hardware
418	* assisted execution. */
419	#define VM_FF_ALL_REM_MASK (~(VM_FF_HIGH_PRIORITY_PRE_RAW_MASK) \| VM_FF_PGM_NO_MEMORY)
420	/** All the forced VMCPU flags except those related to raw-mode and hardware
421	* assisted execution. */
422	#define VMCPU_FF_ALL_REM_MASK (~(VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK \| VMCPU_FF_CSAM_PENDING_ACTION \| VMCPU_FF_PDM_CRITSECT \| VMCPU_FF_TLB_FLUSH \| VMCPU_FF_TLB_SHOOTDOWN))
423
424	/** @} */
425
426	/** @def VM_FF_SET
427	* Sets a force action flag.
428	*
429	* @param pVM VM Handle.
430	* @param fFlag The flag to set.
431	*/
432	#if 1
433	# define VM_FF_SET(pVM, fFlag) ASMAtomicOrU32(&(pVM)->fGlobalForcedActions, (fFlag))
434	#else
435	# define VM_FF_SET(pVM, fFlag) \
436	do { ASMAtomicOrU32(&(pVM)->fGlobalForcedActions, (fFlag)); \
437	RTLogPrintf("VM_FF_SET : %08x %s - %s(%d) %s\n", (pVM)->fGlobalForcedActions, #fFlag, __FILE__, __LINE__, __FUNCTION__); \
438	} while (0)
439	#endif
440
441	/** @def VMCPU_FF_SET
442	* Sets a force action flag for the given VCPU.
443	*
444	* @param pVCpu VMCPU Handle.
445	* @param fFlag The flag to set.
446	*/
447	#define VMCPU_FF_SET(pVCpu, fFlag) ASMAtomicOrU32(&(pVCpu)->fLocalForcedActions, (fFlag))
448
449	/** @def VM_FF_CLEAR
450	* Clears a force action flag.
451	*
452	* @param pVM VM Handle.
453	* @param fFlag The flag to clear.
454	*/
455	#if 1
456	# define VM_FF_CLEAR(pVM, fFlag) ASMAtomicAndU32(&(pVM)->fGlobalForcedActions, ~(fFlag))
457	#else
458	# define VM_FF_CLEAR(pVM, fFlag) \
459	do { ASMAtomicAndU32(&(pVM)->fGlobalForcedActions, ~(fFlag)); \
460	RTLogPrintf("VM_FF_CLEAR: %08x %s - %s(%d) %s\n", (pVM)->fGlobalForcedActions, #fFlag, __FILE__, __LINE__, __FUNCTION__); \
461	} while (0)
462	#endif
463
464	/** @def VMCPU_FF_CLEAR
465	* Clears a force action flag for the given VCPU.
466	*
467	* @param pVCpu VMCPU Handle.
468	* @param fFlag The flag to clear.
469	*/
470	#define VMCPU_FF_CLEAR(pVCpu, fFlag) ASMAtomicAndU32(&(pVCpu)->fLocalForcedActions, ~(fFlag))
471
472	/** @def VM_FF_ISSET
473	* Checks if a force action flag is set.
474	*
475	* @param pVM VM Handle.
476	* @param fFlag The flag to check.
477	*/
478	#define VM_FF_ISSET(pVM, fFlag) (((pVM)->fGlobalForcedActions & (fFlag)) == (fFlag))
479
480	/** @def VMCPU_FF_ISSET
481	* Checks if a force action flag is set for the given VCPU.
482	*
483	* @param pVCpu VMCPU Handle.
484	* @param fFlag The flag to check.
485	*/
486	#define VMCPU_FF_ISSET(pVCpu, fFlag) (((pVCpu)->fLocalForcedActions & (fFlag)) == (fFlag))
487
488	/** @def VM_FF_ISPENDING
489	* Checks if one or more force action in the specified set is pending.
490	*
491	* @param pVM VM Handle.
492	* @param fFlags The flags to check for.
493	*/
494	#define VM_FF_ISPENDING(pVM, fFlags) ((pVM)->fGlobalForcedActions & (fFlags))
495
496	/** @def VM_FF_TESTANDCLEAR
497	* Checks if one (!) force action in the specified set is pending and clears it atomically
498	*
499	* @returns true if the bit was set.
500	* @returns false if the bit was clear.
501	* @param pVM VM Handle.
502	* @param iBit Bit position to check and clear
503	*/
504	#define VM_FF_TESTANDCLEAR(pVM, iBit) (ASMAtomicBitTestAndClear(&(pVM)->fGlobalForcedActions, iBit##_BIT))
505
506	/** @def VMCPU_FF_TESTANDCLEAR
507	* Checks if one (!) force action in the specified set is pending and clears it atomically
508	*
509	* @returns true if the bit was set.
510	* @returns false if the bit was clear.
511	* @param pVCpu VMCPU Handle.
512	* @param iBit Bit position to check and clear
513	*/
514	#define VMCPU_FF_TESTANDCLEAR(pVCpu, iBit) (ASMAtomicBitTestAndClear(&(pVCpu)->fLocalForcedActions, iBit##_BIT))
515
516	/** @def VMCPU_FF_ISPENDING
517	* Checks if one or more force action in the specified set is pending for the given VCPU.
518	*
519	* @param pVCpu VMCPU Handle.
520	* @param fFlags The flags to check for.
521	*/
522	#define VMCPU_FF_ISPENDING(pVCpu, fFlags) ((pVCpu)->fLocalForcedActions & (fFlags))
523
524	/** @def VM_FF_ISPENDING
525	* Checks if one or more force action in the specified set is pending while one
526	* or more other ones are not.
527	*
528	* @param pVM VM Handle.
529	* @param fFlags The flags to check for.
530	* @param fExcpt The flags that should not be set.
531	*/
532	#define VM_FF_IS_PENDING_EXCEPT(pVM, fFlags, fExcpt) ( ((pVM)->fGlobalForcedActions & (fFlags)) && !((pVM)->fGlobalForcedActions & (fExcpt)) )
533
534	/** @def VMCPU_FF_IS_PENDING_EXCEPT
535	* Checks if one or more force action in the specified set is pending for the given
536	* VCPU while one or more other ones are not.
537	*
538	* @param pVCpu VMCPU Handle.
539	* @param fFlags The flags to check for.
540	* @param fExcpt The flags that should not be set.
541	*/
542	#define VMCPU_FF_IS_PENDING_EXCEPT(pVCpu, fFlags, fExcpt) ( ((pVCpu)->fLocalForcedActions & (fFlags)) && !((pVCpu)->fLocalForcedActions & (fExcpt)) )
543
544	/** @def VM_IS_EMT
545	* Checks if the current thread is the emulation thread (EMT).
546	*
547	* @remark The ring-0 variation will need attention if we expand the ring-0
548	* code to let threads other than EMT mess around with the VM.
549	*/
550	#ifdef IN_RC
551	# define VM_IS_EMT(pVM) true
552	#else
553	# define VM_IS_EMT(pVM) (VMMGetCpu(pVM) != NULL)
554	#endif
555
556	/** @def VMCPU_IS_EMT
557	* Checks if the current thread is the emulation thread (EMT) for the specified
558	* virtual CPU.
559	*/
560	#ifdef IN_RC
561	# define VMCPU_IS_EMT(pVCpu) true
562	#else
563	# define VMCPU_IS_EMT(pVCpu) ((pVCpu) && ((pVCpu) == VMMGetCpu((pVCpu)->CTX_SUFF(pVM))))
564	#endif
565
566	/** @def VM_ASSERT_EMT
567	* Asserts that the current thread IS the emulation thread (EMT).
568	*/
569	#ifdef IN_RC
570	# define VM_ASSERT_EMT(pVM) Assert(VM_IS_EMT(pVM))
571	#elif defined(IN_RING0)
572	# define VM_ASSERT_EMT(pVM) Assert(VM_IS_EMT(pVM))
573	#else
574	# define VM_ASSERT_EMT(pVM) \
575	AssertMsg(VM_IS_EMT(pVM), \
576	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd\n", RTThreadNativeSelf(), VMR3GetVMCPUNativeThread(pVM)))
577	#endif
578
579	/** @def VMCPU_ASSERT_EMT
580	* Asserts that the current thread IS the emulation thread (EMT) of the
581	* specified virtual CPU.
582	*/
583	#ifdef IN_RC
584	# define VMCPU_ASSERT_EMT(pVCpu) Assert(VMCPU_IS_EMT(pVCpu))
585	#elif defined(IN_RING0)
586	# define VMCPU_ASSERT_EMT(pVCpu) Assert(VMCPU_IS_EMT(pVCpu))
587	#else
588	# define VMCPU_ASSERT_EMT(pVCpu) \
589	AssertMsg(VMCPU_IS_EMT(pVCpu), \
590	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd idCpu=%#x\n", \
591	RTThreadNativeSelf(), (pVCpu)->hNativeThread, (pVCpu)->idCpu))
592	#endif
593
594	/** @def VM_ASSERT_EMT_RETURN
595	* Asserts that the current thread IS the emulation thread (EMT) and returns if it isn't.
596	*/
597	#ifdef IN_RC
598	# define VM_ASSERT_EMT_RETURN(pVM, rc) AssertReturn(VM_IS_EMT(pVM), (rc))
599	#elif defined(IN_RING0)
600	# define VM_ASSERT_EMT_RETURN(pVM, rc) AssertReturn(VM_IS_EMT(pVM), (rc))
601	#else
602	# define VM_ASSERT_EMT_RETURN(pVM, rc) \
603	AssertMsgReturn(VM_IS_EMT(pVM), \
604	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd\n", RTThreadNativeSelf(), VMR3GetVMCPUNativeThread(pVM)), \
605	(rc))
606	#endif
607
608	/** @def VMCPU_ASSERT_EMT_RETURN
609	* Asserts that the current thread IS the emulation thread (EMT) and returns if it isn't.
610	*/
611	#ifdef IN_RC
612	# define VMCPU_ASSERT_EMT_RETURN(pVCpu, rc) AssertReturn(VMCPU_IS_EMT(pVCpu), (rc))
613	#elif defined(IN_RING0)
614	# define VMCPU_ASSERT_EMT_RETURN(pVCpu, rc) AssertReturn(VMCPU_IS_EMT(pVCpu), (rc))
615	#else
616	# define VMCPU_ASSERT_EMT_RETURN(pVCpu, rc) \
617	AssertMsg(VMCPU_IS_EMT(pVCpu), \
618	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd idCpu=%#x\n", \
619	RTThreadNativeSelf(), (pVCpu)->hNativeThread, (pVCpu)->idCpu), \
620	(rc))
621	#endif
622
623	/** @def VM_ASSERT_EMT0
624	* Asserts that the current thread IS emulation thread \#0 (EMT0).
625	*/
626	#define VM_ASSERT_EMT0(pVM) VMCPU_ASSERT_EMT(&(pVM)->aCpus[0])
627
628	/** @def VM_ASSERT_EMT0_RETURN
629	* Asserts that the current thread IS emulation thread \#0 (EMT0) and returns if
630	* it isn't.
631	*/
632	#define VM_ASSERT_EMT0_RETURN(pVM, rc) VMCPU_ASSERT_EMT_RETURN(&(pVM)->aCpus[0], (rc))
633
634
635	/**
636	* Asserts that the current thread is NOT the emulation thread.
637	*/
638	#define VM_ASSERT_OTHER_THREAD(pVM) \
639	AssertMsg(!VM_IS_EMT(pVM), ("Not other thread!!\n"))
640
641
642	/** @def VM_ASSERT_STATE_RETURN
643	* Asserts a certain VM state.
644	*/
645	#define VM_ASSERT_STATE(pVM, _enmState) \
646	AssertMsg((pVM)->enmVMState == (_enmState), \
647	("state %s, expected %s\n", VMGetStateName((pVM)->enmVMState), VMGetStateName(_enmState)))
648
649	/** @def VM_ASSERT_STATE_RETURN
650	* Asserts a certain VM state and returns if it doesn't match.
651	*/
652	#define VM_ASSERT_STATE_RETURN(pVM, _enmState, rc) \
653	AssertMsgReturn((pVM)->enmVMState == (_enmState), \
654	("state %s, expected %s\n", VMGetStateName((pVM)->enmVMState), VMGetStateName(_enmState)), \
655	(rc))
656
657	/** @def VM_ASSERT_VALID_EXT_RETURN
658	* Asserts a the VM handle is valid for external access, i.e. not being
659	* destroy or terminated.
660	*/
661	#define VM_ASSERT_VALID_EXT_RETURN(pVM, rc) \
662	AssertMsgReturn( RT_VALID_ALIGNED_PTR(pVM, PAGE_SIZE) \
663	&& ( (unsigned)(pVM)->enmVMState < (unsigned)VMSTATE_DESTROYING \
664	\|\| ( (unsigned)(pVM)->enmVMState == (unsigned)VMSTATE_DESTROYING \
665	&& VM_IS_EMT(pVM))), \
666	("pVM=%p state %s\n", (pVM), RT_VALID_ALIGNED_PTR(pVM, PAGE_SIZE) \
667	? VMGetStateName(pVM->enmVMState) : ""), \
668	(rc))
669
670	/** @def VMCPU_ASSERT_VALID_EXT_RETURN
671	* Asserts a the VMCPU handle is valid for external access, i.e. not being
672	* destroy or terminated.
673	*/
674	#define VMCPU_ASSERT_VALID_EXT_RETURN(pVCpu, rc) \
675	AssertMsgReturn( RT_VALID_ALIGNED_PTR(pVCpu, 64) \
676	&& RT_VALID_ALIGNED_PTR((pVCpu)->CTX_SUFF(pVM), PAGE_SIZE) \
677	&& (unsigned)(pVCpu)->CTX_SUFF(pVM)->enmVMState < (unsigned)VMSTATE_DESTROYING, \
678	("pVCpu=%p pVM=%p state %s\n", (pVCpu), RT_VALID_ALIGNED_PTR(pVCpu, 64) ? (pVCpu)->CTX_SUFF(pVM) : NULL, \
679	RT_VALID_ALIGNED_PTR(pVCpu, 64) && RT_VALID_ALIGNED_PTR((pVCpu)->CTX_SUFF(pVM), PAGE_SIZE) \
680	? VMGetStateName((pVCpu)->pVMR3->enmVMState) : ""), \
681	(rc))
682
683
684	/** This is the VM structure.
685	*
686	* It contains (nearly?) all the VM data which have to be available in all
687	* contexts. Even if it contains all the data the idea is to use APIs not
688	* to modify all the members all around the place. Therefore we make use of
689	* unions to hide everything which isn't local to the current source module.
690	* This means we'll have to pay a little bit of attention when adding new
691	* members to structures in the unions and make sure to keep the padding sizes
692	* up to date.
693	*
694	* Run tstVMStructSize after update!
695	*/
696	typedef struct VM
697	{
698	/** The state of the VM.
699	* This field is read only to everyone except the VM and EM. */
700	VMSTATE volatile enmVMState;
701	/** Forced action flags.
702	* See the VM_FF_* \#defines. Updated atomically.
703	*/
704	volatile uint32_t fGlobalForcedActions;
705	/** Pointer to the array of page descriptors for the VM structure allocation. */
706	R3PTRTYPE(PSUPPAGE) paVMPagesR3;
707	/** Session handle. For use when calling SUPR0 APIs. */
708	PSUPDRVSESSION pSession;
709	/** Pointer to the ring-3 VM structure. */
710	PUVM pUVM;
711	/** Ring-3 Host Context VM Pointer. */
712	R3PTRTYPE(struct VM *) pVMR3;
713	/** Ring-0 Host Context VM Pointer. */
714	R0PTRTYPE(struct VM *) pVMR0;
715	/** Raw-mode Context VM Pointer. */
716	RCPTRTYPE(struct VM *) pVMRC;
717
718	/** The GVM VM handle. Only the GVM should modify this field. */
719	uint32_t hSelf;
720	/** Number of virtual CPUs. */
721	uint32_t cCpus;
722	/** CPU excution cap (1-100) */
723	uint32_t uCpuExecutionCap;
724
725	/** Size of the VM structure including the VMCPU array. */
726	uint32_t cbSelf;
727
728	/** Offset to the VMCPU array starting from beginning of this structure. */
729	uint32_t offVMCPU;
730
731	/** Reserved; alignment. */
732	uint32_t u32Reserved[5];
733
734	/** @name Public VMM Switcher APIs
735	* @{ */
736	/**
737	* Assembly switch entry point for returning to host context.
738	* This function will clean up the stack frame.
739	*
740	* @param eax The return code, register.
741	* @param Ctx The guest core context.
742	* @remark Assume interrupts disabled.
743	*/
744	RTRCPTR pfnVMMGCGuestToHostAsmGuestCtx/(int32_t eax, CPUMCTXCORE Ctx)/;
745
746	/**
747	* Assembly switch entry point for returning to host context.
748	*
749	* This is an alternative entry point which we'll be using when the we have the
750	* hypervisor context and need to save that before going to the host.
751	*
752	* This is typically useful when abandoning the hypervisor because of a trap
753	* and want the trap state to be saved.
754	*
755	* @param eax The return code, register.
756	* @param ecx Pointer to the hypervisor core context, register.
757	* @remark Assume interrupts disabled.
758	*/
759	RTRCPTR pfnVMMGCGuestToHostAsmHyperCtx/(int32_t eax, PCPUMCTXCORE ecx)/;
760
761	/**
762	* Assembly switch entry point for returning to host context.
763	*
764	* This is an alternative to the two *Ctx APIs and implies that the context has already
765	* been saved, or that it's just a brief return to HC and that the caller intends to resume
766	* whatever it is doing upon 'return' from this call.
767	*
768	* @param eax The return code, register.
769	* @remark Assume interrupts disabled.
770	*/
771	RTRCPTR pfnVMMGCGuestToHostAsm/(int32_t eax)/;
772	/** @} */
773
774
775	/** @name Various VM data owned by VM.
776	* @{ */
777	RTTHREAD uPadding1;
778	/** The native handle of ThreadEMT. Getting the native handle
779	* is generally faster than getting the IPRT one (except on OS/2 :-). */
780	RTNATIVETHREAD uPadding2;
781	/** @} */
782
783
784	/** @name Various items that are frequently accessed.
785	* @{ */
786	/** Raw ring-3 indicator. */
787	bool fRawR3Enabled;
788	/** Raw ring-0 indicator. */
789	bool fRawR0Enabled;
790	/** PATM enabled flag.
791	* This is placed here for performance reasons. */
792	bool fPATMEnabled;
793	/** CSAM enabled flag.
794	* This is placed here for performance reasons. */
795	bool fCSAMEnabled;
796	/** Hardware VM support is available and enabled.
797	* This is placed here for performance reasons. */
798	bool fHWACCMEnabled;
799	/** Hardware VM support is required and non-optional.
800	* This is initialized together with the rest of the VM structure. */
801	bool fHwVirtExtForced;
802	/** Set when this VM is the master FT node. */
803	bool fFaultTolerantMaster;
804	/** Large page enabled flag. */
805	bool fUseLargePages;
806	/** @} */
807
808
809	/* padding to make gnuc put the StatQemuToGC where msc does. */
810	#if HC_ARCH_BITS == 32
811	uint32_t padding0;
812	#endif
813
814	/** Profiling the total time from Qemu to GC. */
815	STAMPROFILEADV StatTotalQemuToGC;
816	/** Profiling the total time from GC to Qemu. */
817	STAMPROFILEADV StatTotalGCToQemu;
818	/** Profiling the total time spent in GC. */
819	STAMPROFILEADV StatTotalInGC;
820	/** Profiling the total time spent not in Qemu. */
821	STAMPROFILEADV StatTotalInQemu;
822	/** Profiling the VMMSwitcher code for going to GC. */
823	STAMPROFILEADV StatSwitcherToGC;
824	/** Profiling the VMMSwitcher code for going to HC. */
825	STAMPROFILEADV StatSwitcherToHC;
826	STAMPROFILEADV StatSwitcherSaveRegs;
827	STAMPROFILEADV StatSwitcherSysEnter;
828	STAMPROFILEADV StatSwitcherDebug;
829	STAMPROFILEADV StatSwitcherCR0;
830	STAMPROFILEADV StatSwitcherCR4;
831	STAMPROFILEADV StatSwitcherJmpCR3;
832	STAMPROFILEADV StatSwitcherRstrRegs;
833	STAMPROFILEADV StatSwitcherLgdt;
834	STAMPROFILEADV StatSwitcherLidt;
835	STAMPROFILEADV StatSwitcherLldt;
836	STAMPROFILEADV StatSwitcherTSS;
837
838	/** Padding - the unions must be aligned on a 64 bytes boundary and the unions
839	* must start at the same offset on both 64-bit and 32-bit hosts. */
840	uint8_t abAlignment1[HC_ARCH_BITS == 32 ? 48 : 24];
841
842	/** CPUM part. */
843	union
844	{
845	#ifdef ___CPUMInternal_h
846	struct CPUM s;
847	#endif
848	uint8_t padding[1472]; /* multiple of 64 */
849	} cpum;
850
851	/** VMM part. */
852	union
853	{
854	#ifdef ___VMMInternal_h
855	struct VMM s;
856	#endif
857	uint8_t padding[1536]; /* multiple of 64 */
858	} vmm;
859
860	/** PGM part. */
861	union
862	{
863	#ifdef ___PGMInternal_h
864	struct PGM s;
865	#endif
866	uint8_t padding[40962+6080]; / multiple of 64 */
867	} pgm;
868
869	/** HWACCM part. */
870	union
871	{
872	#ifdef ___HWACCMInternal_h
873	struct HWACCM s;
874	#endif
875	uint8_t padding[5376]; /* multiple of 64 */
876	} hwaccm;
877
878	/** TRPM part. */
879	union
880	{
881	#ifdef ___TRPMInternal_h
882	struct TRPM s;
883	#endif
884	uint8_t padding[5184]; /* multiple of 64 */
885	} trpm;
886
887	/** SELM part. */
888	union
889	{
890	#ifdef ___SELMInternal_h
891	struct SELM s;
892	#endif
893	uint8_t padding[576]; /* multiple of 64 */
894	} selm;
895
896	/** MM part. */
897	union
898	{
899	#ifdef ___MMInternal_h
900	struct MM s;
901	#endif
902	uint8_t padding[192]; /* multiple of 64 */
903	} mm;
904
905	/** PDM part. */
906	union
907	{
908	#ifdef ___PDMInternal_h
909	struct PDM s;
910	#endif
911	uint8_t padding[1600]; /* multiple of 64 */
912	} pdm;
913
914	/** IOM part. */
915	union
916	{
917	#ifdef ___IOMInternal_h
918	struct IOM s;
919	#endif
920	uint8_t padding[832]; /* multiple of 64 */
921	} iom;
922
923	/** PATM part. */
924	union
925	{
926	#ifdef ___PATMInternal_h
927	struct PATM s;
928	#endif
929	uint8_t padding[768]; /* multiple of 64 */
930	} patm;
931
932	/** CSAM part. */
933	union
934	{
935	#ifdef ___CSAMInternal_h
936	struct CSAM s;
937	#endif
938	uint8_t padding[1088]; /* multiple of 64 */
939	} csam;
940
941	/** EM part. */
942	union
943	{
944	#ifdef ___EMInternal_h
945	struct EM s;
946	#endif
947	uint8_t padding[256]; /* multiple of 64 */
948	} em;
949
950	/** TM part. */
951	union
952	{
953	#ifdef ___TMInternal_h
954	struct TM s;
955	#endif
956	uint8_t padding[2176]; /* multiple of 64 */
957	} tm;
958
959	/** DBGF part. */
960	union
961	{
962	#ifdef ___DBGFInternal_h
963	struct DBGF s;
964	#endif
965	uint8_t padding[2368]; /* multiple of 64 */
966	} dbgf;
967
968	/** SSM part. */
969	union
970	{
971	#ifdef ___SSMInternal_h
972	struct SSM s;
973	#endif
974	uint8_t padding[128]; /* multiple of 64 */
975	} ssm;
976
977	/** FTM part. */
978	union
979	{
980	#ifdef ___FTMInternal_h
981	struct FTM s;
982	#endif
983	uint8_t padding[512]; /* multiple of 64 */
984	} ftm;
985
986	/** REM part. */
987	union
988	{
989	#ifdef ___REMInternal_h
990	struct REM s;
991	#endif
992	uint8_t padding[0x11100]; /* multiple of 64 */
993	} rem;
994
995	/* ---- begin small stuff ---- */
996
997	/** VM part. */
998	union
999	{
1000	#ifdef ___VMInternal_h
1001	struct VMINT s;
1002	#endif
1003	uint8_t padding[24]; /* multiple of 8 */
1004	} vm;
1005
1006	/** CFGM part. */
1007	union
1008	{
1009	#ifdef ___CFGMInternal_h
1010	struct CFGM s;
1011	#endif
1012	uint8_t padding[8]; /* multiple of 8 */
1013	} cfgm;
1014
1015
1016	/** Padding for aligning the cpu array on a page boundary. */
1017	uint8_t abAlignment2[1502];
1018
1019	/* ---- end small stuff ---- */
1020
1021	/** VMCPU array for the configured number of virtual CPUs.
1022	* Must be aligned on a page boundary for TLB hit reasons as well as
1023	* alignment of VMCPU members. */
1024	VMCPU aCpus[1];
1025	} VM;
1026
1027
1028	#ifdef IN_RC
1029	RT_C_DECLS_BEGIN
1030
1031	/** The VM structure.
1032	* This is imported from the VMMGCBuiltin module, i.e. it's a one
1033	* of those magic globals which we should avoid using.
1034	*/
1035	extern DECLIMPORT(VM) g_VM;
1036
1037	RT_C_DECLS_END
1038	#endif
1039
1040	/** @} */
1041
1042	#endif

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source: vbox/trunk/include/VBox/vmm/vm.h@ 36448

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