vm.h@ 40397

Last change on this file since 40397 was 40397, checked in by vboxsync, 13 years ago
VMM: Make most of the tracing optional so we don't have to be afraid of adding lots more.
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1	/** @file
2	* VM - The Virtual Machine, data.
3	*/
4
5	/*
6	* Copyright (C) 2006-2011 Oracle Corporation
7	*
8	* This file is part of VirtualBox Open Source Edition (OSE), as
9	* available from http://www.virtualbox.org. This file is free software;
10	* you can redistribute it and/or modify it under the terms of the GNU
11	* General Public License (GPL) as published by the Free Software
12	* Foundation, in version 2 as it comes in the "COPYING" file of the
13	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15	*
16	* The contents of this file may alternatively be used under the terms
17	* of the Common Development and Distribution License Version 1.0
18	* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19	* VirtualBox OSE distribution, in which case the provisions of the
20	* CDDL are applicable instead of those of the GPL.
21	*
22	* You may elect to license modified versions of this file under the
23	* terms and conditions of either the GPL or the CDDL or both.
24	*/
25
26	#ifndef ___VBox_vmm_vm_h
27	#define ___VBox_vmm_vm_h
28
29	#include <VBox/types.h>
30	#include <VBox/vmm/cpum.h>
31	#include <VBox/vmm/stam.h>
32	#include <VBox/vmm/vmapi.h>
33	#include <VBox/vmm/vmm.h>
34	#include <VBox/sup.h>
35
36
37	/** @defgroup grp_vm The Virtual Machine
38	* @{
39	*/
40
41	/**
42	* The state of a Virtual CPU.
43	*
44	* The basic state indicated here is whether the CPU has been started or not. In
45	* addition, there are sub-states when started for assisting scheduling (GVMM
46	* mostly).
47	*
48	* The transision out of the STOPPED state is done by a vmR3PowerOn.
49	* The transision back to the STOPPED state is done by vmR3PowerOff.
50	*
51	* (Alternatively we could let vmR3PowerOn start CPU 0 only and let the SPIP
52	* handling switch on the other CPUs. Then vmR3Reset would stop all but CPU 0.)
53	*/
54	typedef enum VMCPUSTATE
55	{
56	/** The customary invalid zero. */
57	VMCPUSTATE_INVALID = 0,
58
59	/** Virtual CPU has not yet been started. */
60	VMCPUSTATE_STOPPED,
61
62	/** CPU started. */
63	VMCPUSTATE_STARTED,
64	/** Executing guest code and can be poked. */
65	VMCPUSTATE_STARTED_EXEC,
66	/** Executing guest code in the recompiler. */
67	VMCPUSTATE_STARTED_EXEC_REM,
68	/** Halted. */
69	VMCPUSTATE_STARTED_HALTED,
70
71	/** The end of valid virtual CPU states. */
72	VMCPUSTATE_END,
73
74	/** Ensure 32-bit type. */
75	VMCPUSTATE_32BIT_HACK = 0x7fffffff
76	} VMCPUSTATE;
77
78
79	/**
80	* Per virtual CPU data.
81	*/
82	typedef struct VMCPU
83	{
84	/** Per CPU forced action.
85	* See the VMCPU_FF_* \#defines. Updated atomically. */
86	uint32_t volatile fLocalForcedActions;
87	/** The CPU state. */
88	VMCPUSTATE volatile enmState;
89
90	/** Pointer to the ring-3 UVMCPU structure. */
91	PUVMCPU pUVCpu;
92	/** Ring-3 Host Context VM Pointer. */
93	PVMR3 pVMR3;
94	/** Ring-0 Host Context VM Pointer. */
95	PVMR0 pVMR0;
96	/** Flag indicating that tracing is enabled. */
97	bool fTracingEnabled;
98	/** Alignment padding. */
99	uint8_t abAlignment0[HC_ARCH_BITS == 32 ? 3 : 7];
100	/** Raw-mode Context VM Pointer. */
101	PVMRC pVMRC;
102	/** The CPU ID.
103	* This is the index into the VM::aCpu array. */
104	VMCPUID idCpu;
105	/** The native thread handle. */
106	RTNATIVETHREAD hNativeThread;
107	/** The native R0 thread handle. (different from the R3 handle!) */
108	RTNATIVETHREAD hNativeThreadR0;
109	/** Which host CPU ID is this EMT running on.
110	* Only valid when in RC or HWACCMR0 with scheduling disabled. */
111	RTCPUID volatile idHostCpu;
112	/** State data for use by ad hoc profiling. */
113	uint32_t uAdHoc;
114	/** Profiling samples for use by ad hoc profiling. */
115	STAMPROFILEADV aStatAdHoc[8];
116
117	/** Align the next bit on a 64-byte boundary and make sure it starts at the same
118	* offset in both 64-bit and 32-bit builds.
119	*
120	* @remarks The alignments of the members that are larger than 48 bytes should be
121	* 64-byte for cache line reasons. structs containing small amounts of
122	* data could be lumped together at the end with a < 64 byte padding
123	* following it (to grow into and align the struct size).
124	* */
125	uint8_t abAlignment1[HC_ARCH_BITS == 32 ? 16+64 : 56];
126
127	/** CPUM part. */
128	union
129	{
130	#ifdef ___CPUMInternal_h
131	struct CPUMCPU s;
132	#endif
133	uint8_t padding[3456]; /* multiple of 64 */
134	} cpum;
135
136	/** HWACCM part. */
137	union
138	{
139	#ifdef ___HWACCMInternal_h
140	struct HWACCMCPU s;
141	#endif
142	uint8_t padding[5312]; /* multiple of 64 */
143	} hwaccm;
144
145	/** EM part. */
146	union
147	{
148	#ifdef ___EMInternal_h
149	struct EMCPU s;
150	#endif
151	uint8_t padding[1472]; /* multiple of 64 */
152	} em;
153
154	/** IEM part. */
155	union
156	{
157	#ifdef ___IEMInternal_h
158	struct IEMCPU s;
159	#endif
160	uint8_t padding[3072]; /* multiple of 64 */
161	} iem;
162
163	/** TRPM part. */
164	union
165	{
166	#ifdef ___TRPMInternal_h
167	struct TRPMCPU s;
168	#endif
169	uint8_t padding[128]; /* multiple of 64 */
170	} trpm;
171
172	/** TM part. */
173	union
174	{
175	#ifdef ___TMInternal_h
176	struct TMCPU s;
177	#endif
178	uint8_t padding[384]; /* multiple of 64 */
179	} tm;
180
181	/** VMM part. */
182	union
183	{
184	#ifdef ___VMMInternal_h
185	struct VMMCPU s;
186	#endif
187	uint8_t padding[384]; /* multiple of 64 */
188	} vmm;
189
190	/** PDM part. */
191	union
192	{
193	#ifdef ___PDMInternal_h
194	struct PDMCPU s;
195	#endif
196	uint8_t padding[128]; /* multiple of 64 */
197	} pdm;
198
199	/** IOM part. */
200	union
201	{
202	#ifdef ___IOMInternal_h
203	struct IOMCPU s;
204	#endif
205	uint8_t padding[512]; /* multiple of 64 */
206	} iom;
207
208	/** DBGF part.
209	* @todo Combine this with other tiny structures. */
210	union
211	{
212	#ifdef ___DBGFInternal_h
213	struct DBGFCPU s;
214	#endif
215	uint8_t padding[64]; /* multiple of 64 */
216	} dbgf;
217
218	/** Align the following members on page boundary. */
219	uint8_t abAlignment2[1024];
220
221	/** PGM part. */
222	union
223	{
224	#ifdef ___PGMInternal_h
225	struct PGMCPU s;
226	#endif
227	uint8_t padding[4096]; /* multiple of 4096 */
228	} pgm;
229
230	} VMCPU;
231
232
233	/** @name Operations on VMCPU::enmState
234	* @{ */
235	/** Gets the VMCPU state. */
236	#define VMCPU_GET_STATE(pVCpu) ( (pVCpu)->enmState )
237	/** Sets the VMCPU state. */
238	#define VMCPU_SET_STATE(pVCpu, enmNewState) \
239	ASMAtomicWriteU32((uint32_t volatile *)&(pVCpu)->enmState, (enmNewState))
240	/** Cmpares and sets the VMCPU state. */
241	#define VMCPU_CMPXCHG_STATE(pVCpu, enmNewState, enmOldState) \
242	ASMAtomicCmpXchgU32((uint32_t volatile *)&(pVCpu)->enmState, (enmNewState), (enmOldState))
243	/** Checks the VMCPU state. */
244	#ifdef VBOX_STRICT
245	# define VMCPU_ASSERT_STATE(pVCpu, enmExpectedState) \
246	do { \
247	VMCPUSTATE enmState = VMCPU_GET_STATE(pVCpu); \
248	AssertMsg(enmState == (enmExpectedState), \
249	("enmState=%d enmExpectedState=%d idCpu=%u\n", \
250	enmState, enmExpectedState, (pVCpu)->idCpu)); \
251	} while (0)
252	#else
253	# define VMCPU_ASSERT_STATE(pVCpu, enmExpectedState) do { } while (0)
254	#endif
255	/** Tests if the state means that the CPU is started. */
256	#define VMCPUSTATE_IS_STARTED(enmState) ( (enmState) > VMCPUSTATE_STOPPED )
257	/** Tests if the state means that the CPU is stopped. */
258	#define VMCPUSTATE_IS_STOPPED(enmState) ( (enmState) == VMCPUSTATE_STOPPED )
259	/** @} */
260
261
262	/** The name of the Guest Context VMM Core module. */
263	#define VMMGC_MAIN_MODULE_NAME "VMMGC.gc"
264	/** The name of the Ring 0 Context VMM Core module. */
265	#define VMMR0_MAIN_MODULE_NAME "VMMR0.r0"
266
267	/** VM Forced Action Flags.
268	*
269	* Use the VM_FF_SET() and VM_FF_CLEAR() macros to change the force
270	* action mask of a VM.
271	*
272	* @{
273	*/
274	/** The virtual sync clock has been stopped, go to TM until it has been
275	* restarted... */
276	#define VM_FF_TM_VIRTUAL_SYNC RT_BIT_32(2)
277	/** PDM Queues are pending. */
278	#define VM_FF_PDM_QUEUES RT_BIT_32(VM_FF_PDM_QUEUES_BIT)
279	/** The bit number for VM_FF_PDM_QUEUES. */
280	#define VM_FF_PDM_QUEUES_BIT 3
281	/** PDM DMA transfers are pending. */
282	#define VM_FF_PDM_DMA RT_BIT_32(VM_FF_PDM_DMA_BIT)
283	/** The bit number for VM_FF_PDM_DMA. */
284	#define VM_FF_PDM_DMA_BIT 4
285	/** This action forces the VM to call DBGF so DBGF can service debugger
286	* requests in the emulation thread.
287	* This action flag stays asserted till DBGF clears it.*/
288	#define VM_FF_DBGF RT_BIT_32(VM_FF_DBGF_BIT)
289	/** The bit number for VM_FF_DBGF. */
290	#define VM_FF_DBGF_BIT 8
291	/** This action forces the VM to service pending requests from other
292	* thread or requests which must be executed in another context. */
293	#define VM_FF_REQUEST RT_BIT_32(9)
294	/** Check for VM state changes and take appropriate action. */
295	#define VM_FF_CHECK_VM_STATE RT_BIT_32(VM_FF_CHECK_VM_STATE_BIT)
296	/** The bit number for VM_FF_CHECK_VM_STATE. */
297	#define VM_FF_CHECK_VM_STATE_BIT 10
298	/** Reset the VM. (postponed) */
299	#define VM_FF_RESET RT_BIT_32(VM_FF_RESET_BIT)
300	/** The bit number for VM_FF_RESET. */
301	#define VM_FF_RESET_BIT 11
302	/** EMT rendezvous in VMM. */
303	#define VM_FF_EMT_RENDEZVOUS RT_BIT_32(VM_FF_EMT_RENDEZVOUS_BIT)
304	/** The bit number for VM_FF_EMT_RENDEZVOUS. */
305	#define VM_FF_EMT_RENDEZVOUS_BIT 12
306
307	/** PGM needs to allocate handy pages. */
308	#define VM_FF_PGM_NEED_HANDY_PAGES RT_BIT_32(18)
309	/** PGM is out of memory.
310	* Abandon all loops and code paths which can be resumed and get up to the EM
311	* loops. */
312	#define VM_FF_PGM_NO_MEMORY RT_BIT_32(19)
313	/** PGM is about to perform a lightweight pool flush
314	* Guest SMP: all EMT threads should return to ring 3
315	*/
316	#define VM_FF_PGM_POOL_FLUSH_PENDING RT_BIT_32(20)
317	/** REM needs to be informed about handler changes. */
318	#define VM_FF_REM_HANDLER_NOTIFY RT_BIT_32(VM_FF_REM_HANDLER_NOTIFY_BIT)
319	/** The bit number for VM_FF_REM_HANDLER_NOTIFY. */
320	#define VM_FF_REM_HANDLER_NOTIFY_BIT 29
321	/** Suspend the VM - debug only. */
322	#define VM_FF_DEBUG_SUSPEND RT_BIT_32(31)
323
324
325	/** This action forces the VM to check any pending interrups on the APIC. */
326	#define VMCPU_FF_INTERRUPT_APIC RT_BIT_32(0)
327	/** This action forces the VM to check any pending interrups on the PIC. */
328	#define VMCPU_FF_INTERRUPT_PIC RT_BIT_32(1)
329	/** This action forces the VM to schedule and run pending timer (TM).
330	* @remarks Don't move - PATM compatibility. */
331	#define VMCPU_FF_TIMER RT_BIT_32(2)
332	/** This action forces the VM to check any pending NMIs. */
333	#define VMCPU_FF_INTERRUPT_NMI_BIT 3
334	#define VMCPU_FF_INTERRUPT_NMI RT_BIT_32(VMCPU_FF_INTERRUPT_NMI_BIT)
335	/** This action forces the VM to check any pending SMIs. */
336	#define VMCPU_FF_INTERRUPT_SMI_BIT 4
337	#define VMCPU_FF_INTERRUPT_SMI RT_BIT_32(VMCPU_FF_INTERRUPT_SMI_BIT)
338	/** PDM critical section unlocking is pending, process promptly upon return to R3. */
339	#define VMCPU_FF_PDM_CRITSECT RT_BIT_32(5)
340	/** This action forces the VM to service pending requests from other
341	* thread or requests which must be executed in another context. */
342	#define VMCPU_FF_REQUEST RT_BIT_32(9)
343	/** This action forces the VM to resync the page tables before going
344	* back to execute guest code. (GLOBAL FLUSH) */
345	#define VMCPU_FF_PGM_SYNC_CR3 RT_BIT_32(16)
346	/** Same as VM_FF_PGM_SYNC_CR3 except that global pages can be skipped.
347	* (NON-GLOBAL FLUSH) */
348	#define VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL RT_BIT_32(17)
349	/** Check for pending TLB shootdown actions.
350	* Consumer: HWACCM
351	* @todo rename to VMCPU_FF_HWACCM_TLB_SHOOTDOWN */
352	#define VMCPU_FF_TLB_SHOOTDOWN RT_BIT_32(18)
353	/** Check for pending TLB flush action.
354	* Consumer: HWACCM
355	* @todo rename to VMCPU_FF_HWACCM_TLB_FLUSH */
356	#define VMCPU_FF_TLB_FLUSH RT_BIT_32(VMCPU_FF_TLB_FLUSH_BIT)
357	/** The bit number for VMCPU_FF_TLB_FLUSH. */
358	#define VMCPU_FF_TLB_FLUSH_BIT 19
359	/** Check the interrupt and trap gates */
360	#define VMCPU_FF_TRPM_SYNC_IDT RT_BIT_32(20)
361	/** Check Guest's TSS ring 0 stack */
362	#define VMCPU_FF_SELM_SYNC_TSS RT_BIT_32(21)
363	/** Check Guest's GDT table */
364	#define VMCPU_FF_SELM_SYNC_GDT RT_BIT_32(22)
365	/** Check Guest's LDT table */
366	#define VMCPU_FF_SELM_SYNC_LDT RT_BIT_32(23)
367	/** Inhibit interrupts pending. See EMGetInhibitInterruptsPC(). */
368	#define VMCPU_FF_INHIBIT_INTERRUPTS RT_BIT_32(24)
369	/** CSAM needs to scan the page that's being executed */
370	#define VMCPU_FF_CSAM_SCAN_PAGE RT_BIT_32(26)
371	/** CSAM needs to do some homework. */
372	#define VMCPU_FF_CSAM_PENDING_ACTION RT_BIT_32(27)
373	/** Force return to Ring-3. */
374	#define VMCPU_FF_TO_R3 RT_BIT_32(28)
375
376	/** Externally VM forced actions. Used to quit the idle/wait loop. */
377	#define VM_FF_EXTERNAL_SUSPENDED_MASK (VM_FF_CHECK_VM_STATE \| VM_FF_DBGF \| VM_FF_REQUEST \| VM_FF_EMT_RENDEZVOUS)
378	/** Externally VMCPU forced actions. Used to quit the idle/wait loop. */
379	#define VMCPU_FF_EXTERNAL_SUSPENDED_MASK (VMCPU_FF_REQUEST)
380
381	/** Externally forced VM actions. Used to quit the idle/wait loop. */
382	#define VM_FF_EXTERNAL_HALTED_MASK ( VM_FF_CHECK_VM_STATE \| VM_FF_DBGF \| VM_FF_REQUEST \
383	\| VM_FF_PDM_QUEUES \| VM_FF_PDM_DMA \| VM_FF_EMT_RENDEZVOUS)
384	/** Externally forced VMCPU actions. Used to quit the idle/wait loop. */
385	#define VMCPU_FF_EXTERNAL_HALTED_MASK (VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC \| VMCPU_FF_REQUEST \| VMCPU_FF_TIMER)
386
387	/** High priority VM pre-execution actions. */
388	#define VM_FF_HIGH_PRIORITY_PRE_MASK ( VM_FF_CHECK_VM_STATE \| VM_FF_DBGF \| VM_FF_TM_VIRTUAL_SYNC \
389	\| VM_FF_DEBUG_SUSPEND \| VM_FF_PGM_NEED_HANDY_PAGES \| VM_FF_PGM_NO_MEMORY \| VM_FF_EMT_RENDEZVOUS)
390	/** High priority VMCPU pre-execution actions. */
391	#define VMCPU_FF_HIGH_PRIORITY_PRE_MASK ( VMCPU_FF_TIMER \| VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC \| VMCPU_FF_PGM_SYNC_CR3 \
392	\| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL \| VMCPU_FF_SELM_SYNC_TSS \| VMCPU_FF_TRPM_SYNC_IDT \
393	\| VMCPU_FF_SELM_SYNC_GDT \| VMCPU_FF_SELM_SYNC_LDT \| VMCPU_FF_INHIBIT_INTERRUPTS)
394
395	/** High priority VM pre raw-mode execution mask. */
396	#define VM_FF_HIGH_PRIORITY_PRE_RAW_MASK (VM_FF_PGM_NEED_HANDY_PAGES \| VM_FF_PGM_NO_MEMORY)
397	/** High priority VMCPU pre raw-mode execution mask. */
398	#define VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK ( VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL \| VMCPU_FF_SELM_SYNC_TSS \| VMCPU_FF_TRPM_SYNC_IDT \
399	\| VMCPU_FF_SELM_SYNC_GDT \| VMCPU_FF_SELM_SYNC_LDT \| VMCPU_FF_INHIBIT_INTERRUPTS)
400
401	/** High priority post-execution actions. */
402	#define VM_FF_HIGH_PRIORITY_POST_MASK (VM_FF_PGM_NO_MEMORY)
403	/** High priority post-execution actions. */
404	#define VMCPU_FF_HIGH_PRIORITY_POST_MASK (VMCPU_FF_PDM_CRITSECT\|VMCPU_FF_CSAM_PENDING_ACTION)
405
406	/** Normal priority VM post-execution actions. */
407	#define VM_FF_NORMAL_PRIORITY_POST_MASK ( VM_FF_CHECK_VM_STATE \| VM_FF_DBGF \| VM_FF_RESET \
408	\| VM_FF_PGM_NO_MEMORY \| VM_FF_EMT_RENDEZVOUS)
409	/** Normal priority VMCPU post-execution actions. */
410	#define VMCPU_FF_NORMAL_PRIORITY_POST_MASK (VMCPU_FF_CSAM_SCAN_PAGE)
411
412	/** Normal priority VM actions. */
413	#define VM_FF_NORMAL_PRIORITY_MASK (VM_FF_REQUEST \| VM_FF_PDM_QUEUES \| VM_FF_PDM_DMA \| VM_FF_REM_HANDLER_NOTIFY \| VM_FF_EMT_RENDEZVOUS)
414	/** Normal priority VMCPU actions. */
415	#define VMCPU_FF_NORMAL_PRIORITY_MASK (VMCPU_FF_REQUEST)
416
417	/** Flags to clear before resuming guest execution. */
418	#define VMCPU_FF_RESUME_GUEST_MASK (VMCPU_FF_TO_R3)
419
420	/** VM Flags that cause the HWACCM loops to go back to ring-3. */
421	#define VM_FF_HWACCM_TO_R3_MASK (VM_FF_TM_VIRTUAL_SYNC \| VM_FF_PGM_NEED_HANDY_PAGES \| VM_FF_PGM_NO_MEMORY \| VM_FF_PDM_QUEUES \| VM_FF_EMT_RENDEZVOUS)
422	/** VMCPU Flags that cause the HWACCM loops to go back to ring-3. */
423	#define VMCPU_FF_HWACCM_TO_R3_MASK (VMCPU_FF_TO_R3 \| VMCPU_FF_TIMER \| VMCPU_FF_PDM_CRITSECT)
424
425	/** All the forced VM flags. */
426	#define VM_FF_ALL_MASK (~0U)
427	/** All the forced VMCPU flags. */
428	#define VMCPU_FF_ALL_MASK (~0U)
429
430	/** All the forced VM flags except those related to raw-mode and hardware
431	* assisted execution. */
432	#define VM_FF_ALL_REM_MASK (~(VM_FF_HIGH_PRIORITY_PRE_RAW_MASK) \| VM_FF_PGM_NO_MEMORY)
433	/** All the forced VMCPU flags except those related to raw-mode and hardware
434	* assisted execution. */
435	#define VMCPU_FF_ALL_REM_MASK (~(VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK \| VMCPU_FF_CSAM_PENDING_ACTION \| VMCPU_FF_PDM_CRITSECT \| VMCPU_FF_TLB_FLUSH \| VMCPU_FF_TLB_SHOOTDOWN))
436
437	/** @} */
438
439	/** @def VM_FF_SET
440	* Sets a force action flag.
441	*
442	* @param pVM VM Handle.
443	* @param fFlag The flag to set.
444	*/
445	#if 1
446	# define VM_FF_SET(pVM, fFlag) ASMAtomicOrU32(&(pVM)->fGlobalForcedActions, (fFlag))
447	#else
448	# define VM_FF_SET(pVM, fFlag) \
449	do { ASMAtomicOrU32(&(pVM)->fGlobalForcedActions, (fFlag)); \
450	RTLogPrintf("VM_FF_SET : %08x %s - %s(%d) %s\n", (pVM)->fGlobalForcedActions, #fFlag, __FILE__, __LINE__, __FUNCTION__); \
451	} while (0)
452	#endif
453
454	/** @def VMCPU_FF_SET
455	* Sets a force action flag for the given VCPU.
456	*
457	* @param pVCpu VMCPU Handle.
458	* @param fFlag The flag to set.
459	*/
460	#define VMCPU_FF_SET(pVCpu, fFlag) ASMAtomicOrU32(&(pVCpu)->fLocalForcedActions, (fFlag))
461
462	/** @def VM_FF_CLEAR
463	* Clears a force action flag.
464	*
465	* @param pVM VM Handle.
466	* @param fFlag The flag to clear.
467	*/
468	#if 1
469	# define VM_FF_CLEAR(pVM, fFlag) ASMAtomicAndU32(&(pVM)->fGlobalForcedActions, ~(fFlag))
470	#else
471	# define VM_FF_CLEAR(pVM, fFlag) \
472	do { ASMAtomicAndU32(&(pVM)->fGlobalForcedActions, ~(fFlag)); \
473	RTLogPrintf("VM_FF_CLEAR: %08x %s - %s(%d) %s\n", (pVM)->fGlobalForcedActions, #fFlag, __FILE__, __LINE__, __FUNCTION__); \
474	} while (0)
475	#endif
476
477	/** @def VMCPU_FF_CLEAR
478	* Clears a force action flag for the given VCPU.
479	*
480	* @param pVCpu VMCPU Handle.
481	* @param fFlag The flag to clear.
482	*/
483	#define VMCPU_FF_CLEAR(pVCpu, fFlag) ASMAtomicAndU32(&(pVCpu)->fLocalForcedActions, ~(fFlag))
484
485	/** @def VM_FF_ISSET
486	* Checks if a force action flag is set.
487	*
488	* @param pVM VM Handle.
489	* @param fFlag The flag to check.
490	*/
491	#define VM_FF_ISSET(pVM, fFlag) (((pVM)->fGlobalForcedActions & (fFlag)) == (fFlag))
492
493	/** @def VMCPU_FF_ISSET
494	* Checks if a force action flag is set for the given VCPU.
495	*
496	* @param pVCpu VMCPU Handle.
497	* @param fFlag The flag to check.
498	*/
499	#define VMCPU_FF_ISSET(pVCpu, fFlag) (((pVCpu)->fLocalForcedActions & (fFlag)) == (fFlag))
500
501	/** @def VM_FF_ISPENDING
502	* Checks if one or more force action in the specified set is pending.
503	*
504	* @param pVM VM Handle.
505	* @param fFlags The flags to check for.
506	*/
507	#define VM_FF_ISPENDING(pVM, fFlags) ((pVM)->fGlobalForcedActions & (fFlags))
508
509	/** @def VM_FF_TESTANDCLEAR
510	* Checks if one (!) force action in the specified set is pending and clears it atomically
511	*
512	* @returns true if the bit was set.
513	* @returns false if the bit was clear.
514	* @param pVM VM Handle.
515	* @param iBit Bit position to check and clear
516	*/
517	#define VM_FF_TESTANDCLEAR(pVM, iBit) (ASMAtomicBitTestAndClear(&(pVM)->fGlobalForcedActions, iBit##_BIT))
518
519	/** @def VMCPU_FF_TESTANDCLEAR
520	* Checks if one (!) force action in the specified set is pending and clears it atomically
521	*
522	* @returns true if the bit was set.
523	* @returns false if the bit was clear.
524	* @param pVCpu VMCPU Handle.
525	* @param iBit Bit position to check and clear
526	*/
527	#define VMCPU_FF_TESTANDCLEAR(pVCpu, iBit) (ASMAtomicBitTestAndClear(&(pVCpu)->fLocalForcedActions, iBit##_BIT))
528
529	/** @def VMCPU_FF_ISPENDING
530	* Checks if one or more force action in the specified set is pending for the given VCPU.
531	*
532	* @param pVCpu VMCPU Handle.
533	* @param fFlags The flags to check for.
534	*/
535	#define VMCPU_FF_ISPENDING(pVCpu, fFlags) ((pVCpu)->fLocalForcedActions & (fFlags))
536
537	/** @def VM_FF_ISPENDING
538	* Checks if one or more force action in the specified set is pending while one
539	* or more other ones are not.
540	*
541	* @param pVM VM Handle.
542	* @param fFlags The flags to check for.
543	* @param fExcpt The flags that should not be set.
544	*/
545	#define VM_FF_IS_PENDING_EXCEPT(pVM, fFlags, fExcpt) ( ((pVM)->fGlobalForcedActions & (fFlags)) && !((pVM)->fGlobalForcedActions & (fExcpt)) )
546
547	/** @def VMCPU_FF_IS_PENDING_EXCEPT
548	* Checks if one or more force action in the specified set is pending for the given
549	* VCPU while one or more other ones are not.
550	*
551	* @param pVCpu VMCPU Handle.
552	* @param fFlags The flags to check for.
553	* @param fExcpt The flags that should not be set.
554	*/
555	#define VMCPU_FF_IS_PENDING_EXCEPT(pVCpu, fFlags, fExcpt) ( ((pVCpu)->fLocalForcedActions & (fFlags)) && !((pVCpu)->fLocalForcedActions & (fExcpt)) )
556
557	/** @def VM_IS_EMT
558	* Checks if the current thread is the emulation thread (EMT).
559	*
560	* @remark The ring-0 variation will need attention if we expand the ring-0
561	* code to let threads other than EMT mess around with the VM.
562	*/
563	#ifdef IN_RC
564	# define VM_IS_EMT(pVM) true
565	#else
566	# define VM_IS_EMT(pVM) (VMMGetCpu(pVM) != NULL)
567	#endif
568
569	/** @def VMCPU_IS_EMT
570	* Checks if the current thread is the emulation thread (EMT) for the specified
571	* virtual CPU.
572	*/
573	#ifdef IN_RC
574	# define VMCPU_IS_EMT(pVCpu) true
575	#else
576	# define VMCPU_IS_EMT(pVCpu) ((pVCpu) && ((pVCpu) == VMMGetCpu((pVCpu)->CTX_SUFF(pVM))))
577	#endif
578
579	/** @def VM_ASSERT_EMT
580	* Asserts that the current thread IS the emulation thread (EMT).
581	*/
582	#ifdef IN_RC
583	# define VM_ASSERT_EMT(pVM) Assert(VM_IS_EMT(pVM))
584	#elif defined(IN_RING0)
585	# define VM_ASSERT_EMT(pVM) Assert(VM_IS_EMT(pVM))
586	#else
587	# define VM_ASSERT_EMT(pVM) \
588	AssertMsg(VM_IS_EMT(pVM), \
589	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd\n", RTThreadNativeSelf(), VMR3GetVMCPUNativeThread(pVM)))
590	#endif
591
592	/** @def VMCPU_ASSERT_EMT
593	* Asserts that the current thread IS the emulation thread (EMT) of the
594	* specified virtual CPU.
595	*/
596	#ifdef IN_RC
597	# define VMCPU_ASSERT_EMT(pVCpu) Assert(VMCPU_IS_EMT(pVCpu))
598	#elif defined(IN_RING0)
599	# define VMCPU_ASSERT_EMT(pVCpu) Assert(VMCPU_IS_EMT(pVCpu))
600	#else
601	# define VMCPU_ASSERT_EMT(pVCpu) \
602	AssertMsg(VMCPU_IS_EMT(pVCpu), \
603	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd idCpu=%#x\n", \
604	RTThreadNativeSelf(), (pVCpu)->hNativeThread, (pVCpu)->idCpu))
605	#endif
606
607	/** @def VM_ASSERT_EMT_RETURN
608	* Asserts that the current thread IS the emulation thread (EMT) and returns if it isn't.
609	*/
610	#ifdef IN_RC
611	# define VM_ASSERT_EMT_RETURN(pVM, rc) AssertReturn(VM_IS_EMT(pVM), (rc))
612	#elif defined(IN_RING0)
613	# define VM_ASSERT_EMT_RETURN(pVM, rc) AssertReturn(VM_IS_EMT(pVM), (rc))
614	#else
615	# define VM_ASSERT_EMT_RETURN(pVM, rc) \
616	AssertMsgReturn(VM_IS_EMT(pVM), \
617	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd\n", RTThreadNativeSelf(), VMR3GetVMCPUNativeThread(pVM)), \
618	(rc))
619	#endif
620
621	/** @def VMCPU_ASSERT_EMT_RETURN
622	* Asserts that the current thread IS the emulation thread (EMT) and returns if it isn't.
623	*/
624	#ifdef IN_RC
625	# define VMCPU_ASSERT_EMT_RETURN(pVCpu, rc) AssertReturn(VMCPU_IS_EMT(pVCpu), (rc))
626	#elif defined(IN_RING0)
627	# define VMCPU_ASSERT_EMT_RETURN(pVCpu, rc) AssertReturn(VMCPU_IS_EMT(pVCpu), (rc))
628	#else
629	# define VMCPU_ASSERT_EMT_RETURN(pVCpu, rc) \
630	AssertMsg(VMCPU_IS_EMT(pVCpu), \
631	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd idCpu=%#x\n", \
632	RTThreadNativeSelf(), (pVCpu)->hNativeThread, (pVCpu)->idCpu), \
633	(rc))
634	#endif
635
636	/** @def VMCPU_ASSERT_EMT_OR_GURU
637	* Asserts that the current thread IS the emulation thread (EMT) of the
638	* specified virtual CPU.
639	*/
640	#if defined(IN_RC) \|\| defined(IN_RING0)
641	# define VMCPU_ASSERT_EMT_OR_GURU(pVCpu) Assert( VMCPU_IS_EMT(pVCpu) \
642	\|\| pVCpu->CTX_SUFF(pVM)->enmVMState == VMSTATE_GURU_MEDITATION \
643	\|\| pVCpu->CTX_SUFF(pVM)->enmVMState == VMSTATE_GURU_MEDITATION_LS )
644	#else
645	# define VMCPU_ASSERT_EMT_OR_GURU(pVCpu) \
646	AssertMsg( VMCPU_IS_EMT(pVCpu) \
647	\|\| pVCpu->CTX_SUFF(pVM)->enmVMState == VMSTATE_GURU_MEDITATION \
648	\|\| pVCpu->CTX_SUFF(pVM)->enmVMState == VMSTATE_GURU_MEDITATION_LS, \
649	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd idCpu=%#x\n", \
650	RTThreadNativeSelf(), (pVCpu)->hNativeThread, (pVCpu)->idCpu))
651	#endif
652
653	/** @def VMCPU_ASSERT_EMT_OR_NOT_RUNNING
654	* Asserts that the current thread IS the emulation thread (EMT) of the
655	* specified virtual CPU when the VM is running.
656	*/
657	#if defined(IN_RC) \|\| defined(IN_RING0)
658	# define VMCPU_ASSERT_EMT_OR_NOT_RUNNING(pVCpu) \
659	Assert( VMCPU_IS_EMT(pVCpu) \
660	\|\| pVCpu->CTX_SUFF(pVM)->enmVMState == VMSTATE_RUNNING \
661	\|\| pVCpu->CTX_SUFF(pVM)->enmVMState == VMSTATE_RUNNING_LS \
662	\|\| pVCpu->CTX_SUFF(pVM)->enmVMState == VMSTATE_RUNNING_FT )
663	#else
664	# define VMCPU_ASSERT_EMT_OR_NOT_RUNNING(pVCpu) \
665	AssertMsg( VMCPU_IS_EMT(pVCpu) \
666	\|\| pVCpu->CTX_SUFF(pVM)->enmVMState == VMSTATE_RUNNING \
667	\|\| pVCpu->CTX_SUFF(pVM)->enmVMState == VMSTATE_RUNNING_LS \
668	\|\| pVCpu->CTX_SUFF(pVM)->enmVMState == VMSTATE_RUNNING_FT, \
669	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd idCpu=%#x\n", \
670	RTThreadNativeSelf(), (pVCpu)->hNativeThread, (pVCpu)->idCpu))
671	#endif
672
673	/** @def VM_ASSERT_EMT0
674	* Asserts that the current thread IS emulation thread \#0 (EMT0).
675	*/
676	#define VM_ASSERT_EMT0(pVM) VMCPU_ASSERT_EMT(&(pVM)->aCpus[0])
677
678	/** @def VM_ASSERT_EMT0_RETURN
679	* Asserts that the current thread IS emulation thread \#0 (EMT0) and returns if
680	* it isn't.
681	*/
682	#define VM_ASSERT_EMT0_RETURN(pVM, rc) VMCPU_ASSERT_EMT_RETURN(&(pVM)->aCpus[0], (rc))
683
684
685	/**
686	* Asserts that the current thread is NOT the emulation thread.
687	*/
688	#define VM_ASSERT_OTHER_THREAD(pVM) \
689	AssertMsg(!VM_IS_EMT(pVM), ("Not other thread!!\n"))
690
691
692	/** @def VM_ASSERT_STATE_RETURN
693	* Asserts a certain VM state.
694	*/
695	#define VM_ASSERT_STATE(pVM, _enmState) \
696	AssertMsg((pVM)->enmVMState == (_enmState), \
697	("state %s, expected %s\n", VMGetStateName((pVM)->enmVMState), VMGetStateName(_enmState)))
698
699	/** @def VM_ASSERT_STATE_RETURN
700	* Asserts a certain VM state and returns if it doesn't match.
701	*/
702	#define VM_ASSERT_STATE_RETURN(pVM, _enmState, rc) \
703	AssertMsgReturn((pVM)->enmVMState == (_enmState), \
704	("state %s, expected %s\n", VMGetStateName((pVM)->enmVMState), VMGetStateName(_enmState)), \
705	(rc))
706
707	/** @def VM_ASSERT_VALID_EXT_RETURN
708	* Asserts a the VM handle is valid for external access, i.e. not being
709	* destroy or terminated.
710	*/
711	#define VM_ASSERT_VALID_EXT_RETURN(pVM, rc) \
712	AssertMsgReturn( RT_VALID_ALIGNED_PTR(pVM, PAGE_SIZE) \
713	&& ( (unsigned)(pVM)->enmVMState < (unsigned)VMSTATE_DESTROYING \
714	\|\| ( (unsigned)(pVM)->enmVMState == (unsigned)VMSTATE_DESTROYING \
715	&& VM_IS_EMT(pVM))), \
716	("pVM=%p state %s\n", (pVM), RT_VALID_ALIGNED_PTR(pVM, PAGE_SIZE) \
717	? VMGetStateName(pVM->enmVMState) : ""), \
718	(rc))
719
720	/** @def VMCPU_ASSERT_VALID_EXT_RETURN
721	* Asserts a the VMCPU handle is valid for external access, i.e. not being
722	* destroy or terminated.
723	*/
724	#define VMCPU_ASSERT_VALID_EXT_RETURN(pVCpu, rc) \
725	AssertMsgReturn( RT_VALID_ALIGNED_PTR(pVCpu, 64) \
726	&& RT_VALID_ALIGNED_PTR((pVCpu)->CTX_SUFF(pVM), PAGE_SIZE) \
727	&& (unsigned)(pVCpu)->CTX_SUFF(pVM)->enmVMState < (unsigned)VMSTATE_DESTROYING, \
728	("pVCpu=%p pVM=%p state %s\n", (pVCpu), RT_VALID_ALIGNED_PTR(pVCpu, 64) ? (pVCpu)->CTX_SUFF(pVM) : NULL, \
729	RT_VALID_ALIGNED_PTR(pVCpu, 64) && RT_VALID_ALIGNED_PTR((pVCpu)->CTX_SUFF(pVM), PAGE_SIZE) \
730	? VMGetStateName((pVCpu)->pVMR3->enmVMState) : ""), \
731	(rc))
732
733
734	/** This is the VM structure.
735	*
736	* It contains (nearly?) all the VM data which have to be available in all
737	* contexts. Even if it contains all the data the idea is to use APIs not
738	* to modify all the members all around the place. Therefore we make use of
739	* unions to hide everything which isn't local to the current source module.
740	* This means we'll have to pay a little bit of attention when adding new
741	* members to structures in the unions and make sure to keep the padding sizes
742	* up to date.
743	*
744	* Run tstVMStructSize after update!
745	*/
746	typedef struct VM
747	{
748	/** The state of the VM.
749	* This field is read only to everyone except the VM and EM. */
750	VMSTATE volatile enmVMState;
751	/** Forced action flags.
752	* See the VM_FF_* \#defines. Updated atomically.
753	*/
754	volatile uint32_t fGlobalForcedActions;
755	/** Pointer to the array of page descriptors for the VM structure allocation. */
756	R3PTRTYPE(PSUPPAGE) paVMPagesR3;
757	/** Session handle. For use when calling SUPR0 APIs. */
758	PSUPDRVSESSION pSession;
759	/** Pointer to the ring-3 VM structure. */
760	PUVM pUVM;
761	/** Ring-3 Host Context VM Pointer. */
762	R3PTRTYPE(struct VM *) pVMR3;
763	/** Ring-0 Host Context VM Pointer. */
764	R0PTRTYPE(struct VM *) pVMR0;
765	/** Raw-mode Context VM Pointer. */
766	RCPTRTYPE(struct VM *) pVMRC;
767
768	/** The GVM VM handle. Only the GVM should modify this field. */
769	uint32_t hSelf;
770	/** Number of virtual CPUs. */
771	uint32_t cCpus;
772	/** CPU excution cap (1-100) */
773	uint32_t uCpuExecutionCap;
774
775	/** Size of the VM structure including the VMCPU array. */
776	uint32_t cbSelf;
777
778	/** Offset to the VMCPU array starting from beginning of this structure. */
779	uint32_t offVMCPU;
780
781	/** Reserved; alignment. */
782	uint32_t u32Reserved[5];
783
784	/** @name Public VMM Switcher APIs
785	* @{ */
786	/**
787	* Assembly switch entry point for returning to host context.
788	* This function will clean up the stack frame.
789	*
790	* @param eax The return code, register.
791	* @param Ctx The guest core context.
792	* @remark Assume interrupts disabled.
793	*/
794	RTRCPTR pfnVMMGCGuestToHostAsmGuestCtx/(int32_t eax, CPUMCTXCORE Ctx)/;
795
796	/**
797	* Assembly switch entry point for returning to host context.
798	*
799	* This is an alternative entry point which we'll be using when the we have the
800	* hypervisor context and need to save that before going to the host.
801	*
802	* This is typically useful when abandoning the hypervisor because of a trap
803	* and want the trap state to be saved.
804	*
805	* @param eax The return code, register.
806	* @param ecx Pointer to the hypervisor core context, register.
807	* @remark Assume interrupts disabled.
808	*/
809	RTRCPTR pfnVMMGCGuestToHostAsmHyperCtx/(int32_t eax, PCPUMCTXCORE ecx)/;
810
811	/**
812	* Assembly switch entry point for returning to host context.
813	*
814	* This is an alternative to the two *Ctx APIs and implies that the context has already
815	* been saved, or that it's just a brief return to HC and that the caller intends to resume
816	* whatever it is doing upon 'return' from this call.
817	*
818	* @param eax The return code, register.
819	* @remark Assume interrupts disabled.
820	*/
821	RTRCPTR pfnVMMGCGuestToHostAsm/(int32_t eax)/;
822	/** @} */
823
824
825	/** @name Various VM data owned by VM.
826	* @{ */
827	RTTHREAD uPadding1;
828	/** The native handle of ThreadEMT. Getting the native handle
829	* is generally faster than getting the IPRT one (except on OS/2 :-). */
830	RTNATIVETHREAD uPadding2;
831	/** @} */
832
833
834	/** @name Various items that are frequently accessed.
835	* @{ */
836	/** Whether to recompile user mode code or run it raw/hm. */
837	bool fRecompileUser;
838	/** Whether to recompile supervisor mode code or run it raw/hm. */
839	bool fRecompileSupervisor;
840	/** PATM enabled flag.
841	* This is placed here for performance reasons. */
842	bool fPATMEnabled;
843	/** CSAM enabled flag.
844	* This is placed here for performance reasons. */
845	bool fCSAMEnabled;
846	/** Hardware VM support is available and enabled.
847	* This is placed here for performance reasons. */
848	bool fHWACCMEnabled;
849	/** Hardware VM support is required and non-optional.
850	* This is initialized together with the rest of the VM structure. */
851	bool fHwVirtExtForced;
852	/** Set when this VM is the master FT node. */
853	bool fFaultTolerantMaster;
854	/** Large page enabled flag. */
855	bool fUseLargePages;
856	/** @} */
857
858	/** @name Debugging
859	* @{ */
860	/** Raw-mode Context VM Pointer. */
861	RCPTRTYPE(RTTRACEBUF) hTraceBufRC;
862	/** Alignment padding */
863	uint32_t uPadding3;
864	/** Ring-3 Host Context VM Pointer. */
865	R3PTRTYPE(RTTRACEBUF) hTraceBufR3;
866	/** Ring-0 Host Context VM Pointer. */
867	R0PTRTYPE(RTTRACEBUF) hTraceBufR0;
868	/** @} */
869
870	#if HC_ARCH_BITS == 32
871	/** Alignment padding.. */
872	uint32_t uPadding4;
873	#endif
874
875	/** @name Switcher statistics (remove)
876	* @{ */
877	/** Profiling the total time from Qemu to GC. */
878	STAMPROFILEADV StatTotalQemuToGC;
879	/** Profiling the total time from GC to Qemu. */
880	STAMPROFILEADV StatTotalGCToQemu;
881	/** Profiling the total time spent in GC. */
882	STAMPROFILEADV StatTotalInGC;
883	/** Profiling the total time spent not in Qemu. */
884	STAMPROFILEADV StatTotalInQemu;
885	/** Profiling the VMMSwitcher code for going to GC. */
886	STAMPROFILEADV StatSwitcherToGC;
887	/** Profiling the VMMSwitcher code for going to HC. */
888	STAMPROFILEADV StatSwitcherToHC;
889	STAMPROFILEADV StatSwitcherSaveRegs;
890	STAMPROFILEADV StatSwitcherSysEnter;
891	STAMPROFILEADV StatSwitcherDebug;
892	STAMPROFILEADV StatSwitcherCR0;
893	STAMPROFILEADV StatSwitcherCR4;
894	STAMPROFILEADV StatSwitcherJmpCR3;
895	STAMPROFILEADV StatSwitcherRstrRegs;
896	STAMPROFILEADV StatSwitcherLgdt;
897	STAMPROFILEADV StatSwitcherLidt;
898	STAMPROFILEADV StatSwitcherLldt;
899	STAMPROFILEADV StatSwitcherTSS;
900	/** @} */
901
902	#if HC_ARCH_BITS != 64
903	/** Padding - the unions must be aligned on a 64 bytes boundary and the unions
904	* must start at the same offset on both 64-bit and 32-bit hosts. */
905	uint8_t abAlignment1[HC_ARCH_BITS == 32 ? 32 : 0];
906	#endif
907
908	/** CPUM part. */
909	union
910	{
911	#ifdef ___CPUMInternal_h
912	struct CPUM s;
913	#endif
914	uint8_t padding[1536]; /* multiple of 64 */
915	} cpum;
916
917	/** VMM part. */
918	union
919	{
920	#ifdef ___VMMInternal_h
921	struct VMM s;
922	#endif
923	uint8_t padding[1600]; /* multiple of 64 */
924	} vmm;
925
926	/** PGM part. */
927	union
928	{
929	#ifdef ___PGMInternal_h
930	struct PGM s;
931	#endif
932	uint8_t padding[40962+6080]; / multiple of 64 */
933	} pgm;
934
935	/** HWACCM part. */
936	union
937	{
938	#ifdef ___HWACCMInternal_h
939	struct HWACCM s;
940	#endif
941	uint8_t padding[5376]; /* multiple of 64 */
942	} hwaccm;
943
944	/** TRPM part. */
945	union
946	{
947	#ifdef ___TRPMInternal_h
948	struct TRPM s;
949	#endif
950	uint8_t padding[5248]; /* multiple of 64 */
951	} trpm;
952
953	/** SELM part. */
954	union
955	{
956	#ifdef ___SELMInternal_h
957	struct SELM s;
958	#endif
959	uint8_t padding[576]; /* multiple of 64 */
960	} selm;
961
962	/** MM part. */
963	union
964	{
965	#ifdef ___MMInternal_h
966	struct MM s;
967	#endif
968	uint8_t padding[192]; /* multiple of 64 */
969	} mm;
970
971	/** PDM part. */
972	union
973	{
974	#ifdef ___PDMInternal_h
975	struct PDM s;
976	#endif
977	uint8_t padding[1920]; /* multiple of 64 */
978	} pdm;
979
980	/** IOM part. */
981	union
982	{
983	#ifdef ___IOMInternal_h
984	struct IOM s;
985	#endif
986	uint8_t padding[832]; /* multiple of 64 */
987	} iom;
988
989	/** PATM part. */
990	union
991	{
992	#ifdef ___PATMInternal_h
993	struct PATM s;
994	#endif
995	uint8_t padding[768]; /* multiple of 64 */
996	} patm;
997
998	/** CSAM part. */
999	union
1000	{
1001	#ifdef ___CSAMInternal_h
1002	struct CSAM s;
1003	#endif
1004	uint8_t padding[1088]; /* multiple of 64 */
1005	} csam;
1006
1007	/** EM part. */
1008	union
1009	{
1010	#ifdef ___EMInternal_h
1011	struct EM s;
1012	#endif
1013	uint8_t padding[256]; /* multiple of 64 */
1014	} em;
1015
1016	/** TM part. */
1017	union
1018	{
1019	#ifdef ___TMInternal_h
1020	struct TM s;
1021	#endif
1022	uint8_t padding[2432]; /* multiple of 64 */
1023	} tm;
1024
1025	/** DBGF part. */
1026	union
1027	{
1028	#ifdef ___DBGFInternal_h
1029	struct DBGF s;
1030	#endif
1031	uint8_t padding[2368]; /* multiple of 64 */
1032	} dbgf;
1033
1034	/** SSM part. */
1035	union
1036	{
1037	#ifdef ___SSMInternal_h
1038	struct SSM s;
1039	#endif
1040	uint8_t padding[128]; /* multiple of 64 */
1041	} ssm;
1042
1043	/** FTM part. */
1044	union
1045	{
1046	#ifdef ___FTMInternal_h
1047	struct FTM s;
1048	#endif
1049	uint8_t padding[512]; /* multiple of 64 */
1050	} ftm;
1051
1052	/** REM part. */
1053	union
1054	{
1055	#ifdef ___REMInternal_h
1056	struct REM s;
1057	#endif
1058	uint8_t padding[0x11100]; /* multiple of 64 */
1059	} rem;
1060
1061	/* ---- begin small stuff ---- */
1062
1063	/** VM part. */
1064	union
1065	{
1066	#ifdef ___VMInternal_h
1067	struct VMINT s;
1068	#endif
1069	uint8_t padding[24]; /* multiple of 8 */
1070	} vm;
1071
1072	/** CFGM part. */
1073	union
1074	{
1075	#ifdef ___CFGMInternal_h
1076	struct CFGM s;
1077	#endif
1078	uint8_t padding[8]; /* multiple of 8 */
1079	} cfgm;
1080
1081
1082	/** Padding for aligning the cpu array on a page boundary. */
1083	uint8_t abAlignment2[734];
1084
1085	/* ---- end small stuff ---- */
1086
1087	/** VMCPU array for the configured number of virtual CPUs.
1088	* Must be aligned on a page boundary for TLB hit reasons as well as
1089	* alignment of VMCPU members. */
1090	VMCPU aCpus[1];
1091	} VM;
1092
1093
1094	#ifdef IN_RC
1095	RT_C_DECLS_BEGIN
1096
1097	/** The VM structure.
1098	* This is imported from the VMMGCBuiltin module, i.e. it's a one
1099	* of those magic globals which we should avoid using.
1100	*/
1101	extern DECLIMPORT(VM) g_VM;
1102
1103	RT_C_DECLS_END
1104	#endif
1105
1106	/** @} */
1107
1108	#endif
1109

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source: vbox/trunk/include/VBox/vmm/vm.h@ 40397

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