vm.h@ 61067

Last change on this file since 61067 was 60871, checked in by vboxsync, 9 years ago
IEMAllCImplStrInstr.cpp.h: Check FFs for each page and after each INS/OUTS rep. In raw-mode, temporarily enable interrupts too.
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 49.5 KB

Line
1	/** @file
2	* VM - The Virtual Machine, data.
3	*/
4
5	/*
6	* Copyright (C) 2006-2015 Oracle Corporation
7	*
8	* This file is part of VirtualBox Open Source Edition (OSE), as
9	* available from http://www.virtualbox.org. This file is free software;
10	* you can redistribute it and/or modify it under the terms of the GNU
11	* General Public License (GPL) as published by the Free Software
12	* Foundation, in version 2 as it comes in the "COPYING" file of the
13	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15	*
16	* The contents of this file may alternatively be used under the terms
17	* of the Common Development and Distribution License Version 1.0
18	* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19	* VirtualBox OSE distribution, in which case the provisions of the
20	* CDDL are applicable instead of those of the GPL.
21	*
22	* You may elect to license modified versions of this file under the
23	* terms and conditions of either the GPL or the CDDL or both.
24	*/
25
26	#ifndef ___VBox_vmm_vm_h
27	#define ___VBox_vmm_vm_h
28
29	#ifndef VBOX_FOR_DTRACE_LIB
30	# include <iprt/param.h>
31	# include <VBox/types.h>
32	# include <VBox/vmm/cpum.h>
33	# include <VBox/vmm/stam.h>
34	# include <VBox/vmm/vmapi.h>
35	# include <VBox/vmm/vmm.h>
36	# include <VBox/sup.h>
37	#else
38	# pragma D depends_on library vbox-types.d
39	# pragma D depends_on library CPUMInternal.d
40	# define ___CPUMInternal_h
41	#endif
42
43
44
45	/** @defgroup grp_vm The Virtual Machine
46	* @ingroup grp_vmm
47	* @{
48	*/
49
50	/**
51	* The state of a Virtual CPU.
52	*
53	* The basic state indicated here is whether the CPU has been started or not. In
54	* addition, there are sub-states when started for assisting scheduling (GVMM
55	* mostly).
56	*
57	* The transition out of the STOPPED state is done by a vmR3PowerOn.
58	* The transition back to the STOPPED state is done by vmR3PowerOff.
59	*
60	* (Alternatively we could let vmR3PowerOn start CPU 0 only and let the SPIP
61	* handling switch on the other CPUs. Then vmR3Reset would stop all but CPU 0.)
62	*/
63	typedef enum VMCPUSTATE
64	{
65	/** The customary invalid zero. */
66	VMCPUSTATE_INVALID = 0,
67
68	/** Virtual CPU has not yet been started. */
69	VMCPUSTATE_STOPPED,
70
71	/** CPU started. */
72	VMCPUSTATE_STARTED,
73	/** CPU started in HM context. */
74	VMCPUSTATE_STARTED_HM,
75	/** Executing guest code and can be poked (RC or STI bits of HM). */
76	VMCPUSTATE_STARTED_EXEC,
77	/** Executing guest code in the recompiler. */
78	VMCPUSTATE_STARTED_EXEC_REM,
79	/** Halted. */
80	VMCPUSTATE_STARTED_HALTED,
81
82	/** The end of valid virtual CPU states. */
83	VMCPUSTATE_END,
84
85	/** Ensure 32-bit type. */
86	VMCPUSTATE_32BIT_HACK = 0x7fffffff
87	} VMCPUSTATE;
88
89
90	/**
91	* The cross context virtual CPU structure.
92	*
93	* Run 'kmk run-struct-tests' (from src/VBox/VMM if you like) after updating!
94	*/
95	typedef struct VMCPU
96	{
97	/** Per CPU forced action.
98	* See the VMCPU_FF_* \#defines. Updated atomically. */
99	uint32_t volatile fLocalForcedActions; /* 0 */
100	/** The CPU state. */
101	VMCPUSTATE volatile enmState; /* 4 */
102
103	/** Pointer to the ring-3 UVMCPU structure. */
104	PUVMCPU pUVCpu; /* 8 */
105	/** Ring-3 Host Context VM Pointer. */
106	PVMR3 pVMR3; /* 16 / 12 */
107	/** Ring-0 Host Context VM Pointer. */
108	PVMR0 pVMR0; /* 24 / 16 */
109	/** Raw-mode Context VM Pointer. */
110	PVMRC pVMRC; /* 32 / 20 */
111	/** The CPU ID.
112	* This is the index into the VM::aCpu array. */
113	VMCPUID idCpu; /* 36 / 24 */
114	/** The native thread handle. */
115	RTNATIVETHREAD hNativeThread; /* 40 / 28 */
116	/** The native R0 thread handle. (different from the R3 handle!) */
117	RTNATIVETHREAD hNativeThreadR0; /* 48 / 32 */
118	/** Which host CPU ID is this EMT running on.
119	* Only valid when in RC or HMR0 with scheduling disabled. */
120	RTCPUID volatile idHostCpu; /* 56 / 36 */
121	/** The CPU set index corresponding to idHostCpu, UINT32_MAX if not valid.
122	* @remarks Best to make sure iHostCpuSet shares cache line with idHostCpu! */
123	uint32_t volatile iHostCpuSet; /* 60 / 40 */
124
125	/** Trace groups enable flags. */
126	uint32_t fTraceGroups; /* 64 / 44 */
127	/** Align the structures below bit on a 64-byte boundary and make sure it starts
128	* at the same offset in both 64-bit and 32-bit builds.
129	*
130	* @remarks The alignments of the members that are larger than 48 bytes should be
131	* 64-byte for cache line reasons. structs containing small amounts of
132	* data could be lumped together at the end with a < 64 byte padding
133	* following it (to grow into and align the struct size).
134	*/
135	uint8_t abAlignment1[HC_ARCH_BITS == 64 ? 56 : 12+64];
136	/** State data for use by ad hoc profiling. */
137	uint32_t uAdHoc;
138	/** Profiling samples for use by ad hoc profiling. */
139	STAMPROFILEADV aStatAdHoc[8]; /* size: 408 = 320 /
140
141	/** HM part. */
142	union
143	{
144	#ifdef ___HMInternal_h
145	struct HMCPU s;
146	#endif
147	uint8_t padding[5760]; /* multiple of 64 */
148	} hm;
149
150	/** EM part. */
151	union
152	{
153	#ifdef ___EMInternal_h
154	struct EMCPU s;
155	#endif
156	uint8_t padding[1408]; /* multiple of 64 */
157	} em;
158
159	/** IEM part. */
160	union
161	{
162	#ifdef ___IEMInternal_h
163	struct IEMCPU s;
164	#endif
165	uint8_t padding[3072]; /* multiple of 64 */
166	} iem;
167
168	/** TRPM part. */
169	union
170	{
171	#ifdef ___TRPMInternal_h
172	struct TRPMCPU s;
173	#endif
174	uint8_t padding[128]; /* multiple of 64 */
175	} trpm;
176
177	/** TM part. */
178	union
179	{
180	#ifdef ___TMInternal_h
181	struct TMCPU s;
182	#endif
183	uint8_t padding[384]; /* multiple of 64 */
184	} tm;
185
186	/** VMM part. */
187	union
188	{
189	#ifdef ___VMMInternal_h
190	struct VMMCPU s;
191	#endif
192	uint8_t padding[704]; /* multiple of 64 */
193	} vmm;
194
195	/** PDM part. */
196	union
197	{
198	#ifdef ___PDMInternal_h
199	struct PDMCPU s;
200	#endif
201	uint8_t padding[256]; /* multiple of 64 */
202	} pdm;
203
204	/** IOM part. */
205	union
206	{
207	#ifdef ___IOMInternal_h
208	struct IOMCPU s;
209	#endif
210	uint8_t padding[512]; /* multiple of 64 */
211	} iom;
212
213	/** DBGF part.
214	* @todo Combine this with other tiny structures. */
215	union
216	{
217	#ifdef ___DBGFInternal_h
218	struct DBGFCPU s;
219	#endif
220	uint8_t padding[256]; /* multiple of 64 */
221	} dbgf;
222
223	/** GIM part. */
224	union
225	{
226	#ifdef ___GIMInternal_h
227	struct GIMCPU s;
228	#endif
229	uint8_t padding[64]; /* multiple of 64 */
230	} gim;
231
232	#ifdef VBOX_WITH_NEW_APIC
233	/** APIC part. */
234	union
235	{
236	# ifdef ___APICInternal_h
237	struct APICCPU s;
238	# endif
239	uint8_t padding[640]; /* multiple of 64 */
240	} apic;
241	#endif
242
243	/** Align the following members on page boundary. */
244	#ifdef VBOX_WITH_NEW_APIC
245	uint8_t abAlignment2[2752];
246	#else
247	uint8_t abAlignment2[3392];
248	#endif
249
250	/** PGM part. */
251	union
252	{
253	#ifdef ___PGMInternal_h
254	struct PGMCPU s;
255	#endif
256	uint8_t padding[4096]; /* multiple of 4096 */
257	} pgm;
258
259	/** CPUM part. */
260	union
261	{
262	#ifdef ___CPUMInternal_h
263	struct CPUMCPU s;
264	#endif
265	uint8_t padding[4096]; /* multiple of 4096 */
266	} cpum;
267	} VMCPU;
268
269
270	#ifndef VBOX_FOR_DTRACE_LIB
271
272	/** @name Operations on VMCPU::enmState
273	* @{ */
274	/** Gets the VMCPU state. */
275	#define VMCPU_GET_STATE(pVCpu) ( (pVCpu)->enmState )
276	/** Sets the VMCPU state. */
277	#define VMCPU_SET_STATE(pVCpu, enmNewState) \
278	ASMAtomicWriteU32((uint32_t volatile *)&(pVCpu)->enmState, (enmNewState))
279	/** Cmpares and sets the VMCPU state. */
280	#define VMCPU_CMPXCHG_STATE(pVCpu, enmNewState, enmOldState) \
281	ASMAtomicCmpXchgU32((uint32_t volatile *)&(pVCpu)->enmState, (enmNewState), (enmOldState))
282	/** Checks the VMCPU state. */
283	#ifdef VBOX_STRICT
284	# define VMCPU_ASSERT_STATE(pVCpu, enmExpectedState) \
285	do { \
286	VMCPUSTATE enmState = VMCPU_GET_STATE(pVCpu); \
287	AssertMsg(enmState == (enmExpectedState), \
288	("enmState=%d enmExpectedState=%d idCpu=%u\n", \
289	enmState, enmExpectedState, (pVCpu)->idCpu)); \
290	} while (0)
291	#else
292	# define VMCPU_ASSERT_STATE(pVCpu, enmExpectedState) do { } while (0)
293	#endif
294	/** Tests if the state means that the CPU is started. */
295	#define VMCPUSTATE_IS_STARTED(enmState) ( (enmState) > VMCPUSTATE_STOPPED )
296	/** Tests if the state means that the CPU is stopped. */
297	#define VMCPUSTATE_IS_STOPPED(enmState) ( (enmState) == VMCPUSTATE_STOPPED )
298	/** @} */
299
300
301	/** The name of the raw-mode context VMM Core module. */
302	#define VMMRC_MAIN_MODULE_NAME "VMMRC.rc"
303	/** The name of the ring-0 context VMM Core module. */
304	#define VMMR0_MAIN_MODULE_NAME "VMMR0.r0"
305
306	/**
307	* Wrapper macro for avoiding too much \#ifdef VBOX_WITH_RAW_MODE.
308	*/
309	#ifdef VBOX_WITH_RAW_MODE
310	# define VM_WHEN_RAW_MODE(a_WithExpr, a_WithoutExpr) a_WithExpr
311	#else
312	# define VM_WHEN_RAW_MODE(a_WithExpr, a_WithoutExpr) a_WithoutExpr
313	#endif
314
315
316	/** VM Forced Action Flags.
317	*
318	* Use the VM_FF_SET() and VM_FF_CLEAR() macros to change the force
319	* action mask of a VM.
320	*
321	* Available VM bits:
322	* 0, 1, 5, 6, 7, 13, 14, 15, 16, 17, 21, 22, 23, 24, 25, 26, 27, 28, 30
323	*
324	*
325	* Available VMCPU bits:
326	* 10, 11, 14, 15, 30, 31
327	*
328	* @todo If we run low on VMCPU, we may consider merging the SELM bits
329	*
330	* @{
331	*/
332	/** The virtual sync clock has been stopped, go to TM until it has been
333	* restarted... */
334	#define VM_FF_TM_VIRTUAL_SYNC RT_BIT_32(2)
335	/** PDM Queues are pending. */
336	#define VM_FF_PDM_QUEUES RT_BIT_32(VM_FF_PDM_QUEUES_BIT)
337	/** The bit number for VM_FF_PDM_QUEUES. */
338	#define VM_FF_PDM_QUEUES_BIT 3
339	/** PDM DMA transfers are pending. */
340	#define VM_FF_PDM_DMA RT_BIT_32(VM_FF_PDM_DMA_BIT)
341	/** The bit number for VM_FF_PDM_DMA. */
342	#define VM_FF_PDM_DMA_BIT 4
343	/** This action forces the VM to call DBGF so DBGF can service debugger
344	* requests in the emulation thread.
345	* This action flag stays asserted till DBGF clears it.*/
346	#define VM_FF_DBGF RT_BIT_32(VM_FF_DBGF_BIT)
347	/** The bit number for VM_FF_DBGF. */
348	#define VM_FF_DBGF_BIT 8
349	/** This action forces the VM to service pending requests from other
350	* thread or requests which must be executed in another context. */
351	#define VM_FF_REQUEST RT_BIT_32(9)
352	/** Check for VM state changes and take appropriate action. */
353	#define VM_FF_CHECK_VM_STATE RT_BIT_32(VM_FF_CHECK_VM_STATE_BIT)
354	/** The bit number for VM_FF_CHECK_VM_STATE. */
355	#define VM_FF_CHECK_VM_STATE_BIT 10
356	/** Reset the VM. (postponed) */
357	#define VM_FF_RESET RT_BIT_32(VM_FF_RESET_BIT)
358	/** The bit number for VM_FF_RESET. */
359	#define VM_FF_RESET_BIT 11
360	/** EMT rendezvous in VMM. */
361	#define VM_FF_EMT_RENDEZVOUS RT_BIT_32(VM_FF_EMT_RENDEZVOUS_BIT)
362	/** The bit number for VM_FF_EMT_RENDEZVOUS. */
363	#define VM_FF_EMT_RENDEZVOUS_BIT 12
364
365	/** PGM needs to allocate handy pages. */
366	#define VM_FF_PGM_NEED_HANDY_PAGES RT_BIT_32(18)
367	/** PGM is out of memory.
368	* Abandon all loops and code paths which can be resumed and get up to the EM
369	* loops. */
370	#define VM_FF_PGM_NO_MEMORY RT_BIT_32(19)
371	/** PGM is about to perform a lightweight pool flush
372	* Guest SMP: all EMT threads should return to ring 3
373	*/
374	#define VM_FF_PGM_POOL_FLUSH_PENDING RT_BIT_32(20)
375	/** REM needs to be informed about handler changes. */
376	#define VM_FF_REM_HANDLER_NOTIFY RT_BIT_32(VM_FF_REM_HANDLER_NOTIFY_BIT)
377	/** The bit number for VM_FF_REM_HANDLER_NOTIFY. */
378	#define VM_FF_REM_HANDLER_NOTIFY_BIT 29
379	/** Suspend the VM - debug only. */
380	#define VM_FF_DEBUG_SUSPEND RT_BIT_32(31)
381
382
383	/** This action forces the VM to check any pending interrupts on the APIC. */
384	#define VMCPU_FF_INTERRUPT_APIC RT_BIT_32(0)
385	/** This action forces the VM to check any pending interrups on the PIC. */
386	#define VMCPU_FF_INTERRUPT_PIC RT_BIT_32(1)
387	/** This action forces the VM to schedule and run pending timer (TM).
388	* @remarks Don't move - PATM compatibility. */
389	#define VMCPU_FF_TIMER RT_BIT_32(2)
390	/** This action forces the VM to check any pending NMIs. */
391	#define VMCPU_FF_INTERRUPT_NMI_BIT 3
392	#define VMCPU_FF_INTERRUPT_NMI RT_BIT_32(VMCPU_FF_INTERRUPT_NMI_BIT)
393	/** This action forces the VM to check any pending SMIs. */
394	#define VMCPU_FF_INTERRUPT_SMI_BIT 4
395	#define VMCPU_FF_INTERRUPT_SMI RT_BIT_32(VMCPU_FF_INTERRUPT_SMI_BIT)
396	/** PDM critical section unlocking is pending, process promptly upon return to R3. */
397	#define VMCPU_FF_PDM_CRITSECT RT_BIT_32(5)
398	/** This action forces the VCPU out of the halted state. */
399	#define VMCPU_FF_UNHALT RT_BIT_32(6)
400	/** Pending IEM action (bit number). */
401	#define VMCPU_FF_IEM_BIT 7
402	/** Pending IEM action (mask). */
403	#define VMCPU_FF_IEM RT_BIT_32(VMCPU_FF_IEM_BIT)
404	/** Pending APIC action (bit number). */
405	#define VMCPU_FF_UPDATE_APIC_BIT 8
406	/** This action forces the VM to update APIC's asynchronously arrived
407	* interrupts as pending interrupts. */
408	#define VMCPU_FF_UPDATE_APIC RT_BIT_32(VMCPU_FF_UPDATE_APIC_BIT)
409
410	/** This action forces the VM to service pending requests from other
411	* thread or requests which must be executed in another context. */
412	#define VMCPU_FF_REQUEST RT_BIT_32(9)
413	/** This action forces the VM to service any pending updates to CR3 (used only
414	* by HM). */
415	#define VMCPU_FF_HM_UPDATE_CR3 RT_BIT_32(12)
416	/** This action forces the VM to service any pending updates to PAE PDPEs (used
417	* only by HM). */
418	#define VMCPU_FF_HM_UPDATE_PAE_PDPES RT_BIT_32(13)
419	/** This action forces the VM to resync the page tables before going
420	* back to execute guest code. (GLOBAL FLUSH) */
421	#define VMCPU_FF_PGM_SYNC_CR3 RT_BIT_32(16)
422	/** Same as VM_FF_PGM_SYNC_CR3 except that global pages can be skipped.
423	* (NON-GLOBAL FLUSH) */
424	#define VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL RT_BIT_32(17)
425	/** Check for pending TLB shootdown actions (deprecated)
426	* Reserved for furture HM re-use if necessary / safe.
427	* Consumer: HM */
428	#define VMCPU_FF_TLB_SHOOTDOWN_UNUSED RT_BIT_32(18)
429	/** Check for pending TLB flush action.
430	* Consumer: HM
431	* @todo rename to VMCPU_FF_HM_TLB_FLUSH */
432	#define VMCPU_FF_TLB_FLUSH RT_BIT_32(VMCPU_FF_TLB_FLUSH_BIT)
433	/** The bit number for VMCPU_FF_TLB_FLUSH. */
434	#define VMCPU_FF_TLB_FLUSH_BIT 19
435	#ifdef VBOX_WITH_RAW_MODE
436	/** Check the interrupt and trap gates */
437	# define VMCPU_FF_TRPM_SYNC_IDT RT_BIT_32(20)
438	/** Check Guest's TSS ring 0 stack */
439	# define VMCPU_FF_SELM_SYNC_TSS RT_BIT_32(21)
440	/** Check Guest's GDT table */
441	# define VMCPU_FF_SELM_SYNC_GDT RT_BIT_32(22)
442	/** Check Guest's LDT table */
443	# define VMCPU_FF_SELM_SYNC_LDT RT_BIT_32(23)
444	#endif /* VBOX_WITH_RAW_MODE */
445	/** Inhibit interrupts pending. See EMGetInhibitInterruptsPC(). */
446	#define VMCPU_FF_INHIBIT_INTERRUPTS RT_BIT_32(24)
447	/** Block injection of non-maskable interrupts to the guest. */
448	#define VMCPU_FF_BLOCK_NMIS RT_BIT_32(25)
449	#ifdef VBOX_WITH_RAW_MODE
450	/** CSAM needs to scan the page that's being executed */
451	# define VMCPU_FF_CSAM_SCAN_PAGE RT_BIT_32(26)
452	/** CSAM needs to do some homework. */
453	# define VMCPU_FF_CSAM_PENDING_ACTION RT_BIT_32(27)
454	#endif /* VBOX_WITH_RAW_MODE */
455	/** Force return to Ring-3. */
456	#define VMCPU_FF_TO_R3 RT_BIT_32(28)
457	/** Force return to ring-3 to service pending I/O or MMIO write.
458	* This is a backup for mechanism VINF_IOM_R3_IOPORT_COMMIT_WRITE and
459	* VINF_IOM_R3_MMIO_COMMIT_WRITE, allowing VINF_EM_DBG_BREAKPOINT and similar
460	* status codes to be propagated at the same time without loss. */
461	#define VMCPU_FF_IOM RT_BIT_32(29)
462
463	/** Externally VM forced actions. Used to quit the idle/wait loop. */
464	#define VM_FF_EXTERNAL_SUSPENDED_MASK (VM_FF_CHECK_VM_STATE \| VM_FF_DBGF \| VM_FF_REQUEST \| VM_FF_EMT_RENDEZVOUS)
465	/** Externally VMCPU forced actions. Used to quit the idle/wait loop. */
466	#define VMCPU_FF_EXTERNAL_SUSPENDED_MASK (VMCPU_FF_REQUEST)
467
468	/** Externally forced VM actions. Used to quit the idle/wait loop. */
469	#define VM_FF_EXTERNAL_HALTED_MASK ( VM_FF_CHECK_VM_STATE \| VM_FF_DBGF \| VM_FF_REQUEST \
470	\| VM_FF_PDM_QUEUES \| VM_FF_PDM_DMA \| VM_FF_EMT_RENDEZVOUS)
471	/** Externally forced VMCPU actions. Used to quit the idle/wait loop. */
472	#define VMCPU_FF_EXTERNAL_HALTED_MASK ( VMCPU_FF_UPDATE_APIC \| VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC \
473	\| VMCPU_FF_REQUEST \| VMCPU_FF_INTERRUPT_NMI \| VMCPU_FF_INTERRUPT_SMI \
474	\| VMCPU_FF_UNHALT \| VMCPU_FF_TIMER)
475
476	/** High priority VM pre-execution actions. */
477	#define VM_FF_HIGH_PRIORITY_PRE_MASK ( VM_FF_CHECK_VM_STATE \| VM_FF_DBGF \| VM_FF_TM_VIRTUAL_SYNC \
478	\| VM_FF_DEBUG_SUSPEND \| VM_FF_PGM_NEED_HANDY_PAGES \| VM_FF_PGM_NO_MEMORY \
479	\| VM_FF_EMT_RENDEZVOUS)
480	/** High priority VMCPU pre-execution actions. */
481	#define VMCPU_FF_HIGH_PRIORITY_PRE_MASK ( VMCPU_FF_TIMER \| VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC \
482	\| VMCPU_FF_UPDATE_APIC \
483	\| VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL \
484	\| VMCPU_FF_INHIBIT_INTERRUPTS \
485	\| VM_WHEN_RAW_MODE( VMCPU_FF_SELM_SYNC_TSS \| VMCPU_FF_TRPM_SYNC_IDT \
486	\| VMCPU_FF_SELM_SYNC_GDT \| VMCPU_FF_SELM_SYNC_LDT, 0 ) )
487
488	/** High priority VM pre raw-mode execution mask. */
489	#define VM_FF_HIGH_PRIORITY_PRE_RAW_MASK (VM_FF_PGM_NEED_HANDY_PAGES \| VM_FF_PGM_NO_MEMORY)
490	/** High priority VMCPU pre raw-mode execution mask. */
491	#define VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK ( VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL \
492	\| VMCPU_FF_INHIBIT_INTERRUPTS \
493	\| VM_WHEN_RAW_MODE( VMCPU_FF_SELM_SYNC_TSS \| VMCPU_FF_TRPM_SYNC_IDT \
494	\| VMCPU_FF_SELM_SYNC_GDT \| VMCPU_FF_SELM_SYNC_LDT, 0) )
495
496	/** High priority post-execution actions. */
497	#define VM_FF_HIGH_PRIORITY_POST_MASK (VM_FF_PGM_NO_MEMORY)
498	/** High priority post-execution actions. */
499	#define VMCPU_FF_HIGH_PRIORITY_POST_MASK ( VMCPU_FF_PDM_CRITSECT \| VM_WHEN_RAW_MODE(VMCPU_FF_CSAM_PENDING_ACTION, 0) \
500	\| VMCPU_FF_HM_UPDATE_CR3 \| VMCPU_FF_HM_UPDATE_PAE_PDPES \
501	\| VMCPU_FF_IEM \| VMCPU_FF_IOM )
502
503	/** Normal priority VM post-execution actions. */
504	#define VM_FF_NORMAL_PRIORITY_POST_MASK ( VM_FF_CHECK_VM_STATE \| VM_FF_DBGF \| VM_FF_RESET \
505	\| VM_FF_PGM_NO_MEMORY \| VM_FF_EMT_RENDEZVOUS)
506	/** Normal priority VMCPU post-execution actions. */
507	#define VMCPU_FF_NORMAL_PRIORITY_POST_MASK VM_WHEN_RAW_MODE(VMCPU_FF_CSAM_SCAN_PAGE, 0)
508
509	/** Normal priority VM actions. */
510	#define VM_FF_NORMAL_PRIORITY_MASK ( VM_FF_REQUEST \| VM_FF_PDM_QUEUES \| VM_FF_PDM_DMA \| VM_FF_REM_HANDLER_NOTIFY \
511	\| VM_FF_EMT_RENDEZVOUS)
512	/** Normal priority VMCPU actions. */
513	#define VMCPU_FF_NORMAL_PRIORITY_MASK (VMCPU_FF_REQUEST \| VMCPU_FF_UNHALT)
514
515	/** Flags to clear before resuming guest execution. */
516	#define VMCPU_FF_RESUME_GUEST_MASK (VMCPU_FF_TO_R3)
517
518
519	/** VM flags that cause the REP[\|NE\|E] STRINS loops to yield immediately. */
520	#define VM_FF_HIGH_PRIORITY_POST_REPSTR_MASK ( VM_FF_TM_VIRTUAL_SYNC \| VM_FF_PGM_NEED_HANDY_PAGES \| VM_FF_PGM_NO_MEMORY \
521	\| VM_FF_EMT_RENDEZVOUS \| VM_FF_RESET \| VM_FF_PGM_POOL_FLUSH_PENDING )
522	/** VM flags that cause the REP[\|NE\|E] STRINS loops to yield. */
523	#define VM_FF_YIELD_REPSTR_MASK ( VM_FF_HIGH_PRIORITY_POST_REPSTR_MASK \
524	\| VM_FF_PDM_QUEUES \| VM_FF_PDM_DMA \| VM_FF_DBGF \| VM_FF_DEBUG_SUSPEND )
525	/** VMCPU flags that cause the REP[\|NE\|E] STRINS loops to yield immediately. */
526	#ifdef IN_RING3
527	# define VMCPU_FF_HIGH_PRIORITY_POST_REPSTR_MASK ( VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL )
528	#else
529	# define VMCPU_FF_HIGH_PRIORITY_POST_REPSTR_MASK ( VMCPU_FF_TO_R3 \| VMCPU_FF_IEM \| VMCPU_FF_IOM \| VMCPU_FF_PGM_SYNC_CR3 \
530	\| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL )
531	#endif
532	/** VMCPU flags that cause the REP[\|NE\|E] STRINS loops to yield, interrupts
533	* enabled. */
534	#define VMCPU_FF_YIELD_REPSTR_MASK ( VMCPU_FF_HIGH_PRIORITY_POST_REPSTR_MASK \
535	\| VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_UPDATE_APIC \| VMCPU_FF_INTERRUPT_PIC \
536	\| VMCPU_FF_INTERRUPT_NMI \| VMCPU_FF_INTERRUPT_SMI \| VMCPU_FF_PDM_CRITSECT \
537	\| VMCPU_FF_TIMER \| VMCPU_FF_REQUEST )
538	/** VMCPU flags that cause the REP[\|NE\|E] STRINS loops to yield, interrupts
539	* disabled. */
540	#define VMCPU_FF_YIELD_REPSTR_NOINT_MASK ( VMCPU_FF_YIELD_REPSTR_MASK \
541	& ~(VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_UPDATE_APIC \| VMCPU_FF_INTERRUPT_PIC) )
542
543	/** VM Flags that cause the HM loops to go back to ring-3. */
544	#define VM_FF_HM_TO_R3_MASK ( VM_FF_TM_VIRTUAL_SYNC \| VM_FF_PGM_NEED_HANDY_PAGES \| VM_FF_PGM_NO_MEMORY \
545	\| VM_FF_PDM_QUEUES \| VM_FF_EMT_RENDEZVOUS)
546	/** VMCPU Flags that cause the HM loops to go back to ring-3. */
547	#define VMCPU_FF_HM_TO_R3_MASK ( VMCPU_FF_TO_R3 \| VMCPU_FF_TIMER \| VMCPU_FF_PDM_CRITSECT \
548	\| VMCPU_FF_IEM \| VMCPU_FF_IOM)
549
550	/** High priority ring-0 VM pre HM-mode execution mask. */
551	#define VM_FF_HP_R0_PRE_HM_MASK (VM_FF_HM_TO_R3_MASK \| VM_FF_REQUEST \| VM_FF_PGM_POOL_FLUSH_PENDING \| VM_FF_PDM_DMA)
552	/** High priority ring-0 VMCPU pre HM-mode execution mask. */
553	#define VMCPU_FF_HP_R0_PRE_HM_MASK ( VMCPU_FF_HM_TO_R3_MASK \| VMCPU_FF_PGM_SYNC_CR3 \
554	\| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL \| VMCPU_FF_REQUEST)
555	/** High priority ring-0 VM pre HM-mode execution mask, single stepping. */
556	#define VM_FF_HP_R0_PRE_HM_STEP_MASK (VM_FF_HP_R0_PRE_HM_MASK & ~( VM_FF_TM_VIRTUAL_SYNC \| VM_FF_PDM_QUEUES \
557	\| VM_FF_EMT_RENDEZVOUS \| VM_FF_REQUEST \
558	\| VM_FF_PDM_DMA) )
559	/** High priority ring-0 VMCPU pre HM-mode execution mask, single stepping. */
560	#define VMCPU_FF_HP_R0_PRE_HM_STEP_MASK (VMCPU_FF_HP_R0_PRE_HM_MASK & ~( VMCPU_FF_TO_R3 \| VMCPU_FF_TIMER \
561	\| VMCPU_FF_PDM_CRITSECT \| VMCPU_FF_REQUEST) )
562
563	/** All the forced VM flags. */
564	#define VM_FF_ALL_MASK (~0U)
565	/** All the forced VMCPU flags. */
566	#define VMCPU_FF_ALL_MASK (~0U)
567
568	/** All the forced VM flags except those related to raw-mode and hardware
569	* assisted execution. */
570	#define VM_FF_ALL_REM_MASK (~(VM_FF_HIGH_PRIORITY_PRE_RAW_MASK) \| VM_FF_PGM_NO_MEMORY)
571	/** All the forced VMCPU flags except those related to raw-mode and hardware
572	* assisted execution. */
573	#define VMCPU_FF_ALL_REM_MASK (~( VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK \| VMCPU_FF_PDM_CRITSECT \
574	\| VMCPU_FF_TLB_FLUSH \| VM_WHEN_RAW_MODE(VMCPU_FF_CSAM_PENDING_ACTION, 0) ))
575	/** @} */
576
577	/** @def VM_FF_SET
578	* Sets a force action flag.
579	*
580	* @param pVM The cross context VM structure.
581	* @param fFlag The flag to set.
582	*/
583	#if 1
584	# define VM_FF_SET(pVM, fFlag) ASMAtomicOrU32(&(pVM)->fGlobalForcedActions, (fFlag))
585	#else
586	# define VM_FF_SET(pVM, fFlag) \
587	do { ASMAtomicOrU32(&(pVM)->fGlobalForcedActions, (fFlag)); \
588	RTLogPrintf("VM_FF_SET : %08x %s - %s(%d) %s\n", (pVM)->fGlobalForcedActions, #fFlag, __FILE__, __LINE__, __FUNCTION__); \
589	} while (0)
590	#endif
591
592	/** @def VMCPU_FF_SET
593	* Sets a force action flag for the given VCPU.
594	*
595	* @param pVCpu The cross context virtual CPU structure.
596	* @param fFlag The flag to set.
597	*/
598	#define VMCPU_FF_SET(pVCpu, fFlag) ASMAtomicOrU32(&(pVCpu)->fLocalForcedActions, (fFlag))
599
600	/** @def VM_FF_CLEAR
601	* Clears a force action flag.
602	*
603	* @param pVM The cross context VM structure.
604	* @param fFlag The flag to clear.
605	*/
606	#if 1
607	# define VM_FF_CLEAR(pVM, fFlag) ASMAtomicAndU32(&(pVM)->fGlobalForcedActions, ~(fFlag))
608	#else
609	# define VM_FF_CLEAR(pVM, fFlag) \
610	do { ASMAtomicAndU32(&(pVM)->fGlobalForcedActions, ~(fFlag)); \
611	RTLogPrintf("VM_FF_CLEAR: %08x %s - %s(%d) %s\n", (pVM)->fGlobalForcedActions, #fFlag, __FILE__, __LINE__, __FUNCTION__); \
612	} while (0)
613	#endif
614
615	/** @def VMCPU_FF_CLEAR
616	* Clears a force action flag for the given VCPU.
617	*
618	* @param pVCpu The cross context virtual CPU structure.
619	* @param fFlag The flag to clear.
620	*/
621	#define VMCPU_FF_CLEAR(pVCpu, fFlag) ASMAtomicAndU32(&(pVCpu)->fLocalForcedActions, ~(fFlag))
622
623	/** @def VM_FF_IS_SET
624	* Checks if a force action flag is set.
625	*
626	* @param pVM The cross context VM structure.
627	* @param fFlag The flag to check.
628	*/
629	#define VM_FF_IS_SET(pVM, fFlag) (((pVM)->fGlobalForcedActions & (fFlag)) == (fFlag))
630
631	/** @def VMCPU_FF_IS_SET
632	* Checks if a force action flag is set for the given VCPU.
633	*
634	* @param pVCpu The cross context virtual CPU structure.
635	* @param fFlag The flag to check.
636	*/
637	#define VMCPU_FF_IS_SET(pVCpu, fFlag) (((pVCpu)->fLocalForcedActions & (fFlag)) == (fFlag))
638
639	/** @def VM_FF_IS_PENDING
640	* Checks if one or more force action in the specified set is pending.
641	*
642	* @param pVM The cross context VM structure.
643	* @param fFlags The flags to check for.
644	*/
645	#define VM_FF_IS_PENDING(pVM, fFlags) RT_BOOL((pVM)->fGlobalForcedActions & (fFlags))
646
647	/** @def VM_FF_TEST_AND_CLEAR
648	* Checks if one (!) force action in the specified set is pending and clears it atomically
649	*
650	* @returns true if the bit was set.
651	* @returns false if the bit was clear.
652	* @param pVM The cross context VM structure.
653	* @param iBit Bit position to check and clear
654	*/
655	#define VM_FF_TEST_AND_CLEAR(pVM, iBit) (ASMAtomicBitTestAndClear(&(pVM)->fGlobalForcedActions, iBit##_BIT))
656
657	/** @def VMCPU_FF_TEST_AND_CLEAR
658	* Checks if one (!) force action in the specified set is pending and clears it atomically
659	*
660	* @returns true if the bit was set.
661	* @returns false if the bit was clear.
662	* @param pVCpu The cross context virtual CPU structure.
663	* @param iBit Bit position to check and clear
664	*/
665	#define VMCPU_FF_TEST_AND_CLEAR(pVCpu, iBit) (ASMAtomicBitTestAndClear(&(pVCpu)->fLocalForcedActions, iBit##_BIT))
666
667	/** @def VMCPU_FF_IS_PENDING
668	* Checks if one or more force action in the specified set is pending for the given VCPU.
669	*
670	* @param pVCpu The cross context virtual CPU structure.
671	* @param fFlags The flags to check for.
672	*/
673	#define VMCPU_FF_IS_PENDING(pVCpu, fFlags) RT_BOOL((pVCpu)->fLocalForcedActions & (fFlags))
674
675	/** @def VM_FF_IS_PENDING_EXCEPT
676	* Checks if one or more force action in the specified set is pending while one
677	* or more other ones are not.
678	*
679	* @param pVM The cross context VM structure.
680	* @param fFlags The flags to check for.
681	* @param fExcpt The flags that should not be set.
682	*/
683	#define VM_FF_IS_PENDING_EXCEPT(pVM, fFlags, fExcpt) ( ((pVM)->fGlobalForcedActions & (fFlags)) && !((pVM)->fGlobalForcedActions & (fExcpt)) )
684
685	/** @def VMCPU_FF_IS_PENDING_EXCEPT
686	* Checks if one or more force action in the specified set is pending for the given
687	* VCPU while one or more other ones are not.
688	*
689	* @param pVCpu The cross context virtual CPU structure.
690	* @param fFlags The flags to check for.
691	* @param fExcpt The flags that should not be set.
692	*/
693	#define VMCPU_FF_IS_PENDING_EXCEPT(pVCpu, fFlags, fExcpt) ( ((pVCpu)->fLocalForcedActions & (fFlags)) && !((pVCpu)->fLocalForcedActions & (fExcpt)) )
694
695	/** @def VM_IS_EMT
696	* Checks if the current thread is the emulation thread (EMT).
697	*
698	* @remark The ring-0 variation will need attention if we expand the ring-0
699	* code to let threads other than EMT mess around with the VM.
700	*/
701	#ifdef IN_RC
702	# define VM_IS_EMT(pVM) true
703	#else
704	# define VM_IS_EMT(pVM) (VMMGetCpu(pVM) != NULL)
705	#endif
706
707	/** @def VMCPU_IS_EMT
708	* Checks if the current thread is the emulation thread (EMT) for the specified
709	* virtual CPU.
710	*/
711	#ifdef IN_RC
712	# define VMCPU_IS_EMT(pVCpu) true
713	#else
714	# define VMCPU_IS_EMT(pVCpu) ((pVCpu) && ((pVCpu) == VMMGetCpu((pVCpu)->CTX_SUFF(pVM))))
715	#endif
716
717	/** @def VM_ASSERT_EMT
718	* Asserts that the current thread IS the emulation thread (EMT).
719	*/
720	#ifdef IN_RC
721	# define VM_ASSERT_EMT(pVM) Assert(VM_IS_EMT(pVM))
722	#elif defined(IN_RING0)
723	# define VM_ASSERT_EMT(pVM) Assert(VM_IS_EMT(pVM))
724	#else
725	# define VM_ASSERT_EMT(pVM) \
726	AssertMsg(VM_IS_EMT(pVM), \
727	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd\n", RTThreadNativeSelf(), VMR3GetVMCPUNativeThread(pVM)))
728	#endif
729
730	/** @def VMCPU_ASSERT_EMT
731	* Asserts that the current thread IS the emulation thread (EMT) of the
732	* specified virtual CPU.
733	*/
734	#ifdef IN_RC
735	# define VMCPU_ASSERT_EMT(pVCpu) Assert(VMCPU_IS_EMT(pVCpu))
736	#elif defined(IN_RING0)
737	# define VMCPU_ASSERT_EMT(pVCpu) AssertMsg(VMCPU_IS_EMT(pVCpu), \
738	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd idCpu=%u\n", \
739	RTThreadNativeSelf(), (pVCpu) ? (pVCpu)->hNativeThreadR0 : 0, \
740	(pVCpu) ? (pVCpu)->idCpu : 0))
741	#else
742	# define VMCPU_ASSERT_EMT(pVCpu) AssertMsg(VMCPU_IS_EMT(pVCpu), \
743	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd idCpu=%#x\n", \
744	RTThreadNativeSelf(), (pVCpu)->hNativeThread, (pVCpu)->idCpu))
745	#endif
746
747	/** @def VM_ASSERT_EMT_RETURN
748	* Asserts that the current thread IS the emulation thread (EMT) and returns if it isn't.
749	*/
750	#ifdef IN_RC
751	# define VM_ASSERT_EMT_RETURN(pVM, rc) AssertReturn(VM_IS_EMT(pVM), (rc))
752	#elif defined(IN_RING0)
753	# define VM_ASSERT_EMT_RETURN(pVM, rc) AssertReturn(VM_IS_EMT(pVM), (rc))
754	#else
755	# define VM_ASSERT_EMT_RETURN(pVM, rc) \
756	AssertMsgReturn(VM_IS_EMT(pVM), \
757	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd\n", RTThreadNativeSelf(), VMR3GetVMCPUNativeThread(pVM)), \
758	(rc))
759	#endif
760
761	/** @def VMCPU_ASSERT_EMT_RETURN
762	* Asserts that the current thread IS the emulation thread (EMT) and returns if it isn't.
763	*/
764	#ifdef IN_RC
765	# define VMCPU_ASSERT_EMT_RETURN(pVCpu, rc) AssertReturn(VMCPU_IS_EMT(pVCpu), (rc))
766	#elif defined(IN_RING0)
767	# define VMCPU_ASSERT_EMT_RETURN(pVCpu, rc) AssertReturn(VMCPU_IS_EMT(pVCpu), (rc))
768	#else
769	# define VMCPU_ASSERT_EMT_RETURN(pVCpu, rc) \
770	AssertMsgReturn(VMCPU_IS_EMT(pVCpu), \
771	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd idCpu=%#x\n", \
772	RTThreadNativeSelf(), (pVCpu)->hNativeThread, (pVCpu)->idCpu), \
773	(rc))
774	#endif
775
776	/** @def VMCPU_ASSERT_EMT_OR_GURU
777	* Asserts that the current thread IS the emulation thread (EMT) of the
778	* specified virtual CPU.
779	*/
780	#if defined(IN_RC) \|\| defined(IN_RING0)
781	# define VMCPU_ASSERT_EMT_OR_GURU(pVCpu) Assert( VMCPU_IS_EMT(pVCpu) \
782	\|\| pVCpu->CTX_SUFF(pVM)->enmVMState == VMSTATE_GURU_MEDITATION \
783	\|\| pVCpu->CTX_SUFF(pVM)->enmVMState == VMSTATE_GURU_MEDITATION_LS )
784	#else
785	# define VMCPU_ASSERT_EMT_OR_GURU(pVCpu) \
786	AssertMsg( VMCPU_IS_EMT(pVCpu) \
787	\|\| pVCpu->CTX_SUFF(pVM)->enmVMState == VMSTATE_GURU_MEDITATION \
788	\|\| pVCpu->CTX_SUFF(pVM)->enmVMState == VMSTATE_GURU_MEDITATION_LS, \
789	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd idCpu=%#x\n", \
790	RTThreadNativeSelf(), (pVCpu)->hNativeThread, (pVCpu)->idCpu))
791	#endif
792
793	/** @def VMCPU_ASSERT_EMT_OR_NOT_RUNNING
794	* Asserts that the current thread IS the emulation thread (EMT) of the
795	* specified virtual CPU or the VM is not running.
796	*/
797	#if defined(IN_RC) \|\| defined(IN_RING0)
798	# define VMCPU_ASSERT_EMT_OR_NOT_RUNNING(pVCpu) \
799	Assert( VMCPU_IS_EMT(pVCpu) \
800	\|\| !VM_IS_RUNNING((pVCpu)->CTX_SUFF(pVM)) )
801	#else
802	# define VMCPU_ASSERT_EMT_OR_NOT_RUNNING(pVCpu) \
803	AssertMsg( VMCPU_IS_EMT(pVCpu) \
804	\|\| !VM_IS_RUNNING((pVCpu)->CTX_SUFF(pVM)), \
805	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd idCpu=%#x\n", \
806	RTThreadNativeSelf(), (pVCpu)->hNativeThread, (pVCpu)->idCpu))
807	#endif
808
809	/** @def VM_IS_RUNNING
810	* Checks if the the VM is running.
811	*/
812	#define VM_IS_RUNNING(pVM) ( (pVM)->enmVMState == VMSTATE_RUNNING \
813	\|\| (pVM)->enmVMState == VMSTATE_RUNNING_LS \
814	\|\| (pVM)->enmVMState == VMSTATE_RUNNING_FT)
815
816	/** @def VM_ASSERT_IS_NOT_RUNNING
817	* Asserts that the VM is not running.
818	*/
819	#if defined(IN_RC) \|\| defined(IN_RING0)
820	#define VM_ASSERT_IS_NOT_RUNNING(pVM) Assert(!VM_IS_RUNNING(pVM))
821	#else
822	#define VM_ASSERT_IS_NOT_RUNNING(pVM) AssertMsg(!VM_IS_RUNNING(pVM), ("VM is running. enmVMState=%d\n", \
823	(pVM)->enmVMState))
824	#endif
825
826	/** @def VM_ASSERT_EMT0
827	* Asserts that the current thread IS emulation thread \#0 (EMT0).
828	*/
829	#define VM_ASSERT_EMT0(pVM) VMCPU_ASSERT_EMT(&(pVM)->aCpus[0])
830
831	/** @def VM_ASSERT_EMT0_RETURN
832	* Asserts that the current thread IS emulation thread \#0 (EMT0) and returns if
833	* it isn't.
834	*/
835	#define VM_ASSERT_EMT0_RETURN(pVM, rc) VMCPU_ASSERT_EMT_RETURN(&(pVM)->aCpus[0], (rc))
836
837
838	/**
839	* Asserts that the current thread is NOT the emulation thread.
840	*/
841	#define VM_ASSERT_OTHER_THREAD(pVM) \
842	AssertMsg(!VM_IS_EMT(pVM), ("Not other thread!!\n"))
843
844
845	/** @def VM_ASSERT_STATE
846	* Asserts a certain VM state.
847	*/
848	#define VM_ASSERT_STATE(pVM, _enmState) \
849	AssertMsg((pVM)->enmVMState == (_enmState), \
850	("state %s, expected %s\n", VMGetStateName((pVM)->enmVMState), VMGetStateName(_enmState)))
851
852	/** @def VM_ASSERT_STATE_RETURN
853	* Asserts a certain VM state and returns if it doesn't match.
854	*/
855	#define VM_ASSERT_STATE_RETURN(pVM, _enmState, rc) \
856	AssertMsgReturn((pVM)->enmVMState == (_enmState), \
857	("state %s, expected %s\n", VMGetStateName((pVM)->enmVMState), VMGetStateName(_enmState)), \
858	(rc))
859
860	/** @def VM_IS_VALID_EXT
861	* Asserts a the VM handle is valid for external access, i.e. not being destroy
862	* or terminated. */
863	#define VM_IS_VALID_EXT(pVM) \
864	( RT_VALID_ALIGNED_PTR(pVM, PAGE_SIZE) \
865	&& ( (unsigned)(pVM)->enmVMState < (unsigned)VMSTATE_DESTROYING \
866	\|\| ( (unsigned)(pVM)->enmVMState == (unsigned)VMSTATE_DESTROYING \
867	&& VM_IS_EMT(pVM))) )
868
869	/** @def VM_ASSERT_VALID_EXT_RETURN
870	* Asserts a the VM handle is valid for external access, i.e. not being
871	* destroy or terminated.
872	*/
873	#define VM_ASSERT_VALID_EXT_RETURN(pVM, rc) \
874	AssertMsgReturn(VM_IS_VALID_EXT(pVM), \
875	("pVM=%p state %s\n", (pVM), RT_VALID_ALIGNED_PTR(pVM, PAGE_SIZE) \
876	? VMGetStateName(pVM->enmVMState) : ""), \
877	(rc))
878
879	/** @def VMCPU_ASSERT_VALID_EXT_RETURN
880	* Asserts a the VMCPU handle is valid for external access, i.e. not being
881	* destroy or terminated.
882	*/
883	#define VMCPU_ASSERT_VALID_EXT_RETURN(pVCpu, rc) \
884	AssertMsgReturn( RT_VALID_ALIGNED_PTR(pVCpu, 64) \
885	&& RT_VALID_ALIGNED_PTR((pVCpu)->CTX_SUFF(pVM), PAGE_SIZE) \
886	&& (unsigned)(pVCpu)->CTX_SUFF(pVM)->enmVMState < (unsigned)VMSTATE_DESTROYING, \
887	("pVCpu=%p pVM=%p state %s\n", (pVCpu), RT_VALID_ALIGNED_PTR(pVCpu, 64) ? (pVCpu)->CTX_SUFF(pVM) : NULL, \
888	RT_VALID_ALIGNED_PTR(pVCpu, 64) && RT_VALID_ALIGNED_PTR((pVCpu)->CTX_SUFF(pVM), PAGE_SIZE) \
889	? VMGetStateName((pVCpu)->pVMR3->enmVMState) : ""), \
890	(rc))
891
892	#endif /* !VBOX_FOR_DTRACE_LIB */
893
894
895
896	/**
897	* The cross context VM structure.
898	*
899	* It contains all the VM data which have to be available in all contexts.
900	* Even if it contains all the data the idea is to use APIs not to modify all
901	* the members all around the place. Therefore we make use of unions to hide
902	* everything which isn't local to the current source module. This means we'll
903	* have to pay a little bit of attention when adding new members to structures
904	* in the unions and make sure to keep the padding sizes up to date.
905	*
906	* Run 'kmk run-struct-tests' (from src/VBox/VMM if you like) after updating!
907	*/
908	typedef struct VM
909	{
910	/** The state of the VM.
911	* This field is read only to everyone except the VM and EM. */
912	VMSTATE volatile enmVMState;
913	/** Forced action flags.
914	* See the VM_FF_* \#defines. Updated atomically.
915	*/
916	volatile uint32_t fGlobalForcedActions;
917	/** Pointer to the array of page descriptors for the VM structure allocation. */
918	R3PTRTYPE(PSUPPAGE) paVMPagesR3;
919	/** Session handle. For use when calling SUPR0 APIs. */
920	PSUPDRVSESSION pSession;
921	/** Pointer to the ring-3 VM structure. */
922	PUVM pUVM;
923	/** Ring-3 Host Context VM Pointer. */
924	R3PTRTYPE(struct VM *) pVMR3;
925	/** Ring-0 Host Context VM Pointer. */
926	R0PTRTYPE(struct VM *) pVMR0;
927	/** Raw-mode Context VM Pointer. */
928	RCPTRTYPE(struct VM *) pVMRC;
929
930	/** The GVM VM handle. Only the GVM should modify this field. */
931	uint32_t hSelf;
932	/** Number of virtual CPUs. */
933	uint32_t cCpus;
934	/** CPU excution cap (1-100) */
935	uint32_t uCpuExecutionCap;
936
937	/** Size of the VM structure including the VMCPU array. */
938	uint32_t cbSelf;
939
940	/** Offset to the VMCPU array starting from beginning of this structure. */
941	uint32_t offVMCPU;
942
943	/**
944	* VMMSwitcher assembly entry point returning to host context.
945	*
946	* Depending on how the host handles the rc status given in @a eax, this may
947	* return and let the caller resume whatever it was doing prior to the call.
948	*
949	*
950	* @param eax The return code, register.
951	* @remark Assume interrupts disabled.
952	* @remark This method pointer lives here because TRPM needs it.
953	*/
954	RTRCPTR pfnVMMRCToHostAsm/(int32_t eax)/;
955
956	/**
957	* VMMSwitcher assembly entry point returning to host context without saving the
958	* raw-mode context (hyper) registers.
959	*
960	* Unlike pfnVMMRC2HCAsm, this will not return to the caller. Instead it
961	* expects the caller to save a RC context in CPUM where one might return if the
962	* return code indicate that this is possible.
963	*
964	* This method pointer lives here because TRPM needs it.
965	*
966	* @param eax The return code, register.
967	* @remark Assume interrupts disabled.
968	* @remark This method pointer lives here because TRPM needs it.
969	*/
970	RTRCPTR pfnVMMRCToHostAsmNoReturn/(int32_t eax)/;
971
972	/** @name Various items that are frequently accessed.
973	* @{ */
974	/** Whether to recompile user mode code or run it raw/hm. */
975	bool fRecompileUser;
976	/** Whether to recompile supervisor mode code or run it raw/hm. */
977	bool fRecompileSupervisor;
978	/** Whether raw mode supports ring-1 code or not. */
979	bool fRawRing1Enabled;
980	/** PATM enabled flag.
981	* This is placed here for performance reasons. */
982	bool fPATMEnabled;
983	/** CSAM enabled flag.
984	* This is placed here for performance reasons. */
985	bool fCSAMEnabled;
986	/** Hardware VM support is available and enabled.
987	* Determined very early during init.
988	* This is placed here for performance reasons. */
989	bool fHMEnabled;
990	/** For asserting on fHMEnable usage. */
991	bool fHMEnabledFixed;
992	/** Hardware VM support requires a minimal raw-mode context.
993	* This is never set on 64-bit hosts, only 32-bit hosts requires it. */
994	bool fHMNeedRawModeCtx;
995	/** Set when this VM is the master FT node.
996	* @todo This doesn't need to be here, FTM should store it in it's own
997	* structures instead. */
998	bool fFaultTolerantMaster;
999	/** Large page enabled flag.
1000	* @todo This doesn't need to be here, PGM should store it in it's own
1001	* structures instead. */
1002	bool fUseLargePages;
1003	/** @} */
1004
1005	/** Alignment padding. */
1006	uint8_t uPadding1[2];
1007
1008	/** @name Debugging
1009	* @{ */
1010	/** Raw-mode Context VM Pointer. */
1011	RCPTRTYPE(RTTRACEBUF) hTraceBufRC;
1012	/** Ring-3 Host Context VM Pointer. */
1013	R3PTRTYPE(RTTRACEBUF) hTraceBufR3;
1014	/** Ring-0 Host Context VM Pointer. */
1015	R0PTRTYPE(RTTRACEBUF) hTraceBufR0;
1016	/** @} */
1017
1018	#if HC_ARCH_BITS == 32
1019	/** Alignment padding. */
1020	uint32_t uPadding2;
1021	#endif
1022
1023	/** @name Switcher statistics (remove)
1024	* @{ */
1025	/** Profiling the total time from Qemu to GC. */
1026	STAMPROFILEADV StatTotalQemuToGC;
1027	/** Profiling the total time from GC to Qemu. */
1028	STAMPROFILEADV StatTotalGCToQemu;
1029	/** Profiling the total time spent in GC. */
1030	STAMPROFILEADV StatTotalInGC;
1031	/** Profiling the total time spent not in Qemu. */
1032	STAMPROFILEADV StatTotalInQemu;
1033	/** Profiling the VMMSwitcher code for going to GC. */
1034	STAMPROFILEADV StatSwitcherToGC;
1035	/** Profiling the VMMSwitcher code for going to HC. */
1036	STAMPROFILEADV StatSwitcherToHC;
1037	STAMPROFILEADV StatSwitcherSaveRegs;
1038	STAMPROFILEADV StatSwitcherSysEnter;
1039	STAMPROFILEADV StatSwitcherDebug;
1040	STAMPROFILEADV StatSwitcherCR0;
1041	STAMPROFILEADV StatSwitcherCR4;
1042	STAMPROFILEADV StatSwitcherJmpCR3;
1043	STAMPROFILEADV StatSwitcherRstrRegs;
1044	STAMPROFILEADV StatSwitcherLgdt;
1045	STAMPROFILEADV StatSwitcherLidt;
1046	STAMPROFILEADV StatSwitcherLldt;
1047	STAMPROFILEADV StatSwitcherTSS;
1048	/** @} */
1049
1050	/** Padding - the unions must be aligned on a 64 bytes boundary and the unions
1051	* must start at the same offset on both 64-bit and 32-bit hosts. */
1052	uint8_t abAlignment3[(HC_ARCH_BITS == 32 ? 24 : 0) + 40];
1053
1054	/** CPUM part. */
1055	union
1056	{
1057	#ifdef ___CPUMInternal_h
1058	struct CPUM s;
1059	#endif
1060	#ifdef ___VBox_vmm_cpum_h
1061	/** Read only info exposed about the host and guest CPUs. */
1062	struct
1063	{
1064	/** Padding for hidden fields. */
1065	uint8_t abHidden0[64];
1066	/** Host CPU feature information. */
1067	CPUMFEATURES HostFeatures;
1068	/** Guest CPU feature information. */
1069	CPUMFEATURES GuestFeatures;
1070	} const ro;
1071	#endif
1072	uint8_t padding[1536]; /* multiple of 64 */
1073	} cpum;
1074
1075	/** VMM part. */
1076	union
1077	{
1078	#ifdef ___VMMInternal_h
1079	struct VMM s;
1080	#endif
1081	uint8_t padding[1600]; /* multiple of 64 */
1082	} vmm;
1083
1084	/** PGM part. */
1085	union
1086	{
1087	#ifdef ___PGMInternal_h
1088	struct PGM s;
1089	#endif
1090	uint8_t padding[40962+6080]; / multiple of 64 */
1091	} pgm;
1092
1093	/** HM part. */
1094	union
1095	{
1096	#ifdef ___HMInternal_h
1097	struct HM s;
1098	#endif
1099	uint8_t padding[5440]; /* multiple of 64 */
1100	} hm;
1101
1102	/** TRPM part. */
1103	union
1104	{
1105	#ifdef ___TRPMInternal_h
1106	struct TRPM s;
1107	#endif
1108	uint8_t padding[5248]; /* multiple of 64 */
1109	} trpm;
1110
1111	/** SELM part. */
1112	union
1113	{
1114	#ifdef ___SELMInternal_h
1115	struct SELM s;
1116	#endif
1117	uint8_t padding[768]; /* multiple of 64 */
1118	} selm;
1119
1120	/** MM part. */
1121	union
1122	{
1123	#ifdef ___MMInternal_h
1124	struct MM s;
1125	#endif
1126	uint8_t padding[192]; /* multiple of 64 */
1127	} mm;
1128
1129	/** PDM part. */
1130	union
1131	{
1132	#ifdef ___PDMInternal_h
1133	struct PDM s;
1134	#endif
1135	uint8_t padding[1920]; /* multiple of 64 */
1136	} pdm;
1137
1138	/** IOM part. */
1139	union
1140	{
1141	#ifdef ___IOMInternal_h
1142	struct IOM s;
1143	#endif
1144	uint8_t padding[896]; /* multiple of 64 */
1145	} iom;
1146
1147	/** PATM part. */
1148	union
1149	{
1150	#ifdef ___PATMInternal_h
1151	struct PATM s;
1152	#endif
1153	uint8_t padding[768]; /* multiple of 64 */
1154	} patm;
1155
1156	/** CSAM part. */
1157	union
1158	{
1159	#ifdef ___CSAMInternal_h
1160	struct CSAM s;
1161	#endif
1162	uint8_t padding[1088]; /* multiple of 64 */
1163	} csam;
1164
1165	/** EM part. */
1166	union
1167	{
1168	#ifdef ___EMInternal_h
1169	struct EM s;
1170	#endif
1171	uint8_t padding[256]; /* multiple of 64 */
1172	} em;
1173
1174	/** TM part. */
1175	union
1176	{
1177	#ifdef ___TMInternal_h
1178	struct TM s;
1179	#endif
1180	uint8_t padding[2496]; /* multiple of 64 */
1181	} tm;
1182
1183	/** DBGF part. */
1184	union
1185	{
1186	#ifdef ___DBGFInternal_h
1187	struct DBGF s;
1188	#endif
1189	#ifdef ___VBox_vmm_dbgf_h
1190	/** Read only info exposed about interrupt breakpoints and selected events. */
1191	struct
1192	{
1193	/** Bitmap of enabled hardware interrupt breakpoints. */
1194	uint32_t bmHardIntBreakpoints[256 / 32];
1195	/** Bitmap of enabled software interrupt breakpoints. */
1196	uint32_t bmSoftIntBreakpoints[256 / 32];
1197	/** Bitmap of selected events.
1198	* This includes non-selectable events too for simplicity, we maintain the
1199	* state for some of these, as it may come in handy. */
1200	uint64_t bmSelectedEvents[(DBGFEVENT_END + 63) / 64];
1201	/** Enabled hardware interrupt breakpoints. */
1202	uint32_t cHardIntBreakpoints;
1203	/** Enabled software interrupt breakpoints. */
1204	uint32_t cSoftIntBreakpoints;
1205	/** Number of selected events. */
1206	uint32_t cSelectedEvents;
1207	} const ro;
1208	#endif
1209	uint8_t padding[2368]; /* multiple of 64 */
1210	} dbgf;
1211
1212	/** SSM part. */
1213	union
1214	{
1215	#ifdef ___SSMInternal_h
1216	struct SSM s;
1217	#endif
1218	uint8_t padding[128]; /* multiple of 64 */
1219	} ssm;
1220
1221	/** FTM part. */
1222	union
1223	{
1224	#ifdef ___FTMInternal_h
1225	struct FTM s;
1226	#endif
1227	uint8_t padding[512]; /* multiple of 64 */
1228	} ftm;
1229
1230	/** REM part. */
1231	union
1232	{
1233	#ifdef ___REMInternal_h
1234	struct REM s;
1235	#endif
1236	uint8_t padding[0x11100]; /* multiple of 64 */
1237	} rem;
1238
1239	union
1240	{
1241	#ifdef ___GIMInternal_h
1242	struct GIM s;
1243	#endif
1244	uint8_t padding[448]; /* multiple of 64 */
1245	} gim;
1246
1247	/* ---- begin small stuff ---- */
1248
1249	/** VM part. */
1250	union
1251	{
1252	#ifdef ___VMInternal_h
1253	struct VMINT s;
1254	#endif
1255	uint8_t padding[24]; /* multiple of 8 */
1256	} vm;
1257
1258	/** CFGM part. */
1259	union
1260	{
1261	#ifdef ___CFGMInternal_h
1262	struct CFGM s;
1263	#endif
1264	uint8_t padding[8]; /* multiple of 8 */
1265	} cfgm;
1266
1267	#ifdef VBOX_WITH_NEW_APIC
1268	union
1269	{
1270	# ifdef ___APICInternal_h
1271	struct APIC s;
1272	# endif
1273	uint8_t padding[128]; /* multiple of 8 */
1274	} apic;
1275	#endif
1276
1277	/** Padding for aligning the cpu array on a page boundary. */
1278	#ifdef VBOX_WITH_NEW_APIC
1279	uint8_t abAlignment2[3870];
1280	#else
1281	uint8_t abAlignment2[3998];
1282	#endif
1283
1284	/* ---- end small stuff ---- */
1285
1286	/** VMCPU array for the configured number of virtual CPUs.
1287	* Must be aligned on a page boundary for TLB hit reasons as well as
1288	* alignment of VMCPU members. */
1289	VMCPU aCpus[1];
1290	} VM;
1291
1292
1293	#ifdef IN_RC
1294	RT_C_DECLS_BEGIN
1295
1296	/** The VM structure.
1297	* This is imported from the VMMRCBuiltin module, i.e. it's a one of those magic
1298	* globals which we should avoid using.
1299	*/
1300	extern DECLIMPORT(VM) g_VM;
1301
1302	RT_C_DECLS_END
1303	#endif
1304
1305	/** @} */
1306
1307	#endif
1308

Note: See TracBrowser for help on using the repository browser.

source: vbox/trunk/include/VBox/vmm/vm.h@ 61067

Download in other formats: