vm.h@ 61144

Last change on this file since 61144 was 61144, checked in by vboxsync, 9 years ago
CPUM,HM,GVMM,TRPM,VMM: Next part of the FPU state handling for IEM. This is a little bit risky change as we now leave CR0.TS+EM cleared after saving the host state, they only get restored when we restore the host state. On Windows, Darwin, and later on Linux (needs testing) we will rely on #NM handling of the host OS and not our own CR.TS/EM handy work. This means we won't be saving the host state but rather the ring-3 state of our own thread. This change also introduces a CPUM force flag that we're using for restoring CR0.TS/EM in raw-mode (it may be extended with other uses later if we need to).
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1	/** @file
2	* VM - The Virtual Machine, data.
3	*/
4
5	/*
6	* Copyright (C) 2006-2015 Oracle Corporation
7	*
8	* This file is part of VirtualBox Open Source Edition (OSE), as
9	* available from http://www.virtualbox.org. This file is free software;
10	* you can redistribute it and/or modify it under the terms of the GNU
11	* General Public License (GPL) as published by the Free Software
12	* Foundation, in version 2 as it comes in the "COPYING" file of the
13	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15	*
16	* The contents of this file may alternatively be used under the terms
17	* of the Common Development and Distribution License Version 1.0
18	* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19	* VirtualBox OSE distribution, in which case the provisions of the
20	* CDDL are applicable instead of those of the GPL.
21	*
22	* You may elect to license modified versions of this file under the
23	* terms and conditions of either the GPL or the CDDL or both.
24	*/
25
26	#ifndef ___VBox_vmm_vm_h
27	#define ___VBox_vmm_vm_h
28
29	#ifndef VBOX_FOR_DTRACE_LIB
30	# include <iprt/param.h>
31	# include <VBox/types.h>
32	# include <VBox/vmm/cpum.h>
33	# include <VBox/vmm/stam.h>
34	# include <VBox/vmm/vmapi.h>
35	# include <VBox/vmm/vmm.h>
36	# include <VBox/sup.h>
37	#else
38	# pragma D depends_on library vbox-types.d
39	# pragma D depends_on library CPUMInternal.d
40	# define ___CPUMInternal_h
41	#endif
42
43
44
45	/** @defgroup grp_vm The Virtual Machine
46	* @ingroup grp_vmm
47	* @{
48	*/
49
50	/**
51	* The state of a Virtual CPU.
52	*
53	* The basic state indicated here is whether the CPU has been started or not. In
54	* addition, there are sub-states when started for assisting scheduling (GVMM
55	* mostly).
56	*
57	* The transition out of the STOPPED state is done by a vmR3PowerOn.
58	* The transition back to the STOPPED state is done by vmR3PowerOff.
59	*
60	* (Alternatively we could let vmR3PowerOn start CPU 0 only and let the SPIP
61	* handling switch on the other CPUs. Then vmR3Reset would stop all but CPU 0.)
62	*/
63	typedef enum VMCPUSTATE
64	{
65	/** The customary invalid zero. */
66	VMCPUSTATE_INVALID = 0,
67
68	/** Virtual CPU has not yet been started. */
69	VMCPUSTATE_STOPPED,
70
71	/** CPU started. */
72	VMCPUSTATE_STARTED,
73	/** CPU started in HM context. */
74	VMCPUSTATE_STARTED_HM,
75	/** Executing guest code and can be poked (RC or STI bits of HM). */
76	VMCPUSTATE_STARTED_EXEC,
77	/** Executing guest code in the recompiler. */
78	VMCPUSTATE_STARTED_EXEC_REM,
79	/** Halted. */
80	VMCPUSTATE_STARTED_HALTED,
81
82	/** The end of valid virtual CPU states. */
83	VMCPUSTATE_END,
84
85	/** Ensure 32-bit type. */
86	VMCPUSTATE_32BIT_HACK = 0x7fffffff
87	} VMCPUSTATE;
88
89
90	/**
91	* The cross context virtual CPU structure.
92	*
93	* Run 'kmk run-struct-tests' (from src/VBox/VMM if you like) after updating!
94	*/
95	typedef struct VMCPU
96	{
97	/** Per CPU forced action.
98	* See the VMCPU_FF_* \#defines. Updated atomically. */
99	uint32_t volatile fLocalForcedActions; /* 0 */
100	/** The CPU state. */
101	VMCPUSTATE volatile enmState; /* 4 */
102
103	/** Pointer to the ring-3 UVMCPU structure. */
104	PUVMCPU pUVCpu; /* 8 */
105	/** Ring-3 Host Context VM Pointer. */
106	PVMR3 pVMR3; /* 16 / 12 */
107	/** Ring-0 Host Context VM Pointer. */
108	PVMR0 pVMR0; /* 24 / 16 */
109	/** Raw-mode Context VM Pointer. */
110	PVMRC pVMRC; /* 32 / 20 */
111	/** The CPU ID.
112	* This is the index into the VM::aCpu array. */
113	VMCPUID idCpu; /* 36 / 24 */
114	/** The native thread handle. */
115	RTNATIVETHREAD hNativeThread; /* 40 / 28 */
116	/** The native R0 thread handle. (different from the R3 handle!) */
117	RTNATIVETHREAD hNativeThreadR0; /* 48 / 32 */
118	/** Which host CPU ID is this EMT running on.
119	* Only valid when in RC or HMR0 with scheduling disabled. */
120	RTCPUID volatile idHostCpu; /* 56 / 36 */
121	/** The CPU set index corresponding to idHostCpu, UINT32_MAX if not valid.
122	* @remarks Best to make sure iHostCpuSet shares cache line with idHostCpu! */
123	uint32_t volatile iHostCpuSet; /* 60 / 40 */
124
125	/** Trace groups enable flags. */
126	uint32_t fTraceGroups; /* 64 / 44 */
127	/** Align the structures below bit on a 64-byte boundary and make sure it starts
128	* at the same offset in both 64-bit and 32-bit builds.
129	*
130	* @remarks The alignments of the members that are larger than 48 bytes should be
131	* 64-byte for cache line reasons. structs containing small amounts of
132	* data could be lumped together at the end with a < 64 byte padding
133	* following it (to grow into and align the struct size).
134	*/
135	uint8_t abAlignment1[HC_ARCH_BITS == 64 ? 56 : 12+64];
136	/** State data for use by ad hoc profiling. */
137	uint32_t uAdHoc;
138	/** Profiling samples for use by ad hoc profiling. */
139	STAMPROFILEADV aStatAdHoc[8]; /* size: 408 = 320 /
140
141	/** HM part. */
142	union
143	{
144	#ifdef ___HMInternal_h
145	struct HMCPU s;
146	#endif
147	uint8_t padding[5760]; /* multiple of 64 */
148	} hm;
149
150	/** EM part. */
151	union
152	{
153	#ifdef ___EMInternal_h
154	struct EMCPU s;
155	#endif
156	uint8_t padding[1408]; /* multiple of 64 */
157	} em;
158
159	/** IEM part. */
160	union
161	{
162	#ifdef ___IEMInternal_h
163	struct IEMCPU s;
164	#endif
165	uint8_t padding[3072]; /* multiple of 64 */
166	} iem;
167
168	/** TRPM part. */
169	union
170	{
171	#ifdef ___TRPMInternal_h
172	struct TRPMCPU s;
173	#endif
174	uint8_t padding[128]; /* multiple of 64 */
175	} trpm;
176
177	/** TM part. */
178	union
179	{
180	#ifdef ___TMInternal_h
181	struct TMCPU s;
182	#endif
183	uint8_t padding[384]; /* multiple of 64 */
184	} tm;
185
186	/** VMM part. */
187	union
188	{
189	#ifdef ___VMMInternal_h
190	struct VMMCPU s;
191	#endif
192	uint8_t padding[704]; /* multiple of 64 */
193	} vmm;
194
195	/** PDM part. */
196	union
197	{
198	#ifdef ___PDMInternal_h
199	struct PDMCPU s;
200	#endif
201	uint8_t padding[256]; /* multiple of 64 */
202	} pdm;
203
204	/** IOM part. */
205	union
206	{
207	#ifdef ___IOMInternal_h
208	struct IOMCPU s;
209	#endif
210	uint8_t padding[512]; /* multiple of 64 */
211	} iom;
212
213	/** DBGF part.
214	* @todo Combine this with other tiny structures. */
215	union
216	{
217	#ifdef ___DBGFInternal_h
218	struct DBGFCPU s;
219	#endif
220	uint8_t padding[256]; /* multiple of 64 */
221	} dbgf;
222
223	/** GIM part. */
224	union
225	{
226	#ifdef ___GIMInternal_h
227	struct GIMCPU s;
228	#endif
229	uint8_t padding[64]; /* multiple of 64 */
230	} gim;
231
232	#ifdef VBOX_WITH_NEW_APIC
233	/** APIC part. */
234	union
235	{
236	# ifdef ___APICInternal_h
237	struct APICCPU s;
238	# endif
239	uint8_t padding[640]; /* multiple of 64 */
240	} apic;
241	#endif
242
243	/** Align the following members on page boundary. */
244	#ifdef VBOX_WITH_NEW_APIC
245	uint8_t abAlignment2[2752];
246	#else
247	uint8_t abAlignment2[3392];
248	#endif
249
250	/** PGM part. */
251	union
252	{
253	#ifdef ___PGMInternal_h
254	struct PGMCPU s;
255	#endif
256	uint8_t padding[4096]; /* multiple of 4096 */
257	} pgm;
258
259	/** CPUM part. */
260	union
261	{
262	#ifdef ___CPUMInternal_h
263	struct CPUMCPU s;
264	#endif
265	uint8_t padding[4096]; /* multiple of 4096 */
266	} cpum;
267	} VMCPU;
268
269
270	#ifndef VBOX_FOR_DTRACE_LIB
271
272	/** @name Operations on VMCPU::enmState
273	* @{ */
274	/** Gets the VMCPU state. */
275	#define VMCPU_GET_STATE(pVCpu) ( (pVCpu)->enmState )
276	/** Sets the VMCPU state. */
277	#define VMCPU_SET_STATE(pVCpu, enmNewState) \
278	ASMAtomicWriteU32((uint32_t volatile *)&(pVCpu)->enmState, (enmNewState))
279	/** Cmpares and sets the VMCPU state. */
280	#define VMCPU_CMPXCHG_STATE(pVCpu, enmNewState, enmOldState) \
281	ASMAtomicCmpXchgU32((uint32_t volatile *)&(pVCpu)->enmState, (enmNewState), (enmOldState))
282	/** Checks the VMCPU state. */
283	#ifdef VBOX_STRICT
284	# define VMCPU_ASSERT_STATE(pVCpu, enmExpectedState) \
285	do { \
286	VMCPUSTATE enmState = VMCPU_GET_STATE(pVCpu); \
287	AssertMsg(enmState == (enmExpectedState), \
288	("enmState=%d enmExpectedState=%d idCpu=%u\n", \
289	enmState, enmExpectedState, (pVCpu)->idCpu)); \
290	} while (0)
291	#else
292	# define VMCPU_ASSERT_STATE(pVCpu, enmExpectedState) do { } while (0)
293	#endif
294	/** Tests if the state means that the CPU is started. */
295	#define VMCPUSTATE_IS_STARTED(enmState) ( (enmState) > VMCPUSTATE_STOPPED )
296	/** Tests if the state means that the CPU is stopped. */
297	#define VMCPUSTATE_IS_STOPPED(enmState) ( (enmState) == VMCPUSTATE_STOPPED )
298	/** @} */
299
300
301	/** The name of the raw-mode context VMM Core module. */
302	#define VMMRC_MAIN_MODULE_NAME "VMMRC.rc"
303	/** The name of the ring-0 context VMM Core module. */
304	#define VMMR0_MAIN_MODULE_NAME "VMMR0.r0"
305
306	/**
307	* Wrapper macro for avoiding too much \#ifdef VBOX_WITH_RAW_MODE.
308	*/
309	#ifdef VBOX_WITH_RAW_MODE
310	# define VM_WHEN_RAW_MODE(a_WithExpr, a_WithoutExpr) a_WithExpr
311	#else
312	# define VM_WHEN_RAW_MODE(a_WithExpr, a_WithoutExpr) a_WithoutExpr
313	#endif
314
315
316	/** VM Forced Action Flags.
317	*
318	* Use the VM_FF_SET() and VM_FF_CLEAR() macros to change the force
319	* action mask of a VM.
320	*
321	* Available VM bits:
322	* 0, 1, 5, 6, 7, 13, 14, 15, 16, 17, 21, 22, 23, 24, 25, 26, 27, 28, 30
323	*
324	*
325	* Available VMCPU bits:
326	* 10, 11, 14, 15, 31
327	*
328	* @todo If we run low on VMCPU, we may consider merging the SELM bits
329	*
330	* @{
331	*/
332	/** The virtual sync clock has been stopped, go to TM until it has been
333	* restarted... */
334	#define VM_FF_TM_VIRTUAL_SYNC RT_BIT_32(2)
335	/** PDM Queues are pending. */
336	#define VM_FF_PDM_QUEUES RT_BIT_32(VM_FF_PDM_QUEUES_BIT)
337	/** The bit number for VM_FF_PDM_QUEUES. */
338	#define VM_FF_PDM_QUEUES_BIT 3
339	/** PDM DMA transfers are pending. */
340	#define VM_FF_PDM_DMA RT_BIT_32(VM_FF_PDM_DMA_BIT)
341	/** The bit number for VM_FF_PDM_DMA. */
342	#define VM_FF_PDM_DMA_BIT 4
343	/** This action forces the VM to call DBGF so DBGF can service debugger
344	* requests in the emulation thread.
345	* This action flag stays asserted till DBGF clears it.*/
346	#define VM_FF_DBGF RT_BIT_32(VM_FF_DBGF_BIT)
347	/** The bit number for VM_FF_DBGF. */
348	#define VM_FF_DBGF_BIT 8
349	/** This action forces the VM to service pending requests from other
350	* thread or requests which must be executed in another context. */
351	#define VM_FF_REQUEST RT_BIT_32(9)
352	/** Check for VM state changes and take appropriate action. */
353	#define VM_FF_CHECK_VM_STATE RT_BIT_32(VM_FF_CHECK_VM_STATE_BIT)
354	/** The bit number for VM_FF_CHECK_VM_STATE. */
355	#define VM_FF_CHECK_VM_STATE_BIT 10
356	/** Reset the VM. (postponed) */
357	#define VM_FF_RESET RT_BIT_32(VM_FF_RESET_BIT)
358	/** The bit number for VM_FF_RESET. */
359	#define VM_FF_RESET_BIT 11
360	/** EMT rendezvous in VMM. */
361	#define VM_FF_EMT_RENDEZVOUS RT_BIT_32(VM_FF_EMT_RENDEZVOUS_BIT)
362	/** The bit number for VM_FF_EMT_RENDEZVOUS. */
363	#define VM_FF_EMT_RENDEZVOUS_BIT 12
364
365	/** PGM needs to allocate handy pages. */
366	#define VM_FF_PGM_NEED_HANDY_PAGES RT_BIT_32(18)
367	/** PGM is out of memory.
368	* Abandon all loops and code paths which can be resumed and get up to the EM
369	* loops. */
370	#define VM_FF_PGM_NO_MEMORY RT_BIT_32(19)
371	/** PGM is about to perform a lightweight pool flush
372	* Guest SMP: all EMT threads should return to ring 3
373	*/
374	#define VM_FF_PGM_POOL_FLUSH_PENDING RT_BIT_32(20)
375	/** REM needs to be informed about handler changes. */
376	#define VM_FF_REM_HANDLER_NOTIFY RT_BIT_32(VM_FF_REM_HANDLER_NOTIFY_BIT)
377	/** The bit number for VM_FF_REM_HANDLER_NOTIFY. */
378	#define VM_FF_REM_HANDLER_NOTIFY_BIT 29
379	/** Suspend the VM - debug only. */
380	#define VM_FF_DEBUG_SUSPEND RT_BIT_32(31)
381
382
383	/** This action forces the VM to check any pending interrupts on the APIC. */
384	#define VMCPU_FF_INTERRUPT_APIC RT_BIT_32(0)
385	/** This action forces the VM to check any pending interrups on the PIC. */
386	#define VMCPU_FF_INTERRUPT_PIC RT_BIT_32(1)
387	/** This action forces the VM to schedule and run pending timer (TM).
388	* @remarks Don't move - PATM compatibility. */
389	#define VMCPU_FF_TIMER RT_BIT_32(2)
390	/** This action forces the VM to check any pending NMIs. */
391	#define VMCPU_FF_INTERRUPT_NMI_BIT 3
392	#define VMCPU_FF_INTERRUPT_NMI RT_BIT_32(VMCPU_FF_INTERRUPT_NMI_BIT)
393	/** This action forces the VM to check any pending SMIs. */
394	#define VMCPU_FF_INTERRUPT_SMI_BIT 4
395	#define VMCPU_FF_INTERRUPT_SMI RT_BIT_32(VMCPU_FF_INTERRUPT_SMI_BIT)
396	/** PDM critical section unlocking is pending, process promptly upon return to R3. */
397	#define VMCPU_FF_PDM_CRITSECT RT_BIT_32(5)
398	/** This action forces the VCPU out of the halted state. */
399	#define VMCPU_FF_UNHALT RT_BIT_32(6)
400	/** Pending IEM action (bit number). */
401	#define VMCPU_FF_IEM_BIT 7
402	/** Pending IEM action (mask). */
403	#define VMCPU_FF_IEM RT_BIT_32(VMCPU_FF_IEM_BIT)
404	/** Pending APIC action (bit number). */
405	#define VMCPU_FF_UPDATE_APIC_BIT 8
406	/** This action forces the VM to update APIC's asynchronously arrived
407	* interrupts as pending interrupts. */
408	#define VMCPU_FF_UPDATE_APIC RT_BIT_32(VMCPU_FF_UPDATE_APIC_BIT)
409
410	/** This action forces the VM to service pending requests from other
411	* thread or requests which must be executed in another context. */
412	#define VMCPU_FF_REQUEST RT_BIT_32(9)
413	/** This action forces the VM to service any pending updates to CR3 (used only
414	* by HM). */
415	#define VMCPU_FF_HM_UPDATE_CR3 RT_BIT_32(12)
416	/** This action forces the VM to service any pending updates to PAE PDPEs (used
417	* only by HM). */
418	#define VMCPU_FF_HM_UPDATE_PAE_PDPES RT_BIT_32(13)
419	/** This action forces the VM to resync the page tables before going
420	* back to execute guest code. (GLOBAL FLUSH) */
421	#define VMCPU_FF_PGM_SYNC_CR3 RT_BIT_32(16)
422	/** Same as VM_FF_PGM_SYNC_CR3 except that global pages can be skipped.
423	* (NON-GLOBAL FLUSH) */
424	#define VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL RT_BIT_32(17)
425	/** Check for pending TLB shootdown actions (deprecated)
426	* Reserved for furture HM re-use if necessary / safe.
427	* Consumer: HM */
428	#define VMCPU_FF_TLB_SHOOTDOWN_UNUSED RT_BIT_32(18)
429	/** Check for pending TLB flush action.
430	* Consumer: HM
431	* @todo rename to VMCPU_FF_HM_TLB_FLUSH */
432	#define VMCPU_FF_TLB_FLUSH RT_BIT_32(VMCPU_FF_TLB_FLUSH_BIT)
433	/** The bit number for VMCPU_FF_TLB_FLUSH. */
434	#define VMCPU_FF_TLB_FLUSH_BIT 19
435	#ifdef VBOX_WITH_RAW_MODE
436	/** Check the interrupt and trap gates */
437	# define VMCPU_FF_TRPM_SYNC_IDT RT_BIT_32(20)
438	/** Check Guest's TSS ring 0 stack */
439	# define VMCPU_FF_SELM_SYNC_TSS RT_BIT_32(21)
440	/** Check Guest's GDT table */
441	# define VMCPU_FF_SELM_SYNC_GDT RT_BIT_32(22)
442	/** Check Guest's LDT table */
443	# define VMCPU_FF_SELM_SYNC_LDT RT_BIT_32(23)
444	#endif /* VBOX_WITH_RAW_MODE */
445	/** Inhibit interrupts pending. See EMGetInhibitInterruptsPC(). */
446	#define VMCPU_FF_INHIBIT_INTERRUPTS RT_BIT_32(24)
447	/** Block injection of non-maskable interrupts to the guest. */
448	#define VMCPU_FF_BLOCK_NMIS RT_BIT_32(25)
449	#ifdef VBOX_WITH_RAW_MODE
450	/** CSAM needs to scan the page that's being executed */
451	# define VMCPU_FF_CSAM_SCAN_PAGE RT_BIT_32(26)
452	/** CSAM needs to do some homework. */
453	# define VMCPU_FF_CSAM_PENDING_ACTION RT_BIT_32(27)
454	#endif /* VBOX_WITH_RAW_MODE */
455	/** Force return to Ring-3. */
456	#define VMCPU_FF_TO_R3 RT_BIT_32(28)
457	/** Force return to ring-3 to service pending I/O or MMIO write.
458	* This is a backup for mechanism VINF_IOM_R3_IOPORT_COMMIT_WRITE and
459	* VINF_IOM_R3_MMIO_COMMIT_WRITE, allowing VINF_EM_DBG_BREAKPOINT and similar
460	* status codes to be propagated at the same time without loss. */
461	#define VMCPU_FF_IOM RT_BIT_32(29)
462	#ifdef VBOX_WITH_RAW_MODE
463	/** CPUM need to adjust CR0.TS/EM before executing raw-mode code again. */
464	# define VMCPU_FF_CPUM RT_BIT_32(VMCPU_FF_CPUM_BIT)
465	/** The bit number for VMCPU_FF_CPUM. */
466	# define VMCPU_FF_CPUM_BIT 30
467	#endif /* VBOX_WITH_RAW_MODE */
468
469	/** Externally VM forced actions. Used to quit the idle/wait loop. */
470	#define VM_FF_EXTERNAL_SUSPENDED_MASK (VM_FF_CHECK_VM_STATE \| VM_FF_DBGF \| VM_FF_REQUEST \| VM_FF_EMT_RENDEZVOUS)
471	/** Externally VMCPU forced actions. Used to quit the idle/wait loop. */
472	#define VMCPU_FF_EXTERNAL_SUSPENDED_MASK (VMCPU_FF_REQUEST)
473
474	/** Externally forced VM actions. Used to quit the idle/wait loop. */
475	#define VM_FF_EXTERNAL_HALTED_MASK ( VM_FF_CHECK_VM_STATE \| VM_FF_DBGF \| VM_FF_REQUEST \
476	\| VM_FF_PDM_QUEUES \| VM_FF_PDM_DMA \| VM_FF_EMT_RENDEZVOUS)
477	/** Externally forced VMCPU actions. Used to quit the idle/wait loop. */
478	#define VMCPU_FF_EXTERNAL_HALTED_MASK ( VMCPU_FF_UPDATE_APIC \| VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC \
479	\| VMCPU_FF_REQUEST \| VMCPU_FF_INTERRUPT_NMI \| VMCPU_FF_INTERRUPT_SMI \
480	\| VMCPU_FF_UNHALT \| VMCPU_FF_TIMER)
481
482	/** High priority VM pre-execution actions. */
483	#define VM_FF_HIGH_PRIORITY_PRE_MASK ( VM_FF_CHECK_VM_STATE \| VM_FF_DBGF \| VM_FF_TM_VIRTUAL_SYNC \
484	\| VM_FF_DEBUG_SUSPEND \| VM_FF_PGM_NEED_HANDY_PAGES \| VM_FF_PGM_NO_MEMORY \
485	\| VM_FF_EMT_RENDEZVOUS)
486	/** High priority VMCPU pre-execution actions. */
487	#define VMCPU_FF_HIGH_PRIORITY_PRE_MASK ( VMCPU_FF_TIMER \| VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC \
488	\| VMCPU_FF_UPDATE_APIC \
489	\| VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL \
490	\| VMCPU_FF_INHIBIT_INTERRUPTS \
491	\| VM_WHEN_RAW_MODE( VMCPU_FF_SELM_SYNC_TSS \| VMCPU_FF_TRPM_SYNC_IDT \
492	\| VMCPU_FF_SELM_SYNC_GDT \| VMCPU_FF_SELM_SYNC_LDT, 0 ) )
493
494	/** High priority VM pre raw-mode execution mask. */
495	#define VM_FF_HIGH_PRIORITY_PRE_RAW_MASK (VM_FF_PGM_NEED_HANDY_PAGES \| VM_FF_PGM_NO_MEMORY)
496	/** High priority VMCPU pre raw-mode execution mask. */
497	#define VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK ( VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL \
498	\| VMCPU_FF_INHIBIT_INTERRUPTS \
499	\| VM_WHEN_RAW_MODE( VMCPU_FF_SELM_SYNC_TSS \| VMCPU_FF_TRPM_SYNC_IDT \
500	\| VMCPU_FF_SELM_SYNC_GDT \| VMCPU_FF_SELM_SYNC_LDT, 0) )
501
502	/** High priority post-execution actions. */
503	#define VM_FF_HIGH_PRIORITY_POST_MASK (VM_FF_PGM_NO_MEMORY)
504	/** High priority post-execution actions. */
505	#define VMCPU_FF_HIGH_PRIORITY_POST_MASK ( VMCPU_FF_PDM_CRITSECT \| VM_WHEN_RAW_MODE(VMCPU_FF_CSAM_PENDING_ACTION, 0) \
506	\| VMCPU_FF_HM_UPDATE_CR3 \| VMCPU_FF_HM_UPDATE_PAE_PDPES \
507	\| VMCPU_FF_IEM \| VMCPU_FF_IOM )
508
509	/** Normal priority VM post-execution actions. */
510	#define VM_FF_NORMAL_PRIORITY_POST_MASK ( VM_FF_CHECK_VM_STATE \| VM_FF_DBGF \| VM_FF_RESET \
511	\| VM_FF_PGM_NO_MEMORY \| VM_FF_EMT_RENDEZVOUS)
512	/** Normal priority VMCPU post-execution actions. */
513	#define VMCPU_FF_NORMAL_PRIORITY_POST_MASK VM_WHEN_RAW_MODE(VMCPU_FF_CSAM_SCAN_PAGE, 0)
514
515	/** Normal priority VM actions. */
516	#define VM_FF_NORMAL_PRIORITY_MASK ( VM_FF_REQUEST \| VM_FF_PDM_QUEUES \| VM_FF_PDM_DMA \| VM_FF_REM_HANDLER_NOTIFY \
517	\| VM_FF_EMT_RENDEZVOUS)
518	/** Normal priority VMCPU actions. */
519	#define VMCPU_FF_NORMAL_PRIORITY_MASK (VMCPU_FF_REQUEST \| VMCPU_FF_UNHALT)
520
521	/** Flags to clear before resuming guest execution. */
522	#define VMCPU_FF_RESUME_GUEST_MASK (VMCPU_FF_TO_R3)
523
524
525	/** VM flags that cause the REP[\|NE\|E] STRINS loops to yield immediately. */
526	#define VM_FF_HIGH_PRIORITY_POST_REPSTR_MASK ( VM_FF_TM_VIRTUAL_SYNC \| VM_FF_PGM_NEED_HANDY_PAGES \| VM_FF_PGM_NO_MEMORY \
527	\| VM_FF_EMT_RENDEZVOUS \| VM_FF_RESET \| VM_FF_PGM_POOL_FLUSH_PENDING )
528	/** VM flags that cause the REP[\|NE\|E] STRINS loops to yield. */
529	#define VM_FF_YIELD_REPSTR_MASK ( VM_FF_HIGH_PRIORITY_POST_REPSTR_MASK \
530	\| VM_FF_PDM_QUEUES \| VM_FF_PDM_DMA \| VM_FF_DBGF \| VM_FF_DEBUG_SUSPEND )
531	/** VMCPU flags that cause the REP[\|NE\|E] STRINS loops to yield immediately. */
532	#ifdef IN_RING3
533	# define VMCPU_FF_HIGH_PRIORITY_POST_REPSTR_MASK ( VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL )
534	#else
535	# define VMCPU_FF_HIGH_PRIORITY_POST_REPSTR_MASK ( VMCPU_FF_TO_R3 \| VMCPU_FF_IEM \| VMCPU_FF_IOM \| VMCPU_FF_PGM_SYNC_CR3 \
536	\| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL )
537	#endif
538	/** VMCPU flags that cause the REP[\|NE\|E] STRINS loops to yield, interrupts
539	* enabled. */
540	#define VMCPU_FF_YIELD_REPSTR_MASK ( VMCPU_FF_HIGH_PRIORITY_POST_REPSTR_MASK \
541	\| VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_UPDATE_APIC \| VMCPU_FF_INTERRUPT_PIC \
542	\| VMCPU_FF_INTERRUPT_NMI \| VMCPU_FF_INTERRUPT_SMI \| VMCPU_FF_PDM_CRITSECT \
543	\| VMCPU_FF_TIMER \| VMCPU_FF_REQUEST )
544	/** VMCPU flags that cause the REP[\|NE\|E] STRINS loops to yield, interrupts
545	* disabled. */
546	#define VMCPU_FF_YIELD_REPSTR_NOINT_MASK ( VMCPU_FF_YIELD_REPSTR_MASK \
547	& ~(VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_UPDATE_APIC \| VMCPU_FF_INTERRUPT_PIC) )
548
549	/** VM Flags that cause the HM loops to go back to ring-3. */
550	#define VM_FF_HM_TO_R3_MASK ( VM_FF_TM_VIRTUAL_SYNC \| VM_FF_PGM_NEED_HANDY_PAGES \| VM_FF_PGM_NO_MEMORY \
551	\| VM_FF_PDM_QUEUES \| VM_FF_EMT_RENDEZVOUS)
552	/** VMCPU Flags that cause the HM loops to go back to ring-3. */
553	#define VMCPU_FF_HM_TO_R3_MASK ( VMCPU_FF_TO_R3 \| VMCPU_FF_TIMER \| VMCPU_FF_PDM_CRITSECT \
554	\| VMCPU_FF_IEM \| VMCPU_FF_IOM)
555
556	/** High priority ring-0 VM pre HM-mode execution mask. */
557	#define VM_FF_HP_R0_PRE_HM_MASK (VM_FF_HM_TO_R3_MASK \| VM_FF_REQUEST \| VM_FF_PGM_POOL_FLUSH_PENDING \| VM_FF_PDM_DMA)
558	/** High priority ring-0 VMCPU pre HM-mode execution mask. */
559	#define VMCPU_FF_HP_R0_PRE_HM_MASK ( VMCPU_FF_HM_TO_R3_MASK \| VMCPU_FF_PGM_SYNC_CR3 \
560	\| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL \| VMCPU_FF_REQUEST)
561	/** High priority ring-0 VM pre HM-mode execution mask, single stepping. */
562	#define VM_FF_HP_R0_PRE_HM_STEP_MASK (VM_FF_HP_R0_PRE_HM_MASK & ~( VM_FF_TM_VIRTUAL_SYNC \| VM_FF_PDM_QUEUES \
563	\| VM_FF_EMT_RENDEZVOUS \| VM_FF_REQUEST \
564	\| VM_FF_PDM_DMA) )
565	/** High priority ring-0 VMCPU pre HM-mode execution mask, single stepping. */
566	#define VMCPU_FF_HP_R0_PRE_HM_STEP_MASK (VMCPU_FF_HP_R0_PRE_HM_MASK & ~( VMCPU_FF_TO_R3 \| VMCPU_FF_TIMER \
567	\| VMCPU_FF_PDM_CRITSECT \| VMCPU_FF_REQUEST) )
568
569	/** All the forced VM flags. */
570	#define VM_FF_ALL_MASK (~0U)
571	/** All the forced VMCPU flags. */
572	#define VMCPU_FF_ALL_MASK (~0U)
573
574	/** All the forced VM flags except those related to raw-mode and hardware
575	* assisted execution. */
576	#define VM_FF_ALL_REM_MASK (~(VM_FF_HIGH_PRIORITY_PRE_RAW_MASK) \| VM_FF_PGM_NO_MEMORY)
577	/** All the forced VMCPU flags except those related to raw-mode and hardware
578	* assisted execution. */
579	#define VMCPU_FF_ALL_REM_MASK (~( VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK \| VMCPU_FF_PDM_CRITSECT \
580	\| VMCPU_FF_TLB_FLUSH \| VM_WHEN_RAW_MODE(VMCPU_FF_CSAM_PENDING_ACTION, 0) ))
581	/** @} */
582
583	/** @def VM_FF_SET
584	* Sets a force action flag.
585	*
586	* @param pVM The cross context VM structure.
587	* @param fFlag The flag to set.
588	*/
589	#if 1
590	# define VM_FF_SET(pVM, fFlag) ASMAtomicOrU32(&(pVM)->fGlobalForcedActions, (fFlag))
591	#else
592	# define VM_FF_SET(pVM, fFlag) \
593	do { ASMAtomicOrU32(&(pVM)->fGlobalForcedActions, (fFlag)); \
594	RTLogPrintf("VM_FF_SET : %08x %s - %s(%d) %s\n", (pVM)->fGlobalForcedActions, #fFlag, __FILE__, __LINE__, __FUNCTION__); \
595	} while (0)
596	#endif
597
598	/** @def VMCPU_FF_SET
599	* Sets a force action flag for the given VCPU.
600	*
601	* @param pVCpu The cross context virtual CPU structure.
602	* @param fFlag The flag to set.
603	*/
604	#define VMCPU_FF_SET(pVCpu, fFlag) ASMAtomicOrU32(&(pVCpu)->fLocalForcedActions, (fFlag))
605
606	/** @def VM_FF_CLEAR
607	* Clears a force action flag.
608	*
609	* @param pVM The cross context VM structure.
610	* @param fFlag The flag to clear.
611	*/
612	#if 1
613	# define VM_FF_CLEAR(pVM, fFlag) ASMAtomicAndU32(&(pVM)->fGlobalForcedActions, ~(fFlag))
614	#else
615	# define VM_FF_CLEAR(pVM, fFlag) \
616	do { ASMAtomicAndU32(&(pVM)->fGlobalForcedActions, ~(fFlag)); \
617	RTLogPrintf("VM_FF_CLEAR: %08x %s - %s(%d) %s\n", (pVM)->fGlobalForcedActions, #fFlag, __FILE__, __LINE__, __FUNCTION__); \
618	} while (0)
619	#endif
620
621	/** @def VMCPU_FF_CLEAR
622	* Clears a force action flag for the given VCPU.
623	*
624	* @param pVCpu The cross context virtual CPU structure.
625	* @param fFlag The flag to clear.
626	*/
627	#define VMCPU_FF_CLEAR(pVCpu, fFlag) ASMAtomicAndU32(&(pVCpu)->fLocalForcedActions, ~(fFlag))
628
629	/** @def VM_FF_IS_SET
630	* Checks if a force action flag is set.
631	*
632	* @param pVM The cross context VM structure.
633	* @param fFlag The flag to check.
634	*/
635	#define VM_FF_IS_SET(pVM, fFlag) (((pVM)->fGlobalForcedActions & (fFlag)) == (fFlag))
636
637	/** @def VMCPU_FF_IS_SET
638	* Checks if a force action flag is set for the given VCPU.
639	*
640	* @param pVCpu The cross context virtual CPU structure.
641	* @param fFlag The flag to check.
642	*/
643	#define VMCPU_FF_IS_SET(pVCpu, fFlag) (((pVCpu)->fLocalForcedActions & (fFlag)) == (fFlag))
644
645	/** @def VM_FF_IS_PENDING
646	* Checks if one or more force action in the specified set is pending.
647	*
648	* @param pVM The cross context VM structure.
649	* @param fFlags The flags to check for.
650	*/
651	#define VM_FF_IS_PENDING(pVM, fFlags) RT_BOOL((pVM)->fGlobalForcedActions & (fFlags))
652
653	/** @def VM_FF_TEST_AND_CLEAR
654	* Checks if one (!) force action in the specified set is pending and clears it atomically
655	*
656	* @returns true if the bit was set.
657	* @returns false if the bit was clear.
658	* @param pVM The cross context VM structure.
659	* @param iBit Bit position to check and clear
660	*/
661	#define VM_FF_TEST_AND_CLEAR(pVM, iBit) (ASMAtomicBitTestAndClear(&(pVM)->fGlobalForcedActions, iBit##_BIT))
662
663	/** @def VMCPU_FF_TEST_AND_CLEAR
664	* Checks if one (!) force action in the specified set is pending and clears it atomically
665	*
666	* @returns true if the bit was set.
667	* @returns false if the bit was clear.
668	* @param pVCpu The cross context virtual CPU structure.
669	* @param iBit Bit position to check and clear
670	*/
671	#define VMCPU_FF_TEST_AND_CLEAR(pVCpu, iBit) (ASMAtomicBitTestAndClear(&(pVCpu)->fLocalForcedActions, iBit##_BIT))
672
673	/** @def VMCPU_FF_IS_PENDING
674	* Checks if one or more force action in the specified set is pending for the given VCPU.
675	*
676	* @param pVCpu The cross context virtual CPU structure.
677	* @param fFlags The flags to check for.
678	*/
679	#define VMCPU_FF_IS_PENDING(pVCpu, fFlags) RT_BOOL((pVCpu)->fLocalForcedActions & (fFlags))
680
681	/** @def VM_FF_IS_PENDING_EXCEPT
682	* Checks if one or more force action in the specified set is pending while one
683	* or more other ones are not.
684	*
685	* @param pVM The cross context VM structure.
686	* @param fFlags The flags to check for.
687	* @param fExcpt The flags that should not be set.
688	*/
689	#define VM_FF_IS_PENDING_EXCEPT(pVM, fFlags, fExcpt) ( ((pVM)->fGlobalForcedActions & (fFlags)) && !((pVM)->fGlobalForcedActions & (fExcpt)) )
690
691	/** @def VMCPU_FF_IS_PENDING_EXCEPT
692	* Checks if one or more force action in the specified set is pending for the given
693	* VCPU while one or more other ones are not.
694	*
695	* @param pVCpu The cross context virtual CPU structure.
696	* @param fFlags The flags to check for.
697	* @param fExcpt The flags that should not be set.
698	*/
699	#define VMCPU_FF_IS_PENDING_EXCEPT(pVCpu, fFlags, fExcpt) ( ((pVCpu)->fLocalForcedActions & (fFlags)) && !((pVCpu)->fLocalForcedActions & (fExcpt)) )
700
701	/** @def VM_IS_EMT
702	* Checks if the current thread is the emulation thread (EMT).
703	*
704	* @remark The ring-0 variation will need attention if we expand the ring-0
705	* code to let threads other than EMT mess around with the VM.
706	*/
707	#ifdef IN_RC
708	# define VM_IS_EMT(pVM) true
709	#else
710	# define VM_IS_EMT(pVM) (VMMGetCpu(pVM) != NULL)
711	#endif
712
713	/** @def VMCPU_IS_EMT
714	* Checks if the current thread is the emulation thread (EMT) for the specified
715	* virtual CPU.
716	*/
717	#ifdef IN_RC
718	# define VMCPU_IS_EMT(pVCpu) true
719	#else
720	# define VMCPU_IS_EMT(pVCpu) ((pVCpu) && ((pVCpu) == VMMGetCpu((pVCpu)->CTX_SUFF(pVM))))
721	#endif
722
723	/** @def VM_ASSERT_EMT
724	* Asserts that the current thread IS the emulation thread (EMT).
725	*/
726	#ifdef IN_RC
727	# define VM_ASSERT_EMT(pVM) Assert(VM_IS_EMT(pVM))
728	#elif defined(IN_RING0)
729	# define VM_ASSERT_EMT(pVM) Assert(VM_IS_EMT(pVM))
730	#else
731	# define VM_ASSERT_EMT(pVM) \
732	AssertMsg(VM_IS_EMT(pVM), \
733	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd\n", RTThreadNativeSelf(), VMR3GetVMCPUNativeThread(pVM)))
734	#endif
735
736	/** @def VMCPU_ASSERT_EMT
737	* Asserts that the current thread IS the emulation thread (EMT) of the
738	* specified virtual CPU.
739	*/
740	#ifdef IN_RC
741	# define VMCPU_ASSERT_EMT(pVCpu) Assert(VMCPU_IS_EMT(pVCpu))
742	#elif defined(IN_RING0)
743	# define VMCPU_ASSERT_EMT(pVCpu) AssertMsg(VMCPU_IS_EMT(pVCpu), \
744	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd idCpu=%u\n", \
745	RTThreadNativeSelf(), (pVCpu) ? (pVCpu)->hNativeThreadR0 : 0, \
746	(pVCpu) ? (pVCpu)->idCpu : 0))
747	#else
748	# define VMCPU_ASSERT_EMT(pVCpu) AssertMsg(VMCPU_IS_EMT(pVCpu), \
749	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd idCpu=%#x\n", \
750	RTThreadNativeSelf(), (pVCpu)->hNativeThread, (pVCpu)->idCpu))
751	#endif
752
753	/** @def VM_ASSERT_EMT_RETURN
754	* Asserts that the current thread IS the emulation thread (EMT) and returns if it isn't.
755	*/
756	#ifdef IN_RC
757	# define VM_ASSERT_EMT_RETURN(pVM, rc) AssertReturn(VM_IS_EMT(pVM), (rc))
758	#elif defined(IN_RING0)
759	# define VM_ASSERT_EMT_RETURN(pVM, rc) AssertReturn(VM_IS_EMT(pVM), (rc))
760	#else
761	# define VM_ASSERT_EMT_RETURN(pVM, rc) \
762	AssertMsgReturn(VM_IS_EMT(pVM), \
763	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd\n", RTThreadNativeSelf(), VMR3GetVMCPUNativeThread(pVM)), \
764	(rc))
765	#endif
766
767	/** @def VMCPU_ASSERT_EMT_RETURN
768	* Asserts that the current thread IS the emulation thread (EMT) and returns if it isn't.
769	*/
770	#ifdef IN_RC
771	# define VMCPU_ASSERT_EMT_RETURN(pVCpu, rc) AssertReturn(VMCPU_IS_EMT(pVCpu), (rc))
772	#elif defined(IN_RING0)
773	# define VMCPU_ASSERT_EMT_RETURN(pVCpu, rc) AssertReturn(VMCPU_IS_EMT(pVCpu), (rc))
774	#else
775	# define VMCPU_ASSERT_EMT_RETURN(pVCpu, rc) \
776	AssertMsgReturn(VMCPU_IS_EMT(pVCpu), \
777	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd idCpu=%#x\n", \
778	RTThreadNativeSelf(), (pVCpu)->hNativeThread, (pVCpu)->idCpu), \
779	(rc))
780	#endif
781
782	/** @def VMCPU_ASSERT_EMT_OR_GURU
783	* Asserts that the current thread IS the emulation thread (EMT) of the
784	* specified virtual CPU.
785	*/
786	#if defined(IN_RC) \|\| defined(IN_RING0)
787	# define VMCPU_ASSERT_EMT_OR_GURU(pVCpu) Assert( VMCPU_IS_EMT(pVCpu) \
788	\|\| pVCpu->CTX_SUFF(pVM)->enmVMState == VMSTATE_GURU_MEDITATION \
789	\|\| pVCpu->CTX_SUFF(pVM)->enmVMState == VMSTATE_GURU_MEDITATION_LS )
790	#else
791	# define VMCPU_ASSERT_EMT_OR_GURU(pVCpu) \
792	AssertMsg( VMCPU_IS_EMT(pVCpu) \
793	\|\| pVCpu->CTX_SUFF(pVM)->enmVMState == VMSTATE_GURU_MEDITATION \
794	\|\| pVCpu->CTX_SUFF(pVM)->enmVMState == VMSTATE_GURU_MEDITATION_LS, \
795	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd idCpu=%#x\n", \
796	RTThreadNativeSelf(), (pVCpu)->hNativeThread, (pVCpu)->idCpu))
797	#endif
798
799	/** @def VMCPU_ASSERT_EMT_OR_NOT_RUNNING
800	* Asserts that the current thread IS the emulation thread (EMT) of the
801	* specified virtual CPU or the VM is not running.
802	*/
803	#if defined(IN_RC) \|\| defined(IN_RING0)
804	# define VMCPU_ASSERT_EMT_OR_NOT_RUNNING(pVCpu) \
805	Assert( VMCPU_IS_EMT(pVCpu) \
806	\|\| !VM_IS_RUNNING((pVCpu)->CTX_SUFF(pVM)) )
807	#else
808	# define VMCPU_ASSERT_EMT_OR_NOT_RUNNING(pVCpu) \
809	AssertMsg( VMCPU_IS_EMT(pVCpu) \
810	\|\| !VM_IS_RUNNING((pVCpu)->CTX_SUFF(pVM)), \
811	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd idCpu=%#x\n", \
812	RTThreadNativeSelf(), (pVCpu)->hNativeThread, (pVCpu)->idCpu))
813	#endif
814
815	/** @def VM_IS_RUNNING
816	* Checks if the the VM is running.
817	*/
818	#define VM_IS_RUNNING(pVM) ( (pVM)->enmVMState == VMSTATE_RUNNING \
819	\|\| (pVM)->enmVMState == VMSTATE_RUNNING_LS \
820	\|\| (pVM)->enmVMState == VMSTATE_RUNNING_FT)
821
822	/** @def VM_ASSERT_IS_NOT_RUNNING
823	* Asserts that the VM is not running.
824	*/
825	#if defined(IN_RC) \|\| defined(IN_RING0)
826	#define VM_ASSERT_IS_NOT_RUNNING(pVM) Assert(!VM_IS_RUNNING(pVM))
827	#else
828	#define VM_ASSERT_IS_NOT_RUNNING(pVM) AssertMsg(!VM_IS_RUNNING(pVM), ("VM is running. enmVMState=%d\n", \
829	(pVM)->enmVMState))
830	#endif
831
832	/** @def VM_ASSERT_EMT0
833	* Asserts that the current thread IS emulation thread \#0 (EMT0).
834	*/
835	#define VM_ASSERT_EMT0(pVM) VMCPU_ASSERT_EMT(&(pVM)->aCpus[0])
836
837	/** @def VM_ASSERT_EMT0_RETURN
838	* Asserts that the current thread IS emulation thread \#0 (EMT0) and returns if
839	* it isn't.
840	*/
841	#define VM_ASSERT_EMT0_RETURN(pVM, rc) VMCPU_ASSERT_EMT_RETURN(&(pVM)->aCpus[0], (rc))
842
843
844	/**
845	* Asserts that the current thread is NOT the emulation thread.
846	*/
847	#define VM_ASSERT_OTHER_THREAD(pVM) \
848	AssertMsg(!VM_IS_EMT(pVM), ("Not other thread!!\n"))
849
850
851	/** @def VM_ASSERT_STATE
852	* Asserts a certain VM state.
853	*/
854	#define VM_ASSERT_STATE(pVM, _enmState) \
855	AssertMsg((pVM)->enmVMState == (_enmState), \
856	("state %s, expected %s\n", VMGetStateName((pVM)->enmVMState), VMGetStateName(_enmState)))
857
858	/** @def VM_ASSERT_STATE_RETURN
859	* Asserts a certain VM state and returns if it doesn't match.
860	*/
861	#define VM_ASSERT_STATE_RETURN(pVM, _enmState, rc) \
862	AssertMsgReturn((pVM)->enmVMState == (_enmState), \
863	("state %s, expected %s\n", VMGetStateName((pVM)->enmVMState), VMGetStateName(_enmState)), \
864	(rc))
865
866	/** @def VM_IS_VALID_EXT
867	* Asserts a the VM handle is valid for external access, i.e. not being destroy
868	* or terminated. */
869	#define VM_IS_VALID_EXT(pVM) \
870	( RT_VALID_ALIGNED_PTR(pVM, PAGE_SIZE) \
871	&& ( (unsigned)(pVM)->enmVMState < (unsigned)VMSTATE_DESTROYING \
872	\|\| ( (unsigned)(pVM)->enmVMState == (unsigned)VMSTATE_DESTROYING \
873	&& VM_IS_EMT(pVM))) )
874
875	/** @def VM_ASSERT_VALID_EXT_RETURN
876	* Asserts a the VM handle is valid for external access, i.e. not being
877	* destroy or terminated.
878	*/
879	#define VM_ASSERT_VALID_EXT_RETURN(pVM, rc) \
880	AssertMsgReturn(VM_IS_VALID_EXT(pVM), \
881	("pVM=%p state %s\n", (pVM), RT_VALID_ALIGNED_PTR(pVM, PAGE_SIZE) \
882	? VMGetStateName(pVM->enmVMState) : ""), \
883	(rc))
884
885	/** @def VMCPU_ASSERT_VALID_EXT_RETURN
886	* Asserts a the VMCPU handle is valid for external access, i.e. not being
887	* destroy or terminated.
888	*/
889	#define VMCPU_ASSERT_VALID_EXT_RETURN(pVCpu, rc) \
890	AssertMsgReturn( RT_VALID_ALIGNED_PTR(pVCpu, 64) \
891	&& RT_VALID_ALIGNED_PTR((pVCpu)->CTX_SUFF(pVM), PAGE_SIZE) \
892	&& (unsigned)(pVCpu)->CTX_SUFF(pVM)->enmVMState < (unsigned)VMSTATE_DESTROYING, \
893	("pVCpu=%p pVM=%p state %s\n", (pVCpu), RT_VALID_ALIGNED_PTR(pVCpu, 64) ? (pVCpu)->CTX_SUFF(pVM) : NULL, \
894	RT_VALID_ALIGNED_PTR(pVCpu, 64) && RT_VALID_ALIGNED_PTR((pVCpu)->CTX_SUFF(pVM), PAGE_SIZE) \
895	? VMGetStateName((pVCpu)->pVMR3->enmVMState) : ""), \
896	(rc))
897
898	#endif /* !VBOX_FOR_DTRACE_LIB */
899
900
901
902	/**
903	* The cross context VM structure.
904	*
905	* It contains all the VM data which have to be available in all contexts.
906	* Even if it contains all the data the idea is to use APIs not to modify all
907	* the members all around the place. Therefore we make use of unions to hide
908	* everything which isn't local to the current source module. This means we'll
909	* have to pay a little bit of attention when adding new members to structures
910	* in the unions and make sure to keep the padding sizes up to date.
911	*
912	* Run 'kmk run-struct-tests' (from src/VBox/VMM if you like) after updating!
913	*/
914	typedef struct VM
915	{
916	/** The state of the VM.
917	* This field is read only to everyone except the VM and EM. */
918	VMSTATE volatile enmVMState;
919	/** Forced action flags.
920	* See the VM_FF_* \#defines. Updated atomically.
921	*/
922	volatile uint32_t fGlobalForcedActions;
923	/** Pointer to the array of page descriptors for the VM structure allocation. */
924	R3PTRTYPE(PSUPPAGE) paVMPagesR3;
925	/** Session handle. For use when calling SUPR0 APIs. */
926	PSUPDRVSESSION pSession;
927	/** Pointer to the ring-3 VM structure. */
928	PUVM pUVM;
929	/** Ring-3 Host Context VM Pointer. */
930	R3PTRTYPE(struct VM *) pVMR3;
931	/** Ring-0 Host Context VM Pointer. */
932	R0PTRTYPE(struct VM *) pVMR0;
933	/** Raw-mode Context VM Pointer. */
934	RCPTRTYPE(struct VM *) pVMRC;
935
936	/** The GVM VM handle. Only the GVM should modify this field. */
937	uint32_t hSelf;
938	/** Number of virtual CPUs. */
939	uint32_t cCpus;
940	/** CPU excution cap (1-100) */
941	uint32_t uCpuExecutionCap;
942
943	/** Size of the VM structure including the VMCPU array. */
944	uint32_t cbSelf;
945
946	/** Offset to the VMCPU array starting from beginning of this structure. */
947	uint32_t offVMCPU;
948
949	/**
950	* VMMSwitcher assembly entry point returning to host context.
951	*
952	* Depending on how the host handles the rc status given in @a eax, this may
953	* return and let the caller resume whatever it was doing prior to the call.
954	*
955	*
956	* @param eax The return code, register.
957	* @remark Assume interrupts disabled.
958	* @remark This method pointer lives here because TRPM needs it.
959	*/
960	RTRCPTR pfnVMMRCToHostAsm/(int32_t eax)/;
961
962	/**
963	* VMMSwitcher assembly entry point returning to host context without saving the
964	* raw-mode context (hyper) registers.
965	*
966	* Unlike pfnVMMRC2HCAsm, this will not return to the caller. Instead it
967	* expects the caller to save a RC context in CPUM where one might return if the
968	* return code indicate that this is possible.
969	*
970	* This method pointer lives here because TRPM needs it.
971	*
972	* @param eax The return code, register.
973	* @remark Assume interrupts disabled.
974	* @remark This method pointer lives here because TRPM needs it.
975	*/
976	RTRCPTR pfnVMMRCToHostAsmNoReturn/(int32_t eax)/;
977
978	/** @name Various items that are frequently accessed.
979	* @{ */
980	/** Whether to recompile user mode code or run it raw/hm. */
981	bool fRecompileUser;
982	/** Whether to recompile supervisor mode code or run it raw/hm. */
983	bool fRecompileSupervisor;
984	/** Whether raw mode supports ring-1 code or not. */
985	bool fRawRing1Enabled;
986	/** PATM enabled flag.
987	* This is placed here for performance reasons. */
988	bool fPATMEnabled;
989	/** CSAM enabled flag.
990	* This is placed here for performance reasons. */
991	bool fCSAMEnabled;
992	/** Hardware VM support is available and enabled.
993	* Determined very early during init.
994	* This is placed here for performance reasons. */
995	bool fHMEnabled;
996	/** For asserting on fHMEnable usage. */
997	bool fHMEnabledFixed;
998	/** Hardware VM support requires a minimal raw-mode context.
999	* This is never set on 64-bit hosts, only 32-bit hosts requires it. */
1000	bool fHMNeedRawModeCtx;
1001	/** Set when this VM is the master FT node.
1002	* @todo This doesn't need to be here, FTM should store it in it's own
1003	* structures instead. */
1004	bool fFaultTolerantMaster;
1005	/** Large page enabled flag.
1006	* @todo This doesn't need to be here, PGM should store it in it's own
1007	* structures instead. */
1008	bool fUseLargePages;
1009	/** @} */
1010
1011	/** Alignment padding. */
1012	uint8_t uPadding1[2];
1013
1014	/** @name Debugging
1015	* @{ */
1016	/** Raw-mode Context VM Pointer. */
1017	RCPTRTYPE(RTTRACEBUF) hTraceBufRC;
1018	/** Ring-3 Host Context VM Pointer. */
1019	R3PTRTYPE(RTTRACEBUF) hTraceBufR3;
1020	/** Ring-0 Host Context VM Pointer. */
1021	R0PTRTYPE(RTTRACEBUF) hTraceBufR0;
1022	/** @} */
1023
1024	#if HC_ARCH_BITS == 32
1025	/** Alignment padding. */
1026	uint32_t uPadding2;
1027	#endif
1028
1029	/** @name Switcher statistics (remove)
1030	* @{ */
1031	/** Profiling the total time from Qemu to GC. */
1032	STAMPROFILEADV StatTotalQemuToGC;
1033	/** Profiling the total time from GC to Qemu. */
1034	STAMPROFILEADV StatTotalGCToQemu;
1035	/** Profiling the total time spent in GC. */
1036	STAMPROFILEADV StatTotalInGC;
1037	/** Profiling the total time spent not in Qemu. */
1038	STAMPROFILEADV StatTotalInQemu;
1039	/** Profiling the VMMSwitcher code for going to GC. */
1040	STAMPROFILEADV StatSwitcherToGC;
1041	/** Profiling the VMMSwitcher code for going to HC. */
1042	STAMPROFILEADV StatSwitcherToHC;
1043	STAMPROFILEADV StatSwitcherSaveRegs;
1044	STAMPROFILEADV StatSwitcherSysEnter;
1045	STAMPROFILEADV StatSwitcherDebug;
1046	STAMPROFILEADV StatSwitcherCR0;
1047	STAMPROFILEADV StatSwitcherCR4;
1048	STAMPROFILEADV StatSwitcherJmpCR3;
1049	STAMPROFILEADV StatSwitcherRstrRegs;
1050	STAMPROFILEADV StatSwitcherLgdt;
1051	STAMPROFILEADV StatSwitcherLidt;
1052	STAMPROFILEADV StatSwitcherLldt;
1053	STAMPROFILEADV StatSwitcherTSS;
1054	/** @} */
1055
1056	/** Padding - the unions must be aligned on a 64 bytes boundary and the unions
1057	* must start at the same offset on both 64-bit and 32-bit hosts. */
1058	uint8_t abAlignment3[(HC_ARCH_BITS == 32 ? 24 : 0) + 40];
1059
1060	/** CPUM part. */
1061	union
1062	{
1063	#ifdef ___CPUMInternal_h
1064	struct CPUM s;
1065	#endif
1066	#ifdef ___VBox_vmm_cpum_h
1067	/** Read only info exposed about the host and guest CPUs. */
1068	struct
1069	{
1070	/** Padding for hidden fields. */
1071	uint8_t abHidden0[64];
1072	/** Host CPU feature information. */
1073	CPUMFEATURES HostFeatures;
1074	/** Guest CPU feature information. */
1075	CPUMFEATURES GuestFeatures;
1076	} const ro;
1077	#endif
1078	uint8_t padding[1536]; /* multiple of 64 */
1079	} cpum;
1080
1081	/** VMM part. */
1082	union
1083	{
1084	#ifdef ___VMMInternal_h
1085	struct VMM s;
1086	#endif
1087	uint8_t padding[1600]; /* multiple of 64 */
1088	} vmm;
1089
1090	/** PGM part. */
1091	union
1092	{
1093	#ifdef ___PGMInternal_h
1094	struct PGM s;
1095	#endif
1096	uint8_t padding[40962+6080]; / multiple of 64 */
1097	} pgm;
1098
1099	/** HM part. */
1100	union
1101	{
1102	#ifdef ___HMInternal_h
1103	struct HM s;
1104	#endif
1105	uint8_t padding[5440]; /* multiple of 64 */
1106	} hm;
1107
1108	/** TRPM part. */
1109	union
1110	{
1111	#ifdef ___TRPMInternal_h
1112	struct TRPM s;
1113	#endif
1114	uint8_t padding[5248]; /* multiple of 64 */
1115	} trpm;
1116
1117	/** SELM part. */
1118	union
1119	{
1120	#ifdef ___SELMInternal_h
1121	struct SELM s;
1122	#endif
1123	uint8_t padding[768]; /* multiple of 64 */
1124	} selm;
1125
1126	/** MM part. */
1127	union
1128	{
1129	#ifdef ___MMInternal_h
1130	struct MM s;
1131	#endif
1132	uint8_t padding[192]; /* multiple of 64 */
1133	} mm;
1134
1135	/** PDM part. */
1136	union
1137	{
1138	#ifdef ___PDMInternal_h
1139	struct PDM s;
1140	#endif
1141	uint8_t padding[1920]; /* multiple of 64 */
1142	} pdm;
1143
1144	/** IOM part. */
1145	union
1146	{
1147	#ifdef ___IOMInternal_h
1148	struct IOM s;
1149	#endif
1150	uint8_t padding[896]; /* multiple of 64 */
1151	} iom;
1152
1153	/** PATM part. */
1154	union
1155	{
1156	#ifdef ___PATMInternal_h
1157	struct PATM s;
1158	#endif
1159	uint8_t padding[768]; /* multiple of 64 */
1160	} patm;
1161
1162	/** CSAM part. */
1163	union
1164	{
1165	#ifdef ___CSAMInternal_h
1166	struct CSAM s;
1167	#endif
1168	uint8_t padding[1088]; /* multiple of 64 */
1169	} csam;
1170
1171	/** EM part. */
1172	union
1173	{
1174	#ifdef ___EMInternal_h
1175	struct EM s;
1176	#endif
1177	uint8_t padding[256]; /* multiple of 64 */
1178	} em;
1179
1180	/** TM part. */
1181	union
1182	{
1183	#ifdef ___TMInternal_h
1184	struct TM s;
1185	#endif
1186	uint8_t padding[2496]; /* multiple of 64 */
1187	} tm;
1188
1189	/** DBGF part. */
1190	union
1191	{
1192	#ifdef ___DBGFInternal_h
1193	struct DBGF s;
1194	#endif
1195	#ifdef ___VBox_vmm_dbgf_h
1196	/** Read only info exposed about interrupt breakpoints and selected events. */
1197	struct
1198	{
1199	/** Bitmap of enabled hardware interrupt breakpoints. */
1200	uint32_t bmHardIntBreakpoints[256 / 32];
1201	/** Bitmap of enabled software interrupt breakpoints. */
1202	uint32_t bmSoftIntBreakpoints[256 / 32];
1203	/** Bitmap of selected events.
1204	* This includes non-selectable events too for simplicity, we maintain the
1205	* state for some of these, as it may come in handy. */
1206	uint64_t bmSelectedEvents[(DBGFEVENT_END + 63) / 64];
1207	/** Enabled hardware interrupt breakpoints. */
1208	uint32_t cHardIntBreakpoints;
1209	/** Enabled software interrupt breakpoints. */
1210	uint32_t cSoftIntBreakpoints;
1211	/** Number of selected events. */
1212	uint32_t cSelectedEvents;
1213	} const ro;
1214	#endif
1215	uint8_t padding[2368]; /* multiple of 64 */
1216	} dbgf;
1217
1218	/** SSM part. */
1219	union
1220	{
1221	#ifdef ___SSMInternal_h
1222	struct SSM s;
1223	#endif
1224	uint8_t padding[128]; /* multiple of 64 */
1225	} ssm;
1226
1227	/** FTM part. */
1228	union
1229	{
1230	#ifdef ___FTMInternal_h
1231	struct FTM s;
1232	#endif
1233	uint8_t padding[512]; /* multiple of 64 */
1234	} ftm;
1235
1236	/** REM part. */
1237	union
1238	{
1239	#ifdef ___REMInternal_h
1240	struct REM s;
1241	#endif
1242	uint8_t padding[0x11100]; /* multiple of 64 */
1243	} rem;
1244
1245	union
1246	{
1247	#ifdef ___GIMInternal_h
1248	struct GIM s;
1249	#endif
1250	uint8_t padding[448]; /* multiple of 64 */
1251	} gim;
1252
1253	/* ---- begin small stuff ---- */
1254
1255	/** VM part. */
1256	union
1257	{
1258	#ifdef ___VMInternal_h
1259	struct VMINT s;
1260	#endif
1261	uint8_t padding[24]; /* multiple of 8 */
1262	} vm;
1263
1264	/** CFGM part. */
1265	union
1266	{
1267	#ifdef ___CFGMInternal_h
1268	struct CFGM s;
1269	#endif
1270	uint8_t padding[8]; /* multiple of 8 */
1271	} cfgm;
1272
1273	#ifdef VBOX_WITH_NEW_APIC
1274	union
1275	{
1276	# ifdef ___APICInternal_h
1277	struct APIC s;
1278	# endif
1279	uint8_t padding[128]; /* multiple of 8 */
1280	} apic;
1281	#endif
1282
1283	/** Padding for aligning the cpu array on a page boundary. */
1284	#ifdef VBOX_WITH_NEW_APIC
1285	uint8_t abAlignment2[3870];
1286	#else
1287	uint8_t abAlignment2[3998];
1288	#endif
1289
1290	/* ---- end small stuff ---- */
1291
1292	/** VMCPU array for the configured number of virtual CPUs.
1293	* Must be aligned on a page boundary for TLB hit reasons as well as
1294	* alignment of VMCPU members. */
1295	VMCPU aCpus[1];
1296	} VM;
1297
1298
1299	#ifdef IN_RC
1300	RT_C_DECLS_BEGIN
1301
1302	/** The VM structure.
1303	* This is imported from the VMMRCBuiltin module, i.e. it's a one of those magic
1304	* globals which we should avoid using.
1305	*/
1306	extern DECLIMPORT(VM) g_VM;
1307
1308	RT_C_DECLS_END
1309	#endif
1310
1311	/** @} */
1312
1313	#endif
1314

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source: vbox/trunk/include/VBox/vmm/vm.h@ 61144

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