vm.h@ 61628

Last change on this file since 61628 was 61628, checked in by vboxsync, 8 years ago
DBGF: Added bsod_msr event, stubbed bsod_efi event. Since we cannot return VINF_EM_DBG_EVENT from an MSR handler, VMCPU_FF_DBGF was introduced as an alternative.
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1	/** @file
2	* VM - The Virtual Machine, data.
3	*/
4
5	/*
6	* Copyright (C) 2006-2015 Oracle Corporation
7	*
8	* This file is part of VirtualBox Open Source Edition (OSE), as
9	* available from http://www.virtualbox.org. This file is free software;
10	* you can redistribute it and/or modify it under the terms of the GNU
11	* General Public License (GPL) as published by the Free Software
12	* Foundation, in version 2 as it comes in the "COPYING" file of the
13	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15	*
16	* The contents of this file may alternatively be used under the terms
17	* of the Common Development and Distribution License Version 1.0
18	* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19	* VirtualBox OSE distribution, in which case the provisions of the
20	* CDDL are applicable instead of those of the GPL.
21	*
22	* You may elect to license modified versions of this file under the
23	* terms and conditions of either the GPL or the CDDL or both.
24	*/
25
26	#ifndef ___VBox_vmm_vm_h
27	#define ___VBox_vmm_vm_h
28
29	#ifndef VBOX_FOR_DTRACE_LIB
30	# include <iprt/param.h>
31	# include <VBox/types.h>
32	# include <VBox/vmm/cpum.h>
33	# include <VBox/vmm/stam.h>
34	# include <VBox/vmm/vmapi.h>
35	# include <VBox/vmm/vmm.h>
36	# include <VBox/sup.h>
37	#else
38	# pragma D depends_on library vbox-types.d
39	# pragma D depends_on library CPUMInternal.d
40	# define ___CPUMInternal_h
41	#endif
42
43
44
45	/** @defgroup grp_vm The Virtual Machine
46	* @ingroup grp_vmm
47	* @{
48	*/
49
50	/**
51	* The state of a Virtual CPU.
52	*
53	* The basic state indicated here is whether the CPU has been started or not. In
54	* addition, there are sub-states when started for assisting scheduling (GVMM
55	* mostly).
56	*
57	* The transition out of the STOPPED state is done by a vmR3PowerOn.
58	* The transition back to the STOPPED state is done by vmR3PowerOff.
59	*
60	* (Alternatively we could let vmR3PowerOn start CPU 0 only and let the SPIP
61	* handling switch on the other CPUs. Then vmR3Reset would stop all but CPU 0.)
62	*/
63	typedef enum VMCPUSTATE
64	{
65	/** The customary invalid zero. */
66	VMCPUSTATE_INVALID = 0,
67
68	/** Virtual CPU has not yet been started. */
69	VMCPUSTATE_STOPPED,
70
71	/** CPU started. */
72	VMCPUSTATE_STARTED,
73	/** CPU started in HM context. */
74	VMCPUSTATE_STARTED_HM,
75	/** Executing guest code and can be poked (RC or STI bits of HM). */
76	VMCPUSTATE_STARTED_EXEC,
77	/** Executing guest code in the recompiler. */
78	VMCPUSTATE_STARTED_EXEC_REM,
79	/** Halted. */
80	VMCPUSTATE_STARTED_HALTED,
81
82	/** The end of valid virtual CPU states. */
83	VMCPUSTATE_END,
84
85	/** Ensure 32-bit type. */
86	VMCPUSTATE_32BIT_HACK = 0x7fffffff
87	} VMCPUSTATE;
88
89
90	/**
91	* The cross context virtual CPU structure.
92	*
93	* Run 'kmk run-struct-tests' (from src/VBox/VMM if you like) after updating!
94	*/
95	typedef struct VMCPU
96	{
97	/** Per CPU forced action.
98	* See the VMCPU_FF_* \#defines. Updated atomically. */
99	uint32_t volatile fLocalForcedActions; /* 0 */
100	/** The CPU state. */
101	VMCPUSTATE volatile enmState; /* 4 */
102
103	/** Pointer to the ring-3 UVMCPU structure. */
104	PUVMCPU pUVCpu; /* 8 */
105	/** Ring-3 Host Context VM Pointer. */
106	PVMR3 pVMR3; /* 16 / 12 */
107	/** Ring-0 Host Context VM Pointer. */
108	PVMR0 pVMR0; /* 24 / 16 */
109	/** Raw-mode Context VM Pointer. */
110	PVMRC pVMRC; /* 32 / 20 */
111	/** The CPU ID.
112	* This is the index into the VM::aCpu array. */
113	VMCPUID idCpu; /* 36 / 24 */
114	/** The native thread handle. */
115	RTNATIVETHREAD hNativeThread; /* 40 / 28 */
116	/** The native R0 thread handle. (different from the R3 handle!) */
117	RTNATIVETHREAD hNativeThreadR0; /* 48 / 32 */
118	/** Which host CPU ID is this EMT running on.
119	* Only valid when in RC or HMR0 with scheduling disabled. */
120	RTCPUID volatile idHostCpu; /* 56 / 36 */
121	/** The CPU set index corresponding to idHostCpu, UINT32_MAX if not valid.
122	* @remarks Best to make sure iHostCpuSet shares cache line with idHostCpu! */
123	uint32_t volatile iHostCpuSet; /* 60 / 40 */
124
125	/** Trace groups enable flags. */
126	uint32_t fTraceGroups; /* 64 / 44 */
127	/** Align the structures below bit on a 64-byte boundary and make sure it starts
128	* at the same offset in both 64-bit and 32-bit builds.
129	*
130	* @remarks The alignments of the members that are larger than 48 bytes should be
131	* 64-byte for cache line reasons. structs containing small amounts of
132	* data could be lumped together at the end with a < 64 byte padding
133	* following it (to grow into and align the struct size).
134	*/
135	uint8_t abAlignment1[HC_ARCH_BITS == 64 ? 56 : 12+64];
136	/** State data for use by ad hoc profiling. */
137	uint32_t uAdHoc;
138	/** Profiling samples for use by ad hoc profiling. */
139	STAMPROFILEADV aStatAdHoc[8]; /* size: 408 = 320 /
140
141	/** HM part. */
142	union
143	{
144	#ifdef ___HMInternal_h
145	struct HMCPU s;
146	#endif
147	uint8_t padding[5760]; /* multiple of 64 */
148	} hm;
149
150	/** EM part. */
151	union
152	{
153	#ifdef ___EMInternal_h
154	struct EMCPU s;
155	#endif
156	uint8_t padding[1408]; /* multiple of 64 */
157	} em;
158
159	/** IEM part. */
160	union
161	{
162	#ifdef ___IEMInternal_h
163	struct IEMCPU s;
164	#endif
165	uint8_t padding[3072]; /* multiple of 64 */
166	} iem;
167
168	/** TRPM part. */
169	union
170	{
171	#ifdef ___TRPMInternal_h
172	struct TRPMCPU s;
173	#endif
174	uint8_t padding[128]; /* multiple of 64 */
175	} trpm;
176
177	/** TM part. */
178	union
179	{
180	#ifdef ___TMInternal_h
181	struct TMCPU s;
182	#endif
183	uint8_t padding[384]; /* multiple of 64 */
184	} tm;
185
186	/** VMM part. */
187	union
188	{
189	#ifdef ___VMMInternal_h
190	struct VMMCPU s;
191	#endif
192	uint8_t padding[704]; /* multiple of 64 */
193	} vmm;
194
195	/** PDM part. */
196	union
197	{
198	#ifdef ___PDMInternal_h
199	struct PDMCPU s;
200	#endif
201	uint8_t padding[256]; /* multiple of 64 */
202	} pdm;
203
204	/** IOM part. */
205	union
206	{
207	#ifdef ___IOMInternal_h
208	struct IOMCPU s;
209	#endif
210	uint8_t padding[512]; /* multiple of 64 */
211	} iom;
212
213	/** DBGF part.
214	* @todo Combine this with other tiny structures. */
215	union
216	{
217	#ifdef ___DBGFInternal_h
218	struct DBGFCPU s;
219	#endif
220	uint8_t padding[256]; /* multiple of 64 */
221	} dbgf;
222
223	/** GIM part. */
224	union
225	{
226	#ifdef ___GIMInternal_h
227	struct GIMCPU s;
228	#endif
229	uint8_t padding[64]; /* multiple of 64 */
230	} gim;
231
232	#ifdef VBOX_WITH_NEW_APIC
233	/** APIC part. */
234	union
235	{
236	# ifdef ___APICInternal_h
237	struct APICCPU s;
238	# endif
239	uint8_t padding[768]; /* multiple of 64 */
240	} apic;
241	#endif
242
243	/** Align the following members on page boundary. */
244	#ifdef VBOX_WITH_NEW_APIC
245	uint8_t abAlignment2[2624];
246	#else
247	uint8_t abAlignment2[3392];
248	#endif
249
250	/** PGM part. */
251	union
252	{
253	#ifdef ___PGMInternal_h
254	struct PGMCPU s;
255	#endif
256	uint8_t padding[4096]; /* multiple of 4096 */
257	} pgm;
258
259	/** CPUM part. */
260	union
261	{
262	#ifdef ___CPUMInternal_h
263	struct CPUMCPU s;
264	#endif
265	uint8_t padding[4096]; /* multiple of 4096 */
266	} cpum;
267	} VMCPU;
268
269
270	#ifndef VBOX_FOR_DTRACE_LIB
271
272	/** @name Operations on VMCPU::enmState
273	* @{ */
274	/** Gets the VMCPU state. */
275	#define VMCPU_GET_STATE(pVCpu) ( (pVCpu)->enmState )
276	/** Sets the VMCPU state. */
277	#define VMCPU_SET_STATE(pVCpu, enmNewState) \
278	ASMAtomicWriteU32((uint32_t volatile *)&(pVCpu)->enmState, (enmNewState))
279	/** Cmpares and sets the VMCPU state. */
280	#define VMCPU_CMPXCHG_STATE(pVCpu, enmNewState, enmOldState) \
281	ASMAtomicCmpXchgU32((uint32_t volatile *)&(pVCpu)->enmState, (enmNewState), (enmOldState))
282	/** Checks the VMCPU state. */
283	#ifdef VBOX_STRICT
284	# define VMCPU_ASSERT_STATE(pVCpu, enmExpectedState) \
285	do { \
286	VMCPUSTATE enmState = VMCPU_GET_STATE(pVCpu); \
287	AssertMsg(enmState == (enmExpectedState), \
288	("enmState=%d enmExpectedState=%d idCpu=%u\n", \
289	enmState, enmExpectedState, (pVCpu)->idCpu)); \
290	} while (0)
291	#else
292	# define VMCPU_ASSERT_STATE(pVCpu, enmExpectedState) do { } while (0)
293	#endif
294	/** Tests if the state means that the CPU is started. */
295	#define VMCPUSTATE_IS_STARTED(enmState) ( (enmState) > VMCPUSTATE_STOPPED )
296	/** Tests if the state means that the CPU is stopped. */
297	#define VMCPUSTATE_IS_STOPPED(enmState) ( (enmState) == VMCPUSTATE_STOPPED )
298	/** @} */
299
300
301	/** The name of the raw-mode context VMM Core module. */
302	#define VMMRC_MAIN_MODULE_NAME "VMMRC.rc"
303	/** The name of the ring-0 context VMM Core module. */
304	#define VMMR0_MAIN_MODULE_NAME "VMMR0.r0"
305
306	/**
307	* Wrapper macro for avoiding too much \#ifdef VBOX_WITH_RAW_MODE.
308	*/
309	#ifdef VBOX_WITH_RAW_MODE
310	# define VM_WHEN_RAW_MODE(a_WithExpr, a_WithoutExpr) a_WithExpr
311	#else
312	# define VM_WHEN_RAW_MODE(a_WithExpr, a_WithoutExpr) a_WithoutExpr
313	#endif
314
315
316	/** VM Forced Action Flags.
317	*
318	* Use the VM_FF_SET() and VM_FF_CLEAR() macros to change the force
319	* action mask of a VM.
320	*
321	* Available VM bits:
322	* 0, 1, 5, 6, 7, 13, 14, 15, 16, 17, 21, 22, 23, 24, 25, 26, 27, 28, 30
323	*
324	*
325	* Available VMCPU bits:
326	* 11, 14, 15, 31
327	*
328	* @todo If we run low on VMCPU, we may consider merging the SELM bits
329	*
330	* @{
331	*/
332	/** The virtual sync clock has been stopped, go to TM until it has been
333	* restarted... */
334	#define VM_FF_TM_VIRTUAL_SYNC RT_BIT_32(2)
335	/** PDM Queues are pending. */
336	#define VM_FF_PDM_QUEUES RT_BIT_32(VM_FF_PDM_QUEUES_BIT)
337	/** The bit number for VM_FF_PDM_QUEUES. */
338	#define VM_FF_PDM_QUEUES_BIT 3
339	/** PDM DMA transfers are pending. */
340	#define VM_FF_PDM_DMA RT_BIT_32(VM_FF_PDM_DMA_BIT)
341	/** The bit number for VM_FF_PDM_DMA. */
342	#define VM_FF_PDM_DMA_BIT 4
343	/** This action forces the VM to call DBGF so DBGF can service debugger
344	* requests in the emulation thread.
345	* This action flag stays asserted till DBGF clears it.*/
346	#define VM_FF_DBGF RT_BIT_32(VM_FF_DBGF_BIT)
347	/** The bit number for VM_FF_DBGF. */
348	#define VM_FF_DBGF_BIT 8
349	/** This action forces the VM to service pending requests from other
350	* thread or requests which must be executed in another context. */
351	#define VM_FF_REQUEST RT_BIT_32(9)
352	/** Check for VM state changes and take appropriate action. */
353	#define VM_FF_CHECK_VM_STATE RT_BIT_32(VM_FF_CHECK_VM_STATE_BIT)
354	/** The bit number for VM_FF_CHECK_VM_STATE. */
355	#define VM_FF_CHECK_VM_STATE_BIT 10
356	/** Reset the VM. (postponed) */
357	#define VM_FF_RESET RT_BIT_32(VM_FF_RESET_BIT)
358	/** The bit number for VM_FF_RESET. */
359	#define VM_FF_RESET_BIT 11
360	/** EMT rendezvous in VMM. */
361	#define VM_FF_EMT_RENDEZVOUS RT_BIT_32(VM_FF_EMT_RENDEZVOUS_BIT)
362	/** The bit number for VM_FF_EMT_RENDEZVOUS. */
363	#define VM_FF_EMT_RENDEZVOUS_BIT 12
364
365	/** PGM needs to allocate handy pages. */
366	#define VM_FF_PGM_NEED_HANDY_PAGES RT_BIT_32(18)
367	/** PGM is out of memory.
368	* Abandon all loops and code paths which can be resumed and get up to the EM
369	* loops. */
370	#define VM_FF_PGM_NO_MEMORY RT_BIT_32(19)
371	/** PGM is about to perform a lightweight pool flush
372	* Guest SMP: all EMT threads should return to ring 3
373	*/
374	#define VM_FF_PGM_POOL_FLUSH_PENDING RT_BIT_32(20)
375	/** REM needs to be informed about handler changes. */
376	#define VM_FF_REM_HANDLER_NOTIFY RT_BIT_32(VM_FF_REM_HANDLER_NOTIFY_BIT)
377	/** The bit number for VM_FF_REM_HANDLER_NOTIFY. */
378	#define VM_FF_REM_HANDLER_NOTIFY_BIT 29
379	/** Suspend the VM - debug only. */
380	#define VM_FF_DEBUG_SUSPEND RT_BIT_32(31)
381
382
383	/** This action forces the VM to check any pending interrupts on the APIC. */
384	#define VMCPU_FF_INTERRUPT_APIC RT_BIT_32(0)
385	/** This action forces the VM to check any pending interrups on the PIC. */
386	#define VMCPU_FF_INTERRUPT_PIC RT_BIT_32(1)
387	/** This action forces the VM to schedule and run pending timer (TM).
388	* @remarks Don't move - PATM compatibility. */
389	#define VMCPU_FF_TIMER RT_BIT_32(2)
390	/** This action forces the VM to check any pending NMIs. */
391	#define VMCPU_FF_INTERRUPT_NMI_BIT 3
392	#define VMCPU_FF_INTERRUPT_NMI RT_BIT_32(VMCPU_FF_INTERRUPT_NMI_BIT)
393	/** This action forces the VM to check any pending SMIs. */
394	#define VMCPU_FF_INTERRUPT_SMI_BIT 4
395	#define VMCPU_FF_INTERRUPT_SMI RT_BIT_32(VMCPU_FF_INTERRUPT_SMI_BIT)
396	/** PDM critical section unlocking is pending, process promptly upon return to R3. */
397	#define VMCPU_FF_PDM_CRITSECT RT_BIT_32(5)
398	/** This action forces the VCPU out of the halted state. */
399	#define VMCPU_FF_UNHALT RT_BIT_32(6)
400	/** Pending IEM action (bit number). */
401	#define VMCPU_FF_IEM_BIT 7
402	/** Pending IEM action (mask). */
403	#define VMCPU_FF_IEM RT_BIT_32(VMCPU_FF_IEM_BIT)
404	/** Pending APIC action (bit number). */
405	#define VMCPU_FF_UPDATE_APIC_BIT 8
406	/** This action forces the VM to update APIC's asynchronously arrived
407	* interrupts as pending interrupts. */
408	#define VMCPU_FF_UPDATE_APIC RT_BIT_32(VMCPU_FF_UPDATE_APIC_BIT)
409	/** This action forces the VM to service pending requests from other
410	* thread or requests which must be executed in another context. */
411	#define VMCPU_FF_REQUEST RT_BIT_32(9)
412	/** Pending DBGF event (alternative to passing VINF_EM_DBG_EVENT around). */
413	#define VMCPU_FF_DBGF RT_BIT_32(VMCPU_FF_DBGF_BIT)
414	/** The bit number for VMCPU_FF_DBGF. */
415	#define VMCPU_FF_DBGF_BIT 10
416	/** This action forces the VM to service any pending updates to CR3 (used only
417	* by HM). */
418	#define VMCPU_FF_HM_UPDATE_CR3 RT_BIT_32(12)
419	/** This action forces the VM to service any pending updates to PAE PDPEs (used
420	* only by HM). */
421	#define VMCPU_FF_HM_UPDATE_PAE_PDPES RT_BIT_32(13)
422	/** This action forces the VM to resync the page tables before going
423	* back to execute guest code. (GLOBAL FLUSH) */
424	#define VMCPU_FF_PGM_SYNC_CR3 RT_BIT_32(16)
425	/** Same as VM_FF_PGM_SYNC_CR3 except that global pages can be skipped.
426	* (NON-GLOBAL FLUSH) */
427	#define VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL RT_BIT_32(17)
428	/** Check for pending TLB shootdown actions (deprecated)
429	* Reserved for furture HM re-use if necessary / safe.
430	* Consumer: HM */
431	#define VMCPU_FF_TLB_SHOOTDOWN_UNUSED RT_BIT_32(18)
432	/** Check for pending TLB flush action.
433	* Consumer: HM
434	* @todo rename to VMCPU_FF_HM_TLB_FLUSH */
435	#define VMCPU_FF_TLB_FLUSH RT_BIT_32(VMCPU_FF_TLB_FLUSH_BIT)
436	/** The bit number for VMCPU_FF_TLB_FLUSH. */
437	#define VMCPU_FF_TLB_FLUSH_BIT 19
438	#ifdef VBOX_WITH_RAW_MODE
439	/** Check the interrupt and trap gates */
440	# define VMCPU_FF_TRPM_SYNC_IDT RT_BIT_32(20)
441	/** Check Guest's TSS ring 0 stack */
442	# define VMCPU_FF_SELM_SYNC_TSS RT_BIT_32(21)
443	/** Check Guest's GDT table */
444	# define VMCPU_FF_SELM_SYNC_GDT RT_BIT_32(22)
445	/** Check Guest's LDT table */
446	# define VMCPU_FF_SELM_SYNC_LDT RT_BIT_32(23)
447	#endif /* VBOX_WITH_RAW_MODE */
448	/** Inhibit interrupts pending. See EMGetInhibitInterruptsPC(). */
449	#define VMCPU_FF_INHIBIT_INTERRUPTS RT_BIT_32(24)
450	/** Block injection of non-maskable interrupts to the guest. */
451	#define VMCPU_FF_BLOCK_NMIS RT_BIT_32(25)
452	#ifdef VBOX_WITH_RAW_MODE
453	/** CSAM needs to scan the page that's being executed */
454	# define VMCPU_FF_CSAM_SCAN_PAGE RT_BIT_32(26)
455	/** CSAM needs to do some homework. */
456	# define VMCPU_FF_CSAM_PENDING_ACTION RT_BIT_32(27)
457	#endif /* VBOX_WITH_RAW_MODE */
458	/** Force return to Ring-3. */
459	#define VMCPU_FF_TO_R3 RT_BIT_32(28)
460	/** Force return to ring-3 to service pending I/O or MMIO write.
461	* This is a backup for mechanism VINF_IOM_R3_IOPORT_COMMIT_WRITE and
462	* VINF_IOM_R3_MMIO_COMMIT_WRITE, allowing VINF_EM_DBG_BREAKPOINT and similar
463	* status codes to be propagated at the same time without loss. */
464	#define VMCPU_FF_IOM RT_BIT_32(29)
465	#ifdef VBOX_WITH_RAW_MODE
466	/** CPUM need to adjust CR0.TS/EM before executing raw-mode code again. */
467	# define VMCPU_FF_CPUM RT_BIT_32(VMCPU_FF_CPUM_BIT)
468	/** The bit number for VMCPU_FF_CPUM. */
469	# define VMCPU_FF_CPUM_BIT 30
470	#endif /* VBOX_WITH_RAW_MODE */
471
472	/** Externally VM forced actions. Used to quit the idle/wait loop. */
473	#define VM_FF_EXTERNAL_SUSPENDED_MASK ( VM_FF_CHECK_VM_STATE \| VM_FF_DBGF \| VM_FF_REQUEST \| VM_FF_EMT_RENDEZVOUS )
474	/** Externally VMCPU forced actions. Used to quit the idle/wait loop. */
475	#define VMCPU_FF_EXTERNAL_SUSPENDED_MASK ( VMCPU_FF_REQUEST \| VMCPU_FF_DBGF )
476
477	/** Externally forced VM actions. Used to quit the idle/wait loop. */
478	#define VM_FF_EXTERNAL_HALTED_MASK ( VM_FF_CHECK_VM_STATE \| VM_FF_DBGF \| VM_FF_REQUEST \
479	\| VM_FF_PDM_QUEUES \| VM_FF_PDM_DMA \| VM_FF_EMT_RENDEZVOUS )
480	/** Externally forced VMCPU actions. Used to quit the idle/wait loop. */
481	#define VMCPU_FF_EXTERNAL_HALTED_MASK ( VMCPU_FF_UPDATE_APIC \| VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC \
482	\| VMCPU_FF_REQUEST \| VMCPU_FF_INTERRUPT_NMI \| VMCPU_FF_INTERRUPT_SMI \
483	\| VMCPU_FF_UNHALT \| VMCPU_FF_TIMER \| VMCPU_FF_DBGF )
484
485	/** High priority VM pre-execution actions. */
486	#define VM_FF_HIGH_PRIORITY_PRE_MASK ( VM_FF_CHECK_VM_STATE \| VM_FF_DBGF \| VM_FF_TM_VIRTUAL_SYNC \
487	\| VM_FF_DEBUG_SUSPEND \| VM_FF_PGM_NEED_HANDY_PAGES \| VM_FF_PGM_NO_MEMORY \
488	\| VM_FF_EMT_RENDEZVOUS )
489	/** High priority VMCPU pre-execution actions. */
490	#define VMCPU_FF_HIGH_PRIORITY_PRE_MASK ( VMCPU_FF_TIMER \| VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC \
491	\| VMCPU_FF_UPDATE_APIC \| VMCPU_FF_INHIBIT_INTERRUPTS \| VMCPU_FF_DBGF \
492	\| VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL \
493	\| VM_WHEN_RAW_MODE( VMCPU_FF_SELM_SYNC_TSS \| VMCPU_FF_TRPM_SYNC_IDT \
494	\| VMCPU_FF_SELM_SYNC_GDT \| VMCPU_FF_SELM_SYNC_LDT, 0 ) )
495
496	/** High priority VM pre raw-mode execution mask. */
497	#define VM_FF_HIGH_PRIORITY_PRE_RAW_MASK ( VM_FF_PGM_NEED_HANDY_PAGES \| VM_FF_PGM_NO_MEMORY )
498	/** High priority VMCPU pre raw-mode execution mask. */
499	#define VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK ( VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL \
500	\| VMCPU_FF_INHIBIT_INTERRUPTS \
501	\| VM_WHEN_RAW_MODE( VMCPU_FF_SELM_SYNC_TSS \| VMCPU_FF_TRPM_SYNC_IDT \
502	\| VMCPU_FF_SELM_SYNC_GDT \| VMCPU_FF_SELM_SYNC_LDT, 0) )
503
504	/** High priority post-execution actions. */
505	#define VM_FF_HIGH_PRIORITY_POST_MASK ( VM_FF_PGM_NO_MEMORY )
506	/** High priority post-execution actions. */
507	#define VMCPU_FF_HIGH_PRIORITY_POST_MASK ( VMCPU_FF_PDM_CRITSECT \| VM_WHEN_RAW_MODE(VMCPU_FF_CSAM_PENDING_ACTION, 0) \
508	\| VMCPU_FF_HM_UPDATE_CR3 \| VMCPU_FF_HM_UPDATE_PAE_PDPES \
509	\| VMCPU_FF_IEM \| VMCPU_FF_IOM )
510
511	/** Normal priority VM post-execution actions. */
512	#define VM_FF_NORMAL_PRIORITY_POST_MASK ( VM_FF_CHECK_VM_STATE \| VM_FF_DBGF \| VM_FF_RESET \
513	\| VM_FF_PGM_NO_MEMORY \| VM_FF_EMT_RENDEZVOUS)
514	/** Normal priority VMCPU post-execution actions. */
515	#define VMCPU_FF_NORMAL_PRIORITY_POST_MASK ( VM_WHEN_RAW_MODE(VMCPU_FF_CSAM_SCAN_PAGE, 0) \| VMCPU_FF_DBGF )
516
517	/** Normal priority VM actions. */
518	#define VM_FF_NORMAL_PRIORITY_MASK ( VM_FF_REQUEST \| VM_FF_PDM_QUEUES \| VM_FF_PDM_DMA \
519	\| VM_FF_REM_HANDLER_NOTIFY \| VM_FF_EMT_RENDEZVOUS)
520	/** Normal priority VMCPU actions. */
521	#define VMCPU_FF_NORMAL_PRIORITY_MASK ( VMCPU_FF_REQUEST \| VMCPU_FF_UNHALT )
522
523	/** Flags to clear before resuming guest execution. */
524	#define VMCPU_FF_RESUME_GUEST_MASK ( VMCPU_FF_TO_R3 )
525
526
527	/** VM flags that cause the REP[\|NE\|E] STRINS loops to yield immediately. */
528	#define VM_FF_HIGH_PRIORITY_POST_REPSTR_MASK ( VM_FF_TM_VIRTUAL_SYNC \| VM_FF_PGM_NEED_HANDY_PAGES \| VM_FF_PGM_NO_MEMORY \
529	\| VM_FF_EMT_RENDEZVOUS \| VM_FF_PGM_POOL_FLUSH_PENDING \| VM_FF_RESET)
530	/** VM flags that cause the REP[\|NE\|E] STRINS loops to yield. */
531	#define VM_FF_YIELD_REPSTR_MASK ( VM_FF_HIGH_PRIORITY_POST_REPSTR_MASK \
532	\| VM_FF_PDM_QUEUES \| VM_FF_PDM_DMA \| VM_FF_DBGF \| VM_FF_DEBUG_SUSPEND )
533	/** VMCPU flags that cause the REP[\|NE\|E] STRINS loops to yield immediately. */
534	#ifdef IN_RING3
535	# define VMCPU_FF_HIGH_PRIORITY_POST_REPSTR_MASK ( VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL \| VMCPU_FF_DBGF )
536	#else
537	# define VMCPU_FF_HIGH_PRIORITY_POST_REPSTR_MASK ( VMCPU_FF_TO_R3 \| VMCPU_FF_IEM \| VMCPU_FF_IOM \| VMCPU_FF_PGM_SYNC_CR3 \
538	\| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL \| VMCPU_FF_DBGF )
539	#endif
540	/** VMCPU flags that cause the REP[\|NE\|E] STRINS loops to yield, interrupts
541	* enabled. */
542	#define VMCPU_FF_YIELD_REPSTR_MASK ( VMCPU_FF_HIGH_PRIORITY_POST_REPSTR_MASK \
543	\| VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_UPDATE_APIC \| VMCPU_FF_INTERRUPT_PIC \
544	\| VMCPU_FF_INTERRUPT_NMI \| VMCPU_FF_INTERRUPT_SMI \| VMCPU_FF_PDM_CRITSECT \
545	\| VMCPU_FF_TIMER \| VMCPU_FF_REQUEST )
546	/** VMCPU flags that cause the REP[\|NE\|E] STRINS loops to yield, interrupts
547	* disabled. */
548	#define VMCPU_FF_YIELD_REPSTR_NOINT_MASK ( VMCPU_FF_YIELD_REPSTR_MASK \
549	& ~(VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_UPDATE_APIC \| VMCPU_FF_INTERRUPT_PIC) )
550
551	/** VM Flags that cause the HM loops to go back to ring-3. */
552	#define VM_FF_HM_TO_R3_MASK ( VM_FF_TM_VIRTUAL_SYNC \| VM_FF_PGM_NEED_HANDY_PAGES \| VM_FF_PGM_NO_MEMORY \
553	\| VM_FF_PDM_QUEUES \| VM_FF_EMT_RENDEZVOUS)
554	/** VMCPU Flags that cause the HM loops to go back to ring-3. */
555	#define VMCPU_FF_HM_TO_R3_MASK ( VMCPU_FF_TO_R3 \| VMCPU_FF_TIMER \| VMCPU_FF_PDM_CRITSECT \
556	\| VMCPU_FF_IEM \| VMCPU_FF_IOM)
557
558	/** High priority ring-0 VM pre HM-mode execution mask. */
559	#define VM_FF_HP_R0_PRE_HM_MASK (VM_FF_HM_TO_R3_MASK \| VM_FF_REQUEST \| VM_FF_PGM_POOL_FLUSH_PENDING \| VM_FF_PDM_DMA)
560	/** High priority ring-0 VMCPU pre HM-mode execution mask. */
561	#define VMCPU_FF_HP_R0_PRE_HM_MASK ( VMCPU_FF_HM_TO_R3_MASK \| VMCPU_FF_PGM_SYNC_CR3 \
562	\| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL \| VMCPU_FF_REQUEST)
563	/** High priority ring-0 VM pre HM-mode execution mask, single stepping. */
564	#define VM_FF_HP_R0_PRE_HM_STEP_MASK (VM_FF_HP_R0_PRE_HM_MASK & ~( VM_FF_TM_VIRTUAL_SYNC \| VM_FF_PDM_QUEUES \
565	\| VM_FF_EMT_RENDEZVOUS \| VM_FF_REQUEST \
566	\| VM_FF_PDM_DMA) )
567	/** High priority ring-0 VMCPU pre HM-mode execution mask, single stepping. */
568	#define VMCPU_FF_HP_R0_PRE_HM_STEP_MASK (VMCPU_FF_HP_R0_PRE_HM_MASK & ~( VMCPU_FF_TO_R3 \| VMCPU_FF_TIMER \
569	\| VMCPU_FF_PDM_CRITSECT \| VMCPU_FF_REQUEST) )
570
571	/** All the forced VM flags. */
572	#define VM_FF_ALL_MASK (~0U)
573	/** All the forced VMCPU flags. */
574	#define VMCPU_FF_ALL_MASK (~0U)
575
576	/** All the forced VM flags except those related to raw-mode and hardware
577	* assisted execution. */
578	#define VM_FF_ALL_REM_MASK (~(VM_FF_HIGH_PRIORITY_PRE_RAW_MASK) \| VM_FF_PGM_NO_MEMORY)
579	/** All the forced VMCPU flags except those related to raw-mode and hardware
580	* assisted execution. */
581	#define VMCPU_FF_ALL_REM_MASK (~( VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK \| VMCPU_FF_PDM_CRITSECT \
582	\| VMCPU_FF_TLB_FLUSH \| VM_WHEN_RAW_MODE(VMCPU_FF_CSAM_PENDING_ACTION, 0) ))
583	/** @} */
584
585	/** @def VM_FF_SET
586	* Sets a force action flag.
587	*
588	* @param pVM The cross context VM structure.
589	* @param fFlag The flag to set.
590	*/
591	#if 1
592	# define VM_FF_SET(pVM, fFlag) ASMAtomicOrU32(&(pVM)->fGlobalForcedActions, (fFlag))
593	#else
594	# define VM_FF_SET(pVM, fFlag) \
595	do { ASMAtomicOrU32(&(pVM)->fGlobalForcedActions, (fFlag)); \
596	RTLogPrintf("VM_FF_SET : %08x %s - %s(%d) %s\n", (pVM)->fGlobalForcedActions, #fFlag, __FILE__, __LINE__, __FUNCTION__); \
597	} while (0)
598	#endif
599
600	/** @def VMCPU_FF_SET
601	* Sets a force action flag for the given VCPU.
602	*
603	* @param pVCpu The cross context virtual CPU structure.
604	* @param fFlag The flag to set.
605	*/
606	#define VMCPU_FF_SET(pVCpu, fFlag) ASMAtomicOrU32(&(pVCpu)->fLocalForcedActions, (fFlag))
607
608	/** @def VM_FF_CLEAR
609	* Clears a force action flag.
610	*
611	* @param pVM The cross context VM structure.
612	* @param fFlag The flag to clear.
613	*/
614	#if 1
615	# define VM_FF_CLEAR(pVM, fFlag) ASMAtomicAndU32(&(pVM)->fGlobalForcedActions, ~(fFlag))
616	#else
617	# define VM_FF_CLEAR(pVM, fFlag) \
618	do { ASMAtomicAndU32(&(pVM)->fGlobalForcedActions, ~(fFlag)); \
619	RTLogPrintf("VM_FF_CLEAR: %08x %s - %s(%d) %s\n", (pVM)->fGlobalForcedActions, #fFlag, __FILE__, __LINE__, __FUNCTION__); \
620	} while (0)
621	#endif
622
623	/** @def VMCPU_FF_CLEAR
624	* Clears a force action flag for the given VCPU.
625	*
626	* @param pVCpu The cross context virtual CPU structure.
627	* @param fFlag The flag to clear.
628	*/
629	#define VMCPU_FF_CLEAR(pVCpu, fFlag) ASMAtomicAndU32(&(pVCpu)->fLocalForcedActions, ~(fFlag))
630
631	/** @def VM_FF_IS_SET
632	* Checks if a force action flag is set.
633	*
634	* @param pVM The cross context VM structure.
635	* @param fFlag The flag to check.
636	*/
637	#define VM_FF_IS_SET(pVM, fFlag) (((pVM)->fGlobalForcedActions & (fFlag)) == (fFlag))
638
639	/** @def VMCPU_FF_IS_SET
640	* Checks if a force action flag is set for the given VCPU.
641	*
642	* @param pVCpu The cross context virtual CPU structure.
643	* @param fFlag The flag to check.
644	*/
645	#define VMCPU_FF_IS_SET(pVCpu, fFlag) (((pVCpu)->fLocalForcedActions & (fFlag)) == (fFlag))
646
647	/** @def VM_FF_IS_PENDING
648	* Checks if one or more force action in the specified set is pending.
649	*
650	* @param pVM The cross context VM structure.
651	* @param fFlags The flags to check for.
652	*/
653	#define VM_FF_IS_PENDING(pVM, fFlags) RT_BOOL((pVM)->fGlobalForcedActions & (fFlags))
654
655	/** @def VM_FF_TEST_AND_CLEAR
656	* Checks if one (!) force action in the specified set is pending and clears it atomically
657	*
658	* @returns true if the bit was set.
659	* @returns false if the bit was clear.
660	* @param pVM The cross context VM structure.
661	* @param iBit Bit position to check and clear
662	*/
663	#define VM_FF_TEST_AND_CLEAR(pVM, iBit) (ASMAtomicBitTestAndClear(&(pVM)->fGlobalForcedActions, iBit##_BIT))
664
665	/** @def VMCPU_FF_TEST_AND_CLEAR
666	* Checks if one (!) force action in the specified set is pending and clears it atomically
667	*
668	* @returns true if the bit was set.
669	* @returns false if the bit was clear.
670	* @param pVCpu The cross context virtual CPU structure.
671	* @param iBit Bit position to check and clear
672	*/
673	#define VMCPU_FF_TEST_AND_CLEAR(pVCpu, iBit) (ASMAtomicBitTestAndClear(&(pVCpu)->fLocalForcedActions, iBit##_BIT))
674
675	/** @def VMCPU_FF_IS_PENDING
676	* Checks if one or more force action in the specified set is pending for the given VCPU.
677	*
678	* @param pVCpu The cross context virtual CPU structure.
679	* @param fFlags The flags to check for.
680	*/
681	#define VMCPU_FF_IS_PENDING(pVCpu, fFlags) RT_BOOL((pVCpu)->fLocalForcedActions & (fFlags))
682
683	/** @def VM_FF_IS_PENDING_EXCEPT
684	* Checks if one or more force action in the specified set is pending while one
685	* or more other ones are not.
686	*
687	* @param pVM The cross context VM structure.
688	* @param fFlags The flags to check for.
689	* @param fExcpt The flags that should not be set.
690	*/
691	#define VM_FF_IS_PENDING_EXCEPT(pVM, fFlags, fExcpt) ( ((pVM)->fGlobalForcedActions & (fFlags)) && !((pVM)->fGlobalForcedActions & (fExcpt)) )
692
693	/** @def VMCPU_FF_IS_PENDING_EXCEPT
694	* Checks if one or more force action in the specified set is pending for the given
695	* VCPU while one or more other ones are not.
696	*
697	* @param pVCpu The cross context virtual CPU structure.
698	* @param fFlags The flags to check for.
699	* @param fExcpt The flags that should not be set.
700	*/
701	#define VMCPU_FF_IS_PENDING_EXCEPT(pVCpu, fFlags, fExcpt) ( ((pVCpu)->fLocalForcedActions & (fFlags)) && !((pVCpu)->fLocalForcedActions & (fExcpt)) )
702
703	/** @def VM_IS_EMT
704	* Checks if the current thread is the emulation thread (EMT).
705	*
706	* @remark The ring-0 variation will need attention if we expand the ring-0
707	* code to let threads other than EMT mess around with the VM.
708	*/
709	#ifdef IN_RC
710	# define VM_IS_EMT(pVM) true
711	#else
712	# define VM_IS_EMT(pVM) (VMMGetCpu(pVM) != NULL)
713	#endif
714
715	/** @def VMCPU_IS_EMT
716	* Checks if the current thread is the emulation thread (EMT) for the specified
717	* virtual CPU.
718	*/
719	#ifdef IN_RC
720	# define VMCPU_IS_EMT(pVCpu) true
721	#else
722	# define VMCPU_IS_EMT(pVCpu) ((pVCpu) && ((pVCpu) == VMMGetCpu((pVCpu)->CTX_SUFF(pVM))))
723	#endif
724
725	/** @def VM_ASSERT_EMT
726	* Asserts that the current thread IS the emulation thread (EMT).
727	*/
728	#ifdef IN_RC
729	# define VM_ASSERT_EMT(pVM) Assert(VM_IS_EMT(pVM))
730	#elif defined(IN_RING0)
731	# define VM_ASSERT_EMT(pVM) Assert(VM_IS_EMT(pVM))
732	#else
733	# define VM_ASSERT_EMT(pVM) \
734	AssertMsg(VM_IS_EMT(pVM), \
735	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd\n", RTThreadNativeSelf(), VMR3GetVMCPUNativeThread(pVM)))
736	#endif
737
738	/** @def VMCPU_ASSERT_EMT
739	* Asserts that the current thread IS the emulation thread (EMT) of the
740	* specified virtual CPU.
741	*/
742	#ifdef IN_RC
743	# define VMCPU_ASSERT_EMT(pVCpu) Assert(VMCPU_IS_EMT(pVCpu))
744	#elif defined(IN_RING0)
745	# define VMCPU_ASSERT_EMT(pVCpu) AssertMsg(VMCPU_IS_EMT(pVCpu), \
746	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd idCpu=%u\n", \
747	RTThreadNativeSelf(), (pVCpu) ? (pVCpu)->hNativeThreadR0 : 0, \
748	(pVCpu) ? (pVCpu)->idCpu : 0))
749	#else
750	# define VMCPU_ASSERT_EMT(pVCpu) AssertMsg(VMCPU_IS_EMT(pVCpu), \
751	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd idCpu=%#x\n", \
752	RTThreadNativeSelf(), (pVCpu)->hNativeThread, (pVCpu)->idCpu))
753	#endif
754
755	/** @def VM_ASSERT_EMT_RETURN
756	* Asserts that the current thread IS the emulation thread (EMT) and returns if it isn't.
757	*/
758	#ifdef IN_RC
759	# define VM_ASSERT_EMT_RETURN(pVM, rc) AssertReturn(VM_IS_EMT(pVM), (rc))
760	#elif defined(IN_RING0)
761	# define VM_ASSERT_EMT_RETURN(pVM, rc) AssertReturn(VM_IS_EMT(pVM), (rc))
762	#else
763	# define VM_ASSERT_EMT_RETURN(pVM, rc) \
764	AssertMsgReturn(VM_IS_EMT(pVM), \
765	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd\n", RTThreadNativeSelf(), VMR3GetVMCPUNativeThread(pVM)), \
766	(rc))
767	#endif
768
769	/** @def VMCPU_ASSERT_EMT_RETURN
770	* Asserts that the current thread IS the emulation thread (EMT) and returns if it isn't.
771	*/
772	#ifdef IN_RC
773	# define VMCPU_ASSERT_EMT_RETURN(pVCpu, rc) AssertReturn(VMCPU_IS_EMT(pVCpu), (rc))
774	#elif defined(IN_RING0)
775	# define VMCPU_ASSERT_EMT_RETURN(pVCpu, rc) AssertReturn(VMCPU_IS_EMT(pVCpu), (rc))
776	#else
777	# define VMCPU_ASSERT_EMT_RETURN(pVCpu, rc) \
778	AssertMsgReturn(VMCPU_IS_EMT(pVCpu), \
779	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd idCpu=%#x\n", \
780	RTThreadNativeSelf(), (pVCpu)->hNativeThread, (pVCpu)->idCpu), \
781	(rc))
782	#endif
783
784	/** @def VMCPU_ASSERT_EMT_OR_GURU
785	* Asserts that the current thread IS the emulation thread (EMT) of the
786	* specified virtual CPU.
787	*/
788	#if defined(IN_RC) \|\| defined(IN_RING0)
789	# define VMCPU_ASSERT_EMT_OR_GURU(pVCpu) Assert( VMCPU_IS_EMT(pVCpu) \
790	\|\| pVCpu->CTX_SUFF(pVM)->enmVMState == VMSTATE_GURU_MEDITATION \
791	\|\| pVCpu->CTX_SUFF(pVM)->enmVMState == VMSTATE_GURU_MEDITATION_LS )
792	#else
793	# define VMCPU_ASSERT_EMT_OR_GURU(pVCpu) \
794	AssertMsg( VMCPU_IS_EMT(pVCpu) \
795	\|\| pVCpu->CTX_SUFF(pVM)->enmVMState == VMSTATE_GURU_MEDITATION \
796	\|\| pVCpu->CTX_SUFF(pVM)->enmVMState == VMSTATE_GURU_MEDITATION_LS, \
797	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd idCpu=%#x\n", \
798	RTThreadNativeSelf(), (pVCpu)->hNativeThread, (pVCpu)->idCpu))
799	#endif
800
801	/** @def VMCPU_ASSERT_EMT_OR_NOT_RUNNING
802	* Asserts that the current thread IS the emulation thread (EMT) of the
803	* specified virtual CPU or the VM is not running.
804	*/
805	#if defined(IN_RC) \|\| defined(IN_RING0)
806	# define VMCPU_ASSERT_EMT_OR_NOT_RUNNING(pVCpu) \
807	Assert( VMCPU_IS_EMT(pVCpu) \
808	\|\| !VM_IS_RUNNING((pVCpu)->CTX_SUFF(pVM)) )
809	#else
810	# define VMCPU_ASSERT_EMT_OR_NOT_RUNNING(pVCpu) \
811	AssertMsg( VMCPU_IS_EMT(pVCpu) \
812	\|\| !VM_IS_RUNNING((pVCpu)->CTX_SUFF(pVM)), \
813	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd idCpu=%#x\n", \
814	RTThreadNativeSelf(), (pVCpu)->hNativeThread, (pVCpu)->idCpu))
815	#endif
816
817	/** @def VM_IS_RUNNING
818	* Checks if the the VM is running.
819	*/
820	#define VM_IS_RUNNING(pVM) ( (pVM)->enmVMState == VMSTATE_RUNNING \
821	\|\| (pVM)->enmVMState == VMSTATE_RUNNING_LS \
822	\|\| (pVM)->enmVMState == VMSTATE_RUNNING_FT)
823
824	/** @def VM_ASSERT_IS_NOT_RUNNING
825	* Asserts that the VM is not running.
826	*/
827	#if defined(IN_RC) \|\| defined(IN_RING0)
828	#define VM_ASSERT_IS_NOT_RUNNING(pVM) Assert(!VM_IS_RUNNING(pVM))
829	#else
830	#define VM_ASSERT_IS_NOT_RUNNING(pVM) AssertMsg(!VM_IS_RUNNING(pVM), ("VM is running. enmVMState=%d\n", \
831	(pVM)->enmVMState))
832	#endif
833
834	/** @def VM_ASSERT_EMT0
835	* Asserts that the current thread IS emulation thread \#0 (EMT0).
836	*/
837	#define VM_ASSERT_EMT0(pVM) VMCPU_ASSERT_EMT(&(pVM)->aCpus[0])
838
839	/** @def VM_ASSERT_EMT0_RETURN
840	* Asserts that the current thread IS emulation thread \#0 (EMT0) and returns if
841	* it isn't.
842	*/
843	#define VM_ASSERT_EMT0_RETURN(pVM, rc) VMCPU_ASSERT_EMT_RETURN(&(pVM)->aCpus[0], (rc))
844
845
846	/**
847	* Asserts that the current thread is NOT the emulation thread.
848	*/
849	#define VM_ASSERT_OTHER_THREAD(pVM) \
850	AssertMsg(!VM_IS_EMT(pVM), ("Not other thread!!\n"))
851
852
853	/** @def VM_ASSERT_STATE
854	* Asserts a certain VM state.
855	*/
856	#define VM_ASSERT_STATE(pVM, _enmState) \
857	AssertMsg((pVM)->enmVMState == (_enmState), \
858	("state %s, expected %s\n", VMGetStateName((pVM)->enmVMState), VMGetStateName(_enmState)))
859
860	/** @def VM_ASSERT_STATE_RETURN
861	* Asserts a certain VM state and returns if it doesn't match.
862	*/
863	#define VM_ASSERT_STATE_RETURN(pVM, _enmState, rc) \
864	AssertMsgReturn((pVM)->enmVMState == (_enmState), \
865	("state %s, expected %s\n", VMGetStateName((pVM)->enmVMState), VMGetStateName(_enmState)), \
866	(rc))
867
868	/** @def VM_IS_VALID_EXT
869	* Asserts a the VM handle is valid for external access, i.e. not being destroy
870	* or terminated. */
871	#define VM_IS_VALID_EXT(pVM) \
872	( RT_VALID_ALIGNED_PTR(pVM, PAGE_SIZE) \
873	&& ( (unsigned)(pVM)->enmVMState < (unsigned)VMSTATE_DESTROYING \
874	\|\| ( (unsigned)(pVM)->enmVMState == (unsigned)VMSTATE_DESTROYING \
875	&& VM_IS_EMT(pVM))) )
876
877	/** @def VM_ASSERT_VALID_EXT_RETURN
878	* Asserts a the VM handle is valid for external access, i.e. not being
879	* destroy or terminated.
880	*/
881	#define VM_ASSERT_VALID_EXT_RETURN(pVM, rc) \
882	AssertMsgReturn(VM_IS_VALID_EXT(pVM), \
883	("pVM=%p state %s\n", (pVM), RT_VALID_ALIGNED_PTR(pVM, PAGE_SIZE) \
884	? VMGetStateName(pVM->enmVMState) : ""), \
885	(rc))
886
887	/** @def VMCPU_ASSERT_VALID_EXT_RETURN
888	* Asserts a the VMCPU handle is valid for external access, i.e. not being
889	* destroy or terminated.
890	*/
891	#define VMCPU_ASSERT_VALID_EXT_RETURN(pVCpu, rc) \
892	AssertMsgReturn( RT_VALID_ALIGNED_PTR(pVCpu, 64) \
893	&& RT_VALID_ALIGNED_PTR((pVCpu)->CTX_SUFF(pVM), PAGE_SIZE) \
894	&& (unsigned)(pVCpu)->CTX_SUFF(pVM)->enmVMState < (unsigned)VMSTATE_DESTROYING, \
895	("pVCpu=%p pVM=%p state %s\n", (pVCpu), RT_VALID_ALIGNED_PTR(pVCpu, 64) ? (pVCpu)->CTX_SUFF(pVM) : NULL, \
896	RT_VALID_ALIGNED_PTR(pVCpu, 64) && RT_VALID_ALIGNED_PTR((pVCpu)->CTX_SUFF(pVM), PAGE_SIZE) \
897	? VMGetStateName((pVCpu)->pVMR3->enmVMState) : ""), \
898	(rc))
899
900	#endif /* !VBOX_FOR_DTRACE_LIB */
901
902
903
904	/**
905	* The cross context VM structure.
906	*
907	* It contains all the VM data which have to be available in all contexts.
908	* Even if it contains all the data the idea is to use APIs not to modify all
909	* the members all around the place. Therefore we make use of unions to hide
910	* everything which isn't local to the current source module. This means we'll
911	* have to pay a little bit of attention when adding new members to structures
912	* in the unions and make sure to keep the padding sizes up to date.
913	*
914	* Run 'kmk run-struct-tests' (from src/VBox/VMM if you like) after updating!
915	*/
916	typedef struct VM
917	{
918	/** The state of the VM.
919	* This field is read only to everyone except the VM and EM. */
920	VMSTATE volatile enmVMState;
921	/** Forced action flags.
922	* See the VM_FF_* \#defines. Updated atomically.
923	*/
924	volatile uint32_t fGlobalForcedActions;
925	/** Pointer to the array of page descriptors for the VM structure allocation. */
926	R3PTRTYPE(PSUPPAGE) paVMPagesR3;
927	/** Session handle. For use when calling SUPR0 APIs. */
928	PSUPDRVSESSION pSession;
929	/** Pointer to the ring-3 VM structure. */
930	PUVM pUVM;
931	/** Ring-3 Host Context VM Pointer. */
932	R3PTRTYPE(struct VM *) pVMR3;
933	/** Ring-0 Host Context VM Pointer. */
934	R0PTRTYPE(struct VM *) pVMR0;
935	/** Raw-mode Context VM Pointer. */
936	RCPTRTYPE(struct VM *) pVMRC;
937
938	/** The GVM VM handle. Only the GVM should modify this field. */
939	uint32_t hSelf;
940	/** Number of virtual CPUs. */
941	uint32_t cCpus;
942	/** CPU excution cap (1-100) */
943	uint32_t uCpuExecutionCap;
944
945	/** Size of the VM structure including the VMCPU array. */
946	uint32_t cbSelf;
947
948	/** Offset to the VMCPU array starting from beginning of this structure. */
949	uint32_t offVMCPU;
950
951	/**
952	* VMMSwitcher assembly entry point returning to host context.
953	*
954	* Depending on how the host handles the rc status given in @a eax, this may
955	* return and let the caller resume whatever it was doing prior to the call.
956	*
957	*
958	* @param eax The return code, register.
959	* @remark Assume interrupts disabled.
960	* @remark This method pointer lives here because TRPM needs it.
961	*/
962	RTRCPTR pfnVMMRCToHostAsm/(int32_t eax)/;
963
964	/**
965	* VMMSwitcher assembly entry point returning to host context without saving the
966	* raw-mode context (hyper) registers.
967	*
968	* Unlike pfnVMMRC2HCAsm, this will not return to the caller. Instead it
969	* expects the caller to save a RC context in CPUM where one might return if the
970	* return code indicate that this is possible.
971	*
972	* This method pointer lives here because TRPM needs it.
973	*
974	* @param eax The return code, register.
975	* @remark Assume interrupts disabled.
976	* @remark This method pointer lives here because TRPM needs it.
977	*/
978	RTRCPTR pfnVMMRCToHostAsmNoReturn/(int32_t eax)/;
979
980	/** @name Various items that are frequently accessed.
981	* @{ */
982	/** Whether to recompile user mode code or run it raw/hm. */
983	bool fRecompileUser;
984	/** Whether to recompile supervisor mode code or run it raw/hm. */
985	bool fRecompileSupervisor;
986	/** Whether raw mode supports ring-1 code or not. */
987	bool fRawRing1Enabled;
988	/** PATM enabled flag.
989	* This is placed here for performance reasons. */
990	bool fPATMEnabled;
991	/** CSAM enabled flag.
992	* This is placed here for performance reasons. */
993	bool fCSAMEnabled;
994	/** Hardware VM support is available and enabled.
995	* Determined very early during init.
996	* This is placed here for performance reasons. */
997	bool fHMEnabled;
998	/** For asserting on fHMEnable usage. */
999	bool fHMEnabledFixed;
1000	/** Hardware VM support requires a minimal raw-mode context.
1001	* This is never set on 64-bit hosts, only 32-bit hosts requires it. */
1002	bool fHMNeedRawModeCtx;
1003	/** Set when this VM is the master FT node.
1004	* @todo This doesn't need to be here, FTM should store it in it's own
1005	* structures instead. */
1006	bool fFaultTolerantMaster;
1007	/** Large page enabled flag.
1008	* @todo This doesn't need to be here, PGM should store it in it's own
1009	* structures instead. */
1010	bool fUseLargePages;
1011	/** @} */
1012
1013	/** Alignment padding. */
1014	uint8_t uPadding1[2];
1015
1016	/** @name Debugging
1017	* @{ */
1018	/** Raw-mode Context VM Pointer. */
1019	RCPTRTYPE(RTTRACEBUF) hTraceBufRC;
1020	/** Ring-3 Host Context VM Pointer. */
1021	R3PTRTYPE(RTTRACEBUF) hTraceBufR3;
1022	/** Ring-0 Host Context VM Pointer. */
1023	R0PTRTYPE(RTTRACEBUF) hTraceBufR0;
1024	/** @} */
1025
1026	#if HC_ARCH_BITS == 32
1027	/** Alignment padding. */
1028	uint32_t uPadding2;
1029	#endif
1030
1031	/** @name Switcher statistics (remove)
1032	* @{ */
1033	/** Profiling the total time from Qemu to GC. */
1034	STAMPROFILEADV StatTotalQemuToGC;
1035	/** Profiling the total time from GC to Qemu. */
1036	STAMPROFILEADV StatTotalGCToQemu;
1037	/** Profiling the total time spent in GC. */
1038	STAMPROFILEADV StatTotalInGC;
1039	/** Profiling the total time spent not in Qemu. */
1040	STAMPROFILEADV StatTotalInQemu;
1041	/** Profiling the VMMSwitcher code for going to GC. */
1042	STAMPROFILEADV StatSwitcherToGC;
1043	/** Profiling the VMMSwitcher code for going to HC. */
1044	STAMPROFILEADV StatSwitcherToHC;
1045	STAMPROFILEADV StatSwitcherSaveRegs;
1046	STAMPROFILEADV StatSwitcherSysEnter;
1047	STAMPROFILEADV StatSwitcherDebug;
1048	STAMPROFILEADV StatSwitcherCR0;
1049	STAMPROFILEADV StatSwitcherCR4;
1050	STAMPROFILEADV StatSwitcherJmpCR3;
1051	STAMPROFILEADV StatSwitcherRstrRegs;
1052	STAMPROFILEADV StatSwitcherLgdt;
1053	STAMPROFILEADV StatSwitcherLidt;
1054	STAMPROFILEADV StatSwitcherLldt;
1055	STAMPROFILEADV StatSwitcherTSS;
1056	/** @} */
1057
1058	/** Padding - the unions must be aligned on a 64 bytes boundary and the unions
1059	* must start at the same offset on both 64-bit and 32-bit hosts. */
1060	uint8_t abAlignment3[(HC_ARCH_BITS == 32 ? 24 : 0) + 40];
1061
1062	/** CPUM part. */
1063	union
1064	{
1065	#ifdef ___CPUMInternal_h
1066	struct CPUM s;
1067	#endif
1068	#ifdef ___VBox_vmm_cpum_h
1069	/** Read only info exposed about the host and guest CPUs. */
1070	struct
1071	{
1072	/** Padding for hidden fields. */
1073	uint8_t abHidden0[64];
1074	/** Host CPU feature information. */
1075	CPUMFEATURES HostFeatures;
1076	/** Guest CPU feature information. */
1077	CPUMFEATURES GuestFeatures;
1078	} const ro;
1079	#endif
1080	uint8_t padding[1536]; /* multiple of 64 */
1081	} cpum;
1082
1083	/** VMM part. */
1084	union
1085	{
1086	#ifdef ___VMMInternal_h
1087	struct VMM s;
1088	#endif
1089	uint8_t padding[1600]; /* multiple of 64 */
1090	} vmm;
1091
1092	/** PGM part. */
1093	union
1094	{
1095	#ifdef ___PGMInternal_h
1096	struct PGM s;
1097	#endif
1098	uint8_t padding[40962+6080]; / multiple of 64 */
1099	} pgm;
1100
1101	/** HM part. */
1102	union
1103	{
1104	#ifdef ___HMInternal_h
1105	struct HM s;
1106	#endif
1107	uint8_t padding[5440]; /* multiple of 64 */
1108	} hm;
1109
1110	/** TRPM part. */
1111	union
1112	{
1113	#ifdef ___TRPMInternal_h
1114	struct TRPM s;
1115	#endif
1116	uint8_t padding[5248]; /* multiple of 64 */
1117	} trpm;
1118
1119	/** SELM part. */
1120	union
1121	{
1122	#ifdef ___SELMInternal_h
1123	struct SELM s;
1124	#endif
1125	uint8_t padding[768]; /* multiple of 64 */
1126	} selm;
1127
1128	/** MM part. */
1129	union
1130	{
1131	#ifdef ___MMInternal_h
1132	struct MM s;
1133	#endif
1134	uint8_t padding[192]; /* multiple of 64 */
1135	} mm;
1136
1137	/** PDM part. */
1138	union
1139	{
1140	#ifdef ___PDMInternal_h
1141	struct PDM s;
1142	#endif
1143	uint8_t padding[1920]; /* multiple of 64 */
1144	} pdm;
1145
1146	/** IOM part. */
1147	union
1148	{
1149	#ifdef ___IOMInternal_h
1150	struct IOM s;
1151	#endif
1152	uint8_t padding[896]; /* multiple of 64 */
1153	} iom;
1154
1155	/** PATM part. */
1156	union
1157	{
1158	#ifdef ___PATMInternal_h
1159	struct PATM s;
1160	#endif
1161	uint8_t padding[768]; /* multiple of 64 */
1162	} patm;
1163
1164	/** CSAM part. */
1165	union
1166	{
1167	#ifdef ___CSAMInternal_h
1168	struct CSAM s;
1169	#endif
1170	uint8_t padding[1088]; /* multiple of 64 */
1171	} csam;
1172
1173	/** EM part. */
1174	union
1175	{
1176	#ifdef ___EMInternal_h
1177	struct EM s;
1178	#endif
1179	uint8_t padding[256]; /* multiple of 64 */
1180	} em;
1181
1182	/** TM part. */
1183	union
1184	{
1185	#ifdef ___TMInternal_h
1186	struct TM s;
1187	#endif
1188	uint8_t padding[2496]; /* multiple of 64 */
1189	} tm;
1190
1191	/** DBGF part. */
1192	union
1193	{
1194	#ifdef ___DBGFInternal_h
1195	struct DBGF s;
1196	#endif
1197	#ifdef ___VBox_vmm_dbgf_h
1198	/** Read only info exposed about interrupt breakpoints and selected events. */
1199	struct
1200	{
1201	/** Bitmap of enabled hardware interrupt breakpoints. */
1202	uint32_t bmHardIntBreakpoints[256 / 32];
1203	/** Bitmap of enabled software interrupt breakpoints. */
1204	uint32_t bmSoftIntBreakpoints[256 / 32];
1205	/** Bitmap of selected events.
1206	* This includes non-selectable events too for simplicity, we maintain the
1207	* state for some of these, as it may come in handy. */
1208	uint64_t bmSelectedEvents[(DBGFEVENT_END + 63) / 64];
1209	/** Enabled hardware interrupt breakpoints. */
1210	uint32_t cHardIntBreakpoints;
1211	/** Enabled software interrupt breakpoints. */
1212	uint32_t cSoftIntBreakpoints;
1213	/** Number of selected events. */
1214	uint32_t cSelectedEvents;
1215	} const ro;
1216	#endif
1217	uint8_t padding[2368]; /* multiple of 64 */
1218	} dbgf;
1219
1220	/** SSM part. */
1221	union
1222	{
1223	#ifdef ___SSMInternal_h
1224	struct SSM s;
1225	#endif
1226	uint8_t padding[128]; /* multiple of 64 */
1227	} ssm;
1228
1229	/** FTM part. */
1230	union
1231	{
1232	#ifdef ___FTMInternal_h
1233	struct FTM s;
1234	#endif
1235	uint8_t padding[512]; /* multiple of 64 */
1236	} ftm;
1237
1238	/** REM part. */
1239	union
1240	{
1241	#ifdef ___REMInternal_h
1242	struct REM s;
1243	#endif
1244	uint8_t padding[0x11100]; /* multiple of 64 */
1245	} rem;
1246
1247	union
1248	{
1249	#ifdef ___GIMInternal_h
1250	struct GIM s;
1251	#endif
1252	uint8_t padding[448]; /* multiple of 64 */
1253	} gim;
1254
1255	/* ---- begin small stuff ---- */
1256
1257	/** VM part. */
1258	union
1259	{
1260	#ifdef ___VMInternal_h
1261	struct VMINT s;
1262	#endif
1263	uint8_t padding[24]; /* multiple of 8 */
1264	} vm;
1265
1266	/** CFGM part. */
1267	union
1268	{
1269	#ifdef ___CFGMInternal_h
1270	struct CFGM s;
1271	#endif
1272	uint8_t padding[8]; /* multiple of 8 */
1273	} cfgm;
1274
1275	#ifdef VBOX_WITH_NEW_APIC
1276	union
1277	{
1278	# ifdef ___APICInternal_h
1279	struct APIC s;
1280	# endif
1281	uint8_t padding[128]; /* multiple of 8 */
1282	} apic;
1283	#endif
1284
1285	/** Padding for aligning the cpu array on a page boundary. */
1286	#ifdef VBOX_WITH_NEW_APIC
1287	uint8_t abAlignment2[3870];
1288	#else
1289	uint8_t abAlignment2[3998];
1290	#endif
1291
1292	/* ---- end small stuff ---- */
1293
1294	/** VMCPU array for the configured number of virtual CPUs.
1295	* Must be aligned on a page boundary for TLB hit reasons as well as
1296	* alignment of VMCPU members. */
1297	VMCPU aCpus[1];
1298	} VM;
1299
1300
1301	#ifdef IN_RC
1302	RT_C_DECLS_BEGIN
1303
1304	/** The VM structure.
1305	* This is imported from the VMMRCBuiltin module, i.e. it's a one of those magic
1306	* globals which we should avoid using.
1307	*/
1308	extern DECLIMPORT(VM) g_VM;
1309
1310	RT_C_DECLS_END
1311	#endif
1312
1313	/** @} */
1314
1315	#endif
1316

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source: vbox/trunk/include/VBox/vmm/vm.h@ 61628

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