vm.h@ 74491

Last change on this file since 74491 was 74436, checked in by vboxsync, 6 years ago
vm.h: Update comment regarding available VCPU force-flags.
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1	/** @file
2	* VM - The Virtual Machine, data.
3	*/
4
5	/*
6	* Copyright (C) 2006-2017 Oracle Corporation
7	*
8	* This file is part of VirtualBox Open Source Edition (OSE), as
9	* available from http://www.virtualbox.org. This file is free software;
10	* you can redistribute it and/or modify it under the terms of the GNU
11	* General Public License (GPL) as published by the Free Software
12	* Foundation, in version 2 as it comes in the "COPYING" file of the
13	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15	*
16	* The contents of this file may alternatively be used under the terms
17	* of the Common Development and Distribution License Version 1.0
18	* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19	* VirtualBox OSE distribution, in which case the provisions of the
20	* CDDL are applicable instead of those of the GPL.
21	*
22	* You may elect to license modified versions of this file under the
23	* terms and conditions of either the GPL or the CDDL or both.
24	*/
25
26	#ifndef ___VBox_vmm_vm_h
27	#define ___VBox_vmm_vm_h
28
29	#ifndef VBOX_FOR_DTRACE_LIB
30	# include <iprt/param.h>
31	# include <VBox/types.h>
32	# include <VBox/vmm/cpum.h>
33	# include <VBox/vmm/stam.h>
34	# include <VBox/vmm/vmapi.h>
35	# include <VBox/vmm/vmm.h>
36	# include <VBox/sup.h>
37	#else
38	# pragma D depends_on library vbox-types.d
39	# pragma D depends_on library CPUMInternal.d
40	# define ___CPUMInternal_h
41	#endif
42
43
44
45	/** @defgroup grp_vm The Virtual Machine
46	* @ingroup grp_vmm
47	* @{
48	*/
49
50	/**
51	* The state of a Virtual CPU.
52	*
53	* The basic state indicated here is whether the CPU has been started or not. In
54	* addition, there are sub-states when started for assisting scheduling (GVMM
55	* mostly).
56	*
57	* The transition out of the STOPPED state is done by a vmR3PowerOn.
58	* The transition back to the STOPPED state is done by vmR3PowerOff.
59	*
60	* (Alternatively we could let vmR3PowerOn start CPU 0 only and let the SPIP
61	* handling switch on the other CPUs. Then vmR3Reset would stop all but CPU 0.)
62	*/
63	typedef enum VMCPUSTATE
64	{
65	/** The customary invalid zero. */
66	VMCPUSTATE_INVALID = 0,
67
68	/** Virtual CPU has not yet been started. */
69	VMCPUSTATE_STOPPED,
70
71	/** CPU started. */
72	VMCPUSTATE_STARTED,
73	/** CPU started in HM context. */
74	VMCPUSTATE_STARTED_HM,
75	/** Executing guest code and can be poked (RC or STI bits of HM). */
76	VMCPUSTATE_STARTED_EXEC,
77	/** Executing guest code in the recompiler. */
78	VMCPUSTATE_STARTED_EXEC_REM,
79	/** Executing guest code using NEM. */
80	VMCPUSTATE_STARTED_EXEC_NEM,
81	VMCPUSTATE_STARTED_EXEC_NEM_WAIT,
82	VMCPUSTATE_STARTED_EXEC_NEM_CANCELED,
83	/** Halted. */
84	VMCPUSTATE_STARTED_HALTED,
85
86	/** The end of valid virtual CPU states. */
87	VMCPUSTATE_END,
88
89	/** Ensure 32-bit type. */
90	VMCPUSTATE_32BIT_HACK = 0x7fffffff
91	} VMCPUSTATE;
92
93
94	/**
95	* The cross context virtual CPU structure.
96	*
97	* Run 'kmk run-struct-tests' (from src/VBox/VMM if you like) after updating!
98	*/
99	typedef struct VMCPU
100	{
101	/** Per CPU forced action.
102	* See the VMCPU_FF_* \#defines. Updated atomically. */
103	uint32_t volatile fLocalForcedActions; /* 0 */
104	/** The CPU state. */
105	VMCPUSTATE volatile enmState; /* 4 */
106
107	/** Pointer to the ring-3 UVMCPU structure. */
108	PUVMCPU pUVCpu; /* 8 */
109	/** Ring-3 Host Context VM Pointer. */
110	PVMR3 pVMR3; /* 16 / 12 */
111	/** Ring-0 Host Context VM Pointer. */
112	PVMR0 pVMR0; /* 24 / 16 */
113	/** Raw-mode Context VM Pointer. */
114	PVMRC pVMRC; /* 32 / 20 */
115	/** The CPU ID.
116	* This is the index into the VM::aCpu array. */
117	VMCPUID idCpu; /* 36 / 24 */
118	/** The native thread handle. */
119	RTNATIVETHREAD hNativeThread; /* 40 / 28 */
120	/** The native R0 thread handle. (different from the R3 handle!) */
121	RTNATIVETHREAD hNativeThreadR0; /* 48 / 32 */
122	/** Which host CPU ID is this EMT running on.
123	* Only valid when in RC or HMR0 with scheduling disabled. */
124	RTCPUID volatile idHostCpu; /* 56 / 36 */
125	/** The CPU set index corresponding to idHostCpu, UINT32_MAX if not valid.
126	* @remarks Best to make sure iHostCpuSet shares cache line with idHostCpu! */
127	uint32_t volatile iHostCpuSet; /* 60 / 40 */
128
129	#if HC_ARCH_BITS == 32
130	/** Align the structures below bit on a 64-byte boundary and make sure it starts
131	* at the same offset in both 64-bit and 32-bit builds.
132	*
133	* @remarks The alignments of the members that are larger than 48 bytes should be
134	* 64-byte for cache line reasons. structs containing small amounts of
135	* data could be lumped together at the end with a < 64 byte padding
136	* following it (to grow into and align the struct size).
137	*/
138	uint8_t abAlignment1[HC_ARCH_BITS == 64 ? 0 : 20];
139	#endif
140
141	/** IEM part.
142	* @remarks This comes first as it allows the use of 8-bit immediates for the
143	* first 64 bytes of the structure, reducing code size a wee bit. */
144	#ifdef ___IEMInternal_h /* For PDB hacking. */
145	union VMCPUUNIONIEMFULL
146	#else
147	union VMCPUUNIONIEMSTUB
148	#endif
149	{
150	#ifdef ___IEMInternal_h
151	struct IEMCPU s;
152	#endif
153	uint8_t padding[18496]; /* multiple of 64 */
154	} iem;
155
156	/** HM part. */
157	union VMCPUUNIONHM
158	{
159	#ifdef ___HMInternal_h
160	struct HMCPU s;
161	#endif
162	uint8_t padding[5888]; /* multiple of 64 */
163	} hm;
164
165	/** NEM part. */
166	union VMCPUUNIONNEM
167	{
168	#ifdef ___NEMInternal_h
169	struct NEMCPU s;
170	#endif
171	uint8_t padding[512]; /* multiple of 64 */
172	} nem;
173
174	/** TRPM part. */
175	union VMCPUUNIONTRPM
176	{
177	#ifdef ___TRPMInternal_h
178	struct TRPMCPU s;
179	#endif
180	uint8_t padding[128]; /* multiple of 64 */
181	} trpm;
182
183	/** TM part. */
184	union VMCPUUNIONTM
185	{
186	#ifdef ___TMInternal_h
187	struct TMCPU s;
188	#endif
189	uint8_t padding[384]; /* multiple of 64 */
190	} tm;
191
192	/** VMM part. */
193	union VMCPUUNIONVMM
194	{
195	#ifdef ___VMMInternal_h
196	struct VMMCPU s;
197	#endif
198	uint8_t padding[768]; /* multiple of 64 */
199	} vmm;
200
201	/** PDM part. */
202	union VMCPUUNIONPDM
203	{
204	#ifdef ___PDMInternal_h
205	struct PDMCPU s;
206	#endif
207	uint8_t padding[256]; /* multiple of 64 */
208	} pdm;
209
210	/** IOM part. */
211	union VMCPUUNIONIOM
212	{
213	#ifdef ___IOMInternal_h
214	struct IOMCPU s;
215	#endif
216	uint8_t padding[512]; /* multiple of 64 */
217	} iom;
218
219	/** DBGF part.
220	* @todo Combine this with other tiny structures. */
221	union VMCPUUNIONDBGF
222	{
223	#ifdef ___DBGFInternal_h
224	struct DBGFCPU s;
225	#endif
226	uint8_t padding[256]; /* multiple of 64 */
227	} dbgf;
228
229	/** GIM part. */
230	union VMCPUUNIONGIM
231	{
232	#ifdef ___GIMInternal_h
233	struct GIMCPU s;
234	#endif
235	uint8_t padding[512]; /* multiple of 64 */
236	} gim;
237
238	/** APIC part. */
239	union VMCPUUNIONAPIC
240	{
241	#ifdef ___APICInternal_h
242	struct APICCPU s;
243	#endif
244	uint8_t padding[1792]; /* multiple of 64 */
245	} apic;
246
247	/*
248	* Some less frequently used global members that doesn't need to take up
249	* precious space at the head of the structure.
250	*/
251
252	/** Trace groups enable flags. */
253	uint32_t fTraceGroups; /* 64 / 44 */
254	/** State data for use by ad hoc profiling. */
255	uint32_t uAdHoc;
256	/** Profiling samples for use by ad hoc profiling. */
257	STAMPROFILEADV aStatAdHoc[8]; /* size: 408 = 320 /
258
259	/** Align the following members on page boundary. */
260	uint8_t abAlignment2[2872];
261
262	/** PGM part. */
263	union VMCPUUNIONPGM
264	{
265	#ifdef ___PGMInternal_h
266	struct PGMCPU s;
267	#endif
268	uint8_t padding[4096]; /* multiple of 4096 */
269	} pgm;
270
271	/** CPUM part. */
272	union VMCPUUNIONCPUM
273	{
274	#ifdef ___CPUMInternal_h
275	struct CPUMCPU s;
276	#endif
277	#ifdef VMCPU_INCL_CPUM_GST_CTX
278	/** The guest CPUM context for direct use by execution engines.
279	* This is not for general consumption, but for HM, REM, IEM, and maybe a few
280	* others. The rest will use the function based CPUM API. */
281	CPUMCTX GstCtx;
282	#endif
283	uint8_t padding[4096]; /* multiple of 4096 */
284	} cpum;
285
286	/** EM part. */
287	union VMCPUUNIONEM
288	{
289	#ifdef ___EMInternal_h
290	struct EMCPU s;
291	#endif
292	uint8_t padding[40960]; /* multiple of 4096 */
293	} em;
294	} VMCPU;
295
296
297	#ifndef VBOX_FOR_DTRACE_LIB
298
299	/** @name Operations on VMCPU::enmState
300	* @{ */
301	/** Gets the VMCPU state. */
302	#define VMCPU_GET_STATE(pVCpu) ( (pVCpu)->enmState )
303	/** Sets the VMCPU state. */
304	#define VMCPU_SET_STATE(pVCpu, enmNewState) \
305	ASMAtomicWriteU32((uint32_t volatile *)&(pVCpu)->enmState, (enmNewState))
306	/** Cmpares and sets the VMCPU state. */
307	#define VMCPU_CMPXCHG_STATE(pVCpu, enmNewState, enmOldState) \
308	ASMAtomicCmpXchgU32((uint32_t volatile *)&(pVCpu)->enmState, (enmNewState), (enmOldState))
309	/** Checks the VMCPU state. */
310	#ifdef VBOX_STRICT
311	# define VMCPU_ASSERT_STATE(pVCpu, enmExpectedState) \
312	do { \
313	VMCPUSTATE enmState = VMCPU_GET_STATE(pVCpu); \
314	AssertMsg(enmState == (enmExpectedState), \
315	("enmState=%d enmExpectedState=%d idCpu=%u\n", \
316	enmState, enmExpectedState, (pVCpu)->idCpu)); \
317	} while (0)
318	#else
319	# define VMCPU_ASSERT_STATE(pVCpu, enmExpectedState) do { } while (0)
320	#endif
321	/** Tests if the state means that the CPU is started. */
322	#define VMCPUSTATE_IS_STARTED(enmState) ( (enmState) > VMCPUSTATE_STOPPED )
323	/** Tests if the state means that the CPU is stopped. */
324	#define VMCPUSTATE_IS_STOPPED(enmState) ( (enmState) == VMCPUSTATE_STOPPED )
325	/** @} */
326
327
328	/** The name of the raw-mode context VMM Core module. */
329	#define VMMRC_MAIN_MODULE_NAME "VMMRC.rc"
330	/** The name of the ring-0 context VMM Core module. */
331	#define VMMR0_MAIN_MODULE_NAME "VMMR0.r0"
332
333	/**
334	* Wrapper macro for avoiding too much \#ifdef VBOX_WITH_RAW_MODE.
335	*/
336	#ifdef VBOX_WITH_RAW_MODE
337	# define VM_WHEN_RAW_MODE(a_WithExpr, a_WithoutExpr) a_WithExpr
338	#else
339	# define VM_WHEN_RAW_MODE(a_WithExpr, a_WithoutExpr) a_WithoutExpr
340	#endif
341
342
343	/** VM Forced Action Flags.
344	*
345	* Use the VM_FF_SET() and VM_FF_CLEAR() macros to change the force
346	* action mask of a VM.
347	*
348	* Available VM bits:
349	* 0, 1, 5, 6, 7, 13, 14, 15, 16, 17, 21, 22, 23, 24, 25, 26, 27, 28, 30
350	*
351	*
352	* Available VMCPU bits:
353	* 14, 15
354	*
355	* @todo If we run low on VMCPU, we may consider merging the SELM bits
356	*
357	* @{
358	*/
359	/** The virtual sync clock has been stopped, go to TM until it has been
360	* restarted... */
361	#define VM_FF_TM_VIRTUAL_SYNC RT_BIT_32(2)
362	/** PDM Queues are pending. */
363	#define VM_FF_PDM_QUEUES RT_BIT_32(VM_FF_PDM_QUEUES_BIT)
364	/** The bit number for VM_FF_PDM_QUEUES. */
365	#define VM_FF_PDM_QUEUES_BIT 3
366	/** PDM DMA transfers are pending. */
367	#define VM_FF_PDM_DMA RT_BIT_32(VM_FF_PDM_DMA_BIT)
368	/** The bit number for VM_FF_PDM_DMA. */
369	#define VM_FF_PDM_DMA_BIT 4
370	/** This action forces the VM to call DBGF so DBGF can service debugger
371	* requests in the emulation thread.
372	* This action flag stays asserted till DBGF clears it.*/
373	#define VM_FF_DBGF RT_BIT_32(VM_FF_DBGF_BIT)
374	/** The bit number for VM_FF_DBGF. */
375	#define VM_FF_DBGF_BIT 8
376	/** This action forces the VM to service pending requests from other
377	* thread or requests which must be executed in another context. */
378	#define VM_FF_REQUEST RT_BIT_32(9)
379	/** Check for VM state changes and take appropriate action. */
380	#define VM_FF_CHECK_VM_STATE RT_BIT_32(VM_FF_CHECK_VM_STATE_BIT)
381	/** The bit number for VM_FF_CHECK_VM_STATE. */
382	#define VM_FF_CHECK_VM_STATE_BIT 10
383	/** Reset the VM. (postponed) */
384	#define VM_FF_RESET RT_BIT_32(VM_FF_RESET_BIT)
385	/** The bit number for VM_FF_RESET. */
386	#define VM_FF_RESET_BIT 11
387	/** EMT rendezvous in VMM. */
388	#define VM_FF_EMT_RENDEZVOUS RT_BIT_32(VM_FF_EMT_RENDEZVOUS_BIT)
389	/** The bit number for VM_FF_EMT_RENDEZVOUS. */
390	#define VM_FF_EMT_RENDEZVOUS_BIT 12
391
392	/** PGM needs to allocate handy pages. */
393	#define VM_FF_PGM_NEED_HANDY_PAGES RT_BIT_32(18)
394	/** PGM is out of memory.
395	* Abandon all loops and code paths which can be resumed and get up to the EM
396	* loops. */
397	#define VM_FF_PGM_NO_MEMORY RT_BIT_32(19)
398	/** PGM is about to perform a lightweight pool flush
399	* Guest SMP: all EMT threads should return to ring 3
400	*/
401	#define VM_FF_PGM_POOL_FLUSH_PENDING RT_BIT_32(20)
402	/** REM needs to be informed about handler changes. */
403	#define VM_FF_REM_HANDLER_NOTIFY RT_BIT_32(VM_FF_REM_HANDLER_NOTIFY_BIT)
404	/** The bit number for VM_FF_REM_HANDLER_NOTIFY. */
405	#define VM_FF_REM_HANDLER_NOTIFY_BIT 29
406	/** Suspend the VM - debug only. */
407	#define VM_FF_DEBUG_SUSPEND RT_BIT_32(31)
408
409
410	/** This action forces the VM to check any pending interrupts on the APIC. */
411	#define VMCPU_FF_INTERRUPT_APIC RT_BIT_32(0)
412	/** This action forces the VM to check any pending interrups on the PIC. */
413	#define VMCPU_FF_INTERRUPT_PIC RT_BIT_32(1)
414	/** This action forces the VM to schedule and run pending timer (TM).
415	* @remarks Don't move - PATM compatibility. */
416	#define VMCPU_FF_TIMER RT_BIT_32(2)
417	/** This action forces the VM to check any pending NMIs. */
418	#define VMCPU_FF_INTERRUPT_NMI_BIT 3
419	#define VMCPU_FF_INTERRUPT_NMI RT_BIT_32(VMCPU_FF_INTERRUPT_NMI_BIT)
420	/** This action forces the VM to check any pending SMIs. */
421	#define VMCPU_FF_INTERRUPT_SMI_BIT 4
422	#define VMCPU_FF_INTERRUPT_SMI RT_BIT_32(VMCPU_FF_INTERRUPT_SMI_BIT)
423	/** PDM critical section unlocking is pending, process promptly upon return to R3. */
424	#define VMCPU_FF_PDM_CRITSECT RT_BIT_32(5)
425	/** Special EM internal force flag that is used by EMUnhaltAndWakeUp() to force
426	* the virtual CPU out of the next (/current) halted state. It is not processed
427	* nor cleared by emR3ForcedActions (similar to VMCPU_FF_BLOCK_NMIS), instead it
428	* is cleared the next time EM leaves the HALTED state. */
429	#define VMCPU_FF_UNHALT RT_BIT_32(6)
430	/** Pending IEM action (bit number). */
431	#define VMCPU_FF_IEM_BIT 7
432	/** Pending IEM action (mask). */
433	#define VMCPU_FF_IEM RT_BIT_32(VMCPU_FF_IEM_BIT)
434	/** Pending APIC action (bit number). */
435	#define VMCPU_FF_UPDATE_APIC_BIT 8
436	/** This action forces the VM to update APIC's asynchronously arrived
437	* interrupts as pending interrupts. */
438	#define VMCPU_FF_UPDATE_APIC RT_BIT_32(VMCPU_FF_UPDATE_APIC_BIT)
439	/** This action forces the VM to service pending requests from other
440	* thread or requests which must be executed in another context. */
441	#define VMCPU_FF_REQUEST RT_BIT_32(9)
442	/** Pending DBGF event (alternative to passing VINF_EM_DBG_EVENT around). */
443	#define VMCPU_FF_DBGF RT_BIT_32(VMCPU_FF_DBGF_BIT)
444	/** The bit number for VMCPU_FF_DBGF. */
445	#define VMCPU_FF_DBGF_BIT 10
446	/** Pending MTF (Monitor Trap Flag) event - Intel only. */
447	#define VMCPU_FF_MTF RT_BIT_32(VMCPU_FF_MTF_BIT)
448	/** The bit number for VMCPU_FF_MTF. */
449	#define VMCPU_FF_MTF_BIT 11
450	/** This action forces the VM to service any pending updates to CR3 (used only
451	* by HM). */
452	#define VMCPU_FF_HM_UPDATE_CR3 RT_BIT_32(12)
453	/** This action forces the VM to service any pending updates to PAE PDPEs (used
454	* only by HM). */
455	#define VMCPU_FF_HM_UPDATE_PAE_PDPES RT_BIT_32(13)
456	/** This action forces the VM to resync the page tables before going
457	* back to execute guest code. (GLOBAL FLUSH) */
458	#define VMCPU_FF_PGM_SYNC_CR3 RT_BIT_32(16)
459	/** Same as VM_FF_PGM_SYNC_CR3 except that global pages can be skipped.
460	* (NON-GLOBAL FLUSH) */
461	#define VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL RT_BIT_32(17)
462	/** Check for pending TLB shootdown actions (deprecated)
463	* Reserved for furture HM re-use if necessary / safe.
464	* Consumer: HM */
465	#define VMCPU_FF_TLB_SHOOTDOWN_UNUSED RT_BIT_32(18)
466	/** Check for pending TLB flush action.
467	* Consumer: HM
468	* @todo rename to VMCPU_FF_HM_TLB_FLUSH */
469	#define VMCPU_FF_TLB_FLUSH RT_BIT_32(VMCPU_FF_TLB_FLUSH_BIT)
470	/** The bit number for VMCPU_FF_TLB_FLUSH. */
471	#define VMCPU_FF_TLB_FLUSH_BIT 19
472	#ifdef VBOX_WITH_RAW_MODE
473	/** Check the interrupt and trap gates */
474	# define VMCPU_FF_TRPM_SYNC_IDT RT_BIT_32(20)
475	/** Check Guest's TSS ring 0 stack */
476	# define VMCPU_FF_SELM_SYNC_TSS RT_BIT_32(21)
477	/** Check Guest's GDT table */
478	# define VMCPU_FF_SELM_SYNC_GDT RT_BIT_32(22)
479	/** Check Guest's LDT table */
480	# define VMCPU_FF_SELM_SYNC_LDT RT_BIT_32(23)
481	#endif /* VBOX_WITH_RAW_MODE */
482	/** Inhibit interrupts pending. See EMGetInhibitInterruptsPC(). */
483	#define VMCPU_FF_INHIBIT_INTERRUPTS RT_BIT_32(24)
484	/** Block injection of non-maskable interrupts to the guest. */
485	#define VMCPU_FF_BLOCK_NMIS RT_BIT_32(25)
486	#ifdef VBOX_WITH_RAW_MODE
487	/** CSAM needs to scan the page that's being executed */
488	# define VMCPU_FF_CSAM_SCAN_PAGE RT_BIT_32(26)
489	/** CSAM needs to do some homework. */
490	# define VMCPU_FF_CSAM_PENDING_ACTION RT_BIT_32(27)
491	#endif /* VBOX_WITH_RAW_MODE */
492	/** Force return to Ring-3. */
493	#define VMCPU_FF_TO_R3 RT_BIT_32(28)
494	/** Force return to ring-3 to service pending I/O or MMIO write.
495	* This is a backup for mechanism VINF_IOM_R3_IOPORT_COMMIT_WRITE and
496	* VINF_IOM_R3_MMIO_COMMIT_WRITE, allowing VINF_EM_DBG_BREAKPOINT and similar
497	* status codes to be propagated at the same time without loss. */
498	#define VMCPU_FF_IOM RT_BIT_32(29)
499	#ifdef VBOX_WITH_RAW_MODE
500	/** CPUM need to adjust CR0.TS/EM before executing raw-mode code again. */
501	# define VMCPU_FF_CPUM RT_BIT_32(VMCPU_FF_CPUM_BIT)
502	/** The bit number for VMCPU_FF_CPUM. */
503	# define VMCPU_FF_CPUM_BIT 30
504	#endif /* VBOX_WITH_RAW_MODE */
505	/** Hardware virtualized nested-guest interrupt pending. */
506	#define VMCPU_FF_INTERRUPT_NESTED_GUEST RT_BIT_32(31)
507
508	/** Externally VM forced actions. Used to quit the idle/wait loop. */
509	#define VM_FF_EXTERNAL_SUSPENDED_MASK ( VM_FF_CHECK_VM_STATE \| VM_FF_DBGF \| VM_FF_REQUEST \| VM_FF_EMT_RENDEZVOUS )
510	/** Externally VMCPU forced actions. Used to quit the idle/wait loop. */
511	#define VMCPU_FF_EXTERNAL_SUSPENDED_MASK ( VMCPU_FF_REQUEST \| VMCPU_FF_DBGF )
512
513	/** Externally forced VM actions. Used to quit the idle/wait loop. */
514	#define VM_FF_EXTERNAL_HALTED_MASK ( VM_FF_CHECK_VM_STATE \| VM_FF_DBGF \| VM_FF_REQUEST \
515	\| VM_FF_PDM_QUEUES \| VM_FF_PDM_DMA \| VM_FF_EMT_RENDEZVOUS )
516	/** Externally forced VMCPU actions. Used to quit the idle/wait loop. */
517	#define VMCPU_FF_EXTERNAL_HALTED_MASK ( VMCPU_FF_UPDATE_APIC \| VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC \
518	\| VMCPU_FF_REQUEST \| VMCPU_FF_INTERRUPT_NMI \| VMCPU_FF_INTERRUPT_SMI \
519	\| VMCPU_FF_UNHALT \| VMCPU_FF_TIMER \| VMCPU_FF_DBGF )
520
521	/** High priority VM pre-execution actions. */
522	#define VM_FF_HIGH_PRIORITY_PRE_MASK ( VM_FF_CHECK_VM_STATE \| VM_FF_DBGF \| VM_FF_TM_VIRTUAL_SYNC \
523	\| VM_FF_DEBUG_SUSPEND \| VM_FF_PGM_NEED_HANDY_PAGES \| VM_FF_PGM_NO_MEMORY \
524	\| VM_FF_EMT_RENDEZVOUS )
525	/** High priority VMCPU pre-execution actions. */
526	#define VMCPU_FF_HIGH_PRIORITY_PRE_MASK ( VMCPU_FF_TIMER \| VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC \
527	\| VMCPU_FF_UPDATE_APIC \| VMCPU_FF_INHIBIT_INTERRUPTS \| VMCPU_FF_DBGF \
528	\| VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL \
529	\| VM_WHEN_RAW_MODE( VMCPU_FF_SELM_SYNC_TSS \| VMCPU_FF_TRPM_SYNC_IDT \
530	\| VMCPU_FF_SELM_SYNC_GDT \| VMCPU_FF_SELM_SYNC_LDT, 0 ) )
531
532	/** High priority VM pre raw-mode execution mask. */
533	#define VM_FF_HIGH_PRIORITY_PRE_RAW_MASK ( VM_FF_PGM_NEED_HANDY_PAGES \| VM_FF_PGM_NO_MEMORY )
534	/** High priority VMCPU pre raw-mode execution mask. */
535	#define VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK ( VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL \
536	\| VMCPU_FF_INHIBIT_INTERRUPTS \
537	\| VM_WHEN_RAW_MODE( VMCPU_FF_SELM_SYNC_TSS \| VMCPU_FF_TRPM_SYNC_IDT \
538	\| VMCPU_FF_SELM_SYNC_GDT \| VMCPU_FF_SELM_SYNC_LDT, 0) )
539
540	/** High priority post-execution actions. */
541	#define VM_FF_HIGH_PRIORITY_POST_MASK ( VM_FF_PGM_NO_MEMORY )
542	/** High priority post-execution actions. */
543	#define VMCPU_FF_HIGH_PRIORITY_POST_MASK ( VMCPU_FF_PDM_CRITSECT \| VM_WHEN_RAW_MODE(VMCPU_FF_CSAM_PENDING_ACTION, 0) \
544	\| VMCPU_FF_HM_UPDATE_CR3 \| VMCPU_FF_HM_UPDATE_PAE_PDPES \
545	\| VMCPU_FF_IEM \| VMCPU_FF_IOM )
546
547	/** Normal priority VM post-execution actions. */
548	#define VM_FF_NORMAL_PRIORITY_POST_MASK ( VM_FF_CHECK_VM_STATE \| VM_FF_DBGF \| VM_FF_RESET \
549	\| VM_FF_PGM_NO_MEMORY \| VM_FF_EMT_RENDEZVOUS)
550	/** Normal priority VMCPU post-execution actions. */
551	#define VMCPU_FF_NORMAL_PRIORITY_POST_MASK ( VM_WHEN_RAW_MODE(VMCPU_FF_CSAM_SCAN_PAGE, 0) \| VMCPU_FF_DBGF )
552
553	/** Normal priority VM actions. */
554	#define VM_FF_NORMAL_PRIORITY_MASK ( VM_FF_REQUEST \| VM_FF_PDM_QUEUES \| VM_FF_PDM_DMA \
555	\| VM_FF_REM_HANDLER_NOTIFY \| VM_FF_EMT_RENDEZVOUS)
556	/** Normal priority VMCPU actions. */
557	#define VMCPU_FF_NORMAL_PRIORITY_MASK ( VMCPU_FF_REQUEST )
558
559	/** Flags to clear before resuming guest execution. */
560	#define VMCPU_FF_RESUME_GUEST_MASK ( VMCPU_FF_TO_R3 )
561
562
563	/** VM flags that cause the REP[\|NE\|E] STRINS loops to yield immediately. */
564	#define VM_FF_HIGH_PRIORITY_POST_REPSTR_MASK ( VM_FF_TM_VIRTUAL_SYNC \| VM_FF_PGM_NEED_HANDY_PAGES \| VM_FF_PGM_NO_MEMORY \
565	\| VM_FF_EMT_RENDEZVOUS \| VM_FF_PGM_POOL_FLUSH_PENDING \| VM_FF_RESET)
566	/** VM flags that cause the REP[\|NE\|E] STRINS loops to yield. */
567	#define VM_FF_YIELD_REPSTR_MASK ( VM_FF_HIGH_PRIORITY_POST_REPSTR_MASK \
568	\| VM_FF_PDM_QUEUES \| VM_FF_PDM_DMA \| VM_FF_DBGF \| VM_FF_DEBUG_SUSPEND )
569	/** VMCPU flags that cause the REP[\|NE\|E] STRINS loops to yield immediately. */
570	#ifdef IN_RING3
571	# define VMCPU_FF_HIGH_PRIORITY_POST_REPSTR_MASK ( VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL \| VMCPU_FF_DBGF )
572	#else
573	# define VMCPU_FF_HIGH_PRIORITY_POST_REPSTR_MASK ( VMCPU_FF_TO_R3 \| VMCPU_FF_IEM \| VMCPU_FF_IOM \| VMCPU_FF_PGM_SYNC_CR3 \
574	\| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL \| VMCPU_FF_DBGF )
575	#endif
576	/** VMCPU flags that cause the REP[\|NE\|E] STRINS loops to yield, interrupts
577	* enabled. */
578	#define VMCPU_FF_YIELD_REPSTR_MASK ( VMCPU_FF_HIGH_PRIORITY_POST_REPSTR_MASK \
579	\| VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_UPDATE_APIC \| VMCPU_FF_INTERRUPT_PIC \
580	\| VMCPU_FF_INTERRUPT_NMI \| VMCPU_FF_INTERRUPT_SMI \| VMCPU_FF_PDM_CRITSECT \
581	\| VMCPU_FF_TIMER \| VMCPU_FF_REQUEST )
582	/** VMCPU flags that cause the REP[\|NE\|E] STRINS loops to yield, interrupts
583	* disabled. */
584	#define VMCPU_FF_YIELD_REPSTR_NOINT_MASK ( VMCPU_FF_YIELD_REPSTR_MASK \
585	& ~(VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_UPDATE_APIC \| VMCPU_FF_INTERRUPT_PIC) )
586
587	/** VM Flags that cause the HM loops to go back to ring-3. */
588	#define VM_FF_HM_TO_R3_MASK ( VM_FF_TM_VIRTUAL_SYNC \| VM_FF_PGM_NEED_HANDY_PAGES \| VM_FF_PGM_NO_MEMORY \
589	\| VM_FF_PDM_QUEUES \| VM_FF_EMT_RENDEZVOUS)
590	/** VMCPU Flags that cause the HM loops to go back to ring-3. */
591	#define VMCPU_FF_HM_TO_R3_MASK ( VMCPU_FF_TO_R3 \| VMCPU_FF_TIMER \| VMCPU_FF_PDM_CRITSECT \
592	\| VMCPU_FF_IEM \| VMCPU_FF_IOM)
593
594	/** High priority ring-0 VM pre HM-mode execution mask. */
595	#define VM_FF_HP_R0_PRE_HM_MASK (VM_FF_HM_TO_R3_MASK \| VM_FF_REQUEST \| VM_FF_PGM_POOL_FLUSH_PENDING \| VM_FF_PDM_DMA)
596	/** High priority ring-0 VMCPU pre HM-mode execution mask. */
597	#define VMCPU_FF_HP_R0_PRE_HM_MASK ( VMCPU_FF_HM_TO_R3_MASK \| VMCPU_FF_PGM_SYNC_CR3 \
598	\| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL \| VMCPU_FF_REQUEST)
599	/** High priority ring-0 VM pre HM-mode execution mask, single stepping. */
600	#define VM_FF_HP_R0_PRE_HM_STEP_MASK (VM_FF_HP_R0_PRE_HM_MASK & ~( VM_FF_TM_VIRTUAL_SYNC \| VM_FF_PDM_QUEUES \
601	\| VM_FF_EMT_RENDEZVOUS \| VM_FF_REQUEST \
602	\| VM_FF_PDM_DMA) )
603	/** High priority ring-0 VMCPU pre HM-mode execution mask, single stepping. */
604	#define VMCPU_FF_HP_R0_PRE_HM_STEP_MASK (VMCPU_FF_HP_R0_PRE_HM_MASK & ~( VMCPU_FF_TO_R3 \| VMCPU_FF_TIMER \
605	\| VMCPU_FF_PDM_CRITSECT \| VMCPU_FF_REQUEST) )
606
607	/** All the forced VM flags. */
608	#define VM_FF_ALL_MASK (UINT32_MAX)
609	/** All the forced VMCPU flags. */
610	#define VMCPU_FF_ALL_MASK (UINT32_MAX)
611
612	/** All the forced VM flags except those related to raw-mode and hardware
613	* assisted execution. */
614	#define VM_FF_ALL_REM_MASK (~(VM_FF_HIGH_PRIORITY_PRE_RAW_MASK) \| VM_FF_PGM_NEED_HANDY_PAGES \| VM_FF_PGM_NO_MEMORY)
615	/** All the forced VMCPU flags except those related to raw-mode and hardware
616	* assisted execution. */
617	#define VMCPU_FF_ALL_REM_MASK (~( VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK \| VMCPU_FF_PDM_CRITSECT \
618	\| VMCPU_FF_TLB_FLUSH \| VM_WHEN_RAW_MODE(VMCPU_FF_CSAM_PENDING_ACTION, 0) ))
619	/** @} */
620
621	/** @def VM_FF_SET
622	* Sets a force action flag.
623	*
624	* @param pVM The cross context VM structure.
625	* @param fFlag The flag to set.
626	*/
627	#if 1
628	# define VM_FF_SET(pVM, fFlag) ASMAtomicOrU32(&(pVM)->fGlobalForcedActions, (fFlag))
629	#else
630	# define VM_FF_SET(pVM, fFlag) \
631	do { ASMAtomicOrU32(&(pVM)->fGlobalForcedActions, (fFlag)); \
632	RTLogPrintf("VM_FF_SET : %08x %s - %s(%d) %s\n", (pVM)->fGlobalForcedActions, #fFlag, __FILE__, __LINE__, __FUNCTION__); \
633	} while (0)
634	#endif
635
636	/** @def VMCPU_FF_SET
637	* Sets a force action flag for the given VCPU.
638	*
639	* @param pVCpu The cross context virtual CPU structure.
640	* @param fFlag The flag to set.
641	*/
642	#define VMCPU_FF_SET(pVCpu, fFlag) ASMAtomicOrU32(&(pVCpu)->fLocalForcedActions, (fFlag))
643
644	/** @def VM_FF_CLEAR
645	* Clears a force action flag.
646	*
647	* @param pVM The cross context VM structure.
648	* @param fFlag The flag to clear.
649	*/
650	#if 1
651	# define VM_FF_CLEAR(pVM, fFlag) ASMAtomicAndU32(&(pVM)->fGlobalForcedActions, ~(fFlag))
652	#else
653	# define VM_FF_CLEAR(pVM, fFlag) \
654	do { ASMAtomicAndU32(&(pVM)->fGlobalForcedActions, ~(fFlag)); \
655	RTLogPrintf("VM_FF_CLEAR: %08x %s - %s(%d) %s\n", (pVM)->fGlobalForcedActions, #fFlag, __FILE__, __LINE__, __FUNCTION__); \
656	} while (0)
657	#endif
658
659	/** @def VMCPU_FF_CLEAR
660	* Clears a force action flag for the given VCPU.
661	*
662	* @param pVCpu The cross context virtual CPU structure.
663	* @param fFlag The flag to clear.
664	*/
665	#define VMCPU_FF_CLEAR(pVCpu, fFlag) ASMAtomicAndU32(&(pVCpu)->fLocalForcedActions, ~(fFlag))
666
667	/** @def VM_FF_IS_SET
668	* Checks if a force action flag is set.
669	*
670	* @param pVM The cross context VM structure.
671	* @param fFlag The flag to check.
672	*/
673	#define VM_FF_IS_SET(pVM, fFlag) (((pVM)->fGlobalForcedActions & (fFlag)) == (fFlag))
674
675	/** @def VMCPU_FF_IS_SET
676	* Checks if a force action flag is set for the given VCPU.
677	*
678	* @param pVCpu The cross context virtual CPU structure.
679	* @param fFlag The flag to check.
680	*/
681	#define VMCPU_FF_IS_SET(pVCpu, fFlag) (((pVCpu)->fLocalForcedActions & (fFlag)) == (fFlag))
682
683	/** @def VM_FF_IS_PENDING
684	* Checks if one or more force action in the specified set is pending.
685	*
686	* @param pVM The cross context VM structure.
687	* @param fFlags The flags to check for.
688	*/
689	#define VM_FF_IS_PENDING(pVM, fFlags) RT_BOOL((pVM)->fGlobalForcedActions & (fFlags))
690
691	/** @def VM_FF_TEST_AND_CLEAR
692	* Checks if one (!) force action in the specified set is pending and clears it atomically
693	*
694	* @returns true if the bit was set.
695	* @returns false if the bit was clear.
696	* @param pVM The cross context VM structure.
697	* @param iBit Bit position to check and clear
698	*/
699	#define VM_FF_TEST_AND_CLEAR(pVM, iBit) (ASMAtomicBitTestAndClear(&(pVM)->fGlobalForcedActions, iBit##_BIT))
700
701	/** @def VMCPU_FF_TEST_AND_CLEAR
702	* Checks if one (!) force action in the specified set is pending and clears it atomically
703	*
704	* @returns true if the bit was set.
705	* @returns false if the bit was clear.
706	* @param pVCpu The cross context virtual CPU structure.
707	* @param iBit Bit position to check and clear
708	*/
709	#define VMCPU_FF_TEST_AND_CLEAR(pVCpu, iBit) (ASMAtomicBitTestAndClear(&(pVCpu)->fLocalForcedActions, iBit##_BIT))
710
711	/** @def VMCPU_FF_IS_PENDING
712	* Checks if one or more force action in the specified set is pending for the given VCPU.
713	*
714	* @param pVCpu The cross context virtual CPU structure.
715	* @param fFlags The flags to check for.
716	*/
717	#define VMCPU_FF_IS_PENDING(pVCpu, fFlags) RT_BOOL((pVCpu)->fLocalForcedActions & (fFlags))
718
719	/** @def VM_FF_IS_PENDING_EXCEPT
720	* Checks if one or more force action in the specified set is pending while one
721	* or more other ones are not.
722	*
723	* @param pVM The cross context VM structure.
724	* @param fFlags The flags to check for.
725	* @param fExcpt The flags that should not be set.
726	*/
727	#define VM_FF_IS_PENDING_EXCEPT(pVM, fFlags, fExcpt) ( ((pVM)->fGlobalForcedActions & (fFlags)) && !((pVM)->fGlobalForcedActions & (fExcpt)) )
728
729	/** @def VMCPU_FF_IS_PENDING_EXCEPT
730	* Checks if one or more force action in the specified set is pending for the given
731	* VCPU while one or more other ones are not.
732	*
733	* @param pVCpu The cross context virtual CPU structure.
734	* @param fFlags The flags to check for.
735	* @param fExcpt The flags that should not be set.
736	*/
737	#define VMCPU_FF_IS_PENDING_EXCEPT(pVCpu, fFlags, fExcpt) ( ((pVCpu)->fLocalForcedActions & (fFlags)) && !((pVCpu)->fLocalForcedActions & (fExcpt)) )
738
739	/** @def VM_IS_EMT
740	* Checks if the current thread is the emulation thread (EMT).
741	*
742	* @remark The ring-0 variation will need attention if we expand the ring-0
743	* code to let threads other than EMT mess around with the VM.
744	*/
745	#ifdef IN_RC
746	# define VM_IS_EMT(pVM) true
747	#else
748	# define VM_IS_EMT(pVM) (VMMGetCpu(pVM) != NULL)
749	#endif
750
751	/** @def VMCPU_IS_EMT
752	* Checks if the current thread is the emulation thread (EMT) for the specified
753	* virtual CPU.
754	*/
755	#ifdef IN_RC
756	# define VMCPU_IS_EMT(pVCpu) true
757	#else
758	# define VMCPU_IS_EMT(pVCpu) ((pVCpu) && ((pVCpu) == VMMGetCpu((pVCpu)->CTX_SUFF(pVM))))
759	#endif
760
761	/** @def VM_ASSERT_EMT
762	* Asserts that the current thread IS the emulation thread (EMT).
763	*/
764	#ifdef IN_RC
765	# define VM_ASSERT_EMT(pVM) Assert(VM_IS_EMT(pVM))
766	#elif defined(IN_RING0)
767	# define VM_ASSERT_EMT(pVM) Assert(VM_IS_EMT(pVM))
768	#else
769	# define VM_ASSERT_EMT(pVM) \
770	AssertMsg(VM_IS_EMT(pVM), \
771	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd\n", RTThreadNativeSelf(), VMR3GetVMCPUNativeThread(pVM)))
772	#endif
773
774	/** @def VMCPU_ASSERT_EMT
775	* Asserts that the current thread IS the emulation thread (EMT) of the
776	* specified virtual CPU.
777	*/
778	#ifdef IN_RC
779	# define VMCPU_ASSERT_EMT(pVCpu) Assert(VMCPU_IS_EMT(pVCpu))
780	#elif defined(IN_RING0)
781	# define VMCPU_ASSERT_EMT(pVCpu) AssertMsg(VMCPU_IS_EMT(pVCpu), \
782	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd idCpu=%u\n", \
783	RTThreadNativeSelf(), (pVCpu) ? (pVCpu)->hNativeThreadR0 : 0, \
784	(pVCpu) ? (pVCpu)->idCpu : 0))
785	#else
786	# define VMCPU_ASSERT_EMT(pVCpu) AssertMsg(VMCPU_IS_EMT(pVCpu), \
787	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd idCpu=%#x\n", \
788	RTThreadNativeSelf(), (pVCpu)->hNativeThread, (pVCpu)->idCpu))
789	#endif
790
791	/** @def VM_ASSERT_EMT_RETURN
792	* Asserts that the current thread IS the emulation thread (EMT) and returns if it isn't.
793	*/
794	#ifdef IN_RC
795	# define VM_ASSERT_EMT_RETURN(pVM, rc) AssertReturn(VM_IS_EMT(pVM), (rc))
796	#elif defined(IN_RING0)
797	# define VM_ASSERT_EMT_RETURN(pVM, rc) AssertReturn(VM_IS_EMT(pVM), (rc))
798	#else
799	# define VM_ASSERT_EMT_RETURN(pVM, rc) \
800	AssertMsgReturn(VM_IS_EMT(pVM), \
801	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd\n", RTThreadNativeSelf(), VMR3GetVMCPUNativeThread(pVM)), \
802	(rc))
803	#endif
804
805	/** @def VMCPU_ASSERT_EMT_RETURN
806	* Asserts that the current thread IS the emulation thread (EMT) and returns if it isn't.
807	*/
808	#ifdef IN_RC
809	# define VMCPU_ASSERT_EMT_RETURN(pVCpu, rc) AssertReturn(VMCPU_IS_EMT(pVCpu), (rc))
810	#elif defined(IN_RING0)
811	# define VMCPU_ASSERT_EMT_RETURN(pVCpu, rc) AssertReturn(VMCPU_IS_EMT(pVCpu), (rc))
812	#else
813	# define VMCPU_ASSERT_EMT_RETURN(pVCpu, rc) \
814	AssertMsgReturn(VMCPU_IS_EMT(pVCpu), \
815	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd idCpu=%#x\n", \
816	RTThreadNativeSelf(), (pVCpu)->hNativeThread, (pVCpu)->idCpu), \
817	(rc))
818	#endif
819
820	/** @def VMCPU_ASSERT_EMT_OR_GURU
821	* Asserts that the current thread IS the emulation thread (EMT) of the
822	* specified virtual CPU.
823	*/
824	#if defined(IN_RC) \|\| defined(IN_RING0)
825	# define VMCPU_ASSERT_EMT_OR_GURU(pVCpu) Assert( VMCPU_IS_EMT(pVCpu) \
826	\|\| pVCpu->CTX_SUFF(pVM)->enmVMState == VMSTATE_GURU_MEDITATION \
827	\|\| pVCpu->CTX_SUFF(pVM)->enmVMState == VMSTATE_GURU_MEDITATION_LS )
828	#else
829	# define VMCPU_ASSERT_EMT_OR_GURU(pVCpu) \
830	AssertMsg( VMCPU_IS_EMT(pVCpu) \
831	\|\| pVCpu->CTX_SUFF(pVM)->enmVMState == VMSTATE_GURU_MEDITATION \
832	\|\| pVCpu->CTX_SUFF(pVM)->enmVMState == VMSTATE_GURU_MEDITATION_LS, \
833	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd idCpu=%#x\n", \
834	RTThreadNativeSelf(), (pVCpu)->hNativeThread, (pVCpu)->idCpu))
835	#endif
836
837	/** @def VMCPU_ASSERT_EMT_OR_NOT_RUNNING
838	* Asserts that the current thread IS the emulation thread (EMT) of the
839	* specified virtual CPU or the VM is not running.
840	*/
841	#if defined(IN_RC) \|\| defined(IN_RING0)
842	# define VMCPU_ASSERT_EMT_OR_NOT_RUNNING(pVCpu) \
843	Assert( VMCPU_IS_EMT(pVCpu) \
844	\|\| !VM_IS_RUNNING_FOR_ASSERTIONS_ONLY((pVCpu)->CTX_SUFF(pVM)) )
845	#else
846	# define VMCPU_ASSERT_EMT_OR_NOT_RUNNING(pVCpu) \
847	AssertMsg( VMCPU_IS_EMT(pVCpu) \
848	\|\| !VM_IS_RUNNING_FOR_ASSERTIONS_ONLY((pVCpu)->CTX_SUFF(pVM)), \
849	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd idCpu=%#x\n", \
850	RTThreadNativeSelf(), (pVCpu)->hNativeThread, (pVCpu)->idCpu))
851	#endif
852
853	/** @def VMSTATE_IS_RUNNING
854	* Checks if the given state indicates a running VM.
855	*/
856	#define VMSTATE_IS_RUNNING(a_enmVMState) \
857	( (enmVMState) == VMSTATE_RUNNING \
858	\|\| (enmVMState) == VMSTATE_RUNNING_LS \
859	\|\| (enmVMState) == VMSTATE_RUNNING_FT )
860
861	/** @def VM_IS_RUNNING_FOR_ASSERTIONS_ONLY
862	* Checks if the VM is running.
863	* @note This is only for pure debug assertions. No AssertReturn or similar!
864	* @sa VMSTATE_IS_RUNNING
865	*/
866	#define VM_IS_RUNNING_FOR_ASSERTIONS_ONLY(pVM) \
867	( (pVM)->enmVMState == VMSTATE_RUNNING \
868	\|\| (pVM)->enmVMState == VMSTATE_RUNNING_LS \
869	\|\| (pVM)->enmVMState == VMSTATE_RUNNING_FT )
870
871	/** @def VM_ASSERT_IS_NOT_RUNNING
872	* Asserts that the VM is not running.
873	*/
874	#if defined(IN_RC) \|\| defined(IN_RING0)
875	#define VM_ASSERT_IS_NOT_RUNNING(pVM) Assert(!VM_IS_RUNNING_FOR_ASSERTIONS_ONLY(pVM))
876	#else
877	#define VM_ASSERT_IS_NOT_RUNNING(pVM) AssertMsg(!VM_IS_RUNNING_FOR_ASSERTIONS_ONLY(pVM), \
878	("VM is running. enmVMState=%d\n", (pVM)->enmVMState))
879	#endif
880
881	/** @def VM_ASSERT_EMT0
882	* Asserts that the current thread IS emulation thread \#0 (EMT0).
883	*/
884	#define VM_ASSERT_EMT0(pVM) VMCPU_ASSERT_EMT(&(pVM)->aCpus[0])
885
886	/** @def VM_ASSERT_EMT0_RETURN
887	* Asserts that the current thread IS emulation thread \#0 (EMT0) and returns if
888	* it isn't.
889	*/
890	#define VM_ASSERT_EMT0_RETURN(pVM, rc) VMCPU_ASSERT_EMT_RETURN(&(pVM)->aCpus[0], (rc))
891
892
893	/**
894	* Asserts that the current thread is NOT the emulation thread.
895	*/
896	#define VM_ASSERT_OTHER_THREAD(pVM) \
897	AssertMsg(!VM_IS_EMT(pVM), ("Not other thread!!\n"))
898
899
900	/** @def VM_ASSERT_STATE
901	* Asserts a certain VM state.
902	*/
903	#define VM_ASSERT_STATE(pVM, _enmState) \
904	AssertMsg((pVM)->enmVMState == (_enmState), \
905	("state %s, expected %s\n", VMGetStateName((pVM)->enmVMState), VMGetStateName(_enmState)))
906
907	/** @def VM_ASSERT_STATE_RETURN
908	* Asserts a certain VM state and returns if it doesn't match.
909	*/
910	#define VM_ASSERT_STATE_RETURN(pVM, _enmState, rc) \
911	AssertMsgReturn((pVM)->enmVMState == (_enmState), \
912	("state %s, expected %s\n", VMGetStateName((pVM)->enmVMState), VMGetStateName(_enmState)), \
913	(rc))
914
915	/** @def VM_IS_VALID_EXT
916	* Asserts a the VM handle is valid for external access, i.e. not being destroy
917	* or terminated. */
918	#define VM_IS_VALID_EXT(pVM) \
919	( RT_VALID_ALIGNED_PTR(pVM, PAGE_SIZE) \
920	&& ( (unsigned)(pVM)->enmVMState < (unsigned)VMSTATE_DESTROYING \
921	\|\| ( (unsigned)(pVM)->enmVMState == (unsigned)VMSTATE_DESTROYING \
922	&& VM_IS_EMT(pVM))) )
923
924	/** @def VM_ASSERT_VALID_EXT_RETURN
925	* Asserts a the VM handle is valid for external access, i.e. not being
926	* destroy or terminated.
927	*/
928	#define VM_ASSERT_VALID_EXT_RETURN(pVM, rc) \
929	AssertMsgReturn(VM_IS_VALID_EXT(pVM), \
930	("pVM=%p state %s\n", (pVM), RT_VALID_ALIGNED_PTR(pVM, PAGE_SIZE) \
931	? VMGetStateName(pVM->enmVMState) : ""), \
932	(rc))
933
934	/** @def VMCPU_ASSERT_VALID_EXT_RETURN
935	* Asserts a the VMCPU handle is valid for external access, i.e. not being
936	* destroy or terminated.
937	*/
938	#define VMCPU_ASSERT_VALID_EXT_RETURN(pVCpu, rc) \
939	AssertMsgReturn( RT_VALID_ALIGNED_PTR(pVCpu, 64) \
940	&& RT_VALID_ALIGNED_PTR((pVCpu)->CTX_SUFF(pVM), PAGE_SIZE) \
941	&& (unsigned)(pVCpu)->CTX_SUFF(pVM)->enmVMState < (unsigned)VMSTATE_DESTROYING, \
942	("pVCpu=%p pVM=%p state %s\n", (pVCpu), RT_VALID_ALIGNED_PTR(pVCpu, 64) ? (pVCpu)->CTX_SUFF(pVM) : NULL, \
943	RT_VALID_ALIGNED_PTR(pVCpu, 64) && RT_VALID_ALIGNED_PTR((pVCpu)->CTX_SUFF(pVM), PAGE_SIZE) \
944	? VMGetStateName((pVCpu)->pVMR3->enmVMState) : ""), \
945	(rc))
946
947	#endif /* !VBOX_FOR_DTRACE_LIB */
948
949
950	/**
951	* Helper that HM and NEM uses for safely modifying VM::bMainExecutionEngine.
952	*
953	* ONLY HM and NEM MAY USE THIS!
954	*
955	* @param a_pVM The cross context VM structure.
956	* @param a_bValue The new value.
957	* @internal
958	*/
959	#define VM_SET_MAIN_EXECUTION_ENGINE(a_pVM, a_bValue) \
960	do { \
961	const_cast<uint8_t >(&(a_pVM)->bMainExecutionEngine) = (a_bValue); \
962	ASMCompilerBarrier(); /* just to be on the safe side */ \
963	} while (0)
964
965	/**
966	* Checks whether raw-mode is used.
967	*
968	* @retval true if either is used.
969	* @retval false if software virtualization (raw-mode) is used.
970	*
971	* @param a_pVM The cross context VM structure.
972	* @sa VM_IS_HM_OR_NEM_ENABLED, VM_IS_HM_ENABLED, VM_IS_NEM_ENABLED.
973	* @internal
974	*/
975	#ifdef VBOX_WITH_RAW_MODE
976	# define VM_IS_RAW_MODE_ENABLED(a_pVM) ((a_pVM)->bMainExecutionEngine == VM_EXEC_ENGINE_RAW_MODE)
977	#else
978	# define VM_IS_RAW_MODE_ENABLED(a_pVM) (false)
979	#endif
980
981	/**
982	* Checks whether HM (VT-x/AMD-V) or NEM is being used by this VM.
983	*
984	* @retval true if either is used.
985	* @retval false if software virtualization (raw-mode) is used.
986	*
987	* @param a_pVM The cross context VM structure.
988	* @sa VM_IS_RAW_MODE_ENABLED, VM_IS_HM_ENABLED, VM_IS_NEM_ENABLED.
989	* @internal
990	*/
991	#define VM_IS_HM_OR_NEM_ENABLED(a_pVM) ((a_pVM)->bMainExecutionEngine != VM_EXEC_ENGINE_RAW_MODE)
992
993	/**
994	* Checks whether HM is being used by this VM.
995	*
996	* @retval true if HM (VT-x/AMD-v) is used.
997	* @retval false if not.
998	*
999	* @param a_pVM The cross context VM structure.
1000	* @sa VM_IS_NEM_ENABLED, VM_IS_RAW_MODE_ENABLED, VM_IS_HM_OR_NEM_ENABLED.
1001	* @internal
1002	*/
1003	#define VM_IS_HM_ENABLED(a_pVM) ((a_pVM)->bMainExecutionEngine == VM_EXEC_ENGINE_HW_VIRT)
1004
1005	/**
1006	* Checks whether NEM is being used by this VM.
1007	*
1008	* @retval true if a native hypervisor API is used.
1009	* @retval false if not.
1010	*
1011	* @param a_pVM The cross context VM structure.
1012	* @sa VM_IS_HM_ENABLED, VM_IS_RAW_MODE_ENABLED, VM_IS_HM_OR_NEM_ENABLED.
1013	* @internal
1014	*/
1015	#define VM_IS_NEM_ENABLED(a_pVM) ((a_pVM)->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API)
1016
1017
1018	/**
1019	* The cross context VM structure.
1020	*
1021	* It contains all the VM data which have to be available in all contexts.
1022	* Even if it contains all the data the idea is to use APIs not to modify all
1023	* the members all around the place. Therefore we make use of unions to hide
1024	* everything which isn't local to the current source module. This means we'll
1025	* have to pay a little bit of attention when adding new members to structures
1026	* in the unions and make sure to keep the padding sizes up to date.
1027	*
1028	* Run 'kmk run-struct-tests' (from src/VBox/VMM if you like) after updating!
1029	*/
1030	typedef struct VM
1031	{
1032	/** The state of the VM.
1033	* This field is read only to everyone except the VM and EM. */
1034	VMSTATE volatile enmVMState;
1035	/** Forced action flags.
1036	* See the VM_FF_* \#defines. Updated atomically.
1037	*/
1038	volatile uint32_t fGlobalForcedActions;
1039	/** Pointer to the array of page descriptors for the VM structure allocation. */
1040	R3PTRTYPE(PSUPPAGE) paVMPagesR3;
1041	/** Session handle. For use when calling SUPR0 APIs. */
1042	PSUPDRVSESSION pSession;
1043	/** Pointer to the ring-3 VM structure. */
1044	PUVM pUVM;
1045	/** Ring-3 Host Context VM Pointer. */
1046	R3PTRTYPE(struct VM *) pVMR3;
1047	/** Ring-0 Host Context VM Pointer. */
1048	R0PTRTYPE(struct VM *) pVMR0;
1049	/** Raw-mode Context VM Pointer. */
1050	RCPTRTYPE(struct VM *) pVMRC;
1051
1052	/** The GVM VM handle. Only the GVM should modify this field. */
1053	uint32_t hSelf;
1054	/** Number of virtual CPUs. */
1055	uint32_t cCpus;
1056	/** CPU excution cap (1-100) */
1057	uint32_t uCpuExecutionCap;
1058
1059	/** Size of the VM structure including the VMCPU array. */
1060	uint32_t cbSelf;
1061
1062	/** Offset to the VMCPU array starting from beginning of this structure. */
1063	uint32_t offVMCPU;
1064
1065	/**
1066	* VMMSwitcher assembly entry point returning to host context.
1067	*
1068	* Depending on how the host handles the rc status given in @a eax, this may
1069	* return and let the caller resume whatever it was doing prior to the call.
1070	*
1071	*
1072	* @param eax The return code, register.
1073	* @remark Assume interrupts disabled.
1074	* @remark This method pointer lives here because TRPM needs it.
1075	*/
1076	RTRCPTR pfnVMMRCToHostAsm/(int32_t eax)/;
1077
1078	/**
1079	* VMMSwitcher assembly entry point returning to host context without saving the
1080	* raw-mode context (hyper) registers.
1081	*
1082	* Unlike pfnVMMRC2HCAsm, this will not return to the caller. Instead it
1083	* expects the caller to save a RC context in CPUM where one might return if the
1084	* return code indicate that this is possible.
1085	*
1086	* This method pointer lives here because TRPM needs it.
1087	*
1088	* @param eax The return code, register.
1089	* @remark Assume interrupts disabled.
1090	* @remark This method pointer lives here because TRPM needs it.
1091	*/
1092	RTRCPTR pfnVMMRCToHostAsmNoReturn/(int32_t eax)/;
1093
1094	/** @name Various items that are frequently accessed.
1095	* @{ */
1096	/** The main execution engine, VM_EXEC_ENGINE_XXX.
1097	* This is set early during vmR3InitRing3 by HM or NEM. */
1098	uint8_t const bMainExecutionEngine;
1099
1100	/** Whether to recompile user mode code or run it raw/hm/nem.
1101	* In non-raw-mode both fRecompileUser and fRecompileSupervisor must be set
1102	* to recompiler stuff. */
1103	bool fRecompileUser;
1104	/** Whether to recompile supervisor mode code or run it raw/hm/nem.
1105	* In non-raw-mode both fRecompileUser and fRecompileSupervisor must be set
1106	* to recompiler stuff. */
1107	bool fRecompileSupervisor;
1108	/** Whether raw mode supports ring-1 code or not.
1109	* This will be cleared when not in raw-mode. */
1110	bool fRawRing1Enabled;
1111	/** PATM enabled flag.
1112	* This is placed here for performance reasons.
1113	* This will be cleared when not in raw-mode. */
1114	bool fPATMEnabled;
1115	/** CSAM enabled flag.
1116	* This is placed here for performance reasons.
1117	* This will be cleared when not in raw-mode. */
1118	bool fCSAMEnabled;
1119
1120	/** Hardware VM support is available and enabled.
1121	* Determined very early during init.
1122	* This is placed here for performance reasons.
1123	* @todo obsoleted by bMainExecutionEngine, eliminate. */
1124	bool fHMEnabled;
1125	/** Hardware VM support requires a minimal raw-mode context.
1126	* This is never set on 64-bit hosts, only 32-bit hosts requires it. */
1127	bool fHMNeedRawModeCtx;
1128
1129	/** Set when this VM is the master FT node.
1130	* @todo This doesn't need to be here, FTM should store it in it's own
1131	* structures instead. */
1132	bool fFaultTolerantMaster;
1133	/** Large page enabled flag.
1134	* @todo This doesn't need to be here, PGM should store it in it's own
1135	* structures instead. */
1136	bool fUseLargePages;
1137	/** @} */
1138
1139	/** Alignment padding. */
1140	uint8_t uPadding1[2];
1141
1142	/** @name Debugging
1143	* @{ */
1144	/** Raw-mode Context VM Pointer. */
1145	RCPTRTYPE(RTTRACEBUF) hTraceBufRC;
1146	/** Ring-3 Host Context VM Pointer. */
1147	R3PTRTYPE(RTTRACEBUF) hTraceBufR3;
1148	/** Ring-0 Host Context VM Pointer. */
1149	R0PTRTYPE(RTTRACEBUF) hTraceBufR0;
1150	/** @} */
1151
1152	#if HC_ARCH_BITS == 32
1153	/** Alignment padding. */
1154	uint32_t uPadding2;
1155	#endif
1156
1157	/** @name Switcher statistics (remove)
1158	* @{ */
1159	/** Profiling the total time from Qemu to GC. */
1160	STAMPROFILEADV StatTotalQemuToGC;
1161	/** Profiling the total time from GC to Qemu. */
1162	STAMPROFILEADV StatTotalGCToQemu;
1163	/** Profiling the total time spent in GC. */
1164	STAMPROFILEADV StatTotalInGC;
1165	/** Profiling the total time spent not in Qemu. */
1166	STAMPROFILEADV StatTotalInQemu;
1167	/** Profiling the VMMSwitcher code for going to GC. */
1168	STAMPROFILEADV StatSwitcherToGC;
1169	/** Profiling the VMMSwitcher code for going to HC. */
1170	STAMPROFILEADV StatSwitcherToHC;
1171	STAMPROFILEADV StatSwitcherSaveRegs;
1172	STAMPROFILEADV StatSwitcherSysEnter;
1173	STAMPROFILEADV StatSwitcherDebug;
1174	STAMPROFILEADV StatSwitcherCR0;
1175	STAMPROFILEADV StatSwitcherCR4;
1176	STAMPROFILEADV StatSwitcherJmpCR3;
1177	STAMPROFILEADV StatSwitcherRstrRegs;
1178	STAMPROFILEADV StatSwitcherLgdt;
1179	STAMPROFILEADV StatSwitcherLidt;
1180	STAMPROFILEADV StatSwitcherLldt;
1181	STAMPROFILEADV StatSwitcherTSS;
1182	/** @} */
1183
1184	/** Padding - the unions must be aligned on a 64 bytes boundary and the unions
1185	* must start at the same offset on both 64-bit and 32-bit hosts. */
1186	uint8_t abAlignment3[(HC_ARCH_BITS == 32 ? 24 : 0) + 40];
1187
1188	/** CPUM part. */
1189	union
1190	{
1191	#ifdef ___CPUMInternal_h
1192	struct CPUM s;
1193	#endif
1194	#ifdef ___VBox_vmm_cpum_h
1195	/** Read only info exposed about the host and guest CPUs. */
1196	struct
1197	{
1198	/** Padding for hidden fields. */
1199	uint8_t abHidden0[64];
1200	/** Host CPU feature information. */
1201	CPUMFEATURES HostFeatures;
1202	/** Guest CPU feature information. */
1203	CPUMFEATURES GuestFeatures;
1204	} const ro;
1205	#endif
1206	uint8_t padding[1536]; /* multiple of 64 */
1207	} cpum;
1208
1209	/** VMM part. */
1210	union
1211	{
1212	#ifdef ___VMMInternal_h
1213	struct VMM s;
1214	#endif
1215	uint8_t padding[1600]; /* multiple of 64 */
1216	} vmm;
1217
1218	/** PGM part. */
1219	union
1220	{
1221	#ifdef ___PGMInternal_h
1222	struct PGM s;
1223	#endif
1224	uint8_t padding[40962+6080]; / multiple of 64 */
1225	} pgm;
1226
1227	/** HM part. */
1228	union
1229	{
1230	#ifdef ___HMInternal_h
1231	struct HM s;
1232	#endif
1233	uint8_t padding[5440]; /* multiple of 64 */
1234	} hm;
1235
1236	/** TRPM part. */
1237	union
1238	{
1239	#ifdef ___TRPMInternal_h
1240	struct TRPM s;
1241	#endif
1242	uint8_t padding[5248]; /* multiple of 64 */
1243	} trpm;
1244
1245	/** SELM part. */
1246	union
1247	{
1248	#ifdef ___SELMInternal_h
1249	struct SELM s;
1250	#endif
1251	uint8_t padding[768]; /* multiple of 64 */
1252	} selm;
1253
1254	/** MM part. */
1255	union
1256	{
1257	#ifdef ___MMInternal_h
1258	struct MM s;
1259	#endif
1260	uint8_t padding[192]; /* multiple of 64 */
1261	} mm;
1262
1263	/** PDM part. */
1264	union
1265	{
1266	#ifdef ___PDMInternal_h
1267	struct PDM s;
1268	#endif
1269	uint8_t padding[1920]; /* multiple of 64 */
1270	} pdm;
1271
1272	/** IOM part. */
1273	union
1274	{
1275	#ifdef ___IOMInternal_h
1276	struct IOM s;
1277	#endif
1278	uint8_t padding[896]; /* multiple of 64 */
1279	} iom;
1280
1281	/** EM part. */
1282	union
1283	{
1284	#ifdef ___EMInternal_h
1285	struct EM s;
1286	#endif
1287	uint8_t padding[256]; /* multiple of 64 */
1288	} em;
1289
1290	/** NEM part. */
1291	union
1292	{
1293	#ifdef ___NEMInternal_h
1294	struct NEM s;
1295	#endif
1296	uint8_t padding[128]; /* multiple of 64 */
1297	} nem;
1298
1299	/** TM part. */
1300	union
1301	{
1302	#ifdef ___TMInternal_h
1303	struct TM s;
1304	#endif
1305	uint8_t padding[2496]; /* multiple of 64 */
1306	} tm;
1307
1308	/** DBGF part. */
1309	union
1310	{
1311	#ifdef ___DBGFInternal_h
1312	struct DBGF s;
1313	#endif
1314	#ifdef ___VBox_vmm_dbgf_h
1315	/** Read only info exposed about interrupt breakpoints and selected events. */
1316	struct
1317	{
1318	/** Bitmap of enabled hardware interrupt breakpoints. */
1319	uint32_t bmHardIntBreakpoints[256 / 32];
1320	/** Bitmap of enabled software interrupt breakpoints. */
1321	uint32_t bmSoftIntBreakpoints[256 / 32];
1322	/** Bitmap of selected events.
1323	* This includes non-selectable events too for simplicity, we maintain the
1324	* state for some of these, as it may come in handy. */
1325	uint64_t bmSelectedEvents[(DBGFEVENT_END + 63) / 64];
1326	/** Enabled hardware interrupt breakpoints. */
1327	uint32_t cHardIntBreakpoints;
1328	/** Enabled software interrupt breakpoints. */
1329	uint32_t cSoftIntBreakpoints;
1330	/** The number of selected events. */
1331	uint32_t cSelectedEvents;
1332	/** The number of enabled hardware breakpoints. */
1333	uint8_t cEnabledHwBreakpoints;
1334	/** The number of enabled hardware I/O breakpoints. */
1335	uint8_t cEnabledHwIoBreakpoints;
1336	/** The number of enabled INT3 breakpoints. */
1337	uint8_t cEnabledInt3Breakpoints;
1338	uint8_t abPadding[1]; /*< Unused padding space up for grabs. /
1339	} const ro;
1340	#endif
1341	uint8_t padding[2432]; /* multiple of 64 */
1342	} dbgf;
1343
1344	/** SSM part. */
1345	union
1346	{
1347	#ifdef ___SSMInternal_h
1348	struct SSM s;
1349	#endif
1350	uint8_t padding[128]; /* multiple of 64 */
1351	} ssm;
1352
1353	/** FTM part. */
1354	union
1355	{
1356	#ifdef ___FTMInternal_h
1357	struct FTM s;
1358	#endif
1359	uint8_t padding[512]; /* multiple of 64 */
1360	} ftm;
1361
1362	#ifdef VBOX_WITH_RAW_MODE
1363	/** PATM part. */
1364	union
1365	{
1366	# ifdef ___PATMInternal_h
1367	struct PATM s;
1368	# endif
1369	uint8_t padding[768]; /* multiple of 64 */
1370	} patm;
1371
1372	/** CSAM part. */
1373	union
1374	{
1375	# ifdef ___CSAMInternal_h
1376	struct CSAM s;
1377	# endif
1378	uint8_t padding[1088]; /* multiple of 64 */
1379	} csam;
1380	#endif
1381
1382	#ifdef VBOX_WITH_REM
1383	/** REM part. */
1384	union
1385	{
1386	# ifdef ___REMInternal_h
1387	struct REM s;
1388	# endif
1389	uint8_t padding[0x11100]; /* multiple of 64 */
1390	} rem;
1391	#endif
1392
1393	union
1394	{
1395	#ifdef ___GIMInternal_h
1396	struct GIM s;
1397	#endif
1398	uint8_t padding[448]; /* multiple of 64 */
1399	} gim;
1400
1401	union
1402	{
1403	#ifdef ___APICInternal_h
1404	struct APIC s;
1405	#endif
1406	uint8_t padding[128]; /* multiple of 8 */
1407	} apic;
1408
1409	/* ---- begin small stuff ---- */
1410
1411	/** VM part. */
1412	union
1413	{
1414	#ifdef ___VMInternal_h
1415	struct VMINT s;
1416	#endif
1417	uint8_t padding[32]; /* multiple of 8 */
1418	} vm;
1419
1420	/** CFGM part. */
1421	union
1422	{
1423	#ifdef ___CFGMInternal_h
1424	struct CFGM s;
1425	#endif
1426	uint8_t padding[8]; /* multiple of 8 */
1427	} cfgm;
1428
1429	/** Padding for aligning the cpu array on a page boundary. */
1430	#if defined(VBOX_WITH_REM) && defined(VBOX_WITH_RAW_MODE)
1431	uint8_t abAlignment2[3670];
1432	#elif defined(VBOX_WITH_REM) && !defined(VBOX_WITH_RAW_MODE)
1433	uint8_t abAlignment2[1430];
1434	#elif !defined(VBOX_WITH_REM) && defined(VBOX_WITH_RAW_MODE)
1435	uint8_t abAlignment2[3926];
1436	#else
1437	uint8_t abAlignment2[1686];
1438	#endif
1439
1440	/* ---- end small stuff ---- */
1441
1442	/** VMCPU array for the configured number of virtual CPUs.
1443	* Must be aligned on a page boundary for TLB hit reasons as well as
1444	* alignment of VMCPU members. */
1445	VMCPU aCpus[1];
1446	} VM;
1447
1448
1449	#ifdef IN_RC
1450	RT_C_DECLS_BEGIN
1451
1452	/** The VM structure.
1453	* This is imported from the VMMRCBuiltin module, i.e. it's a one of those magic
1454	* globals which we should avoid using.
1455	*/
1456	extern DECLIMPORT(VM) g_VM;
1457
1458	RT_C_DECLS_END
1459	#endif
1460
1461	/** @} */
1462
1463	#endif
1464

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source: vbox/trunk/include/VBox/vmm/vm.h@ 74491

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