VirtualBox

source: vbox/trunk/include/VBox/vmm/vm.h@ 74787

Last change on this file since 74787 was 74787, checked in by vboxsync, 6 years ago

vm.h,VMM: Made VM_FF_CLEAR work on a single flag too. bugref:9180

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1/** @file
2 * VM - The Virtual Machine, data.
3 */
4
5/*
6 * Copyright (C) 2006-2017 Oracle Corporation
7 *
8 * This file is part of VirtualBox Open Source Edition (OSE), as
9 * available from http://www.virtualbox.org. This file is free software;
10 * you can redistribute it and/or modify it under the terms of the GNU
11 * General Public License (GPL) as published by the Free Software
12 * Foundation, in version 2 as it comes in the "COPYING" file of the
13 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15 *
16 * The contents of this file may alternatively be used under the terms
17 * of the Common Development and Distribution License Version 1.0
18 * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19 * VirtualBox OSE distribution, in which case the provisions of the
20 * CDDL are applicable instead of those of the GPL.
21 *
22 * You may elect to license modified versions of this file under the
23 * terms and conditions of either the GPL or the CDDL or both.
24 */
25
26#ifndef ___VBox_vmm_vm_h
27#define ___VBox_vmm_vm_h
28
29#ifndef VBOX_FOR_DTRACE_LIB
30# include <iprt/param.h>
31# include <VBox/types.h>
32# include <VBox/vmm/cpum.h>
33# include <VBox/vmm/stam.h>
34# include <VBox/vmm/vmapi.h>
35# include <VBox/vmm/vmm.h>
36# include <VBox/sup.h>
37#else
38# pragma D depends_on library vbox-types.d
39# pragma D depends_on library CPUMInternal.d
40# define ___CPUMInternal_h
41#endif
42
43
44
45/** @defgroup grp_vm The Virtual Machine
46 * @ingroup grp_vmm
47 * @{
48 */
49
50/**
51 * The state of a Virtual CPU.
52 *
53 * The basic state indicated here is whether the CPU has been started or not. In
54 * addition, there are sub-states when started for assisting scheduling (GVMM
55 * mostly).
56 *
57 * The transition out of the STOPPED state is done by a vmR3PowerOn.
58 * The transition back to the STOPPED state is done by vmR3PowerOff.
59 *
60 * (Alternatively we could let vmR3PowerOn start CPU 0 only and let the SPIP
61 * handling switch on the other CPUs. Then vmR3Reset would stop all but CPU 0.)
62 */
63typedef enum VMCPUSTATE
64{
65 /** The customary invalid zero. */
66 VMCPUSTATE_INVALID = 0,
67
68 /** Virtual CPU has not yet been started. */
69 VMCPUSTATE_STOPPED,
70
71 /** CPU started. */
72 VMCPUSTATE_STARTED,
73 /** CPU started in HM context. */
74 VMCPUSTATE_STARTED_HM,
75 /** Executing guest code and can be poked (RC or STI bits of HM). */
76 VMCPUSTATE_STARTED_EXEC,
77 /** Executing guest code in the recompiler. */
78 VMCPUSTATE_STARTED_EXEC_REM,
79 /** Executing guest code using NEM. */
80 VMCPUSTATE_STARTED_EXEC_NEM,
81 VMCPUSTATE_STARTED_EXEC_NEM_WAIT,
82 VMCPUSTATE_STARTED_EXEC_NEM_CANCELED,
83 /** Halted. */
84 VMCPUSTATE_STARTED_HALTED,
85
86 /** The end of valid virtual CPU states. */
87 VMCPUSTATE_END,
88
89 /** Ensure 32-bit type. */
90 VMCPUSTATE_32BIT_HACK = 0x7fffffff
91} VMCPUSTATE;
92
93
94/**
95 * The cross context virtual CPU structure.
96 *
97 * Run 'kmk run-struct-tests' (from src/VBox/VMM if you like) after updating!
98 */
99typedef struct VMCPU
100{
101 /** Per CPU forced action.
102 * See the VMCPU_FF_* \#defines. Updated atomically. */
103 uint32_t volatile fLocalForcedActions; /* 0 */
104 /** The CPU state. */
105 VMCPUSTATE volatile enmState; /* 4 */
106
107 /** Pointer to the ring-3 UVMCPU structure. */
108 PUVMCPU pUVCpu; /* 8 */
109 /** Ring-3 Host Context VM Pointer. */
110 PVMR3 pVMR3; /* 16 / 12 */
111 /** Ring-0 Host Context VM Pointer. */
112 PVMR0 pVMR0; /* 24 / 16 */
113 /** Raw-mode Context VM Pointer. */
114 PVMRC pVMRC; /* 32 / 20 */
115 /** The CPU ID.
116 * This is the index into the VM::aCpu array. */
117 VMCPUID idCpu; /* 36 / 24 */
118 /** The native thread handle. */
119 RTNATIVETHREAD hNativeThread; /* 40 / 28 */
120 /** The native R0 thread handle. (different from the R3 handle!) */
121 RTNATIVETHREAD hNativeThreadR0; /* 48 / 32 */
122 /** Which host CPU ID is this EMT running on.
123 * Only valid when in RC or HMR0 with scheduling disabled. */
124 RTCPUID volatile idHostCpu; /* 56 / 36 */
125 /** The CPU set index corresponding to idHostCpu, UINT32_MAX if not valid.
126 * @remarks Best to make sure iHostCpuSet shares cache line with idHostCpu! */
127 uint32_t volatile iHostCpuSet; /* 60 / 40 */
128
129#if HC_ARCH_BITS == 32
130 /** Align the structures below bit on a 64-byte boundary and make sure it starts
131 * at the same offset in both 64-bit and 32-bit builds.
132 *
133 * @remarks The alignments of the members that are larger than 48 bytes should be
134 * 64-byte for cache line reasons. structs containing small amounts of
135 * data could be lumped together at the end with a < 64 byte padding
136 * following it (to grow into and align the struct size).
137 */
138 uint8_t abAlignment1[HC_ARCH_BITS == 64 ? 0 : 20];
139#endif
140
141 /** IEM part.
142 * @remarks This comes first as it allows the use of 8-bit immediates for the
143 * first 64 bytes of the structure, reducing code size a wee bit. */
144#ifdef ___IEMInternal_h /* For PDB hacking. */
145 union VMCPUUNIONIEMFULL
146#else
147 union VMCPUUNIONIEMSTUB
148#endif
149 {
150#ifdef ___IEMInternal_h
151 struct IEMCPU s;
152#endif
153 uint8_t padding[18496]; /* multiple of 64 */
154 } iem;
155
156 /** HM part. */
157 union VMCPUUNIONHM
158 {
159#ifdef ___HMInternal_h
160 struct HMCPU s;
161#endif
162 uint8_t padding[5888]; /* multiple of 64 */
163 } hm;
164
165 /** NEM part. */
166 union VMCPUUNIONNEM
167 {
168#ifdef ___NEMInternal_h
169 struct NEMCPU s;
170#endif
171 uint8_t padding[512]; /* multiple of 64 */
172 } nem;
173
174 /** TRPM part. */
175 union VMCPUUNIONTRPM
176 {
177#ifdef ___TRPMInternal_h
178 struct TRPMCPU s;
179#endif
180 uint8_t padding[128]; /* multiple of 64 */
181 } trpm;
182
183 /** TM part. */
184 union VMCPUUNIONTM
185 {
186#ifdef ___TMInternal_h
187 struct TMCPU s;
188#endif
189 uint8_t padding[384]; /* multiple of 64 */
190 } tm;
191
192 /** VMM part. */
193 union VMCPUUNIONVMM
194 {
195#ifdef ___VMMInternal_h
196 struct VMMCPU s;
197#endif
198 uint8_t padding[768]; /* multiple of 64 */
199 } vmm;
200
201 /** PDM part. */
202 union VMCPUUNIONPDM
203 {
204#ifdef ___PDMInternal_h
205 struct PDMCPU s;
206#endif
207 uint8_t padding[256]; /* multiple of 64 */
208 } pdm;
209
210 /** IOM part. */
211 union VMCPUUNIONIOM
212 {
213#ifdef ___IOMInternal_h
214 struct IOMCPU s;
215#endif
216 uint8_t padding[512]; /* multiple of 64 */
217 } iom;
218
219 /** DBGF part.
220 * @todo Combine this with other tiny structures. */
221 union VMCPUUNIONDBGF
222 {
223#ifdef ___DBGFInternal_h
224 struct DBGFCPU s;
225#endif
226 uint8_t padding[256]; /* multiple of 64 */
227 } dbgf;
228
229 /** GIM part. */
230 union VMCPUUNIONGIM
231 {
232#ifdef ___GIMInternal_h
233 struct GIMCPU s;
234#endif
235 uint8_t padding[512]; /* multiple of 64 */
236 } gim;
237
238 /** APIC part. */
239 union VMCPUUNIONAPIC
240 {
241#ifdef ___APICInternal_h
242 struct APICCPU s;
243#endif
244 uint8_t padding[1792]; /* multiple of 64 */
245 } apic;
246
247 /*
248 * Some less frequently used global members that doesn't need to take up
249 * precious space at the head of the structure.
250 */
251
252 /** Trace groups enable flags. */
253 uint32_t fTraceGroups; /* 64 / 44 */
254 /** State data for use by ad hoc profiling. */
255 uint32_t uAdHoc;
256 /** Profiling samples for use by ad hoc profiling. */
257 STAMPROFILEADV aStatAdHoc[8]; /* size: 40*8 = 320 */
258
259 /** Align the following members on page boundary. */
260 uint8_t abAlignment2[2872];
261
262 /** PGM part. */
263 union VMCPUUNIONPGM
264 {
265#ifdef ___PGMInternal_h
266 struct PGMCPU s;
267#endif
268 uint8_t padding[4096]; /* multiple of 4096 */
269 } pgm;
270
271 /** CPUM part. */
272 union VMCPUUNIONCPUM
273 {
274#ifdef ___CPUMInternal_h
275 struct CPUMCPU s;
276#endif
277#ifdef VMCPU_INCL_CPUM_GST_CTX
278 /** The guest CPUM context for direct use by execution engines.
279 * This is not for general consumption, but for HM, REM, IEM, and maybe a few
280 * others. The rest will use the function based CPUM API. */
281 CPUMCTX GstCtx;
282#endif
283 uint8_t padding[4096]; /* multiple of 4096 */
284 } cpum;
285
286 /** EM part. */
287 union VMCPUUNIONEM
288 {
289#ifdef ___EMInternal_h
290 struct EMCPU s;
291#endif
292 uint8_t padding[40960]; /* multiple of 4096 */
293 } em;
294} VMCPU;
295
296
297#ifndef VBOX_FOR_DTRACE_LIB
298
299/** @name Operations on VMCPU::enmState
300 * @{ */
301/** Gets the VMCPU state. */
302#define VMCPU_GET_STATE(pVCpu) ( (pVCpu)->enmState )
303/** Sets the VMCPU state. */
304#define VMCPU_SET_STATE(pVCpu, enmNewState) \
305 ASMAtomicWriteU32((uint32_t volatile *)&(pVCpu)->enmState, (enmNewState))
306/** Cmpares and sets the VMCPU state. */
307#define VMCPU_CMPXCHG_STATE(pVCpu, enmNewState, enmOldState) \
308 ASMAtomicCmpXchgU32((uint32_t volatile *)&(pVCpu)->enmState, (enmNewState), (enmOldState))
309/** Checks the VMCPU state. */
310#ifdef VBOX_STRICT
311# define VMCPU_ASSERT_STATE(pVCpu, enmExpectedState) \
312 do { \
313 VMCPUSTATE enmState = VMCPU_GET_STATE(pVCpu); \
314 AssertMsg(enmState == (enmExpectedState), \
315 ("enmState=%d enmExpectedState=%d idCpu=%u\n", \
316 enmState, enmExpectedState, (pVCpu)->idCpu)); \
317 } while (0)
318#else
319# define VMCPU_ASSERT_STATE(pVCpu, enmExpectedState) do { } while (0)
320#endif
321/** Tests if the state means that the CPU is started. */
322#define VMCPUSTATE_IS_STARTED(enmState) ( (enmState) > VMCPUSTATE_STOPPED )
323/** Tests if the state means that the CPU is stopped. */
324#define VMCPUSTATE_IS_STOPPED(enmState) ( (enmState) == VMCPUSTATE_STOPPED )
325/** @} */
326
327
328/** The name of the raw-mode context VMM Core module. */
329#define VMMRC_MAIN_MODULE_NAME "VMMRC.rc"
330/** The name of the ring-0 context VMM Core module. */
331#define VMMR0_MAIN_MODULE_NAME "VMMR0.r0"
332
333/**
334 * Wrapper macro for avoiding too much \#ifdef VBOX_WITH_RAW_MODE.
335 */
336#ifdef VBOX_WITH_RAW_MODE
337# define VM_WHEN_RAW_MODE(a_WithExpr, a_WithoutExpr) a_WithExpr
338#else
339# define VM_WHEN_RAW_MODE(a_WithExpr, a_WithoutExpr) a_WithoutExpr
340#endif
341
342
343/** VM Forced Action Flags.
344 *
345 * Use the VM_FF_SET() and VM_FF_CLEAR() macros to change the force
346 * action mask of a VM.
347 *
348 * Available VM bits:
349 * 0, 1, 5, 6, 7, 13, 14, 15, 16, 17, 21, 22, 23, 24, 25, 26, 27, 28, 30
350 *
351 *
352 * Available VMCPU bits:
353 * 14, 15
354 *
355 * @todo If we run low on VMCPU, we may consider merging the SELM bits
356 *
357 * @{
358 */
359/** The virtual sync clock has been stopped, go to TM until it has been
360 * restarted... */
361#define VM_FF_TM_VIRTUAL_SYNC RT_BIT_32(2)
362/** PDM Queues are pending. */
363#define VM_FF_PDM_QUEUES RT_BIT_32(VM_FF_PDM_QUEUES_BIT)
364/** The bit number for VM_FF_PDM_QUEUES. */
365#define VM_FF_PDM_QUEUES_BIT 3
366/** PDM DMA transfers are pending. */
367#define VM_FF_PDM_DMA RT_BIT_32(VM_FF_PDM_DMA_BIT)
368/** The bit number for VM_FF_PDM_DMA. */
369#define VM_FF_PDM_DMA_BIT 4
370/** This action forces the VM to call DBGF so DBGF can service debugger
371 * requests in the emulation thread.
372 * This action flag stays asserted till DBGF clears it.*/
373#define VM_FF_DBGF RT_BIT_32(VM_FF_DBGF_BIT)
374/** The bit number for VM_FF_DBGF. */
375#define VM_FF_DBGF_BIT 8
376/** This action forces the VM to service pending requests from other
377 * thread or requests which must be executed in another context. */
378#define VM_FF_REQUEST RT_BIT_32(9)
379/** Check for VM state changes and take appropriate action. */
380#define VM_FF_CHECK_VM_STATE RT_BIT_32(VM_FF_CHECK_VM_STATE_BIT)
381/** The bit number for VM_FF_CHECK_VM_STATE. */
382#define VM_FF_CHECK_VM_STATE_BIT 10
383/** Reset the VM. (postponed) */
384#define VM_FF_RESET RT_BIT_32(VM_FF_RESET_BIT)
385/** The bit number for VM_FF_RESET. */
386#define VM_FF_RESET_BIT 11
387/** EMT rendezvous in VMM. */
388#define VM_FF_EMT_RENDEZVOUS RT_BIT_32(VM_FF_EMT_RENDEZVOUS_BIT)
389/** The bit number for VM_FF_EMT_RENDEZVOUS. */
390#define VM_FF_EMT_RENDEZVOUS_BIT 12
391
392/** PGM needs to allocate handy pages. */
393#define VM_FF_PGM_NEED_HANDY_PAGES RT_BIT_32(18)
394/** PGM is out of memory.
395 * Abandon all loops and code paths which can be resumed and get up to the EM
396 * loops. */
397#define VM_FF_PGM_NO_MEMORY RT_BIT_32(19)
398 /** PGM is about to perform a lightweight pool flush
399 * Guest SMP: all EMT threads should return to ring 3
400 */
401#define VM_FF_PGM_POOL_FLUSH_PENDING RT_BIT_32(20)
402/** REM needs to be informed about handler changes. */
403#define VM_FF_REM_HANDLER_NOTIFY RT_BIT_32(VM_FF_REM_HANDLER_NOTIFY_BIT)
404/** The bit number for VM_FF_REM_HANDLER_NOTIFY. */
405#define VM_FF_REM_HANDLER_NOTIFY_BIT 29
406/** Suspend the VM - debug only. */
407#define VM_FF_DEBUG_SUSPEND RT_BIT_32(31)
408
409
410/** This action forces the VM to check any pending interrupts on the APIC. */
411#define VMCPU_FF_INTERRUPT_APIC RT_BIT_32(0)
412/** This action forces the VM to check any pending interrups on the PIC. */
413#define VMCPU_FF_INTERRUPT_PIC RT_BIT_32(1)
414/** This action forces the VM to schedule and run pending timer (TM).
415 * @remarks Don't move - PATM compatibility. */
416#define VMCPU_FF_TIMER RT_BIT_32(2)
417/** This action forces the VM to check any pending NMIs. */
418#define VMCPU_FF_INTERRUPT_NMI_BIT 3
419#define VMCPU_FF_INTERRUPT_NMI RT_BIT_32(VMCPU_FF_INTERRUPT_NMI_BIT)
420/** This action forces the VM to check any pending SMIs. */
421#define VMCPU_FF_INTERRUPT_SMI_BIT 4
422#define VMCPU_FF_INTERRUPT_SMI RT_BIT_32(VMCPU_FF_INTERRUPT_SMI_BIT)
423/** PDM critical section unlocking is pending, process promptly upon return to R3. */
424#define VMCPU_FF_PDM_CRITSECT RT_BIT_32(5)
425/** Special EM internal force flag that is used by EMUnhaltAndWakeUp() to force
426 * the virtual CPU out of the next (/current) halted state. It is not processed
427 * nor cleared by emR3ForcedActions (similar to VMCPU_FF_BLOCK_NMIS), instead it
428 * is cleared the next time EM leaves the HALTED state. */
429#define VMCPU_FF_UNHALT RT_BIT_32(6)
430/** Pending IEM action (bit number). */
431#define VMCPU_FF_IEM_BIT 7
432/** Pending IEM action (mask). */
433#define VMCPU_FF_IEM RT_BIT_32(VMCPU_FF_IEM_BIT)
434/** Pending APIC action (bit number). */
435#define VMCPU_FF_UPDATE_APIC_BIT 8
436/** This action forces the VM to update APIC's asynchronously arrived
437 * interrupts as pending interrupts. */
438#define VMCPU_FF_UPDATE_APIC RT_BIT_32(VMCPU_FF_UPDATE_APIC_BIT)
439/** This action forces the VM to service pending requests from other
440 * thread or requests which must be executed in another context. */
441#define VMCPU_FF_REQUEST RT_BIT_32(9)
442/** Pending DBGF event (alternative to passing VINF_EM_DBG_EVENT around). */
443#define VMCPU_FF_DBGF RT_BIT_32(VMCPU_FF_DBGF_BIT)
444/** The bit number for VMCPU_FF_DBGF. */
445#define VMCPU_FF_DBGF_BIT 10
446/** Pending MTF (Monitor Trap Flag) event - Intel only. */
447#define VMCPU_FF_MTF RT_BIT_32(VMCPU_FF_MTF_BIT)
448/** The bit number for VMCPU_FF_MTF. */
449#define VMCPU_FF_MTF_BIT 11
450/** This action forces the VM to service any pending updates to CR3 (used only
451 * by HM). */
452#define VMCPU_FF_HM_UPDATE_CR3 RT_BIT_32(12)
453/** This action forces the VM to service any pending updates to PAE PDPEs (used
454 * only by HM). */
455#define VMCPU_FF_HM_UPDATE_PAE_PDPES RT_BIT_32(13)
456/** This action forces the VM to resync the page tables before going
457 * back to execute guest code. (GLOBAL FLUSH) */
458#define VMCPU_FF_PGM_SYNC_CR3 RT_BIT_32(16)
459/** Same as VM_FF_PGM_SYNC_CR3 except that global pages can be skipped.
460 * (NON-GLOBAL FLUSH) */
461#define VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL RT_BIT_32(17)
462/** Check for pending TLB shootdown actions (deprecated)
463 * Reserved for furture HM re-use if necessary / safe.
464 * Consumer: HM */
465#define VMCPU_FF_TLB_SHOOTDOWN_UNUSED RT_BIT_32(18)
466/** Check for pending TLB flush action.
467 * Consumer: HM
468 * @todo rename to VMCPU_FF_HM_TLB_FLUSH */
469#define VMCPU_FF_TLB_FLUSH RT_BIT_32(VMCPU_FF_TLB_FLUSH_BIT)
470/** The bit number for VMCPU_FF_TLB_FLUSH. */
471#define VMCPU_FF_TLB_FLUSH_BIT 19
472#ifdef VBOX_WITH_RAW_MODE
473/** Check the interrupt and trap gates */
474# define VMCPU_FF_TRPM_SYNC_IDT RT_BIT_32(20)
475/** Check Guest's TSS ring 0 stack */
476# define VMCPU_FF_SELM_SYNC_TSS RT_BIT_32(21)
477/** Check Guest's GDT table */
478# define VMCPU_FF_SELM_SYNC_GDT RT_BIT_32(22)
479/** Check Guest's LDT table */
480# define VMCPU_FF_SELM_SYNC_LDT RT_BIT_32(23)
481#endif /* VBOX_WITH_RAW_MODE */
482/** Inhibit interrupts pending. See EMGetInhibitInterruptsPC(). */
483#define VMCPU_FF_INHIBIT_INTERRUPTS RT_BIT_32(24)
484/** Block injection of non-maskable interrupts to the guest. */
485#define VMCPU_FF_BLOCK_NMIS RT_BIT_32(25)
486#ifdef VBOX_WITH_RAW_MODE
487/** CSAM needs to scan the page that's being executed */
488# define VMCPU_FF_CSAM_SCAN_PAGE RT_BIT_32(26)
489/** CSAM needs to do some homework. */
490# define VMCPU_FF_CSAM_PENDING_ACTION RT_BIT_32(27)
491#endif /* VBOX_WITH_RAW_MODE */
492/** Force return to Ring-3. */
493#define VMCPU_FF_TO_R3 RT_BIT_32(28)
494/** Force return to ring-3 to service pending I/O or MMIO write.
495 * This is a backup for mechanism VINF_IOM_R3_IOPORT_COMMIT_WRITE and
496 * VINF_IOM_R3_MMIO_COMMIT_WRITE, allowing VINF_EM_DBG_BREAKPOINT and similar
497 * status codes to be propagated at the same time without loss. */
498#define VMCPU_FF_IOM RT_BIT_32(29)
499#ifdef VBOX_WITH_RAW_MODE
500/** CPUM need to adjust CR0.TS/EM before executing raw-mode code again. */
501# define VMCPU_FF_CPUM RT_BIT_32(VMCPU_FF_CPUM_BIT)
502/** The bit number for VMCPU_FF_CPUM. */
503# define VMCPU_FF_CPUM_BIT 30
504#endif /* VBOX_WITH_RAW_MODE */
505/** Hardware virtualized nested-guest interrupt pending. */
506#define VMCPU_FF_INTERRUPT_NESTED_GUEST RT_BIT_32(31)
507
508/** Externally VM forced actions. Used to quit the idle/wait loop. */
509#define VM_FF_EXTERNAL_SUSPENDED_MASK ( VM_FF_CHECK_VM_STATE | VM_FF_DBGF | VM_FF_REQUEST | VM_FF_EMT_RENDEZVOUS )
510/** Externally VMCPU forced actions. Used to quit the idle/wait loop. */
511#define VMCPU_FF_EXTERNAL_SUSPENDED_MASK ( VMCPU_FF_REQUEST | VMCPU_FF_DBGF )
512
513/** Externally forced VM actions. Used to quit the idle/wait loop. */
514#define VM_FF_EXTERNAL_HALTED_MASK ( VM_FF_CHECK_VM_STATE | VM_FF_DBGF | VM_FF_REQUEST \
515 | VM_FF_PDM_QUEUES | VM_FF_PDM_DMA | VM_FF_EMT_RENDEZVOUS )
516/** Externally forced VMCPU actions. Used to quit the idle/wait loop. */
517#define VMCPU_FF_EXTERNAL_HALTED_MASK ( VMCPU_FF_UPDATE_APIC | VMCPU_FF_INTERRUPT_APIC | VMCPU_FF_INTERRUPT_PIC \
518 | VMCPU_FF_REQUEST | VMCPU_FF_INTERRUPT_NMI | VMCPU_FF_INTERRUPT_SMI \
519 | VMCPU_FF_UNHALT | VMCPU_FF_TIMER | VMCPU_FF_DBGF )
520
521/** High priority VM pre-execution actions. */
522#define VM_FF_HIGH_PRIORITY_PRE_MASK ( VM_FF_CHECK_VM_STATE | VM_FF_DBGF | VM_FF_TM_VIRTUAL_SYNC \
523 | VM_FF_DEBUG_SUSPEND | VM_FF_PGM_NEED_HANDY_PAGES | VM_FF_PGM_NO_MEMORY \
524 | VM_FF_EMT_RENDEZVOUS )
525/** High priority VMCPU pre-execution actions. */
526#define VMCPU_FF_HIGH_PRIORITY_PRE_MASK ( VMCPU_FF_TIMER | VMCPU_FF_INTERRUPT_APIC | VMCPU_FF_INTERRUPT_PIC \
527 | VMCPU_FF_UPDATE_APIC | VMCPU_FF_INHIBIT_INTERRUPTS | VMCPU_FF_DBGF \
528 | VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL \
529 | VM_WHEN_RAW_MODE( VMCPU_FF_SELM_SYNC_TSS | VMCPU_FF_TRPM_SYNC_IDT \
530 | VMCPU_FF_SELM_SYNC_GDT | VMCPU_FF_SELM_SYNC_LDT, 0 ) )
531
532/** High priority VM pre raw-mode execution mask. */
533#define VM_FF_HIGH_PRIORITY_PRE_RAW_MASK ( VM_FF_PGM_NEED_HANDY_PAGES | VM_FF_PGM_NO_MEMORY )
534/** High priority VMCPU pre raw-mode execution mask. */
535#define VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK ( VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL \
536 | VMCPU_FF_INHIBIT_INTERRUPTS \
537 | VM_WHEN_RAW_MODE( VMCPU_FF_SELM_SYNC_TSS | VMCPU_FF_TRPM_SYNC_IDT \
538 | VMCPU_FF_SELM_SYNC_GDT | VMCPU_FF_SELM_SYNC_LDT, 0) )
539
540/** High priority post-execution actions. */
541#define VM_FF_HIGH_PRIORITY_POST_MASK ( VM_FF_PGM_NO_MEMORY )
542/** High priority post-execution actions. */
543#define VMCPU_FF_HIGH_PRIORITY_POST_MASK ( VMCPU_FF_PDM_CRITSECT | VM_WHEN_RAW_MODE(VMCPU_FF_CSAM_PENDING_ACTION, 0) \
544 | VMCPU_FF_HM_UPDATE_CR3 | VMCPU_FF_HM_UPDATE_PAE_PDPES \
545 | VMCPU_FF_IEM | VMCPU_FF_IOM )
546
547/** Normal priority VM post-execution actions. */
548#define VM_FF_NORMAL_PRIORITY_POST_MASK ( VM_FF_CHECK_VM_STATE | VM_FF_DBGF | VM_FF_RESET \
549 | VM_FF_PGM_NO_MEMORY | VM_FF_EMT_RENDEZVOUS)
550/** Normal priority VMCPU post-execution actions. */
551#define VMCPU_FF_NORMAL_PRIORITY_POST_MASK ( VM_WHEN_RAW_MODE(VMCPU_FF_CSAM_SCAN_PAGE, 0) | VMCPU_FF_DBGF )
552
553/** Normal priority VM actions. */
554#define VM_FF_NORMAL_PRIORITY_MASK ( VM_FF_REQUEST | VM_FF_PDM_QUEUES | VM_FF_PDM_DMA \
555 | VM_FF_REM_HANDLER_NOTIFY | VM_FF_EMT_RENDEZVOUS)
556/** Normal priority VMCPU actions. */
557#define VMCPU_FF_NORMAL_PRIORITY_MASK ( VMCPU_FF_REQUEST )
558
559/** Flags to clear before resuming guest execution. */
560#define VMCPU_FF_RESUME_GUEST_MASK ( VMCPU_FF_TO_R3 )
561
562
563/** VM flags that cause the REP[|NE|E] STRINS loops to yield immediately. */
564#define VM_FF_HIGH_PRIORITY_POST_REPSTR_MASK ( VM_FF_TM_VIRTUAL_SYNC | VM_FF_PGM_NEED_HANDY_PAGES | VM_FF_PGM_NO_MEMORY \
565 | VM_FF_EMT_RENDEZVOUS | VM_FF_PGM_POOL_FLUSH_PENDING | VM_FF_RESET)
566/** VM flags that cause the REP[|NE|E] STRINS loops to yield. */
567#define VM_FF_YIELD_REPSTR_MASK ( VM_FF_HIGH_PRIORITY_POST_REPSTR_MASK \
568 | VM_FF_PDM_QUEUES | VM_FF_PDM_DMA | VM_FF_DBGF | VM_FF_DEBUG_SUSPEND )
569/** VMCPU flags that cause the REP[|NE|E] STRINS loops to yield immediately. */
570#ifdef IN_RING3
571# define VMCPU_FF_HIGH_PRIORITY_POST_REPSTR_MASK ( VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL | VMCPU_FF_DBGF )
572#else
573# define VMCPU_FF_HIGH_PRIORITY_POST_REPSTR_MASK ( VMCPU_FF_TO_R3 | VMCPU_FF_IEM | VMCPU_FF_IOM | VMCPU_FF_PGM_SYNC_CR3 \
574 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL | VMCPU_FF_DBGF )
575#endif
576/** VMCPU flags that cause the REP[|NE|E] STRINS loops to yield, interrupts
577 * enabled. */
578#define VMCPU_FF_YIELD_REPSTR_MASK ( VMCPU_FF_HIGH_PRIORITY_POST_REPSTR_MASK \
579 | VMCPU_FF_INTERRUPT_APIC | VMCPU_FF_UPDATE_APIC | VMCPU_FF_INTERRUPT_PIC \
580 | VMCPU_FF_INTERRUPT_NMI | VMCPU_FF_INTERRUPT_SMI | VMCPU_FF_PDM_CRITSECT \
581 | VMCPU_FF_TIMER | VMCPU_FF_REQUEST )
582/** VMCPU flags that cause the REP[|NE|E] STRINS loops to yield, interrupts
583 * disabled. */
584#define VMCPU_FF_YIELD_REPSTR_NOINT_MASK ( VMCPU_FF_YIELD_REPSTR_MASK \
585 & ~(VMCPU_FF_INTERRUPT_APIC | VMCPU_FF_UPDATE_APIC | VMCPU_FF_INTERRUPT_PIC) )
586
587/** VM Flags that cause the HM loops to go back to ring-3. */
588#define VM_FF_HM_TO_R3_MASK ( VM_FF_TM_VIRTUAL_SYNC | VM_FF_PGM_NEED_HANDY_PAGES | VM_FF_PGM_NO_MEMORY \
589 | VM_FF_PDM_QUEUES | VM_FF_EMT_RENDEZVOUS)
590/** VMCPU Flags that cause the HM loops to go back to ring-3. */
591#define VMCPU_FF_HM_TO_R3_MASK ( VMCPU_FF_TO_R3 | VMCPU_FF_TIMER | VMCPU_FF_PDM_CRITSECT \
592 | VMCPU_FF_IEM | VMCPU_FF_IOM)
593
594/** High priority ring-0 VM pre HM-mode execution mask. */
595#define VM_FF_HP_R0_PRE_HM_MASK (VM_FF_HM_TO_R3_MASK | VM_FF_REQUEST | VM_FF_PGM_POOL_FLUSH_PENDING | VM_FF_PDM_DMA)
596/** High priority ring-0 VMCPU pre HM-mode execution mask. */
597#define VMCPU_FF_HP_R0_PRE_HM_MASK ( VMCPU_FF_HM_TO_R3_MASK | VMCPU_FF_PGM_SYNC_CR3 \
598 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL | VMCPU_FF_REQUEST)
599/** High priority ring-0 VM pre HM-mode execution mask, single stepping. */
600#define VM_FF_HP_R0_PRE_HM_STEP_MASK (VM_FF_HP_R0_PRE_HM_MASK & ~( VM_FF_TM_VIRTUAL_SYNC | VM_FF_PDM_QUEUES \
601 | VM_FF_EMT_RENDEZVOUS | VM_FF_REQUEST \
602 | VM_FF_PDM_DMA) )
603/** High priority ring-0 VMCPU pre HM-mode execution mask, single stepping. */
604#define VMCPU_FF_HP_R0_PRE_HM_STEP_MASK (VMCPU_FF_HP_R0_PRE_HM_MASK & ~( VMCPU_FF_TO_R3 | VMCPU_FF_TIMER \
605 | VMCPU_FF_PDM_CRITSECT | VMCPU_FF_REQUEST) )
606
607/** All the forced VM flags. */
608#define VM_FF_ALL_MASK (UINT32_MAX)
609/** All the forced VMCPU flags. */
610#define VMCPU_FF_ALL_MASK (UINT32_MAX)
611
612/** All the forced VM flags except those related to raw-mode and hardware
613 * assisted execution. */
614#define VM_FF_ALL_REM_MASK (~(VM_FF_HIGH_PRIORITY_PRE_RAW_MASK) | VM_FF_PGM_NEED_HANDY_PAGES | VM_FF_PGM_NO_MEMORY)
615/** All the forced VMCPU flags except those related to raw-mode and hardware
616 * assisted execution. */
617#define VMCPU_FF_ALL_REM_MASK (~( VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK | VMCPU_FF_PDM_CRITSECT \
618 | VMCPU_FF_TLB_FLUSH | VM_WHEN_RAW_MODE(VMCPU_FF_CSAM_PENDING_ACTION, 0) ))
619/** @} */
620
621/** @def VM_FF_SET
622 * Sets a force action flag.
623 *
624 * @param pVM The cross context VM structure.
625 * @param fFlag The flag to set.
626 */
627#if 1
628# define VM_FF_SET(pVM, fFlag) ASMAtomicOrU32(&(pVM)->fGlobalForcedActions, (fFlag))
629#else
630# define VM_FF_SET(pVM, fFlag) \
631 do { ASMAtomicOrU32(&(pVM)->fGlobalForcedActions, (fFlag)); \
632 RTLogPrintf("VM_FF_SET : %08x %s - %s(%d) %s\n", (pVM)->fGlobalForcedActions, #fFlag, __FILE__, __LINE__, __FUNCTION__); \
633 } while (0)
634#endif
635
636/** @def VMCPU_FF_SET
637 * Sets a force action flag for the given VCPU.
638 *
639 * @param pVCpu The cross context virtual CPU structure.
640 * @param fFlag The flag to set.
641 */
642#define VMCPU_FF_SET(pVCpu, fFlag) ASMAtomicOrU32(&(pVCpu)->fLocalForcedActions, (fFlag))
643
644/** @def VM_FF_CLEAR
645 * Clears a single force action flag.
646 *
647 * @param pVM The cross context VM structure.
648 * @param fFlag The flag to clear.
649 */
650#if 1
651# if !defined(VBOX_STRICT) || !defined(RT_COMPILER_SUPPORTS_LAMBDA)
652# define VM_FF_CLEAR(pVM, fFlag) ASMAtomicAndU32(&(pVM)->fGlobalForcedActions, ~(fFlag))
653# else
654# define VM_FF_CLEAR(pVM, fFlag) \
655 ([](PVM a_pVM) -> void \
656 { \
657 AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
658 ASMAtomicAndU32(&a_pVM->fGlobalForcedActions, ~(fFlag)); \
659 }(pVM))
660# endif
661#else
662# define VM_FF_CLEAR(pVM, fFlag) \
663 do { ASMAtomicAndU32(&(pVM)->fGlobalForcedActions, ~(fFlag)); \
664 RTLogPrintf("VM_FF_CLEAR: %08x %s - %s(%d) %s\n", (pVM)->fGlobalForcedActions, #fFlag, __FILE__, __LINE__, __FUNCTION__); \
665 } while (0)
666#endif
667
668/** @def VMCPU_FF_CLEAR
669 * Clears a single force action flag for the given VCPU.
670 *
671 * @param pVCpu The cross context virtual CPU structure.
672 * @param fFlag The flag to clear.
673 */
674#if !defined(VBOX_STRICT) || !defined(RT_COMPILER_SUPPORTS_LAMBDA)
675# define VMCPU_FF_CLEAR(pVCpu, fFlag) ASMAtomicAndU32(&(pVCpu)->fLocalForcedActions, ~(fFlag))
676#else
677# define VMCPU_FF_CLEAR(pVCpu, fFlag) \
678 ([](PVMCPU a_pVCpu) -> void \
679 { \
680 AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
681 ASMAtomicAndU32(&a_pVCpu->fLocalForcedActions, ~(fFlag)); \
682 }(pVCpu))
683#endif
684
685/** @def VMCPU_FF_CLEAR_MASK
686 * Clears two or more force action flags for the given VCPU.
687 *
688 * @param pVCpu The cross context virtual CPU structure.
689 * @param fFlags The flags to clear.
690 */
691#define VMCPU_FF_CLEAR_MASK(pVCpu, fFlags) ASMAtomicAndU32(&(pVCpu)->fLocalForcedActions, ~(fFlags))
692
693/** @def VM_FF_IS_SET
694 * Checks if a force action flag is set.
695 *
696 * @param pVM The cross context VM structure.
697 * @param fFlag The flag to check.
698 */
699#define VM_FF_IS_SET(pVM, fFlag) (((pVM)->fGlobalForcedActions & (fFlag)) == (fFlag))
700
701
702/** @def VMCPU_FF_IS_SET
703 * Checks if a force action flag is set for the given VCPU.
704 *
705 * @param pVCpu The cross context virtual CPU structure.
706 * @param fFlag The flag to check.
707 */
708#if !defined(VBOX_STRICT) || !defined(RT_COMPILER_SUPPORTS_LAMBDA)
709# define VMCPU_FF_IS_SET(pVCpu, fFlag) (((pVCpu)->fLocalForcedActions & (fFlag)) == (fFlag))
710#else
711# define VMCPU_FF_IS_SET(pVCpu, fFlag) \
712 ([](PVMCPU a_pVCpu) -> bool \
713 { \
714 AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
715 return (a_pVCpu->fLocalForcedActions & (fFlag)) == (fFlag); \
716 }(pVCpu))
717#endif
718
719/** @def VM_FF_IS_PENDING
720 * Checks if one or more force action in the specified set is pending.
721 *
722 * @param pVM The cross context VM structure.
723 * @param fFlags The flags to check for.
724 */
725#define VM_FF_IS_PENDING(pVM, fFlags) RT_BOOL((pVM)->fGlobalForcedActions & (fFlags))
726
727/** @def VMCPU_FF_IS_PENDING
728 * Checks if one or more force action in the specified set is pending for the given VCPU.
729 *
730 * @param pVCpu The cross context virtual CPU structure.
731 * @param fFlags The flags to check for.
732 */
733#define VMCPU_FF_IS_PENDING(pVCpu, fFlags) RT_BOOL((pVCpu)->fLocalForcedActions & (fFlags))
734
735/** @def VM_FF_TEST_AND_CLEAR
736 * Checks if one (!) force action in the specified set is pending and clears it atomically
737 *
738 * @returns true if the bit was set.
739 * @returns false if the bit was clear.
740 * @param pVM The cross context VM structure.
741 * @param iBit Bit position to check and clear
742 */
743#define VM_FF_TEST_AND_CLEAR(pVM, iBit) (ASMAtomicBitTestAndClear(&(pVM)->fGlobalForcedActions, iBit##_BIT))
744
745/** @def VMCPU_FF_TEST_AND_CLEAR
746 * Checks if one (!) force action in the specified set is pending and clears it atomically
747 *
748 * @returns true if the bit was set.
749 * @returns false if the bit was clear.
750 * @param pVCpu The cross context virtual CPU structure.
751 * @param iBit Bit position to check and clear
752 */
753#define VMCPU_FF_TEST_AND_CLEAR(pVCpu, iBit) (ASMAtomicBitTestAndClear(&(pVCpu)->fLocalForcedActions, iBit##_BIT))
754
755/** @def VM_FF_IS_PENDING_EXCEPT
756 * Checks if one or more force action in the specified set is pending while one
757 * or more other ones are not.
758 *
759 * @param pVM The cross context VM structure.
760 * @param fFlags The flags to check for.
761 * @param fExcpt The flags that should not be set.
762 */
763#define VM_FF_IS_PENDING_EXCEPT(pVM, fFlags, fExcpt) ( ((pVM)->fGlobalForcedActions & (fFlags)) && !((pVM)->fGlobalForcedActions & (fExcpt)) )
764
765/** @def VM_IS_EMT
766 * Checks if the current thread is the emulation thread (EMT).
767 *
768 * @remark The ring-0 variation will need attention if we expand the ring-0
769 * code to let threads other than EMT mess around with the VM.
770 */
771#ifdef IN_RC
772# define VM_IS_EMT(pVM) true
773#else
774# define VM_IS_EMT(pVM) (VMMGetCpu(pVM) != NULL)
775#endif
776
777/** @def VMCPU_IS_EMT
778 * Checks if the current thread is the emulation thread (EMT) for the specified
779 * virtual CPU.
780 */
781#ifdef IN_RC
782# define VMCPU_IS_EMT(pVCpu) true
783#else
784# define VMCPU_IS_EMT(pVCpu) ((pVCpu) && ((pVCpu) == VMMGetCpu((pVCpu)->CTX_SUFF(pVM))))
785#endif
786
787/** @def VM_ASSERT_EMT
788 * Asserts that the current thread IS the emulation thread (EMT).
789 */
790#ifdef IN_RC
791# define VM_ASSERT_EMT(pVM) Assert(VM_IS_EMT(pVM))
792#elif defined(IN_RING0)
793# define VM_ASSERT_EMT(pVM) Assert(VM_IS_EMT(pVM))
794#else
795# define VM_ASSERT_EMT(pVM) \
796 AssertMsg(VM_IS_EMT(pVM), \
797 ("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd\n", RTThreadNativeSelf(), VMR3GetVMCPUNativeThread(pVM)))
798#endif
799
800/** @def VMCPU_ASSERT_EMT
801 * Asserts that the current thread IS the emulation thread (EMT) of the
802 * specified virtual CPU.
803 */
804#ifdef IN_RC
805# define VMCPU_ASSERT_EMT(pVCpu) Assert(VMCPU_IS_EMT(pVCpu))
806#elif defined(IN_RING0)
807# define VMCPU_ASSERT_EMT(pVCpu) AssertMsg(VMCPU_IS_EMT(pVCpu), \
808 ("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd idCpu=%u\n", \
809 RTThreadNativeSelf(), (pVCpu) ? (pVCpu)->hNativeThreadR0 : 0, \
810 (pVCpu) ? (pVCpu)->idCpu : 0))
811#else
812# define VMCPU_ASSERT_EMT(pVCpu) AssertMsg(VMCPU_IS_EMT(pVCpu), \
813 ("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd idCpu=%#x\n", \
814 RTThreadNativeSelf(), (pVCpu)->hNativeThread, (pVCpu)->idCpu))
815#endif
816
817/** @def VM_ASSERT_EMT_RETURN
818 * Asserts that the current thread IS the emulation thread (EMT) and returns if it isn't.
819 */
820#ifdef IN_RC
821# define VM_ASSERT_EMT_RETURN(pVM, rc) AssertReturn(VM_IS_EMT(pVM), (rc))
822#elif defined(IN_RING0)
823# define VM_ASSERT_EMT_RETURN(pVM, rc) AssertReturn(VM_IS_EMT(pVM), (rc))
824#else
825# define VM_ASSERT_EMT_RETURN(pVM, rc) \
826 AssertMsgReturn(VM_IS_EMT(pVM), \
827 ("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd\n", RTThreadNativeSelf(), VMR3GetVMCPUNativeThread(pVM)), \
828 (rc))
829#endif
830
831/** @def VMCPU_ASSERT_EMT_RETURN
832 * Asserts that the current thread IS the emulation thread (EMT) and returns if it isn't.
833 */
834#ifdef IN_RC
835# define VMCPU_ASSERT_EMT_RETURN(pVCpu, rc) AssertReturn(VMCPU_IS_EMT(pVCpu), (rc))
836#elif defined(IN_RING0)
837# define VMCPU_ASSERT_EMT_RETURN(pVCpu, rc) AssertReturn(VMCPU_IS_EMT(pVCpu), (rc))
838#else
839# define VMCPU_ASSERT_EMT_RETURN(pVCpu, rc) \
840 AssertMsgReturn(VMCPU_IS_EMT(pVCpu), \
841 ("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd idCpu=%#x\n", \
842 RTThreadNativeSelf(), (pVCpu)->hNativeThread, (pVCpu)->idCpu), \
843 (rc))
844#endif
845
846/** @def VMCPU_ASSERT_EMT_OR_GURU
847 * Asserts that the current thread IS the emulation thread (EMT) of the
848 * specified virtual CPU.
849 */
850#if defined(IN_RC) || defined(IN_RING0)
851# define VMCPU_ASSERT_EMT_OR_GURU(pVCpu) Assert( VMCPU_IS_EMT(pVCpu) \
852 || pVCpu->CTX_SUFF(pVM)->enmVMState == VMSTATE_GURU_MEDITATION \
853 || pVCpu->CTX_SUFF(pVM)->enmVMState == VMSTATE_GURU_MEDITATION_LS )
854#else
855# define VMCPU_ASSERT_EMT_OR_GURU(pVCpu) \
856 AssertMsg( VMCPU_IS_EMT(pVCpu) \
857 || pVCpu->CTX_SUFF(pVM)->enmVMState == VMSTATE_GURU_MEDITATION \
858 || pVCpu->CTX_SUFF(pVM)->enmVMState == VMSTATE_GURU_MEDITATION_LS, \
859 ("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd idCpu=%#x\n", \
860 RTThreadNativeSelf(), (pVCpu)->hNativeThread, (pVCpu)->idCpu))
861#endif
862
863/** @def VMCPU_ASSERT_EMT_OR_NOT_RUNNING
864 * Asserts that the current thread IS the emulation thread (EMT) of the
865 * specified virtual CPU or the VM is not running.
866 */
867#if defined(IN_RC) || defined(IN_RING0)
868# define VMCPU_ASSERT_EMT_OR_NOT_RUNNING(pVCpu) \
869 Assert( VMCPU_IS_EMT(pVCpu) \
870 || !VM_IS_RUNNING_FOR_ASSERTIONS_ONLY((pVCpu)->CTX_SUFF(pVM)) )
871#else
872# define VMCPU_ASSERT_EMT_OR_NOT_RUNNING(pVCpu) \
873 AssertMsg( VMCPU_IS_EMT(pVCpu) \
874 || !VM_IS_RUNNING_FOR_ASSERTIONS_ONLY((pVCpu)->CTX_SUFF(pVM)), \
875 ("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd idCpu=%#x\n", \
876 RTThreadNativeSelf(), (pVCpu)->hNativeThread, (pVCpu)->idCpu))
877#endif
878
879/** @def VMSTATE_IS_RUNNING
880 * Checks if the given state indicates a running VM.
881 */
882#define VMSTATE_IS_RUNNING(a_enmVMState) \
883 ( (enmVMState) == VMSTATE_RUNNING \
884 || (enmVMState) == VMSTATE_RUNNING_LS \
885 || (enmVMState) == VMSTATE_RUNNING_FT )
886
887/** @def VM_IS_RUNNING_FOR_ASSERTIONS_ONLY
888 * Checks if the VM is running.
889 * @note This is only for pure debug assertions. No AssertReturn or similar!
890 * @sa VMSTATE_IS_RUNNING
891 */
892#define VM_IS_RUNNING_FOR_ASSERTIONS_ONLY(pVM) \
893 ( (pVM)->enmVMState == VMSTATE_RUNNING \
894 || (pVM)->enmVMState == VMSTATE_RUNNING_LS \
895 || (pVM)->enmVMState == VMSTATE_RUNNING_FT )
896
897/** @def VM_ASSERT_IS_NOT_RUNNING
898 * Asserts that the VM is not running.
899 */
900#if defined(IN_RC) || defined(IN_RING0)
901#define VM_ASSERT_IS_NOT_RUNNING(pVM) Assert(!VM_IS_RUNNING_FOR_ASSERTIONS_ONLY(pVM))
902#else
903#define VM_ASSERT_IS_NOT_RUNNING(pVM) AssertMsg(!VM_IS_RUNNING_FOR_ASSERTIONS_ONLY(pVM), \
904 ("VM is running. enmVMState=%d\n", (pVM)->enmVMState))
905#endif
906
907/** @def VM_ASSERT_EMT0
908 * Asserts that the current thread IS emulation thread \#0 (EMT0).
909 */
910#define VM_ASSERT_EMT0(pVM) VMCPU_ASSERT_EMT(&(pVM)->aCpus[0])
911
912/** @def VM_ASSERT_EMT0_RETURN
913 * Asserts that the current thread IS emulation thread \#0 (EMT0) and returns if
914 * it isn't.
915 */
916#define VM_ASSERT_EMT0_RETURN(pVM, rc) VMCPU_ASSERT_EMT_RETURN(&(pVM)->aCpus[0], (rc))
917
918
919/**
920 * Asserts that the current thread is NOT the emulation thread.
921 */
922#define VM_ASSERT_OTHER_THREAD(pVM) \
923 AssertMsg(!VM_IS_EMT(pVM), ("Not other thread!!\n"))
924
925
926/** @def VM_ASSERT_STATE
927 * Asserts a certain VM state.
928 */
929#define VM_ASSERT_STATE(pVM, _enmState) \
930 AssertMsg((pVM)->enmVMState == (_enmState), \
931 ("state %s, expected %s\n", VMGetStateName((pVM)->enmVMState), VMGetStateName(_enmState)))
932
933/** @def VM_ASSERT_STATE_RETURN
934 * Asserts a certain VM state and returns if it doesn't match.
935 */
936#define VM_ASSERT_STATE_RETURN(pVM, _enmState, rc) \
937 AssertMsgReturn((pVM)->enmVMState == (_enmState), \
938 ("state %s, expected %s\n", VMGetStateName((pVM)->enmVMState), VMGetStateName(_enmState)), \
939 (rc))
940
941/** @def VM_IS_VALID_EXT
942 * Asserts a the VM handle is valid for external access, i.e. not being destroy
943 * or terminated. */
944#define VM_IS_VALID_EXT(pVM) \
945 ( RT_VALID_ALIGNED_PTR(pVM, PAGE_SIZE) \
946 && ( (unsigned)(pVM)->enmVMState < (unsigned)VMSTATE_DESTROYING \
947 || ( (unsigned)(pVM)->enmVMState == (unsigned)VMSTATE_DESTROYING \
948 && VM_IS_EMT(pVM))) )
949
950/** @def VM_ASSERT_VALID_EXT_RETURN
951 * Asserts a the VM handle is valid for external access, i.e. not being
952 * destroy or terminated.
953 */
954#define VM_ASSERT_VALID_EXT_RETURN(pVM, rc) \
955 AssertMsgReturn(VM_IS_VALID_EXT(pVM), \
956 ("pVM=%p state %s\n", (pVM), RT_VALID_ALIGNED_PTR(pVM, PAGE_SIZE) \
957 ? VMGetStateName(pVM->enmVMState) : ""), \
958 (rc))
959
960/** @def VMCPU_ASSERT_VALID_EXT_RETURN
961 * Asserts a the VMCPU handle is valid for external access, i.e. not being
962 * destroy or terminated.
963 */
964#define VMCPU_ASSERT_VALID_EXT_RETURN(pVCpu, rc) \
965 AssertMsgReturn( RT_VALID_ALIGNED_PTR(pVCpu, 64) \
966 && RT_VALID_ALIGNED_PTR((pVCpu)->CTX_SUFF(pVM), PAGE_SIZE) \
967 && (unsigned)(pVCpu)->CTX_SUFF(pVM)->enmVMState < (unsigned)VMSTATE_DESTROYING, \
968 ("pVCpu=%p pVM=%p state %s\n", (pVCpu), RT_VALID_ALIGNED_PTR(pVCpu, 64) ? (pVCpu)->CTX_SUFF(pVM) : NULL, \
969 RT_VALID_ALIGNED_PTR(pVCpu, 64) && RT_VALID_ALIGNED_PTR((pVCpu)->CTX_SUFF(pVM), PAGE_SIZE) \
970 ? VMGetStateName((pVCpu)->pVMR3->enmVMState) : ""), \
971 (rc))
972
973#endif /* !VBOX_FOR_DTRACE_LIB */
974
975
976/**
977 * Helper that HM and NEM uses for safely modifying VM::bMainExecutionEngine.
978 *
979 * ONLY HM and NEM MAY USE THIS!
980 *
981 * @param a_pVM The cross context VM structure.
982 * @param a_bValue The new value.
983 * @internal
984 */
985#define VM_SET_MAIN_EXECUTION_ENGINE(a_pVM, a_bValue) \
986 do { \
987 *const_cast<uint8_t *>(&(a_pVM)->bMainExecutionEngine) = (a_bValue); \
988 ASMCompilerBarrier(); /* just to be on the safe side */ \
989 } while (0)
990
991/**
992 * Checks whether raw-mode is used.
993 *
994 * @retval true if either is used.
995 * @retval false if software virtualization (raw-mode) is used.
996 *
997 * @param a_pVM The cross context VM structure.
998 * @sa VM_IS_HM_OR_NEM_ENABLED, VM_IS_HM_ENABLED, VM_IS_NEM_ENABLED.
999 * @internal
1000 */
1001#ifdef VBOX_WITH_RAW_MODE
1002# define VM_IS_RAW_MODE_ENABLED(a_pVM) ((a_pVM)->bMainExecutionEngine == VM_EXEC_ENGINE_RAW_MODE)
1003#else
1004# define VM_IS_RAW_MODE_ENABLED(a_pVM) (false)
1005#endif
1006
1007/**
1008 * Checks whether HM (VT-x/AMD-V) or NEM is being used by this VM.
1009 *
1010 * @retval true if either is used.
1011 * @retval false if software virtualization (raw-mode) is used.
1012 *
1013 * @param a_pVM The cross context VM structure.
1014 * @sa VM_IS_RAW_MODE_ENABLED, VM_IS_HM_ENABLED, VM_IS_NEM_ENABLED.
1015 * @internal
1016 */
1017#define VM_IS_HM_OR_NEM_ENABLED(a_pVM) ((a_pVM)->bMainExecutionEngine != VM_EXEC_ENGINE_RAW_MODE)
1018
1019/**
1020 * Checks whether HM is being used by this VM.
1021 *
1022 * @retval true if HM (VT-x/AMD-v) is used.
1023 * @retval false if not.
1024 *
1025 * @param a_pVM The cross context VM structure.
1026 * @sa VM_IS_NEM_ENABLED, VM_IS_RAW_MODE_ENABLED, VM_IS_HM_OR_NEM_ENABLED.
1027 * @internal
1028 */
1029#define VM_IS_HM_ENABLED(a_pVM) ((a_pVM)->bMainExecutionEngine == VM_EXEC_ENGINE_HW_VIRT)
1030
1031/**
1032 * Checks whether NEM is being used by this VM.
1033 *
1034 * @retval true if a native hypervisor API is used.
1035 * @retval false if not.
1036 *
1037 * @param a_pVM The cross context VM structure.
1038 * @sa VM_IS_HM_ENABLED, VM_IS_RAW_MODE_ENABLED, VM_IS_HM_OR_NEM_ENABLED.
1039 * @internal
1040 */
1041#define VM_IS_NEM_ENABLED(a_pVM) ((a_pVM)->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API)
1042
1043
1044/**
1045 * The cross context VM structure.
1046 *
1047 * It contains all the VM data which have to be available in all contexts.
1048 * Even if it contains all the data the idea is to use APIs not to modify all
1049 * the members all around the place. Therefore we make use of unions to hide
1050 * everything which isn't local to the current source module. This means we'll
1051 * have to pay a little bit of attention when adding new members to structures
1052 * in the unions and make sure to keep the padding sizes up to date.
1053 *
1054 * Run 'kmk run-struct-tests' (from src/VBox/VMM if you like) after updating!
1055 */
1056typedef struct VM
1057{
1058 /** The state of the VM.
1059 * This field is read only to everyone except the VM and EM. */
1060 VMSTATE volatile enmVMState;
1061 /** Forced action flags.
1062 * See the VM_FF_* \#defines. Updated atomically.
1063 */
1064 volatile uint32_t fGlobalForcedActions;
1065 /** Pointer to the array of page descriptors for the VM structure allocation. */
1066 R3PTRTYPE(PSUPPAGE) paVMPagesR3;
1067 /** Session handle. For use when calling SUPR0 APIs. */
1068 PSUPDRVSESSION pSession;
1069 /** Pointer to the ring-3 VM structure. */
1070 PUVM pUVM;
1071 /** Ring-3 Host Context VM Pointer. */
1072 R3PTRTYPE(struct VM *) pVMR3;
1073 /** Ring-0 Host Context VM Pointer. */
1074 R0PTRTYPE(struct VM *) pVMR0;
1075 /** Raw-mode Context VM Pointer. */
1076 RCPTRTYPE(struct VM *) pVMRC;
1077
1078 /** The GVM VM handle. Only the GVM should modify this field. */
1079 uint32_t hSelf;
1080 /** Number of virtual CPUs. */
1081 uint32_t cCpus;
1082 /** CPU excution cap (1-100) */
1083 uint32_t uCpuExecutionCap;
1084
1085 /** Size of the VM structure including the VMCPU array. */
1086 uint32_t cbSelf;
1087
1088 /** Offset to the VMCPU array starting from beginning of this structure. */
1089 uint32_t offVMCPU;
1090
1091 /**
1092 * VMMSwitcher assembly entry point returning to host context.
1093 *
1094 * Depending on how the host handles the rc status given in @a eax, this may
1095 * return and let the caller resume whatever it was doing prior to the call.
1096 *
1097 *
1098 * @param eax The return code, register.
1099 * @remark Assume interrupts disabled.
1100 * @remark This method pointer lives here because TRPM needs it.
1101 */
1102 RTRCPTR pfnVMMRCToHostAsm/*(int32_t eax)*/;
1103
1104 /**
1105 * VMMSwitcher assembly entry point returning to host context without saving the
1106 * raw-mode context (hyper) registers.
1107 *
1108 * Unlike pfnVMMRC2HCAsm, this will not return to the caller. Instead it
1109 * expects the caller to save a RC context in CPUM where one might return if the
1110 * return code indicate that this is possible.
1111 *
1112 * This method pointer lives here because TRPM needs it.
1113 *
1114 * @param eax The return code, register.
1115 * @remark Assume interrupts disabled.
1116 * @remark This method pointer lives here because TRPM needs it.
1117 */
1118 RTRCPTR pfnVMMRCToHostAsmNoReturn/*(int32_t eax)*/;
1119
1120 /** @name Various items that are frequently accessed.
1121 * @{ */
1122 /** The main execution engine, VM_EXEC_ENGINE_XXX.
1123 * This is set early during vmR3InitRing3 by HM or NEM. */
1124 uint8_t const bMainExecutionEngine;
1125
1126 /** Whether to recompile user mode code or run it raw/hm/nem.
1127 * In non-raw-mode both fRecompileUser and fRecompileSupervisor must be set
1128 * to recompiler stuff. */
1129 bool fRecompileUser;
1130 /** Whether to recompile supervisor mode code or run it raw/hm/nem.
1131 * In non-raw-mode both fRecompileUser and fRecompileSupervisor must be set
1132 * to recompiler stuff. */
1133 bool fRecompileSupervisor;
1134 /** Whether raw mode supports ring-1 code or not.
1135 * This will be cleared when not in raw-mode. */
1136 bool fRawRing1Enabled;
1137 /** PATM enabled flag.
1138 * This is placed here for performance reasons.
1139 * This will be cleared when not in raw-mode. */
1140 bool fPATMEnabled;
1141 /** CSAM enabled flag.
1142 * This is placed here for performance reasons.
1143 * This will be cleared when not in raw-mode. */
1144 bool fCSAMEnabled;
1145
1146 /** Hardware VM support is available and enabled.
1147 * Determined very early during init.
1148 * This is placed here for performance reasons.
1149 * @todo obsoleted by bMainExecutionEngine, eliminate. */
1150 bool fHMEnabled;
1151 /** Hardware VM support requires a minimal raw-mode context.
1152 * This is never set on 64-bit hosts, only 32-bit hosts requires it. */
1153 bool fHMNeedRawModeCtx;
1154
1155 /** Set when this VM is the master FT node.
1156 * @todo This doesn't need to be here, FTM should store it in it's own
1157 * structures instead. */
1158 bool fFaultTolerantMaster;
1159 /** Large page enabled flag.
1160 * @todo This doesn't need to be here, PGM should store it in it's own
1161 * structures instead. */
1162 bool fUseLargePages;
1163 /** @} */
1164
1165 /** Alignment padding. */
1166 uint8_t uPadding1[2];
1167
1168 /** @name Debugging
1169 * @{ */
1170 /** Raw-mode Context VM Pointer. */
1171 RCPTRTYPE(RTTRACEBUF) hTraceBufRC;
1172 /** Ring-3 Host Context VM Pointer. */
1173 R3PTRTYPE(RTTRACEBUF) hTraceBufR3;
1174 /** Ring-0 Host Context VM Pointer. */
1175 R0PTRTYPE(RTTRACEBUF) hTraceBufR0;
1176 /** @} */
1177
1178#if HC_ARCH_BITS == 32
1179 /** Alignment padding. */
1180 uint32_t uPadding2;
1181#endif
1182
1183 /** @name Switcher statistics (remove)
1184 * @{ */
1185 /** Profiling the total time from Qemu to GC. */
1186 STAMPROFILEADV StatTotalQemuToGC;
1187 /** Profiling the total time from GC to Qemu. */
1188 STAMPROFILEADV StatTotalGCToQemu;
1189 /** Profiling the total time spent in GC. */
1190 STAMPROFILEADV StatTotalInGC;
1191 /** Profiling the total time spent not in Qemu. */
1192 STAMPROFILEADV StatTotalInQemu;
1193 /** Profiling the VMMSwitcher code for going to GC. */
1194 STAMPROFILEADV StatSwitcherToGC;
1195 /** Profiling the VMMSwitcher code for going to HC. */
1196 STAMPROFILEADV StatSwitcherToHC;
1197 STAMPROFILEADV StatSwitcherSaveRegs;
1198 STAMPROFILEADV StatSwitcherSysEnter;
1199 STAMPROFILEADV StatSwitcherDebug;
1200 STAMPROFILEADV StatSwitcherCR0;
1201 STAMPROFILEADV StatSwitcherCR4;
1202 STAMPROFILEADV StatSwitcherJmpCR3;
1203 STAMPROFILEADV StatSwitcherRstrRegs;
1204 STAMPROFILEADV StatSwitcherLgdt;
1205 STAMPROFILEADV StatSwitcherLidt;
1206 STAMPROFILEADV StatSwitcherLldt;
1207 STAMPROFILEADV StatSwitcherTSS;
1208 /** @} */
1209
1210 /** Padding - the unions must be aligned on a 64 bytes boundary and the unions
1211 * must start at the same offset on both 64-bit and 32-bit hosts. */
1212 uint8_t abAlignment3[(HC_ARCH_BITS == 32 ? 24 : 0) + 40];
1213
1214 /** CPUM part. */
1215 union
1216 {
1217#ifdef ___CPUMInternal_h
1218 struct CPUM s;
1219#endif
1220#ifdef ___VBox_vmm_cpum_h
1221 /** Read only info exposed about the host and guest CPUs. */
1222 struct
1223 {
1224 /** Padding for hidden fields. */
1225 uint8_t abHidden0[64];
1226 /** Host CPU feature information. */
1227 CPUMFEATURES HostFeatures;
1228 /** Guest CPU feature information. */
1229 CPUMFEATURES GuestFeatures;
1230 } const ro;
1231#endif
1232 uint8_t padding[1536]; /* multiple of 64 */
1233 } cpum;
1234
1235 /** VMM part. */
1236 union
1237 {
1238#ifdef ___VMMInternal_h
1239 struct VMM s;
1240#endif
1241 uint8_t padding[1600]; /* multiple of 64 */
1242 } vmm;
1243
1244 /** PGM part. */
1245 union
1246 {
1247#ifdef ___PGMInternal_h
1248 struct PGM s;
1249#endif
1250 uint8_t padding[4096*2+6080]; /* multiple of 64 */
1251 } pgm;
1252
1253 /** HM part. */
1254 union
1255 {
1256#ifdef ___HMInternal_h
1257 struct HM s;
1258#endif
1259 uint8_t padding[5440]; /* multiple of 64 */
1260 } hm;
1261
1262 /** TRPM part. */
1263 union
1264 {
1265#ifdef ___TRPMInternal_h
1266 struct TRPM s;
1267#endif
1268 uint8_t padding[5248]; /* multiple of 64 */
1269 } trpm;
1270
1271 /** SELM part. */
1272 union
1273 {
1274#ifdef ___SELMInternal_h
1275 struct SELM s;
1276#endif
1277 uint8_t padding[768]; /* multiple of 64 */
1278 } selm;
1279
1280 /** MM part. */
1281 union
1282 {
1283#ifdef ___MMInternal_h
1284 struct MM s;
1285#endif
1286 uint8_t padding[192]; /* multiple of 64 */
1287 } mm;
1288
1289 /** PDM part. */
1290 union
1291 {
1292#ifdef ___PDMInternal_h
1293 struct PDM s;
1294#endif
1295 uint8_t padding[1920]; /* multiple of 64 */
1296 } pdm;
1297
1298 /** IOM part. */
1299 union
1300 {
1301#ifdef ___IOMInternal_h
1302 struct IOM s;
1303#endif
1304 uint8_t padding[896]; /* multiple of 64 */
1305 } iom;
1306
1307 /** EM part. */
1308 union
1309 {
1310#ifdef ___EMInternal_h
1311 struct EM s;
1312#endif
1313 uint8_t padding[256]; /* multiple of 64 */
1314 } em;
1315
1316 /** NEM part. */
1317 union
1318 {
1319#ifdef ___NEMInternal_h
1320 struct NEM s;
1321#endif
1322 uint8_t padding[128]; /* multiple of 64 */
1323 } nem;
1324
1325 /** TM part. */
1326 union
1327 {
1328#ifdef ___TMInternal_h
1329 struct TM s;
1330#endif
1331 uint8_t padding[2496]; /* multiple of 64 */
1332 } tm;
1333
1334 /** DBGF part. */
1335 union
1336 {
1337#ifdef ___DBGFInternal_h
1338 struct DBGF s;
1339#endif
1340#ifdef ___VBox_vmm_dbgf_h
1341 /** Read only info exposed about interrupt breakpoints and selected events. */
1342 struct
1343 {
1344 /** Bitmap of enabled hardware interrupt breakpoints. */
1345 uint32_t bmHardIntBreakpoints[256 / 32];
1346 /** Bitmap of enabled software interrupt breakpoints. */
1347 uint32_t bmSoftIntBreakpoints[256 / 32];
1348 /** Bitmap of selected events.
1349 * This includes non-selectable events too for simplicity, we maintain the
1350 * state for some of these, as it may come in handy. */
1351 uint64_t bmSelectedEvents[(DBGFEVENT_END + 63) / 64];
1352 /** Enabled hardware interrupt breakpoints. */
1353 uint32_t cHardIntBreakpoints;
1354 /** Enabled software interrupt breakpoints. */
1355 uint32_t cSoftIntBreakpoints;
1356 /** The number of selected events. */
1357 uint32_t cSelectedEvents;
1358 /** The number of enabled hardware breakpoints. */
1359 uint8_t cEnabledHwBreakpoints;
1360 /** The number of enabled hardware I/O breakpoints. */
1361 uint8_t cEnabledHwIoBreakpoints;
1362 /** The number of enabled INT3 breakpoints. */
1363 uint8_t cEnabledInt3Breakpoints;
1364 uint8_t abPadding[1]; /**< Unused padding space up for grabs. */
1365 } const ro;
1366#endif
1367 uint8_t padding[2432]; /* multiple of 64 */
1368 } dbgf;
1369
1370 /** SSM part. */
1371 union
1372 {
1373#ifdef ___SSMInternal_h
1374 struct SSM s;
1375#endif
1376 uint8_t padding[128]; /* multiple of 64 */
1377 } ssm;
1378
1379 /** FTM part. */
1380 union
1381 {
1382#ifdef ___FTMInternal_h
1383 struct FTM s;
1384#endif
1385 uint8_t padding[512]; /* multiple of 64 */
1386 } ftm;
1387
1388#ifdef VBOX_WITH_RAW_MODE
1389 /** PATM part. */
1390 union
1391 {
1392# ifdef ___PATMInternal_h
1393 struct PATM s;
1394# endif
1395 uint8_t padding[768]; /* multiple of 64 */
1396 } patm;
1397
1398 /** CSAM part. */
1399 union
1400 {
1401# ifdef ___CSAMInternal_h
1402 struct CSAM s;
1403# endif
1404 uint8_t padding[1088]; /* multiple of 64 */
1405 } csam;
1406#endif
1407
1408#ifdef VBOX_WITH_REM
1409 /** REM part. */
1410 union
1411 {
1412# ifdef ___REMInternal_h
1413 struct REM s;
1414# endif
1415 uint8_t padding[0x11100]; /* multiple of 64 */
1416 } rem;
1417#endif
1418
1419 union
1420 {
1421#ifdef ___GIMInternal_h
1422 struct GIM s;
1423#endif
1424 uint8_t padding[448]; /* multiple of 64 */
1425 } gim;
1426
1427 union
1428 {
1429#ifdef ___APICInternal_h
1430 struct APIC s;
1431#endif
1432 uint8_t padding[128]; /* multiple of 8 */
1433 } apic;
1434
1435 /* ---- begin small stuff ---- */
1436
1437 /** VM part. */
1438 union
1439 {
1440#ifdef ___VMInternal_h
1441 struct VMINT s;
1442#endif
1443 uint8_t padding[32]; /* multiple of 8 */
1444 } vm;
1445
1446 /** CFGM part. */
1447 union
1448 {
1449#ifdef ___CFGMInternal_h
1450 struct CFGM s;
1451#endif
1452 uint8_t padding[8]; /* multiple of 8 */
1453 } cfgm;
1454
1455 /** Padding for aligning the cpu array on a page boundary. */
1456#if defined(VBOX_WITH_REM) && defined(VBOX_WITH_RAW_MODE)
1457 uint8_t abAlignment2[3670];
1458#elif defined(VBOX_WITH_REM) && !defined(VBOX_WITH_RAW_MODE)
1459 uint8_t abAlignment2[1430];
1460#elif !defined(VBOX_WITH_REM) && defined(VBOX_WITH_RAW_MODE)
1461 uint8_t abAlignment2[3926];
1462#else
1463 uint8_t abAlignment2[1686];
1464#endif
1465
1466 /* ---- end small stuff ---- */
1467
1468 /** VMCPU array for the configured number of virtual CPUs.
1469 * Must be aligned on a page boundary for TLB hit reasons as well as
1470 * alignment of VMCPU members. */
1471 VMCPU aCpus[1];
1472} VM;
1473
1474
1475#ifdef IN_RC
1476RT_C_DECLS_BEGIN
1477
1478/** The VM structure.
1479 * This is imported from the VMMRCBuiltin module, i.e. it's a one of those magic
1480 * globals which we should avoid using.
1481 */
1482extern DECLIMPORT(VM) g_VM;
1483
1484RT_C_DECLS_END
1485#endif
1486
1487/** @} */
1488
1489#endif
1490
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