vm.h@ 74794

Last change on this file since 74794 was 74794, checked in by vboxsync, 6 years ago
vm.h: Added _BIT macros for all FFs. bugref:9180
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1	/** @file
2	* VM - The Virtual Machine, data.
3	*/
4
5	/*
6	* Copyright (C) 2006-2017 Oracle Corporation
7	*
8	* This file is part of VirtualBox Open Source Edition (OSE), as
9	* available from http://www.virtualbox.org. This file is free software;
10	* you can redistribute it and/or modify it under the terms of the GNU
11	* General Public License (GPL) as published by the Free Software
12	* Foundation, in version 2 as it comes in the "COPYING" file of the
13	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15	*
16	* The contents of this file may alternatively be used under the terms
17	* of the Common Development and Distribution License Version 1.0
18	* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19	* VirtualBox OSE distribution, in which case the provisions of the
20	* CDDL are applicable instead of those of the GPL.
21	*
22	* You may elect to license modified versions of this file under the
23	* terms and conditions of either the GPL or the CDDL or both.
24	*/
25
26	#ifndef ___VBox_vmm_vm_h
27	#define ___VBox_vmm_vm_h
28
29	#ifndef VBOX_FOR_DTRACE_LIB
30	# include <iprt/param.h>
31	# include <VBox/types.h>
32	# include <VBox/vmm/cpum.h>
33	# include <VBox/vmm/stam.h>
34	# include <VBox/vmm/vmapi.h>
35	# include <VBox/vmm/vmm.h>
36	# include <VBox/sup.h>
37	#else
38	# pragma D depends_on library vbox-types.d
39	# pragma D depends_on library CPUMInternal.d
40	# define ___CPUMInternal_h
41	#endif
42
43
44
45	/** @defgroup grp_vm The Virtual Machine
46	* @ingroup grp_vmm
47	* @{
48	*/
49
50	/**
51	* The state of a Virtual CPU.
52	*
53	* The basic state indicated here is whether the CPU has been started or not. In
54	* addition, there are sub-states when started for assisting scheduling (GVMM
55	* mostly).
56	*
57	* The transition out of the STOPPED state is done by a vmR3PowerOn.
58	* The transition back to the STOPPED state is done by vmR3PowerOff.
59	*
60	* (Alternatively we could let vmR3PowerOn start CPU 0 only and let the SPIP
61	* handling switch on the other CPUs. Then vmR3Reset would stop all but CPU 0.)
62	*/
63	typedef enum VMCPUSTATE
64	{
65	/** The customary invalid zero. */
66	VMCPUSTATE_INVALID = 0,
67
68	/** Virtual CPU has not yet been started. */
69	VMCPUSTATE_STOPPED,
70
71	/** CPU started. */
72	VMCPUSTATE_STARTED,
73	/** CPU started in HM context. */
74	VMCPUSTATE_STARTED_HM,
75	/** Executing guest code and can be poked (RC or STI bits of HM). */
76	VMCPUSTATE_STARTED_EXEC,
77	/** Executing guest code in the recompiler. */
78	VMCPUSTATE_STARTED_EXEC_REM,
79	/** Executing guest code using NEM. */
80	VMCPUSTATE_STARTED_EXEC_NEM,
81	VMCPUSTATE_STARTED_EXEC_NEM_WAIT,
82	VMCPUSTATE_STARTED_EXEC_NEM_CANCELED,
83	/** Halted. */
84	VMCPUSTATE_STARTED_HALTED,
85
86	/** The end of valid virtual CPU states. */
87	VMCPUSTATE_END,
88
89	/** Ensure 32-bit type. */
90	VMCPUSTATE_32BIT_HACK = 0x7fffffff
91	} VMCPUSTATE;
92
93
94	/**
95	* The cross context virtual CPU structure.
96	*
97	* Run 'kmk run-struct-tests' (from src/VBox/VMM if you like) after updating!
98	*/
99	typedef struct VMCPU
100	{
101	/** Per CPU forced action.
102	* See the VMCPU_FF_* \#defines. Updated atomically. */
103	uint32_t volatile fLocalForcedActions; /* 0 */
104	/** The CPU state. */
105	VMCPUSTATE volatile enmState; /* 4 */
106
107	/** Pointer to the ring-3 UVMCPU structure. */
108	PUVMCPU pUVCpu; /* 8 */
109	/** Ring-3 Host Context VM Pointer. */
110	PVMR3 pVMR3; /* 16 / 12 */
111	/** Ring-0 Host Context VM Pointer. */
112	PVMR0 pVMR0; /* 24 / 16 */
113	/** Raw-mode Context VM Pointer. */
114	PVMRC pVMRC; /* 32 / 20 */
115	/** The CPU ID.
116	* This is the index into the VM::aCpu array. */
117	VMCPUID idCpu; /* 36 / 24 */
118	/** The native thread handle. */
119	RTNATIVETHREAD hNativeThread; /* 40 / 28 */
120	/** The native R0 thread handle. (different from the R3 handle!) */
121	RTNATIVETHREAD hNativeThreadR0; /* 48 / 32 */
122	/** Which host CPU ID is this EMT running on.
123	* Only valid when in RC or HMR0 with scheduling disabled. */
124	RTCPUID volatile idHostCpu; /* 56 / 36 */
125	/** The CPU set index corresponding to idHostCpu, UINT32_MAX if not valid.
126	* @remarks Best to make sure iHostCpuSet shares cache line with idHostCpu! */
127	uint32_t volatile iHostCpuSet; /* 60 / 40 */
128
129	#if HC_ARCH_BITS == 32
130	/** Align the structures below bit on a 64-byte boundary and make sure it starts
131	* at the same offset in both 64-bit and 32-bit builds.
132	*
133	* @remarks The alignments of the members that are larger than 48 bytes should be
134	* 64-byte for cache line reasons. structs containing small amounts of
135	* data could be lumped together at the end with a < 64 byte padding
136	* following it (to grow into and align the struct size).
137	*/
138	uint8_t abAlignment1[HC_ARCH_BITS == 64 ? 0 : 20];
139	#endif
140
141	/** IEM part.
142	* @remarks This comes first as it allows the use of 8-bit immediates for the
143	* first 64 bytes of the structure, reducing code size a wee bit. */
144	#ifdef ___IEMInternal_h /* For PDB hacking. */
145	union VMCPUUNIONIEMFULL
146	#else
147	union VMCPUUNIONIEMSTUB
148	#endif
149	{
150	#ifdef ___IEMInternal_h
151	struct IEMCPU s;
152	#endif
153	uint8_t padding[18496]; /* multiple of 64 */
154	} iem;
155
156	/** HM part. */
157	union VMCPUUNIONHM
158	{
159	#ifdef ___HMInternal_h
160	struct HMCPU s;
161	#endif
162	uint8_t padding[5888]; /* multiple of 64 */
163	} hm;
164
165	/** NEM part. */
166	union VMCPUUNIONNEM
167	{
168	#ifdef ___NEMInternal_h
169	struct NEMCPU s;
170	#endif
171	uint8_t padding[512]; /* multiple of 64 */
172	} nem;
173
174	/** TRPM part. */
175	union VMCPUUNIONTRPM
176	{
177	#ifdef ___TRPMInternal_h
178	struct TRPMCPU s;
179	#endif
180	uint8_t padding[128]; /* multiple of 64 */
181	} trpm;
182
183	/** TM part. */
184	union VMCPUUNIONTM
185	{
186	#ifdef ___TMInternal_h
187	struct TMCPU s;
188	#endif
189	uint8_t padding[384]; /* multiple of 64 */
190	} tm;
191
192	/** VMM part. */
193	union VMCPUUNIONVMM
194	{
195	#ifdef ___VMMInternal_h
196	struct VMMCPU s;
197	#endif
198	uint8_t padding[768]; /* multiple of 64 */
199	} vmm;
200
201	/** PDM part. */
202	union VMCPUUNIONPDM
203	{
204	#ifdef ___PDMInternal_h
205	struct PDMCPU s;
206	#endif
207	uint8_t padding[256]; /* multiple of 64 */
208	} pdm;
209
210	/** IOM part. */
211	union VMCPUUNIONIOM
212	{
213	#ifdef ___IOMInternal_h
214	struct IOMCPU s;
215	#endif
216	uint8_t padding[512]; /* multiple of 64 */
217	} iom;
218
219	/** DBGF part.
220	* @todo Combine this with other tiny structures. */
221	union VMCPUUNIONDBGF
222	{
223	#ifdef ___DBGFInternal_h
224	struct DBGFCPU s;
225	#endif
226	uint8_t padding[256]; /* multiple of 64 */
227	} dbgf;
228
229	/** GIM part. */
230	union VMCPUUNIONGIM
231	{
232	#ifdef ___GIMInternal_h
233	struct GIMCPU s;
234	#endif
235	uint8_t padding[512]; /* multiple of 64 */
236	} gim;
237
238	/** APIC part. */
239	union VMCPUUNIONAPIC
240	{
241	#ifdef ___APICInternal_h
242	struct APICCPU s;
243	#endif
244	uint8_t padding[1792]; /* multiple of 64 */
245	} apic;
246
247	/*
248	* Some less frequently used global members that doesn't need to take up
249	* precious space at the head of the structure.
250	*/
251
252	/** Trace groups enable flags. */
253	uint32_t fTraceGroups; /* 64 / 44 */
254	/** State data for use by ad hoc profiling. */
255	uint32_t uAdHoc;
256	/** Profiling samples for use by ad hoc profiling. */
257	STAMPROFILEADV aStatAdHoc[8]; /* size: 408 = 320 /
258
259	/** Align the following members on page boundary. */
260	uint8_t abAlignment2[2872];
261
262	/** PGM part. */
263	union VMCPUUNIONPGM
264	{
265	#ifdef ___PGMInternal_h
266	struct PGMCPU s;
267	#endif
268	uint8_t padding[4096]; /* multiple of 4096 */
269	} pgm;
270
271	/** CPUM part. */
272	union VMCPUUNIONCPUM
273	{
274	#ifdef ___CPUMInternal_h
275	struct CPUMCPU s;
276	#endif
277	#ifdef VMCPU_INCL_CPUM_GST_CTX
278	/** The guest CPUM context for direct use by execution engines.
279	* This is not for general consumption, but for HM, REM, IEM, and maybe a few
280	* others. The rest will use the function based CPUM API. */
281	CPUMCTX GstCtx;
282	#endif
283	uint8_t padding[4096]; /* multiple of 4096 */
284	} cpum;
285
286	/** EM part. */
287	union VMCPUUNIONEM
288	{
289	#ifdef ___EMInternal_h
290	struct EMCPU s;
291	#endif
292	uint8_t padding[40960]; /* multiple of 4096 */
293	} em;
294	} VMCPU;
295
296
297	#ifndef VBOX_FOR_DTRACE_LIB
298
299	/** @name Operations on VMCPU::enmState
300	* @{ */
301	/** Gets the VMCPU state. */
302	#define VMCPU_GET_STATE(pVCpu) ( (pVCpu)->enmState )
303	/** Sets the VMCPU state. */
304	#define VMCPU_SET_STATE(pVCpu, enmNewState) \
305	ASMAtomicWriteU32((uint32_t volatile *)&(pVCpu)->enmState, (enmNewState))
306	/** Cmpares and sets the VMCPU state. */
307	#define VMCPU_CMPXCHG_STATE(pVCpu, enmNewState, enmOldState) \
308	ASMAtomicCmpXchgU32((uint32_t volatile *)&(pVCpu)->enmState, (enmNewState), (enmOldState))
309	/** Checks the VMCPU state. */
310	#ifdef VBOX_STRICT
311	# define VMCPU_ASSERT_STATE(pVCpu, enmExpectedState) \
312	do { \
313	VMCPUSTATE enmState = VMCPU_GET_STATE(pVCpu); \
314	AssertMsg(enmState == (enmExpectedState), \
315	("enmState=%d enmExpectedState=%d idCpu=%u\n", \
316	enmState, enmExpectedState, (pVCpu)->idCpu)); \
317	} while (0)
318	#else
319	# define VMCPU_ASSERT_STATE(pVCpu, enmExpectedState) do { } while (0)
320	#endif
321	/** Tests if the state means that the CPU is started. */
322	#define VMCPUSTATE_IS_STARTED(enmState) ( (enmState) > VMCPUSTATE_STOPPED )
323	/** Tests if the state means that the CPU is stopped. */
324	#define VMCPUSTATE_IS_STOPPED(enmState) ( (enmState) == VMCPUSTATE_STOPPED )
325	/** @} */
326
327
328	/** The name of the raw-mode context VMM Core module. */
329	#define VMMRC_MAIN_MODULE_NAME "VMMRC.rc"
330	/** The name of the ring-0 context VMM Core module. */
331	#define VMMR0_MAIN_MODULE_NAME "VMMR0.r0"
332
333	/**
334	* Wrapper macro for avoiding too much \#ifdef VBOX_WITH_RAW_MODE.
335	*/
336	#ifdef VBOX_WITH_RAW_MODE
337	# define VM_WHEN_RAW_MODE(a_WithExpr, a_WithoutExpr) a_WithExpr
338	#else
339	# define VM_WHEN_RAW_MODE(a_WithExpr, a_WithoutExpr) a_WithoutExpr
340	#endif
341
342
343	/** VM Forced Action Flags.
344	*
345	* Use the VM_FF_SET() and VM_FF_CLEAR() macros to change the force
346	* action mask of a VM.
347	*
348	* Available VM bits:
349	* 0, 1, 5, 6, 7, 13, 14, 15, 16, 17, 21, 22, 23, 24, 25, 26, 27, 28, 30
350	*
351	*
352	* Available VMCPU bits:
353	* 14, 15
354	*
355	* @todo If we run low on VMCPU, we may consider merging the SELM bits
356	*
357	* @{
358	*/
359	/** The virtual sync clock has been stopped, go to TM until it has been
360	* restarted... */
361	#define VM_FF_TM_VIRTUAL_SYNC RT_BIT_32(VM_FF_TM_VIRTUAL_SYNC_BIT)
362	#define VM_FF_TM_VIRTUAL_SYNC_BIT 2
363	/** PDM Queues are pending. */
364	#define VM_FF_PDM_QUEUES RT_BIT_32(VM_FF_PDM_QUEUES_BIT)
365	/** The bit number for VM_FF_PDM_QUEUES. */
366	#define VM_FF_PDM_QUEUES_BIT 3
367	/** PDM DMA transfers are pending. */
368	#define VM_FF_PDM_DMA RT_BIT_32(VM_FF_PDM_DMA_BIT)
369	/** The bit number for VM_FF_PDM_DMA. */
370	#define VM_FF_PDM_DMA_BIT 4
371	/** This action forces the VM to call DBGF so DBGF can service debugger
372	* requests in the emulation thread.
373	* This action flag stays asserted till DBGF clears it.*/
374	#define VM_FF_DBGF RT_BIT_32(VM_FF_DBGF_BIT)
375	/** The bit number for VM_FF_DBGF. */
376	#define VM_FF_DBGF_BIT 8
377	/** This action forces the VM to service pending requests from other
378	* thread or requests which must be executed in another context. */
379	#define VM_FF_REQUEST RT_BIT_32(VM_FF_REQUEST_BIT)
380	#define VM_FF_REQUEST_BIT 9
381	/** Check for VM state changes and take appropriate action. */
382	#define VM_FF_CHECK_VM_STATE RT_BIT_32(VM_FF_CHECK_VM_STATE_BIT)
383	/** The bit number for VM_FF_CHECK_VM_STATE. */
384	#define VM_FF_CHECK_VM_STATE_BIT 10
385	/** Reset the VM. (postponed) */
386	#define VM_FF_RESET RT_BIT_32(VM_FF_RESET_BIT)
387	/** The bit number for VM_FF_RESET. */
388	#define VM_FF_RESET_BIT 11
389	/** EMT rendezvous in VMM. */
390	#define VM_FF_EMT_RENDEZVOUS RT_BIT_32(VM_FF_EMT_RENDEZVOUS_BIT)
391	/** The bit number for VM_FF_EMT_RENDEZVOUS. */
392	#define VM_FF_EMT_RENDEZVOUS_BIT 12
393
394	/** PGM needs to allocate handy pages. */
395	#define VM_FF_PGM_NEED_HANDY_PAGES RT_BIT_32(VM_FF_PGM_NEED_HANDY_PAGES_BIT)
396	#define VM_FF_PGM_NEED_HANDY_PAGES_BIT 18
397	/** PGM is out of memory.
398	* Abandon all loops and code paths which can be resumed and get up to the EM
399	* loops. */
400	#define VM_FF_PGM_NO_MEMORY RT_BIT_32(VM_FF_PGM_NO_MEMORY_BIT)
401	#define VM_FF_PGM_NO_MEMORY_BIT 19
402	/** PGM is about to perform a lightweight pool flush
403	* Guest SMP: all EMT threads should return to ring 3
404	*/
405	#define VM_FF_PGM_POOL_FLUSH_PENDING RT_BIT_32(VM_FF_PGM_POOL_FLUSH_PENDING_BIT)
406	#define VM_FF_PGM_POOL_FLUSH_PENDING_BIT 20
407	/** REM needs to be informed about handler changes. */
408	#define VM_FF_REM_HANDLER_NOTIFY RT_BIT_32(VM_FF_REM_HANDLER_NOTIFY_BIT)
409	/** The bit number for VM_FF_REM_HANDLER_NOTIFY. */
410	#define VM_FF_REM_HANDLER_NOTIFY_BIT 29
411	/** Suspend the VM - debug only. */
412	#define VM_FF_DEBUG_SUSPEND RT_BIT_32(VM_FF_DEBUG_SUSPEND_BIT)
413	#define VM_FF_DEBUG_SUSPEND_BIT 31
414
415
416	/** This action forces the VM to check any pending interrupts on the APIC. */
417	#define VMCPU_FF_INTERRUPT_APIC RT_BIT_32(VMCPU_FF_INTERRUPT_APIC_BIT)
418	#define VMCPU_FF_INTERRUPT_APIC_BIT 0
419	/** This action forces the VM to check any pending interrups on the PIC. */
420	#define VMCPU_FF_INTERRUPT_PIC RT_BIT_32(VMCPU_FF_INTERRUPT_PIC_BIT)
421	#define VMCPU_FF_INTERRUPT_PIC_BIT 1
422	/** This action forces the VM to schedule and run pending timer (TM).
423	* @remarks Don't move - PATM compatibility. */
424	#define VMCPU_FF_TIMER RT_BIT_32(VMCPU_FF_TIMER_BIT)
425	#define VMCPU_FF_TIMER_BIT 2
426	/** This action forces the VM to check any pending NMIs. */
427	#define VMCPU_FF_INTERRUPT_NMI RT_BIT_32(VMCPU_FF_INTERRUPT_NMI_BIT)
428	#define VMCPU_FF_INTERRUPT_NMI_BIT 3
429	/** This action forces the VM to check any pending SMIs. */
430	#define VMCPU_FF_INTERRUPT_SMI RT_BIT_32(VMCPU_FF_INTERRUPT_SMI_BIT)
431	#define VMCPU_FF_INTERRUPT_SMI_BIT 4
432	/** PDM critical section unlocking is pending, process promptly upon return to R3. */
433	#define VMCPU_FF_PDM_CRITSECT RT_BIT_32(VMCPU_FF_PDM_CRITSECT_BIT)
434	#define VMCPU_FF_PDM_CRITSECT_BIT 5
435	/** Special EM internal force flag that is used by EMUnhaltAndWakeUp() to force
436	* the virtual CPU out of the next (/current) halted state. It is not processed
437	* nor cleared by emR3ForcedActions (similar to VMCPU_FF_BLOCK_NMIS), instead it
438	* is cleared the next time EM leaves the HALTED state. */
439	#define VMCPU_FF_UNHALT RT_BIT_32(VMCPU_FF_UNHALT_BIT)
440	#define VMCPU_FF_UNHALT_BIT 6
441	/** Pending IEM action (mask). */
442	#define VMCPU_FF_IEM RT_BIT_32(VMCPU_FF_IEM_BIT)
443	/** Pending IEM action (bit number). */
444	#define VMCPU_FF_IEM_BIT 7
445	/** Pending APIC action (bit number). */
446	#define VMCPU_FF_UPDATE_APIC_BIT 8
447	/** This action forces the VM to update APIC's asynchronously arrived
448	* interrupts as pending interrupts. */
449	#define VMCPU_FF_UPDATE_APIC RT_BIT_32(VMCPU_FF_UPDATE_APIC_BIT)
450	/** This action forces the VM to service pending requests from other
451	* thread or requests which must be executed in another context. */
452	#define VMCPU_FF_REQUEST RT_BIT_32(VMCPU_FF_REQUEST_BIT)
453	#define VMCPU_FF_REQUEST_BIT 9
454	/** Pending DBGF event (alternative to passing VINF_EM_DBG_EVENT around). */
455	#define VMCPU_FF_DBGF RT_BIT_32(VMCPU_FF_DBGF_BIT)
456	/** The bit number for VMCPU_FF_DBGF. */
457	#define VMCPU_FF_DBGF_BIT 10
458	/** Pending MTF (Monitor Trap Flag) event - Intel only. */
459	#define VMCPU_FF_MTF RT_BIT_32(VMCPU_FF_MTF_BIT)
460	/** The bit number for VMCPU_FF_MTF. */
461	#define VMCPU_FF_MTF_BIT 11
462	/** This action forces the VM to service any pending updates to CR3 (used only
463	* by HM). */
464	#define VMCPU_FF_HM_UPDATE_CR3 RT_BIT_32(VMCPU_FF_HM_UPDATE_CR3_BIT)
465	#define VMCPU_FF_HM_UPDATE_CR3_BIT 12
466	/** This action forces the VM to service any pending updates to PAE PDPEs (used
467	* only by HM). */
468	#define VMCPU_FF_HM_UPDATE_PAE_PDPES RT_BIT_32(VMCPU_FF_HM_UPDATE_PAE_PDPES_BIT)
469	#define VMCPU_FF_HM_UPDATE_PAE_PDPES_BIT 13
470	/** This action forces the VM to resync the page tables before going
471	* back to execute guest code. (GLOBAL FLUSH) */
472	#define VMCPU_FF_PGM_SYNC_CR3 RT_BIT_32(VMCPU_FF_PGM_SYNC_CR3_BIT)
473	#define VMCPU_FF_PGM_SYNC_CR3_BIT 16
474	/** Same as VM_FF_PGM_SYNC_CR3 except that global pages can be skipped.
475	* (NON-GLOBAL FLUSH) */
476	#define VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL RT_BIT_32(VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL_BIT)
477	#define VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL_BIT 17
478	/** Check for pending TLB shootdown actions (deprecated)
479	* Reserved for furture HM re-use if necessary / safe.
480	* Consumer: HM */
481	#define VMCPU_FF_TLB_SHOOTDOWN_UNUSED RT_BIT_32(VMCPU_FF_TLB_SHOOTDOWN_UNUSED_BIT)
482	#define VMCPU_FF_TLB_SHOOTDOWN_UNUSED_BIT 18
483	/** Check for pending TLB flush action.
484	* Consumer: HM
485	* @todo rename to VMCPU_FF_HM_TLB_FLUSH */
486	#define VMCPU_FF_TLB_FLUSH RT_BIT_32(VMCPU_FF_TLB_FLUSH_BIT)
487	/** The bit number for VMCPU_FF_TLB_FLUSH. */
488	#define VMCPU_FF_TLB_FLUSH_BIT 19
489	#ifdef VBOX_WITH_RAW_MODE
490	/** Check the interrupt and trap gates */
491	# define VMCPU_FF_TRPM_SYNC_IDT RT_BIT_32(VMCPU_FF_TRPM_SYNC_IDT_BIT)
492	# define VMCPU_FF_TRPM_SYNC_IDT_BIT 20
493	/** Check Guest's TSS ring 0 stack */
494	# define VMCPU_FF_SELM_SYNC_TSS RT_BIT_32(VMCPU_FF_SELM_SYNC_TSS_BIT)
495	# define VMCPU_FF_SELM_SYNC_TSS_BIT 21
496	/** Check Guest's GDT table */
497	# define VMCPU_FF_SELM_SYNC_GDT RT_BIT_32(VMCPU_FF_SELM_SYNC_GDT_BIT)
498	# define VMCPU_FF_SELM_SYNC_GDT_BIT 22
499	/** Check Guest's LDT table */
500	# define VMCPU_FF_SELM_SYNC_LDT RT_BIT_32(VMCPU_FF_SELM_SYNC_LDT_BIT)
501	# define VMCPU_FF_SELM_SYNC_LDT_BIT 23
502	#endif /* VBOX_WITH_RAW_MODE */
503	/** Inhibit interrupts pending. See EMGetInhibitInterruptsPC(). */
504	#define VMCPU_FF_INHIBIT_INTERRUPTS RT_BIT_32(VMCPU_FF_INHIBIT_INTERRUPTS_BIT)
505	#define VMCPU_FF_INHIBIT_INTERRUPTS_BIT 24
506	/** Block injection of non-maskable interrupts to the guest. */
507	#define VMCPU_FF_BLOCK_NMIS RT_BIT_32(VMCPU_FF_BLOCK_NMIS_BIT)
508	#define VMCPU_FF_BLOCK_NMIS_BIT 25
509	#ifdef VBOX_WITH_RAW_MODE
510	/** CSAM needs to scan the page that's being executed */
511	# define VMCPU_FF_CSAM_SCAN_PAGE RT_BIT_32(VMCPU_FF_CSAM_SCAN_PAGE_BIT)
512	# define VMCPU_FF_CSAM_SCAN_PAGE_BIT 26
513	/** CSAM needs to do some homework. */
514	# define VMCPU_FF_CSAM_PENDING_ACTION RT_BIT_32(VMCPU_FF_CSAM_PENDING_ACTION_BIT)
515	# define VMCPU_FF_CSAM_PENDING_ACTION_BIT 27
516	#endif /* VBOX_WITH_RAW_MODE */
517	/** Force return to Ring-3. */
518	#define VMCPU_FF_TO_R3 RT_BIT_32(VMCPU_FF_TO_R3_BIT)
519	#define VMCPU_FF_TO_R3_BIT 28
520	/** Force return to ring-3 to service pending I/O or MMIO write.
521	* This is a backup for mechanism VINF_IOM_R3_IOPORT_COMMIT_WRITE and
522	* VINF_IOM_R3_MMIO_COMMIT_WRITE, allowing VINF_EM_DBG_BREAKPOINT and similar
523	* status codes to be propagated at the same time without loss. */
524	#define VMCPU_FF_IOM RT_BIT_32(VMCPU_FF_IOM_BIT)
525	#define VMCPU_FF_IOM_BIT 29
526	#ifdef VBOX_WITH_RAW_MODE
527	/** CPUM need to adjust CR0.TS/EM before executing raw-mode code again. */
528	# define VMCPU_FF_CPUM RT_BIT_32(VMCPU_FF_CPUM_BIT)
529	/** The bit number for VMCPU_FF_CPUM. */
530	# define VMCPU_FF_CPUM_BIT 30
531	#endif /* VBOX_WITH_RAW_MODE */
532	/** Hardware virtualized nested-guest interrupt pending. */
533	#define VMCPU_FF_INTERRUPT_NESTED_GUEST RT_BIT_32(VMCPU_FF_INTERRUPT_NESTED_GUEST_BIT)
534	#define VMCPU_FF_INTERRUPT_NESTED_GUEST_BIT 31
535
536
537	/** Externally VM forced actions. Used to quit the idle/wait loop. */
538	#define VM_FF_EXTERNAL_SUSPENDED_MASK ( VM_FF_CHECK_VM_STATE \| VM_FF_DBGF \| VM_FF_REQUEST \| VM_FF_EMT_RENDEZVOUS )
539	/** Externally VMCPU forced actions. Used to quit the idle/wait loop. */
540	#define VMCPU_FF_EXTERNAL_SUSPENDED_MASK ( VMCPU_FF_REQUEST \| VMCPU_FF_DBGF )
541
542	/** Externally forced VM actions. Used to quit the idle/wait loop. */
543	#define VM_FF_EXTERNAL_HALTED_MASK ( VM_FF_CHECK_VM_STATE \| VM_FF_DBGF \| VM_FF_REQUEST \
544	\| VM_FF_PDM_QUEUES \| VM_FF_PDM_DMA \| VM_FF_EMT_RENDEZVOUS )
545	/** Externally forced VMCPU actions. Used to quit the idle/wait loop. */
546	#define VMCPU_FF_EXTERNAL_HALTED_MASK ( VMCPU_FF_UPDATE_APIC \| VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC \
547	\| VMCPU_FF_REQUEST \| VMCPU_FF_INTERRUPT_NMI \| VMCPU_FF_INTERRUPT_SMI \
548	\| VMCPU_FF_UNHALT \| VMCPU_FF_TIMER \| VMCPU_FF_DBGF )
549
550	/** High priority VM pre-execution actions. */
551	#define VM_FF_HIGH_PRIORITY_PRE_MASK ( VM_FF_CHECK_VM_STATE \| VM_FF_DBGF \| VM_FF_TM_VIRTUAL_SYNC \
552	\| VM_FF_DEBUG_SUSPEND \| VM_FF_PGM_NEED_HANDY_PAGES \| VM_FF_PGM_NO_MEMORY \
553	\| VM_FF_EMT_RENDEZVOUS )
554	/** High priority VMCPU pre-execution actions. */
555	#define VMCPU_FF_HIGH_PRIORITY_PRE_MASK ( VMCPU_FF_TIMER \| VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC \
556	\| VMCPU_FF_UPDATE_APIC \| VMCPU_FF_INHIBIT_INTERRUPTS \| VMCPU_FF_DBGF \
557	\| VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL \
558	\| VM_WHEN_RAW_MODE( VMCPU_FF_SELM_SYNC_TSS \| VMCPU_FF_TRPM_SYNC_IDT \
559	\| VMCPU_FF_SELM_SYNC_GDT \| VMCPU_FF_SELM_SYNC_LDT, 0 ) )
560
561	/** High priority VM pre raw-mode execution mask. */
562	#define VM_FF_HIGH_PRIORITY_PRE_RAW_MASK ( VM_FF_PGM_NEED_HANDY_PAGES \| VM_FF_PGM_NO_MEMORY )
563	/** High priority VMCPU pre raw-mode execution mask. */
564	#define VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK ( VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL \
565	\| VMCPU_FF_INHIBIT_INTERRUPTS \
566	\| VM_WHEN_RAW_MODE( VMCPU_FF_SELM_SYNC_TSS \| VMCPU_FF_TRPM_SYNC_IDT \
567	\| VMCPU_FF_SELM_SYNC_GDT \| VMCPU_FF_SELM_SYNC_LDT, 0) )
568
569	/** High priority post-execution actions. */
570	#define VM_FF_HIGH_PRIORITY_POST_MASK ( VM_FF_PGM_NO_MEMORY )
571	/** High priority post-execution actions. */
572	#define VMCPU_FF_HIGH_PRIORITY_POST_MASK ( VMCPU_FF_PDM_CRITSECT \| VM_WHEN_RAW_MODE(VMCPU_FF_CSAM_PENDING_ACTION, 0) \
573	\| VMCPU_FF_HM_UPDATE_CR3 \| VMCPU_FF_HM_UPDATE_PAE_PDPES \
574	\| VMCPU_FF_IEM \| VMCPU_FF_IOM )
575
576	/** Normal priority VM post-execution actions. */
577	#define VM_FF_NORMAL_PRIORITY_POST_MASK ( VM_FF_CHECK_VM_STATE \| VM_FF_DBGF \| VM_FF_RESET \
578	\| VM_FF_PGM_NO_MEMORY \| VM_FF_EMT_RENDEZVOUS)
579	/** Normal priority VMCPU post-execution actions. */
580	#define VMCPU_FF_NORMAL_PRIORITY_POST_MASK ( VM_WHEN_RAW_MODE(VMCPU_FF_CSAM_SCAN_PAGE, 0) \| VMCPU_FF_DBGF )
581
582	/** Normal priority VM actions. */
583	#define VM_FF_NORMAL_PRIORITY_MASK ( VM_FF_REQUEST \| VM_FF_PDM_QUEUES \| VM_FF_PDM_DMA \
584	\| VM_FF_REM_HANDLER_NOTIFY \| VM_FF_EMT_RENDEZVOUS)
585	/** Normal priority VMCPU actions. */
586	#define VMCPU_FF_NORMAL_PRIORITY_MASK ( VMCPU_FF_REQUEST )
587
588	/** Flags to clear before resuming guest execution. */
589	#define VMCPU_FF_RESUME_GUEST_MASK ( VMCPU_FF_TO_R3 )
590
591
592	/** VM flags that cause the REP[\|NE\|E] STRINS loops to yield immediately. */
593	#define VM_FF_HIGH_PRIORITY_POST_REPSTR_MASK ( VM_FF_TM_VIRTUAL_SYNC \| VM_FF_PGM_NEED_HANDY_PAGES \| VM_FF_PGM_NO_MEMORY \
594	\| VM_FF_EMT_RENDEZVOUS \| VM_FF_PGM_POOL_FLUSH_PENDING \| VM_FF_RESET)
595	/** VM flags that cause the REP[\|NE\|E] STRINS loops to yield. */
596	#define VM_FF_YIELD_REPSTR_MASK ( VM_FF_HIGH_PRIORITY_POST_REPSTR_MASK \
597	\| VM_FF_PDM_QUEUES \| VM_FF_PDM_DMA \| VM_FF_DBGF \| VM_FF_DEBUG_SUSPEND )
598	/** VMCPU flags that cause the REP[\|NE\|E] STRINS loops to yield immediately. */
599	#ifdef IN_RING3
600	# define VMCPU_FF_HIGH_PRIORITY_POST_REPSTR_MASK ( VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL \| VMCPU_FF_DBGF )
601	#else
602	# define VMCPU_FF_HIGH_PRIORITY_POST_REPSTR_MASK ( VMCPU_FF_TO_R3 \| VMCPU_FF_IEM \| VMCPU_FF_IOM \| VMCPU_FF_PGM_SYNC_CR3 \
603	\| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL \| VMCPU_FF_DBGF )
604	#endif
605	/** VMCPU flags that cause the REP[\|NE\|E] STRINS loops to yield, interrupts
606	* enabled. */
607	#define VMCPU_FF_YIELD_REPSTR_MASK ( VMCPU_FF_HIGH_PRIORITY_POST_REPSTR_MASK \
608	\| VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_UPDATE_APIC \| VMCPU_FF_INTERRUPT_PIC \
609	\| VMCPU_FF_INTERRUPT_NMI \| VMCPU_FF_INTERRUPT_SMI \| VMCPU_FF_PDM_CRITSECT \
610	\| VMCPU_FF_TIMER \| VMCPU_FF_REQUEST )
611	/** VMCPU flags that cause the REP[\|NE\|E] STRINS loops to yield, interrupts
612	* disabled. */
613	#define VMCPU_FF_YIELD_REPSTR_NOINT_MASK ( VMCPU_FF_YIELD_REPSTR_MASK \
614	& ~(VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_UPDATE_APIC \| VMCPU_FF_INTERRUPT_PIC) )
615
616	/** VM Flags that cause the HM loops to go back to ring-3. */
617	#define VM_FF_HM_TO_R3_MASK ( VM_FF_TM_VIRTUAL_SYNC \| VM_FF_PGM_NEED_HANDY_PAGES \| VM_FF_PGM_NO_MEMORY \
618	\| VM_FF_PDM_QUEUES \| VM_FF_EMT_RENDEZVOUS)
619	/** VMCPU Flags that cause the HM loops to go back to ring-3. */
620	#define VMCPU_FF_HM_TO_R3_MASK ( VMCPU_FF_TO_R3 \| VMCPU_FF_TIMER \| VMCPU_FF_PDM_CRITSECT \
621	\| VMCPU_FF_IEM \| VMCPU_FF_IOM)
622
623	/** High priority ring-0 VM pre HM-mode execution mask. */
624	#define VM_FF_HP_R0_PRE_HM_MASK (VM_FF_HM_TO_R3_MASK \| VM_FF_REQUEST \| VM_FF_PGM_POOL_FLUSH_PENDING \| VM_FF_PDM_DMA)
625	/** High priority ring-0 VMCPU pre HM-mode execution mask. */
626	#define VMCPU_FF_HP_R0_PRE_HM_MASK ( VMCPU_FF_HM_TO_R3_MASK \| VMCPU_FF_PGM_SYNC_CR3 \
627	\| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL \| VMCPU_FF_REQUEST)
628	/** High priority ring-0 VM pre HM-mode execution mask, single stepping. */
629	#define VM_FF_HP_R0_PRE_HM_STEP_MASK (VM_FF_HP_R0_PRE_HM_MASK & ~( VM_FF_TM_VIRTUAL_SYNC \| VM_FF_PDM_QUEUES \
630	\| VM_FF_EMT_RENDEZVOUS \| VM_FF_REQUEST \
631	\| VM_FF_PDM_DMA) )
632	/** High priority ring-0 VMCPU pre HM-mode execution mask, single stepping. */
633	#define VMCPU_FF_HP_R0_PRE_HM_STEP_MASK (VMCPU_FF_HP_R0_PRE_HM_MASK & ~( VMCPU_FF_TO_R3 \| VMCPU_FF_TIMER \
634	\| VMCPU_FF_PDM_CRITSECT \| VMCPU_FF_REQUEST) )
635
636	/** All the forced VM flags. */
637	#define VM_FF_ALL_MASK (UINT32_MAX)
638	/** All the forced VMCPU flags. */
639	#define VMCPU_FF_ALL_MASK (UINT32_MAX)
640
641	/** All the forced VM flags except those related to raw-mode and hardware
642	* assisted execution. */
643	#define VM_FF_ALL_REM_MASK (~(VM_FF_HIGH_PRIORITY_PRE_RAW_MASK) \| VM_FF_PGM_NEED_HANDY_PAGES \| VM_FF_PGM_NO_MEMORY)
644	/** All the forced VMCPU flags except those related to raw-mode and hardware
645	* assisted execution. */
646	#define VMCPU_FF_ALL_REM_MASK (~( VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK \| VMCPU_FF_PDM_CRITSECT \
647	\| VMCPU_FF_TLB_FLUSH \| VM_WHEN_RAW_MODE(VMCPU_FF_CSAM_PENDING_ACTION, 0) ))
648	/** @} */
649
650	/** @def VM_FF_SET
651	* Sets a single force action flag.
652	*
653	* @param pVM The cross context VM structure.
654	* @param fFlag The flag to set.
655	*/
656	#define VM_FF_SET(pVM, fFlag) \
657	do { AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); ASMAtomicOrU32(&(pVM)->fGlobalForcedActions, (fFlag)); } while (0)
658
659	/** @def VMCPU_FF_SET
660	* Sets a single force action flag for the given VCPU.
661	*
662	* @param pVCpu The cross context virtual CPU structure.
663	* @param fFlag The flag to set.
664	* @sa VMCPU_FF_SET_MASK
665	*/
666	#define VMCPU_FF_SET(pVCpu, fFlag) \
667	do { AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); ASMAtomicOrU32(&(pVCpu)->fLocalForcedActions, (fFlag)); } while (0)
668
669	/** @def VMCPU_FF_SET_MASK
670	* Sets a two or more force action flag for the given VCPU.
671	*
672	* @param pVCpu The cross context virtual CPU structure.
673	* @param fFlags The flags to set.
674	* @sa VMCPU_FF_SET
675	*/
676	#define VMCPU_FF_SET_MASK(a_pVCpu, fFlags) \
677	do { ASMAtomicOrU32(&a_pVCpu->fLocalForcedActions, (fFlags)); } while (0)
678
679	/** @def VM_FF_CLEAR
680	* Clears a single force action flag.
681	*
682	* @param pVM The cross context VM structure.
683	* @param fFlag The flag to clear.
684	*/
685	#define VM_FF_CLEAR(pVM, fFlag) \
686	do { AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); ASMAtomicAndU32(&(pVM)->fGlobalForcedActions, ~(fFlag)); } while (0)
687
688	/** @def VMCPU_FF_CLEAR
689	* Clears a single force action flag for the given VCPU.
690	*
691	* @param pVCpu The cross context virtual CPU structure.
692	* @param fFlag The flag to clear.
693	*/
694	#define VMCPU_FF_CLEAR(pVCpu, fFlag) \
695	do { AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); ASMAtomicAndU32(&(pVCpu)->fLocalForcedActions, ~(fFlag)); } while (0)
696
697	/** @def VMCPU_FF_CLEAR_MASK
698	* Clears two or more force action flags for the given VCPU.
699	*
700	* @param pVCpu The cross context virtual CPU structure.
701	* @param fFlags The flags to clear.
702	*/
703	#define VMCPU_FF_CLEAR_MASK(pVCpu, fFlags) \
704	do { ASMAtomicAndU32(&(pVCpu)->fLocalForcedActions, ~(fFlags)); } while (0)
705
706	/** @def VM_FF_IS_SET
707	* Checks if single a force action flag is set.
708	*
709	* @param pVM The cross context VM structure.
710	* @param fFlag The flag to check.
711	* @sa VM_FF_IS_ANY_SET
712	*/
713	#if !defined(VBOX_STRICT) \|\| !defined(RT_COMPILER_SUPPORTS_LAMBDA)
714	# define VM_FF_IS_SET(pVM, fFlag) (((pVM)->fGlobalForcedActions & (fFlag)) == (fFlag))
715	#else
716	# define VM_FF_IS_SET(pVM, fFlag) \
717	([](PVM a_pVM) -> bool \
718	{ \
719	AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
720	return (a_pVM->fGlobalForcedActions & (fFlag)) == (fFlag); \
721	}(pVM))
722	#endif
723
724	/** @def VMCPU_FF_IS_SET
725	* Checks if a single force action flag is set for the given VCPU.
726	*
727	* @param pVCpu The cross context virtual CPU structure.
728	* @param fFlag The flag to check.
729	* @sa VMCPU_FF_IS_ANY_SET
730	*/
731	#if !defined(VBOX_STRICT) \|\| !defined(RT_COMPILER_SUPPORTS_LAMBDA)
732	# define VMCPU_FF_IS_SET(pVCpu, fFlag) (((pVCpu)->fLocalForcedActions & (fFlag)) == (fFlag))
733	#else
734	# define VMCPU_FF_IS_SET(pVCpu, fFlag) \
735	([](PVMCPU a_pVCpu) -> bool \
736	{ \
737	AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
738	return (a_pVCpu->fLocalForcedActions & (fFlag)) == (fFlag); \
739	}(pVCpu))
740	#endif
741
742	/** @def VM_FF_IS_ANY_SET
743	* Checks if one or more force action in the specified set is pending.
744	*
745	* @param pVM The cross context VM structure.
746	* @param fFlags The flags to check for.
747	* @sa VM_FF_IS_SET
748	*/
749	#define VM_FF_IS_ANY_SET(pVM, fFlags) RT_BOOL((pVM)->fGlobalForcedActions & (fFlags))
750
751	/** @def VMCPU_FF_IS_ANY_SET
752	* Checks if two or more force action flags in the specified set is set for the given VCPU.
753	*
754	* @param pVCpu The cross context virtual CPU structure.
755	* @param fFlags The flags to check for.
756	* @sa VMCPU_FF_IS_SET
757	*/
758	#define VMCPU_FF_IS_ANY_SET(pVCpu, fFlags) RT_BOOL((pVCpu)->fLocalForcedActions & (fFlags))
759
760	/** @def VM_FF_TEST_AND_CLEAR
761	* Checks if one (!) force action in the specified set is pending and clears it atomically
762	*
763	* @returns true if the bit was set.
764	* @returns false if the bit was clear.
765	* @param pVM The cross context VM structure.
766	* @param fFlag Flag constant to check and clear (_BIT is appended).
767	*/
768	#define VM_FF_TEST_AND_CLEAR(pVM, fFlag) (ASMAtomicBitTestAndClear(&(pVM)->fGlobalForcedActions, fFlag##_BIT))
769
770	/** @def VMCPU_FF_TEST_AND_CLEAR
771	* Checks if one (!) force action in the specified set is pending and clears it atomically
772	*
773	* @returns true if the bit was set.
774	* @returns false if the bit was clear.
775	* @param pVCpu The cross context virtual CPU structure.
776	* @param fFlag Flag constant to check and clear (_BIT is appended).
777	*/
778	#define VMCPU_FF_TEST_AND_CLEAR(pVCpu, fFlag) (ASMAtomicBitTestAndClear(&(pVCpu)->fLocalForcedActions, fFlag##_BIT))
779
780	/** @def VM_FF_IS_PENDING_EXCEPT
781	* Checks if one or more force action in the specified set is pending while one
782	* or more other ones are not.
783	*
784	* @param pVM The cross context VM structure.
785	* @param fFlags The flags to check for.
786	* @param fExcpt The flags that should not be set.
787	*/
788	#define VM_FF_IS_PENDING_EXCEPT(pVM, fFlags, fExcpt) \
789	( ((pVM)->fGlobalForcedActions & (fFlags)) && !((pVM)->fGlobalForcedActions & (fExcpt)) )
790
791	/** @def VM_IS_EMT
792	* Checks if the current thread is the emulation thread (EMT).
793	*
794	* @remark The ring-0 variation will need attention if we expand the ring-0
795	* code to let threads other than EMT mess around with the VM.
796	*/
797	#ifdef IN_RC
798	# define VM_IS_EMT(pVM) true
799	#else
800	# define VM_IS_EMT(pVM) (VMMGetCpu(pVM) != NULL)
801	#endif
802
803	/** @def VMCPU_IS_EMT
804	* Checks if the current thread is the emulation thread (EMT) for the specified
805	* virtual CPU.
806	*/
807	#ifdef IN_RC
808	# define VMCPU_IS_EMT(pVCpu) true
809	#else
810	# define VMCPU_IS_EMT(pVCpu) ((pVCpu) && ((pVCpu) == VMMGetCpu((pVCpu)->CTX_SUFF(pVM))))
811	#endif
812
813	/** @def VM_ASSERT_EMT
814	* Asserts that the current thread IS the emulation thread (EMT).
815	*/
816	#ifdef IN_RC
817	# define VM_ASSERT_EMT(pVM) Assert(VM_IS_EMT(pVM))
818	#elif defined(IN_RING0)
819	# define VM_ASSERT_EMT(pVM) Assert(VM_IS_EMT(pVM))
820	#else
821	# define VM_ASSERT_EMT(pVM) \
822	AssertMsg(VM_IS_EMT(pVM), \
823	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd\n", RTThreadNativeSelf(), VMR3GetVMCPUNativeThread(pVM)))
824	#endif
825
826	/** @def VMCPU_ASSERT_EMT
827	* Asserts that the current thread IS the emulation thread (EMT) of the
828	* specified virtual CPU.
829	*/
830	#ifdef IN_RC
831	# define VMCPU_ASSERT_EMT(pVCpu) Assert(VMCPU_IS_EMT(pVCpu))
832	#elif defined(IN_RING0)
833	# define VMCPU_ASSERT_EMT(pVCpu) AssertMsg(VMCPU_IS_EMT(pVCpu), \
834	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd idCpu=%u\n", \
835	RTThreadNativeSelf(), (pVCpu) ? (pVCpu)->hNativeThreadR0 : 0, \
836	(pVCpu) ? (pVCpu)->idCpu : 0))
837	#else
838	# define VMCPU_ASSERT_EMT(pVCpu) AssertMsg(VMCPU_IS_EMT(pVCpu), \
839	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd idCpu=%#x\n", \
840	RTThreadNativeSelf(), (pVCpu)->hNativeThread, (pVCpu)->idCpu))
841	#endif
842
843	/** @def VM_ASSERT_EMT_RETURN
844	* Asserts that the current thread IS the emulation thread (EMT) and returns if it isn't.
845	*/
846	#ifdef IN_RC
847	# define VM_ASSERT_EMT_RETURN(pVM, rc) AssertReturn(VM_IS_EMT(pVM), (rc))
848	#elif defined(IN_RING0)
849	# define VM_ASSERT_EMT_RETURN(pVM, rc) AssertReturn(VM_IS_EMT(pVM), (rc))
850	#else
851	# define VM_ASSERT_EMT_RETURN(pVM, rc) \
852	AssertMsgReturn(VM_IS_EMT(pVM), \
853	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd\n", RTThreadNativeSelf(), VMR3GetVMCPUNativeThread(pVM)), \
854	(rc))
855	#endif
856
857	/** @def VMCPU_ASSERT_EMT_RETURN
858	* Asserts that the current thread IS the emulation thread (EMT) and returns if it isn't.
859	*/
860	#ifdef IN_RC
861	# define VMCPU_ASSERT_EMT_RETURN(pVCpu, rc) AssertReturn(VMCPU_IS_EMT(pVCpu), (rc))
862	#elif defined(IN_RING0)
863	# define VMCPU_ASSERT_EMT_RETURN(pVCpu, rc) AssertReturn(VMCPU_IS_EMT(pVCpu), (rc))
864	#else
865	# define VMCPU_ASSERT_EMT_RETURN(pVCpu, rc) \
866	AssertMsgReturn(VMCPU_IS_EMT(pVCpu), \
867	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd idCpu=%#x\n", \
868	RTThreadNativeSelf(), (pVCpu)->hNativeThread, (pVCpu)->idCpu), \
869	(rc))
870	#endif
871
872	/** @def VMCPU_ASSERT_EMT_OR_GURU
873	* Asserts that the current thread IS the emulation thread (EMT) of the
874	* specified virtual CPU.
875	*/
876	#if defined(IN_RC) \|\| defined(IN_RING0)
877	# define VMCPU_ASSERT_EMT_OR_GURU(pVCpu) Assert( VMCPU_IS_EMT(pVCpu) \
878	\|\| pVCpu->CTX_SUFF(pVM)->enmVMState == VMSTATE_GURU_MEDITATION \
879	\|\| pVCpu->CTX_SUFF(pVM)->enmVMState == VMSTATE_GURU_MEDITATION_LS )
880	#else
881	# define VMCPU_ASSERT_EMT_OR_GURU(pVCpu) \
882	AssertMsg( VMCPU_IS_EMT(pVCpu) \
883	\|\| pVCpu->CTX_SUFF(pVM)->enmVMState == VMSTATE_GURU_MEDITATION \
884	\|\| pVCpu->CTX_SUFF(pVM)->enmVMState == VMSTATE_GURU_MEDITATION_LS, \
885	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd idCpu=%#x\n", \
886	RTThreadNativeSelf(), (pVCpu)->hNativeThread, (pVCpu)->idCpu))
887	#endif
888
889	/** @def VMCPU_ASSERT_EMT_OR_NOT_RUNNING
890	* Asserts that the current thread IS the emulation thread (EMT) of the
891	* specified virtual CPU or the VM is not running.
892	*/
893	#if defined(IN_RC) \|\| defined(IN_RING0)
894	# define VMCPU_ASSERT_EMT_OR_NOT_RUNNING(pVCpu) \
895	Assert( VMCPU_IS_EMT(pVCpu) \
896	\|\| !VM_IS_RUNNING_FOR_ASSERTIONS_ONLY((pVCpu)->CTX_SUFF(pVM)) )
897	#else
898	# define VMCPU_ASSERT_EMT_OR_NOT_RUNNING(pVCpu) \
899	AssertMsg( VMCPU_IS_EMT(pVCpu) \
900	\|\| !VM_IS_RUNNING_FOR_ASSERTIONS_ONLY((pVCpu)->CTX_SUFF(pVM)), \
901	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd idCpu=%#x\n", \
902	RTThreadNativeSelf(), (pVCpu)->hNativeThread, (pVCpu)->idCpu))
903	#endif
904
905	/** @def VMSTATE_IS_RUNNING
906	* Checks if the given state indicates a running VM.
907	*/
908	#define VMSTATE_IS_RUNNING(a_enmVMState) \
909	( (enmVMState) == VMSTATE_RUNNING \
910	\|\| (enmVMState) == VMSTATE_RUNNING_LS \
911	\|\| (enmVMState) == VMSTATE_RUNNING_FT )
912
913	/** @def VM_IS_RUNNING_FOR_ASSERTIONS_ONLY
914	* Checks if the VM is running.
915	* @note This is only for pure debug assertions. No AssertReturn or similar!
916	* @sa VMSTATE_IS_RUNNING
917	*/
918	#define VM_IS_RUNNING_FOR_ASSERTIONS_ONLY(pVM) \
919	( (pVM)->enmVMState == VMSTATE_RUNNING \
920	\|\| (pVM)->enmVMState == VMSTATE_RUNNING_LS \
921	\|\| (pVM)->enmVMState == VMSTATE_RUNNING_FT )
922
923	/** @def VM_ASSERT_IS_NOT_RUNNING
924	* Asserts that the VM is not running.
925	*/
926	#if defined(IN_RC) \|\| defined(IN_RING0)
927	#define VM_ASSERT_IS_NOT_RUNNING(pVM) Assert(!VM_IS_RUNNING_FOR_ASSERTIONS_ONLY(pVM))
928	#else
929	#define VM_ASSERT_IS_NOT_RUNNING(pVM) AssertMsg(!VM_IS_RUNNING_FOR_ASSERTIONS_ONLY(pVM), \
930	("VM is running. enmVMState=%d\n", (pVM)->enmVMState))
931	#endif
932
933	/** @def VM_ASSERT_EMT0
934	* Asserts that the current thread IS emulation thread \#0 (EMT0).
935	*/
936	#define VM_ASSERT_EMT0(pVM) VMCPU_ASSERT_EMT(&(pVM)->aCpus[0])
937
938	/** @def VM_ASSERT_EMT0_RETURN
939	* Asserts that the current thread IS emulation thread \#0 (EMT0) and returns if
940	* it isn't.
941	*/
942	#define VM_ASSERT_EMT0_RETURN(pVM, rc) VMCPU_ASSERT_EMT_RETURN(&(pVM)->aCpus[0], (rc))
943
944
945	/**
946	* Asserts that the current thread is NOT the emulation thread.
947	*/
948	#define VM_ASSERT_OTHER_THREAD(pVM) \
949	AssertMsg(!VM_IS_EMT(pVM), ("Not other thread!!\n"))
950
951
952	/** @def VM_ASSERT_STATE
953	* Asserts a certain VM state.
954	*/
955	#define VM_ASSERT_STATE(pVM, _enmState) \
956	AssertMsg((pVM)->enmVMState == (_enmState), \
957	("state %s, expected %s\n", VMGetStateName((pVM)->enmVMState), VMGetStateName(_enmState)))
958
959	/** @def VM_ASSERT_STATE_RETURN
960	* Asserts a certain VM state and returns if it doesn't match.
961	*/
962	#define VM_ASSERT_STATE_RETURN(pVM, _enmState, rc) \
963	AssertMsgReturn((pVM)->enmVMState == (_enmState), \
964	("state %s, expected %s\n", VMGetStateName((pVM)->enmVMState), VMGetStateName(_enmState)), \
965	(rc))
966
967	/** @def VM_IS_VALID_EXT
968	* Asserts a the VM handle is valid for external access, i.e. not being destroy
969	* or terminated. */
970	#define VM_IS_VALID_EXT(pVM) \
971	( RT_VALID_ALIGNED_PTR(pVM, PAGE_SIZE) \
972	&& ( (unsigned)(pVM)->enmVMState < (unsigned)VMSTATE_DESTROYING \
973	\|\| ( (unsigned)(pVM)->enmVMState == (unsigned)VMSTATE_DESTROYING \
974	&& VM_IS_EMT(pVM))) )
975
976	/** @def VM_ASSERT_VALID_EXT_RETURN
977	* Asserts a the VM handle is valid for external access, i.e. not being
978	* destroy or terminated.
979	*/
980	#define VM_ASSERT_VALID_EXT_RETURN(pVM, rc) \
981	AssertMsgReturn(VM_IS_VALID_EXT(pVM), \
982	("pVM=%p state %s\n", (pVM), RT_VALID_ALIGNED_PTR(pVM, PAGE_SIZE) \
983	? VMGetStateName(pVM->enmVMState) : ""), \
984	(rc))
985
986	/** @def VMCPU_ASSERT_VALID_EXT_RETURN
987	* Asserts a the VMCPU handle is valid for external access, i.e. not being
988	* destroy or terminated.
989	*/
990	#define VMCPU_ASSERT_VALID_EXT_RETURN(pVCpu, rc) \
991	AssertMsgReturn( RT_VALID_ALIGNED_PTR(pVCpu, 64) \
992	&& RT_VALID_ALIGNED_PTR((pVCpu)->CTX_SUFF(pVM), PAGE_SIZE) \
993	&& (unsigned)(pVCpu)->CTX_SUFF(pVM)->enmVMState < (unsigned)VMSTATE_DESTROYING, \
994	("pVCpu=%p pVM=%p state %s\n", (pVCpu), RT_VALID_ALIGNED_PTR(pVCpu, 64) ? (pVCpu)->CTX_SUFF(pVM) : NULL, \
995	RT_VALID_ALIGNED_PTR(pVCpu, 64) && RT_VALID_ALIGNED_PTR((pVCpu)->CTX_SUFF(pVM), PAGE_SIZE) \
996	? VMGetStateName((pVCpu)->pVMR3->enmVMState) : ""), \
997	(rc))
998
999	#endif /* !VBOX_FOR_DTRACE_LIB */
1000
1001
1002	/**
1003	* Helper that HM and NEM uses for safely modifying VM::bMainExecutionEngine.
1004	*
1005	* ONLY HM and NEM MAY USE THIS!
1006	*
1007	* @param a_pVM The cross context VM structure.
1008	* @param a_bValue The new value.
1009	* @internal
1010	*/
1011	#define VM_SET_MAIN_EXECUTION_ENGINE(a_pVM, a_bValue) \
1012	do { \
1013	const_cast<uint8_t >(&(a_pVM)->bMainExecutionEngine) = (a_bValue); \
1014	ASMCompilerBarrier(); /* just to be on the safe side */ \
1015	} while (0)
1016
1017	/**
1018	* Checks whether raw-mode is used.
1019	*
1020	* @retval true if either is used.
1021	* @retval false if software virtualization (raw-mode) is used.
1022	*
1023	* @param a_pVM The cross context VM structure.
1024	* @sa VM_IS_HM_OR_NEM_ENABLED, VM_IS_HM_ENABLED, VM_IS_NEM_ENABLED.
1025	* @internal
1026	*/
1027	#ifdef VBOX_WITH_RAW_MODE
1028	# define VM_IS_RAW_MODE_ENABLED(a_pVM) ((a_pVM)->bMainExecutionEngine == VM_EXEC_ENGINE_RAW_MODE)
1029	#else
1030	# define VM_IS_RAW_MODE_ENABLED(a_pVM) (false)
1031	#endif
1032
1033	/**
1034	* Checks whether HM (VT-x/AMD-V) or NEM is being used by this VM.
1035	*
1036	* @retval true if either is used.
1037	* @retval false if software virtualization (raw-mode) is used.
1038	*
1039	* @param a_pVM The cross context VM structure.
1040	* @sa VM_IS_RAW_MODE_ENABLED, VM_IS_HM_ENABLED, VM_IS_NEM_ENABLED.
1041	* @internal
1042	*/
1043	#define VM_IS_HM_OR_NEM_ENABLED(a_pVM) ((a_pVM)->bMainExecutionEngine != VM_EXEC_ENGINE_RAW_MODE)
1044
1045	/**
1046	* Checks whether HM is being used by this VM.
1047	*
1048	* @retval true if HM (VT-x/AMD-v) is used.
1049	* @retval false if not.
1050	*
1051	* @param a_pVM The cross context VM structure.
1052	* @sa VM_IS_NEM_ENABLED, VM_IS_RAW_MODE_ENABLED, VM_IS_HM_OR_NEM_ENABLED.
1053	* @internal
1054	*/
1055	#define VM_IS_HM_ENABLED(a_pVM) ((a_pVM)->bMainExecutionEngine == VM_EXEC_ENGINE_HW_VIRT)
1056
1057	/**
1058	* Checks whether NEM is being used by this VM.
1059	*
1060	* @retval true if a native hypervisor API is used.
1061	* @retval false if not.
1062	*
1063	* @param a_pVM The cross context VM structure.
1064	* @sa VM_IS_HM_ENABLED, VM_IS_RAW_MODE_ENABLED, VM_IS_HM_OR_NEM_ENABLED.
1065	* @internal
1066	*/
1067	#define VM_IS_NEM_ENABLED(a_pVM) ((a_pVM)->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API)
1068
1069
1070	/**
1071	* The cross context VM structure.
1072	*
1073	* It contains all the VM data which have to be available in all contexts.
1074	* Even if it contains all the data the idea is to use APIs not to modify all
1075	* the members all around the place. Therefore we make use of unions to hide
1076	* everything which isn't local to the current source module. This means we'll
1077	* have to pay a little bit of attention when adding new members to structures
1078	* in the unions and make sure to keep the padding sizes up to date.
1079	*
1080	* Run 'kmk run-struct-tests' (from src/VBox/VMM if you like) after updating!
1081	*/
1082	typedef struct VM
1083	{
1084	/** The state of the VM.
1085	* This field is read only to everyone except the VM and EM. */
1086	VMSTATE volatile enmVMState;
1087	/** Forced action flags.
1088	* See the VM_FF_* \#defines. Updated atomically.
1089	*/
1090	volatile uint32_t fGlobalForcedActions;
1091	/** Pointer to the array of page descriptors for the VM structure allocation. */
1092	R3PTRTYPE(PSUPPAGE) paVMPagesR3;
1093	/** Session handle. For use when calling SUPR0 APIs. */
1094	PSUPDRVSESSION pSession;
1095	/** Pointer to the ring-3 VM structure. */
1096	PUVM pUVM;
1097	/** Ring-3 Host Context VM Pointer. */
1098	R3PTRTYPE(struct VM *) pVMR3;
1099	/** Ring-0 Host Context VM Pointer. */
1100	R0PTRTYPE(struct VM *) pVMR0;
1101	/** Raw-mode Context VM Pointer. */
1102	RCPTRTYPE(struct VM *) pVMRC;
1103
1104	/** The GVM VM handle. Only the GVM should modify this field. */
1105	uint32_t hSelf;
1106	/** Number of virtual CPUs. */
1107	uint32_t cCpus;
1108	/** CPU excution cap (1-100) */
1109	uint32_t uCpuExecutionCap;
1110
1111	/** Size of the VM structure including the VMCPU array. */
1112	uint32_t cbSelf;
1113
1114	/** Offset to the VMCPU array starting from beginning of this structure. */
1115	uint32_t offVMCPU;
1116
1117	/**
1118	* VMMSwitcher assembly entry point returning to host context.
1119	*
1120	* Depending on how the host handles the rc status given in @a eax, this may
1121	* return and let the caller resume whatever it was doing prior to the call.
1122	*
1123	*
1124	* @param eax The return code, register.
1125	* @remark Assume interrupts disabled.
1126	* @remark This method pointer lives here because TRPM needs it.
1127	*/
1128	RTRCPTR pfnVMMRCToHostAsm/(int32_t eax)/;
1129
1130	/**
1131	* VMMSwitcher assembly entry point returning to host context without saving the
1132	* raw-mode context (hyper) registers.
1133	*
1134	* Unlike pfnVMMRC2HCAsm, this will not return to the caller. Instead it
1135	* expects the caller to save a RC context in CPUM where one might return if the
1136	* return code indicate that this is possible.
1137	*
1138	* This method pointer lives here because TRPM needs it.
1139	*
1140	* @param eax The return code, register.
1141	* @remark Assume interrupts disabled.
1142	* @remark This method pointer lives here because TRPM needs it.
1143	*/
1144	RTRCPTR pfnVMMRCToHostAsmNoReturn/(int32_t eax)/;
1145
1146	/** @name Various items that are frequently accessed.
1147	* @{ */
1148	/** The main execution engine, VM_EXEC_ENGINE_XXX.
1149	* This is set early during vmR3InitRing3 by HM or NEM. */
1150	uint8_t const bMainExecutionEngine;
1151
1152	/** Whether to recompile user mode code or run it raw/hm/nem.
1153	* In non-raw-mode both fRecompileUser and fRecompileSupervisor must be set
1154	* to recompiler stuff. */
1155	bool fRecompileUser;
1156	/** Whether to recompile supervisor mode code or run it raw/hm/nem.
1157	* In non-raw-mode both fRecompileUser and fRecompileSupervisor must be set
1158	* to recompiler stuff. */
1159	bool fRecompileSupervisor;
1160	/** Whether raw mode supports ring-1 code or not.
1161	* This will be cleared when not in raw-mode. */
1162	bool fRawRing1Enabled;
1163	/** PATM enabled flag.
1164	* This is placed here for performance reasons.
1165	* This will be cleared when not in raw-mode. */
1166	bool fPATMEnabled;
1167	/** CSAM enabled flag.
1168	* This is placed here for performance reasons.
1169	* This will be cleared when not in raw-mode. */
1170	bool fCSAMEnabled;
1171
1172	/** Hardware VM support is available and enabled.
1173	* Determined very early during init.
1174	* This is placed here for performance reasons.
1175	* @todo obsoleted by bMainExecutionEngine, eliminate. */
1176	bool fHMEnabled;
1177	/** Hardware VM support requires a minimal raw-mode context.
1178	* This is never set on 64-bit hosts, only 32-bit hosts requires it. */
1179	bool fHMNeedRawModeCtx;
1180
1181	/** Set when this VM is the master FT node.
1182	* @todo This doesn't need to be here, FTM should store it in it's own
1183	* structures instead. */
1184	bool fFaultTolerantMaster;
1185	/** Large page enabled flag.
1186	* @todo This doesn't need to be here, PGM should store it in it's own
1187	* structures instead. */
1188	bool fUseLargePages;
1189	/** @} */
1190
1191	/** Alignment padding. */
1192	uint8_t uPadding1[2];
1193
1194	/** @name Debugging
1195	* @{ */
1196	/** Raw-mode Context VM Pointer. */
1197	RCPTRTYPE(RTTRACEBUF) hTraceBufRC;
1198	/** Ring-3 Host Context VM Pointer. */
1199	R3PTRTYPE(RTTRACEBUF) hTraceBufR3;
1200	/** Ring-0 Host Context VM Pointer. */
1201	R0PTRTYPE(RTTRACEBUF) hTraceBufR0;
1202	/** @} */
1203
1204	#if HC_ARCH_BITS == 32
1205	/** Alignment padding. */
1206	uint32_t uPadding2;
1207	#endif
1208
1209	/** @name Switcher statistics (remove)
1210	* @{ */
1211	/** Profiling the total time from Qemu to GC. */
1212	STAMPROFILEADV StatTotalQemuToGC;
1213	/** Profiling the total time from GC to Qemu. */
1214	STAMPROFILEADV StatTotalGCToQemu;
1215	/** Profiling the total time spent in GC. */
1216	STAMPROFILEADV StatTotalInGC;
1217	/** Profiling the total time spent not in Qemu. */
1218	STAMPROFILEADV StatTotalInQemu;
1219	/** Profiling the VMMSwitcher code for going to GC. */
1220	STAMPROFILEADV StatSwitcherToGC;
1221	/** Profiling the VMMSwitcher code for going to HC. */
1222	STAMPROFILEADV StatSwitcherToHC;
1223	STAMPROFILEADV StatSwitcherSaveRegs;
1224	STAMPROFILEADV StatSwitcherSysEnter;
1225	STAMPROFILEADV StatSwitcherDebug;
1226	STAMPROFILEADV StatSwitcherCR0;
1227	STAMPROFILEADV StatSwitcherCR4;
1228	STAMPROFILEADV StatSwitcherJmpCR3;
1229	STAMPROFILEADV StatSwitcherRstrRegs;
1230	STAMPROFILEADV StatSwitcherLgdt;
1231	STAMPROFILEADV StatSwitcherLidt;
1232	STAMPROFILEADV StatSwitcherLldt;
1233	STAMPROFILEADV StatSwitcherTSS;
1234	/** @} */
1235
1236	/** Padding - the unions must be aligned on a 64 bytes boundary and the unions
1237	* must start at the same offset on both 64-bit and 32-bit hosts. */
1238	uint8_t abAlignment3[(HC_ARCH_BITS == 32 ? 24 : 0) + 40];
1239
1240	/** CPUM part. */
1241	union
1242	{
1243	#ifdef ___CPUMInternal_h
1244	struct CPUM s;
1245	#endif
1246	#ifdef ___VBox_vmm_cpum_h
1247	/** Read only info exposed about the host and guest CPUs. */
1248	struct
1249	{
1250	/** Padding for hidden fields. */
1251	uint8_t abHidden0[64];
1252	/** Host CPU feature information. */
1253	CPUMFEATURES HostFeatures;
1254	/** Guest CPU feature information. */
1255	CPUMFEATURES GuestFeatures;
1256	} const ro;
1257	#endif
1258	uint8_t padding[1536]; /* multiple of 64 */
1259	} cpum;
1260
1261	/** VMM part. */
1262	union
1263	{
1264	#ifdef ___VMMInternal_h
1265	struct VMM s;
1266	#endif
1267	uint8_t padding[1600]; /* multiple of 64 */
1268	} vmm;
1269
1270	/** PGM part. */
1271	union
1272	{
1273	#ifdef ___PGMInternal_h
1274	struct PGM s;
1275	#endif
1276	uint8_t padding[40962+6080]; / multiple of 64 */
1277	} pgm;
1278
1279	/** HM part. */
1280	union
1281	{
1282	#ifdef ___HMInternal_h
1283	struct HM s;
1284	#endif
1285	uint8_t padding[5440]; /* multiple of 64 */
1286	} hm;
1287
1288	/** TRPM part. */
1289	union
1290	{
1291	#ifdef ___TRPMInternal_h
1292	struct TRPM s;
1293	#endif
1294	uint8_t padding[5248]; /* multiple of 64 */
1295	} trpm;
1296
1297	/** SELM part. */
1298	union
1299	{
1300	#ifdef ___SELMInternal_h
1301	struct SELM s;
1302	#endif
1303	uint8_t padding[768]; /* multiple of 64 */
1304	} selm;
1305
1306	/** MM part. */
1307	union
1308	{
1309	#ifdef ___MMInternal_h
1310	struct MM s;
1311	#endif
1312	uint8_t padding[192]; /* multiple of 64 */
1313	} mm;
1314
1315	/** PDM part. */
1316	union
1317	{
1318	#ifdef ___PDMInternal_h
1319	struct PDM s;
1320	#endif
1321	uint8_t padding[1920]; /* multiple of 64 */
1322	} pdm;
1323
1324	/** IOM part. */
1325	union
1326	{
1327	#ifdef ___IOMInternal_h
1328	struct IOM s;
1329	#endif
1330	uint8_t padding[896]; /* multiple of 64 */
1331	} iom;
1332
1333	/** EM part. */
1334	union
1335	{
1336	#ifdef ___EMInternal_h
1337	struct EM s;
1338	#endif
1339	uint8_t padding[256]; /* multiple of 64 */
1340	} em;
1341
1342	/** NEM part. */
1343	union
1344	{
1345	#ifdef ___NEMInternal_h
1346	struct NEM s;
1347	#endif
1348	uint8_t padding[128]; /* multiple of 64 */
1349	} nem;
1350
1351	/** TM part. */
1352	union
1353	{
1354	#ifdef ___TMInternal_h
1355	struct TM s;
1356	#endif
1357	uint8_t padding[2496]; /* multiple of 64 */
1358	} tm;
1359
1360	/** DBGF part. */
1361	union
1362	{
1363	#ifdef ___DBGFInternal_h
1364	struct DBGF s;
1365	#endif
1366	#ifdef ___VBox_vmm_dbgf_h
1367	/** Read only info exposed about interrupt breakpoints and selected events. */
1368	struct
1369	{
1370	/** Bitmap of enabled hardware interrupt breakpoints. */
1371	uint32_t bmHardIntBreakpoints[256 / 32];
1372	/** Bitmap of enabled software interrupt breakpoints. */
1373	uint32_t bmSoftIntBreakpoints[256 / 32];
1374	/** Bitmap of selected events.
1375	* This includes non-selectable events too for simplicity, we maintain the
1376	* state for some of these, as it may come in handy. */
1377	uint64_t bmSelectedEvents[(DBGFEVENT_END + 63) / 64];
1378	/** Enabled hardware interrupt breakpoints. */
1379	uint32_t cHardIntBreakpoints;
1380	/** Enabled software interrupt breakpoints. */
1381	uint32_t cSoftIntBreakpoints;
1382	/** The number of selected events. */
1383	uint32_t cSelectedEvents;
1384	/** The number of enabled hardware breakpoints. */
1385	uint8_t cEnabledHwBreakpoints;
1386	/** The number of enabled hardware I/O breakpoints. */
1387	uint8_t cEnabledHwIoBreakpoints;
1388	/** The number of enabled INT3 breakpoints. */
1389	uint8_t cEnabledInt3Breakpoints;
1390	uint8_t abPadding[1]; /*< Unused padding space up for grabs. /
1391	} const ro;
1392	#endif
1393	uint8_t padding[2432]; /* multiple of 64 */
1394	} dbgf;
1395
1396	/** SSM part. */
1397	union
1398	{
1399	#ifdef ___SSMInternal_h
1400	struct SSM s;
1401	#endif
1402	uint8_t padding[128]; /* multiple of 64 */
1403	} ssm;
1404
1405	/** FTM part. */
1406	union
1407	{
1408	#ifdef ___FTMInternal_h
1409	struct FTM s;
1410	#endif
1411	uint8_t padding[512]; /* multiple of 64 */
1412	} ftm;
1413
1414	#ifdef VBOX_WITH_RAW_MODE
1415	/** PATM part. */
1416	union
1417	{
1418	# ifdef ___PATMInternal_h
1419	struct PATM s;
1420	# endif
1421	uint8_t padding[768]; /* multiple of 64 */
1422	} patm;
1423
1424	/** CSAM part. */
1425	union
1426	{
1427	# ifdef ___CSAMInternal_h
1428	struct CSAM s;
1429	# endif
1430	uint8_t padding[1088]; /* multiple of 64 */
1431	} csam;
1432	#endif
1433
1434	#ifdef VBOX_WITH_REM
1435	/** REM part. */
1436	union
1437	{
1438	# ifdef ___REMInternal_h
1439	struct REM s;
1440	# endif
1441	uint8_t padding[0x11100]; /* multiple of 64 */
1442	} rem;
1443	#endif
1444
1445	union
1446	{
1447	#ifdef ___GIMInternal_h
1448	struct GIM s;
1449	#endif
1450	uint8_t padding[448]; /* multiple of 64 */
1451	} gim;
1452
1453	union
1454	{
1455	#ifdef ___APICInternal_h
1456	struct APIC s;
1457	#endif
1458	uint8_t padding[128]; /* multiple of 8 */
1459	} apic;
1460
1461	/* ---- begin small stuff ---- */
1462
1463	/** VM part. */
1464	union
1465	{
1466	#ifdef ___VMInternal_h
1467	struct VMINT s;
1468	#endif
1469	uint8_t padding[32]; /* multiple of 8 */
1470	} vm;
1471
1472	/** CFGM part. */
1473	union
1474	{
1475	#ifdef ___CFGMInternal_h
1476	struct CFGM s;
1477	#endif
1478	uint8_t padding[8]; /* multiple of 8 */
1479	} cfgm;
1480
1481	/** Padding for aligning the cpu array on a page boundary. */
1482	#if defined(VBOX_WITH_REM) && defined(VBOX_WITH_RAW_MODE)
1483	uint8_t abAlignment2[3670];
1484	#elif defined(VBOX_WITH_REM) && !defined(VBOX_WITH_RAW_MODE)
1485	uint8_t abAlignment2[1430];
1486	#elif !defined(VBOX_WITH_REM) && defined(VBOX_WITH_RAW_MODE)
1487	uint8_t abAlignment2[3926];
1488	#else
1489	uint8_t abAlignment2[1686];
1490	#endif
1491
1492	/* ---- end small stuff ---- */
1493
1494	/** VMCPU array for the configured number of virtual CPUs.
1495	* Must be aligned on a page boundary for TLB hit reasons as well as
1496	* alignment of VMCPU members. */
1497	VMCPU aCpus[1];
1498	} VM;
1499
1500
1501	#ifdef IN_RC
1502	RT_C_DECLS_BEGIN
1503
1504	/** The VM structure.
1505	* This is imported from the VMMRCBuiltin module, i.e. it's a one of those magic
1506	* globals which we should avoid using.
1507	*/
1508	extern DECLIMPORT(VM) g_VM;
1509
1510	RT_C_DECLS_END
1511	#endif
1512
1513	/** @} */
1514
1515	#endif
1516

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source: vbox/trunk/include/VBox/vmm/vm.h@ 74794

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