vm.h@ 74796

Last change on this file since 74796 was 74796, checked in by vboxsync, 6 years ago
vm.h: Made the FF_IS_SET macros only take constants with _BIT variants. bugref:9180
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 58.8 KB

Line
1	/** @file
2	* VM - The Virtual Machine, data.
3	*/
4
5	/*
6	* Copyright (C) 2006-2017 Oracle Corporation
7	*
8	* This file is part of VirtualBox Open Source Edition (OSE), as
9	* available from http://www.virtualbox.org. This file is free software;
10	* you can redistribute it and/or modify it under the terms of the GNU
11	* General Public License (GPL) as published by the Free Software
12	* Foundation, in version 2 as it comes in the "COPYING" file of the
13	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15	*
16	* The contents of this file may alternatively be used under the terms
17	* of the Common Development and Distribution License Version 1.0
18	* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19	* VirtualBox OSE distribution, in which case the provisions of the
20	* CDDL are applicable instead of those of the GPL.
21	*
22	* You may elect to license modified versions of this file under the
23	* terms and conditions of either the GPL or the CDDL or both.
24	*/
25
26	#ifndef ___VBox_vmm_vm_h
27	#define ___VBox_vmm_vm_h
28
29	#ifndef VBOX_FOR_DTRACE_LIB
30	# include <iprt/param.h>
31	# include <VBox/types.h>
32	# include <VBox/vmm/cpum.h>
33	# include <VBox/vmm/stam.h>
34	# include <VBox/vmm/vmapi.h>
35	# include <VBox/vmm/vmm.h>
36	# include <VBox/sup.h>
37	#else
38	# pragma D depends_on library vbox-types.d
39	# pragma D depends_on library CPUMInternal.d
40	# define ___CPUMInternal_h
41	#endif
42
43
44
45	/** @defgroup grp_vm The Virtual Machine
46	* @ingroup grp_vmm
47	* @{
48	*/
49
50	/**
51	* The state of a Virtual CPU.
52	*
53	* The basic state indicated here is whether the CPU has been started or not. In
54	* addition, there are sub-states when started for assisting scheduling (GVMM
55	* mostly).
56	*
57	* The transition out of the STOPPED state is done by a vmR3PowerOn.
58	* The transition back to the STOPPED state is done by vmR3PowerOff.
59	*
60	* (Alternatively we could let vmR3PowerOn start CPU 0 only and let the SPIP
61	* handling switch on the other CPUs. Then vmR3Reset would stop all but CPU 0.)
62	*/
63	typedef enum VMCPUSTATE
64	{
65	/** The customary invalid zero. */
66	VMCPUSTATE_INVALID = 0,
67
68	/** Virtual CPU has not yet been started. */
69	VMCPUSTATE_STOPPED,
70
71	/** CPU started. */
72	VMCPUSTATE_STARTED,
73	/** CPU started in HM context. */
74	VMCPUSTATE_STARTED_HM,
75	/** Executing guest code and can be poked (RC or STI bits of HM). */
76	VMCPUSTATE_STARTED_EXEC,
77	/** Executing guest code in the recompiler. */
78	VMCPUSTATE_STARTED_EXEC_REM,
79	/** Executing guest code using NEM. */
80	VMCPUSTATE_STARTED_EXEC_NEM,
81	VMCPUSTATE_STARTED_EXEC_NEM_WAIT,
82	VMCPUSTATE_STARTED_EXEC_NEM_CANCELED,
83	/** Halted. */
84	VMCPUSTATE_STARTED_HALTED,
85
86	/** The end of valid virtual CPU states. */
87	VMCPUSTATE_END,
88
89	/** Ensure 32-bit type. */
90	VMCPUSTATE_32BIT_HACK = 0x7fffffff
91	} VMCPUSTATE;
92
93
94	/**
95	* The cross context virtual CPU structure.
96	*
97	* Run 'kmk run-struct-tests' (from src/VBox/VMM if you like) after updating!
98	*/
99	typedef struct VMCPU
100	{
101	/** Per CPU forced action.
102	* See the VMCPU_FF_* \#defines. Updated atomically. */
103	uint32_t volatile fLocalForcedActions; /* 0 */
104	/** The CPU state. */
105	VMCPUSTATE volatile enmState; /* 4 */
106
107	/** Pointer to the ring-3 UVMCPU structure. */
108	PUVMCPU pUVCpu; /* 8 */
109	/** Ring-3 Host Context VM Pointer. */
110	PVMR3 pVMR3; /* 16 / 12 */
111	/** Ring-0 Host Context VM Pointer. */
112	PVMR0 pVMR0; /* 24 / 16 */
113	/** Raw-mode Context VM Pointer. */
114	PVMRC pVMRC; /* 32 / 20 */
115	/** The CPU ID.
116	* This is the index into the VM::aCpu array. */
117	VMCPUID idCpu; /* 36 / 24 */
118	/** The native thread handle. */
119	RTNATIVETHREAD hNativeThread; /* 40 / 28 */
120	/** The native R0 thread handle. (different from the R3 handle!) */
121	RTNATIVETHREAD hNativeThreadR0; /* 48 / 32 */
122	/** Which host CPU ID is this EMT running on.
123	* Only valid when in RC or HMR0 with scheduling disabled. */
124	RTCPUID volatile idHostCpu; /* 56 / 36 */
125	/** The CPU set index corresponding to idHostCpu, UINT32_MAX if not valid.
126	* @remarks Best to make sure iHostCpuSet shares cache line with idHostCpu! */
127	uint32_t volatile iHostCpuSet; /* 60 / 40 */
128
129	#if HC_ARCH_BITS == 32
130	/** Align the structures below bit on a 64-byte boundary and make sure it starts
131	* at the same offset in both 64-bit and 32-bit builds.
132	*
133	* @remarks The alignments of the members that are larger than 48 bytes should be
134	* 64-byte for cache line reasons. structs containing small amounts of
135	* data could be lumped together at the end with a < 64 byte padding
136	* following it (to grow into and align the struct size).
137	*/
138	uint8_t abAlignment1[HC_ARCH_BITS == 64 ? 0 : 20];
139	#endif
140
141	/** IEM part.
142	* @remarks This comes first as it allows the use of 8-bit immediates for the
143	* first 64 bytes of the structure, reducing code size a wee bit. */
144	#ifdef ___IEMInternal_h /* For PDB hacking. */
145	union VMCPUUNIONIEMFULL
146	#else
147	union VMCPUUNIONIEMSTUB
148	#endif
149	{
150	#ifdef ___IEMInternal_h
151	struct IEMCPU s;
152	#endif
153	uint8_t padding[18496]; /* multiple of 64 */
154	} iem;
155
156	/** HM part. */
157	union VMCPUUNIONHM
158	{
159	#ifdef ___HMInternal_h
160	struct HMCPU s;
161	#endif
162	uint8_t padding[5888]; /* multiple of 64 */
163	} hm;
164
165	/** NEM part. */
166	union VMCPUUNIONNEM
167	{
168	#ifdef ___NEMInternal_h
169	struct NEMCPU s;
170	#endif
171	uint8_t padding[512]; /* multiple of 64 */
172	} nem;
173
174	/** TRPM part. */
175	union VMCPUUNIONTRPM
176	{
177	#ifdef ___TRPMInternal_h
178	struct TRPMCPU s;
179	#endif
180	uint8_t padding[128]; /* multiple of 64 */
181	} trpm;
182
183	/** TM part. */
184	union VMCPUUNIONTM
185	{
186	#ifdef ___TMInternal_h
187	struct TMCPU s;
188	#endif
189	uint8_t padding[384]; /* multiple of 64 */
190	} tm;
191
192	/** VMM part. */
193	union VMCPUUNIONVMM
194	{
195	#ifdef ___VMMInternal_h
196	struct VMMCPU s;
197	#endif
198	uint8_t padding[768]; /* multiple of 64 */
199	} vmm;
200
201	/** PDM part. */
202	union VMCPUUNIONPDM
203	{
204	#ifdef ___PDMInternal_h
205	struct PDMCPU s;
206	#endif
207	uint8_t padding[256]; /* multiple of 64 */
208	} pdm;
209
210	/** IOM part. */
211	union VMCPUUNIONIOM
212	{
213	#ifdef ___IOMInternal_h
214	struct IOMCPU s;
215	#endif
216	uint8_t padding[512]; /* multiple of 64 */
217	} iom;
218
219	/** DBGF part.
220	* @todo Combine this with other tiny structures. */
221	union VMCPUUNIONDBGF
222	{
223	#ifdef ___DBGFInternal_h
224	struct DBGFCPU s;
225	#endif
226	uint8_t padding[256]; /* multiple of 64 */
227	} dbgf;
228
229	/** GIM part. */
230	union VMCPUUNIONGIM
231	{
232	#ifdef ___GIMInternal_h
233	struct GIMCPU s;
234	#endif
235	uint8_t padding[512]; /* multiple of 64 */
236	} gim;
237
238	/** APIC part. */
239	union VMCPUUNIONAPIC
240	{
241	#ifdef ___APICInternal_h
242	struct APICCPU s;
243	#endif
244	uint8_t padding[1792]; /* multiple of 64 */
245	} apic;
246
247	/*
248	* Some less frequently used global members that doesn't need to take up
249	* precious space at the head of the structure.
250	*/
251
252	/** Trace groups enable flags. */
253	uint32_t fTraceGroups; /* 64 / 44 */
254	/** State data for use by ad hoc profiling. */
255	uint32_t uAdHoc;
256	/** Profiling samples for use by ad hoc profiling. */
257	STAMPROFILEADV aStatAdHoc[8]; /* size: 408 = 320 /
258
259	/** Align the following members on page boundary. */
260	uint8_t abAlignment2[2872];
261
262	/** PGM part. */
263	union VMCPUUNIONPGM
264	{
265	#ifdef ___PGMInternal_h
266	struct PGMCPU s;
267	#endif
268	uint8_t padding[4096]; /* multiple of 4096 */
269	} pgm;
270
271	/** CPUM part. */
272	union VMCPUUNIONCPUM
273	{
274	#ifdef ___CPUMInternal_h
275	struct CPUMCPU s;
276	#endif
277	#ifdef VMCPU_INCL_CPUM_GST_CTX
278	/** The guest CPUM context for direct use by execution engines.
279	* This is not for general consumption, but for HM, REM, IEM, and maybe a few
280	* others. The rest will use the function based CPUM API. */
281	CPUMCTX GstCtx;
282	#endif
283	uint8_t padding[4096]; /* multiple of 4096 */
284	} cpum;
285
286	/** EM part. */
287	union VMCPUUNIONEM
288	{
289	#ifdef ___EMInternal_h
290	struct EMCPU s;
291	#endif
292	uint8_t padding[40960]; /* multiple of 4096 */
293	} em;
294	} VMCPU;
295
296
297	#ifndef VBOX_FOR_DTRACE_LIB
298
299	/** @name Operations on VMCPU::enmState
300	* @{ */
301	/** Gets the VMCPU state. */
302	#define VMCPU_GET_STATE(pVCpu) ( (pVCpu)->enmState )
303	/** Sets the VMCPU state. */
304	#define VMCPU_SET_STATE(pVCpu, enmNewState) \
305	ASMAtomicWriteU32((uint32_t volatile *)&(pVCpu)->enmState, (enmNewState))
306	/** Cmpares and sets the VMCPU state. */
307	#define VMCPU_CMPXCHG_STATE(pVCpu, enmNewState, enmOldState) \
308	ASMAtomicCmpXchgU32((uint32_t volatile *)&(pVCpu)->enmState, (enmNewState), (enmOldState))
309	/** Checks the VMCPU state. */
310	#ifdef VBOX_STRICT
311	# define VMCPU_ASSERT_STATE(pVCpu, enmExpectedState) \
312	do { \
313	VMCPUSTATE enmState = VMCPU_GET_STATE(pVCpu); \
314	AssertMsg(enmState == (enmExpectedState), \
315	("enmState=%d enmExpectedState=%d idCpu=%u\n", \
316	enmState, enmExpectedState, (pVCpu)->idCpu)); \
317	} while (0)
318	#else
319	# define VMCPU_ASSERT_STATE(pVCpu, enmExpectedState) do { } while (0)
320	#endif
321	/** Tests if the state means that the CPU is started. */
322	#define VMCPUSTATE_IS_STARTED(enmState) ( (enmState) > VMCPUSTATE_STOPPED )
323	/** Tests if the state means that the CPU is stopped. */
324	#define VMCPUSTATE_IS_STOPPED(enmState) ( (enmState) == VMCPUSTATE_STOPPED )
325	/** @} */
326
327
328	/** The name of the raw-mode context VMM Core module. */
329	#define VMMRC_MAIN_MODULE_NAME "VMMRC.rc"
330	/** The name of the ring-0 context VMM Core module. */
331	#define VMMR0_MAIN_MODULE_NAME "VMMR0.r0"
332
333	/**
334	* Wrapper macro for avoiding too much \#ifdef VBOX_WITH_RAW_MODE.
335	*/
336	#ifdef VBOX_WITH_RAW_MODE
337	# define VM_WHEN_RAW_MODE(a_WithExpr, a_WithoutExpr) a_WithExpr
338	#else
339	# define VM_WHEN_RAW_MODE(a_WithExpr, a_WithoutExpr) a_WithoutExpr
340	#endif
341
342
343	/** VM Forced Action Flags.
344	*
345	* Use the VM_FF_SET() and VM_FF_CLEAR() macros to change the force
346	* action mask of a VM.
347	*
348	* Available VM bits:
349	* 0, 1, 5, 6, 7, 13, 14, 15, 16, 17, 21, 22, 23, 24, 25, 26, 27, 28, 30
350	*
351	*
352	* Available VMCPU bits:
353	* 14, 15
354	*
355	* @todo If we run low on VMCPU, we may consider merging the SELM bits
356	*
357	* @{
358	*/
359	/** The virtual sync clock has been stopped, go to TM until it has been
360	* restarted... */
361	#define VM_FF_TM_VIRTUAL_SYNC RT_BIT_32(VM_FF_TM_VIRTUAL_SYNC_BIT)
362	#define VM_FF_TM_VIRTUAL_SYNC_BIT 2
363	/** PDM Queues are pending. */
364	#define VM_FF_PDM_QUEUES RT_BIT_32(VM_FF_PDM_QUEUES_BIT)
365	/** The bit number for VM_FF_PDM_QUEUES. */
366	#define VM_FF_PDM_QUEUES_BIT 3
367	/** PDM DMA transfers are pending. */
368	#define VM_FF_PDM_DMA RT_BIT_32(VM_FF_PDM_DMA_BIT)
369	/** The bit number for VM_FF_PDM_DMA. */
370	#define VM_FF_PDM_DMA_BIT 4
371	/** This action forces the VM to call DBGF so DBGF can service debugger
372	* requests in the emulation thread.
373	* This action flag stays asserted till DBGF clears it.*/
374	#define VM_FF_DBGF RT_BIT_32(VM_FF_DBGF_BIT)
375	/** The bit number for VM_FF_DBGF. */
376	#define VM_FF_DBGF_BIT 8
377	/** This action forces the VM to service pending requests from other
378	* thread or requests which must be executed in another context. */
379	#define VM_FF_REQUEST RT_BIT_32(VM_FF_REQUEST_BIT)
380	#define VM_FF_REQUEST_BIT 9
381	/** Check for VM state changes and take appropriate action. */
382	#define VM_FF_CHECK_VM_STATE RT_BIT_32(VM_FF_CHECK_VM_STATE_BIT)
383	/** The bit number for VM_FF_CHECK_VM_STATE. */
384	#define VM_FF_CHECK_VM_STATE_BIT 10
385	/** Reset the VM. (postponed) */
386	#define VM_FF_RESET RT_BIT_32(VM_FF_RESET_BIT)
387	/** The bit number for VM_FF_RESET. */
388	#define VM_FF_RESET_BIT 11
389	/** EMT rendezvous in VMM. */
390	#define VM_FF_EMT_RENDEZVOUS RT_BIT_32(VM_FF_EMT_RENDEZVOUS_BIT)
391	/** The bit number for VM_FF_EMT_RENDEZVOUS. */
392	#define VM_FF_EMT_RENDEZVOUS_BIT 12
393
394	/** PGM needs to allocate handy pages. */
395	#define VM_FF_PGM_NEED_HANDY_PAGES RT_BIT_32(VM_FF_PGM_NEED_HANDY_PAGES_BIT)
396	#define VM_FF_PGM_NEED_HANDY_PAGES_BIT 18
397	/** PGM is out of memory.
398	* Abandon all loops and code paths which can be resumed and get up to the EM
399	* loops. */
400	#define VM_FF_PGM_NO_MEMORY RT_BIT_32(VM_FF_PGM_NO_MEMORY_BIT)
401	#define VM_FF_PGM_NO_MEMORY_BIT 19
402	/** PGM is about to perform a lightweight pool flush
403	* Guest SMP: all EMT threads should return to ring 3
404	*/
405	#define VM_FF_PGM_POOL_FLUSH_PENDING RT_BIT_32(VM_FF_PGM_POOL_FLUSH_PENDING_BIT)
406	#define VM_FF_PGM_POOL_FLUSH_PENDING_BIT 20
407	/** REM needs to be informed about handler changes. */
408	#define VM_FF_REM_HANDLER_NOTIFY RT_BIT_32(VM_FF_REM_HANDLER_NOTIFY_BIT)
409	/** The bit number for VM_FF_REM_HANDLER_NOTIFY. */
410	#define VM_FF_REM_HANDLER_NOTIFY_BIT 29
411	/** Suspend the VM - debug only. */
412	#define VM_FF_DEBUG_SUSPEND RT_BIT_32(VM_FF_DEBUG_SUSPEND_BIT)
413	#define VM_FF_DEBUG_SUSPEND_BIT 31
414
415
416	/** This action forces the VM to check any pending interrupts on the APIC. */
417	#define VMCPU_FF_INTERRUPT_APIC RT_BIT_32(VMCPU_FF_INTERRUPT_APIC_BIT)
418	#define VMCPU_FF_INTERRUPT_APIC_BIT 0
419	/** This action forces the VM to check any pending interrups on the PIC. */
420	#define VMCPU_FF_INTERRUPT_PIC RT_BIT_32(VMCPU_FF_INTERRUPT_PIC_BIT)
421	#define VMCPU_FF_INTERRUPT_PIC_BIT 1
422	/** This action forces the VM to schedule and run pending timer (TM).
423	* @remarks Don't move - PATM compatibility. */
424	#define VMCPU_FF_TIMER RT_BIT_32(VMCPU_FF_TIMER_BIT)
425	#define VMCPU_FF_TIMER_BIT 2
426	/** This action forces the VM to check any pending NMIs. */
427	#define VMCPU_FF_INTERRUPT_NMI RT_BIT_32(VMCPU_FF_INTERRUPT_NMI_BIT)
428	#define VMCPU_FF_INTERRUPT_NMI_BIT 3
429	/** This action forces the VM to check any pending SMIs. */
430	#define VMCPU_FF_INTERRUPT_SMI RT_BIT_32(VMCPU_FF_INTERRUPT_SMI_BIT)
431	#define VMCPU_FF_INTERRUPT_SMI_BIT 4
432	/** PDM critical section unlocking is pending, process promptly upon return to R3. */
433	#define VMCPU_FF_PDM_CRITSECT RT_BIT_32(VMCPU_FF_PDM_CRITSECT_BIT)
434	#define VMCPU_FF_PDM_CRITSECT_BIT 5
435	/** Special EM internal force flag that is used by EMUnhaltAndWakeUp() to force
436	* the virtual CPU out of the next (/current) halted state. It is not processed
437	* nor cleared by emR3ForcedActions (similar to VMCPU_FF_BLOCK_NMIS), instead it
438	* is cleared the next time EM leaves the HALTED state. */
439	#define VMCPU_FF_UNHALT RT_BIT_32(VMCPU_FF_UNHALT_BIT)
440	#define VMCPU_FF_UNHALT_BIT 6
441	/** Pending IEM action (mask). */
442	#define VMCPU_FF_IEM RT_BIT_32(VMCPU_FF_IEM_BIT)
443	/** Pending IEM action (bit number). */
444	#define VMCPU_FF_IEM_BIT 7
445	/** Pending APIC action (bit number). */
446	#define VMCPU_FF_UPDATE_APIC_BIT 8
447	/** This action forces the VM to update APIC's asynchronously arrived
448	* interrupts as pending interrupts. */
449	#define VMCPU_FF_UPDATE_APIC RT_BIT_32(VMCPU_FF_UPDATE_APIC_BIT)
450	/** This action forces the VM to service pending requests from other
451	* thread or requests which must be executed in another context. */
452	#define VMCPU_FF_REQUEST RT_BIT_32(VMCPU_FF_REQUEST_BIT)
453	#define VMCPU_FF_REQUEST_BIT 9
454	/** Pending DBGF event (alternative to passing VINF_EM_DBG_EVENT around). */
455	#define VMCPU_FF_DBGF RT_BIT_32(VMCPU_FF_DBGF_BIT)
456	/** The bit number for VMCPU_FF_DBGF. */
457	#define VMCPU_FF_DBGF_BIT 10
458	/** Pending MTF (Monitor Trap Flag) event - Intel only. */
459	#define VMCPU_FF_MTF RT_BIT_32(VMCPU_FF_MTF_BIT)
460	/** The bit number for VMCPU_FF_MTF. */
461	#define VMCPU_FF_MTF_BIT 11
462	/** This action forces the VM to service any pending updates to CR3 (used only
463	* by HM). */
464	#define VMCPU_FF_HM_UPDATE_CR3 RT_BIT_32(VMCPU_FF_HM_UPDATE_CR3_BIT)
465	#define VMCPU_FF_HM_UPDATE_CR3_BIT 12
466	/** This action forces the VM to service any pending updates to PAE PDPEs (used
467	* only by HM). */
468	#define VMCPU_FF_HM_UPDATE_PAE_PDPES RT_BIT_32(VMCPU_FF_HM_UPDATE_PAE_PDPES_BIT)
469	#define VMCPU_FF_HM_UPDATE_PAE_PDPES_BIT 13
470	/** This action forces the VM to resync the page tables before going
471	* back to execute guest code. (GLOBAL FLUSH) */
472	#define VMCPU_FF_PGM_SYNC_CR3 RT_BIT_32(VMCPU_FF_PGM_SYNC_CR3_BIT)
473	#define VMCPU_FF_PGM_SYNC_CR3_BIT 16
474	/** Same as VM_FF_PGM_SYNC_CR3 except that global pages can be skipped.
475	* (NON-GLOBAL FLUSH) */
476	#define VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL RT_BIT_32(VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL_BIT)
477	#define VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL_BIT 17
478	/** Check for pending TLB shootdown actions (deprecated)
479	* Reserved for furture HM re-use if necessary / safe.
480	* Consumer: HM */
481	#define VMCPU_FF_TLB_SHOOTDOWN_UNUSED RT_BIT_32(VMCPU_FF_TLB_SHOOTDOWN_UNUSED_BIT)
482	#define VMCPU_FF_TLB_SHOOTDOWN_UNUSED_BIT 18
483	/** Check for pending TLB flush action.
484	* Consumer: HM
485	* @todo rename to VMCPU_FF_HM_TLB_FLUSH */
486	#define VMCPU_FF_TLB_FLUSH RT_BIT_32(VMCPU_FF_TLB_FLUSH_BIT)
487	/** The bit number for VMCPU_FF_TLB_FLUSH. */
488	#define VMCPU_FF_TLB_FLUSH_BIT 19
489	#ifdef VBOX_WITH_RAW_MODE
490	/** Check the interrupt and trap gates */
491	# define VMCPU_FF_TRPM_SYNC_IDT RT_BIT_32(VMCPU_FF_TRPM_SYNC_IDT_BIT)
492	# define VMCPU_FF_TRPM_SYNC_IDT_BIT 20
493	/** Check Guest's TSS ring 0 stack */
494	# define VMCPU_FF_SELM_SYNC_TSS RT_BIT_32(VMCPU_FF_SELM_SYNC_TSS_BIT)
495	# define VMCPU_FF_SELM_SYNC_TSS_BIT 21
496	/** Check Guest's GDT table */
497	# define VMCPU_FF_SELM_SYNC_GDT RT_BIT_32(VMCPU_FF_SELM_SYNC_GDT_BIT)
498	# define VMCPU_FF_SELM_SYNC_GDT_BIT 22
499	/** Check Guest's LDT table */
500	# define VMCPU_FF_SELM_SYNC_LDT RT_BIT_32(VMCPU_FF_SELM_SYNC_LDT_BIT)
501	# define VMCPU_FF_SELM_SYNC_LDT_BIT 23
502	#endif /* VBOX_WITH_RAW_MODE */
503	/** Inhibit interrupts pending. See EMGetInhibitInterruptsPC(). */
504	#define VMCPU_FF_INHIBIT_INTERRUPTS RT_BIT_32(VMCPU_FF_INHIBIT_INTERRUPTS_BIT)
505	#define VMCPU_FF_INHIBIT_INTERRUPTS_BIT 24
506	/** Block injection of non-maskable interrupts to the guest. */
507	#define VMCPU_FF_BLOCK_NMIS RT_BIT_32(VMCPU_FF_BLOCK_NMIS_BIT)
508	#define VMCPU_FF_BLOCK_NMIS_BIT 25
509	#ifdef VBOX_WITH_RAW_MODE
510	/** CSAM needs to scan the page that's being executed */
511	# define VMCPU_FF_CSAM_SCAN_PAGE RT_BIT_32(VMCPU_FF_CSAM_SCAN_PAGE_BIT)
512	# define VMCPU_FF_CSAM_SCAN_PAGE_BIT 26
513	/** CSAM needs to do some homework. */
514	# define VMCPU_FF_CSAM_PENDING_ACTION RT_BIT_32(VMCPU_FF_CSAM_PENDING_ACTION_BIT)
515	# define VMCPU_FF_CSAM_PENDING_ACTION_BIT 27
516	#endif /* VBOX_WITH_RAW_MODE */
517	/** Force return to Ring-3. */
518	#define VMCPU_FF_TO_R3 RT_BIT_32(VMCPU_FF_TO_R3_BIT)
519	#define VMCPU_FF_TO_R3_BIT 28
520	/** Force return to ring-3 to service pending I/O or MMIO write.
521	* This is a backup for mechanism VINF_IOM_R3_IOPORT_COMMIT_WRITE and
522	* VINF_IOM_R3_MMIO_COMMIT_WRITE, allowing VINF_EM_DBG_BREAKPOINT and similar
523	* status codes to be propagated at the same time without loss. */
524	#define VMCPU_FF_IOM RT_BIT_32(VMCPU_FF_IOM_BIT)
525	#define VMCPU_FF_IOM_BIT 29
526	#ifdef VBOX_WITH_RAW_MODE
527	/** CPUM need to adjust CR0.TS/EM before executing raw-mode code again. */
528	# define VMCPU_FF_CPUM RT_BIT_32(VMCPU_FF_CPUM_BIT)
529	/** The bit number for VMCPU_FF_CPUM. */
530	# define VMCPU_FF_CPUM_BIT 30
531	#endif /* VBOX_WITH_RAW_MODE */
532	/** Hardware virtualized nested-guest interrupt pending. */
533	#define VMCPU_FF_INTERRUPT_NESTED_GUEST RT_BIT_32(VMCPU_FF_INTERRUPT_NESTED_GUEST_BIT)
534	#define VMCPU_FF_INTERRUPT_NESTED_GUEST_BIT 31
535
536
537	/** Externally VM forced actions. Used to quit the idle/wait loop. */
538	#define VM_FF_EXTERNAL_SUSPENDED_MASK ( VM_FF_CHECK_VM_STATE \| VM_FF_DBGF \| VM_FF_REQUEST \| VM_FF_EMT_RENDEZVOUS )
539	/** Externally VMCPU forced actions. Used to quit the idle/wait loop. */
540	#define VMCPU_FF_EXTERNAL_SUSPENDED_MASK ( VMCPU_FF_REQUEST \| VMCPU_FF_DBGF )
541
542	/** Externally forced VM actions. Used to quit the idle/wait loop. */
543	#define VM_FF_EXTERNAL_HALTED_MASK ( VM_FF_CHECK_VM_STATE \| VM_FF_DBGF \| VM_FF_REQUEST \
544	\| VM_FF_PDM_QUEUES \| VM_FF_PDM_DMA \| VM_FF_EMT_RENDEZVOUS )
545	/** Externally forced VMCPU actions. Used to quit the idle/wait loop. */
546	#define VMCPU_FF_EXTERNAL_HALTED_MASK ( VMCPU_FF_UPDATE_APIC \| VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC \
547	\| VMCPU_FF_REQUEST \| VMCPU_FF_INTERRUPT_NMI \| VMCPU_FF_INTERRUPT_SMI \
548	\| VMCPU_FF_UNHALT \| VMCPU_FF_TIMER \| VMCPU_FF_DBGF )
549
550	/** High priority VM pre-execution actions. */
551	#define VM_FF_HIGH_PRIORITY_PRE_MASK ( VM_FF_CHECK_VM_STATE \| VM_FF_DBGF \| VM_FF_TM_VIRTUAL_SYNC \
552	\| VM_FF_DEBUG_SUSPEND \| VM_FF_PGM_NEED_HANDY_PAGES \| VM_FF_PGM_NO_MEMORY \
553	\| VM_FF_EMT_RENDEZVOUS )
554	/** High priority VMCPU pre-execution actions. */
555	#define VMCPU_FF_HIGH_PRIORITY_PRE_MASK ( VMCPU_FF_TIMER \| VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC \
556	\| VMCPU_FF_UPDATE_APIC \| VMCPU_FF_INHIBIT_INTERRUPTS \| VMCPU_FF_DBGF \
557	\| VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL \
558	\| VM_WHEN_RAW_MODE( VMCPU_FF_SELM_SYNC_TSS \| VMCPU_FF_TRPM_SYNC_IDT \
559	\| VMCPU_FF_SELM_SYNC_GDT \| VMCPU_FF_SELM_SYNC_LDT, 0 ) )
560
561	/** High priority VM pre raw-mode execution mask. */
562	#define VM_FF_HIGH_PRIORITY_PRE_RAW_MASK ( VM_FF_PGM_NEED_HANDY_PAGES \| VM_FF_PGM_NO_MEMORY )
563	/** High priority VMCPU pre raw-mode execution mask. */
564	#define VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK ( VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL \
565	\| VMCPU_FF_INHIBIT_INTERRUPTS \
566	\| VM_WHEN_RAW_MODE( VMCPU_FF_SELM_SYNC_TSS \| VMCPU_FF_TRPM_SYNC_IDT \
567	\| VMCPU_FF_SELM_SYNC_GDT \| VMCPU_FF_SELM_SYNC_LDT, 0) )
568
569	/** High priority post-execution actions. */
570	#define VM_FF_HIGH_PRIORITY_POST_MASK ( VM_FF_PGM_NO_MEMORY )
571	/** High priority post-execution actions. */
572	#define VMCPU_FF_HIGH_PRIORITY_POST_MASK ( VMCPU_FF_PDM_CRITSECT \| VM_WHEN_RAW_MODE(VMCPU_FF_CSAM_PENDING_ACTION, 0) \
573	\| VMCPU_FF_HM_UPDATE_CR3 \| VMCPU_FF_HM_UPDATE_PAE_PDPES \
574	\| VMCPU_FF_IEM \| VMCPU_FF_IOM )
575
576	/** Normal priority VM post-execution actions. */
577	#define VM_FF_NORMAL_PRIORITY_POST_MASK ( VM_FF_CHECK_VM_STATE \| VM_FF_DBGF \| VM_FF_RESET \
578	\| VM_FF_PGM_NO_MEMORY \| VM_FF_EMT_RENDEZVOUS)
579	/** Normal priority VMCPU post-execution actions. */
580	#define VMCPU_FF_NORMAL_PRIORITY_POST_MASK ( VM_WHEN_RAW_MODE(VMCPU_FF_CSAM_SCAN_PAGE, 0) \| VMCPU_FF_DBGF )
581
582	/** Normal priority VM actions. */
583	#define VM_FF_NORMAL_PRIORITY_MASK ( VM_FF_REQUEST \| VM_FF_PDM_QUEUES \| VM_FF_PDM_DMA \
584	\| VM_FF_REM_HANDLER_NOTIFY \| VM_FF_EMT_RENDEZVOUS)
585	/** Normal priority VMCPU actions. */
586	#define VMCPU_FF_NORMAL_PRIORITY_MASK ( VMCPU_FF_REQUEST )
587
588	/** Flags to clear before resuming guest execution. */
589	#define VMCPU_FF_RESUME_GUEST_MASK ( VMCPU_FF_TO_R3 )
590
591
592	/** VM flags that cause the REP[\|NE\|E] STRINS loops to yield immediately. */
593	#define VM_FF_HIGH_PRIORITY_POST_REPSTR_MASK ( VM_FF_TM_VIRTUAL_SYNC \| VM_FF_PGM_NEED_HANDY_PAGES \| VM_FF_PGM_NO_MEMORY \
594	\| VM_FF_EMT_RENDEZVOUS \| VM_FF_PGM_POOL_FLUSH_PENDING \| VM_FF_RESET)
595	/** VM flags that cause the REP[\|NE\|E] STRINS loops to yield. */
596	#define VM_FF_YIELD_REPSTR_MASK ( VM_FF_HIGH_PRIORITY_POST_REPSTR_MASK \
597	\| VM_FF_PDM_QUEUES \| VM_FF_PDM_DMA \| VM_FF_DBGF \| VM_FF_DEBUG_SUSPEND )
598	/** VMCPU flags that cause the REP[\|NE\|E] STRINS loops to yield immediately. */
599	#ifdef IN_RING3
600	# define VMCPU_FF_HIGH_PRIORITY_POST_REPSTR_MASK ( VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL \| VMCPU_FF_DBGF )
601	#else
602	# define VMCPU_FF_HIGH_PRIORITY_POST_REPSTR_MASK ( VMCPU_FF_TO_R3 \| VMCPU_FF_IEM \| VMCPU_FF_IOM \| VMCPU_FF_PGM_SYNC_CR3 \
603	\| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL \| VMCPU_FF_DBGF )
604	#endif
605	/** VMCPU flags that cause the REP[\|NE\|E] STRINS loops to yield, interrupts
606	* enabled. */
607	#define VMCPU_FF_YIELD_REPSTR_MASK ( VMCPU_FF_HIGH_PRIORITY_POST_REPSTR_MASK \
608	\| VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_UPDATE_APIC \| VMCPU_FF_INTERRUPT_PIC \
609	\| VMCPU_FF_INTERRUPT_NMI \| VMCPU_FF_INTERRUPT_SMI \| VMCPU_FF_PDM_CRITSECT \
610	\| VMCPU_FF_TIMER \| VMCPU_FF_REQUEST )
611	/** VMCPU flags that cause the REP[\|NE\|E] STRINS loops to yield, interrupts
612	* disabled. */
613	#define VMCPU_FF_YIELD_REPSTR_NOINT_MASK ( VMCPU_FF_YIELD_REPSTR_MASK \
614	& ~(VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_UPDATE_APIC \| VMCPU_FF_INTERRUPT_PIC) )
615
616	/** VM Flags that cause the HM loops to go back to ring-3. */
617	#define VM_FF_HM_TO_R3_MASK ( VM_FF_TM_VIRTUAL_SYNC \| VM_FF_PGM_NEED_HANDY_PAGES \| VM_FF_PGM_NO_MEMORY \
618	\| VM_FF_PDM_QUEUES \| VM_FF_EMT_RENDEZVOUS)
619	/** VMCPU Flags that cause the HM loops to go back to ring-3. */
620	#define VMCPU_FF_HM_TO_R3_MASK ( VMCPU_FF_TO_R3 \| VMCPU_FF_TIMER \| VMCPU_FF_PDM_CRITSECT \
621	\| VMCPU_FF_IEM \| VMCPU_FF_IOM)
622
623	/** High priority ring-0 VM pre HM-mode execution mask. */
624	#define VM_FF_HP_R0_PRE_HM_MASK (VM_FF_HM_TO_R3_MASK \| VM_FF_REQUEST \| VM_FF_PGM_POOL_FLUSH_PENDING \| VM_FF_PDM_DMA)
625	/** High priority ring-0 VMCPU pre HM-mode execution mask. */
626	#define VMCPU_FF_HP_R0_PRE_HM_MASK ( VMCPU_FF_HM_TO_R3_MASK \| VMCPU_FF_PGM_SYNC_CR3 \
627	\| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL \| VMCPU_FF_REQUEST)
628	/** High priority ring-0 VM pre HM-mode execution mask, single stepping. */
629	#define VM_FF_HP_R0_PRE_HM_STEP_MASK (VM_FF_HP_R0_PRE_HM_MASK & ~( VM_FF_TM_VIRTUAL_SYNC \| VM_FF_PDM_QUEUES \
630	\| VM_FF_EMT_RENDEZVOUS \| VM_FF_REQUEST \
631	\| VM_FF_PDM_DMA) )
632	/** High priority ring-0 VMCPU pre HM-mode execution mask, single stepping. */
633	#define VMCPU_FF_HP_R0_PRE_HM_STEP_MASK (VMCPU_FF_HP_R0_PRE_HM_MASK & ~( VMCPU_FF_TO_R3 \| VMCPU_FF_TIMER \
634	\| VMCPU_FF_PDM_CRITSECT \| VMCPU_FF_REQUEST) )
635
636	/** All the forced VM flags. */
637	#define VM_FF_ALL_MASK (UINT32_MAX)
638	/** All the forced VMCPU flags. */
639	#define VMCPU_FF_ALL_MASK (UINT32_MAX)
640
641	/** All the forced VM flags except those related to raw-mode and hardware
642	* assisted execution. */
643	#define VM_FF_ALL_REM_MASK (~(VM_FF_HIGH_PRIORITY_PRE_RAW_MASK) \| VM_FF_PGM_NEED_HANDY_PAGES \| VM_FF_PGM_NO_MEMORY)
644	/** All the forced VMCPU flags except those related to raw-mode and hardware
645	* assisted execution. */
646	#define VMCPU_FF_ALL_REM_MASK (~( VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK \| VMCPU_FF_PDM_CRITSECT \
647	\| VMCPU_FF_TLB_FLUSH \| VM_WHEN_RAW_MODE(VMCPU_FF_CSAM_PENDING_ACTION, 0) ))
648	/** @} */
649
650	/** @def VM_FF_SET
651	* Sets a single force action flag.
652	*
653	* @param pVM The cross context VM structure.
654	* @param fFlag The flag to set.
655	*/
656	#define VM_FF_SET(pVM, fFlag) do { \
657	AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
658	AssertCompile((fFlag) == RT_BIT_32(fFlag##_BIT)); \
659	ASMAtomicOrU32(&(pVM)->fGlobalForcedActions, (fFlag)); \
660	} while (0)
661
662	/** @def VMCPU_FF_SET
663	* Sets a single force action flag for the given VCPU.
664	*
665	* @param pVCpu The cross context virtual CPU structure.
666	* @param fFlag The flag to set.
667	* @sa VMCPU_FF_SET_MASK
668	*/
669	#define VMCPU_FF_SET(pVCpu, fFlag) do { \
670	AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
671	AssertCompile((fFlag) == RT_BIT_32(fFlag##_BIT)); \
672	ASMAtomicOrU32(&(pVCpu)->fLocalForcedActions, (fFlag)); \
673	} while (0)
674
675	/** @def VMCPU_FF_SET_MASK
676	* Sets a two or more force action flag for the given VCPU.
677	*
678	* @param pVCpu The cross context virtual CPU structure.
679	* @param fFlags The flags to set.
680	* @sa VMCPU_FF_SET
681	*/
682	#define VMCPU_FF_SET_MASK(a_pVCpu, fFlags) \
683	do { ASMAtomicOrU32(&a_pVCpu->fLocalForcedActions, (fFlags)); } while (0)
684
685	/** @def VM_FF_CLEAR
686	* Clears a single force action flag.
687	*
688	* @param pVM The cross context VM structure.
689	* @param fFlag The flag to clear.
690	*/
691	#define VM_FF_CLEAR(pVM, fFlag) do { \
692	AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
693	AssertCompile((fFlag) == RT_BIT_32(fFlag##_BIT)); \
694	ASMAtomicAndU32(&(pVM)->fGlobalForcedActions, ~(fFlag)); \
695	} while (0)
696
697	/** @def VMCPU_FF_CLEAR
698	* Clears a single force action flag for the given VCPU.
699	*
700	* @param pVCpu The cross context virtual CPU structure.
701	* @param fFlag The flag to clear.
702	*/
703	#define VMCPU_FF_CLEAR(pVCpu, fFlag) do { \
704	AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
705	AssertCompile((fFlag) == RT_BIT_32(fFlag##_BIT)); \
706	ASMAtomicAndU32(&(pVCpu)->fLocalForcedActions, ~(fFlag)); \
707	} while (0)
708
709	/** @def VMCPU_FF_CLEAR_MASK
710	* Clears two or more force action flags for the given VCPU.
711	*
712	* @param pVCpu The cross context virtual CPU structure.
713	* @param fFlags The flags to clear.
714	*/
715	#define VMCPU_FF_CLEAR_MASK(pVCpu, fFlags) \
716	do { ASMAtomicAndU32(&(pVCpu)->fLocalForcedActions, ~(fFlags)); } while (0)
717
718	/** @def VM_FF_IS_SET
719	* Checks if single a force action flag is set.
720	*
721	* @param pVM The cross context VM structure.
722	* @param fFlag The flag to check.
723	* @sa VM_FF_IS_ANY_SET
724	*/
725	#if !defined(VBOX_STRICT) \|\| !defined(RT_COMPILER_SUPPORTS_LAMBDA)
726	# define VM_FF_IS_SET(pVM, fFlag) (((pVM)->fGlobalForcedActions & (fFlag)) == (fFlag))
727	#else
728	# define VM_FF_IS_SET(pVM, fFlag) \
729	([](PVM a_pVM) -> bool \
730	{ \
731	AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
732	AssertCompile((fFlag) == RT_BIT_32(fFlag##_BIT)); \
733	return (a_pVM->fGlobalForcedActions & (fFlag)) == (fFlag); \
734	}(pVM))
735	#endif
736
737	/** @def VMCPU_FF_IS_SET
738	* Checks if a single force action flag is set for the given VCPU.
739	*
740	* @param pVCpu The cross context virtual CPU structure.
741	* @param fFlag The flag to check.
742	* @sa VMCPU_FF_IS_ANY_SET
743	*/
744	#if !defined(VBOX_STRICT) \|\| !defined(RT_COMPILER_SUPPORTS_LAMBDA)
745	# define VMCPU_FF_IS_SET(pVCpu, fFlag) (((pVCpu)->fLocalForcedActions & (fFlag)) == (fFlag))
746	#else
747	# define VMCPU_FF_IS_SET(pVCpu, fFlag) \
748	([](PVMCPU a_pVCpu) -> bool \
749	{ \
750	AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
751	AssertCompile((fFlag) == RT_BIT_32(fFlag##_BIT)); \
752	return (a_pVCpu->fLocalForcedActions & (fFlag)) == (fFlag); \
753	}(pVCpu))
754	#endif
755
756	/** @def VM_FF_IS_ANY_SET
757	* Checks if one or more force action in the specified set is pending.
758	*
759	* @param pVM The cross context VM structure.
760	* @param fFlags The flags to check for.
761	* @sa VM_FF_IS_SET
762	*/
763	#define VM_FF_IS_ANY_SET(pVM, fFlags) RT_BOOL((pVM)->fGlobalForcedActions & (fFlags))
764
765	/** @def VMCPU_FF_IS_ANY_SET
766	* Checks if two or more force action flags in the specified set is set for the given VCPU.
767	*
768	* @param pVCpu The cross context virtual CPU structure.
769	* @param fFlags The flags to check for.
770	* @sa VMCPU_FF_IS_SET
771	*/
772	#define VMCPU_FF_IS_ANY_SET(pVCpu, fFlags) RT_BOOL((pVCpu)->fLocalForcedActions & (fFlags))
773
774	/** @def VM_FF_TEST_AND_CLEAR
775	* Checks if one (!) force action in the specified set is pending and clears it atomically
776	*
777	* @returns true if the bit was set.
778	* @returns false if the bit was clear.
779	* @param pVM The cross context VM structure.
780	* @param fFlag Flag constant to check and clear (_BIT is appended).
781	*/
782	#define VM_FF_TEST_AND_CLEAR(pVM, fFlag) (ASMAtomicBitTestAndClear(&(pVM)->fGlobalForcedActions, fFlag##_BIT))
783
784	/** @def VMCPU_FF_TEST_AND_CLEAR
785	* Checks if one (!) force action in the specified set is pending and clears it atomically
786	*
787	* @returns true if the bit was set.
788	* @returns false if the bit was clear.
789	* @param pVCpu The cross context virtual CPU structure.
790	* @param fFlag Flag constant to check and clear (_BIT is appended).
791	*/
792	#define VMCPU_FF_TEST_AND_CLEAR(pVCpu, fFlag) (ASMAtomicBitTestAndClear(&(pVCpu)->fLocalForcedActions, fFlag##_BIT))
793
794	/** @def VM_FF_IS_PENDING_EXCEPT
795	* Checks if one or more force action in the specified set is pending while one
796	* or more other ones are not.
797	*
798	* @param pVM The cross context VM structure.
799	* @param fFlags The flags to check for.
800	* @param fExcpt The flags that should not be set.
801	*/
802	#define VM_FF_IS_PENDING_EXCEPT(pVM, fFlags, fExcpt) \
803	( ((pVM)->fGlobalForcedActions & (fFlags)) && !((pVM)->fGlobalForcedActions & (fExcpt)) )
804
805	/** @def VM_IS_EMT
806	* Checks if the current thread is the emulation thread (EMT).
807	*
808	* @remark The ring-0 variation will need attention if we expand the ring-0
809	* code to let threads other than EMT mess around with the VM.
810	*/
811	#ifdef IN_RC
812	# define VM_IS_EMT(pVM) true
813	#else
814	# define VM_IS_EMT(pVM) (VMMGetCpu(pVM) != NULL)
815	#endif
816
817	/** @def VMCPU_IS_EMT
818	* Checks if the current thread is the emulation thread (EMT) for the specified
819	* virtual CPU.
820	*/
821	#ifdef IN_RC
822	# define VMCPU_IS_EMT(pVCpu) true
823	#else
824	# define VMCPU_IS_EMT(pVCpu) ((pVCpu) && ((pVCpu) == VMMGetCpu((pVCpu)->CTX_SUFF(pVM))))
825	#endif
826
827	/** @def VM_ASSERT_EMT
828	* Asserts that the current thread IS the emulation thread (EMT).
829	*/
830	#ifdef IN_RC
831	# define VM_ASSERT_EMT(pVM) Assert(VM_IS_EMT(pVM))
832	#elif defined(IN_RING0)
833	# define VM_ASSERT_EMT(pVM) Assert(VM_IS_EMT(pVM))
834	#else
835	# define VM_ASSERT_EMT(pVM) \
836	AssertMsg(VM_IS_EMT(pVM), \
837	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd\n", RTThreadNativeSelf(), VMR3GetVMCPUNativeThread(pVM)))
838	#endif
839
840	/** @def VMCPU_ASSERT_EMT
841	* Asserts that the current thread IS the emulation thread (EMT) of the
842	* specified virtual CPU.
843	*/
844	#ifdef IN_RC
845	# define VMCPU_ASSERT_EMT(pVCpu) Assert(VMCPU_IS_EMT(pVCpu))
846	#elif defined(IN_RING0)
847	# define VMCPU_ASSERT_EMT(pVCpu) AssertMsg(VMCPU_IS_EMT(pVCpu), \
848	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd idCpu=%u\n", \
849	RTThreadNativeSelf(), (pVCpu) ? (pVCpu)->hNativeThreadR0 : 0, \
850	(pVCpu) ? (pVCpu)->idCpu : 0))
851	#else
852	# define VMCPU_ASSERT_EMT(pVCpu) AssertMsg(VMCPU_IS_EMT(pVCpu), \
853	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd idCpu=%#x\n", \
854	RTThreadNativeSelf(), (pVCpu)->hNativeThread, (pVCpu)->idCpu))
855	#endif
856
857	/** @def VM_ASSERT_EMT_RETURN
858	* Asserts that the current thread IS the emulation thread (EMT) and returns if it isn't.
859	*/
860	#ifdef IN_RC
861	# define VM_ASSERT_EMT_RETURN(pVM, rc) AssertReturn(VM_IS_EMT(pVM), (rc))
862	#elif defined(IN_RING0)
863	# define VM_ASSERT_EMT_RETURN(pVM, rc) AssertReturn(VM_IS_EMT(pVM), (rc))
864	#else
865	# define VM_ASSERT_EMT_RETURN(pVM, rc) \
866	AssertMsgReturn(VM_IS_EMT(pVM), \
867	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd\n", RTThreadNativeSelf(), VMR3GetVMCPUNativeThread(pVM)), \
868	(rc))
869	#endif
870
871	/** @def VMCPU_ASSERT_EMT_RETURN
872	* Asserts that the current thread IS the emulation thread (EMT) and returns if it isn't.
873	*/
874	#ifdef IN_RC
875	# define VMCPU_ASSERT_EMT_RETURN(pVCpu, rc) AssertReturn(VMCPU_IS_EMT(pVCpu), (rc))
876	#elif defined(IN_RING0)
877	# define VMCPU_ASSERT_EMT_RETURN(pVCpu, rc) AssertReturn(VMCPU_IS_EMT(pVCpu), (rc))
878	#else
879	# define VMCPU_ASSERT_EMT_RETURN(pVCpu, rc) \
880	AssertMsgReturn(VMCPU_IS_EMT(pVCpu), \
881	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd idCpu=%#x\n", \
882	RTThreadNativeSelf(), (pVCpu)->hNativeThread, (pVCpu)->idCpu), \
883	(rc))
884	#endif
885
886	/** @def VMCPU_ASSERT_EMT_OR_GURU
887	* Asserts that the current thread IS the emulation thread (EMT) of the
888	* specified virtual CPU.
889	*/
890	#if defined(IN_RC) \|\| defined(IN_RING0)
891	# define VMCPU_ASSERT_EMT_OR_GURU(pVCpu) Assert( VMCPU_IS_EMT(pVCpu) \
892	\|\| pVCpu->CTX_SUFF(pVM)->enmVMState == VMSTATE_GURU_MEDITATION \
893	\|\| pVCpu->CTX_SUFF(pVM)->enmVMState == VMSTATE_GURU_MEDITATION_LS )
894	#else
895	# define VMCPU_ASSERT_EMT_OR_GURU(pVCpu) \
896	AssertMsg( VMCPU_IS_EMT(pVCpu) \
897	\|\| pVCpu->CTX_SUFF(pVM)->enmVMState == VMSTATE_GURU_MEDITATION \
898	\|\| pVCpu->CTX_SUFF(pVM)->enmVMState == VMSTATE_GURU_MEDITATION_LS, \
899	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd idCpu=%#x\n", \
900	RTThreadNativeSelf(), (pVCpu)->hNativeThread, (pVCpu)->idCpu))
901	#endif
902
903	/** @def VMCPU_ASSERT_EMT_OR_NOT_RUNNING
904	* Asserts that the current thread IS the emulation thread (EMT) of the
905	* specified virtual CPU or the VM is not running.
906	*/
907	#if defined(IN_RC) \|\| defined(IN_RING0)
908	# define VMCPU_ASSERT_EMT_OR_NOT_RUNNING(pVCpu) \
909	Assert( VMCPU_IS_EMT(pVCpu) \
910	\|\| !VM_IS_RUNNING_FOR_ASSERTIONS_ONLY((pVCpu)->CTX_SUFF(pVM)) )
911	#else
912	# define VMCPU_ASSERT_EMT_OR_NOT_RUNNING(pVCpu) \
913	AssertMsg( VMCPU_IS_EMT(pVCpu) \
914	\|\| !VM_IS_RUNNING_FOR_ASSERTIONS_ONLY((pVCpu)->CTX_SUFF(pVM)), \
915	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd idCpu=%#x\n", \
916	RTThreadNativeSelf(), (pVCpu)->hNativeThread, (pVCpu)->idCpu))
917	#endif
918
919	/** @def VMSTATE_IS_RUNNING
920	* Checks if the given state indicates a running VM.
921	*/
922	#define VMSTATE_IS_RUNNING(a_enmVMState) \
923	( (enmVMState) == VMSTATE_RUNNING \
924	\|\| (enmVMState) == VMSTATE_RUNNING_LS \
925	\|\| (enmVMState) == VMSTATE_RUNNING_FT )
926
927	/** @def VM_IS_RUNNING_FOR_ASSERTIONS_ONLY
928	* Checks if the VM is running.
929	* @note This is only for pure debug assertions. No AssertReturn or similar!
930	* @sa VMSTATE_IS_RUNNING
931	*/
932	#define VM_IS_RUNNING_FOR_ASSERTIONS_ONLY(pVM) \
933	( (pVM)->enmVMState == VMSTATE_RUNNING \
934	\|\| (pVM)->enmVMState == VMSTATE_RUNNING_LS \
935	\|\| (pVM)->enmVMState == VMSTATE_RUNNING_FT )
936
937	/** @def VM_ASSERT_IS_NOT_RUNNING
938	* Asserts that the VM is not running.
939	*/
940	#if defined(IN_RC) \|\| defined(IN_RING0)
941	#define VM_ASSERT_IS_NOT_RUNNING(pVM) Assert(!VM_IS_RUNNING_FOR_ASSERTIONS_ONLY(pVM))
942	#else
943	#define VM_ASSERT_IS_NOT_RUNNING(pVM) AssertMsg(!VM_IS_RUNNING_FOR_ASSERTIONS_ONLY(pVM), \
944	("VM is running. enmVMState=%d\n", (pVM)->enmVMState))
945	#endif
946
947	/** @def VM_ASSERT_EMT0
948	* Asserts that the current thread IS emulation thread \#0 (EMT0).
949	*/
950	#define VM_ASSERT_EMT0(pVM) VMCPU_ASSERT_EMT(&(pVM)->aCpus[0])
951
952	/** @def VM_ASSERT_EMT0_RETURN
953	* Asserts that the current thread IS emulation thread \#0 (EMT0) and returns if
954	* it isn't.
955	*/
956	#define VM_ASSERT_EMT0_RETURN(pVM, rc) VMCPU_ASSERT_EMT_RETURN(&(pVM)->aCpus[0], (rc))
957
958
959	/**
960	* Asserts that the current thread is NOT the emulation thread.
961	*/
962	#define VM_ASSERT_OTHER_THREAD(pVM) \
963	AssertMsg(!VM_IS_EMT(pVM), ("Not other thread!!\n"))
964
965
966	/** @def VM_ASSERT_STATE
967	* Asserts a certain VM state.
968	*/
969	#define VM_ASSERT_STATE(pVM, _enmState) \
970	AssertMsg((pVM)->enmVMState == (_enmState), \
971	("state %s, expected %s\n", VMGetStateName((pVM)->enmVMState), VMGetStateName(_enmState)))
972
973	/** @def VM_ASSERT_STATE_RETURN
974	* Asserts a certain VM state and returns if it doesn't match.
975	*/
976	#define VM_ASSERT_STATE_RETURN(pVM, _enmState, rc) \
977	AssertMsgReturn((pVM)->enmVMState == (_enmState), \
978	("state %s, expected %s\n", VMGetStateName((pVM)->enmVMState), VMGetStateName(_enmState)), \
979	(rc))
980
981	/** @def VM_IS_VALID_EXT
982	* Asserts a the VM handle is valid for external access, i.e. not being destroy
983	* or terminated. */
984	#define VM_IS_VALID_EXT(pVM) \
985	( RT_VALID_ALIGNED_PTR(pVM, PAGE_SIZE) \
986	&& ( (unsigned)(pVM)->enmVMState < (unsigned)VMSTATE_DESTROYING \
987	\|\| ( (unsigned)(pVM)->enmVMState == (unsigned)VMSTATE_DESTROYING \
988	&& VM_IS_EMT(pVM))) )
989
990	/** @def VM_ASSERT_VALID_EXT_RETURN
991	* Asserts a the VM handle is valid for external access, i.e. not being
992	* destroy or terminated.
993	*/
994	#define VM_ASSERT_VALID_EXT_RETURN(pVM, rc) \
995	AssertMsgReturn(VM_IS_VALID_EXT(pVM), \
996	("pVM=%p state %s\n", (pVM), RT_VALID_ALIGNED_PTR(pVM, PAGE_SIZE) \
997	? VMGetStateName(pVM->enmVMState) : ""), \
998	(rc))
999
1000	/** @def VMCPU_ASSERT_VALID_EXT_RETURN
1001	* Asserts a the VMCPU handle is valid for external access, i.e. not being
1002	* destroy or terminated.
1003	*/
1004	#define VMCPU_ASSERT_VALID_EXT_RETURN(pVCpu, rc) \
1005	AssertMsgReturn( RT_VALID_ALIGNED_PTR(pVCpu, 64) \
1006	&& RT_VALID_ALIGNED_PTR((pVCpu)->CTX_SUFF(pVM), PAGE_SIZE) \
1007	&& (unsigned)(pVCpu)->CTX_SUFF(pVM)->enmVMState < (unsigned)VMSTATE_DESTROYING, \
1008	("pVCpu=%p pVM=%p state %s\n", (pVCpu), RT_VALID_ALIGNED_PTR(pVCpu, 64) ? (pVCpu)->CTX_SUFF(pVM) : NULL, \
1009	RT_VALID_ALIGNED_PTR(pVCpu, 64) && RT_VALID_ALIGNED_PTR((pVCpu)->CTX_SUFF(pVM), PAGE_SIZE) \
1010	? VMGetStateName((pVCpu)->pVMR3->enmVMState) : ""), \
1011	(rc))
1012
1013	#endif /* !VBOX_FOR_DTRACE_LIB */
1014
1015
1016	/**
1017	* Helper that HM and NEM uses for safely modifying VM::bMainExecutionEngine.
1018	*
1019	* ONLY HM and NEM MAY USE THIS!
1020	*
1021	* @param a_pVM The cross context VM structure.
1022	* @param a_bValue The new value.
1023	* @internal
1024	*/
1025	#define VM_SET_MAIN_EXECUTION_ENGINE(a_pVM, a_bValue) \
1026	do { \
1027	const_cast<uint8_t >(&(a_pVM)->bMainExecutionEngine) = (a_bValue); \
1028	ASMCompilerBarrier(); /* just to be on the safe side */ \
1029	} while (0)
1030
1031	/**
1032	* Checks whether raw-mode is used.
1033	*
1034	* @retval true if either is used.
1035	* @retval false if software virtualization (raw-mode) is used.
1036	*
1037	* @param a_pVM The cross context VM structure.
1038	* @sa VM_IS_HM_OR_NEM_ENABLED, VM_IS_HM_ENABLED, VM_IS_NEM_ENABLED.
1039	* @internal
1040	*/
1041	#ifdef VBOX_WITH_RAW_MODE
1042	# define VM_IS_RAW_MODE_ENABLED(a_pVM) ((a_pVM)->bMainExecutionEngine == VM_EXEC_ENGINE_RAW_MODE)
1043	#else
1044	# define VM_IS_RAW_MODE_ENABLED(a_pVM) (false)
1045	#endif
1046
1047	/**
1048	* Checks whether HM (VT-x/AMD-V) or NEM is being used by this VM.
1049	*
1050	* @retval true if either is used.
1051	* @retval false if software virtualization (raw-mode) is used.
1052	*
1053	* @param a_pVM The cross context VM structure.
1054	* @sa VM_IS_RAW_MODE_ENABLED, VM_IS_HM_ENABLED, VM_IS_NEM_ENABLED.
1055	* @internal
1056	*/
1057	#define VM_IS_HM_OR_NEM_ENABLED(a_pVM) ((a_pVM)->bMainExecutionEngine != VM_EXEC_ENGINE_RAW_MODE)
1058
1059	/**
1060	* Checks whether HM is being used by this VM.
1061	*
1062	* @retval true if HM (VT-x/AMD-v) is used.
1063	* @retval false if not.
1064	*
1065	* @param a_pVM The cross context VM structure.
1066	* @sa VM_IS_NEM_ENABLED, VM_IS_RAW_MODE_ENABLED, VM_IS_HM_OR_NEM_ENABLED.
1067	* @internal
1068	*/
1069	#define VM_IS_HM_ENABLED(a_pVM) ((a_pVM)->bMainExecutionEngine == VM_EXEC_ENGINE_HW_VIRT)
1070
1071	/**
1072	* Checks whether NEM is being used by this VM.
1073	*
1074	* @retval true if a native hypervisor API is used.
1075	* @retval false if not.
1076	*
1077	* @param a_pVM The cross context VM structure.
1078	* @sa VM_IS_HM_ENABLED, VM_IS_RAW_MODE_ENABLED, VM_IS_HM_OR_NEM_ENABLED.
1079	* @internal
1080	*/
1081	#define VM_IS_NEM_ENABLED(a_pVM) ((a_pVM)->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API)
1082
1083
1084	/**
1085	* The cross context VM structure.
1086	*
1087	* It contains all the VM data which have to be available in all contexts.
1088	* Even if it contains all the data the idea is to use APIs not to modify all
1089	* the members all around the place. Therefore we make use of unions to hide
1090	* everything which isn't local to the current source module. This means we'll
1091	* have to pay a little bit of attention when adding new members to structures
1092	* in the unions and make sure to keep the padding sizes up to date.
1093	*
1094	* Run 'kmk run-struct-tests' (from src/VBox/VMM if you like) after updating!
1095	*/
1096	typedef struct VM
1097	{
1098	/** The state of the VM.
1099	* This field is read only to everyone except the VM and EM. */
1100	VMSTATE volatile enmVMState;
1101	/** Forced action flags.
1102	* See the VM_FF_* \#defines. Updated atomically.
1103	*/
1104	volatile uint32_t fGlobalForcedActions;
1105	/** Pointer to the array of page descriptors for the VM structure allocation. */
1106	R3PTRTYPE(PSUPPAGE) paVMPagesR3;
1107	/** Session handle. For use when calling SUPR0 APIs. */
1108	PSUPDRVSESSION pSession;
1109	/** Pointer to the ring-3 VM structure. */
1110	PUVM pUVM;
1111	/** Ring-3 Host Context VM Pointer. */
1112	R3PTRTYPE(struct VM *) pVMR3;
1113	/** Ring-0 Host Context VM Pointer. */
1114	R0PTRTYPE(struct VM *) pVMR0;
1115	/** Raw-mode Context VM Pointer. */
1116	RCPTRTYPE(struct VM *) pVMRC;
1117
1118	/** The GVM VM handle. Only the GVM should modify this field. */
1119	uint32_t hSelf;
1120	/** Number of virtual CPUs. */
1121	uint32_t cCpus;
1122	/** CPU excution cap (1-100) */
1123	uint32_t uCpuExecutionCap;
1124
1125	/** Size of the VM structure including the VMCPU array. */
1126	uint32_t cbSelf;
1127
1128	/** Offset to the VMCPU array starting from beginning of this structure. */
1129	uint32_t offVMCPU;
1130
1131	/**
1132	* VMMSwitcher assembly entry point returning to host context.
1133	*
1134	* Depending on how the host handles the rc status given in @a eax, this may
1135	* return and let the caller resume whatever it was doing prior to the call.
1136	*
1137	*
1138	* @param eax The return code, register.
1139	* @remark Assume interrupts disabled.
1140	* @remark This method pointer lives here because TRPM needs it.
1141	*/
1142	RTRCPTR pfnVMMRCToHostAsm/(int32_t eax)/;
1143
1144	/**
1145	* VMMSwitcher assembly entry point returning to host context without saving the
1146	* raw-mode context (hyper) registers.
1147	*
1148	* Unlike pfnVMMRC2HCAsm, this will not return to the caller. Instead it
1149	* expects the caller to save a RC context in CPUM where one might return if the
1150	* return code indicate that this is possible.
1151	*
1152	* This method pointer lives here because TRPM needs it.
1153	*
1154	* @param eax The return code, register.
1155	* @remark Assume interrupts disabled.
1156	* @remark This method pointer lives here because TRPM needs it.
1157	*/
1158	RTRCPTR pfnVMMRCToHostAsmNoReturn/(int32_t eax)/;
1159
1160	/** @name Various items that are frequently accessed.
1161	* @{ */
1162	/** The main execution engine, VM_EXEC_ENGINE_XXX.
1163	* This is set early during vmR3InitRing3 by HM or NEM. */
1164	uint8_t const bMainExecutionEngine;
1165
1166	/** Whether to recompile user mode code or run it raw/hm/nem.
1167	* In non-raw-mode both fRecompileUser and fRecompileSupervisor must be set
1168	* to recompiler stuff. */
1169	bool fRecompileUser;
1170	/** Whether to recompile supervisor mode code or run it raw/hm/nem.
1171	* In non-raw-mode both fRecompileUser and fRecompileSupervisor must be set
1172	* to recompiler stuff. */
1173	bool fRecompileSupervisor;
1174	/** Whether raw mode supports ring-1 code or not.
1175	* This will be cleared when not in raw-mode. */
1176	bool fRawRing1Enabled;
1177	/** PATM enabled flag.
1178	* This is placed here for performance reasons.
1179	* This will be cleared when not in raw-mode. */
1180	bool fPATMEnabled;
1181	/** CSAM enabled flag.
1182	* This is placed here for performance reasons.
1183	* This will be cleared when not in raw-mode. */
1184	bool fCSAMEnabled;
1185
1186	/** Hardware VM support is available and enabled.
1187	* Determined very early during init.
1188	* This is placed here for performance reasons.
1189	* @todo obsoleted by bMainExecutionEngine, eliminate. */
1190	bool fHMEnabled;
1191	/** Hardware VM support requires a minimal raw-mode context.
1192	* This is never set on 64-bit hosts, only 32-bit hosts requires it. */
1193	bool fHMNeedRawModeCtx;
1194
1195	/** Set when this VM is the master FT node.
1196	* @todo This doesn't need to be here, FTM should store it in it's own
1197	* structures instead. */
1198	bool fFaultTolerantMaster;
1199	/** Large page enabled flag.
1200	* @todo This doesn't need to be here, PGM should store it in it's own
1201	* structures instead. */
1202	bool fUseLargePages;
1203	/** @} */
1204
1205	/** Alignment padding. */
1206	uint8_t uPadding1[2];
1207
1208	/** @name Debugging
1209	* @{ */
1210	/** Raw-mode Context VM Pointer. */
1211	RCPTRTYPE(RTTRACEBUF) hTraceBufRC;
1212	/** Ring-3 Host Context VM Pointer. */
1213	R3PTRTYPE(RTTRACEBUF) hTraceBufR3;
1214	/** Ring-0 Host Context VM Pointer. */
1215	R0PTRTYPE(RTTRACEBUF) hTraceBufR0;
1216	/** @} */
1217
1218	#if HC_ARCH_BITS == 32
1219	/** Alignment padding. */
1220	uint32_t uPadding2;
1221	#endif
1222
1223	/** @name Switcher statistics (remove)
1224	* @{ */
1225	/** Profiling the total time from Qemu to GC. */
1226	STAMPROFILEADV StatTotalQemuToGC;
1227	/** Profiling the total time from GC to Qemu. */
1228	STAMPROFILEADV StatTotalGCToQemu;
1229	/** Profiling the total time spent in GC. */
1230	STAMPROFILEADV StatTotalInGC;
1231	/** Profiling the total time spent not in Qemu. */
1232	STAMPROFILEADV StatTotalInQemu;
1233	/** Profiling the VMMSwitcher code for going to GC. */
1234	STAMPROFILEADV StatSwitcherToGC;
1235	/** Profiling the VMMSwitcher code for going to HC. */
1236	STAMPROFILEADV StatSwitcherToHC;
1237	STAMPROFILEADV StatSwitcherSaveRegs;
1238	STAMPROFILEADV StatSwitcherSysEnter;
1239	STAMPROFILEADV StatSwitcherDebug;
1240	STAMPROFILEADV StatSwitcherCR0;
1241	STAMPROFILEADV StatSwitcherCR4;
1242	STAMPROFILEADV StatSwitcherJmpCR3;
1243	STAMPROFILEADV StatSwitcherRstrRegs;
1244	STAMPROFILEADV StatSwitcherLgdt;
1245	STAMPROFILEADV StatSwitcherLidt;
1246	STAMPROFILEADV StatSwitcherLldt;
1247	STAMPROFILEADV StatSwitcherTSS;
1248	/** @} */
1249
1250	/** Padding - the unions must be aligned on a 64 bytes boundary and the unions
1251	* must start at the same offset on both 64-bit and 32-bit hosts. */
1252	uint8_t abAlignment3[(HC_ARCH_BITS == 32 ? 24 : 0) + 40];
1253
1254	/** CPUM part. */
1255	union
1256	{
1257	#ifdef ___CPUMInternal_h
1258	struct CPUM s;
1259	#endif
1260	#ifdef ___VBox_vmm_cpum_h
1261	/** Read only info exposed about the host and guest CPUs. */
1262	struct
1263	{
1264	/** Padding for hidden fields. */
1265	uint8_t abHidden0[64];
1266	/** Host CPU feature information. */
1267	CPUMFEATURES HostFeatures;
1268	/** Guest CPU feature information. */
1269	CPUMFEATURES GuestFeatures;
1270	} const ro;
1271	#endif
1272	uint8_t padding[1536]; /* multiple of 64 */
1273	} cpum;
1274
1275	/** VMM part. */
1276	union
1277	{
1278	#ifdef ___VMMInternal_h
1279	struct VMM s;
1280	#endif
1281	uint8_t padding[1600]; /* multiple of 64 */
1282	} vmm;
1283
1284	/** PGM part. */
1285	union
1286	{
1287	#ifdef ___PGMInternal_h
1288	struct PGM s;
1289	#endif
1290	uint8_t padding[40962+6080]; / multiple of 64 */
1291	} pgm;
1292
1293	/** HM part. */
1294	union
1295	{
1296	#ifdef ___HMInternal_h
1297	struct HM s;
1298	#endif
1299	uint8_t padding[5440]; /* multiple of 64 */
1300	} hm;
1301
1302	/** TRPM part. */
1303	union
1304	{
1305	#ifdef ___TRPMInternal_h
1306	struct TRPM s;
1307	#endif
1308	uint8_t padding[5248]; /* multiple of 64 */
1309	} trpm;
1310
1311	/** SELM part. */
1312	union
1313	{
1314	#ifdef ___SELMInternal_h
1315	struct SELM s;
1316	#endif
1317	uint8_t padding[768]; /* multiple of 64 */
1318	} selm;
1319
1320	/** MM part. */
1321	union
1322	{
1323	#ifdef ___MMInternal_h
1324	struct MM s;
1325	#endif
1326	uint8_t padding[192]; /* multiple of 64 */
1327	} mm;
1328
1329	/** PDM part. */
1330	union
1331	{
1332	#ifdef ___PDMInternal_h
1333	struct PDM s;
1334	#endif
1335	uint8_t padding[1920]; /* multiple of 64 */
1336	} pdm;
1337
1338	/** IOM part. */
1339	union
1340	{
1341	#ifdef ___IOMInternal_h
1342	struct IOM s;
1343	#endif
1344	uint8_t padding[896]; /* multiple of 64 */
1345	} iom;
1346
1347	/** EM part. */
1348	union
1349	{
1350	#ifdef ___EMInternal_h
1351	struct EM s;
1352	#endif
1353	uint8_t padding[256]; /* multiple of 64 */
1354	} em;
1355
1356	/** NEM part. */
1357	union
1358	{
1359	#ifdef ___NEMInternal_h
1360	struct NEM s;
1361	#endif
1362	uint8_t padding[128]; /* multiple of 64 */
1363	} nem;
1364
1365	/** TM part. */
1366	union
1367	{
1368	#ifdef ___TMInternal_h
1369	struct TM s;
1370	#endif
1371	uint8_t padding[2496]; /* multiple of 64 */
1372	} tm;
1373
1374	/** DBGF part. */
1375	union
1376	{
1377	#ifdef ___DBGFInternal_h
1378	struct DBGF s;
1379	#endif
1380	#ifdef ___VBox_vmm_dbgf_h
1381	/** Read only info exposed about interrupt breakpoints and selected events. */
1382	struct
1383	{
1384	/** Bitmap of enabled hardware interrupt breakpoints. */
1385	uint32_t bmHardIntBreakpoints[256 / 32];
1386	/** Bitmap of enabled software interrupt breakpoints. */
1387	uint32_t bmSoftIntBreakpoints[256 / 32];
1388	/** Bitmap of selected events.
1389	* This includes non-selectable events too for simplicity, we maintain the
1390	* state for some of these, as it may come in handy. */
1391	uint64_t bmSelectedEvents[(DBGFEVENT_END + 63) / 64];
1392	/** Enabled hardware interrupt breakpoints. */
1393	uint32_t cHardIntBreakpoints;
1394	/** Enabled software interrupt breakpoints. */
1395	uint32_t cSoftIntBreakpoints;
1396	/** The number of selected events. */
1397	uint32_t cSelectedEvents;
1398	/** The number of enabled hardware breakpoints. */
1399	uint8_t cEnabledHwBreakpoints;
1400	/** The number of enabled hardware I/O breakpoints. */
1401	uint8_t cEnabledHwIoBreakpoints;
1402	/** The number of enabled INT3 breakpoints. */
1403	uint8_t cEnabledInt3Breakpoints;
1404	uint8_t abPadding[1]; /*< Unused padding space up for grabs. /
1405	} const ro;
1406	#endif
1407	uint8_t padding[2432]; /* multiple of 64 */
1408	} dbgf;
1409
1410	/** SSM part. */
1411	union
1412	{
1413	#ifdef ___SSMInternal_h
1414	struct SSM s;
1415	#endif
1416	uint8_t padding[128]; /* multiple of 64 */
1417	} ssm;
1418
1419	/** FTM part. */
1420	union
1421	{
1422	#ifdef ___FTMInternal_h
1423	struct FTM s;
1424	#endif
1425	uint8_t padding[512]; /* multiple of 64 */
1426	} ftm;
1427
1428	#ifdef VBOX_WITH_RAW_MODE
1429	/** PATM part. */
1430	union
1431	{
1432	# ifdef ___PATMInternal_h
1433	struct PATM s;
1434	# endif
1435	uint8_t padding[768]; /* multiple of 64 */
1436	} patm;
1437
1438	/** CSAM part. */
1439	union
1440	{
1441	# ifdef ___CSAMInternal_h
1442	struct CSAM s;
1443	# endif
1444	uint8_t padding[1088]; /* multiple of 64 */
1445	} csam;
1446	#endif
1447
1448	#ifdef VBOX_WITH_REM
1449	/** REM part. */
1450	union
1451	{
1452	# ifdef ___REMInternal_h
1453	struct REM s;
1454	# endif
1455	uint8_t padding[0x11100]; /* multiple of 64 */
1456	} rem;
1457	#endif
1458
1459	union
1460	{
1461	#ifdef ___GIMInternal_h
1462	struct GIM s;
1463	#endif
1464	uint8_t padding[448]; /* multiple of 64 */
1465	} gim;
1466
1467	union
1468	{
1469	#ifdef ___APICInternal_h
1470	struct APIC s;
1471	#endif
1472	uint8_t padding[128]; /* multiple of 8 */
1473	} apic;
1474
1475	/* ---- begin small stuff ---- */
1476
1477	/** VM part. */
1478	union
1479	{
1480	#ifdef ___VMInternal_h
1481	struct VMINT s;
1482	#endif
1483	uint8_t padding[32]; /* multiple of 8 */
1484	} vm;
1485
1486	/** CFGM part. */
1487	union
1488	{
1489	#ifdef ___CFGMInternal_h
1490	struct CFGM s;
1491	#endif
1492	uint8_t padding[8]; /* multiple of 8 */
1493	} cfgm;
1494
1495	/** Padding for aligning the cpu array on a page boundary. */
1496	#if defined(VBOX_WITH_REM) && defined(VBOX_WITH_RAW_MODE)
1497	uint8_t abAlignment2[3670];
1498	#elif defined(VBOX_WITH_REM) && !defined(VBOX_WITH_RAW_MODE)
1499	uint8_t abAlignment2[1430];
1500	#elif !defined(VBOX_WITH_REM) && defined(VBOX_WITH_RAW_MODE)
1501	uint8_t abAlignment2[3926];
1502	#else
1503	uint8_t abAlignment2[1686];
1504	#endif
1505
1506	/* ---- end small stuff ---- */
1507
1508	/** VMCPU array for the configured number of virtual CPUs.
1509	* Must be aligned on a page boundary for TLB hit reasons as well as
1510	* alignment of VMCPU members. */
1511	VMCPU aCpus[1];
1512	} VM;
1513
1514
1515	#ifdef IN_RC
1516	RT_C_DECLS_BEGIN
1517
1518	/** The VM structure.
1519	* This is imported from the VMMRCBuiltin module, i.e. it's a one of those magic
1520	* globals which we should avoid using.
1521	*/
1522	extern DECLIMPORT(VM) g_VM;
1523
1524	RT_C_DECLS_END
1525	#endif
1526
1527	/** @} */
1528
1529	#endif
1530

Note: See TracBrowser for help on using the repository browser.

source: vbox/trunk/include/VBox/vmm/vm.h@ 74796

Download in other formats: