vm.h@ 74865

Last change on this file since 74865 was 74835, checked in by vboxsync, 6 years ago
vm.h: Enabled 64-bit VMCPU FFs. bugref:9180
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1	/** @file
2	* VM - The Virtual Machine, data.
3	*/
4
5	/*
6	* Copyright (C) 2006-2017 Oracle Corporation
7	*
8	* This file is part of VirtualBox Open Source Edition (OSE), as
9	* available from http://www.virtualbox.org. This file is free software;
10	* you can redistribute it and/or modify it under the terms of the GNU
11	* General Public License (GPL) as published by the Free Software
12	* Foundation, in version 2 as it comes in the "COPYING" file of the
13	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15	*
16	* The contents of this file may alternatively be used under the terms
17	* of the Common Development and Distribution License Version 1.0
18	* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19	* VirtualBox OSE distribution, in which case the provisions of the
20	* CDDL are applicable instead of those of the GPL.
21	*
22	* You may elect to license modified versions of this file under the
23	* terms and conditions of either the GPL or the CDDL or both.
24	*/
25
26	#ifndef ___VBox_vmm_vm_h
27	#define ___VBox_vmm_vm_h
28
29	#ifndef VBOX_FOR_DTRACE_LIB
30	# include <iprt/param.h>
31	# include <VBox/types.h>
32	# include <VBox/vmm/cpum.h>
33	# include <VBox/vmm/stam.h>
34	# include <VBox/vmm/vmapi.h>
35	# include <VBox/vmm/vmm.h>
36	# include <VBox/sup.h>
37	#else
38	# pragma D depends_on library vbox-types.d
39	# pragma D depends_on library CPUMInternal.d
40	# define ___CPUMInternal_h
41	#endif
42
43
44
45	/** @defgroup grp_vm The Virtual Machine
46	* @ingroup grp_vmm
47	* @{
48	*/
49
50	/**
51	* The state of a Virtual CPU.
52	*
53	* The basic state indicated here is whether the CPU has been started or not. In
54	* addition, there are sub-states when started for assisting scheduling (GVMM
55	* mostly).
56	*
57	* The transition out of the STOPPED state is done by a vmR3PowerOn.
58	* The transition back to the STOPPED state is done by vmR3PowerOff.
59	*
60	* (Alternatively we could let vmR3PowerOn start CPU 0 only and let the SPIP
61	* handling switch on the other CPUs. Then vmR3Reset would stop all but CPU 0.)
62	*/
63	typedef enum VMCPUSTATE
64	{
65	/** The customary invalid zero. */
66	VMCPUSTATE_INVALID = 0,
67
68	/** Virtual CPU has not yet been started. */
69	VMCPUSTATE_STOPPED,
70
71	/** CPU started. */
72	VMCPUSTATE_STARTED,
73	/** CPU started in HM context. */
74	VMCPUSTATE_STARTED_HM,
75	/** Executing guest code and can be poked (RC or STI bits of HM). */
76	VMCPUSTATE_STARTED_EXEC,
77	/** Executing guest code in the recompiler. */
78	VMCPUSTATE_STARTED_EXEC_REM,
79	/** Executing guest code using NEM. */
80	VMCPUSTATE_STARTED_EXEC_NEM,
81	VMCPUSTATE_STARTED_EXEC_NEM_WAIT,
82	VMCPUSTATE_STARTED_EXEC_NEM_CANCELED,
83	/** Halted. */
84	VMCPUSTATE_STARTED_HALTED,
85
86	/** The end of valid virtual CPU states. */
87	VMCPUSTATE_END,
88
89	/** Ensure 32-bit type. */
90	VMCPUSTATE_32BIT_HACK = 0x7fffffff
91	} VMCPUSTATE;
92
93	/** Enables 64-bit FFs. */
94	#define VMCPU_WITH_64_BIT_FFS
95
96
97	/**
98	* The cross context virtual CPU structure.
99	*
100	* Run 'kmk run-struct-tests' (from src/VBox/VMM if you like) after updating!
101	*/
102	typedef struct VMCPU
103	{
104	/** @name Volatile per-cpu data.
105	* @{ */
106	/** Per CPU forced action.
107	* See the VMCPU_FF_* \#defines. Updated atomically. */
108	#ifdef VMCPU_WITH_64_BIT_FFS
109	uint64_t volatile fLocalForcedActions;
110	#else
111	uint32_t volatile fLocalForcedActions;
112	uint32_t fForLocalForcedActionsExpansion;
113	#endif
114	/** The CPU state. */
115	VMCPUSTATE volatile enmState;
116
117	/** Which host CPU ID is this EMT running on.
118	* Only valid when in RC or HMR0 with scheduling disabled. */
119	RTCPUID volatile idHostCpu;
120	/** The CPU set index corresponding to idHostCpu, UINT32_MAX if not valid.
121	* @remarks Best to make sure iHostCpuSet shares cache line with idHostCpu! */
122	uint32_t volatile iHostCpuSet;
123	/** Padding up to 64 bytes. */
124	uint8_t abAlignment0[64 - 20];
125	/** @} */
126
127	/** IEM part.
128	* @remarks This comes first as it allows the use of 8-bit immediates for the
129	* first 64 bytes of the structure, reducing code size a wee bit. */
130	#ifdef ___IEMInternal_h /* For PDB hacking. */
131	union VMCPUUNIONIEMFULL
132	#else
133	union VMCPUUNIONIEMSTUB
134	#endif
135	{
136	#ifdef ___IEMInternal_h
137	struct IEMCPU s;
138	#endif
139	uint8_t padding[18496]; /* multiple of 64 */
140	} iem;
141
142	/** @name Static per-cpu data.
143	* (Putting this after IEM, hoping that it's less frequently used than it.)
144	* @{ */
145	/** The CPU ID.
146	* This is the index into the VM::aCpu array. */
147	VMCPUID idCpu;
148	/** Raw-mode Context VM Pointer. */
149	PVMRC pVMRC;
150	/** Ring-3 Host Context VM Pointer. */
151	PVMR3 pVMR3;
152	/** Ring-0 Host Context VM Pointer. */
153	PVMR0 pVMR0;
154	/** Pointer to the ring-3 UVMCPU structure. */
155	PUVMCPU pUVCpu;
156	/** The native thread handle. */
157	RTNATIVETHREAD hNativeThread;
158	/** The native R0 thread handle. (different from the R3 handle!) */
159	RTNATIVETHREAD hNativeThreadR0;
160	/** Align the structures below bit on a 64-byte boundary and make sure it starts
161	* at the same offset in both 64-bit and 32-bit builds.
162	*
163	* @remarks The alignments of the members that are larger than 48 bytes should be
164	* 64-byte for cache line reasons. structs containing small amounts of
165	* data could be lumped together at the end with a < 64 byte padding
166	* following it (to grow into and align the struct size).
167	*/
168	uint8_t abAlignment1[64 - 4 - 4 - 5 * (HC_ARCH_BITS == 64 ? 8 : 4)];
169	/** @} */
170
171	/** HM part. */
172	union VMCPUUNIONHM
173	{
174	#ifdef ___HMInternal_h
175	struct HMCPU s;
176	#endif
177	uint8_t padding[5888]; /* multiple of 64 */
178	} hm;
179
180	/** NEM part. */
181	union VMCPUUNIONNEM
182	{
183	#ifdef ___NEMInternal_h
184	struct NEMCPU s;
185	#endif
186	uint8_t padding[512]; /* multiple of 64 */
187	} nem;
188
189	/** TRPM part. */
190	union VMCPUUNIONTRPM
191	{
192	#ifdef ___TRPMInternal_h
193	struct TRPMCPU s;
194	#endif
195	uint8_t padding[128]; /* multiple of 64 */
196	} trpm;
197
198	/** TM part. */
199	union VMCPUUNIONTM
200	{
201	#ifdef ___TMInternal_h
202	struct TMCPU s;
203	#endif
204	uint8_t padding[384]; /* multiple of 64 */
205	} tm;
206
207	/** VMM part. */
208	union VMCPUUNIONVMM
209	{
210	#ifdef ___VMMInternal_h
211	struct VMMCPU s;
212	#endif
213	uint8_t padding[768]; /* multiple of 64 */
214	} vmm;
215
216	/** PDM part. */
217	union VMCPUUNIONPDM
218	{
219	#ifdef ___PDMInternal_h
220	struct PDMCPU s;
221	#endif
222	uint8_t padding[256]; /* multiple of 64 */
223	} pdm;
224
225	/** IOM part. */
226	union VMCPUUNIONIOM
227	{
228	#ifdef ___IOMInternal_h
229	struct IOMCPU s;
230	#endif
231	uint8_t padding[512]; /* multiple of 64 */
232	} iom;
233
234	/** DBGF part.
235	* @todo Combine this with other tiny structures. */
236	union VMCPUUNIONDBGF
237	{
238	#ifdef ___DBGFInternal_h
239	struct DBGFCPU s;
240	#endif
241	uint8_t padding[256]; /* multiple of 64 */
242	} dbgf;
243
244	/** GIM part. */
245	union VMCPUUNIONGIM
246	{
247	#ifdef ___GIMInternal_h
248	struct GIMCPU s;
249	#endif
250	uint8_t padding[512]; /* multiple of 64 */
251	} gim;
252
253	/** APIC part. */
254	union VMCPUUNIONAPIC
255	{
256	#ifdef ___APICInternal_h
257	struct APICCPU s;
258	#endif
259	uint8_t padding[1792]; /* multiple of 64 */
260	} apic;
261
262	/*
263	* Some less frequently used global members that doesn't need to take up
264	* precious space at the head of the structure.
265	*/
266
267	/** Trace groups enable flags. */
268	uint32_t fTraceGroups; /* 64 / 44 */
269	/** State data for use by ad hoc profiling. */
270	uint32_t uAdHoc;
271	/** Profiling samples for use by ad hoc profiling. */
272	STAMPROFILEADV aStatAdHoc[8]; /* size: 408 = 320 /
273
274	/** Align the following members on page boundary. */
275	uint8_t abAlignment2[2808];
276
277	/** PGM part. */
278	union VMCPUUNIONPGM
279	{
280	#ifdef ___PGMInternal_h
281	struct PGMCPU s;
282	#endif
283	uint8_t padding[4096]; /* multiple of 4096 */
284	} pgm;
285
286	/** CPUM part. */
287	union VMCPUUNIONCPUM
288	{
289	#ifdef ___CPUMInternal_h
290	struct CPUMCPU s;
291	#endif
292	#ifdef VMCPU_INCL_CPUM_GST_CTX
293	/** The guest CPUM context for direct use by execution engines.
294	* This is not for general consumption, but for HM, REM, IEM, and maybe a few
295	* others. The rest will use the function based CPUM API. */
296	CPUMCTX GstCtx;
297	#endif
298	uint8_t padding[4096]; /* multiple of 4096 */
299	} cpum;
300
301	/** EM part. */
302	union VMCPUUNIONEM
303	{
304	#ifdef ___EMInternal_h
305	struct EMCPU s;
306	#endif
307	uint8_t padding[40960]; /* multiple of 4096 */
308	} em;
309	} VMCPU;
310
311
312	#ifndef VBOX_FOR_DTRACE_LIB
313
314	/** @name Operations on VMCPU::enmState
315	* @{ */
316	/** Gets the VMCPU state. */
317	#define VMCPU_GET_STATE(pVCpu) ( (pVCpu)->enmState )
318	/** Sets the VMCPU state. */
319	#define VMCPU_SET_STATE(pVCpu, enmNewState) \
320	ASMAtomicWriteU32((uint32_t volatile *)&(pVCpu)->enmState, (enmNewState))
321	/** Cmpares and sets the VMCPU state. */
322	#define VMCPU_CMPXCHG_STATE(pVCpu, enmNewState, enmOldState) \
323	ASMAtomicCmpXchgU32((uint32_t volatile *)&(pVCpu)->enmState, (enmNewState), (enmOldState))
324	/** Checks the VMCPU state. */
325	#ifdef VBOX_STRICT
326	# define VMCPU_ASSERT_STATE(pVCpu, enmExpectedState) \
327	do { \
328	VMCPUSTATE enmState = VMCPU_GET_STATE(pVCpu); \
329	AssertMsg(enmState == (enmExpectedState), \
330	("enmState=%d enmExpectedState=%d idCpu=%u\n", \
331	enmState, enmExpectedState, (pVCpu)->idCpu)); \
332	} while (0)
333	#else
334	# define VMCPU_ASSERT_STATE(pVCpu, enmExpectedState) do { } while (0)
335	#endif
336	/** Tests if the state means that the CPU is started. */
337	#define VMCPUSTATE_IS_STARTED(enmState) ( (enmState) > VMCPUSTATE_STOPPED )
338	/** Tests if the state means that the CPU is stopped. */
339	#define VMCPUSTATE_IS_STOPPED(enmState) ( (enmState) == VMCPUSTATE_STOPPED )
340	/** @} */
341
342
343	/** The name of the raw-mode context VMM Core module. */
344	#define VMMRC_MAIN_MODULE_NAME "VMMRC.rc"
345	/** The name of the ring-0 context VMM Core module. */
346	#define VMMR0_MAIN_MODULE_NAME "VMMR0.r0"
347
348	/**
349	* Wrapper macro for avoiding too much \#ifdef VBOX_WITH_RAW_MODE.
350	*/
351	#ifdef VBOX_WITH_RAW_MODE
352	# define VM_WHEN_RAW_MODE(a_WithExpr, a_WithoutExpr) a_WithExpr
353	#else
354	# define VM_WHEN_RAW_MODE(a_WithExpr, a_WithoutExpr) a_WithoutExpr
355	#endif
356
357
358	/** VM Forced Action Flags.
359	*
360	* Use the VM_FF_SET() and VM_FF_CLEAR() macros to change the force
361	* action mask of a VM.
362	*
363	* Available VM bits:
364	* 0, 1, 5, 6, 7, 13, 14, 15, 16, 17, 21, 22, 23, 24, 25, 26, 27, 28, 30
365	*
366	*
367	* Available VMCPU bits:
368	* 14, 15
369	*
370	* @todo If we run low on VMCPU, we may consider merging the SELM bits
371	*
372	* @{
373	*/
374	/** The virtual sync clock has been stopped, go to TM until it has been
375	* restarted... */
376	#define VM_FF_TM_VIRTUAL_SYNC RT_BIT_32(VM_FF_TM_VIRTUAL_SYNC_BIT)
377	#define VM_FF_TM_VIRTUAL_SYNC_BIT 2
378	/** PDM Queues are pending. */
379	#define VM_FF_PDM_QUEUES RT_BIT_32(VM_FF_PDM_QUEUES_BIT)
380	/** The bit number for VM_FF_PDM_QUEUES. */
381	#define VM_FF_PDM_QUEUES_BIT 3
382	/** PDM DMA transfers are pending. */
383	#define VM_FF_PDM_DMA RT_BIT_32(VM_FF_PDM_DMA_BIT)
384	/** The bit number for VM_FF_PDM_DMA. */
385	#define VM_FF_PDM_DMA_BIT 4
386	/** This action forces the VM to call DBGF so DBGF can service debugger
387	* requests in the emulation thread.
388	* This action flag stays asserted till DBGF clears it.*/
389	#define VM_FF_DBGF RT_BIT_32(VM_FF_DBGF_BIT)
390	/** The bit number for VM_FF_DBGF. */
391	#define VM_FF_DBGF_BIT 8
392	/** This action forces the VM to service pending requests from other
393	* thread or requests which must be executed in another context. */
394	#define VM_FF_REQUEST RT_BIT_32(VM_FF_REQUEST_BIT)
395	#define VM_FF_REQUEST_BIT 9
396	/** Check for VM state changes and take appropriate action. */
397	#define VM_FF_CHECK_VM_STATE RT_BIT_32(VM_FF_CHECK_VM_STATE_BIT)
398	/** The bit number for VM_FF_CHECK_VM_STATE. */
399	#define VM_FF_CHECK_VM_STATE_BIT 10
400	/** Reset the VM. (postponed) */
401	#define VM_FF_RESET RT_BIT_32(VM_FF_RESET_BIT)
402	/** The bit number for VM_FF_RESET. */
403	#define VM_FF_RESET_BIT 11
404	/** EMT rendezvous in VMM. */
405	#define VM_FF_EMT_RENDEZVOUS RT_BIT_32(VM_FF_EMT_RENDEZVOUS_BIT)
406	/** The bit number for VM_FF_EMT_RENDEZVOUS. */
407	#define VM_FF_EMT_RENDEZVOUS_BIT 12
408
409	/** PGM needs to allocate handy pages. */
410	#define VM_FF_PGM_NEED_HANDY_PAGES RT_BIT_32(VM_FF_PGM_NEED_HANDY_PAGES_BIT)
411	#define VM_FF_PGM_NEED_HANDY_PAGES_BIT 18
412	/** PGM is out of memory.
413	* Abandon all loops and code paths which can be resumed and get up to the EM
414	* loops. */
415	#define VM_FF_PGM_NO_MEMORY RT_BIT_32(VM_FF_PGM_NO_MEMORY_BIT)
416	#define VM_FF_PGM_NO_MEMORY_BIT 19
417	/** PGM is about to perform a lightweight pool flush
418	* Guest SMP: all EMT threads should return to ring 3
419	*/
420	#define VM_FF_PGM_POOL_FLUSH_PENDING RT_BIT_32(VM_FF_PGM_POOL_FLUSH_PENDING_BIT)
421	#define VM_FF_PGM_POOL_FLUSH_PENDING_BIT 20
422	/** REM needs to be informed about handler changes. */
423	#define VM_FF_REM_HANDLER_NOTIFY RT_BIT_32(VM_FF_REM_HANDLER_NOTIFY_BIT)
424	/** The bit number for VM_FF_REM_HANDLER_NOTIFY. */
425	#define VM_FF_REM_HANDLER_NOTIFY_BIT 29
426	/** Suspend the VM - debug only. */
427	#define VM_FF_DEBUG_SUSPEND RT_BIT_32(VM_FF_DEBUG_SUSPEND_BIT)
428	#define VM_FF_DEBUG_SUSPEND_BIT 31
429
430
431	/** This action forces the VM to check any pending interrupts on the APIC. */
432	#define VMCPU_FF_INTERRUPT_APIC RT_BIT_64(VMCPU_FF_INTERRUPT_APIC_BIT)
433	#define VMCPU_FF_INTERRUPT_APIC_BIT 0
434	/** This action forces the VM to check any pending interrups on the PIC. */
435	#define VMCPU_FF_INTERRUPT_PIC RT_BIT_64(VMCPU_FF_INTERRUPT_PIC_BIT)
436	#define VMCPU_FF_INTERRUPT_PIC_BIT 1
437	/** This action forces the VM to schedule and run pending timer (TM).
438	* @remarks Don't move - PATM compatibility. */
439	#define VMCPU_FF_TIMER RT_BIT_64(VMCPU_FF_TIMER_BIT)
440	#define VMCPU_FF_TIMER_BIT 2
441	/** This action forces the VM to check any pending NMIs. */
442	#define VMCPU_FF_INTERRUPT_NMI RT_BIT_64(VMCPU_FF_INTERRUPT_NMI_BIT)
443	#define VMCPU_FF_INTERRUPT_NMI_BIT 3
444	/** This action forces the VM to check any pending SMIs. */
445	#define VMCPU_FF_INTERRUPT_SMI RT_BIT_64(VMCPU_FF_INTERRUPT_SMI_BIT)
446	#define VMCPU_FF_INTERRUPT_SMI_BIT 4
447	/** PDM critical section unlocking is pending, process promptly upon return to R3. */
448	#define VMCPU_FF_PDM_CRITSECT RT_BIT_64(VMCPU_FF_PDM_CRITSECT_BIT)
449	#define VMCPU_FF_PDM_CRITSECT_BIT 5
450	/** Special EM internal force flag that is used by EMUnhaltAndWakeUp() to force
451	* the virtual CPU out of the next (/current) halted state. It is not processed
452	* nor cleared by emR3ForcedActions (similar to VMCPU_FF_BLOCK_NMIS), instead it
453	* is cleared the next time EM leaves the HALTED state. */
454	#define VMCPU_FF_UNHALT RT_BIT_64(VMCPU_FF_UNHALT_BIT)
455	#define VMCPU_FF_UNHALT_BIT 6
456	/** Pending IEM action (mask). */
457	#define VMCPU_FF_IEM RT_BIT_64(VMCPU_FF_IEM_BIT)
458	/** Pending IEM action (bit number). */
459	#define VMCPU_FF_IEM_BIT 7
460	/** Pending APIC action (bit number). */
461	#define VMCPU_FF_UPDATE_APIC_BIT 8
462	/** This action forces the VM to update APIC's asynchronously arrived
463	* interrupts as pending interrupts. */
464	#define VMCPU_FF_UPDATE_APIC RT_BIT_64(VMCPU_FF_UPDATE_APIC_BIT)
465	/** This action forces the VM to service pending requests from other
466	* thread or requests which must be executed in another context. */
467	#define VMCPU_FF_REQUEST RT_BIT_64(VMCPU_FF_REQUEST_BIT)
468	#define VMCPU_FF_REQUEST_BIT 9
469	/** Pending DBGF event (alternative to passing VINF_EM_DBG_EVENT around). */
470	#define VMCPU_FF_DBGF RT_BIT_64(VMCPU_FF_DBGF_BIT)
471	/** The bit number for VMCPU_FF_DBGF. */
472	#define VMCPU_FF_DBGF_BIT 10
473	/** Pending MTF (Monitor Trap Flag) event - Intel only. */
474	#define VMCPU_FF_MTF RT_BIT_64(VMCPU_FF_MTF_BIT)
475	/** The bit number for VMCPU_FF_MTF. */
476	#define VMCPU_FF_MTF_BIT 11
477	/** This action forces the VM to service any pending updates to CR3 (used only
478	* by HM). */
479	#define VMCPU_FF_HM_UPDATE_CR3 RT_BIT_64(VMCPU_FF_HM_UPDATE_CR3_BIT)
480	#define VMCPU_FF_HM_UPDATE_CR3_BIT 12
481	/** This action forces the VM to service any pending updates to PAE PDPEs (used
482	* only by HM). */
483	#define VMCPU_FF_HM_UPDATE_PAE_PDPES RT_BIT_64(VMCPU_FF_HM_UPDATE_PAE_PDPES_BIT)
484	#define VMCPU_FF_HM_UPDATE_PAE_PDPES_BIT 13
485	/** This action forces the VM to resync the page tables before going
486	* back to execute guest code. (GLOBAL FLUSH) */
487	#define VMCPU_FF_PGM_SYNC_CR3 RT_BIT_64(VMCPU_FF_PGM_SYNC_CR3_BIT)
488	#define VMCPU_FF_PGM_SYNC_CR3_BIT 16
489	/** Same as VM_FF_PGM_SYNC_CR3 except that global pages can be skipped.
490	* (NON-GLOBAL FLUSH) */
491	#define VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL RT_BIT_64(VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL_BIT)
492	#define VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL_BIT 17
493	/** Check for pending TLB shootdown actions (deprecated)
494	* Reserved for furture HM re-use if necessary / safe.
495	* Consumer: HM */
496	#define VMCPU_FF_TLB_SHOOTDOWN_UNUSED RT_BIT_64(VMCPU_FF_TLB_SHOOTDOWN_UNUSED_BIT)
497	#define VMCPU_FF_TLB_SHOOTDOWN_UNUSED_BIT 18
498	/** Check for pending TLB flush action.
499	* Consumer: HM
500	* @todo rename to VMCPU_FF_HM_TLB_FLUSH */
501	#define VMCPU_FF_TLB_FLUSH RT_BIT_64(VMCPU_FF_TLB_FLUSH_BIT)
502	/** The bit number for VMCPU_FF_TLB_FLUSH. */
503	#define VMCPU_FF_TLB_FLUSH_BIT 19
504	#ifdef VBOX_WITH_RAW_MODE
505	/** Check the interrupt and trap gates */
506	# define VMCPU_FF_TRPM_SYNC_IDT RT_BIT_64(VMCPU_FF_TRPM_SYNC_IDT_BIT)
507	# define VMCPU_FF_TRPM_SYNC_IDT_BIT 20
508	/** Check Guest's TSS ring 0 stack */
509	# define VMCPU_FF_SELM_SYNC_TSS RT_BIT_64(VMCPU_FF_SELM_SYNC_TSS_BIT)
510	# define VMCPU_FF_SELM_SYNC_TSS_BIT 21
511	/** Check Guest's GDT table */
512	# define VMCPU_FF_SELM_SYNC_GDT RT_BIT_64(VMCPU_FF_SELM_SYNC_GDT_BIT)
513	# define VMCPU_FF_SELM_SYNC_GDT_BIT 22
514	/** Check Guest's LDT table */
515	# define VMCPU_FF_SELM_SYNC_LDT RT_BIT_64(VMCPU_FF_SELM_SYNC_LDT_BIT)
516	# define VMCPU_FF_SELM_SYNC_LDT_BIT 23
517	#endif /* VBOX_WITH_RAW_MODE */
518	/** Inhibit interrupts pending. See EMGetInhibitInterruptsPC(). */
519	#define VMCPU_FF_INHIBIT_INTERRUPTS RT_BIT_64(VMCPU_FF_INHIBIT_INTERRUPTS_BIT)
520	#define VMCPU_FF_INHIBIT_INTERRUPTS_BIT 24
521	/** Block injection of non-maskable interrupts to the guest. */
522	#define VMCPU_FF_BLOCK_NMIS RT_BIT_64(VMCPU_FF_BLOCK_NMIS_BIT)
523	#define VMCPU_FF_BLOCK_NMIS_BIT 25
524	#ifdef VBOX_WITH_RAW_MODE
525	/** CSAM needs to scan the page that's being executed */
526	# define VMCPU_FF_CSAM_SCAN_PAGE RT_BIT_64(VMCPU_FF_CSAM_SCAN_PAGE_BIT)
527	# define VMCPU_FF_CSAM_SCAN_PAGE_BIT 26
528	/** CSAM needs to do some homework. */
529	# define VMCPU_FF_CSAM_PENDING_ACTION RT_BIT_64(VMCPU_FF_CSAM_PENDING_ACTION_BIT)
530	# define VMCPU_FF_CSAM_PENDING_ACTION_BIT 27
531	#endif /* VBOX_WITH_RAW_MODE */
532	/** Force return to Ring-3. */
533	#define VMCPU_FF_TO_R3 RT_BIT_64(VMCPU_FF_TO_R3_BIT)
534	#define VMCPU_FF_TO_R3_BIT 28
535	/** Force return to ring-3 to service pending I/O or MMIO write.
536	* This is a backup for mechanism VINF_IOM_R3_IOPORT_COMMIT_WRITE and
537	* VINF_IOM_R3_MMIO_COMMIT_WRITE, allowing VINF_EM_DBG_BREAKPOINT and similar
538	* status codes to be propagated at the same time without loss. */
539	#define VMCPU_FF_IOM RT_BIT_64(VMCPU_FF_IOM_BIT)
540	#define VMCPU_FF_IOM_BIT 29
541	#ifdef VBOX_WITH_RAW_MODE
542	/** CPUM need to adjust CR0.TS/EM before executing raw-mode code again. */
543	# define VMCPU_FF_CPUM RT_BIT_64(VMCPU_FF_CPUM_BIT)
544	/** The bit number for VMCPU_FF_CPUM. */
545	# define VMCPU_FF_CPUM_BIT 30
546	#endif /* VBOX_WITH_RAW_MODE */
547	/** Hardware virtualized nested-guest interrupt pending. */
548	#define VMCPU_FF_INTERRUPT_NESTED_GUEST RT_BIT_64(VMCPU_FF_INTERRUPT_NESTED_GUEST_BIT)
549	#define VMCPU_FF_INTERRUPT_NESTED_GUEST_BIT 31
550
551
552	/** Externally VM forced actions. Used to quit the idle/wait loop. */
553	#define VM_FF_EXTERNAL_SUSPENDED_MASK ( VM_FF_CHECK_VM_STATE \| VM_FF_DBGF \| VM_FF_REQUEST \| VM_FF_EMT_RENDEZVOUS )
554	/** Externally VMCPU forced actions. Used to quit the idle/wait loop. */
555	#define VMCPU_FF_EXTERNAL_SUSPENDED_MASK ( VMCPU_FF_REQUEST \| VMCPU_FF_DBGF )
556
557	/** Externally forced VM actions. Used to quit the idle/wait loop. */
558	#define VM_FF_EXTERNAL_HALTED_MASK ( VM_FF_CHECK_VM_STATE \| VM_FF_DBGF \| VM_FF_REQUEST \
559	\| VM_FF_PDM_QUEUES \| VM_FF_PDM_DMA \| VM_FF_EMT_RENDEZVOUS )
560	/** Externally forced VMCPU actions. Used to quit the idle/wait loop. */
561	#define VMCPU_FF_EXTERNAL_HALTED_MASK ( VMCPU_FF_UPDATE_APIC \| VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC \
562	\| VMCPU_FF_REQUEST \| VMCPU_FF_INTERRUPT_NMI \| VMCPU_FF_INTERRUPT_SMI \
563	\| VMCPU_FF_UNHALT \| VMCPU_FF_TIMER \| VMCPU_FF_DBGF )
564
565	/** High priority VM pre-execution actions. */
566	#define VM_FF_HIGH_PRIORITY_PRE_MASK ( VM_FF_CHECK_VM_STATE \| VM_FF_DBGF \| VM_FF_TM_VIRTUAL_SYNC \
567	\| VM_FF_DEBUG_SUSPEND \| VM_FF_PGM_NEED_HANDY_PAGES \| VM_FF_PGM_NO_MEMORY \
568	\| VM_FF_EMT_RENDEZVOUS )
569	/** High priority VMCPU pre-execution actions. */
570	#define VMCPU_FF_HIGH_PRIORITY_PRE_MASK ( VMCPU_FF_TIMER \| VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC \
571	\| VMCPU_FF_UPDATE_APIC \| VMCPU_FF_INHIBIT_INTERRUPTS \| VMCPU_FF_DBGF \
572	\| VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL \
573	\| VM_WHEN_RAW_MODE( VMCPU_FF_SELM_SYNC_TSS \| VMCPU_FF_TRPM_SYNC_IDT \
574	\| VMCPU_FF_SELM_SYNC_GDT \| VMCPU_FF_SELM_SYNC_LDT, 0 ) )
575
576	/** High priority VM pre raw-mode execution mask. */
577	#define VM_FF_HIGH_PRIORITY_PRE_RAW_MASK ( VM_FF_PGM_NEED_HANDY_PAGES \| VM_FF_PGM_NO_MEMORY )
578	/** High priority VMCPU pre raw-mode execution mask. */
579	#define VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK ( VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL \
580	\| VMCPU_FF_INHIBIT_INTERRUPTS \
581	\| VM_WHEN_RAW_MODE( VMCPU_FF_SELM_SYNC_TSS \| VMCPU_FF_TRPM_SYNC_IDT \
582	\| VMCPU_FF_SELM_SYNC_GDT \| VMCPU_FF_SELM_SYNC_LDT, 0) )
583
584	/** High priority post-execution actions. */
585	#define VM_FF_HIGH_PRIORITY_POST_MASK ( VM_FF_PGM_NO_MEMORY )
586	/** High priority post-execution actions. */
587	#define VMCPU_FF_HIGH_PRIORITY_POST_MASK ( VMCPU_FF_PDM_CRITSECT \| VM_WHEN_RAW_MODE(VMCPU_FF_CSAM_PENDING_ACTION, 0) \
588	\| VMCPU_FF_HM_UPDATE_CR3 \| VMCPU_FF_HM_UPDATE_PAE_PDPES \
589	\| VMCPU_FF_IEM \| VMCPU_FF_IOM )
590
591	/** Normal priority VM post-execution actions. */
592	#define VM_FF_NORMAL_PRIORITY_POST_MASK ( VM_FF_CHECK_VM_STATE \| VM_FF_DBGF \| VM_FF_RESET \
593	\| VM_FF_PGM_NO_MEMORY \| VM_FF_EMT_RENDEZVOUS)
594	/** Normal priority VMCPU post-execution actions. */
595	#define VMCPU_FF_NORMAL_PRIORITY_POST_MASK ( VM_WHEN_RAW_MODE(VMCPU_FF_CSAM_SCAN_PAGE, 0) \| VMCPU_FF_DBGF )
596
597	/** Normal priority VM actions. */
598	#define VM_FF_NORMAL_PRIORITY_MASK ( VM_FF_REQUEST \| VM_FF_PDM_QUEUES \| VM_FF_PDM_DMA \
599	\| VM_FF_REM_HANDLER_NOTIFY \| VM_FF_EMT_RENDEZVOUS)
600	/** Normal priority VMCPU actions. */
601	#define VMCPU_FF_NORMAL_PRIORITY_MASK ( VMCPU_FF_REQUEST )
602
603	/** Flags to clear before resuming guest execution. */
604	#define VMCPU_FF_RESUME_GUEST_MASK ( VMCPU_FF_TO_R3 )
605
606
607	/** VM flags that cause the REP[\|NE\|E] STRINS loops to yield immediately. */
608	#define VM_FF_HIGH_PRIORITY_POST_REPSTR_MASK ( VM_FF_TM_VIRTUAL_SYNC \| VM_FF_PGM_NEED_HANDY_PAGES \| VM_FF_PGM_NO_MEMORY \
609	\| VM_FF_EMT_RENDEZVOUS \| VM_FF_PGM_POOL_FLUSH_PENDING \| VM_FF_RESET)
610	/** VM flags that cause the REP[\|NE\|E] STRINS loops to yield. */
611	#define VM_FF_YIELD_REPSTR_MASK ( VM_FF_HIGH_PRIORITY_POST_REPSTR_MASK \
612	\| VM_FF_PDM_QUEUES \| VM_FF_PDM_DMA \| VM_FF_DBGF \| VM_FF_DEBUG_SUSPEND )
613	/** VMCPU flags that cause the REP[\|NE\|E] STRINS loops to yield immediately. */
614	#ifdef IN_RING3
615	# define VMCPU_FF_HIGH_PRIORITY_POST_REPSTR_MASK ( VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL \| VMCPU_FF_DBGF )
616	#else
617	# define VMCPU_FF_HIGH_PRIORITY_POST_REPSTR_MASK ( VMCPU_FF_TO_R3 \| VMCPU_FF_IEM \| VMCPU_FF_IOM \| VMCPU_FF_PGM_SYNC_CR3 \
618	\| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL \| VMCPU_FF_DBGF )
619	#endif
620	/** VMCPU flags that cause the REP[\|NE\|E] STRINS loops to yield, interrupts
621	* enabled. */
622	#define VMCPU_FF_YIELD_REPSTR_MASK ( VMCPU_FF_HIGH_PRIORITY_POST_REPSTR_MASK \
623	\| VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_UPDATE_APIC \| VMCPU_FF_INTERRUPT_PIC \
624	\| VMCPU_FF_INTERRUPT_NMI \| VMCPU_FF_INTERRUPT_SMI \| VMCPU_FF_PDM_CRITSECT \
625	\| VMCPU_FF_TIMER \| VMCPU_FF_REQUEST )
626	/** VMCPU flags that cause the REP[\|NE\|E] STRINS loops to yield, interrupts
627	* disabled. */
628	#define VMCPU_FF_YIELD_REPSTR_NOINT_MASK ( VMCPU_FF_YIELD_REPSTR_MASK \
629	& ~(VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_UPDATE_APIC \| VMCPU_FF_INTERRUPT_PIC) )
630
631	/** VM Flags that cause the HM loops to go back to ring-3. */
632	#define VM_FF_HM_TO_R3_MASK ( VM_FF_TM_VIRTUAL_SYNC \| VM_FF_PGM_NEED_HANDY_PAGES \| VM_FF_PGM_NO_MEMORY \
633	\| VM_FF_PDM_QUEUES \| VM_FF_EMT_RENDEZVOUS)
634	/** VMCPU Flags that cause the HM loops to go back to ring-3. */
635	#define VMCPU_FF_HM_TO_R3_MASK ( VMCPU_FF_TO_R3 \| VMCPU_FF_TIMER \| VMCPU_FF_PDM_CRITSECT \
636	\| VMCPU_FF_IEM \| VMCPU_FF_IOM)
637
638	/** High priority ring-0 VM pre HM-mode execution mask. */
639	#define VM_FF_HP_R0_PRE_HM_MASK (VM_FF_HM_TO_R3_MASK \| VM_FF_REQUEST \| VM_FF_PGM_POOL_FLUSH_PENDING \| VM_FF_PDM_DMA)
640	/** High priority ring-0 VMCPU pre HM-mode execution mask. */
641	#define VMCPU_FF_HP_R0_PRE_HM_MASK ( VMCPU_FF_HM_TO_R3_MASK \| VMCPU_FF_PGM_SYNC_CR3 \
642	\| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL \| VMCPU_FF_REQUEST)
643	/** High priority ring-0 VM pre HM-mode execution mask, single stepping. */
644	#define VM_FF_HP_R0_PRE_HM_STEP_MASK (VM_FF_HP_R0_PRE_HM_MASK & ~( VM_FF_TM_VIRTUAL_SYNC \| VM_FF_PDM_QUEUES \
645	\| VM_FF_EMT_RENDEZVOUS \| VM_FF_REQUEST \
646	\| VM_FF_PDM_DMA) )
647	/** High priority ring-0 VMCPU pre HM-mode execution mask, single stepping. */
648	#define VMCPU_FF_HP_R0_PRE_HM_STEP_MASK (VMCPU_FF_HP_R0_PRE_HM_MASK & ~( VMCPU_FF_TO_R3 \| VMCPU_FF_TIMER \
649	\| VMCPU_FF_PDM_CRITSECT \| VMCPU_FF_REQUEST) )
650
651	/** All the forced VM flags. */
652	#define VM_FF_ALL_MASK (UINT32_MAX)
653	/** All the forced VMCPU flags. */
654	#define VMCPU_FF_ALL_MASK (UINT32_MAX)
655
656	/** All the forced VM flags except those related to raw-mode and hardware
657	* assisted execution. */
658	#define VM_FF_ALL_REM_MASK (~(VM_FF_HIGH_PRIORITY_PRE_RAW_MASK) \| VM_FF_PGM_NEED_HANDY_PAGES \| VM_FF_PGM_NO_MEMORY)
659	/** All the forced VMCPU flags except those related to raw-mode and hardware
660	* assisted execution. */
661	#define VMCPU_FF_ALL_REM_MASK (~( VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK \| VMCPU_FF_PDM_CRITSECT \
662	\| VMCPU_FF_TLB_FLUSH \| VM_WHEN_RAW_MODE(VMCPU_FF_CSAM_PENDING_ACTION, 0) ))
663	/** @} */
664
665	/** @def VM_FF_SET
666	* Sets a single force action flag.
667	*
668	* @param pVM The cross context VM structure.
669	* @param fFlag The flag to set.
670	*/
671	#define VM_FF_SET(pVM, fFlag) do { \
672	AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
673	AssertCompile((fFlag) == RT_BIT_32(fFlag##_BIT)); \
674	ASMAtomicOrU32(&(pVM)->fGlobalForcedActions, (fFlag)); \
675	} while (0)
676
677	/** @def VMCPU_FF_SET
678	* Sets a single force action flag for the given VCPU.
679	*
680	* @param pVCpu The cross context virtual CPU structure.
681	* @param fFlag The flag to set.
682	* @sa VMCPU_FF_SET_MASK
683	*/
684	#ifdef VMCPU_WITH_64_BIT_FFS
685	# define VMCPU_FF_SET(pVCpu, fFlag) do { \
686	AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
687	AssertCompile((fFlag) == RT_BIT_64(fFlag##_BIT)); \
688	ASMAtomicBitSet(&(pVCpu)->fLocalForcedActions, fFlag##_BIT); \
689	} while (0)
690	#else
691	# define VMCPU_FF_SET(pVCpu, fFlag) do { \
692	AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
693	AssertCompile((fFlag) == RT_BIT_32(fFlag##_BIT)); \
694	ASMAtomicOrU32(&(pVCpu)->fLocalForcedActions, (fFlag)); \
695	} while (0)
696	#endif
697
698	/** @def VMCPU_FF_SET_MASK
699	* Sets a two or more force action flag for the given VCPU.
700	*
701	* @param pVCpu The cross context virtual CPU structure.
702	* @param fFlags The flags to set.
703	* @sa VMCPU_FF_SET
704	*/
705	#ifdef VMCPU_WITH_64_BIT_FFS
706	# if ARCH_BITS > 32
707	# define VMCPU_FF_SET_MASK(pVCpu, fFlags) \
708	do { ASMAtomicOrU64(&pVCpu->fLocalForcedActions, (fFlags)); } while (0)
709	# else
710	# define VMCPU_FF_SET_MASK(pVCpu, fFlags) do { \
711	if (!((fFlags) >> 32)) ASMAtomicOrU32((uint32_t volatile *)&pVCpu->fLocalForcedActions, (uint32_t)(fFlags)); \
712	else ASMAtomicOrU64(&pVCpu->fLocalForcedActions, (fFlags)); \
713	} while (0)
714	# endif
715	#else
716	# define VMCPU_FF_SET_MASK(pVCpu, fFlags) \
717	do { ASMAtomicOrU32(&pVCpu->fLocalForcedActions, (fFlags)); } while (0)
718	#endif
719
720	/** @def VM_FF_CLEAR
721	* Clears a single force action flag.
722	*
723	* @param pVM The cross context VM structure.
724	* @param fFlag The flag to clear.
725	*/
726	#define VM_FF_CLEAR(pVM, fFlag) do { \
727	AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
728	AssertCompile((fFlag) == RT_BIT_32(fFlag##_BIT)); \
729	ASMAtomicAndU32(&(pVM)->fGlobalForcedActions, ~(fFlag)); \
730	} while (0)
731
732	/** @def VMCPU_FF_CLEAR
733	* Clears a single force action flag for the given VCPU.
734	*
735	* @param pVCpu The cross context virtual CPU structure.
736	* @param fFlag The flag to clear.
737	*/
738	#ifdef VMCPU_WITH_64_BIT_FFS
739	# define VMCPU_FF_CLEAR(pVCpu, fFlag) do { \
740	AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
741	AssertCompile((fFlag) == RT_BIT_64(fFlag##_BIT)); \
742	ASMAtomicBitClear(&(pVCpu)->fLocalForcedActions, fFlag##_BIT); \
743	} while (0)
744	#else
745	# define VMCPU_FF_CLEAR(pVCpu, fFlag) do { \
746	AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
747	AssertCompile((fFlag) == RT_BIT_32(fFlag##_BIT)); \
748	ASMAtomicAndU32(&(pVCpu)->fLocalForcedActions, ~(fFlag)); \
749	} while (0)
750	#endif
751
752	/** @def VMCPU_FF_CLEAR_MASK
753	* Clears two or more force action flags for the given VCPU.
754	*
755	* @param pVCpu The cross context virtual CPU structure.
756	* @param fFlags The flags to clear.
757	*/
758	#ifdef VMCPU_WITH_64_BIT_FFS
759	# if ARCH_BITS > 32
760	# define VMCPU_FF_CLEAR_MASK(pVCpu, fFlags) \
761	do { ASMAtomicAndU64(&(pVCpu)->fLocalForcedActions, ~(fFlags)); } while (0)
762	# else
763	# define VMCPU_FF_CLEAR_MASK(pVCpu, fFlags) do { \
764	if (!((fFlags) >> 32)) ASMAtomicAndU32((uint32_t volatile *)&(pVCpu)->fLocalForcedActions, ~(uint32_t)(fFlags)); \
765	else ASMAtomicAndU64(&(pVCpu)->fLocalForcedActions, ~(fFlags)); \
766	} while (0)
767	# endif
768	#else
769	# define VMCPU_FF_CLEAR_MASK(pVCpu, fFlags) \
770	do { ASMAtomicAndU32(&(pVCpu)->fLocalForcedActions, ~(fFlags)); } while (0)
771	#endif
772
773	/** @def VM_FF_IS_SET
774	* Checks if single a force action flag is set.
775	*
776	* @param pVM The cross context VM structure.
777	* @param fFlag The flag to check.
778	* @sa VM_FF_IS_ANY_SET
779	*/
780	#if !defined(VBOX_STRICT) \|\| !defined(RT_COMPILER_SUPPORTS_LAMBDA)
781	# define VM_FF_IS_SET(pVM, fFlag) RT_BOOL((pVM)->fGlobalForcedActions & (fFlag))
782	#else
783	# define VM_FF_IS_SET(pVM, fFlag) \
784	([](PVM a_pVM) -> bool \
785	{ \
786	AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
787	AssertCompile((fFlag) == RT_BIT_32(fFlag##_BIT)); \
788	return RT_BOOL(a_pVM->fGlobalForcedActions & (fFlag)); \
789	}(pVM))
790	#endif
791
792	/** @def VMCPU_FF_IS_SET
793	* Checks if a single force action flag is set for the given VCPU.
794	*
795	* @param pVCpu The cross context virtual CPU structure.
796	* @param fFlag The flag to check.
797	* @sa VMCPU_FF_IS_ANY_SET
798	*/
799	#if !defined(VBOX_STRICT) \|\| !defined(RT_COMPILER_SUPPORTS_LAMBDA)
800	# define VMCPU_FF_IS_SET(pVCpu, fFlag) RT_BOOL((pVCpu)->fLocalForcedActions & (fFlag))
801	#else
802	# define VMCPU_FF_IS_SET(pVCpu, fFlag) \
803	([](PVMCPU a_pVCpu) -> bool \
804	{ \
805	AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
806	AssertCompile((fFlag) == RT_BIT_64(fFlag##_BIT)); \
807	return RT_BOOL(a_pVCpu->fLocalForcedActions & (fFlag)); \
808	}(pVCpu))
809	#endif
810
811	/** @def VM_FF_IS_ANY_SET
812	* Checks if one or more force action in the specified set is pending.
813	*
814	* @param pVM The cross context VM structure.
815	* @param fFlags The flags to check for.
816	* @sa VM_FF_IS_SET
817	*/
818	#define VM_FF_IS_ANY_SET(pVM, fFlags) RT_BOOL((pVM)->fGlobalForcedActions & (fFlags))
819
820	/** @def VMCPU_FF_IS_ANY_SET
821	* Checks if two or more force action flags in the specified set is set for the given VCPU.
822	*
823	* @param pVCpu The cross context virtual CPU structure.
824	* @param fFlags The flags to check for.
825	* @sa VMCPU_FF_IS_SET
826	*/
827	#define VMCPU_FF_IS_ANY_SET(pVCpu, fFlags) RT_BOOL((pVCpu)->fLocalForcedActions & (fFlags))
828
829	/** @def VM_FF_TEST_AND_CLEAR
830	* Checks if one (!) force action in the specified set is pending and clears it atomically
831	*
832	* @returns true if the bit was set.
833	* @returns false if the bit was clear.
834	* @param pVM The cross context VM structure.
835	* @param fFlag Flag constant to check and clear (_BIT is appended).
836	*/
837	#define VM_FF_TEST_AND_CLEAR(pVM, fFlag) (ASMAtomicBitTestAndClear(&(pVM)->fGlobalForcedActions, fFlag##_BIT))
838
839	/** @def VMCPU_FF_TEST_AND_CLEAR
840	* Checks if one (!) force action in the specified set is pending and clears it atomically
841	*
842	* @returns true if the bit was set.
843	* @returns false if the bit was clear.
844	* @param pVCpu The cross context virtual CPU structure.
845	* @param fFlag Flag constant to check and clear (_BIT is appended).
846	*/
847	#define VMCPU_FF_TEST_AND_CLEAR(pVCpu, fFlag) (ASMAtomicBitTestAndClear(&(pVCpu)->fLocalForcedActions, fFlag##_BIT))
848
849	/** @def VM_FF_IS_PENDING_EXCEPT
850	* Checks if one or more force action in the specified set is pending while one
851	* or more other ones are not.
852	*
853	* @param pVM The cross context VM structure.
854	* @param fFlags The flags to check for.
855	* @param fExcpt The flags that should not be set.
856	*/
857	#define VM_FF_IS_PENDING_EXCEPT(pVM, fFlags, fExcpt) \
858	( ((pVM)->fGlobalForcedActions & (fFlags)) && !((pVM)->fGlobalForcedActions & (fExcpt)) )
859
860	/** @def VM_IS_EMT
861	* Checks if the current thread is the emulation thread (EMT).
862	*
863	* @remark The ring-0 variation will need attention if we expand the ring-0
864	* code to let threads other than EMT mess around with the VM.
865	*/
866	#ifdef IN_RC
867	# define VM_IS_EMT(pVM) true
868	#else
869	# define VM_IS_EMT(pVM) (VMMGetCpu(pVM) != NULL)
870	#endif
871
872	/** @def VMCPU_IS_EMT
873	* Checks if the current thread is the emulation thread (EMT) for the specified
874	* virtual CPU.
875	*/
876	#ifdef IN_RC
877	# define VMCPU_IS_EMT(pVCpu) true
878	#else
879	# define VMCPU_IS_EMT(pVCpu) ((pVCpu) && ((pVCpu) == VMMGetCpu((pVCpu)->CTX_SUFF(pVM))))
880	#endif
881
882	/** @def VM_ASSERT_EMT
883	* Asserts that the current thread IS the emulation thread (EMT).
884	*/
885	#ifdef IN_RC
886	# define VM_ASSERT_EMT(pVM) Assert(VM_IS_EMT(pVM))
887	#elif defined(IN_RING0)
888	# define VM_ASSERT_EMT(pVM) Assert(VM_IS_EMT(pVM))
889	#else
890	# define VM_ASSERT_EMT(pVM) \
891	AssertMsg(VM_IS_EMT(pVM), \
892	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd\n", RTThreadNativeSelf(), VMR3GetVMCPUNativeThread(pVM)))
893	#endif
894
895	/** @def VMCPU_ASSERT_EMT
896	* Asserts that the current thread IS the emulation thread (EMT) of the
897	* specified virtual CPU.
898	*/
899	#ifdef IN_RC
900	# define VMCPU_ASSERT_EMT(pVCpu) Assert(VMCPU_IS_EMT(pVCpu))
901	#elif defined(IN_RING0)
902	# define VMCPU_ASSERT_EMT(pVCpu) AssertMsg(VMCPU_IS_EMT(pVCpu), \
903	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd idCpu=%u\n", \
904	RTThreadNativeSelf(), (pVCpu) ? (pVCpu)->hNativeThreadR0 : 0, \
905	(pVCpu) ? (pVCpu)->idCpu : 0))
906	#else
907	# define VMCPU_ASSERT_EMT(pVCpu) AssertMsg(VMCPU_IS_EMT(pVCpu), \
908	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd idCpu=%#x\n", \
909	RTThreadNativeSelf(), (pVCpu)->hNativeThread, (pVCpu)->idCpu))
910	#endif
911
912	/** @def VM_ASSERT_EMT_RETURN
913	* Asserts that the current thread IS the emulation thread (EMT) and returns if it isn't.
914	*/
915	#ifdef IN_RC
916	# define VM_ASSERT_EMT_RETURN(pVM, rc) AssertReturn(VM_IS_EMT(pVM), (rc))
917	#elif defined(IN_RING0)
918	# define VM_ASSERT_EMT_RETURN(pVM, rc) AssertReturn(VM_IS_EMT(pVM), (rc))
919	#else
920	# define VM_ASSERT_EMT_RETURN(pVM, rc) \
921	AssertMsgReturn(VM_IS_EMT(pVM), \
922	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd\n", RTThreadNativeSelf(), VMR3GetVMCPUNativeThread(pVM)), \
923	(rc))
924	#endif
925
926	/** @def VMCPU_ASSERT_EMT_RETURN
927	* Asserts that the current thread IS the emulation thread (EMT) and returns if it isn't.
928	*/
929	#ifdef IN_RC
930	# define VMCPU_ASSERT_EMT_RETURN(pVCpu, rc) AssertReturn(VMCPU_IS_EMT(pVCpu), (rc))
931	#elif defined(IN_RING0)
932	# define VMCPU_ASSERT_EMT_RETURN(pVCpu, rc) AssertReturn(VMCPU_IS_EMT(pVCpu), (rc))
933	#else
934	# define VMCPU_ASSERT_EMT_RETURN(pVCpu, rc) \
935	AssertMsgReturn(VMCPU_IS_EMT(pVCpu), \
936	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd idCpu=%#x\n", \
937	RTThreadNativeSelf(), (pVCpu)->hNativeThread, (pVCpu)->idCpu), \
938	(rc))
939	#endif
940
941	/** @def VMCPU_ASSERT_EMT_OR_GURU
942	* Asserts that the current thread IS the emulation thread (EMT) of the
943	* specified virtual CPU.
944	*/
945	#if defined(IN_RC) \|\| defined(IN_RING0)
946	# define VMCPU_ASSERT_EMT_OR_GURU(pVCpu) Assert( VMCPU_IS_EMT(pVCpu) \
947	\|\| pVCpu->CTX_SUFF(pVM)->enmVMState == VMSTATE_GURU_MEDITATION \
948	\|\| pVCpu->CTX_SUFF(pVM)->enmVMState == VMSTATE_GURU_MEDITATION_LS )
949	#else
950	# define VMCPU_ASSERT_EMT_OR_GURU(pVCpu) \
951	AssertMsg( VMCPU_IS_EMT(pVCpu) \
952	\|\| pVCpu->CTX_SUFF(pVM)->enmVMState == VMSTATE_GURU_MEDITATION \
953	\|\| pVCpu->CTX_SUFF(pVM)->enmVMState == VMSTATE_GURU_MEDITATION_LS, \
954	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd idCpu=%#x\n", \
955	RTThreadNativeSelf(), (pVCpu)->hNativeThread, (pVCpu)->idCpu))
956	#endif
957
958	/** @def VMCPU_ASSERT_EMT_OR_NOT_RUNNING
959	* Asserts that the current thread IS the emulation thread (EMT) of the
960	* specified virtual CPU or the VM is not running.
961	*/
962	#if defined(IN_RC) \|\| defined(IN_RING0)
963	# define VMCPU_ASSERT_EMT_OR_NOT_RUNNING(pVCpu) \
964	Assert( VMCPU_IS_EMT(pVCpu) \
965	\|\| !VM_IS_RUNNING_FOR_ASSERTIONS_ONLY((pVCpu)->CTX_SUFF(pVM)) )
966	#else
967	# define VMCPU_ASSERT_EMT_OR_NOT_RUNNING(pVCpu) \
968	AssertMsg( VMCPU_IS_EMT(pVCpu) \
969	\|\| !VM_IS_RUNNING_FOR_ASSERTIONS_ONLY((pVCpu)->CTX_SUFF(pVM)), \
970	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd idCpu=%#x\n", \
971	RTThreadNativeSelf(), (pVCpu)->hNativeThread, (pVCpu)->idCpu))
972	#endif
973
974	/** @def VMSTATE_IS_RUNNING
975	* Checks if the given state indicates a running VM.
976	*/
977	#define VMSTATE_IS_RUNNING(a_enmVMState) \
978	( (enmVMState) == VMSTATE_RUNNING \
979	\|\| (enmVMState) == VMSTATE_RUNNING_LS \
980	\|\| (enmVMState) == VMSTATE_RUNNING_FT )
981
982	/** @def VM_IS_RUNNING_FOR_ASSERTIONS_ONLY
983	* Checks if the VM is running.
984	* @note This is only for pure debug assertions. No AssertReturn or similar!
985	* @sa VMSTATE_IS_RUNNING
986	*/
987	#define VM_IS_RUNNING_FOR_ASSERTIONS_ONLY(pVM) \
988	( (pVM)->enmVMState == VMSTATE_RUNNING \
989	\|\| (pVM)->enmVMState == VMSTATE_RUNNING_LS \
990	\|\| (pVM)->enmVMState == VMSTATE_RUNNING_FT )
991
992	/** @def VM_ASSERT_IS_NOT_RUNNING
993	* Asserts that the VM is not running.
994	*/
995	#if defined(IN_RC) \|\| defined(IN_RING0)
996	#define VM_ASSERT_IS_NOT_RUNNING(pVM) Assert(!VM_IS_RUNNING_FOR_ASSERTIONS_ONLY(pVM))
997	#else
998	#define VM_ASSERT_IS_NOT_RUNNING(pVM) AssertMsg(!VM_IS_RUNNING_FOR_ASSERTIONS_ONLY(pVM), \
999	("VM is running. enmVMState=%d\n", (pVM)->enmVMState))
1000	#endif
1001
1002	/** @def VM_ASSERT_EMT0
1003	* Asserts that the current thread IS emulation thread \#0 (EMT0).
1004	*/
1005	#define VM_ASSERT_EMT0(pVM) VMCPU_ASSERT_EMT(&(pVM)->aCpus[0])
1006
1007	/** @def VM_ASSERT_EMT0_RETURN
1008	* Asserts that the current thread IS emulation thread \#0 (EMT0) and returns if
1009	* it isn't.
1010	*/
1011	#define VM_ASSERT_EMT0_RETURN(pVM, rc) VMCPU_ASSERT_EMT_RETURN(&(pVM)->aCpus[0], (rc))
1012
1013
1014	/**
1015	* Asserts that the current thread is NOT the emulation thread.
1016	*/
1017	#define VM_ASSERT_OTHER_THREAD(pVM) \
1018	AssertMsg(!VM_IS_EMT(pVM), ("Not other thread!!\n"))
1019
1020
1021	/** @def VM_ASSERT_STATE
1022	* Asserts a certain VM state.
1023	*/
1024	#define VM_ASSERT_STATE(pVM, _enmState) \
1025	AssertMsg((pVM)->enmVMState == (_enmState), \
1026	("state %s, expected %s\n", VMGetStateName((pVM)->enmVMState), VMGetStateName(_enmState)))
1027
1028	/** @def VM_ASSERT_STATE_RETURN
1029	* Asserts a certain VM state and returns if it doesn't match.
1030	*/
1031	#define VM_ASSERT_STATE_RETURN(pVM, _enmState, rc) \
1032	AssertMsgReturn((pVM)->enmVMState == (_enmState), \
1033	("state %s, expected %s\n", VMGetStateName((pVM)->enmVMState), VMGetStateName(_enmState)), \
1034	(rc))
1035
1036	/** @def VM_IS_VALID_EXT
1037	* Asserts a the VM handle is valid for external access, i.e. not being destroy
1038	* or terminated. */
1039	#define VM_IS_VALID_EXT(pVM) \
1040	( RT_VALID_ALIGNED_PTR(pVM, PAGE_SIZE) \
1041	&& ( (unsigned)(pVM)->enmVMState < (unsigned)VMSTATE_DESTROYING \
1042	\|\| ( (unsigned)(pVM)->enmVMState == (unsigned)VMSTATE_DESTROYING \
1043	&& VM_IS_EMT(pVM))) )
1044
1045	/** @def VM_ASSERT_VALID_EXT_RETURN
1046	* Asserts a the VM handle is valid for external access, i.e. not being
1047	* destroy or terminated.
1048	*/
1049	#define VM_ASSERT_VALID_EXT_RETURN(pVM, rc) \
1050	AssertMsgReturn(VM_IS_VALID_EXT(pVM), \
1051	("pVM=%p state %s\n", (pVM), RT_VALID_ALIGNED_PTR(pVM, PAGE_SIZE) \
1052	? VMGetStateName(pVM->enmVMState) : ""), \
1053	(rc))
1054
1055	/** @def VMCPU_ASSERT_VALID_EXT_RETURN
1056	* Asserts a the VMCPU handle is valid for external access, i.e. not being
1057	* destroy or terminated.
1058	*/
1059	#define VMCPU_ASSERT_VALID_EXT_RETURN(pVCpu, rc) \
1060	AssertMsgReturn( RT_VALID_ALIGNED_PTR(pVCpu, 64) \
1061	&& RT_VALID_ALIGNED_PTR((pVCpu)->CTX_SUFF(pVM), PAGE_SIZE) \
1062	&& (unsigned)(pVCpu)->CTX_SUFF(pVM)->enmVMState < (unsigned)VMSTATE_DESTROYING, \
1063	("pVCpu=%p pVM=%p state %s\n", (pVCpu), RT_VALID_ALIGNED_PTR(pVCpu, 64) ? (pVCpu)->CTX_SUFF(pVM) : NULL, \
1064	RT_VALID_ALIGNED_PTR(pVCpu, 64) && RT_VALID_ALIGNED_PTR((pVCpu)->CTX_SUFF(pVM), PAGE_SIZE) \
1065	? VMGetStateName((pVCpu)->pVMR3->enmVMState) : ""), \
1066	(rc))
1067
1068	#endif /* !VBOX_FOR_DTRACE_LIB */
1069
1070
1071	/**
1072	* Helper that HM and NEM uses for safely modifying VM::bMainExecutionEngine.
1073	*
1074	* ONLY HM and NEM MAY USE THIS!
1075	*
1076	* @param a_pVM The cross context VM structure.
1077	* @param a_bValue The new value.
1078	* @internal
1079	*/
1080	#define VM_SET_MAIN_EXECUTION_ENGINE(a_pVM, a_bValue) \
1081	do { \
1082	const_cast<uint8_t >(&(a_pVM)->bMainExecutionEngine) = (a_bValue); \
1083	ASMCompilerBarrier(); /* just to be on the safe side */ \
1084	} while (0)
1085
1086	/**
1087	* Checks whether raw-mode is used.
1088	*
1089	* @retval true if either is used.
1090	* @retval false if software virtualization (raw-mode) is used.
1091	*
1092	* @param a_pVM The cross context VM structure.
1093	* @sa VM_IS_HM_OR_NEM_ENABLED, VM_IS_HM_ENABLED, VM_IS_NEM_ENABLED.
1094	* @internal
1095	*/
1096	#ifdef VBOX_WITH_RAW_MODE
1097	# define VM_IS_RAW_MODE_ENABLED(a_pVM) ((a_pVM)->bMainExecutionEngine == VM_EXEC_ENGINE_RAW_MODE)
1098	#else
1099	# define VM_IS_RAW_MODE_ENABLED(a_pVM) (false)
1100	#endif
1101
1102	/**
1103	* Checks whether HM (VT-x/AMD-V) or NEM is being used by this VM.
1104	*
1105	* @retval true if either is used.
1106	* @retval false if software virtualization (raw-mode) is used.
1107	*
1108	* @param a_pVM The cross context VM structure.
1109	* @sa VM_IS_RAW_MODE_ENABLED, VM_IS_HM_ENABLED, VM_IS_NEM_ENABLED.
1110	* @internal
1111	*/
1112	#define VM_IS_HM_OR_NEM_ENABLED(a_pVM) ((a_pVM)->bMainExecutionEngine != VM_EXEC_ENGINE_RAW_MODE)
1113
1114	/**
1115	* Checks whether HM is being used by this VM.
1116	*
1117	* @retval true if HM (VT-x/AMD-v) is used.
1118	* @retval false if not.
1119	*
1120	* @param a_pVM The cross context VM structure.
1121	* @sa VM_IS_NEM_ENABLED, VM_IS_RAW_MODE_ENABLED, VM_IS_HM_OR_NEM_ENABLED.
1122	* @internal
1123	*/
1124	#define VM_IS_HM_ENABLED(a_pVM) ((a_pVM)->bMainExecutionEngine == VM_EXEC_ENGINE_HW_VIRT)
1125
1126	/**
1127	* Checks whether NEM is being used by this VM.
1128	*
1129	* @retval true if a native hypervisor API is used.
1130	* @retval false if not.
1131	*
1132	* @param a_pVM The cross context VM structure.
1133	* @sa VM_IS_HM_ENABLED, VM_IS_RAW_MODE_ENABLED, VM_IS_HM_OR_NEM_ENABLED.
1134	* @internal
1135	*/
1136	#define VM_IS_NEM_ENABLED(a_pVM) ((a_pVM)->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API)
1137
1138
1139	/**
1140	* The cross context VM structure.
1141	*
1142	* It contains all the VM data which have to be available in all contexts.
1143	* Even if it contains all the data the idea is to use APIs not to modify all
1144	* the members all around the place. Therefore we make use of unions to hide
1145	* everything which isn't local to the current source module. This means we'll
1146	* have to pay a little bit of attention when adding new members to structures
1147	* in the unions and make sure to keep the padding sizes up to date.
1148	*
1149	* Run 'kmk run-struct-tests' (from src/VBox/VMM if you like) after updating!
1150	*/
1151	typedef struct VM
1152	{
1153	/** The state of the VM.
1154	* This field is read only to everyone except the VM and EM. */
1155	VMSTATE volatile enmVMState;
1156	/** Forced action flags.
1157	* See the VM_FF_* \#defines. Updated atomically.
1158	*/
1159	volatile uint32_t fGlobalForcedActions;
1160	/** Pointer to the array of page descriptors for the VM structure allocation. */
1161	R3PTRTYPE(PSUPPAGE) paVMPagesR3;
1162	/** Session handle. For use when calling SUPR0 APIs. */
1163	PSUPDRVSESSION pSession;
1164	/** Pointer to the ring-3 VM structure. */
1165	PUVM pUVM;
1166	/** Ring-3 Host Context VM Pointer. */
1167	R3PTRTYPE(struct VM *) pVMR3;
1168	/** Ring-0 Host Context VM Pointer. */
1169	R0PTRTYPE(struct VM *) pVMR0;
1170	/** Raw-mode Context VM Pointer. */
1171	RCPTRTYPE(struct VM *) pVMRC;
1172
1173	/** The GVM VM handle. Only the GVM should modify this field. */
1174	uint32_t hSelf;
1175	/** Number of virtual CPUs. */
1176	uint32_t cCpus;
1177	/** CPU excution cap (1-100) */
1178	uint32_t uCpuExecutionCap;
1179
1180	/** Size of the VM structure including the VMCPU array. */
1181	uint32_t cbSelf;
1182
1183	/** Offset to the VMCPU array starting from beginning of this structure. */
1184	uint32_t offVMCPU;
1185
1186	/**
1187	* VMMSwitcher assembly entry point returning to host context.
1188	*
1189	* Depending on how the host handles the rc status given in @a eax, this may
1190	* return and let the caller resume whatever it was doing prior to the call.
1191	*
1192	*
1193	* @param eax The return code, register.
1194	* @remark Assume interrupts disabled.
1195	* @remark This method pointer lives here because TRPM needs it.
1196	*/
1197	RTRCPTR pfnVMMRCToHostAsm/(int32_t eax)/;
1198
1199	/**
1200	* VMMSwitcher assembly entry point returning to host context without saving the
1201	* raw-mode context (hyper) registers.
1202	*
1203	* Unlike pfnVMMRC2HCAsm, this will not return to the caller. Instead it
1204	* expects the caller to save a RC context in CPUM where one might return if the
1205	* return code indicate that this is possible.
1206	*
1207	* This method pointer lives here because TRPM needs it.
1208	*
1209	* @param eax The return code, register.
1210	* @remark Assume interrupts disabled.
1211	* @remark This method pointer lives here because TRPM needs it.
1212	*/
1213	RTRCPTR pfnVMMRCToHostAsmNoReturn/(int32_t eax)/;
1214
1215	/** @name Various items that are frequently accessed.
1216	* @{ */
1217	/** The main execution engine, VM_EXEC_ENGINE_XXX.
1218	* This is set early during vmR3InitRing3 by HM or NEM. */
1219	uint8_t const bMainExecutionEngine;
1220
1221	/** Whether to recompile user mode code or run it raw/hm/nem.
1222	* In non-raw-mode both fRecompileUser and fRecompileSupervisor must be set
1223	* to recompiler stuff. */
1224	bool fRecompileUser;
1225	/** Whether to recompile supervisor mode code or run it raw/hm/nem.
1226	* In non-raw-mode both fRecompileUser and fRecompileSupervisor must be set
1227	* to recompiler stuff. */
1228	bool fRecompileSupervisor;
1229	/** Whether raw mode supports ring-1 code or not.
1230	* This will be cleared when not in raw-mode. */
1231	bool fRawRing1Enabled;
1232	/** PATM enabled flag.
1233	* This is placed here for performance reasons.
1234	* This will be cleared when not in raw-mode. */
1235	bool fPATMEnabled;
1236	/** CSAM enabled flag.
1237	* This is placed here for performance reasons.
1238	* This will be cleared when not in raw-mode. */
1239	bool fCSAMEnabled;
1240
1241	/** Hardware VM support is available and enabled.
1242	* Determined very early during init.
1243	* This is placed here for performance reasons.
1244	* @todo obsoleted by bMainExecutionEngine, eliminate. */
1245	bool fHMEnabled;
1246	/** Hardware VM support requires a minimal raw-mode context.
1247	* This is never set on 64-bit hosts, only 32-bit hosts requires it. */
1248	bool fHMNeedRawModeCtx;
1249
1250	/** Set when this VM is the master FT node.
1251	* @todo This doesn't need to be here, FTM should store it in it's own
1252	* structures instead. */
1253	bool fFaultTolerantMaster;
1254	/** Large page enabled flag.
1255	* @todo This doesn't need to be here, PGM should store it in it's own
1256	* structures instead. */
1257	bool fUseLargePages;
1258	/** @} */
1259
1260	/** Alignment padding. */
1261	uint8_t uPadding1[2];
1262
1263	/** @name Debugging
1264	* @{ */
1265	/** Raw-mode Context VM Pointer. */
1266	RCPTRTYPE(RTTRACEBUF) hTraceBufRC;
1267	/** Ring-3 Host Context VM Pointer. */
1268	R3PTRTYPE(RTTRACEBUF) hTraceBufR3;
1269	/** Ring-0 Host Context VM Pointer. */
1270	R0PTRTYPE(RTTRACEBUF) hTraceBufR0;
1271	/** @} */
1272
1273	#if HC_ARCH_BITS == 32
1274	/** Alignment padding. */
1275	uint32_t uPadding2;
1276	#endif
1277
1278	/** @name Switcher statistics (remove)
1279	* @{ */
1280	/** Profiling the total time from Qemu to GC. */
1281	STAMPROFILEADV StatTotalQemuToGC;
1282	/** Profiling the total time from GC to Qemu. */
1283	STAMPROFILEADV StatTotalGCToQemu;
1284	/** Profiling the total time spent in GC. */
1285	STAMPROFILEADV StatTotalInGC;
1286	/** Profiling the total time spent not in Qemu. */
1287	STAMPROFILEADV StatTotalInQemu;
1288	/** Profiling the VMMSwitcher code for going to GC. */
1289	STAMPROFILEADV StatSwitcherToGC;
1290	/** Profiling the VMMSwitcher code for going to HC. */
1291	STAMPROFILEADV StatSwitcherToHC;
1292	STAMPROFILEADV StatSwitcherSaveRegs;
1293	STAMPROFILEADV StatSwitcherSysEnter;
1294	STAMPROFILEADV StatSwitcherDebug;
1295	STAMPROFILEADV StatSwitcherCR0;
1296	STAMPROFILEADV StatSwitcherCR4;
1297	STAMPROFILEADV StatSwitcherJmpCR3;
1298	STAMPROFILEADV StatSwitcherRstrRegs;
1299	STAMPROFILEADV StatSwitcherLgdt;
1300	STAMPROFILEADV StatSwitcherLidt;
1301	STAMPROFILEADV StatSwitcherLldt;
1302	STAMPROFILEADV StatSwitcherTSS;
1303	/** @} */
1304
1305	/** Padding - the unions must be aligned on a 64 bytes boundary and the unions
1306	* must start at the same offset on both 64-bit and 32-bit hosts. */
1307	uint8_t abAlignment3[(HC_ARCH_BITS == 32 ? 24 : 0) + 40];
1308
1309	/** CPUM part. */
1310	union
1311	{
1312	#ifdef ___CPUMInternal_h
1313	struct CPUM s;
1314	#endif
1315	#ifdef ___VBox_vmm_cpum_h
1316	/** Read only info exposed about the host and guest CPUs. */
1317	struct
1318	{
1319	/** Padding for hidden fields. */
1320	uint8_t abHidden0[64];
1321	/** Host CPU feature information. */
1322	CPUMFEATURES HostFeatures;
1323	/** Guest CPU feature information. */
1324	CPUMFEATURES GuestFeatures;
1325	} const ro;
1326	#endif
1327	uint8_t padding[1536]; /* multiple of 64 */
1328	} cpum;
1329
1330	/** VMM part. */
1331	union
1332	{
1333	#ifdef ___VMMInternal_h
1334	struct VMM s;
1335	#endif
1336	uint8_t padding[1600]; /* multiple of 64 */
1337	} vmm;
1338
1339	/** PGM part. */
1340	union
1341	{
1342	#ifdef ___PGMInternal_h
1343	struct PGM s;
1344	#endif
1345	uint8_t padding[40962+6080]; / multiple of 64 */
1346	} pgm;
1347
1348	/** HM part. */
1349	union
1350	{
1351	#ifdef ___HMInternal_h
1352	struct HM s;
1353	#endif
1354	uint8_t padding[5440]; /* multiple of 64 */
1355	} hm;
1356
1357	/** TRPM part. */
1358	union
1359	{
1360	#ifdef ___TRPMInternal_h
1361	struct TRPM s;
1362	#endif
1363	uint8_t padding[5248]; /* multiple of 64 */
1364	} trpm;
1365
1366	/** SELM part. */
1367	union
1368	{
1369	#ifdef ___SELMInternal_h
1370	struct SELM s;
1371	#endif
1372	uint8_t padding[768]; /* multiple of 64 */
1373	} selm;
1374
1375	/** MM part. */
1376	union
1377	{
1378	#ifdef ___MMInternal_h
1379	struct MM s;
1380	#endif
1381	uint8_t padding[192]; /* multiple of 64 */
1382	} mm;
1383
1384	/** PDM part. */
1385	union
1386	{
1387	#ifdef ___PDMInternal_h
1388	struct PDM s;
1389	#endif
1390	uint8_t padding[1920]; /* multiple of 64 */
1391	} pdm;
1392
1393	/** IOM part. */
1394	union
1395	{
1396	#ifdef ___IOMInternal_h
1397	struct IOM s;
1398	#endif
1399	uint8_t padding[896]; /* multiple of 64 */
1400	} iom;
1401
1402	/** EM part. */
1403	union
1404	{
1405	#ifdef ___EMInternal_h
1406	struct EM s;
1407	#endif
1408	uint8_t padding[256]; /* multiple of 64 */
1409	} em;
1410
1411	/** NEM part. */
1412	union
1413	{
1414	#ifdef ___NEMInternal_h
1415	struct NEM s;
1416	#endif
1417	uint8_t padding[128]; /* multiple of 64 */
1418	} nem;
1419
1420	/** TM part. */
1421	union
1422	{
1423	#ifdef ___TMInternal_h
1424	struct TM s;
1425	#endif
1426	uint8_t padding[2496]; /* multiple of 64 */
1427	} tm;
1428
1429	/** DBGF part. */
1430	union
1431	{
1432	#ifdef ___DBGFInternal_h
1433	struct DBGF s;
1434	#endif
1435	#ifdef ___VBox_vmm_dbgf_h
1436	/** Read only info exposed about interrupt breakpoints and selected events. */
1437	struct
1438	{
1439	/** Bitmap of enabled hardware interrupt breakpoints. */
1440	uint32_t bmHardIntBreakpoints[256 / 32];
1441	/** Bitmap of enabled software interrupt breakpoints. */
1442	uint32_t bmSoftIntBreakpoints[256 / 32];
1443	/** Bitmap of selected events.
1444	* This includes non-selectable events too for simplicity, we maintain the
1445	* state for some of these, as it may come in handy. */
1446	uint64_t bmSelectedEvents[(DBGFEVENT_END + 63) / 64];
1447	/** Enabled hardware interrupt breakpoints. */
1448	uint32_t cHardIntBreakpoints;
1449	/** Enabled software interrupt breakpoints. */
1450	uint32_t cSoftIntBreakpoints;
1451	/** The number of selected events. */
1452	uint32_t cSelectedEvents;
1453	/** The number of enabled hardware breakpoints. */
1454	uint8_t cEnabledHwBreakpoints;
1455	/** The number of enabled hardware I/O breakpoints. */
1456	uint8_t cEnabledHwIoBreakpoints;
1457	/** The number of enabled INT3 breakpoints. */
1458	uint8_t cEnabledInt3Breakpoints;
1459	uint8_t abPadding[1]; /*< Unused padding space up for grabs. /
1460	} const ro;
1461	#endif
1462	uint8_t padding[2432]; /* multiple of 64 */
1463	} dbgf;
1464
1465	/** SSM part. */
1466	union
1467	{
1468	#ifdef ___SSMInternal_h
1469	struct SSM s;
1470	#endif
1471	uint8_t padding[128]; /* multiple of 64 */
1472	} ssm;
1473
1474	/** FTM part. */
1475	union
1476	{
1477	#ifdef ___FTMInternal_h
1478	struct FTM s;
1479	#endif
1480	uint8_t padding[512]; /* multiple of 64 */
1481	} ftm;
1482
1483	#ifdef VBOX_WITH_RAW_MODE
1484	/** PATM part. */
1485	union
1486	{
1487	# ifdef ___PATMInternal_h
1488	struct PATM s;
1489	# endif
1490	uint8_t padding[768]; /* multiple of 64 */
1491	} patm;
1492
1493	/** CSAM part. */
1494	union
1495	{
1496	# ifdef ___CSAMInternal_h
1497	struct CSAM s;
1498	# endif
1499	uint8_t padding[1088]; /* multiple of 64 */
1500	} csam;
1501	#endif
1502
1503	#ifdef VBOX_WITH_REM
1504	/** REM part. */
1505	union
1506	{
1507	# ifdef ___REMInternal_h
1508	struct REM s;
1509	# endif
1510	uint8_t padding[0x11100]; /* multiple of 64 */
1511	} rem;
1512	#endif
1513
1514	union
1515	{
1516	#ifdef ___GIMInternal_h
1517	struct GIM s;
1518	#endif
1519	uint8_t padding[448]; /* multiple of 64 */
1520	} gim;
1521
1522	union
1523	{
1524	#ifdef ___APICInternal_h
1525	struct APIC s;
1526	#endif
1527	uint8_t padding[128]; /* multiple of 8 */
1528	} apic;
1529
1530	/* ---- begin small stuff ---- */
1531
1532	/** VM part. */
1533	union
1534	{
1535	#ifdef ___VMInternal_h
1536	struct VMINT s;
1537	#endif
1538	uint8_t padding[32]; /* multiple of 8 */
1539	} vm;
1540
1541	/** CFGM part. */
1542	union
1543	{
1544	#ifdef ___CFGMInternal_h
1545	struct CFGM s;
1546	#endif
1547	uint8_t padding[8]; /* multiple of 8 */
1548	} cfgm;
1549
1550	/** Padding for aligning the cpu array on a page boundary. */
1551	#if defined(VBOX_WITH_REM) && defined(VBOX_WITH_RAW_MODE)
1552	uint8_t abAlignment2[3670];
1553	#elif defined(VBOX_WITH_REM) && !defined(VBOX_WITH_RAW_MODE)
1554	uint8_t abAlignment2[1430];
1555	#elif !defined(VBOX_WITH_REM) && defined(VBOX_WITH_RAW_MODE)
1556	uint8_t abAlignment2[3926];
1557	#else
1558	uint8_t abAlignment2[1686];
1559	#endif
1560
1561	/* ---- end small stuff ---- */
1562
1563	/** VMCPU array for the configured number of virtual CPUs.
1564	* Must be aligned on a page boundary for TLB hit reasons as well as
1565	* alignment of VMCPU members. */
1566	VMCPU aCpus[1];
1567	} VM;
1568
1569
1570	#ifdef IN_RC
1571	RT_C_DECLS_BEGIN
1572
1573	/** The VM structure.
1574	* This is imported from the VMMRCBuiltin module, i.e. it's a one of those magic
1575	* globals which we should avoid using.
1576	*/
1577	extern DECLIMPORT(VM) g_VM;
1578
1579	RT_C_DECLS_END
1580	#endif
1581
1582	/** @} */
1583
1584	#endif
1585

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source: vbox/trunk/include/VBox/vmm/vm.h@ 74865

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