vm.h@ 75200

Last change on this file since 75200 was 75200, checked in by vboxsync, 6 years ago
vm.h: Comment update.
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 60.4 KB

Line
1	/** @file
2	* VM - The Virtual Machine, data.
3	*/
4
5	/*
6	* Copyright (C) 2006-2017 Oracle Corporation
7	*
8	* This file is part of VirtualBox Open Source Edition (OSE), as
9	* available from http://www.virtualbox.org. This file is free software;
10	* you can redistribute it and/or modify it under the terms of the GNU
11	* General Public License (GPL) as published by the Free Software
12	* Foundation, in version 2 as it comes in the "COPYING" file of the
13	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15	*
16	* The contents of this file may alternatively be used under the terms
17	* of the Common Development and Distribution License Version 1.0
18	* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19	* VirtualBox OSE distribution, in which case the provisions of the
20	* CDDL are applicable instead of those of the GPL.
21	*
22	* You may elect to license modified versions of this file under the
23	* terms and conditions of either the GPL or the CDDL or both.
24	*/
25
26	#ifndef ___VBox_vmm_vm_h
27	#define ___VBox_vmm_vm_h
28
29	#ifndef VBOX_FOR_DTRACE_LIB
30	# include <iprt/param.h>
31	# include <VBox/types.h>
32	# include <VBox/vmm/cpum.h>
33	# include <VBox/vmm/stam.h>
34	# include <VBox/vmm/vmapi.h>
35	# include <VBox/vmm/vmm.h>
36	# include <VBox/sup.h>
37	#else
38	# pragma D depends_on library vbox-types.d
39	# pragma D depends_on library CPUMInternal.d
40	# define ___CPUMInternal_h
41	#endif
42
43
44
45	/** @defgroup grp_vm The Virtual Machine
46	* @ingroup grp_vmm
47	* @{
48	*/
49
50	/**
51	* The state of a Virtual CPU.
52	*
53	* The basic state indicated here is whether the CPU has been started or not. In
54	* addition, there are sub-states when started for assisting scheduling (GVMM
55	* mostly).
56	*
57	* The transition out of the STOPPED state is done by a vmR3PowerOn.
58	* The transition back to the STOPPED state is done by vmR3PowerOff.
59	*
60	* (Alternatively we could let vmR3PowerOn start CPU 0 only and let the SPIP
61	* handling switch on the other CPUs. Then vmR3Reset would stop all but CPU 0.)
62	*/
63	typedef enum VMCPUSTATE
64	{
65	/** The customary invalid zero. */
66	VMCPUSTATE_INVALID = 0,
67
68	/** Virtual CPU has not yet been started. */
69	VMCPUSTATE_STOPPED,
70
71	/** CPU started. */
72	VMCPUSTATE_STARTED,
73	/** CPU started in HM context. */
74	VMCPUSTATE_STARTED_HM,
75	/** Executing guest code and can be poked (RC or STI bits of HM). */
76	VMCPUSTATE_STARTED_EXEC,
77	/** Executing guest code in the recompiler. */
78	VMCPUSTATE_STARTED_EXEC_REM,
79	/** Executing guest code using NEM. */
80	VMCPUSTATE_STARTED_EXEC_NEM,
81	VMCPUSTATE_STARTED_EXEC_NEM_WAIT,
82	VMCPUSTATE_STARTED_EXEC_NEM_CANCELED,
83	/** Halted. */
84	VMCPUSTATE_STARTED_HALTED,
85
86	/** The end of valid virtual CPU states. */
87	VMCPUSTATE_END,
88
89	/** Ensure 32-bit type. */
90	VMCPUSTATE_32BIT_HACK = 0x7fffffff
91	} VMCPUSTATE;
92
93	/** Enables 64-bit FFs. */
94	#define VMCPU_WITH_64_BIT_FFS
95
96
97	/**
98	* The cross context virtual CPU structure.
99	*
100	* Run 'kmk run-struct-tests' (from src/VBox/VMM if you like) after updating!
101	*/
102	typedef struct VMCPU
103	{
104	/** @name Volatile per-cpu data.
105	* @{ */
106	/** Per CPU forced action.
107	* See the VMCPU_FF_* \#defines. Updated atomically. */
108	#ifdef VMCPU_WITH_64_BIT_FFS
109	uint64_t volatile fLocalForcedActions;
110	#else
111	uint32_t volatile fLocalForcedActions;
112	uint32_t fForLocalForcedActionsExpansion;
113	#endif
114	/** The CPU state. */
115	VMCPUSTATE volatile enmState;
116
117	/** Which host CPU ID is this EMT running on.
118	* Only valid when in RC or HMR0 with scheduling disabled. */
119	RTCPUID volatile idHostCpu;
120	/** The CPU set index corresponding to idHostCpu, UINT32_MAX if not valid.
121	* @remarks Best to make sure iHostCpuSet shares cache line with idHostCpu! */
122	uint32_t volatile iHostCpuSet;
123	/** Padding up to 64 bytes. */
124	uint8_t abAlignment0[64 - 20];
125	/** @} */
126
127	/** IEM part.
128	* @remarks This comes first as it allows the use of 8-bit immediates for the
129	* first 64 bytes of the structure, reducing code size a wee bit. */
130	#ifdef ___IEMInternal_h /* For PDB hacking. */
131	union VMCPUUNIONIEMFULL
132	#else
133	union VMCPUUNIONIEMSTUB
134	#endif
135	{
136	#ifdef ___IEMInternal_h
137	struct IEMCPU s;
138	#endif
139	uint8_t padding[18496]; /* multiple of 64 */
140	} iem;
141
142	/** @name Static per-cpu data.
143	* (Putting this after IEM, hoping that it's less frequently used than it.)
144	* @{ */
145	/** The CPU ID.
146	* This is the index into the VM::aCpu array. */
147	VMCPUID idCpu;
148	/** Raw-mode Context VM Pointer. */
149	PVMRC pVMRC;
150	/** Ring-3 Host Context VM Pointer. */
151	PVMR3 pVMR3;
152	/** Ring-0 Host Context VM Pointer. */
153	PVMR0 pVMR0;
154	/** Pointer to the ring-3 UVMCPU structure. */
155	PUVMCPU pUVCpu;
156	/** The native thread handle. */
157	RTNATIVETHREAD hNativeThread;
158	/** The native R0 thread handle. (different from the R3 handle!) */
159	RTNATIVETHREAD hNativeThreadR0;
160	/** Align the structures below bit on a 64-byte boundary and make sure it starts
161	* at the same offset in both 64-bit and 32-bit builds.
162	*
163	* @remarks The alignments of the members that are larger than 48 bytes should be
164	* 64-byte for cache line reasons. structs containing small amounts of
165	* data could be lumped together at the end with a < 64 byte padding
166	* following it (to grow into and align the struct size).
167	*/
168	uint8_t abAlignment1[64 - 4 - 4 - 5 * (HC_ARCH_BITS == 64 ? 8 : 4)];
169	/** @} */
170
171	/** HM part. */
172	union VMCPUUNIONHM
173	{
174	#ifdef ___HMInternal_h
175	struct HMCPU s;
176	#endif
177	uint8_t padding[5888]; /* multiple of 64 */
178	} hm;
179
180	/** NEM part. */
181	union VMCPUUNIONNEM
182	{
183	#ifdef ___NEMInternal_h
184	struct NEMCPU s;
185	#endif
186	uint8_t padding[512]; /* multiple of 64 */
187	} nem;
188
189	/** TRPM part. */
190	union VMCPUUNIONTRPM
191	{
192	#ifdef ___TRPMInternal_h
193	struct TRPMCPU s;
194	#endif
195	uint8_t padding[128]; /* multiple of 64 */
196	} trpm;
197
198	/** TM part. */
199	union VMCPUUNIONTM
200	{
201	#ifdef ___TMInternal_h
202	struct TMCPU s;
203	#endif
204	uint8_t padding[384]; /* multiple of 64 */
205	} tm;
206
207	/** VMM part. */
208	union VMCPUUNIONVMM
209	{
210	#ifdef ___VMMInternal_h
211	struct VMMCPU s;
212	#endif
213	uint8_t padding[768]; /* multiple of 64 */
214	} vmm;
215
216	/** PDM part. */
217	union VMCPUUNIONPDM
218	{
219	#ifdef ___PDMInternal_h
220	struct PDMCPU s;
221	#endif
222	uint8_t padding[256]; /* multiple of 64 */
223	} pdm;
224
225	/** IOM part. */
226	union VMCPUUNIONIOM
227	{
228	#ifdef ___IOMInternal_h
229	struct IOMCPU s;
230	#endif
231	uint8_t padding[512]; /* multiple of 64 */
232	} iom;
233
234	/** DBGF part.
235	* @todo Combine this with other tiny structures. */
236	union VMCPUUNIONDBGF
237	{
238	#ifdef ___DBGFInternal_h
239	struct DBGFCPU s;
240	#endif
241	uint8_t padding[256]; /* multiple of 64 */
242	} dbgf;
243
244	/** GIM part. */
245	union VMCPUUNIONGIM
246	{
247	#ifdef ___GIMInternal_h
248	struct GIMCPU s;
249	#endif
250	uint8_t padding[512]; /* multiple of 64 */
251	} gim;
252
253	/** APIC part. */
254	union VMCPUUNIONAPIC
255	{
256	#ifdef ___APICInternal_h
257	struct APICCPU s;
258	#endif
259	uint8_t padding[1792]; /* multiple of 64 */
260	} apic;
261
262	/*
263	* Some less frequently used global members that doesn't need to take up
264	* precious space at the head of the structure.
265	*/
266
267	/** Trace groups enable flags. */
268	uint32_t fTraceGroups; /* 64 / 44 */
269	/** State data for use by ad hoc profiling. */
270	uint32_t uAdHoc;
271	/** Profiling samples for use by ad hoc profiling. */
272	STAMPROFILEADV aStatAdHoc[8]; /* size: 408 = 320 /
273
274	/** Align the following members on page boundary. */
275	uint8_t abAlignment2[2808];
276
277	/** PGM part. */
278	union VMCPUUNIONPGM
279	{
280	#ifdef ___PGMInternal_h
281	struct PGMCPU s;
282	#endif
283	uint8_t padding[4096]; /* multiple of 4096 */
284	} pgm;
285
286	/** CPUM part. */
287	union VMCPUUNIONCPUM
288	{
289	#ifdef ___CPUMInternal_h
290	struct CPUMCPU s;
291	#endif
292	#ifdef VMCPU_INCL_CPUM_GST_CTX
293	/** The guest CPUM context for direct use by execution engines.
294	* This is not for general consumption, but for HM, REM, IEM, and maybe a few
295	* others. The rest will use the function based CPUM API. */
296	CPUMCTX GstCtx;
297	#endif
298	uint8_t padding[4096]; /* multiple of 4096 */
299	} cpum;
300
301	/** EM part. */
302	union VMCPUUNIONEM
303	{
304	#ifdef ___EMInternal_h
305	struct EMCPU s;
306	#endif
307	uint8_t padding[40960]; /* multiple of 4096 */
308	} em;
309	} VMCPU;
310
311
312	#ifndef VBOX_FOR_DTRACE_LIB
313
314	/** @name Operations on VMCPU::enmState
315	* @{ */
316	/** Gets the VMCPU state. */
317	#define VMCPU_GET_STATE(pVCpu) ( (pVCpu)->enmState )
318	/** Sets the VMCPU state. */
319	#define VMCPU_SET_STATE(pVCpu, enmNewState) \
320	ASMAtomicWriteU32((uint32_t volatile *)&(pVCpu)->enmState, (enmNewState))
321	/** Cmpares and sets the VMCPU state. */
322	#define VMCPU_CMPXCHG_STATE(pVCpu, enmNewState, enmOldState) \
323	ASMAtomicCmpXchgU32((uint32_t volatile *)&(pVCpu)->enmState, (enmNewState), (enmOldState))
324	/** Checks the VMCPU state. */
325	#ifdef VBOX_STRICT
326	# define VMCPU_ASSERT_STATE(pVCpu, enmExpectedState) \
327	do { \
328	VMCPUSTATE enmState = VMCPU_GET_STATE(pVCpu); \
329	AssertMsg(enmState == (enmExpectedState), \
330	("enmState=%d enmExpectedState=%d idCpu=%u\n", \
331	enmState, enmExpectedState, (pVCpu)->idCpu)); \
332	} while (0)
333	#else
334	# define VMCPU_ASSERT_STATE(pVCpu, enmExpectedState) do { } while (0)
335	#endif
336	/** Tests if the state means that the CPU is started. */
337	#define VMCPUSTATE_IS_STARTED(enmState) ( (enmState) > VMCPUSTATE_STOPPED )
338	/** Tests if the state means that the CPU is stopped. */
339	#define VMCPUSTATE_IS_STOPPED(enmState) ( (enmState) == VMCPUSTATE_STOPPED )
340	/** @} */
341
342
343	/** The name of the raw-mode context VMM Core module. */
344	#define VMMRC_MAIN_MODULE_NAME "VMMRC.rc"
345	/** The name of the ring-0 context VMM Core module. */
346	#define VMMR0_MAIN_MODULE_NAME "VMMR0.r0"
347
348	/**
349	* Wrapper macro for avoiding too much \#ifdef VBOX_WITH_RAW_MODE.
350	*/
351	#ifdef VBOX_WITH_RAW_MODE
352	# define VM_WHEN_RAW_MODE(a_WithExpr, a_WithoutExpr) a_WithExpr
353	#else
354	# define VM_WHEN_RAW_MODE(a_WithExpr, a_WithoutExpr) a_WithoutExpr
355	#endif
356
357
358	/** VM Forced Action Flags.
359	*
360	* Use the VM_FF_SET() and VM_FF_CLEAR() macros to change the force
361	* action mask of a VM.
362	*
363	* Available VM bits:
364	* 0, 1, 5, 6, 7, 13, 14, 15, 16, 17, 21, 22, 23, 24, 25, 26, 27, 28, 30
365	*
366	*
367	* Available VMCPU bits:
368	* 14, 15, 33 to 63
369	*
370	* @todo If we run low on VMCPU, we may consider merging the SELM bits
371	*
372	* @{
373	*/
374	/** The virtual sync clock has been stopped, go to TM until it has been
375	* restarted... */
376	#define VM_FF_TM_VIRTUAL_SYNC RT_BIT_32(VM_FF_TM_VIRTUAL_SYNC_BIT)
377	#define VM_FF_TM_VIRTUAL_SYNC_BIT 2
378	/** PDM Queues are pending. */
379	#define VM_FF_PDM_QUEUES RT_BIT_32(VM_FF_PDM_QUEUES_BIT)
380	/** The bit number for VM_FF_PDM_QUEUES. */
381	#define VM_FF_PDM_QUEUES_BIT 3
382	/** PDM DMA transfers are pending. */
383	#define VM_FF_PDM_DMA RT_BIT_32(VM_FF_PDM_DMA_BIT)
384	/** The bit number for VM_FF_PDM_DMA. */
385	#define VM_FF_PDM_DMA_BIT 4
386	/** This action forces the VM to call DBGF so DBGF can service debugger
387	* requests in the emulation thread.
388	* This action flag stays asserted till DBGF clears it.*/
389	#define VM_FF_DBGF RT_BIT_32(VM_FF_DBGF_BIT)
390	/** The bit number for VM_FF_DBGF. */
391	#define VM_FF_DBGF_BIT 8
392	/** This action forces the VM to service pending requests from other
393	* thread or requests which must be executed in another context. */
394	#define VM_FF_REQUEST RT_BIT_32(VM_FF_REQUEST_BIT)
395	#define VM_FF_REQUEST_BIT 9
396	/** Check for VM state changes and take appropriate action. */
397	#define VM_FF_CHECK_VM_STATE RT_BIT_32(VM_FF_CHECK_VM_STATE_BIT)
398	/** The bit number for VM_FF_CHECK_VM_STATE. */
399	#define VM_FF_CHECK_VM_STATE_BIT 10
400	/** Reset the VM. (postponed) */
401	#define VM_FF_RESET RT_BIT_32(VM_FF_RESET_BIT)
402	/** The bit number for VM_FF_RESET. */
403	#define VM_FF_RESET_BIT 11
404	/** EMT rendezvous in VMM. */
405	#define VM_FF_EMT_RENDEZVOUS RT_BIT_32(VM_FF_EMT_RENDEZVOUS_BIT)
406	/** The bit number for VM_FF_EMT_RENDEZVOUS. */
407	#define VM_FF_EMT_RENDEZVOUS_BIT 12
408
409	/** PGM needs to allocate handy pages. */
410	#define VM_FF_PGM_NEED_HANDY_PAGES RT_BIT_32(VM_FF_PGM_NEED_HANDY_PAGES_BIT)
411	#define VM_FF_PGM_NEED_HANDY_PAGES_BIT 18
412	/** PGM is out of memory.
413	* Abandon all loops and code paths which can be resumed and get up to the EM
414	* loops. */
415	#define VM_FF_PGM_NO_MEMORY RT_BIT_32(VM_FF_PGM_NO_MEMORY_BIT)
416	#define VM_FF_PGM_NO_MEMORY_BIT 19
417	/** PGM is about to perform a lightweight pool flush
418	* Guest SMP: all EMT threads should return to ring 3
419	*/
420	#define VM_FF_PGM_POOL_FLUSH_PENDING RT_BIT_32(VM_FF_PGM_POOL_FLUSH_PENDING_BIT)
421	#define VM_FF_PGM_POOL_FLUSH_PENDING_BIT 20
422	/** REM needs to be informed about handler changes. */
423	#define VM_FF_REM_HANDLER_NOTIFY RT_BIT_32(VM_FF_REM_HANDLER_NOTIFY_BIT)
424	/** The bit number for VM_FF_REM_HANDLER_NOTIFY. */
425	#define VM_FF_REM_HANDLER_NOTIFY_BIT 29
426	/** Suspend the VM - debug only. */
427	#define VM_FF_DEBUG_SUSPEND RT_BIT_32(VM_FF_DEBUG_SUSPEND_BIT)
428	#define VM_FF_DEBUG_SUSPEND_BIT 31
429
430
431	/** This action forces the VM to check any pending interrupts on the APIC. */
432	#define VMCPU_FF_INTERRUPT_APIC RT_BIT_64(VMCPU_FF_INTERRUPT_APIC_BIT)
433	#define VMCPU_FF_INTERRUPT_APIC_BIT 0
434	/** This action forces the VM to check any pending interrups on the PIC. */
435	#define VMCPU_FF_INTERRUPT_PIC RT_BIT_64(VMCPU_FF_INTERRUPT_PIC_BIT)
436	#define VMCPU_FF_INTERRUPT_PIC_BIT 1
437	/** This action forces the VM to schedule and run pending timer (TM).
438	* @remarks Don't move - PATM compatibility. */
439	#define VMCPU_FF_TIMER RT_BIT_64(VMCPU_FF_TIMER_BIT)
440	#define VMCPU_FF_TIMER_BIT 2
441	/** This action forces the VM to check any pending NMIs. */
442	#define VMCPU_FF_INTERRUPT_NMI RT_BIT_64(VMCPU_FF_INTERRUPT_NMI_BIT)
443	#define VMCPU_FF_INTERRUPT_NMI_BIT 3
444	/** This action forces the VM to check any pending SMIs. */
445	#define VMCPU_FF_INTERRUPT_SMI RT_BIT_64(VMCPU_FF_INTERRUPT_SMI_BIT)
446	#define VMCPU_FF_INTERRUPT_SMI_BIT 4
447	/** PDM critical section unlocking is pending, process promptly upon return to R3. */
448	#define VMCPU_FF_PDM_CRITSECT RT_BIT_64(VMCPU_FF_PDM_CRITSECT_BIT)
449	#define VMCPU_FF_PDM_CRITSECT_BIT 5
450	/** Special EM internal force flag that is used by EMUnhaltAndWakeUp() to force
451	* the virtual CPU out of the next (/current) halted state. It is not processed
452	* nor cleared by emR3ForcedActions (similar to VMCPU_FF_BLOCK_NMIS), instead it
453	* is cleared the next time EM leaves the HALTED state. */
454	#define VMCPU_FF_UNHALT RT_BIT_64(VMCPU_FF_UNHALT_BIT)
455	#define VMCPU_FF_UNHALT_BIT 6
456	/** Pending IEM action (mask). */
457	#define VMCPU_FF_IEM RT_BIT_64(VMCPU_FF_IEM_BIT)
458	/** Pending IEM action (bit number). */
459	#define VMCPU_FF_IEM_BIT 7
460	/** Pending APIC action (bit number). */
461	#define VMCPU_FF_UPDATE_APIC_BIT 8
462	/** This action forces the VM to update APIC's asynchronously arrived
463	* interrupts as pending interrupts. */
464	#define VMCPU_FF_UPDATE_APIC RT_BIT_64(VMCPU_FF_UPDATE_APIC_BIT)
465	/** This action forces the VM to service pending requests from other
466	* thread or requests which must be executed in another context. */
467	#define VMCPU_FF_REQUEST RT_BIT_64(VMCPU_FF_REQUEST_BIT)
468	#define VMCPU_FF_REQUEST_BIT 9
469	/** Pending DBGF event (alternative to passing VINF_EM_DBG_EVENT around). */
470	#define VMCPU_FF_DBGF RT_BIT_64(VMCPU_FF_DBGF_BIT)
471	/** The bit number for VMCPU_FF_DBGF. */
472	#define VMCPU_FF_DBGF_BIT 10
473	/** Pending MTF (Monitor Trap Flag) event - Intel only. */
474	#define VMCPU_FF_MTF RT_BIT_64(VMCPU_FF_MTF_BIT)
475	/** The bit number for VMCPU_FF_MTF. */
476	#define VMCPU_FF_MTF_BIT 11
477	/** This action forces the VM to service any pending updates to CR3 (used only
478	* by HM). */
479	#define VMCPU_FF_HM_UPDATE_CR3 RT_BIT_64(VMCPU_FF_HM_UPDATE_CR3_BIT)
480	#define VMCPU_FF_HM_UPDATE_CR3_BIT 12
481	/** This action forces the VM to service any pending updates to PAE PDPEs (used
482	* only by HM). */
483	#define VMCPU_FF_HM_UPDATE_PAE_PDPES RT_BIT_64(VMCPU_FF_HM_UPDATE_PAE_PDPES_BIT)
484	#define VMCPU_FF_HM_UPDATE_PAE_PDPES_BIT 13
485	/** This action forces the VM to resync the page tables before going
486	* back to execute guest code. (GLOBAL FLUSH) */
487	#define VMCPU_FF_PGM_SYNC_CR3 RT_BIT_64(VMCPU_FF_PGM_SYNC_CR3_BIT)
488	#define VMCPU_FF_PGM_SYNC_CR3_BIT 16
489	/** Same as VM_FF_PGM_SYNC_CR3 except that global pages can be skipped.
490	* (NON-GLOBAL FLUSH) */
491	#define VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL RT_BIT_64(VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL_BIT)
492	#define VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL_BIT 17
493	/** Check for pending TLB shootdown actions (deprecated)
494	* Reserved for furture HM re-use if necessary / safe.
495	* Consumer: HM */
496	#define VMCPU_FF_TLB_SHOOTDOWN_UNUSED RT_BIT_64(VMCPU_FF_TLB_SHOOTDOWN_UNUSED_BIT)
497	#define VMCPU_FF_TLB_SHOOTDOWN_UNUSED_BIT 18
498	/** Check for pending TLB flush action.
499	* Consumer: HM
500	* @todo rename to VMCPU_FF_HM_TLB_FLUSH */
501	#define VMCPU_FF_TLB_FLUSH RT_BIT_64(VMCPU_FF_TLB_FLUSH_BIT)
502	/** The bit number for VMCPU_FF_TLB_FLUSH. */
503	#define VMCPU_FF_TLB_FLUSH_BIT 19
504	#ifdef VBOX_WITH_RAW_MODE
505	/** Check the interrupt and trap gates */
506	# define VMCPU_FF_TRPM_SYNC_IDT RT_BIT_64(VMCPU_FF_TRPM_SYNC_IDT_BIT)
507	# define VMCPU_FF_TRPM_SYNC_IDT_BIT 20
508	/** Check Guest's TSS ring 0 stack */
509	# define VMCPU_FF_SELM_SYNC_TSS RT_BIT_64(VMCPU_FF_SELM_SYNC_TSS_BIT)
510	# define VMCPU_FF_SELM_SYNC_TSS_BIT 21
511	/** Check Guest's GDT table */
512	# define VMCPU_FF_SELM_SYNC_GDT RT_BIT_64(VMCPU_FF_SELM_SYNC_GDT_BIT)
513	# define VMCPU_FF_SELM_SYNC_GDT_BIT 22
514	/** Check Guest's LDT table */
515	# define VMCPU_FF_SELM_SYNC_LDT RT_BIT_64(VMCPU_FF_SELM_SYNC_LDT_BIT)
516	# define VMCPU_FF_SELM_SYNC_LDT_BIT 23
517	#endif /* VBOX_WITH_RAW_MODE */
518	/** Inhibit interrupts pending. See EMGetInhibitInterruptsPC(). */
519	#define VMCPU_FF_INHIBIT_INTERRUPTS RT_BIT_64(VMCPU_FF_INHIBIT_INTERRUPTS_BIT)
520	#define VMCPU_FF_INHIBIT_INTERRUPTS_BIT 24
521	/** Block injection of non-maskable interrupts to the guest. */
522	#define VMCPU_FF_BLOCK_NMIS RT_BIT_64(VMCPU_FF_BLOCK_NMIS_BIT)
523	#define VMCPU_FF_BLOCK_NMIS_BIT 25
524	#ifdef VBOX_WITH_RAW_MODE
525	/** CSAM needs to scan the page that's being executed */
526	# define VMCPU_FF_CSAM_SCAN_PAGE RT_BIT_64(VMCPU_FF_CSAM_SCAN_PAGE_BIT)
527	# define VMCPU_FF_CSAM_SCAN_PAGE_BIT 26
528	/** CSAM needs to do some homework. */
529	# define VMCPU_FF_CSAM_PENDING_ACTION RT_BIT_64(VMCPU_FF_CSAM_PENDING_ACTION_BIT)
530	# define VMCPU_FF_CSAM_PENDING_ACTION_BIT 27
531	#endif /* VBOX_WITH_RAW_MODE */
532	/** Force return to Ring-3. */
533	#define VMCPU_FF_TO_R3 RT_BIT_64(VMCPU_FF_TO_R3_BIT)
534	#define VMCPU_FF_TO_R3_BIT 28
535	/** Force return to ring-3 to service pending I/O or MMIO write.
536	* This is a backup for mechanism VINF_IOM_R3_IOPORT_COMMIT_WRITE and
537	* VINF_IOM_R3_MMIO_COMMIT_WRITE, allowing VINF_EM_DBG_BREAKPOINT and similar
538	* status codes to be propagated at the same time without loss. */
539	#define VMCPU_FF_IOM RT_BIT_64(VMCPU_FF_IOM_BIT)
540	#define VMCPU_FF_IOM_BIT 29
541	#ifdef VBOX_WITH_RAW_MODE
542	/** CPUM need to adjust CR0.TS/EM before executing raw-mode code again. */
543	# define VMCPU_FF_CPUM RT_BIT_64(VMCPU_FF_CPUM_BIT)
544	/** The bit number for VMCPU_FF_CPUM. */
545	# define VMCPU_FF_CPUM_BIT 30
546	#endif /* VBOX_WITH_RAW_MODE */
547	/** Hardware virtualized nested-guest interrupt pending. */
548	#define VMCPU_FF_INTERRUPT_NESTED_GUEST RT_BIT_64(VMCPU_FF_INTERRUPT_NESTED_GUEST_BIT)
549	#define VMCPU_FF_INTERRUPT_NESTED_GUEST_BIT 31
550	/** VMX-preemption timer in effect. */
551	#define VMCPU_FF_VMX_PREEMPT_TIMER RT_BIT_64(VMCPU_FF_VMX_PREEMPT_TIMER_BIT)
552	#define VMCPU_FF_VMX_PREEMPT_TIMER_BIT 32
553
554
555	/** Externally VM forced actions. Used to quit the idle/wait loop. */
556	#define VM_FF_EXTERNAL_SUSPENDED_MASK ( VM_FF_CHECK_VM_STATE \| VM_FF_DBGF \| VM_FF_REQUEST \| VM_FF_EMT_RENDEZVOUS )
557	/** Externally VMCPU forced actions. Used to quit the idle/wait loop. */
558	#define VMCPU_FF_EXTERNAL_SUSPENDED_MASK ( VMCPU_FF_REQUEST \| VMCPU_FF_DBGF )
559
560	/** Externally forced VM actions. Used to quit the idle/wait loop. */
561	#define VM_FF_EXTERNAL_HALTED_MASK ( VM_FF_CHECK_VM_STATE \| VM_FF_DBGF \| VM_FF_REQUEST \
562	\| VM_FF_PDM_QUEUES \| VM_FF_PDM_DMA \| VM_FF_EMT_RENDEZVOUS )
563	/** Externally forced VMCPU actions. Used to quit the idle/wait loop. */
564	#define VMCPU_FF_EXTERNAL_HALTED_MASK ( VMCPU_FF_UPDATE_APIC \| VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC \
565	\| VMCPU_FF_REQUEST \| VMCPU_FF_INTERRUPT_NMI \| VMCPU_FF_INTERRUPT_SMI \
566	\| VMCPU_FF_UNHALT \| VMCPU_FF_TIMER \| VMCPU_FF_DBGF )
567
568	/** High priority VM pre-execution actions. */
569	#define VM_FF_HIGH_PRIORITY_PRE_MASK ( VM_FF_CHECK_VM_STATE \| VM_FF_DBGF \| VM_FF_TM_VIRTUAL_SYNC \
570	\| VM_FF_DEBUG_SUSPEND \| VM_FF_PGM_NEED_HANDY_PAGES \| VM_FF_PGM_NO_MEMORY \
571	\| VM_FF_EMT_RENDEZVOUS )
572	/** High priority VMCPU pre-execution actions. */
573	#define VMCPU_FF_HIGH_PRIORITY_PRE_MASK ( VMCPU_FF_TIMER \| VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC \
574	\| VMCPU_FF_UPDATE_APIC \| VMCPU_FF_INHIBIT_INTERRUPTS \| VMCPU_FF_DBGF \
575	\| VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL \
576	\| VM_WHEN_RAW_MODE( VMCPU_FF_SELM_SYNC_TSS \| VMCPU_FF_TRPM_SYNC_IDT \
577	\| VMCPU_FF_SELM_SYNC_GDT \| VMCPU_FF_SELM_SYNC_LDT, 0 ) )
578
579	/** High priority VM pre raw-mode execution mask. */
580	#define VM_FF_HIGH_PRIORITY_PRE_RAW_MASK ( VM_FF_PGM_NEED_HANDY_PAGES \| VM_FF_PGM_NO_MEMORY )
581	/** High priority VMCPU pre raw-mode execution mask. */
582	#define VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK ( VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL \
583	\| VMCPU_FF_INHIBIT_INTERRUPTS \
584	\| VM_WHEN_RAW_MODE( VMCPU_FF_SELM_SYNC_TSS \| VMCPU_FF_TRPM_SYNC_IDT \
585	\| VMCPU_FF_SELM_SYNC_GDT \| VMCPU_FF_SELM_SYNC_LDT, 0) )
586
587	/** High priority post-execution actions. */
588	#define VM_FF_HIGH_PRIORITY_POST_MASK ( VM_FF_PGM_NO_MEMORY )
589	/** High priority post-execution actions. */
590	#define VMCPU_FF_HIGH_PRIORITY_POST_MASK ( VMCPU_FF_PDM_CRITSECT \| VM_WHEN_RAW_MODE(VMCPU_FF_CSAM_PENDING_ACTION, 0) \
591	\| VMCPU_FF_HM_UPDATE_CR3 \| VMCPU_FF_HM_UPDATE_PAE_PDPES \
592	\| VMCPU_FF_IEM \| VMCPU_FF_IOM )
593
594	/** Normal priority VM post-execution actions. */
595	#define VM_FF_NORMAL_PRIORITY_POST_MASK ( VM_FF_CHECK_VM_STATE \| VM_FF_DBGF \| VM_FF_RESET \
596	\| VM_FF_PGM_NO_MEMORY \| VM_FF_EMT_RENDEZVOUS)
597	/** Normal priority VMCPU post-execution actions. */
598	#define VMCPU_FF_NORMAL_PRIORITY_POST_MASK ( VM_WHEN_RAW_MODE(VMCPU_FF_CSAM_SCAN_PAGE, 0) \| VMCPU_FF_DBGF )
599
600	/** Normal priority VM actions. */
601	#define VM_FF_NORMAL_PRIORITY_MASK ( VM_FF_REQUEST \| VM_FF_PDM_QUEUES \| VM_FF_PDM_DMA \
602	\| VM_FF_REM_HANDLER_NOTIFY \| VM_FF_EMT_RENDEZVOUS)
603	/** Normal priority VMCPU actions. */
604	#define VMCPU_FF_NORMAL_PRIORITY_MASK ( VMCPU_FF_REQUEST )
605
606	/** Flags to clear before resuming guest execution. */
607	#define VMCPU_FF_RESUME_GUEST_MASK ( VMCPU_FF_TO_R3 )
608
609
610	/** VM flags that cause the REP[\|NE\|E] STRINS loops to yield immediately. */
611	#define VM_FF_HIGH_PRIORITY_POST_REPSTR_MASK ( VM_FF_TM_VIRTUAL_SYNC \| VM_FF_PGM_NEED_HANDY_PAGES \| VM_FF_PGM_NO_MEMORY \
612	\| VM_FF_EMT_RENDEZVOUS \| VM_FF_PGM_POOL_FLUSH_PENDING \| VM_FF_RESET)
613	/** VM flags that cause the REP[\|NE\|E] STRINS loops to yield. */
614	#define VM_FF_YIELD_REPSTR_MASK ( VM_FF_HIGH_PRIORITY_POST_REPSTR_MASK \
615	\| VM_FF_PDM_QUEUES \| VM_FF_PDM_DMA \| VM_FF_DBGF \| VM_FF_DEBUG_SUSPEND )
616	/** VMCPU flags that cause the REP[\|NE\|E] STRINS loops to yield immediately. */
617	#ifdef IN_RING3
618	# define VMCPU_FF_HIGH_PRIORITY_POST_REPSTR_MASK ( VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL \| VMCPU_FF_DBGF )
619	#else
620	# define VMCPU_FF_HIGH_PRIORITY_POST_REPSTR_MASK ( VMCPU_FF_TO_R3 \| VMCPU_FF_IEM \| VMCPU_FF_IOM \| VMCPU_FF_PGM_SYNC_CR3 \
621	\| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL \| VMCPU_FF_DBGF )
622	#endif
623	/** VMCPU flags that cause the REP[\|NE\|E] STRINS loops to yield, interrupts
624	* enabled. */
625	#define VMCPU_FF_YIELD_REPSTR_MASK ( VMCPU_FF_HIGH_PRIORITY_POST_REPSTR_MASK \
626	\| VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_UPDATE_APIC \| VMCPU_FF_INTERRUPT_PIC \
627	\| VMCPU_FF_INTERRUPT_NMI \| VMCPU_FF_INTERRUPT_SMI \| VMCPU_FF_PDM_CRITSECT \
628	\| VMCPU_FF_TIMER \| VMCPU_FF_REQUEST )
629	/** VMCPU flags that cause the REP[\|NE\|E] STRINS loops to yield, interrupts
630	* disabled. */
631	#define VMCPU_FF_YIELD_REPSTR_NOINT_MASK ( VMCPU_FF_YIELD_REPSTR_MASK \
632	& ~(VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_UPDATE_APIC \| VMCPU_FF_INTERRUPT_PIC) )
633
634	/** VM Flags that cause the HM loops to go back to ring-3. */
635	#define VM_FF_HM_TO_R3_MASK ( VM_FF_TM_VIRTUAL_SYNC \| VM_FF_PGM_NEED_HANDY_PAGES \| VM_FF_PGM_NO_MEMORY \
636	\| VM_FF_PDM_QUEUES \| VM_FF_EMT_RENDEZVOUS)
637	/** VMCPU Flags that cause the HM loops to go back to ring-3. */
638	#define VMCPU_FF_HM_TO_R3_MASK ( VMCPU_FF_TO_R3 \| VMCPU_FF_TIMER \| VMCPU_FF_PDM_CRITSECT \
639	\| VMCPU_FF_IEM \| VMCPU_FF_IOM)
640
641	/** High priority ring-0 VM pre HM-mode execution mask. */
642	#define VM_FF_HP_R0_PRE_HM_MASK (VM_FF_HM_TO_R3_MASK \| VM_FF_REQUEST \| VM_FF_PGM_POOL_FLUSH_PENDING \| VM_FF_PDM_DMA)
643	/** High priority ring-0 VMCPU pre HM-mode execution mask. */
644	#define VMCPU_FF_HP_R0_PRE_HM_MASK ( VMCPU_FF_HM_TO_R3_MASK \| VMCPU_FF_PGM_SYNC_CR3 \
645	\| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL \| VMCPU_FF_REQUEST)
646	/** High priority ring-0 VM pre HM-mode execution mask, single stepping. */
647	#define VM_FF_HP_R0_PRE_HM_STEP_MASK (VM_FF_HP_R0_PRE_HM_MASK & ~( VM_FF_TM_VIRTUAL_SYNC \| VM_FF_PDM_QUEUES \
648	\| VM_FF_EMT_RENDEZVOUS \| VM_FF_REQUEST \
649	\| VM_FF_PDM_DMA) )
650	/** High priority ring-0 VMCPU pre HM-mode execution mask, single stepping. */
651	#define VMCPU_FF_HP_R0_PRE_HM_STEP_MASK (VMCPU_FF_HP_R0_PRE_HM_MASK & ~( VMCPU_FF_TO_R3 \| VMCPU_FF_TIMER \
652	\| VMCPU_FF_PDM_CRITSECT \| VMCPU_FF_REQUEST) )
653
654	/** All the forced VM flags. */
655	#define VM_FF_ALL_MASK (UINT32_MAX)
656	/** All the forced VMCPU flags. */
657	#define VMCPU_FF_ALL_MASK (UINT32_MAX)
658
659	/** All the forced VM flags except those related to raw-mode and hardware
660	* assisted execution. */
661	#define VM_FF_ALL_REM_MASK (~(VM_FF_HIGH_PRIORITY_PRE_RAW_MASK) \| VM_FF_PGM_NEED_HANDY_PAGES \| VM_FF_PGM_NO_MEMORY)
662	/** All the forced VMCPU flags except those related to raw-mode and hardware
663	* assisted execution. */
664	#define VMCPU_FF_ALL_REM_MASK (~( VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK \| VMCPU_FF_PDM_CRITSECT \
665	\| VMCPU_FF_TLB_FLUSH \| VM_WHEN_RAW_MODE(VMCPU_FF_CSAM_PENDING_ACTION, 0) ))
666	/** @} */
667
668	/** @def VM_FF_SET
669	* Sets a single force action flag.
670	*
671	* @param pVM The cross context VM structure.
672	* @param fFlag The flag to set.
673	*/
674	#define VM_FF_SET(pVM, fFlag) do { \
675	AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
676	AssertCompile((fFlag) == RT_BIT_32(fFlag##_BIT)); \
677	ASMAtomicOrU32(&(pVM)->fGlobalForcedActions, (fFlag)); \
678	} while (0)
679
680	/** @def VMCPU_FF_SET
681	* Sets a single force action flag for the given VCPU.
682	*
683	* @param pVCpu The cross context virtual CPU structure.
684	* @param fFlag The flag to set.
685	* @sa VMCPU_FF_SET_MASK
686	*/
687	#ifdef VMCPU_WITH_64_BIT_FFS
688	# define VMCPU_FF_SET(pVCpu, fFlag) do { \
689	AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
690	AssertCompile((fFlag) == RT_BIT_64(fFlag##_BIT)); \
691	ASMAtomicBitSet(&(pVCpu)->fLocalForcedActions, fFlag##_BIT); \
692	} while (0)
693	#else
694	# define VMCPU_FF_SET(pVCpu, fFlag) do { \
695	AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
696	AssertCompile((fFlag) == RT_BIT_32(fFlag##_BIT)); \
697	ASMAtomicOrU32(&(pVCpu)->fLocalForcedActions, (fFlag)); \
698	} while (0)
699	#endif
700
701	/** @def VMCPU_FF_SET_MASK
702	* Sets a two or more force action flag for the given VCPU.
703	*
704	* @param pVCpu The cross context virtual CPU structure.
705	* @param fFlags The flags to set.
706	* @sa VMCPU_FF_SET
707	*/
708	#ifdef VMCPU_WITH_64_BIT_FFS
709	# if ARCH_BITS > 32
710	# define VMCPU_FF_SET_MASK(pVCpu, fFlags) \
711	do { ASMAtomicOrU64(&pVCpu->fLocalForcedActions, (fFlags)); } while (0)
712	# else
713	# define VMCPU_FF_SET_MASK(pVCpu, fFlags) do { \
714	if (!((fFlags) >> 32)) ASMAtomicOrU32((uint32_t volatile *)&pVCpu->fLocalForcedActions, (uint32_t)(fFlags)); \
715	else ASMAtomicOrU64(&pVCpu->fLocalForcedActions, (fFlags)); \
716	} while (0)
717	# endif
718	#else
719	# define VMCPU_FF_SET_MASK(pVCpu, fFlags) \
720	do { ASMAtomicOrU32(&pVCpu->fLocalForcedActions, (fFlags)); } while (0)
721	#endif
722
723	/** @def VM_FF_CLEAR
724	* Clears a single force action flag.
725	*
726	* @param pVM The cross context VM structure.
727	* @param fFlag The flag to clear.
728	*/
729	#define VM_FF_CLEAR(pVM, fFlag) do { \
730	AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
731	AssertCompile((fFlag) == RT_BIT_32(fFlag##_BIT)); \
732	ASMAtomicAndU32(&(pVM)->fGlobalForcedActions, ~(fFlag)); \
733	} while (0)
734
735	/** @def VMCPU_FF_CLEAR
736	* Clears a single force action flag for the given VCPU.
737	*
738	* @param pVCpu The cross context virtual CPU structure.
739	* @param fFlag The flag to clear.
740	*/
741	#ifdef VMCPU_WITH_64_BIT_FFS
742	# define VMCPU_FF_CLEAR(pVCpu, fFlag) do { \
743	AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
744	AssertCompile((fFlag) == RT_BIT_64(fFlag##_BIT)); \
745	ASMAtomicBitClear(&(pVCpu)->fLocalForcedActions, fFlag##_BIT); \
746	} while (0)
747	#else
748	# define VMCPU_FF_CLEAR(pVCpu, fFlag) do { \
749	AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
750	AssertCompile((fFlag) == RT_BIT_32(fFlag##_BIT)); \
751	ASMAtomicAndU32(&(pVCpu)->fLocalForcedActions, ~(fFlag)); \
752	} while (0)
753	#endif
754
755	/** @def VMCPU_FF_CLEAR_MASK
756	* Clears two or more force action flags for the given VCPU.
757	*
758	* @param pVCpu The cross context virtual CPU structure.
759	* @param fFlags The flags to clear.
760	*/
761	#ifdef VMCPU_WITH_64_BIT_FFS
762	# if ARCH_BITS > 32
763	# define VMCPU_FF_CLEAR_MASK(pVCpu, fFlags) \
764	do { ASMAtomicAndU64(&(pVCpu)->fLocalForcedActions, ~(fFlags)); } while (0)
765	# else
766	# define VMCPU_FF_CLEAR_MASK(pVCpu, fFlags) do { \
767	if (!((fFlags) >> 32)) ASMAtomicAndU32((uint32_t volatile *)&(pVCpu)->fLocalForcedActions, ~(uint32_t)(fFlags)); \
768	else ASMAtomicAndU64(&(pVCpu)->fLocalForcedActions, ~(fFlags)); \
769	} while (0)
770	# endif
771	#else
772	# define VMCPU_FF_CLEAR_MASK(pVCpu, fFlags) \
773	do { ASMAtomicAndU32(&(pVCpu)->fLocalForcedActions, ~(fFlags)); } while (0)
774	#endif
775
776	/** @def VM_FF_IS_SET
777	* Checks if single a force action flag is set.
778	*
779	* @param pVM The cross context VM structure.
780	* @param fFlag The flag to check.
781	* @sa VM_FF_IS_ANY_SET
782	*/
783	#if !defined(VBOX_STRICT) \|\| !defined(RT_COMPILER_SUPPORTS_LAMBDA)
784	# define VM_FF_IS_SET(pVM, fFlag) RT_BOOL((pVM)->fGlobalForcedActions & (fFlag))
785	#else
786	# define VM_FF_IS_SET(pVM, fFlag) \
787	([](PVM a_pVM) -> bool \
788	{ \
789	AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
790	AssertCompile((fFlag) == RT_BIT_32(fFlag##_BIT)); \
791	return RT_BOOL(a_pVM->fGlobalForcedActions & (fFlag)); \
792	}(pVM))
793	#endif
794
795	/** @def VMCPU_FF_IS_SET
796	* Checks if a single force action flag is set for the given VCPU.
797	*
798	* @param pVCpu The cross context virtual CPU structure.
799	* @param fFlag The flag to check.
800	* @sa VMCPU_FF_IS_ANY_SET
801	*/
802	#if !defined(VBOX_STRICT) \|\| !defined(RT_COMPILER_SUPPORTS_LAMBDA)
803	# define VMCPU_FF_IS_SET(pVCpu, fFlag) RT_BOOL((pVCpu)->fLocalForcedActions & (fFlag))
804	#else
805	# define VMCPU_FF_IS_SET(pVCpu, fFlag) \
806	([](PVMCPU a_pVCpu) -> bool \
807	{ \
808	AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
809	AssertCompile((fFlag) == RT_BIT_64(fFlag##_BIT)); \
810	return RT_BOOL(a_pVCpu->fLocalForcedActions & (fFlag)); \
811	}(pVCpu))
812	#endif
813
814	/** @def VM_FF_IS_ANY_SET
815	* Checks if one or more force action in the specified set is pending.
816	*
817	* @param pVM The cross context VM structure.
818	* @param fFlags The flags to check for.
819	* @sa VM_FF_IS_SET
820	*/
821	#define VM_FF_IS_ANY_SET(pVM, fFlags) RT_BOOL((pVM)->fGlobalForcedActions & (fFlags))
822
823	/** @def VMCPU_FF_IS_ANY_SET
824	* Checks if two or more force action flags in the specified set is set for the given VCPU.
825	*
826	* @param pVCpu The cross context virtual CPU structure.
827	* @param fFlags The flags to check for.
828	* @sa VMCPU_FF_IS_SET
829	*/
830	#define VMCPU_FF_IS_ANY_SET(pVCpu, fFlags) RT_BOOL((pVCpu)->fLocalForcedActions & (fFlags))
831
832	/** @def VM_FF_TEST_AND_CLEAR
833	* Checks if one (!) force action in the specified set is pending and clears it atomically
834	*
835	* @returns true if the bit was set.
836	* @returns false if the bit was clear.
837	* @param pVM The cross context VM structure.
838	* @param fFlag Flag constant to check and clear (_BIT is appended).
839	*/
840	#define VM_FF_TEST_AND_CLEAR(pVM, fFlag) (ASMAtomicBitTestAndClear(&(pVM)->fGlobalForcedActions, fFlag##_BIT))
841
842	/** @def VMCPU_FF_TEST_AND_CLEAR
843	* Checks if one (!) force action in the specified set is pending and clears it atomically
844	*
845	* @returns true if the bit was set.
846	* @returns false if the bit was clear.
847	* @param pVCpu The cross context virtual CPU structure.
848	* @param fFlag Flag constant to check and clear (_BIT is appended).
849	*/
850	#define VMCPU_FF_TEST_AND_CLEAR(pVCpu, fFlag) (ASMAtomicBitTestAndClear(&(pVCpu)->fLocalForcedActions, fFlag##_BIT))
851
852	/** @def VM_FF_IS_PENDING_EXCEPT
853	* Checks if one or more force action in the specified set is pending while one
854	* or more other ones are not.
855	*
856	* @param pVM The cross context VM structure.
857	* @param fFlags The flags to check for.
858	* @param fExcpt The flags that should not be set.
859	*/
860	#define VM_FF_IS_PENDING_EXCEPT(pVM, fFlags, fExcpt) \
861	( ((pVM)->fGlobalForcedActions & (fFlags)) && !((pVM)->fGlobalForcedActions & (fExcpt)) )
862
863	/** @def VM_IS_EMT
864	* Checks if the current thread is the emulation thread (EMT).
865	*
866	* @remark The ring-0 variation will need attention if we expand the ring-0
867	* code to let threads other than EMT mess around with the VM.
868	*/
869	#ifdef IN_RC
870	# define VM_IS_EMT(pVM) true
871	#else
872	# define VM_IS_EMT(pVM) (VMMGetCpu(pVM) != NULL)
873	#endif
874
875	/** @def VMCPU_IS_EMT
876	* Checks if the current thread is the emulation thread (EMT) for the specified
877	* virtual CPU.
878	*/
879	#ifdef IN_RC
880	# define VMCPU_IS_EMT(pVCpu) true
881	#else
882	# define VMCPU_IS_EMT(pVCpu) ((pVCpu) && ((pVCpu) == VMMGetCpu((pVCpu)->CTX_SUFF(pVM))))
883	#endif
884
885	/** @def VM_ASSERT_EMT
886	* Asserts that the current thread IS the emulation thread (EMT).
887	*/
888	#ifdef IN_RC
889	# define VM_ASSERT_EMT(pVM) Assert(VM_IS_EMT(pVM))
890	#elif defined(IN_RING0)
891	# define VM_ASSERT_EMT(pVM) Assert(VM_IS_EMT(pVM))
892	#else
893	# define VM_ASSERT_EMT(pVM) \
894	AssertMsg(VM_IS_EMT(pVM), \
895	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd\n", RTThreadNativeSelf(), VMR3GetVMCPUNativeThread(pVM)))
896	#endif
897
898	/** @def VMCPU_ASSERT_EMT
899	* Asserts that the current thread IS the emulation thread (EMT) of the
900	* specified virtual CPU.
901	*/
902	#ifdef IN_RC
903	# define VMCPU_ASSERT_EMT(pVCpu) Assert(VMCPU_IS_EMT(pVCpu))
904	#elif defined(IN_RING0)
905	# define VMCPU_ASSERT_EMT(pVCpu) AssertMsg(VMCPU_IS_EMT(pVCpu), \
906	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd idCpu=%u\n", \
907	RTThreadNativeSelf(), (pVCpu) ? (pVCpu)->hNativeThreadR0 : 0, \
908	(pVCpu) ? (pVCpu)->idCpu : 0))
909	#else
910	# define VMCPU_ASSERT_EMT(pVCpu) AssertMsg(VMCPU_IS_EMT(pVCpu), \
911	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd idCpu=%#x\n", \
912	RTThreadNativeSelf(), (pVCpu)->hNativeThread, (pVCpu)->idCpu))
913	#endif
914
915	/** @def VM_ASSERT_EMT_RETURN
916	* Asserts that the current thread IS the emulation thread (EMT) and returns if it isn't.
917	*/
918	#ifdef IN_RC
919	# define VM_ASSERT_EMT_RETURN(pVM, rc) AssertReturn(VM_IS_EMT(pVM), (rc))
920	#elif defined(IN_RING0)
921	# define VM_ASSERT_EMT_RETURN(pVM, rc) AssertReturn(VM_IS_EMT(pVM), (rc))
922	#else
923	# define VM_ASSERT_EMT_RETURN(pVM, rc) \
924	AssertMsgReturn(VM_IS_EMT(pVM), \
925	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd\n", RTThreadNativeSelf(), VMR3GetVMCPUNativeThread(pVM)), \
926	(rc))
927	#endif
928
929	/** @def VMCPU_ASSERT_EMT_RETURN
930	* Asserts that the current thread IS the emulation thread (EMT) and returns if it isn't.
931	*/
932	#ifdef IN_RC
933	# define VMCPU_ASSERT_EMT_RETURN(pVCpu, rc) AssertReturn(VMCPU_IS_EMT(pVCpu), (rc))
934	#elif defined(IN_RING0)
935	# define VMCPU_ASSERT_EMT_RETURN(pVCpu, rc) AssertReturn(VMCPU_IS_EMT(pVCpu), (rc))
936	#else
937	# define VMCPU_ASSERT_EMT_RETURN(pVCpu, rc) \
938	AssertMsgReturn(VMCPU_IS_EMT(pVCpu), \
939	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd idCpu=%#x\n", \
940	RTThreadNativeSelf(), (pVCpu)->hNativeThread, (pVCpu)->idCpu), \
941	(rc))
942	#endif
943
944	/** @def VMCPU_ASSERT_EMT_OR_GURU
945	* Asserts that the current thread IS the emulation thread (EMT) of the
946	* specified virtual CPU.
947	*/
948	#if defined(IN_RC) \|\| defined(IN_RING0)
949	# define VMCPU_ASSERT_EMT_OR_GURU(pVCpu) Assert( VMCPU_IS_EMT(pVCpu) \
950	\|\| pVCpu->CTX_SUFF(pVM)->enmVMState == VMSTATE_GURU_MEDITATION \
951	\|\| pVCpu->CTX_SUFF(pVM)->enmVMState == VMSTATE_GURU_MEDITATION_LS )
952	#else
953	# define VMCPU_ASSERT_EMT_OR_GURU(pVCpu) \
954	AssertMsg( VMCPU_IS_EMT(pVCpu) \
955	\|\| pVCpu->CTX_SUFF(pVM)->enmVMState == VMSTATE_GURU_MEDITATION \
956	\|\| pVCpu->CTX_SUFF(pVM)->enmVMState == VMSTATE_GURU_MEDITATION_LS, \
957	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd idCpu=%#x\n", \
958	RTThreadNativeSelf(), (pVCpu)->hNativeThread, (pVCpu)->idCpu))
959	#endif
960
961	/** @def VMCPU_ASSERT_EMT_OR_NOT_RUNNING
962	* Asserts that the current thread IS the emulation thread (EMT) of the
963	* specified virtual CPU or the VM is not running.
964	*/
965	#if defined(IN_RC) \|\| defined(IN_RING0)
966	# define VMCPU_ASSERT_EMT_OR_NOT_RUNNING(pVCpu) \
967	Assert( VMCPU_IS_EMT(pVCpu) \
968	\|\| !VM_IS_RUNNING_FOR_ASSERTIONS_ONLY((pVCpu)->CTX_SUFF(pVM)) )
969	#else
970	# define VMCPU_ASSERT_EMT_OR_NOT_RUNNING(pVCpu) \
971	AssertMsg( VMCPU_IS_EMT(pVCpu) \
972	\|\| !VM_IS_RUNNING_FOR_ASSERTIONS_ONLY((pVCpu)->CTX_SUFF(pVM)), \
973	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd idCpu=%#x\n", \
974	RTThreadNativeSelf(), (pVCpu)->hNativeThread, (pVCpu)->idCpu))
975	#endif
976
977	/** @def VMSTATE_IS_RUNNING
978	* Checks if the given state indicates a running VM.
979	*/
980	#define VMSTATE_IS_RUNNING(a_enmVMState) \
981	( (enmVMState) == VMSTATE_RUNNING \
982	\|\| (enmVMState) == VMSTATE_RUNNING_LS \
983	\|\| (enmVMState) == VMSTATE_RUNNING_FT )
984
985	/** @def VM_IS_RUNNING_FOR_ASSERTIONS_ONLY
986	* Checks if the VM is running.
987	* @note This is only for pure debug assertions. No AssertReturn or similar!
988	* @sa VMSTATE_IS_RUNNING
989	*/
990	#define VM_IS_RUNNING_FOR_ASSERTIONS_ONLY(pVM) \
991	( (pVM)->enmVMState == VMSTATE_RUNNING \
992	\|\| (pVM)->enmVMState == VMSTATE_RUNNING_LS \
993	\|\| (pVM)->enmVMState == VMSTATE_RUNNING_FT )
994
995	/** @def VM_ASSERT_IS_NOT_RUNNING
996	* Asserts that the VM is not running.
997	*/
998	#if defined(IN_RC) \|\| defined(IN_RING0)
999	#define VM_ASSERT_IS_NOT_RUNNING(pVM) Assert(!VM_IS_RUNNING_FOR_ASSERTIONS_ONLY(pVM))
1000	#else
1001	#define VM_ASSERT_IS_NOT_RUNNING(pVM) AssertMsg(!VM_IS_RUNNING_FOR_ASSERTIONS_ONLY(pVM), \
1002	("VM is running. enmVMState=%d\n", (pVM)->enmVMState))
1003	#endif
1004
1005	/** @def VM_ASSERT_EMT0
1006	* Asserts that the current thread IS emulation thread \#0 (EMT0).
1007	*/
1008	#define VM_ASSERT_EMT0(pVM) VMCPU_ASSERT_EMT(&(pVM)->aCpus[0])
1009
1010	/** @def VM_ASSERT_EMT0_RETURN
1011	* Asserts that the current thread IS emulation thread \#0 (EMT0) and returns if
1012	* it isn't.
1013	*/
1014	#define VM_ASSERT_EMT0_RETURN(pVM, rc) VMCPU_ASSERT_EMT_RETURN(&(pVM)->aCpus[0], (rc))
1015
1016
1017	/**
1018	* Asserts that the current thread is NOT the emulation thread.
1019	*/
1020	#define VM_ASSERT_OTHER_THREAD(pVM) \
1021	AssertMsg(!VM_IS_EMT(pVM), ("Not other thread!!\n"))
1022
1023
1024	/** @def VM_ASSERT_STATE
1025	* Asserts a certain VM state.
1026	*/
1027	#define VM_ASSERT_STATE(pVM, _enmState) \
1028	AssertMsg((pVM)->enmVMState == (_enmState), \
1029	("state %s, expected %s\n", VMGetStateName((pVM)->enmVMState), VMGetStateName(_enmState)))
1030
1031	/** @def VM_ASSERT_STATE_RETURN
1032	* Asserts a certain VM state and returns if it doesn't match.
1033	*/
1034	#define VM_ASSERT_STATE_RETURN(pVM, _enmState, rc) \
1035	AssertMsgReturn((pVM)->enmVMState == (_enmState), \
1036	("state %s, expected %s\n", VMGetStateName((pVM)->enmVMState), VMGetStateName(_enmState)), \
1037	(rc))
1038
1039	/** @def VM_IS_VALID_EXT
1040	* Asserts a the VM handle is valid for external access, i.e. not being destroy
1041	* or terminated. */
1042	#define VM_IS_VALID_EXT(pVM) \
1043	( RT_VALID_ALIGNED_PTR(pVM, PAGE_SIZE) \
1044	&& ( (unsigned)(pVM)->enmVMState < (unsigned)VMSTATE_DESTROYING \
1045	\|\| ( (unsigned)(pVM)->enmVMState == (unsigned)VMSTATE_DESTROYING \
1046	&& VM_IS_EMT(pVM))) )
1047
1048	/** @def VM_ASSERT_VALID_EXT_RETURN
1049	* Asserts a the VM handle is valid for external access, i.e. not being
1050	* destroy or terminated.
1051	*/
1052	#define VM_ASSERT_VALID_EXT_RETURN(pVM, rc) \
1053	AssertMsgReturn(VM_IS_VALID_EXT(pVM), \
1054	("pVM=%p state %s\n", (pVM), RT_VALID_ALIGNED_PTR(pVM, PAGE_SIZE) \
1055	? VMGetStateName(pVM->enmVMState) : ""), \
1056	(rc))
1057
1058	/** @def VMCPU_ASSERT_VALID_EXT_RETURN
1059	* Asserts a the VMCPU handle is valid for external access, i.e. not being
1060	* destroy or terminated.
1061	*/
1062	#define VMCPU_ASSERT_VALID_EXT_RETURN(pVCpu, rc) \
1063	AssertMsgReturn( RT_VALID_ALIGNED_PTR(pVCpu, 64) \
1064	&& RT_VALID_ALIGNED_PTR((pVCpu)->CTX_SUFF(pVM), PAGE_SIZE) \
1065	&& (unsigned)(pVCpu)->CTX_SUFF(pVM)->enmVMState < (unsigned)VMSTATE_DESTROYING, \
1066	("pVCpu=%p pVM=%p state %s\n", (pVCpu), RT_VALID_ALIGNED_PTR(pVCpu, 64) ? (pVCpu)->CTX_SUFF(pVM) : NULL, \
1067	RT_VALID_ALIGNED_PTR(pVCpu, 64) && RT_VALID_ALIGNED_PTR((pVCpu)->CTX_SUFF(pVM), PAGE_SIZE) \
1068	? VMGetStateName((pVCpu)->pVMR3->enmVMState) : ""), \
1069	(rc))
1070
1071	#endif /* !VBOX_FOR_DTRACE_LIB */
1072
1073
1074	/**
1075	* Helper that HM and NEM uses for safely modifying VM::bMainExecutionEngine.
1076	*
1077	* ONLY HM and NEM MAY USE THIS!
1078	*
1079	* @param a_pVM The cross context VM structure.
1080	* @param a_bValue The new value.
1081	* @internal
1082	*/
1083	#define VM_SET_MAIN_EXECUTION_ENGINE(a_pVM, a_bValue) \
1084	do { \
1085	const_cast<uint8_t >(&(a_pVM)->bMainExecutionEngine) = (a_bValue); \
1086	ASMCompilerBarrier(); /* just to be on the safe side */ \
1087	} while (0)
1088
1089	/**
1090	* Checks whether raw-mode is used.
1091	*
1092	* @retval true if either is used.
1093	* @retval false if software virtualization (raw-mode) is used.
1094	*
1095	* @param a_pVM The cross context VM structure.
1096	* @sa VM_IS_HM_OR_NEM_ENABLED, VM_IS_HM_ENABLED, VM_IS_NEM_ENABLED.
1097	* @internal
1098	*/
1099	#ifdef VBOX_WITH_RAW_MODE
1100	# define VM_IS_RAW_MODE_ENABLED(a_pVM) ((a_pVM)->bMainExecutionEngine == VM_EXEC_ENGINE_RAW_MODE)
1101	#else
1102	# define VM_IS_RAW_MODE_ENABLED(a_pVM) (false)
1103	#endif
1104
1105	/**
1106	* Checks whether HM (VT-x/AMD-V) or NEM is being used by this VM.
1107	*
1108	* @retval true if either is used.
1109	* @retval false if software virtualization (raw-mode) is used.
1110	*
1111	* @param a_pVM The cross context VM structure.
1112	* @sa VM_IS_RAW_MODE_ENABLED, VM_IS_HM_ENABLED, VM_IS_NEM_ENABLED.
1113	* @internal
1114	*/
1115	#define VM_IS_HM_OR_NEM_ENABLED(a_pVM) ((a_pVM)->bMainExecutionEngine != VM_EXEC_ENGINE_RAW_MODE)
1116
1117	/**
1118	* Checks whether HM is being used by this VM.
1119	*
1120	* @retval true if HM (VT-x/AMD-v) is used.
1121	* @retval false if not.
1122	*
1123	* @param a_pVM The cross context VM structure.
1124	* @sa VM_IS_NEM_ENABLED, VM_IS_RAW_MODE_ENABLED, VM_IS_HM_OR_NEM_ENABLED.
1125	* @internal
1126	*/
1127	#define VM_IS_HM_ENABLED(a_pVM) ((a_pVM)->bMainExecutionEngine == VM_EXEC_ENGINE_HW_VIRT)
1128
1129	/**
1130	* Checks whether NEM is being used by this VM.
1131	*
1132	* @retval true if a native hypervisor API is used.
1133	* @retval false if not.
1134	*
1135	* @param a_pVM The cross context VM structure.
1136	* @sa VM_IS_HM_ENABLED, VM_IS_RAW_MODE_ENABLED, VM_IS_HM_OR_NEM_ENABLED.
1137	* @internal
1138	*/
1139	#define VM_IS_NEM_ENABLED(a_pVM) ((a_pVM)->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API)
1140
1141
1142	/**
1143	* The cross context VM structure.
1144	*
1145	* It contains all the VM data which have to be available in all contexts.
1146	* Even if it contains all the data the idea is to use APIs not to modify all
1147	* the members all around the place. Therefore we make use of unions to hide
1148	* everything which isn't local to the current source module. This means we'll
1149	* have to pay a little bit of attention when adding new members to structures
1150	* in the unions and make sure to keep the padding sizes up to date.
1151	*
1152	* Run 'kmk run-struct-tests' (from src/VBox/VMM if you like) after updating!
1153	*/
1154	typedef struct VM
1155	{
1156	/** The state of the VM.
1157	* This field is read only to everyone except the VM and EM. */
1158	VMSTATE volatile enmVMState;
1159	/** Forced action flags.
1160	* See the VM_FF_* \#defines. Updated atomically.
1161	*/
1162	volatile uint32_t fGlobalForcedActions;
1163	/** Pointer to the array of page descriptors for the VM structure allocation. */
1164	R3PTRTYPE(PSUPPAGE) paVMPagesR3;
1165	/** Session handle. For use when calling SUPR0 APIs. */
1166	PSUPDRVSESSION pSession;
1167	/** Pointer to the ring-3 VM structure. */
1168	PUVM pUVM;
1169	/** Ring-3 Host Context VM Pointer. */
1170	R3PTRTYPE(struct VM *) pVMR3;
1171	/** Ring-0 Host Context VM Pointer. */
1172	R0PTRTYPE(struct VM *) pVMR0;
1173	/** Raw-mode Context VM Pointer. */
1174	RCPTRTYPE(struct VM *) pVMRC;
1175
1176	/** The GVM VM handle. Only the GVM should modify this field. */
1177	uint32_t hSelf;
1178	/** Number of virtual CPUs. */
1179	uint32_t cCpus;
1180	/** CPU excution cap (1-100) */
1181	uint32_t uCpuExecutionCap;
1182
1183	/** Size of the VM structure including the VMCPU array. */
1184	uint32_t cbSelf;
1185
1186	/** Offset to the VMCPU array starting from beginning of this structure. */
1187	uint32_t offVMCPU;
1188
1189	/**
1190	* VMMSwitcher assembly entry point returning to host context.
1191	*
1192	* Depending on how the host handles the rc status given in @a eax, this may
1193	* return and let the caller resume whatever it was doing prior to the call.
1194	*
1195	*
1196	* @param eax The return code, register.
1197	* @remark Assume interrupts disabled.
1198	* @remark This method pointer lives here because TRPM needs it.
1199	*/
1200	RTRCPTR pfnVMMRCToHostAsm/(int32_t eax)/;
1201
1202	/**
1203	* VMMSwitcher assembly entry point returning to host context without saving the
1204	* raw-mode context (hyper) registers.
1205	*
1206	* Unlike pfnVMMRC2HCAsm, this will not return to the caller. Instead it
1207	* expects the caller to save a RC context in CPUM where one might return if the
1208	* return code indicate that this is possible.
1209	*
1210	* This method pointer lives here because TRPM needs it.
1211	*
1212	* @param eax The return code, register.
1213	* @remark Assume interrupts disabled.
1214	* @remark This method pointer lives here because TRPM needs it.
1215	*/
1216	RTRCPTR pfnVMMRCToHostAsmNoReturn/(int32_t eax)/;
1217
1218	/** @name Various items that are frequently accessed.
1219	* @{ */
1220	/** The main execution engine, VM_EXEC_ENGINE_XXX.
1221	* This is set early during vmR3InitRing3 by HM or NEM. */
1222	uint8_t const bMainExecutionEngine;
1223
1224	/** Whether to recompile user mode code or run it raw/hm/nem.
1225	* In non-raw-mode both fRecompileUser and fRecompileSupervisor must be set
1226	* to recompiler stuff. */
1227	bool fRecompileUser;
1228	/** Whether to recompile supervisor mode code or run it raw/hm/nem.
1229	* In non-raw-mode both fRecompileUser and fRecompileSupervisor must be set
1230	* to recompiler stuff. */
1231	bool fRecompileSupervisor;
1232	/** Whether raw mode supports ring-1 code or not.
1233	* This will be cleared when not in raw-mode. */
1234	bool fRawRing1Enabled;
1235	/** PATM enabled flag.
1236	* This is placed here for performance reasons.
1237	* This will be cleared when not in raw-mode. */
1238	bool fPATMEnabled;
1239	/** CSAM enabled flag.
1240	* This is placed here for performance reasons.
1241	* This will be cleared when not in raw-mode. */
1242	bool fCSAMEnabled;
1243
1244	/** Hardware VM support is available and enabled.
1245	* Determined very early during init.
1246	* This is placed here for performance reasons.
1247	* @todo obsoleted by bMainExecutionEngine, eliminate. */
1248	bool fHMEnabled;
1249	/** Hardware VM support requires a minimal raw-mode context.
1250	* This is never set on 64-bit hosts, only 32-bit hosts requires it. */
1251	bool fHMNeedRawModeCtx;
1252
1253	/** Set when this VM is the master FT node.
1254	* @todo This doesn't need to be here, FTM should store it in it's own
1255	* structures instead. */
1256	bool fFaultTolerantMaster;
1257	/** Large page enabled flag.
1258	* @todo This doesn't need to be here, PGM should store it in it's own
1259	* structures instead. */
1260	bool fUseLargePages;
1261	/** @} */
1262
1263	/** Alignment padding. */
1264	uint8_t uPadding1[2];
1265
1266	/** @name Debugging
1267	* @{ */
1268	/** Raw-mode Context VM Pointer. */
1269	RCPTRTYPE(RTTRACEBUF) hTraceBufRC;
1270	/** Ring-3 Host Context VM Pointer. */
1271	R3PTRTYPE(RTTRACEBUF) hTraceBufR3;
1272	/** Ring-0 Host Context VM Pointer. */
1273	R0PTRTYPE(RTTRACEBUF) hTraceBufR0;
1274	/** @} */
1275
1276	#if HC_ARCH_BITS == 32
1277	/** Alignment padding. */
1278	uint32_t uPadding2;
1279	#endif
1280
1281	/** @name Switcher statistics (remove)
1282	* @{ */
1283	/** Profiling the total time from Qemu to GC. */
1284	STAMPROFILEADV StatTotalQemuToGC;
1285	/** Profiling the total time from GC to Qemu. */
1286	STAMPROFILEADV StatTotalGCToQemu;
1287	/** Profiling the total time spent in GC. */
1288	STAMPROFILEADV StatTotalInGC;
1289	/** Profiling the total time spent not in Qemu. */
1290	STAMPROFILEADV StatTotalInQemu;
1291	/** Profiling the VMMSwitcher code for going to GC. */
1292	STAMPROFILEADV StatSwitcherToGC;
1293	/** Profiling the VMMSwitcher code for going to HC. */
1294	STAMPROFILEADV StatSwitcherToHC;
1295	STAMPROFILEADV StatSwitcherSaveRegs;
1296	STAMPROFILEADV StatSwitcherSysEnter;
1297	STAMPROFILEADV StatSwitcherDebug;
1298	STAMPROFILEADV StatSwitcherCR0;
1299	STAMPROFILEADV StatSwitcherCR4;
1300	STAMPROFILEADV StatSwitcherJmpCR3;
1301	STAMPROFILEADV StatSwitcherRstrRegs;
1302	STAMPROFILEADV StatSwitcherLgdt;
1303	STAMPROFILEADV StatSwitcherLidt;
1304	STAMPROFILEADV StatSwitcherLldt;
1305	STAMPROFILEADV StatSwitcherTSS;
1306	/** @} */
1307
1308	/** Padding - the unions must be aligned on a 64 bytes boundary and the unions
1309	* must start at the same offset on both 64-bit and 32-bit hosts. */
1310	uint8_t abAlignment3[(HC_ARCH_BITS == 32 ? 24 : 0) + 40];
1311
1312	/** CPUM part. */
1313	union
1314	{
1315	#ifdef ___CPUMInternal_h
1316	struct CPUM s;
1317	#endif
1318	#ifdef ___VBox_vmm_cpum_h
1319	/** Read only info exposed about the host and guest CPUs. */
1320	struct
1321	{
1322	/** Padding for hidden fields. */
1323	uint8_t abHidden0[64];
1324	/** Host CPU feature information. */
1325	CPUMFEATURES HostFeatures;
1326	/** Guest CPU feature information. */
1327	CPUMFEATURES GuestFeatures;
1328	} const ro;
1329	#endif
1330	uint8_t padding[1536]; /* multiple of 64 */
1331	} cpum;
1332
1333	/** VMM part. */
1334	union
1335	{
1336	#ifdef ___VMMInternal_h
1337	struct VMM s;
1338	#endif
1339	uint8_t padding[1600]; /* multiple of 64 */
1340	} vmm;
1341
1342	/** PGM part. */
1343	union
1344	{
1345	#ifdef ___PGMInternal_h
1346	struct PGM s;
1347	#endif
1348	uint8_t padding[40962+6080]; / multiple of 64 */
1349	} pgm;
1350
1351	/** HM part. */
1352	union
1353	{
1354	#ifdef ___HMInternal_h
1355	struct HM s;
1356	#endif
1357	uint8_t padding[5440]; /* multiple of 64 */
1358	} hm;
1359
1360	/** TRPM part. */
1361	union
1362	{
1363	#ifdef ___TRPMInternal_h
1364	struct TRPM s;
1365	#endif
1366	uint8_t padding[5248]; /* multiple of 64 */
1367	} trpm;
1368
1369	/** SELM part. */
1370	union
1371	{
1372	#ifdef ___SELMInternal_h
1373	struct SELM s;
1374	#endif
1375	uint8_t padding[768]; /* multiple of 64 */
1376	} selm;
1377
1378	/** MM part. */
1379	union
1380	{
1381	#ifdef ___MMInternal_h
1382	struct MM s;
1383	#endif
1384	uint8_t padding[192]; /* multiple of 64 */
1385	} mm;
1386
1387	/** PDM part. */
1388	union
1389	{
1390	#ifdef ___PDMInternal_h
1391	struct PDM s;
1392	#endif
1393	uint8_t padding[1920]; /* multiple of 64 */
1394	} pdm;
1395
1396	/** IOM part. */
1397	union
1398	{
1399	#ifdef ___IOMInternal_h
1400	struct IOM s;
1401	#endif
1402	uint8_t padding[896]; /* multiple of 64 */
1403	} iom;
1404
1405	/** EM part. */
1406	union
1407	{
1408	#ifdef ___EMInternal_h
1409	struct EM s;
1410	#endif
1411	uint8_t padding[256]; /* multiple of 64 */
1412	} em;
1413
1414	/** NEM part. */
1415	union
1416	{
1417	#ifdef ___NEMInternal_h
1418	struct NEM s;
1419	#endif
1420	uint8_t padding[128]; /* multiple of 64 */
1421	} nem;
1422
1423	/** TM part. */
1424	union
1425	{
1426	#ifdef ___TMInternal_h
1427	struct TM s;
1428	#endif
1429	uint8_t padding[2496]; /* multiple of 64 */
1430	} tm;
1431
1432	/** DBGF part. */
1433	union
1434	{
1435	#ifdef ___DBGFInternal_h
1436	struct DBGF s;
1437	#endif
1438	#ifdef ___VBox_vmm_dbgf_h
1439	/** Read only info exposed about interrupt breakpoints and selected events. */
1440	struct
1441	{
1442	/** Bitmap of enabled hardware interrupt breakpoints. */
1443	uint32_t bmHardIntBreakpoints[256 / 32];
1444	/** Bitmap of enabled software interrupt breakpoints. */
1445	uint32_t bmSoftIntBreakpoints[256 / 32];
1446	/** Bitmap of selected events.
1447	* This includes non-selectable events too for simplicity, we maintain the
1448	* state for some of these, as it may come in handy. */
1449	uint64_t bmSelectedEvents[(DBGFEVENT_END + 63) / 64];
1450	/** Enabled hardware interrupt breakpoints. */
1451	uint32_t cHardIntBreakpoints;
1452	/** Enabled software interrupt breakpoints. */
1453	uint32_t cSoftIntBreakpoints;
1454	/** The number of selected events. */
1455	uint32_t cSelectedEvents;
1456	/** The number of enabled hardware breakpoints. */
1457	uint8_t cEnabledHwBreakpoints;
1458	/** The number of enabled hardware I/O breakpoints. */
1459	uint8_t cEnabledHwIoBreakpoints;
1460	/** The number of enabled INT3 breakpoints. */
1461	uint8_t cEnabledInt3Breakpoints;
1462	uint8_t abPadding[1]; /*< Unused padding space up for grabs. /
1463	} const ro;
1464	#endif
1465	uint8_t padding[2432]; /* multiple of 64 */
1466	} dbgf;
1467
1468	/** SSM part. */
1469	union
1470	{
1471	#ifdef ___SSMInternal_h
1472	struct SSM s;
1473	#endif
1474	uint8_t padding[128]; /* multiple of 64 */
1475	} ssm;
1476
1477	/** FTM part. */
1478	union
1479	{
1480	#ifdef ___FTMInternal_h
1481	struct FTM s;
1482	#endif
1483	uint8_t padding[512]; /* multiple of 64 */
1484	} ftm;
1485
1486	#ifdef VBOX_WITH_RAW_MODE
1487	/** PATM part. */
1488	union
1489	{
1490	# ifdef ___PATMInternal_h
1491	struct PATM s;
1492	# endif
1493	uint8_t padding[768]; /* multiple of 64 */
1494	} patm;
1495
1496	/** CSAM part. */
1497	union
1498	{
1499	# ifdef ___CSAMInternal_h
1500	struct CSAM s;
1501	# endif
1502	uint8_t padding[1088]; /* multiple of 64 */
1503	} csam;
1504	#endif
1505
1506	#ifdef VBOX_WITH_REM
1507	/** REM part. */
1508	union
1509	{
1510	# ifdef ___REMInternal_h
1511	struct REM s;
1512	# endif
1513	uint8_t padding[0x11100]; /* multiple of 64 */
1514	} rem;
1515	#endif
1516
1517	union
1518	{
1519	#ifdef ___GIMInternal_h
1520	struct GIM s;
1521	#endif
1522	uint8_t padding[448]; /* multiple of 64 */
1523	} gim;
1524
1525	union
1526	{
1527	#ifdef ___APICInternal_h
1528	struct APIC s;
1529	#endif
1530	uint8_t padding[128]; /* multiple of 8 */
1531	} apic;
1532
1533	/* ---- begin small stuff ---- */
1534
1535	/** VM part. */
1536	union
1537	{
1538	#ifdef ___VMInternal_h
1539	struct VMINT s;
1540	#endif
1541	uint8_t padding[32]; /* multiple of 8 */
1542	} vm;
1543
1544	/** CFGM part. */
1545	union
1546	{
1547	#ifdef ___CFGMInternal_h
1548	struct CFGM s;
1549	#endif
1550	uint8_t padding[8]; /* multiple of 8 */
1551	} cfgm;
1552
1553	/** Padding for aligning the cpu array on a page boundary. */
1554	#if defined(VBOX_WITH_REM) && defined(VBOX_WITH_RAW_MODE)
1555	uint8_t abAlignment2[3670];
1556	#elif defined(VBOX_WITH_REM) && !defined(VBOX_WITH_RAW_MODE)
1557	uint8_t abAlignment2[1430];
1558	#elif !defined(VBOX_WITH_REM) && defined(VBOX_WITH_RAW_MODE)
1559	uint8_t abAlignment2[3926];
1560	#else
1561	uint8_t abAlignment2[1686];
1562	#endif
1563
1564	/* ---- end small stuff ---- */
1565
1566	/** VMCPU array for the configured number of virtual CPUs.
1567	* Must be aligned on a page boundary for TLB hit reasons as well as
1568	* alignment of VMCPU members. */
1569	VMCPU aCpus[1];
1570	} VM;
1571
1572
1573	#ifdef IN_RC
1574	RT_C_DECLS_BEGIN
1575
1576	/** The VM structure.
1577	* This is imported from the VMMRCBuiltin module, i.e. it's a one of those magic
1578	* globals which we should avoid using.
1579	*/
1580	extern DECLIMPORT(VM) g_VM;
1581
1582	RT_C_DECLS_END
1583	#endif
1584
1585	/** @} */
1586
1587	#endif
1588

Note: See TracBrowser for help on using the repository browser.

source: vbox/trunk/include/VBox/vmm/vm.h@ 75200

Download in other formats: