vm.h@ 75620

Last change on this file since 75620 was 75620, checked in by vboxsync, 6 years ago
VMM: Nested VMX: bugref:9180 APIC-write emulation bits.
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1	/** @file
2	* VM - The Virtual Machine, data.
3	*/
4
5	/*
6	* Copyright (C) 2006-2017 Oracle Corporation
7	*
8	* This file is part of VirtualBox Open Source Edition (OSE), as
9	* available from http://www.virtualbox.org. This file is free software;
10	* you can redistribute it and/or modify it under the terms of the GNU
11	* General Public License (GPL) as published by the Free Software
12	* Foundation, in version 2 as it comes in the "COPYING" file of the
13	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15	*
16	* The contents of this file may alternatively be used under the terms
17	* of the Common Development and Distribution License Version 1.0
18	* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19	* VirtualBox OSE distribution, in which case the provisions of the
20	* CDDL are applicable instead of those of the GPL.
21	*
22	* You may elect to license modified versions of this file under the
23	* terms and conditions of either the GPL or the CDDL or both.
24	*/
25
26	#ifndef ___VBox_vmm_vm_h
27	#define ___VBox_vmm_vm_h
28
29	#ifndef VBOX_FOR_DTRACE_LIB
30	# include <iprt/param.h>
31	# include <VBox/types.h>
32	# include <VBox/vmm/cpum.h>
33	# include <VBox/vmm/stam.h>
34	# include <VBox/vmm/vmapi.h>
35	# include <VBox/vmm/vmm.h>
36	# include <VBox/sup.h>
37	#else
38	# pragma D depends_on library vbox-types.d
39	# pragma D depends_on library CPUMInternal.d
40	# define ___CPUMInternal_h
41	#endif
42
43
44
45	/** @defgroup grp_vm The Virtual Machine
46	* @ingroup grp_vmm
47	* @{
48	*/
49
50	/**
51	* The state of a Virtual CPU.
52	*
53	* The basic state indicated here is whether the CPU has been started or not. In
54	* addition, there are sub-states when started for assisting scheduling (GVMM
55	* mostly).
56	*
57	* The transition out of the STOPPED state is done by a vmR3PowerOn.
58	* The transition back to the STOPPED state is done by vmR3PowerOff.
59	*
60	* (Alternatively we could let vmR3PowerOn start CPU 0 only and let the SPIP
61	* handling switch on the other CPUs. Then vmR3Reset would stop all but CPU 0.)
62	*/
63	typedef enum VMCPUSTATE
64	{
65	/** The customary invalid zero. */
66	VMCPUSTATE_INVALID = 0,
67
68	/** Virtual CPU has not yet been started. */
69	VMCPUSTATE_STOPPED,
70
71	/** CPU started. */
72	VMCPUSTATE_STARTED,
73	/** CPU started in HM context. */
74	VMCPUSTATE_STARTED_HM,
75	/** Executing guest code and can be poked (RC or STI bits of HM). */
76	VMCPUSTATE_STARTED_EXEC,
77	/** Executing guest code in the recompiler. */
78	VMCPUSTATE_STARTED_EXEC_REM,
79	/** Executing guest code using NEM. */
80	VMCPUSTATE_STARTED_EXEC_NEM,
81	VMCPUSTATE_STARTED_EXEC_NEM_WAIT,
82	VMCPUSTATE_STARTED_EXEC_NEM_CANCELED,
83	/** Halted. */
84	VMCPUSTATE_STARTED_HALTED,
85
86	/** The end of valid virtual CPU states. */
87	VMCPUSTATE_END,
88
89	/** Ensure 32-bit type. */
90	VMCPUSTATE_32BIT_HACK = 0x7fffffff
91	} VMCPUSTATE;
92
93	/** Enables 64-bit FFs. */
94	#define VMCPU_WITH_64_BIT_FFS
95
96
97	/**
98	* The cross context virtual CPU structure.
99	*
100	* Run 'kmk run-struct-tests' (from src/VBox/VMM if you like) after updating!
101	*/
102	typedef struct VMCPU
103	{
104	/** @name Volatile per-cpu data.
105	* @{ */
106	/** Per CPU forced action.
107	* See the VMCPU_FF_* \#defines. Updated atomically. */
108	#ifdef VMCPU_WITH_64_BIT_FFS
109	uint64_t volatile fLocalForcedActions;
110	#else
111	uint32_t volatile fLocalForcedActions;
112	uint32_t fForLocalForcedActionsExpansion;
113	#endif
114	/** The CPU state. */
115	VMCPUSTATE volatile enmState;
116
117	/** Which host CPU ID is this EMT running on.
118	* Only valid when in RC or HMR0 with scheduling disabled. */
119	RTCPUID volatile idHostCpu;
120	/** The CPU set index corresponding to idHostCpu, UINT32_MAX if not valid.
121	* @remarks Best to make sure iHostCpuSet shares cache line with idHostCpu! */
122	uint32_t volatile iHostCpuSet;
123	/** Padding up to 64 bytes. */
124	uint8_t abAlignment0[64 - 20];
125	/** @} */
126
127	/** IEM part.
128	* @remarks This comes first as it allows the use of 8-bit immediates for the
129	* first 64 bytes of the structure, reducing code size a wee bit. */
130	#ifdef ___IEMInternal_h /* For PDB hacking. */
131	union VMCPUUNIONIEMFULL
132	#else
133	union VMCPUUNIONIEMSTUB
134	#endif
135	{
136	#ifdef ___IEMInternal_h
137	struct IEMCPU s;
138	#endif
139	uint8_t padding[18496]; /* multiple of 64 */
140	} iem;
141
142	/** @name Static per-cpu data.
143	* (Putting this after IEM, hoping that it's less frequently used than it.)
144	* @{ */
145	/** The CPU ID.
146	* This is the index into the VM::aCpu array. */
147	VMCPUID idCpu;
148	/** Raw-mode Context VM Pointer. */
149	PVMRC pVMRC;
150	/** Ring-3 Host Context VM Pointer. */
151	PVMR3 pVMR3;
152	/** Ring-0 Host Context VM Pointer. */
153	PVMR0 pVMR0;
154	/** Pointer to the ring-3 UVMCPU structure. */
155	PUVMCPU pUVCpu;
156	/** The native thread handle. */
157	RTNATIVETHREAD hNativeThread;
158	/** The native R0 thread handle. (different from the R3 handle!) */
159	RTNATIVETHREAD hNativeThreadR0;
160	/** Align the structures below bit on a 64-byte boundary and make sure it starts
161	* at the same offset in both 64-bit and 32-bit builds.
162	*
163	* @remarks The alignments of the members that are larger than 48 bytes should be
164	* 64-byte for cache line reasons. structs containing small amounts of
165	* data could be lumped together at the end with a < 64 byte padding
166	* following it (to grow into and align the struct size).
167	*/
168	uint8_t abAlignment1[64 - 4 - 4 - 5 * (HC_ARCH_BITS == 64 ? 8 : 4)];
169	/** @} */
170
171	/** HM part. */
172	union VMCPUUNIONHM
173	{
174	#ifdef ___HMInternal_h
175	struct HMCPU s;
176	#endif
177	uint8_t padding[5888]; /* multiple of 64 */
178	} hm;
179
180	/** NEM part. */
181	union VMCPUUNIONNEM
182	{
183	#ifdef ___NEMInternal_h
184	struct NEMCPU s;
185	#endif
186	uint8_t padding[512]; /* multiple of 64 */
187	} nem;
188
189	/** TRPM part. */
190	union VMCPUUNIONTRPM
191	{
192	#ifdef ___TRPMInternal_h
193	struct TRPMCPU s;
194	#endif
195	uint8_t padding[128]; /* multiple of 64 */
196	} trpm;
197
198	/** TM part. */
199	union VMCPUUNIONTM
200	{
201	#ifdef ___TMInternal_h
202	struct TMCPU s;
203	#endif
204	uint8_t padding[384]; /* multiple of 64 */
205	} tm;
206
207	/** VMM part. */
208	union VMCPUUNIONVMM
209	{
210	#ifdef ___VMMInternal_h
211	struct VMMCPU s;
212	#endif
213	uint8_t padding[768]; /* multiple of 64 */
214	} vmm;
215
216	/** PDM part. */
217	union VMCPUUNIONPDM
218	{
219	#ifdef ___PDMInternal_h
220	struct PDMCPU s;
221	#endif
222	uint8_t padding[256]; /* multiple of 64 */
223	} pdm;
224
225	/** IOM part. */
226	union VMCPUUNIONIOM
227	{
228	#ifdef ___IOMInternal_h
229	struct IOMCPU s;
230	#endif
231	uint8_t padding[512]; /* multiple of 64 */
232	} iom;
233
234	/** DBGF part.
235	* @todo Combine this with other tiny structures. */
236	union VMCPUUNIONDBGF
237	{
238	#ifdef ___DBGFInternal_h
239	struct DBGFCPU s;
240	#endif
241	uint8_t padding[256]; /* multiple of 64 */
242	} dbgf;
243
244	/** GIM part. */
245	union VMCPUUNIONGIM
246	{
247	#ifdef ___GIMInternal_h
248	struct GIMCPU s;
249	#endif
250	uint8_t padding[512]; /* multiple of 64 */
251	} gim;
252
253	/** APIC part. */
254	union VMCPUUNIONAPIC
255	{
256	#ifdef ___APICInternal_h
257	struct APICCPU s;
258	#endif
259	uint8_t padding[1792]; /* multiple of 64 */
260	} apic;
261
262	/*
263	* Some less frequently used global members that doesn't need to take up
264	* precious space at the head of the structure.
265	*/
266
267	/** Trace groups enable flags. */
268	uint32_t fTraceGroups; /* 64 / 44 */
269	/** State data for use by ad hoc profiling. */
270	uint32_t uAdHoc;
271	/** Profiling samples for use by ad hoc profiling. */
272	STAMPROFILEADV aStatAdHoc[8]; /* size: 408 = 320 /
273
274	/** Align the following members on page boundary. */
275	uint8_t abAlignment2[2808];
276
277	/** PGM part. */
278	union VMCPUUNIONPGM
279	{
280	#ifdef ___PGMInternal_h
281	struct PGMCPU s;
282	#endif
283	uint8_t padding[4096]; /* multiple of 4096 */
284	} pgm;
285
286	/** CPUM part. */
287	union VMCPUUNIONCPUM
288	{
289	#ifdef ___CPUMInternal_h
290	struct CPUMCPU s;
291	#endif
292	#ifdef VMCPU_INCL_CPUM_GST_CTX
293	/** The guest CPUM context for direct use by execution engines.
294	* This is not for general consumption, but for HM, REM, IEM, and maybe a few
295	* others. The rest will use the function based CPUM API. */
296	CPUMCTX GstCtx;
297	#endif
298	uint8_t padding[4096]; /* multiple of 4096 */
299	} cpum;
300
301	/** EM part. */
302	union VMCPUUNIONEM
303	{
304	#ifdef ___EMInternal_h
305	struct EMCPU s;
306	#endif
307	uint8_t padding[40960]; /* multiple of 4096 */
308	} em;
309	} VMCPU;
310
311
312	#ifndef VBOX_FOR_DTRACE_LIB
313
314	/** @name Operations on VMCPU::enmState
315	* @{ */
316	/** Gets the VMCPU state. */
317	#define VMCPU_GET_STATE(pVCpu) ( (pVCpu)->enmState )
318	/** Sets the VMCPU state. */
319	#define VMCPU_SET_STATE(pVCpu, enmNewState) \
320	ASMAtomicWriteU32((uint32_t volatile *)&(pVCpu)->enmState, (enmNewState))
321	/** Cmpares and sets the VMCPU state. */
322	#define VMCPU_CMPXCHG_STATE(pVCpu, enmNewState, enmOldState) \
323	ASMAtomicCmpXchgU32((uint32_t volatile *)&(pVCpu)->enmState, (enmNewState), (enmOldState))
324	/** Checks the VMCPU state. */
325	#ifdef VBOX_STRICT
326	# define VMCPU_ASSERT_STATE(pVCpu, enmExpectedState) \
327	do { \
328	VMCPUSTATE enmState = VMCPU_GET_STATE(pVCpu); \
329	AssertMsg(enmState == (enmExpectedState), \
330	("enmState=%d enmExpectedState=%d idCpu=%u\n", \
331	enmState, enmExpectedState, (pVCpu)->idCpu)); \
332	} while (0)
333	#else
334	# define VMCPU_ASSERT_STATE(pVCpu, enmExpectedState) do { } while (0)
335	#endif
336	/** Tests if the state means that the CPU is started. */
337	#define VMCPUSTATE_IS_STARTED(enmState) ( (enmState) > VMCPUSTATE_STOPPED )
338	/** Tests if the state means that the CPU is stopped. */
339	#define VMCPUSTATE_IS_STOPPED(enmState) ( (enmState) == VMCPUSTATE_STOPPED )
340	/** @} */
341
342
343	/** The name of the raw-mode context VMM Core module. */
344	#define VMMRC_MAIN_MODULE_NAME "VMMRC.rc"
345	/** The name of the ring-0 context VMM Core module. */
346	#define VMMR0_MAIN_MODULE_NAME "VMMR0.r0"
347
348	/**
349	* Wrapper macro for avoiding too much \#ifdef VBOX_WITH_RAW_MODE.
350	*/
351	#ifdef VBOX_WITH_RAW_MODE
352	# define VM_WHEN_RAW_MODE(a_WithExpr, a_WithoutExpr) a_WithExpr
353	#else
354	# define VM_WHEN_RAW_MODE(a_WithExpr, a_WithoutExpr) a_WithoutExpr
355	#endif
356
357
358	/** VM Forced Action Flags.
359	*
360	* Use the VM_FF_SET() and VM_FF_CLEAR() macros to change the force
361	* action mask of a VM.
362	*
363	* Available VM bits:
364	* 0, 1, 5, 6, 7, 13, 14, 15, 16, 17, 21, 22, 23, 24, 25, 26, 27, 28, 30
365	*
366	*
367	* Available VMCPU bits:
368	* 11, 14, 15, 35 to 63
369	*
370	* @todo If we run low on VMCPU, we may consider merging the SELM bits
371	*
372	* @{
373	*/
374	/** The virtual sync clock has been stopped, go to TM until it has been
375	* restarted... */
376	#define VM_FF_TM_VIRTUAL_SYNC RT_BIT_32(VM_FF_TM_VIRTUAL_SYNC_BIT)
377	#define VM_FF_TM_VIRTUAL_SYNC_BIT 2
378	/** PDM Queues are pending. */
379	#define VM_FF_PDM_QUEUES RT_BIT_32(VM_FF_PDM_QUEUES_BIT)
380	/** The bit number for VM_FF_PDM_QUEUES. */
381	#define VM_FF_PDM_QUEUES_BIT 3
382	/** PDM DMA transfers are pending. */
383	#define VM_FF_PDM_DMA RT_BIT_32(VM_FF_PDM_DMA_BIT)
384	/** The bit number for VM_FF_PDM_DMA. */
385	#define VM_FF_PDM_DMA_BIT 4
386	/** This action forces the VM to call DBGF so DBGF can service debugger
387	* requests in the emulation thread.
388	* This action flag stays asserted till DBGF clears it.*/
389	#define VM_FF_DBGF RT_BIT_32(VM_FF_DBGF_BIT)
390	/** The bit number for VM_FF_DBGF. */
391	#define VM_FF_DBGF_BIT 8
392	/** This action forces the VM to service pending requests from other
393	* thread or requests which must be executed in another context. */
394	#define VM_FF_REQUEST RT_BIT_32(VM_FF_REQUEST_BIT)
395	#define VM_FF_REQUEST_BIT 9
396	/** Check for VM state changes and take appropriate action. */
397	#define VM_FF_CHECK_VM_STATE RT_BIT_32(VM_FF_CHECK_VM_STATE_BIT)
398	/** The bit number for VM_FF_CHECK_VM_STATE. */
399	#define VM_FF_CHECK_VM_STATE_BIT 10
400	/** Reset the VM. (postponed) */
401	#define VM_FF_RESET RT_BIT_32(VM_FF_RESET_BIT)
402	/** The bit number for VM_FF_RESET. */
403	#define VM_FF_RESET_BIT 11
404	/** EMT rendezvous in VMM. */
405	#define VM_FF_EMT_RENDEZVOUS RT_BIT_32(VM_FF_EMT_RENDEZVOUS_BIT)
406	/** The bit number for VM_FF_EMT_RENDEZVOUS. */
407	#define VM_FF_EMT_RENDEZVOUS_BIT 12
408
409	/** PGM needs to allocate handy pages. */
410	#define VM_FF_PGM_NEED_HANDY_PAGES RT_BIT_32(VM_FF_PGM_NEED_HANDY_PAGES_BIT)
411	#define VM_FF_PGM_NEED_HANDY_PAGES_BIT 18
412	/** PGM is out of memory.
413	* Abandon all loops and code paths which can be resumed and get up to the EM
414	* loops. */
415	#define VM_FF_PGM_NO_MEMORY RT_BIT_32(VM_FF_PGM_NO_MEMORY_BIT)
416	#define VM_FF_PGM_NO_MEMORY_BIT 19
417	/** PGM is about to perform a lightweight pool flush
418	* Guest SMP: all EMT threads should return to ring 3
419	*/
420	#define VM_FF_PGM_POOL_FLUSH_PENDING RT_BIT_32(VM_FF_PGM_POOL_FLUSH_PENDING_BIT)
421	#define VM_FF_PGM_POOL_FLUSH_PENDING_BIT 20
422	/** REM needs to be informed about handler changes. */
423	#define VM_FF_REM_HANDLER_NOTIFY RT_BIT_32(VM_FF_REM_HANDLER_NOTIFY_BIT)
424	/** The bit number for VM_FF_REM_HANDLER_NOTIFY. */
425	#define VM_FF_REM_HANDLER_NOTIFY_BIT 29
426	/** Suspend the VM - debug only. */
427	#define VM_FF_DEBUG_SUSPEND RT_BIT_32(VM_FF_DEBUG_SUSPEND_BIT)
428	#define VM_FF_DEBUG_SUSPEND_BIT 31
429
430
431	/** This action forces the VM to check any pending interrupts on the APIC. */
432	#define VMCPU_FF_INTERRUPT_APIC RT_BIT_64(VMCPU_FF_INTERRUPT_APIC_BIT)
433	#define VMCPU_FF_INTERRUPT_APIC_BIT 0
434	/** This action forces the VM to check any pending interrups on the PIC. */
435	#define VMCPU_FF_INTERRUPT_PIC RT_BIT_64(VMCPU_FF_INTERRUPT_PIC_BIT)
436	#define VMCPU_FF_INTERRUPT_PIC_BIT 1
437	/** This action forces the VM to schedule and run pending timer (TM).
438	* @remarks Don't move - PATM compatibility. */
439	#define VMCPU_FF_TIMER RT_BIT_64(VMCPU_FF_TIMER_BIT)
440	#define VMCPU_FF_TIMER_BIT 2
441	/** This action forces the VM to check any pending NMIs. */
442	#define VMCPU_FF_INTERRUPT_NMI RT_BIT_64(VMCPU_FF_INTERRUPT_NMI_BIT)
443	#define VMCPU_FF_INTERRUPT_NMI_BIT 3
444	/** This action forces the VM to check any pending SMIs. */
445	#define VMCPU_FF_INTERRUPT_SMI RT_BIT_64(VMCPU_FF_INTERRUPT_SMI_BIT)
446	#define VMCPU_FF_INTERRUPT_SMI_BIT 4
447	/** PDM critical section unlocking is pending, process promptly upon return to R3. */
448	#define VMCPU_FF_PDM_CRITSECT RT_BIT_64(VMCPU_FF_PDM_CRITSECT_BIT)
449	#define VMCPU_FF_PDM_CRITSECT_BIT 5
450	/** Special EM internal force flag that is used by EMUnhaltAndWakeUp() to force
451	* the virtual CPU out of the next (/current) halted state. It is not processed
452	* nor cleared by emR3ForcedActions (similar to VMCPU_FF_BLOCK_NMIS), instead it
453	* is cleared the next time EM leaves the HALTED state. */
454	#define VMCPU_FF_UNHALT RT_BIT_64(VMCPU_FF_UNHALT_BIT)
455	#define VMCPU_FF_UNHALT_BIT 6
456	/** Pending IEM action (mask). */
457	#define VMCPU_FF_IEM RT_BIT_64(VMCPU_FF_IEM_BIT)
458	/** Pending IEM action (bit number). */
459	#define VMCPU_FF_IEM_BIT 7
460	/** Pending APIC action (bit number). */
461	#define VMCPU_FF_UPDATE_APIC_BIT 8
462	/** This action forces the VM to update APIC's asynchronously arrived
463	* interrupts as pending interrupts. */
464	#define VMCPU_FF_UPDATE_APIC RT_BIT_64(VMCPU_FF_UPDATE_APIC_BIT)
465	/** This action forces the VM to service pending requests from other
466	* thread or requests which must be executed in another context. */
467	#define VMCPU_FF_REQUEST RT_BIT_64(VMCPU_FF_REQUEST_BIT)
468	#define VMCPU_FF_REQUEST_BIT 9
469	/** Pending DBGF event (alternative to passing VINF_EM_DBG_EVENT around). */
470	#define VMCPU_FF_DBGF RT_BIT_64(VMCPU_FF_DBGF_BIT)
471	/** The bit number for VMCPU_FF_DBGF. */
472	#define VMCPU_FF_DBGF_BIT 10
473	/** This action forces the VM to service any pending updates to CR3 (used only
474	* by HM). */
475	#define VMCPU_FF_HM_UPDATE_CR3 RT_BIT_64(VMCPU_FF_HM_UPDATE_CR3_BIT)
476	#define VMCPU_FF_HM_UPDATE_CR3_BIT 12
477	/** This action forces the VM to service any pending updates to PAE PDPEs (used
478	* only by HM). */
479	#define VMCPU_FF_HM_UPDATE_PAE_PDPES RT_BIT_64(VMCPU_FF_HM_UPDATE_PAE_PDPES_BIT)
480	#define VMCPU_FF_HM_UPDATE_PAE_PDPES_BIT 13
481	/** This action forces the VM to resync the page tables before going
482	* back to execute guest code. (GLOBAL FLUSH) */
483	#define VMCPU_FF_PGM_SYNC_CR3 RT_BIT_64(VMCPU_FF_PGM_SYNC_CR3_BIT)
484	#define VMCPU_FF_PGM_SYNC_CR3_BIT 16
485	/** Same as VM_FF_PGM_SYNC_CR3 except that global pages can be skipped.
486	* (NON-GLOBAL FLUSH) */
487	#define VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL RT_BIT_64(VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL_BIT)
488	#define VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL_BIT 17
489	/** Check for pending TLB shootdown actions (deprecated)
490	* Reserved for furture HM re-use if necessary / safe.
491	* Consumer: HM */
492	#define VMCPU_FF_TLB_SHOOTDOWN_UNUSED RT_BIT_64(VMCPU_FF_TLB_SHOOTDOWN_UNUSED_BIT)
493	#define VMCPU_FF_TLB_SHOOTDOWN_UNUSED_BIT 18
494	/** Check for pending TLB flush action.
495	* Consumer: HM
496	* @todo rename to VMCPU_FF_HM_TLB_FLUSH */
497	#define VMCPU_FF_TLB_FLUSH RT_BIT_64(VMCPU_FF_TLB_FLUSH_BIT)
498	/** The bit number for VMCPU_FF_TLB_FLUSH. */
499	#define VMCPU_FF_TLB_FLUSH_BIT 19
500	#ifdef VBOX_WITH_RAW_MODE
501	/** Check the interrupt and trap gates */
502	# define VMCPU_FF_TRPM_SYNC_IDT RT_BIT_64(VMCPU_FF_TRPM_SYNC_IDT_BIT)
503	# define VMCPU_FF_TRPM_SYNC_IDT_BIT 20
504	/** Check Guest's TSS ring 0 stack */
505	# define VMCPU_FF_SELM_SYNC_TSS RT_BIT_64(VMCPU_FF_SELM_SYNC_TSS_BIT)
506	# define VMCPU_FF_SELM_SYNC_TSS_BIT 21
507	/** Check Guest's GDT table */
508	# define VMCPU_FF_SELM_SYNC_GDT RT_BIT_64(VMCPU_FF_SELM_SYNC_GDT_BIT)
509	# define VMCPU_FF_SELM_SYNC_GDT_BIT 22
510	/** Check Guest's LDT table */
511	# define VMCPU_FF_SELM_SYNC_LDT RT_BIT_64(VMCPU_FF_SELM_SYNC_LDT_BIT)
512	# define VMCPU_FF_SELM_SYNC_LDT_BIT 23
513	#endif /* VBOX_WITH_RAW_MODE */
514	/** Inhibit interrupts pending. See EMGetInhibitInterruptsPC(). */
515	#define VMCPU_FF_INHIBIT_INTERRUPTS RT_BIT_64(VMCPU_FF_INHIBIT_INTERRUPTS_BIT)
516	#define VMCPU_FF_INHIBIT_INTERRUPTS_BIT 24
517	/** Block injection of non-maskable interrupts to the guest. */
518	#define VMCPU_FF_BLOCK_NMIS RT_BIT_64(VMCPU_FF_BLOCK_NMIS_BIT)
519	#define VMCPU_FF_BLOCK_NMIS_BIT 25
520	#ifdef VBOX_WITH_RAW_MODE
521	/** CSAM needs to scan the page that's being executed */
522	# define VMCPU_FF_CSAM_SCAN_PAGE RT_BIT_64(VMCPU_FF_CSAM_SCAN_PAGE_BIT)
523	# define VMCPU_FF_CSAM_SCAN_PAGE_BIT 26
524	/** CSAM needs to do some homework. */
525	# define VMCPU_FF_CSAM_PENDING_ACTION RT_BIT_64(VMCPU_FF_CSAM_PENDING_ACTION_BIT)
526	# define VMCPU_FF_CSAM_PENDING_ACTION_BIT 27
527	#endif /* VBOX_WITH_RAW_MODE */
528	/** Force return to Ring-3. */
529	#define VMCPU_FF_TO_R3 RT_BIT_64(VMCPU_FF_TO_R3_BIT)
530	#define VMCPU_FF_TO_R3_BIT 28
531	/** Force return to ring-3 to service pending I/O or MMIO write.
532	* This is a backup for mechanism VINF_IOM_R3_IOPORT_COMMIT_WRITE and
533	* VINF_IOM_R3_MMIO_COMMIT_WRITE, allowing VINF_EM_DBG_BREAKPOINT and similar
534	* status codes to be propagated at the same time without loss. */
535	#define VMCPU_FF_IOM RT_BIT_64(VMCPU_FF_IOM_BIT)
536	#define VMCPU_FF_IOM_BIT 29
537	#ifdef VBOX_WITH_RAW_MODE
538	/** CPUM need to adjust CR0.TS/EM before executing raw-mode code again. */
539	# define VMCPU_FF_CPUM RT_BIT_64(VMCPU_FF_CPUM_BIT)
540	/** The bit number for VMCPU_FF_CPUM. */
541	# define VMCPU_FF_CPUM_BIT 30
542	#endif /* VBOX_WITH_RAW_MODE */
543	/** Hardware virtualized nested-guest interrupt pending. */
544	#define VMCPU_FF_INTERRUPT_NESTED_GUEST RT_BIT_64(VMCPU_FF_INTERRUPT_NESTED_GUEST_BIT)
545	#define VMCPU_FF_INTERRUPT_NESTED_GUEST_BIT 31
546	/** VMX-preemption timer in effect. */
547	#define VMCPU_FF_VMX_PREEMPT_TIMER RT_BIT_64(VMCPU_FF_VMX_PREEMPT_TIMER_BIT)
548	/** Bit number for VMCPU_FF_VMX_PREEMPT_TIMER. */
549	#define VMCPU_FF_VMX_PREEMPT_TIMER_BIT 32
550	/** Pending MTF (Monitor Trap Flag) event. */
551	#define VMCPU_FF_VMX_MTF RT_BIT_64(VMCPU_FF_VMX_MTF_BIT)
552	/** The bit number for VMCPU_FF_VMX_MTF. */
553	#define VMCPU_FF_VMX_MTF_BIT 33
554	/** VMX APIC-write emulation pending. */
555	#define VMCPU_FF_VMX_APIC_WRITE RT_BIT_64(VMCPU_FF_VMX_APIC_WRITE_BIT)
556	/** The bit number for VMCPU_FF_VMX_UPDATE_VTPR. */
557	#define VMCPU_FF_VMX_APIC_WRITE_BIT 34
558
559
560	/** Externally VM forced actions. Used to quit the idle/wait loop. */
561	#define VM_FF_EXTERNAL_SUSPENDED_MASK ( VM_FF_CHECK_VM_STATE \| VM_FF_DBGF \| VM_FF_REQUEST \| VM_FF_EMT_RENDEZVOUS )
562	/** Externally VMCPU forced actions. Used to quit the idle/wait loop. */
563	#define VMCPU_FF_EXTERNAL_SUSPENDED_MASK ( VMCPU_FF_REQUEST \| VMCPU_FF_DBGF )
564
565	/** Externally forced VM actions. Used to quit the idle/wait loop. */
566	#define VM_FF_EXTERNAL_HALTED_MASK ( VM_FF_CHECK_VM_STATE \| VM_FF_DBGF \| VM_FF_REQUEST \
567	\| VM_FF_PDM_QUEUES \| VM_FF_PDM_DMA \| VM_FF_EMT_RENDEZVOUS )
568	/** Externally forced VMCPU actions. Used to quit the idle/wait loop. */
569	#define VMCPU_FF_EXTERNAL_HALTED_MASK ( VMCPU_FF_UPDATE_APIC \| VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC \
570	\| VMCPU_FF_REQUEST \| VMCPU_FF_INTERRUPT_NMI \| VMCPU_FF_INTERRUPT_SMI \
571	\| VMCPU_FF_UNHALT \| VMCPU_FF_TIMER \| VMCPU_FF_DBGF )
572
573	/** High priority VM pre-execution actions. */
574	#define VM_FF_HIGH_PRIORITY_PRE_MASK ( VM_FF_CHECK_VM_STATE \| VM_FF_DBGF \| VM_FF_TM_VIRTUAL_SYNC \
575	\| VM_FF_DEBUG_SUSPEND \| VM_FF_PGM_NEED_HANDY_PAGES \| VM_FF_PGM_NO_MEMORY \
576	\| VM_FF_EMT_RENDEZVOUS )
577	/** High priority VMCPU pre-execution actions. */
578	#define VMCPU_FF_HIGH_PRIORITY_PRE_MASK ( VMCPU_FF_TIMER \| VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC \
579	\| VMCPU_FF_UPDATE_APIC \| VMCPU_FF_INHIBIT_INTERRUPTS \| VMCPU_FF_DBGF \
580	\| VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL \
581	\| VM_WHEN_RAW_MODE( VMCPU_FF_SELM_SYNC_TSS \| VMCPU_FF_TRPM_SYNC_IDT \
582	\| VMCPU_FF_SELM_SYNC_GDT \| VMCPU_FF_SELM_SYNC_LDT, 0 ) )
583
584	/** High priority VM pre raw-mode execution mask. */
585	#define VM_FF_HIGH_PRIORITY_PRE_RAW_MASK ( VM_FF_PGM_NEED_HANDY_PAGES \| VM_FF_PGM_NO_MEMORY )
586	/** High priority VMCPU pre raw-mode execution mask. */
587	#define VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK ( VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL \
588	\| VMCPU_FF_INHIBIT_INTERRUPTS \
589	\| VM_WHEN_RAW_MODE( VMCPU_FF_SELM_SYNC_TSS \| VMCPU_FF_TRPM_SYNC_IDT \
590	\| VMCPU_FF_SELM_SYNC_GDT \| VMCPU_FF_SELM_SYNC_LDT, 0) )
591
592	/** High priority post-execution actions. */
593	#define VM_FF_HIGH_PRIORITY_POST_MASK ( VM_FF_PGM_NO_MEMORY )
594	/** High priority post-execution actions. */
595	#define VMCPU_FF_HIGH_PRIORITY_POST_MASK ( VMCPU_FF_PDM_CRITSECT \| VM_WHEN_RAW_MODE(VMCPU_FF_CSAM_PENDING_ACTION, 0) \
596	\| VMCPU_FF_HM_UPDATE_CR3 \| VMCPU_FF_HM_UPDATE_PAE_PDPES \
597	\| VMCPU_FF_IEM \| VMCPU_FF_IOM )
598
599	/** Normal priority VM post-execution actions. */
600	#define VM_FF_NORMAL_PRIORITY_POST_MASK ( VM_FF_CHECK_VM_STATE \| VM_FF_DBGF \| VM_FF_RESET \
601	\| VM_FF_PGM_NO_MEMORY \| VM_FF_EMT_RENDEZVOUS)
602	/** Normal priority VMCPU post-execution actions. */
603	#define VMCPU_FF_NORMAL_PRIORITY_POST_MASK ( VM_WHEN_RAW_MODE(VMCPU_FF_CSAM_SCAN_PAGE, 0) \| VMCPU_FF_DBGF )
604
605	/** Normal priority VM actions. */
606	#define VM_FF_NORMAL_PRIORITY_MASK ( VM_FF_REQUEST \| VM_FF_PDM_QUEUES \| VM_FF_PDM_DMA \
607	\| VM_FF_REM_HANDLER_NOTIFY \| VM_FF_EMT_RENDEZVOUS)
608	/** Normal priority VMCPU actions. */
609	#define VMCPU_FF_NORMAL_PRIORITY_MASK ( VMCPU_FF_REQUEST )
610
611	/** Flags to clear before resuming guest execution. */
612	#define VMCPU_FF_RESUME_GUEST_MASK ( VMCPU_FF_TO_R3 )
613
614
615	/** VM flags that cause the REP[\|NE\|E] STRINS loops to yield immediately. */
616	#define VM_FF_HIGH_PRIORITY_POST_REPSTR_MASK ( VM_FF_TM_VIRTUAL_SYNC \| VM_FF_PGM_NEED_HANDY_PAGES \| VM_FF_PGM_NO_MEMORY \
617	\| VM_FF_EMT_RENDEZVOUS \| VM_FF_PGM_POOL_FLUSH_PENDING \| VM_FF_RESET)
618	/** VM flags that cause the REP[\|NE\|E] STRINS loops to yield. */
619	#define VM_FF_YIELD_REPSTR_MASK ( VM_FF_HIGH_PRIORITY_POST_REPSTR_MASK \
620	\| VM_FF_PDM_QUEUES \| VM_FF_PDM_DMA \| VM_FF_DBGF \| VM_FF_DEBUG_SUSPEND )
621	/** VMCPU flags that cause the REP[\|NE\|E] STRINS loops to yield immediately. */
622	#ifdef IN_RING3
623	# define VMCPU_FF_HIGH_PRIORITY_POST_REPSTR_MASK ( VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL \| VMCPU_FF_DBGF )
624	#else
625	# define VMCPU_FF_HIGH_PRIORITY_POST_REPSTR_MASK ( VMCPU_FF_TO_R3 \| VMCPU_FF_IEM \| VMCPU_FF_IOM \| VMCPU_FF_PGM_SYNC_CR3 \
626	\| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL \| VMCPU_FF_DBGF )
627	#endif
628	/** VMCPU flags that cause the REP[\|NE\|E] STRINS loops to yield, interrupts
629	* enabled. */
630	#define VMCPU_FF_YIELD_REPSTR_MASK ( VMCPU_FF_HIGH_PRIORITY_POST_REPSTR_MASK \
631	\| VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_UPDATE_APIC \| VMCPU_FF_INTERRUPT_PIC \
632	\| VMCPU_FF_INTERRUPT_NMI \| VMCPU_FF_INTERRUPT_SMI \| VMCPU_FF_PDM_CRITSECT \
633	\| VMCPU_FF_TIMER \| VMCPU_FF_REQUEST )
634	/** VMCPU flags that cause the REP[\|NE\|E] STRINS loops to yield, interrupts
635	* disabled. */
636	#define VMCPU_FF_YIELD_REPSTR_NOINT_MASK ( VMCPU_FF_YIELD_REPSTR_MASK \
637	& ~(VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_UPDATE_APIC \| VMCPU_FF_INTERRUPT_PIC) )
638
639	/** VM Flags that cause the HM loops to go back to ring-3. */
640	#define VM_FF_HM_TO_R3_MASK ( VM_FF_TM_VIRTUAL_SYNC \| VM_FF_PGM_NEED_HANDY_PAGES \| VM_FF_PGM_NO_MEMORY \
641	\| VM_FF_PDM_QUEUES \| VM_FF_EMT_RENDEZVOUS)
642	/** VMCPU Flags that cause the HM loops to go back to ring-3. */
643	#define VMCPU_FF_HM_TO_R3_MASK ( VMCPU_FF_TO_R3 \| VMCPU_FF_TIMER \| VMCPU_FF_PDM_CRITSECT \
644	\| VMCPU_FF_IEM \| VMCPU_FF_IOM)
645
646	/** High priority ring-0 VM pre HM-mode execution mask. */
647	#define VM_FF_HP_R0_PRE_HM_MASK (VM_FF_HM_TO_R3_MASK \| VM_FF_REQUEST \| VM_FF_PGM_POOL_FLUSH_PENDING \| VM_FF_PDM_DMA)
648	/** High priority ring-0 VMCPU pre HM-mode execution mask. */
649	#define VMCPU_FF_HP_R0_PRE_HM_MASK ( VMCPU_FF_HM_TO_R3_MASK \| VMCPU_FF_PGM_SYNC_CR3 \
650	\| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL \| VMCPU_FF_REQUEST)
651	/** High priority ring-0 VM pre HM-mode execution mask, single stepping. */
652	#define VM_FF_HP_R0_PRE_HM_STEP_MASK (VM_FF_HP_R0_PRE_HM_MASK & ~( VM_FF_TM_VIRTUAL_SYNC \| VM_FF_PDM_QUEUES \
653	\| VM_FF_EMT_RENDEZVOUS \| VM_FF_REQUEST \
654	\| VM_FF_PDM_DMA) )
655	/** High priority ring-0 VMCPU pre HM-mode execution mask, single stepping. */
656	#define VMCPU_FF_HP_R0_PRE_HM_STEP_MASK (VMCPU_FF_HP_R0_PRE_HM_MASK & ~( VMCPU_FF_TO_R3 \| VMCPU_FF_TIMER \
657	\| VMCPU_FF_PDM_CRITSECT \| VMCPU_FF_REQUEST) )
658
659	/** All the forced VM flags. */
660	#define VM_FF_ALL_MASK (UINT32_MAX)
661	/** All the forced VMCPU flags. */
662	#define VMCPU_FF_ALL_MASK (UINT32_MAX)
663
664	/** All the forced VM flags except those related to raw-mode and hardware
665	* assisted execution. */
666	#define VM_FF_ALL_REM_MASK (~(VM_FF_HIGH_PRIORITY_PRE_RAW_MASK) \| VM_FF_PGM_NEED_HANDY_PAGES \| VM_FF_PGM_NO_MEMORY)
667	/** All the forced VMCPU flags except those related to raw-mode and hardware
668	* assisted execution. */
669	#define VMCPU_FF_ALL_REM_MASK (~( VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK \| VMCPU_FF_PDM_CRITSECT \
670	\| VMCPU_FF_TLB_FLUSH \| VM_WHEN_RAW_MODE(VMCPU_FF_CSAM_PENDING_ACTION, 0) ))
671	/** @} */
672
673	/** @def VM_FF_SET
674	* Sets a single force action flag.
675	*
676	* @param pVM The cross context VM structure.
677	* @param fFlag The flag to set.
678	*/
679	#define VM_FF_SET(pVM, fFlag) do { \
680	AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
681	AssertCompile((fFlag) == RT_BIT_32(fFlag##_BIT)); \
682	ASMAtomicOrU32(&(pVM)->fGlobalForcedActions, (fFlag)); \
683	} while (0)
684
685	/** @def VMCPU_FF_SET
686	* Sets a single force action flag for the given VCPU.
687	*
688	* @param pVCpu The cross context virtual CPU structure.
689	* @param fFlag The flag to set.
690	* @sa VMCPU_FF_SET_MASK
691	*/
692	#ifdef VMCPU_WITH_64_BIT_FFS
693	# define VMCPU_FF_SET(pVCpu, fFlag) do { \
694	AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
695	AssertCompile((fFlag) == RT_BIT_64(fFlag##_BIT)); \
696	ASMAtomicBitSet(&(pVCpu)->fLocalForcedActions, fFlag##_BIT); \
697	} while (0)
698	#else
699	# define VMCPU_FF_SET(pVCpu, fFlag) do { \
700	AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
701	AssertCompile((fFlag) == RT_BIT_32(fFlag##_BIT)); \
702	ASMAtomicOrU32(&(pVCpu)->fLocalForcedActions, (fFlag)); \
703	} while (0)
704	#endif
705
706	/** @def VMCPU_FF_SET_MASK
707	* Sets a two or more force action flag for the given VCPU.
708	*
709	* @param pVCpu The cross context virtual CPU structure.
710	* @param fFlags The flags to set.
711	* @sa VMCPU_FF_SET
712	*/
713	#ifdef VMCPU_WITH_64_BIT_FFS
714	# if ARCH_BITS > 32
715	# define VMCPU_FF_SET_MASK(pVCpu, fFlags) \
716	do { ASMAtomicOrU64(&pVCpu->fLocalForcedActions, (fFlags)); } while (0)
717	# else
718	# define VMCPU_FF_SET_MASK(pVCpu, fFlags) do { \
719	if (!((fFlags) >> 32)) ASMAtomicOrU32((uint32_t volatile *)&pVCpu->fLocalForcedActions, (uint32_t)(fFlags)); \
720	else ASMAtomicOrU64(&pVCpu->fLocalForcedActions, (fFlags)); \
721	} while (0)
722	# endif
723	#else
724	# define VMCPU_FF_SET_MASK(pVCpu, fFlags) \
725	do { ASMAtomicOrU32(&pVCpu->fLocalForcedActions, (fFlags)); } while (0)
726	#endif
727
728	/** @def VM_FF_CLEAR
729	* Clears a single force action flag.
730	*
731	* @param pVM The cross context VM structure.
732	* @param fFlag The flag to clear.
733	*/
734	#define VM_FF_CLEAR(pVM, fFlag) do { \
735	AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
736	AssertCompile((fFlag) == RT_BIT_32(fFlag##_BIT)); \
737	ASMAtomicAndU32(&(pVM)->fGlobalForcedActions, ~(fFlag)); \
738	} while (0)
739
740	/** @def VMCPU_FF_CLEAR
741	* Clears a single force action flag for the given VCPU.
742	*
743	* @param pVCpu The cross context virtual CPU structure.
744	* @param fFlag The flag to clear.
745	*/
746	#ifdef VMCPU_WITH_64_BIT_FFS
747	# define VMCPU_FF_CLEAR(pVCpu, fFlag) do { \
748	AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
749	AssertCompile((fFlag) == RT_BIT_64(fFlag##_BIT)); \
750	ASMAtomicBitClear(&(pVCpu)->fLocalForcedActions, fFlag##_BIT); \
751	} while (0)
752	#else
753	# define VMCPU_FF_CLEAR(pVCpu, fFlag) do { \
754	AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
755	AssertCompile((fFlag) == RT_BIT_32(fFlag##_BIT)); \
756	ASMAtomicAndU32(&(pVCpu)->fLocalForcedActions, ~(fFlag)); \
757	} while (0)
758	#endif
759
760	/** @def VMCPU_FF_CLEAR_MASK
761	* Clears two or more force action flags for the given VCPU.
762	*
763	* @param pVCpu The cross context virtual CPU structure.
764	* @param fFlags The flags to clear.
765	*/
766	#ifdef VMCPU_WITH_64_BIT_FFS
767	# if ARCH_BITS > 32
768	# define VMCPU_FF_CLEAR_MASK(pVCpu, fFlags) \
769	do { ASMAtomicAndU64(&(pVCpu)->fLocalForcedActions, ~(fFlags)); } while (0)
770	# else
771	# define VMCPU_FF_CLEAR_MASK(pVCpu, fFlags) do { \
772	if (!((fFlags) >> 32)) ASMAtomicAndU32((uint32_t volatile *)&(pVCpu)->fLocalForcedActions, ~(uint32_t)(fFlags)); \
773	else ASMAtomicAndU64(&(pVCpu)->fLocalForcedActions, ~(fFlags)); \
774	} while (0)
775	# endif
776	#else
777	# define VMCPU_FF_CLEAR_MASK(pVCpu, fFlags) \
778	do { ASMAtomicAndU32(&(pVCpu)->fLocalForcedActions, ~(fFlags)); } while (0)
779	#endif
780
781	/** @def VM_FF_IS_SET
782	* Checks if single a force action flag is set.
783	*
784	* @param pVM The cross context VM structure.
785	* @param fFlag The flag to check.
786	* @sa VM_FF_IS_ANY_SET
787	*/
788	#if !defined(VBOX_STRICT) \|\| !defined(RT_COMPILER_SUPPORTS_LAMBDA)
789	# define VM_FF_IS_SET(pVM, fFlag) RT_BOOL((pVM)->fGlobalForcedActions & (fFlag))
790	#else
791	# define VM_FF_IS_SET(pVM, fFlag) \
792	([](PVM a_pVM) -> bool \
793	{ \
794	AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
795	AssertCompile((fFlag) == RT_BIT_32(fFlag##_BIT)); \
796	return RT_BOOL(a_pVM->fGlobalForcedActions & (fFlag)); \
797	}(pVM))
798	#endif
799
800	/** @def VMCPU_FF_IS_SET
801	* Checks if a single force action flag is set for the given VCPU.
802	*
803	* @param pVCpu The cross context virtual CPU structure.
804	* @param fFlag The flag to check.
805	* @sa VMCPU_FF_IS_ANY_SET
806	*/
807	#if !defined(VBOX_STRICT) \|\| !defined(RT_COMPILER_SUPPORTS_LAMBDA)
808	# define VMCPU_FF_IS_SET(pVCpu, fFlag) RT_BOOL((pVCpu)->fLocalForcedActions & (fFlag))
809	#else
810	# define VMCPU_FF_IS_SET(pVCpu, fFlag) \
811	([](PVMCPU a_pVCpu) -> bool \
812	{ \
813	AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
814	AssertCompile((fFlag) == RT_BIT_64(fFlag##_BIT)); \
815	return RT_BOOL(a_pVCpu->fLocalForcedActions & (fFlag)); \
816	}(pVCpu))
817	#endif
818
819	/** @def VM_FF_IS_ANY_SET
820	* Checks if one or more force action in the specified set is pending.
821	*
822	* @param pVM The cross context VM structure.
823	* @param fFlags The flags to check for.
824	* @sa VM_FF_IS_SET
825	*/
826	#define VM_FF_IS_ANY_SET(pVM, fFlags) RT_BOOL((pVM)->fGlobalForcedActions & (fFlags))
827
828	/** @def VMCPU_FF_IS_ANY_SET
829	* Checks if two or more force action flags in the specified set is set for the given VCPU.
830	*
831	* @param pVCpu The cross context virtual CPU structure.
832	* @param fFlags The flags to check for.
833	* @sa VMCPU_FF_IS_SET
834	*/
835	#define VMCPU_FF_IS_ANY_SET(pVCpu, fFlags) RT_BOOL((pVCpu)->fLocalForcedActions & (fFlags))
836
837	/** @def VM_FF_TEST_AND_CLEAR
838	* Checks if one (!) force action in the specified set is pending and clears it atomically
839	*
840	* @returns true if the bit was set.
841	* @returns false if the bit was clear.
842	* @param pVM The cross context VM structure.
843	* @param fFlag Flag constant to check and clear (_BIT is appended).
844	*/
845	#define VM_FF_TEST_AND_CLEAR(pVM, fFlag) (ASMAtomicBitTestAndClear(&(pVM)->fGlobalForcedActions, fFlag##_BIT))
846
847	/** @def VMCPU_FF_TEST_AND_CLEAR
848	* Checks if one (!) force action in the specified set is pending and clears it atomically
849	*
850	* @returns true if the bit was set.
851	* @returns false if the bit was clear.
852	* @param pVCpu The cross context virtual CPU structure.
853	* @param fFlag Flag constant to check and clear (_BIT is appended).
854	*/
855	#define VMCPU_FF_TEST_AND_CLEAR(pVCpu, fFlag) (ASMAtomicBitTestAndClear(&(pVCpu)->fLocalForcedActions, fFlag##_BIT))
856
857	/** @def VM_FF_IS_PENDING_EXCEPT
858	* Checks if one or more force action in the specified set is pending while one
859	* or more other ones are not.
860	*
861	* @param pVM The cross context VM structure.
862	* @param fFlags The flags to check for.
863	* @param fExcpt The flags that should not be set.
864	*/
865	#define VM_FF_IS_PENDING_EXCEPT(pVM, fFlags, fExcpt) \
866	( ((pVM)->fGlobalForcedActions & (fFlags)) && !((pVM)->fGlobalForcedActions & (fExcpt)) )
867
868	/** @def VM_IS_EMT
869	* Checks if the current thread is the emulation thread (EMT).
870	*
871	* @remark The ring-0 variation will need attention if we expand the ring-0
872	* code to let threads other than EMT mess around with the VM.
873	*/
874	#ifdef IN_RC
875	# define VM_IS_EMT(pVM) true
876	#else
877	# define VM_IS_EMT(pVM) (VMMGetCpu(pVM) != NULL)
878	#endif
879
880	/** @def VMCPU_IS_EMT
881	* Checks if the current thread is the emulation thread (EMT) for the specified
882	* virtual CPU.
883	*/
884	#ifdef IN_RC
885	# define VMCPU_IS_EMT(pVCpu) true
886	#else
887	# define VMCPU_IS_EMT(pVCpu) ((pVCpu) && ((pVCpu) == VMMGetCpu((pVCpu)->CTX_SUFF(pVM))))
888	#endif
889
890	/** @def VM_ASSERT_EMT
891	* Asserts that the current thread IS the emulation thread (EMT).
892	*/
893	#ifdef IN_RC
894	# define VM_ASSERT_EMT(pVM) Assert(VM_IS_EMT(pVM))
895	#elif defined(IN_RING0)
896	# define VM_ASSERT_EMT(pVM) Assert(VM_IS_EMT(pVM))
897	#else
898	# define VM_ASSERT_EMT(pVM) \
899	AssertMsg(VM_IS_EMT(pVM), \
900	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd\n", RTThreadNativeSelf(), VMR3GetVMCPUNativeThread(pVM)))
901	#endif
902
903	/** @def VMCPU_ASSERT_EMT
904	* Asserts that the current thread IS the emulation thread (EMT) of the
905	* specified virtual CPU.
906	*/
907	#ifdef IN_RC
908	# define VMCPU_ASSERT_EMT(pVCpu) Assert(VMCPU_IS_EMT(pVCpu))
909	#elif defined(IN_RING0)
910	# define VMCPU_ASSERT_EMT(pVCpu) AssertMsg(VMCPU_IS_EMT(pVCpu), \
911	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd idCpu=%u\n", \
912	RTThreadNativeSelf(), (pVCpu) ? (pVCpu)->hNativeThreadR0 : 0, \
913	(pVCpu) ? (pVCpu)->idCpu : 0))
914	#else
915	# define VMCPU_ASSERT_EMT(pVCpu) AssertMsg(VMCPU_IS_EMT(pVCpu), \
916	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd idCpu=%#x\n", \
917	RTThreadNativeSelf(), (pVCpu)->hNativeThread, (pVCpu)->idCpu))
918	#endif
919
920	/** @def VM_ASSERT_EMT_RETURN
921	* Asserts that the current thread IS the emulation thread (EMT) and returns if it isn't.
922	*/
923	#ifdef IN_RC
924	# define VM_ASSERT_EMT_RETURN(pVM, rc) AssertReturn(VM_IS_EMT(pVM), (rc))
925	#elif defined(IN_RING0)
926	# define VM_ASSERT_EMT_RETURN(pVM, rc) AssertReturn(VM_IS_EMT(pVM), (rc))
927	#else
928	# define VM_ASSERT_EMT_RETURN(pVM, rc) \
929	AssertMsgReturn(VM_IS_EMT(pVM), \
930	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd\n", RTThreadNativeSelf(), VMR3GetVMCPUNativeThread(pVM)), \
931	(rc))
932	#endif
933
934	/** @def VMCPU_ASSERT_EMT_RETURN
935	* Asserts that the current thread IS the emulation thread (EMT) and returns if it isn't.
936	*/
937	#ifdef IN_RC
938	# define VMCPU_ASSERT_EMT_RETURN(pVCpu, rc) AssertReturn(VMCPU_IS_EMT(pVCpu), (rc))
939	#elif defined(IN_RING0)
940	# define VMCPU_ASSERT_EMT_RETURN(pVCpu, rc) AssertReturn(VMCPU_IS_EMT(pVCpu), (rc))
941	#else
942	# define VMCPU_ASSERT_EMT_RETURN(pVCpu, rc) \
943	AssertMsgReturn(VMCPU_IS_EMT(pVCpu), \
944	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd idCpu=%#x\n", \
945	RTThreadNativeSelf(), (pVCpu)->hNativeThread, (pVCpu)->idCpu), \
946	(rc))
947	#endif
948
949	/** @def VMCPU_ASSERT_EMT_OR_GURU
950	* Asserts that the current thread IS the emulation thread (EMT) of the
951	* specified virtual CPU.
952	*/
953	#if defined(IN_RC) \|\| defined(IN_RING0)
954	# define VMCPU_ASSERT_EMT_OR_GURU(pVCpu) Assert( VMCPU_IS_EMT(pVCpu) \
955	\|\| pVCpu->CTX_SUFF(pVM)->enmVMState == VMSTATE_GURU_MEDITATION \
956	\|\| pVCpu->CTX_SUFF(pVM)->enmVMState == VMSTATE_GURU_MEDITATION_LS )
957	#else
958	# define VMCPU_ASSERT_EMT_OR_GURU(pVCpu) \
959	AssertMsg( VMCPU_IS_EMT(pVCpu) \
960	\|\| pVCpu->CTX_SUFF(pVM)->enmVMState == VMSTATE_GURU_MEDITATION \
961	\|\| pVCpu->CTX_SUFF(pVM)->enmVMState == VMSTATE_GURU_MEDITATION_LS, \
962	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd idCpu=%#x\n", \
963	RTThreadNativeSelf(), (pVCpu)->hNativeThread, (pVCpu)->idCpu))
964	#endif
965
966	/** @def VMCPU_ASSERT_EMT_OR_NOT_RUNNING
967	* Asserts that the current thread IS the emulation thread (EMT) of the
968	* specified virtual CPU or the VM is not running.
969	*/
970	#if defined(IN_RC) \|\| defined(IN_RING0)
971	# define VMCPU_ASSERT_EMT_OR_NOT_RUNNING(pVCpu) \
972	Assert( VMCPU_IS_EMT(pVCpu) \
973	\|\| !VM_IS_RUNNING_FOR_ASSERTIONS_ONLY((pVCpu)->CTX_SUFF(pVM)) )
974	#else
975	# define VMCPU_ASSERT_EMT_OR_NOT_RUNNING(pVCpu) \
976	AssertMsg( VMCPU_IS_EMT(pVCpu) \
977	\|\| !VM_IS_RUNNING_FOR_ASSERTIONS_ONLY((pVCpu)->CTX_SUFF(pVM)), \
978	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd idCpu=%#x\n", \
979	RTThreadNativeSelf(), (pVCpu)->hNativeThread, (pVCpu)->idCpu))
980	#endif
981
982	/** @def VMSTATE_IS_RUNNING
983	* Checks if the given state indicates a running VM.
984	*/
985	#define VMSTATE_IS_RUNNING(a_enmVMState) \
986	( (enmVMState) == VMSTATE_RUNNING \
987	\|\| (enmVMState) == VMSTATE_RUNNING_LS \
988	\|\| (enmVMState) == VMSTATE_RUNNING_FT )
989
990	/** @def VM_IS_RUNNING_FOR_ASSERTIONS_ONLY
991	* Checks if the VM is running.
992	* @note This is only for pure debug assertions. No AssertReturn or similar!
993	* @sa VMSTATE_IS_RUNNING
994	*/
995	#define VM_IS_RUNNING_FOR_ASSERTIONS_ONLY(pVM) \
996	( (pVM)->enmVMState == VMSTATE_RUNNING \
997	\|\| (pVM)->enmVMState == VMSTATE_RUNNING_LS \
998	\|\| (pVM)->enmVMState == VMSTATE_RUNNING_FT )
999
1000	/** @def VM_ASSERT_IS_NOT_RUNNING
1001	* Asserts that the VM is not running.
1002	*/
1003	#if defined(IN_RC) \|\| defined(IN_RING0)
1004	#define VM_ASSERT_IS_NOT_RUNNING(pVM) Assert(!VM_IS_RUNNING_FOR_ASSERTIONS_ONLY(pVM))
1005	#else
1006	#define VM_ASSERT_IS_NOT_RUNNING(pVM) AssertMsg(!VM_IS_RUNNING_FOR_ASSERTIONS_ONLY(pVM), \
1007	("VM is running. enmVMState=%d\n", (pVM)->enmVMState))
1008	#endif
1009
1010	/** @def VM_ASSERT_EMT0
1011	* Asserts that the current thread IS emulation thread \#0 (EMT0).
1012	*/
1013	#define VM_ASSERT_EMT0(pVM) VMCPU_ASSERT_EMT(&(pVM)->aCpus[0])
1014
1015	/** @def VM_ASSERT_EMT0_RETURN
1016	* Asserts that the current thread IS emulation thread \#0 (EMT0) and returns if
1017	* it isn't.
1018	*/
1019	#define VM_ASSERT_EMT0_RETURN(pVM, rc) VMCPU_ASSERT_EMT_RETURN(&(pVM)->aCpus[0], (rc))
1020
1021
1022	/**
1023	* Asserts that the current thread is NOT the emulation thread.
1024	*/
1025	#define VM_ASSERT_OTHER_THREAD(pVM) \
1026	AssertMsg(!VM_IS_EMT(pVM), ("Not other thread!!\n"))
1027
1028
1029	/** @def VM_ASSERT_STATE
1030	* Asserts a certain VM state.
1031	*/
1032	#define VM_ASSERT_STATE(pVM, _enmState) \
1033	AssertMsg((pVM)->enmVMState == (_enmState), \
1034	("state %s, expected %s\n", VMGetStateName((pVM)->enmVMState), VMGetStateName(_enmState)))
1035
1036	/** @def VM_ASSERT_STATE_RETURN
1037	* Asserts a certain VM state and returns if it doesn't match.
1038	*/
1039	#define VM_ASSERT_STATE_RETURN(pVM, _enmState, rc) \
1040	AssertMsgReturn((pVM)->enmVMState == (_enmState), \
1041	("state %s, expected %s\n", VMGetStateName((pVM)->enmVMState), VMGetStateName(_enmState)), \
1042	(rc))
1043
1044	/** @def VM_IS_VALID_EXT
1045	* Asserts a the VM handle is valid for external access, i.e. not being destroy
1046	* or terminated. */
1047	#define VM_IS_VALID_EXT(pVM) \
1048	( RT_VALID_ALIGNED_PTR(pVM, PAGE_SIZE) \
1049	&& ( (unsigned)(pVM)->enmVMState < (unsigned)VMSTATE_DESTROYING \
1050	\|\| ( (unsigned)(pVM)->enmVMState == (unsigned)VMSTATE_DESTROYING \
1051	&& VM_IS_EMT(pVM))) )
1052
1053	/** @def VM_ASSERT_VALID_EXT_RETURN
1054	* Asserts a the VM handle is valid for external access, i.e. not being
1055	* destroy or terminated.
1056	*/
1057	#define VM_ASSERT_VALID_EXT_RETURN(pVM, rc) \
1058	AssertMsgReturn(VM_IS_VALID_EXT(pVM), \
1059	("pVM=%p state %s\n", (pVM), RT_VALID_ALIGNED_PTR(pVM, PAGE_SIZE) \
1060	? VMGetStateName(pVM->enmVMState) : ""), \
1061	(rc))
1062
1063	/** @def VMCPU_ASSERT_VALID_EXT_RETURN
1064	* Asserts a the VMCPU handle is valid for external access, i.e. not being
1065	* destroy or terminated.
1066	*/
1067	#define VMCPU_ASSERT_VALID_EXT_RETURN(pVCpu, rc) \
1068	AssertMsgReturn( RT_VALID_ALIGNED_PTR(pVCpu, 64) \
1069	&& RT_VALID_ALIGNED_PTR((pVCpu)->CTX_SUFF(pVM), PAGE_SIZE) \
1070	&& (unsigned)(pVCpu)->CTX_SUFF(pVM)->enmVMState < (unsigned)VMSTATE_DESTROYING, \
1071	("pVCpu=%p pVM=%p state %s\n", (pVCpu), RT_VALID_ALIGNED_PTR(pVCpu, 64) ? (pVCpu)->CTX_SUFF(pVM) : NULL, \
1072	RT_VALID_ALIGNED_PTR(pVCpu, 64) && RT_VALID_ALIGNED_PTR((pVCpu)->CTX_SUFF(pVM), PAGE_SIZE) \
1073	? VMGetStateName((pVCpu)->pVMR3->enmVMState) : ""), \
1074	(rc))
1075
1076	#endif /* !VBOX_FOR_DTRACE_LIB */
1077
1078
1079	/**
1080	* Helper that HM and NEM uses for safely modifying VM::bMainExecutionEngine.
1081	*
1082	* ONLY HM and NEM MAY USE THIS!
1083	*
1084	* @param a_pVM The cross context VM structure.
1085	* @param a_bValue The new value.
1086	* @internal
1087	*/
1088	#define VM_SET_MAIN_EXECUTION_ENGINE(a_pVM, a_bValue) \
1089	do { \
1090	const_cast<uint8_t >(&(a_pVM)->bMainExecutionEngine) = (a_bValue); \
1091	ASMCompilerBarrier(); /* just to be on the safe side */ \
1092	} while (0)
1093
1094	/**
1095	* Checks whether raw-mode is used.
1096	*
1097	* @retval true if either is used.
1098	* @retval false if software virtualization (raw-mode) is used.
1099	*
1100	* @param a_pVM The cross context VM structure.
1101	* @sa VM_IS_HM_OR_NEM_ENABLED, VM_IS_HM_ENABLED, VM_IS_NEM_ENABLED.
1102	* @internal
1103	*/
1104	#ifdef VBOX_WITH_RAW_MODE
1105	# define VM_IS_RAW_MODE_ENABLED(a_pVM) ((a_pVM)->bMainExecutionEngine == VM_EXEC_ENGINE_RAW_MODE)
1106	#else
1107	# define VM_IS_RAW_MODE_ENABLED(a_pVM) (false)
1108	#endif
1109
1110	/**
1111	* Checks whether HM (VT-x/AMD-V) or NEM is being used by this VM.
1112	*
1113	* @retval true if either is used.
1114	* @retval false if software virtualization (raw-mode) is used.
1115	*
1116	* @param a_pVM The cross context VM structure.
1117	* @sa VM_IS_RAW_MODE_ENABLED, VM_IS_HM_ENABLED, VM_IS_NEM_ENABLED.
1118	* @internal
1119	*/
1120	#define VM_IS_HM_OR_NEM_ENABLED(a_pVM) ((a_pVM)->bMainExecutionEngine != VM_EXEC_ENGINE_RAW_MODE)
1121
1122	/**
1123	* Checks whether HM is being used by this VM.
1124	*
1125	* @retval true if HM (VT-x/AMD-v) is used.
1126	* @retval false if not.
1127	*
1128	* @param a_pVM The cross context VM structure.
1129	* @sa VM_IS_NEM_ENABLED, VM_IS_RAW_MODE_ENABLED, VM_IS_HM_OR_NEM_ENABLED.
1130	* @internal
1131	*/
1132	#define VM_IS_HM_ENABLED(a_pVM) ((a_pVM)->bMainExecutionEngine == VM_EXEC_ENGINE_HW_VIRT)
1133
1134	/**
1135	* Checks whether NEM is being used by this VM.
1136	*
1137	* @retval true if a native hypervisor API is used.
1138	* @retval false if not.
1139	*
1140	* @param a_pVM The cross context VM structure.
1141	* @sa VM_IS_HM_ENABLED, VM_IS_RAW_MODE_ENABLED, VM_IS_HM_OR_NEM_ENABLED.
1142	* @internal
1143	*/
1144	#define VM_IS_NEM_ENABLED(a_pVM) ((a_pVM)->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API)
1145
1146
1147	/**
1148	* The cross context VM structure.
1149	*
1150	* It contains all the VM data which have to be available in all contexts.
1151	* Even if it contains all the data the idea is to use APIs not to modify all
1152	* the members all around the place. Therefore we make use of unions to hide
1153	* everything which isn't local to the current source module. This means we'll
1154	* have to pay a little bit of attention when adding new members to structures
1155	* in the unions and make sure to keep the padding sizes up to date.
1156	*
1157	* Run 'kmk run-struct-tests' (from src/VBox/VMM if you like) after updating!
1158	*/
1159	typedef struct VM
1160	{
1161	/** The state of the VM.
1162	* This field is read only to everyone except the VM and EM. */
1163	VMSTATE volatile enmVMState;
1164	/** Forced action flags.
1165	* See the VM_FF_* \#defines. Updated atomically.
1166	*/
1167	volatile uint32_t fGlobalForcedActions;
1168	/** Pointer to the array of page descriptors for the VM structure allocation. */
1169	R3PTRTYPE(PSUPPAGE) paVMPagesR3;
1170	/** Session handle. For use when calling SUPR0 APIs. */
1171	PSUPDRVSESSION pSession;
1172	/** Pointer to the ring-3 VM structure. */
1173	PUVM pUVM;
1174	/** Ring-3 Host Context VM Pointer. */
1175	R3PTRTYPE(struct VM *) pVMR3;
1176	/** Ring-0 Host Context VM Pointer. */
1177	R0PTRTYPE(struct VM *) pVMR0;
1178	/** Raw-mode Context VM Pointer. */
1179	RCPTRTYPE(struct VM *) pVMRC;
1180
1181	/** The GVM VM handle. Only the GVM should modify this field. */
1182	uint32_t hSelf;
1183	/** Number of virtual CPUs. */
1184	uint32_t cCpus;
1185	/** CPU excution cap (1-100) */
1186	uint32_t uCpuExecutionCap;
1187
1188	/** Size of the VM structure including the VMCPU array. */
1189	uint32_t cbSelf;
1190
1191	/** Offset to the VMCPU array starting from beginning of this structure. */
1192	uint32_t offVMCPU;
1193
1194	/**
1195	* VMMSwitcher assembly entry point returning to host context.
1196	*
1197	* Depending on how the host handles the rc status given in @a eax, this may
1198	* return and let the caller resume whatever it was doing prior to the call.
1199	*
1200	*
1201	* @param eax The return code, register.
1202	* @remark Assume interrupts disabled.
1203	* @remark This method pointer lives here because TRPM needs it.
1204	*/
1205	RTRCPTR pfnVMMRCToHostAsm/(int32_t eax)/;
1206
1207	/**
1208	* VMMSwitcher assembly entry point returning to host context without saving the
1209	* raw-mode context (hyper) registers.
1210	*
1211	* Unlike pfnVMMRC2HCAsm, this will not return to the caller. Instead it
1212	* expects the caller to save a RC context in CPUM where one might return if the
1213	* return code indicate that this is possible.
1214	*
1215	* This method pointer lives here because TRPM needs it.
1216	*
1217	* @param eax The return code, register.
1218	* @remark Assume interrupts disabled.
1219	* @remark This method pointer lives here because TRPM needs it.
1220	*/
1221	RTRCPTR pfnVMMRCToHostAsmNoReturn/(int32_t eax)/;
1222
1223	/** @name Various items that are frequently accessed.
1224	* @{ */
1225	/** The main execution engine, VM_EXEC_ENGINE_XXX.
1226	* This is set early during vmR3InitRing3 by HM or NEM. */
1227	uint8_t const bMainExecutionEngine;
1228
1229	/** Whether to recompile user mode code or run it raw/hm/nem.
1230	* In non-raw-mode both fRecompileUser and fRecompileSupervisor must be set
1231	* to recompiler stuff. */
1232	bool fRecompileUser;
1233	/** Whether to recompile supervisor mode code or run it raw/hm/nem.
1234	* In non-raw-mode both fRecompileUser and fRecompileSupervisor must be set
1235	* to recompiler stuff. */
1236	bool fRecompileSupervisor;
1237	/** Whether raw mode supports ring-1 code or not.
1238	* This will be cleared when not in raw-mode. */
1239	bool fRawRing1Enabled;
1240	/** PATM enabled flag.
1241	* This is placed here for performance reasons.
1242	* This will be cleared when not in raw-mode. */
1243	bool fPATMEnabled;
1244	/** CSAM enabled flag.
1245	* This is placed here for performance reasons.
1246	* This will be cleared when not in raw-mode. */
1247	bool fCSAMEnabled;
1248
1249	/** Hardware VM support is available and enabled.
1250	* Determined very early during init.
1251	* This is placed here for performance reasons.
1252	* @todo obsoleted by bMainExecutionEngine, eliminate. */
1253	bool fHMEnabled;
1254	/** Hardware VM support requires a minimal raw-mode context.
1255	* This is never set on 64-bit hosts, only 32-bit hosts requires it. */
1256	bool fHMNeedRawModeCtx;
1257
1258	/** Set when this VM is the master FT node.
1259	* @todo This doesn't need to be here, FTM should store it in it's own
1260	* structures instead. */
1261	bool fFaultTolerantMaster;
1262	/** Large page enabled flag.
1263	* @todo This doesn't need to be here, PGM should store it in it's own
1264	* structures instead. */
1265	bool fUseLargePages;
1266	/** @} */
1267
1268	/** Alignment padding. */
1269	uint8_t uPadding1[2];
1270
1271	/** @name Debugging
1272	* @{ */
1273	/** Raw-mode Context VM Pointer. */
1274	RCPTRTYPE(RTTRACEBUF) hTraceBufRC;
1275	/** Ring-3 Host Context VM Pointer. */
1276	R3PTRTYPE(RTTRACEBUF) hTraceBufR3;
1277	/** Ring-0 Host Context VM Pointer. */
1278	R0PTRTYPE(RTTRACEBUF) hTraceBufR0;
1279	/** @} */
1280
1281	#if HC_ARCH_BITS == 32
1282	/** Alignment padding. */
1283	uint32_t uPadding2;
1284	#endif
1285
1286	/** @name Switcher statistics (remove)
1287	* @{ */
1288	/** Profiling the total time from Qemu to GC. */
1289	STAMPROFILEADV StatTotalQemuToGC;
1290	/** Profiling the total time from GC to Qemu. */
1291	STAMPROFILEADV StatTotalGCToQemu;
1292	/** Profiling the total time spent in GC. */
1293	STAMPROFILEADV StatTotalInGC;
1294	/** Profiling the total time spent not in Qemu. */
1295	STAMPROFILEADV StatTotalInQemu;
1296	/** Profiling the VMMSwitcher code for going to GC. */
1297	STAMPROFILEADV StatSwitcherToGC;
1298	/** Profiling the VMMSwitcher code for going to HC. */
1299	STAMPROFILEADV StatSwitcherToHC;
1300	STAMPROFILEADV StatSwitcherSaveRegs;
1301	STAMPROFILEADV StatSwitcherSysEnter;
1302	STAMPROFILEADV StatSwitcherDebug;
1303	STAMPROFILEADV StatSwitcherCR0;
1304	STAMPROFILEADV StatSwitcherCR4;
1305	STAMPROFILEADV StatSwitcherJmpCR3;
1306	STAMPROFILEADV StatSwitcherRstrRegs;
1307	STAMPROFILEADV StatSwitcherLgdt;
1308	STAMPROFILEADV StatSwitcherLidt;
1309	STAMPROFILEADV StatSwitcherLldt;
1310	STAMPROFILEADV StatSwitcherTSS;
1311	/** @} */
1312
1313	/** Padding - the unions must be aligned on a 64 bytes boundary and the unions
1314	* must start at the same offset on both 64-bit and 32-bit hosts. */
1315	uint8_t abAlignment3[(HC_ARCH_BITS == 32 ? 24 : 0) + 40];
1316
1317	/** CPUM part. */
1318	union
1319	{
1320	#ifdef ___CPUMInternal_h
1321	struct CPUM s;
1322	#endif
1323	#ifdef ___VBox_vmm_cpum_h
1324	/** Read only info exposed about the host and guest CPUs. */
1325	struct
1326	{
1327	/** Padding for hidden fields. */
1328	uint8_t abHidden0[64];
1329	/** Host CPU feature information. */
1330	CPUMFEATURES HostFeatures;
1331	/** Guest CPU feature information. */
1332	CPUMFEATURES GuestFeatures;
1333	} const ro;
1334	#endif
1335	uint8_t padding[1536]; /* multiple of 64 */
1336	} cpum;
1337
1338	/** VMM part. */
1339	union
1340	{
1341	#ifdef ___VMMInternal_h
1342	struct VMM s;
1343	#endif
1344	uint8_t padding[1600]; /* multiple of 64 */
1345	} vmm;
1346
1347	/** PGM part. */
1348	union
1349	{
1350	#ifdef ___PGMInternal_h
1351	struct PGM s;
1352	#endif
1353	uint8_t padding[40962+6080]; / multiple of 64 */
1354	} pgm;
1355
1356	/** HM part. */
1357	union
1358	{
1359	#ifdef ___HMInternal_h
1360	struct HM s;
1361	#endif
1362	uint8_t padding[5440]; /* multiple of 64 */
1363	} hm;
1364
1365	/** TRPM part. */
1366	union
1367	{
1368	#ifdef ___TRPMInternal_h
1369	struct TRPM s;
1370	#endif
1371	uint8_t padding[5248]; /* multiple of 64 */
1372	} trpm;
1373
1374	/** SELM part. */
1375	union
1376	{
1377	#ifdef ___SELMInternal_h
1378	struct SELM s;
1379	#endif
1380	uint8_t padding[768]; /* multiple of 64 */
1381	} selm;
1382
1383	/** MM part. */
1384	union
1385	{
1386	#ifdef ___MMInternal_h
1387	struct MM s;
1388	#endif
1389	uint8_t padding[192]; /* multiple of 64 */
1390	} mm;
1391
1392	/** PDM part. */
1393	union
1394	{
1395	#ifdef ___PDMInternal_h
1396	struct PDM s;
1397	#endif
1398	uint8_t padding[1920]; /* multiple of 64 */
1399	} pdm;
1400
1401	/** IOM part. */
1402	union
1403	{
1404	#ifdef ___IOMInternal_h
1405	struct IOM s;
1406	#endif
1407	uint8_t padding[896]; /* multiple of 64 */
1408	} iom;
1409
1410	/** EM part. */
1411	union
1412	{
1413	#ifdef ___EMInternal_h
1414	struct EM s;
1415	#endif
1416	uint8_t padding[256]; /* multiple of 64 */
1417	} em;
1418
1419	/** NEM part. */
1420	union
1421	{
1422	#ifdef ___NEMInternal_h
1423	struct NEM s;
1424	#endif
1425	uint8_t padding[128]; /* multiple of 64 */
1426	} nem;
1427
1428	/** TM part. */
1429	union
1430	{
1431	#ifdef ___TMInternal_h
1432	struct TM s;
1433	#endif
1434	uint8_t padding[2496]; /* multiple of 64 */
1435	} tm;
1436
1437	/** DBGF part. */
1438	union
1439	{
1440	#ifdef ___DBGFInternal_h
1441	struct DBGF s;
1442	#endif
1443	#ifdef ___VBox_vmm_dbgf_h
1444	/** Read only info exposed about interrupt breakpoints and selected events. */
1445	struct
1446	{
1447	/** Bitmap of enabled hardware interrupt breakpoints. */
1448	uint32_t bmHardIntBreakpoints[256 / 32];
1449	/** Bitmap of enabled software interrupt breakpoints. */
1450	uint32_t bmSoftIntBreakpoints[256 / 32];
1451	/** Bitmap of selected events.
1452	* This includes non-selectable events too for simplicity, we maintain the
1453	* state for some of these, as it may come in handy. */
1454	uint64_t bmSelectedEvents[(DBGFEVENT_END + 63) / 64];
1455	/** Enabled hardware interrupt breakpoints. */
1456	uint32_t cHardIntBreakpoints;
1457	/** Enabled software interrupt breakpoints. */
1458	uint32_t cSoftIntBreakpoints;
1459	/** The number of selected events. */
1460	uint32_t cSelectedEvents;
1461	/** The number of enabled hardware breakpoints. */
1462	uint8_t cEnabledHwBreakpoints;
1463	/** The number of enabled hardware I/O breakpoints. */
1464	uint8_t cEnabledHwIoBreakpoints;
1465	/** The number of enabled INT3 breakpoints. */
1466	uint8_t cEnabledInt3Breakpoints;
1467	uint8_t abPadding[1]; /*< Unused padding space up for grabs. /
1468	} const ro;
1469	#endif
1470	uint8_t padding[2432]; /* multiple of 64 */
1471	} dbgf;
1472
1473	/** SSM part. */
1474	union
1475	{
1476	#ifdef ___SSMInternal_h
1477	struct SSM s;
1478	#endif
1479	uint8_t padding[128]; /* multiple of 64 */
1480	} ssm;
1481
1482	/** FTM part. */
1483	union
1484	{
1485	#ifdef ___FTMInternal_h
1486	struct FTM s;
1487	#endif
1488	uint8_t padding[512]; /* multiple of 64 */
1489	} ftm;
1490
1491	#ifdef VBOX_WITH_RAW_MODE
1492	/** PATM part. */
1493	union
1494	{
1495	# ifdef ___PATMInternal_h
1496	struct PATM s;
1497	# endif
1498	uint8_t padding[768]; /* multiple of 64 */
1499	} patm;
1500
1501	/** CSAM part. */
1502	union
1503	{
1504	# ifdef ___CSAMInternal_h
1505	struct CSAM s;
1506	# endif
1507	uint8_t padding[1088]; /* multiple of 64 */
1508	} csam;
1509	#endif
1510
1511	#ifdef VBOX_WITH_REM
1512	/** REM part. */
1513	union
1514	{
1515	# ifdef ___REMInternal_h
1516	struct REM s;
1517	# endif
1518	uint8_t padding[0x11100]; /* multiple of 64 */
1519	} rem;
1520	#endif
1521
1522	union
1523	{
1524	#ifdef ___GIMInternal_h
1525	struct GIM s;
1526	#endif
1527	uint8_t padding[448]; /* multiple of 64 */
1528	} gim;
1529
1530	union
1531	{
1532	#ifdef ___APICInternal_h
1533	struct APIC s;
1534	#endif
1535	uint8_t padding[128]; /* multiple of 8 */
1536	} apic;
1537
1538	/* ---- begin small stuff ---- */
1539
1540	/** VM part. */
1541	union
1542	{
1543	#ifdef ___VMInternal_h
1544	struct VMINT s;
1545	#endif
1546	uint8_t padding[32]; /* multiple of 8 */
1547	} vm;
1548
1549	/** CFGM part. */
1550	union
1551	{
1552	#ifdef ___CFGMInternal_h
1553	struct CFGM s;
1554	#endif
1555	uint8_t padding[8]; /* multiple of 8 */
1556	} cfgm;
1557
1558	/** Padding for aligning the cpu array on a page boundary. */
1559	#if defined(VBOX_WITH_REM) && defined(VBOX_WITH_RAW_MODE)
1560	uint8_t abAlignment2[3670];
1561	#elif defined(VBOX_WITH_REM) && !defined(VBOX_WITH_RAW_MODE)
1562	uint8_t abAlignment2[1430];
1563	#elif !defined(VBOX_WITH_REM) && defined(VBOX_WITH_RAW_MODE)
1564	uint8_t abAlignment2[3926];
1565	#else
1566	uint8_t abAlignment2[1686];
1567	#endif
1568
1569	/* ---- end small stuff ---- */
1570
1571	/** VMCPU array for the configured number of virtual CPUs.
1572	* Must be aligned on a page boundary for TLB hit reasons as well as
1573	* alignment of VMCPU members. */
1574	VMCPU aCpus[1];
1575	} VM;
1576
1577
1578	#ifdef IN_RC
1579	RT_C_DECLS_BEGIN
1580
1581	/** The VM structure.
1582	* This is imported from the VMMRCBuiltin module, i.e. it's a one of those magic
1583	* globals which we should avoid using.
1584	*/
1585	extern DECLIMPORT(VM) g_VM;
1586
1587	RT_C_DECLS_END
1588	#endif
1589
1590	/** @} */
1591
1592	#endif
1593

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source: vbox/trunk/include/VBox/vmm/vm.h@ 75620

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