vm.h@ 75671

Last change on this file since 75671 was 75671, checked in by vboxsync, 6 years ago
VMM: Nested VMX: bugref:9180 Implement NMI-unblocking due to IRET for VM-exits. Implemented restoring blocking of NMI when VM-entry fails while checking/loading guest-state. Fixed loading blocking by NMI during VM-entry.
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 60.6 KB

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1	/** @file
2	* VM - The Virtual Machine, data.
3	*/
4
5	/*
6	* Copyright (C) 2006-2017 Oracle Corporation
7	*
8	* This file is part of VirtualBox Open Source Edition (OSE), as
9	* available from http://www.virtualbox.org. This file is free software;
10	* you can redistribute it and/or modify it under the terms of the GNU
11	* General Public License (GPL) as published by the Free Software
12	* Foundation, in version 2 as it comes in the "COPYING" file of the
13	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15	*
16	* The contents of this file may alternatively be used under the terms
17	* of the Common Development and Distribution License Version 1.0
18	* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19	* VirtualBox OSE distribution, in which case the provisions of the
20	* CDDL are applicable instead of those of the GPL.
21	*
22	* You may elect to license modified versions of this file under the
23	* terms and conditions of either the GPL or the CDDL or both.
24	*/
25
26	#ifndef ___VBox_vmm_vm_h
27	#define ___VBox_vmm_vm_h
28
29	#ifndef VBOX_FOR_DTRACE_LIB
30	# include <iprt/param.h>
31	# include <VBox/types.h>
32	# include <VBox/vmm/cpum.h>
33	# include <VBox/vmm/stam.h>
34	# include <VBox/vmm/vmapi.h>
35	# include <VBox/vmm/vmm.h>
36	# include <VBox/sup.h>
37	#else
38	# pragma D depends_on library vbox-types.d
39	# pragma D depends_on library CPUMInternal.d
40	# define ___CPUMInternal_h
41	#endif
42
43
44
45	/** @defgroup grp_vm The Virtual Machine
46	* @ingroup grp_vmm
47	* @{
48	*/
49
50	/**
51	* The state of a Virtual CPU.
52	*
53	* The basic state indicated here is whether the CPU has been started or not. In
54	* addition, there are sub-states when started for assisting scheduling (GVMM
55	* mostly).
56	*
57	* The transition out of the STOPPED state is done by a vmR3PowerOn.
58	* The transition back to the STOPPED state is done by vmR3PowerOff.
59	*
60	* (Alternatively we could let vmR3PowerOn start CPU 0 only and let the SPIP
61	* handling switch on the other CPUs. Then vmR3Reset would stop all but CPU 0.)
62	*/
63	typedef enum VMCPUSTATE
64	{
65	/** The customary invalid zero. */
66	VMCPUSTATE_INVALID = 0,
67
68	/** Virtual CPU has not yet been started. */
69	VMCPUSTATE_STOPPED,
70
71	/** CPU started. */
72	VMCPUSTATE_STARTED,
73	/** CPU started in HM context. */
74	VMCPUSTATE_STARTED_HM,
75	/** Executing guest code and can be poked (RC or STI bits of HM). */
76	VMCPUSTATE_STARTED_EXEC,
77	/** Executing guest code in the recompiler. */
78	VMCPUSTATE_STARTED_EXEC_REM,
79	/** Executing guest code using NEM. */
80	VMCPUSTATE_STARTED_EXEC_NEM,
81	VMCPUSTATE_STARTED_EXEC_NEM_WAIT,
82	VMCPUSTATE_STARTED_EXEC_NEM_CANCELED,
83	/** Halted. */
84	VMCPUSTATE_STARTED_HALTED,
85
86	/** The end of valid virtual CPU states. */
87	VMCPUSTATE_END,
88
89	/** Ensure 32-bit type. */
90	VMCPUSTATE_32BIT_HACK = 0x7fffffff
91	} VMCPUSTATE;
92
93	/** Enables 64-bit FFs. */
94	#define VMCPU_WITH_64_BIT_FFS
95
96
97	/**
98	* The cross context virtual CPU structure.
99	*
100	* Run 'kmk run-struct-tests' (from src/VBox/VMM if you like) after updating!
101	*/
102	typedef struct VMCPU
103	{
104	/** @name Volatile per-cpu data.
105	* @{ */
106	/** Per CPU forced action.
107	* See the VMCPU_FF_* \#defines. Updated atomically. */
108	#ifdef VMCPU_WITH_64_BIT_FFS
109	uint64_t volatile fLocalForcedActions;
110	#else
111	uint32_t volatile fLocalForcedActions;
112	uint32_t fForLocalForcedActionsExpansion;
113	#endif
114	/** The CPU state. */
115	VMCPUSTATE volatile enmState;
116
117	/** Which host CPU ID is this EMT running on.
118	* Only valid when in RC or HMR0 with scheduling disabled. */
119	RTCPUID volatile idHostCpu;
120	/** The CPU set index corresponding to idHostCpu, UINT32_MAX if not valid.
121	* @remarks Best to make sure iHostCpuSet shares cache line with idHostCpu! */
122	uint32_t volatile iHostCpuSet;
123	/** Padding up to 64 bytes. */
124	uint8_t abAlignment0[64 - 20];
125	/** @} */
126
127	/** IEM part.
128	* @remarks This comes first as it allows the use of 8-bit immediates for the
129	* first 64 bytes of the structure, reducing code size a wee bit. */
130	#ifdef ___IEMInternal_h /* For PDB hacking. */
131	union VMCPUUNIONIEMFULL
132	#else
133	union VMCPUUNIONIEMSTUB
134	#endif
135	{
136	#ifdef ___IEMInternal_h
137	struct IEMCPU s;
138	#endif
139	uint8_t padding[18496]; /* multiple of 64 */
140	} iem;
141
142	/** @name Static per-cpu data.
143	* (Putting this after IEM, hoping that it's less frequently used than it.)
144	* @{ */
145	/** The CPU ID.
146	* This is the index into the VM::aCpu array. */
147	VMCPUID idCpu;
148	/** Raw-mode Context VM Pointer. */
149	PVMRC pVMRC;
150	/** Ring-3 Host Context VM Pointer. */
151	PVMR3 pVMR3;
152	/** Ring-0 Host Context VM Pointer. */
153	PVMR0 pVMR0;
154	/** Pointer to the ring-3 UVMCPU structure. */
155	PUVMCPU pUVCpu;
156	/** The native thread handle. */
157	RTNATIVETHREAD hNativeThread;
158	/** The native R0 thread handle. (different from the R3 handle!) */
159	RTNATIVETHREAD hNativeThreadR0;
160	/** Align the structures below bit on a 64-byte boundary and make sure it starts
161	* at the same offset in both 64-bit and 32-bit builds.
162	*
163	* @remarks The alignments of the members that are larger than 48 bytes should be
164	* 64-byte for cache line reasons. structs containing small amounts of
165	* data could be lumped together at the end with a < 64 byte padding
166	* following it (to grow into and align the struct size).
167	*/
168	uint8_t abAlignment1[64 - 4 - 4 - 5 * (HC_ARCH_BITS == 64 ? 8 : 4)];
169	/** @} */
170
171	/** HM part. */
172	union VMCPUUNIONHM
173	{
174	#ifdef ___HMInternal_h
175	struct HMCPU s;
176	#endif
177	uint8_t padding[5888]; /* multiple of 64 */
178	} hm;
179
180	/** NEM part. */
181	union VMCPUUNIONNEM
182	{
183	#ifdef ___NEMInternal_h
184	struct NEMCPU s;
185	#endif
186	uint8_t padding[512]; /* multiple of 64 */
187	} nem;
188
189	/** TRPM part. */
190	union VMCPUUNIONTRPM
191	{
192	#ifdef ___TRPMInternal_h
193	struct TRPMCPU s;
194	#endif
195	uint8_t padding[128]; /* multiple of 64 */
196	} trpm;
197
198	/** TM part. */
199	union VMCPUUNIONTM
200	{
201	#ifdef ___TMInternal_h
202	struct TMCPU s;
203	#endif
204	uint8_t padding[384]; /* multiple of 64 */
205	} tm;
206
207	/** VMM part. */
208	union VMCPUUNIONVMM
209	{
210	#ifdef ___VMMInternal_h
211	struct VMMCPU s;
212	#endif
213	uint8_t padding[896]; /* multiple of 64 */
214	} vmm;
215
216	/** PDM part. */
217	union VMCPUUNIONPDM
218	{
219	#ifdef ___PDMInternal_h
220	struct PDMCPU s;
221	#endif
222	uint8_t padding[256]; /* multiple of 64 */
223	} pdm;
224
225	/** IOM part. */
226	union VMCPUUNIONIOM
227	{
228	#ifdef ___IOMInternal_h
229	struct IOMCPU s;
230	#endif
231	uint8_t padding[512]; /* multiple of 64 */
232	} iom;
233
234	/** DBGF part.
235	* @todo Combine this with other tiny structures. */
236	union VMCPUUNIONDBGF
237	{
238	#ifdef ___DBGFInternal_h
239	struct DBGFCPU s;
240	#endif
241	uint8_t padding[256]; /* multiple of 64 */
242	} dbgf;
243
244	/** GIM part. */
245	union VMCPUUNIONGIM
246	{
247	#ifdef ___GIMInternal_h
248	struct GIMCPU s;
249	#endif
250	uint8_t padding[512]; /* multiple of 64 */
251	} gim;
252
253	/** APIC part. */
254	union VMCPUUNIONAPIC
255	{
256	#ifdef ___APICInternal_h
257	struct APICCPU s;
258	#endif
259	uint8_t padding[1792]; /* multiple of 64 */
260	} apic;
261
262	/*
263	* Some less frequently used global members that doesn't need to take up
264	* precious space at the head of the structure.
265	*/
266
267	/** Trace groups enable flags. */
268	uint32_t fTraceGroups; /* 64 / 44 */
269	/** State data for use by ad hoc profiling. */
270	uint32_t uAdHoc;
271	/** Profiling samples for use by ad hoc profiling. */
272	STAMPROFILEADV aStatAdHoc[8]; /* size: 408 = 320 /
273
274	/** Align the following members on page boundary. */
275	uint8_t abAlignment2[2680];
276
277	/** PGM part. */
278	union VMCPUUNIONPGM
279	{
280	#ifdef ___PGMInternal_h
281	struct PGMCPU s;
282	#endif
283	uint8_t padding[4096]; /* multiple of 4096 */
284	} pgm;
285
286	/** CPUM part. */
287	union VMCPUUNIONCPUM
288	{
289	#ifdef ___CPUMInternal_h
290	struct CPUMCPU s;
291	#endif
292	#ifdef VMCPU_INCL_CPUM_GST_CTX
293	/** The guest CPUM context for direct use by execution engines.
294	* This is not for general consumption, but for HM, REM, IEM, and maybe a few
295	* others. The rest will use the function based CPUM API. */
296	CPUMCTX GstCtx;
297	#endif
298	uint8_t padding[4096]; /* multiple of 4096 */
299	} cpum;
300
301	/** EM part. */
302	union VMCPUUNIONEM
303	{
304	#ifdef ___EMInternal_h
305	struct EMCPU s;
306	#endif
307	uint8_t padding[40960]; /* multiple of 4096 */
308	} em;
309	} VMCPU;
310
311
312	#ifndef VBOX_FOR_DTRACE_LIB
313
314	/** @name Operations on VMCPU::enmState
315	* @{ */
316	/** Gets the VMCPU state. */
317	#define VMCPU_GET_STATE(pVCpu) ( (pVCpu)->enmState )
318	/** Sets the VMCPU state. */
319	#define VMCPU_SET_STATE(pVCpu, enmNewState) \
320	ASMAtomicWriteU32((uint32_t volatile *)&(pVCpu)->enmState, (enmNewState))
321	/** Cmpares and sets the VMCPU state. */
322	#define VMCPU_CMPXCHG_STATE(pVCpu, enmNewState, enmOldState) \
323	ASMAtomicCmpXchgU32((uint32_t volatile *)&(pVCpu)->enmState, (enmNewState), (enmOldState))
324	/** Checks the VMCPU state. */
325	#ifdef VBOX_STRICT
326	# define VMCPU_ASSERT_STATE(pVCpu, enmExpectedState) \
327	do { \
328	VMCPUSTATE enmState = VMCPU_GET_STATE(pVCpu); \
329	AssertMsg(enmState == (enmExpectedState), \
330	("enmState=%d enmExpectedState=%d idCpu=%u\n", \
331	enmState, enmExpectedState, (pVCpu)->idCpu)); \
332	} while (0)
333	#else
334	# define VMCPU_ASSERT_STATE(pVCpu, enmExpectedState) do { } while (0)
335	#endif
336	/** Tests if the state means that the CPU is started. */
337	#define VMCPUSTATE_IS_STARTED(enmState) ( (enmState) > VMCPUSTATE_STOPPED )
338	/** Tests if the state means that the CPU is stopped. */
339	#define VMCPUSTATE_IS_STOPPED(enmState) ( (enmState) == VMCPUSTATE_STOPPED )
340	/** @} */
341
342
343	/** The name of the raw-mode context VMM Core module. */
344	#define VMMRC_MAIN_MODULE_NAME "VMMRC.rc"
345	/** The name of the ring-0 context VMM Core module. */
346	#define VMMR0_MAIN_MODULE_NAME "VMMR0.r0"
347
348	/**
349	* Wrapper macro for avoiding too much \#ifdef VBOX_WITH_RAW_MODE.
350	*/
351	#ifdef VBOX_WITH_RAW_MODE
352	# define VM_WHEN_RAW_MODE(a_WithExpr, a_WithoutExpr) a_WithExpr
353	#else
354	# define VM_WHEN_RAW_MODE(a_WithExpr, a_WithoutExpr) a_WithoutExpr
355	#endif
356
357
358	/** VM Forced Action Flags.
359	*
360	* Use the VM_FF_SET() and VM_FF_CLEAR() macros to change the force
361	* action mask of a VM.
362	*
363	* Available VM bits:
364	* 0, 1, 5, 6, 7, 13, 14, 15, 16, 17, 21, 22, 23, 24, 25, 26, 27, 28, 30
365	*
366	*
367	* Available VMCPU bits:
368	* 11, 14, 15, 35 to 63
369	*
370	* @todo If we run low on VMCPU, we may consider merging the SELM bits
371	*
372	* @{
373	*/
374	/** The virtual sync clock has been stopped, go to TM until it has been
375	* restarted... */
376	#define VM_FF_TM_VIRTUAL_SYNC RT_BIT_32(VM_FF_TM_VIRTUAL_SYNC_BIT)
377	#define VM_FF_TM_VIRTUAL_SYNC_BIT 2
378	/** PDM Queues are pending. */
379	#define VM_FF_PDM_QUEUES RT_BIT_32(VM_FF_PDM_QUEUES_BIT)
380	/** The bit number for VM_FF_PDM_QUEUES. */
381	#define VM_FF_PDM_QUEUES_BIT 3
382	/** PDM DMA transfers are pending. */
383	#define VM_FF_PDM_DMA RT_BIT_32(VM_FF_PDM_DMA_BIT)
384	/** The bit number for VM_FF_PDM_DMA. */
385	#define VM_FF_PDM_DMA_BIT 4
386	/** This action forces the VM to call DBGF so DBGF can service debugger
387	* requests in the emulation thread.
388	* This action flag stays asserted till DBGF clears it.*/
389	#define VM_FF_DBGF RT_BIT_32(VM_FF_DBGF_BIT)
390	/** The bit number for VM_FF_DBGF. */
391	#define VM_FF_DBGF_BIT 8
392	/** This action forces the VM to service pending requests from other
393	* thread or requests which must be executed in another context. */
394	#define VM_FF_REQUEST RT_BIT_32(VM_FF_REQUEST_BIT)
395	#define VM_FF_REQUEST_BIT 9
396	/** Check for VM state changes and take appropriate action. */
397	#define VM_FF_CHECK_VM_STATE RT_BIT_32(VM_FF_CHECK_VM_STATE_BIT)
398	/** The bit number for VM_FF_CHECK_VM_STATE. */
399	#define VM_FF_CHECK_VM_STATE_BIT 10
400	/** Reset the VM. (postponed) */
401	#define VM_FF_RESET RT_BIT_32(VM_FF_RESET_BIT)
402	/** The bit number for VM_FF_RESET. */
403	#define VM_FF_RESET_BIT 11
404	/** EMT rendezvous in VMM. */
405	#define VM_FF_EMT_RENDEZVOUS RT_BIT_32(VM_FF_EMT_RENDEZVOUS_BIT)
406	/** The bit number for VM_FF_EMT_RENDEZVOUS. */
407	#define VM_FF_EMT_RENDEZVOUS_BIT 12
408
409	/** PGM needs to allocate handy pages. */
410	#define VM_FF_PGM_NEED_HANDY_PAGES RT_BIT_32(VM_FF_PGM_NEED_HANDY_PAGES_BIT)
411	#define VM_FF_PGM_NEED_HANDY_PAGES_BIT 18
412	/** PGM is out of memory.
413	* Abandon all loops and code paths which can be resumed and get up to the EM
414	* loops. */
415	#define VM_FF_PGM_NO_MEMORY RT_BIT_32(VM_FF_PGM_NO_MEMORY_BIT)
416	#define VM_FF_PGM_NO_MEMORY_BIT 19
417	/** PGM is about to perform a lightweight pool flush
418	* Guest SMP: all EMT threads should return to ring 3
419	*/
420	#define VM_FF_PGM_POOL_FLUSH_PENDING RT_BIT_32(VM_FF_PGM_POOL_FLUSH_PENDING_BIT)
421	#define VM_FF_PGM_POOL_FLUSH_PENDING_BIT 20
422	/** REM needs to be informed about handler changes. */
423	#define VM_FF_REM_HANDLER_NOTIFY RT_BIT_32(VM_FF_REM_HANDLER_NOTIFY_BIT)
424	/** The bit number for VM_FF_REM_HANDLER_NOTIFY. */
425	#define VM_FF_REM_HANDLER_NOTIFY_BIT 29
426	/** Suspend the VM - debug only. */
427	#define VM_FF_DEBUG_SUSPEND RT_BIT_32(VM_FF_DEBUG_SUSPEND_BIT)
428	#define VM_FF_DEBUG_SUSPEND_BIT 31
429
430
431	/** This action forces the VM to check any pending interrupts on the APIC. */
432	#define VMCPU_FF_INTERRUPT_APIC RT_BIT_64(VMCPU_FF_INTERRUPT_APIC_BIT)
433	#define VMCPU_FF_INTERRUPT_APIC_BIT 0
434	/** This action forces the VM to check any pending interrups on the PIC. */
435	#define VMCPU_FF_INTERRUPT_PIC RT_BIT_64(VMCPU_FF_INTERRUPT_PIC_BIT)
436	#define VMCPU_FF_INTERRUPT_PIC_BIT 1
437	/** This action forces the VM to schedule and run pending timer (TM).
438	* @remarks Don't move - PATM compatibility. */
439	#define VMCPU_FF_TIMER RT_BIT_64(VMCPU_FF_TIMER_BIT)
440	#define VMCPU_FF_TIMER_BIT 2
441	/** This action forces the VM to check any pending NMIs. */
442	#define VMCPU_FF_INTERRUPT_NMI RT_BIT_64(VMCPU_FF_INTERRUPT_NMI_BIT)
443	#define VMCPU_FF_INTERRUPT_NMI_BIT 3
444	/** This action forces the VM to check any pending SMIs. */
445	#define VMCPU_FF_INTERRUPT_SMI RT_BIT_64(VMCPU_FF_INTERRUPT_SMI_BIT)
446	#define VMCPU_FF_INTERRUPT_SMI_BIT 4
447	/** PDM critical section unlocking is pending, process promptly upon return to R3. */
448	#define VMCPU_FF_PDM_CRITSECT RT_BIT_64(VMCPU_FF_PDM_CRITSECT_BIT)
449	#define VMCPU_FF_PDM_CRITSECT_BIT 5
450	/** Special EM internal force flag that is used by EMUnhaltAndWakeUp() to force
451	* the virtual CPU out of the next (/current) halted state. It is not processed
452	* nor cleared by emR3ForcedActions (similar to VMCPU_FF_BLOCK_NMIS), instead it
453	* is cleared the next time EM leaves the HALTED state. */
454	#define VMCPU_FF_UNHALT RT_BIT_64(VMCPU_FF_UNHALT_BIT)
455	#define VMCPU_FF_UNHALT_BIT 6
456	/** Pending IEM action (mask). */
457	#define VMCPU_FF_IEM RT_BIT_64(VMCPU_FF_IEM_BIT)
458	/** Pending IEM action (bit number). */
459	#define VMCPU_FF_IEM_BIT 7
460	/** Pending APIC action (bit number). */
461	#define VMCPU_FF_UPDATE_APIC_BIT 8
462	/** This action forces the VM to update APIC's asynchronously arrived
463	* interrupts as pending interrupts. */
464	#define VMCPU_FF_UPDATE_APIC RT_BIT_64(VMCPU_FF_UPDATE_APIC_BIT)
465	/** This action forces the VM to service pending requests from other
466	* thread or requests which must be executed in another context. */
467	#define VMCPU_FF_REQUEST RT_BIT_64(VMCPU_FF_REQUEST_BIT)
468	#define VMCPU_FF_REQUEST_BIT 9
469	/** Pending DBGF event (alternative to passing VINF_EM_DBG_EVENT around). */
470	#define VMCPU_FF_DBGF RT_BIT_64(VMCPU_FF_DBGF_BIT)
471	/** The bit number for VMCPU_FF_DBGF. */
472	#define VMCPU_FF_DBGF_BIT 10
473	/** This action forces the VM to service any pending updates to CR3 (used only
474	* by HM). */
475	#define VMCPU_FF_HM_UPDATE_CR3 RT_BIT_64(VMCPU_FF_HM_UPDATE_CR3_BIT)
476	#define VMCPU_FF_HM_UPDATE_CR3_BIT 12
477	/** This action forces the VM to service any pending updates to PAE PDPEs (used
478	* only by HM). */
479	#define VMCPU_FF_HM_UPDATE_PAE_PDPES RT_BIT_64(VMCPU_FF_HM_UPDATE_PAE_PDPES_BIT)
480	#define VMCPU_FF_HM_UPDATE_PAE_PDPES_BIT 13
481	/** This action forces the VM to resync the page tables before going
482	* back to execute guest code. (GLOBAL FLUSH) */
483	#define VMCPU_FF_PGM_SYNC_CR3 RT_BIT_64(VMCPU_FF_PGM_SYNC_CR3_BIT)
484	#define VMCPU_FF_PGM_SYNC_CR3_BIT 16
485	/** Same as VM_FF_PGM_SYNC_CR3 except that global pages can be skipped.
486	* (NON-GLOBAL FLUSH) */
487	#define VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL RT_BIT_64(VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL_BIT)
488	#define VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL_BIT 17
489	/** Check for pending TLB shootdown actions (deprecated)
490	* Reserved for furture HM re-use if necessary / safe.
491	* Consumer: HM */
492	#define VMCPU_FF_TLB_SHOOTDOWN_UNUSED RT_BIT_64(VMCPU_FF_TLB_SHOOTDOWN_UNUSED_BIT)
493	#define VMCPU_FF_TLB_SHOOTDOWN_UNUSED_BIT 18
494	/** Check for pending TLB flush action.
495	* Consumer: HM
496	* @todo rename to VMCPU_FF_HM_TLB_FLUSH */
497	#define VMCPU_FF_TLB_FLUSH RT_BIT_64(VMCPU_FF_TLB_FLUSH_BIT)
498	/** The bit number for VMCPU_FF_TLB_FLUSH. */
499	#define VMCPU_FF_TLB_FLUSH_BIT 19
500	#ifdef VBOX_WITH_RAW_MODE
501	/** Check the interrupt and trap gates */
502	# define VMCPU_FF_TRPM_SYNC_IDT RT_BIT_64(VMCPU_FF_TRPM_SYNC_IDT_BIT)
503	# define VMCPU_FF_TRPM_SYNC_IDT_BIT 20
504	/** Check Guest's TSS ring 0 stack */
505	# define VMCPU_FF_SELM_SYNC_TSS RT_BIT_64(VMCPU_FF_SELM_SYNC_TSS_BIT)
506	# define VMCPU_FF_SELM_SYNC_TSS_BIT 21
507	/** Check Guest's GDT table */
508	# define VMCPU_FF_SELM_SYNC_GDT RT_BIT_64(VMCPU_FF_SELM_SYNC_GDT_BIT)
509	# define VMCPU_FF_SELM_SYNC_GDT_BIT 22
510	/** Check Guest's LDT table */
511	# define VMCPU_FF_SELM_SYNC_LDT RT_BIT_64(VMCPU_FF_SELM_SYNC_LDT_BIT)
512	# define VMCPU_FF_SELM_SYNC_LDT_BIT 23
513	#endif /* VBOX_WITH_RAW_MODE */
514	/** Inhibit interrupts pending. See EMGetInhibitInterruptsPC(). */
515	#define VMCPU_FF_INHIBIT_INTERRUPTS RT_BIT_64(VMCPU_FF_INHIBIT_INTERRUPTS_BIT)
516	#define VMCPU_FF_INHIBIT_INTERRUPTS_BIT 24
517	/** Block injection of non-maskable interrupts to the guest. */
518	#define VMCPU_FF_BLOCK_NMIS RT_BIT_64(VMCPU_FF_BLOCK_NMIS_BIT)
519	#define VMCPU_FF_BLOCK_NMIS_BIT 25
520	#ifdef VBOX_WITH_RAW_MODE
521	/** CSAM needs to scan the page that's being executed */
522	# define VMCPU_FF_CSAM_SCAN_PAGE RT_BIT_64(VMCPU_FF_CSAM_SCAN_PAGE_BIT)
523	# define VMCPU_FF_CSAM_SCAN_PAGE_BIT 26
524	/** CSAM needs to do some homework. */
525	# define VMCPU_FF_CSAM_PENDING_ACTION RT_BIT_64(VMCPU_FF_CSAM_PENDING_ACTION_BIT)
526	# define VMCPU_FF_CSAM_PENDING_ACTION_BIT 27
527	#endif /* VBOX_WITH_RAW_MODE */
528	/** Force return to Ring-3. */
529	#define VMCPU_FF_TO_R3 RT_BIT_64(VMCPU_FF_TO_R3_BIT)
530	#define VMCPU_FF_TO_R3_BIT 28
531	/** Force return to ring-3 to service pending I/O or MMIO write.
532	* This is a backup for mechanism VINF_IOM_R3_IOPORT_COMMIT_WRITE and
533	* VINF_IOM_R3_MMIO_COMMIT_WRITE, allowing VINF_EM_DBG_BREAKPOINT and similar
534	* status codes to be propagated at the same time without loss. */
535	#define VMCPU_FF_IOM RT_BIT_64(VMCPU_FF_IOM_BIT)
536	#define VMCPU_FF_IOM_BIT 29
537	#ifdef VBOX_WITH_RAW_MODE
538	/** CPUM need to adjust CR0.TS/EM before executing raw-mode code again. */
539	# define VMCPU_FF_CPUM RT_BIT_64(VMCPU_FF_CPUM_BIT)
540	/** The bit number for VMCPU_FF_CPUM. */
541	# define VMCPU_FF_CPUM_BIT 30
542	#endif /* VBOX_WITH_RAW_MODE */
543	/** Hardware virtualized nested-guest interrupt pending. */
544	#define VMCPU_FF_INTERRUPT_NESTED_GUEST RT_BIT_64(VMCPU_FF_INTERRUPT_NESTED_GUEST_BIT)
545	#define VMCPU_FF_INTERRUPT_NESTED_GUEST_BIT 31
546	/** VMX-preemption timer in effect. */
547	#define VMCPU_FF_VMX_PREEMPT_TIMER RT_BIT_64(VMCPU_FF_VMX_PREEMPT_TIMER_BIT)
548	#define VMCPU_FF_VMX_PREEMPT_TIMER_BIT 32
549	/** Pending MTF (Monitor Trap Flag) event. */
550	#define VMCPU_FF_VMX_MTF RT_BIT_64(VMCPU_FF_VMX_MTF_BIT)
551	#define VMCPU_FF_VMX_MTF_BIT 33
552	/** VMX APIC-write emulation pending. */
553	#define VMCPU_FF_VMX_APIC_WRITE RT_BIT_64(VMCPU_FF_VMX_APIC_WRITE_BIT)
554	#define VMCPU_FF_VMX_APIC_WRITE_BIT 34
555
556
557	/** Externally VM forced actions. Used to quit the idle/wait loop. */
558	#define VM_FF_EXTERNAL_SUSPENDED_MASK ( VM_FF_CHECK_VM_STATE \| VM_FF_DBGF \| VM_FF_REQUEST \| VM_FF_EMT_RENDEZVOUS )
559	/** Externally VMCPU forced actions. Used to quit the idle/wait loop. */
560	#define VMCPU_FF_EXTERNAL_SUSPENDED_MASK ( VMCPU_FF_REQUEST \| VMCPU_FF_DBGF )
561
562	/** Externally forced VM actions. Used to quit the idle/wait loop. */
563	#define VM_FF_EXTERNAL_HALTED_MASK ( VM_FF_CHECK_VM_STATE \| VM_FF_DBGF \| VM_FF_REQUEST \
564	\| VM_FF_PDM_QUEUES \| VM_FF_PDM_DMA \| VM_FF_EMT_RENDEZVOUS )
565	/** Externally forced VMCPU actions. Used to quit the idle/wait loop. */
566	#define VMCPU_FF_EXTERNAL_HALTED_MASK ( VMCPU_FF_UPDATE_APIC \| VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC \
567	\| VMCPU_FF_REQUEST \| VMCPU_FF_INTERRUPT_NMI \| VMCPU_FF_INTERRUPT_SMI \
568	\| VMCPU_FF_UNHALT \| VMCPU_FF_TIMER \| VMCPU_FF_DBGF \
569	\| VMCPU_FF_INTERRUPT_NESTED_GUEST)
570
571	/** High priority VM pre-execution actions. */
572	#define VM_FF_HIGH_PRIORITY_PRE_MASK ( VM_FF_CHECK_VM_STATE \| VM_FF_DBGF \| VM_FF_TM_VIRTUAL_SYNC \
573	\| VM_FF_DEBUG_SUSPEND \| VM_FF_PGM_NEED_HANDY_PAGES \| VM_FF_PGM_NO_MEMORY \
574	\| VM_FF_EMT_RENDEZVOUS )
575	/** High priority VMCPU pre-execution actions. */
576	#define VMCPU_FF_HIGH_PRIORITY_PRE_MASK ( VMCPU_FF_TIMER \| VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC \
577	\| VMCPU_FF_UPDATE_APIC \| VMCPU_FF_INHIBIT_INTERRUPTS \| VMCPU_FF_DBGF \
578	\| VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL \
579	\| VM_WHEN_RAW_MODE( VMCPU_FF_SELM_SYNC_TSS \| VMCPU_FF_TRPM_SYNC_IDT \
580	\| VMCPU_FF_SELM_SYNC_GDT \| VMCPU_FF_SELM_SYNC_LDT, 0 ) )
581
582	/** High priority VM pre raw-mode execution mask. */
583	#define VM_FF_HIGH_PRIORITY_PRE_RAW_MASK ( VM_FF_PGM_NEED_HANDY_PAGES \| VM_FF_PGM_NO_MEMORY )
584	/** High priority VMCPU pre raw-mode execution mask. */
585	#define VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK ( VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL \
586	\| VMCPU_FF_INHIBIT_INTERRUPTS \
587	\| VM_WHEN_RAW_MODE( VMCPU_FF_SELM_SYNC_TSS \| VMCPU_FF_TRPM_SYNC_IDT \
588	\| VMCPU_FF_SELM_SYNC_GDT \| VMCPU_FF_SELM_SYNC_LDT, 0) )
589
590	/** High priority post-execution actions. */
591	#define VM_FF_HIGH_PRIORITY_POST_MASK ( VM_FF_PGM_NO_MEMORY )
592	/** High priority post-execution actions. */
593	#define VMCPU_FF_HIGH_PRIORITY_POST_MASK ( VMCPU_FF_PDM_CRITSECT \| VM_WHEN_RAW_MODE(VMCPU_FF_CSAM_PENDING_ACTION, 0) \
594	\| VMCPU_FF_HM_UPDATE_CR3 \| VMCPU_FF_HM_UPDATE_PAE_PDPES \
595	\| VMCPU_FF_IEM \| VMCPU_FF_IOM )
596
597	/** Normal priority VM post-execution actions. */
598	#define VM_FF_NORMAL_PRIORITY_POST_MASK ( VM_FF_CHECK_VM_STATE \| VM_FF_DBGF \| VM_FF_RESET \
599	\| VM_FF_PGM_NO_MEMORY \| VM_FF_EMT_RENDEZVOUS)
600	/** Normal priority VMCPU post-execution actions. */
601	#define VMCPU_FF_NORMAL_PRIORITY_POST_MASK ( VM_WHEN_RAW_MODE(VMCPU_FF_CSAM_SCAN_PAGE, 0) \| VMCPU_FF_DBGF )
602
603	/** Normal priority VM actions. */
604	#define VM_FF_NORMAL_PRIORITY_MASK ( VM_FF_REQUEST \| VM_FF_PDM_QUEUES \| VM_FF_PDM_DMA \
605	\| VM_FF_REM_HANDLER_NOTIFY \| VM_FF_EMT_RENDEZVOUS)
606	/** Normal priority VMCPU actions. */
607	#define VMCPU_FF_NORMAL_PRIORITY_MASK ( VMCPU_FF_REQUEST )
608
609	/** Flags to clear before resuming guest execution. */
610	#define VMCPU_FF_RESUME_GUEST_MASK ( VMCPU_FF_TO_R3 )
611
612
613	/** VM flags that cause the REP[\|NE\|E] STRINS loops to yield immediately. */
614	#define VM_FF_HIGH_PRIORITY_POST_REPSTR_MASK ( VM_FF_TM_VIRTUAL_SYNC \| VM_FF_PGM_NEED_HANDY_PAGES \| VM_FF_PGM_NO_MEMORY \
615	\| VM_FF_EMT_RENDEZVOUS \| VM_FF_PGM_POOL_FLUSH_PENDING \| VM_FF_RESET)
616	/** VM flags that cause the REP[\|NE\|E] STRINS loops to yield. */
617	#define VM_FF_YIELD_REPSTR_MASK ( VM_FF_HIGH_PRIORITY_POST_REPSTR_MASK \
618	\| VM_FF_PDM_QUEUES \| VM_FF_PDM_DMA \| VM_FF_DBGF \| VM_FF_DEBUG_SUSPEND )
619	/** VMCPU flags that cause the REP[\|NE\|E] STRINS loops to yield immediately. */
620	#ifdef IN_RING3
621	# define VMCPU_FF_HIGH_PRIORITY_POST_REPSTR_MASK ( VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL \| VMCPU_FF_DBGF )
622	#else
623	# define VMCPU_FF_HIGH_PRIORITY_POST_REPSTR_MASK ( VMCPU_FF_TO_R3 \| VMCPU_FF_IEM \| VMCPU_FF_IOM \| VMCPU_FF_PGM_SYNC_CR3 \
624	\| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL \| VMCPU_FF_DBGF )
625	#endif
626	/** VMCPU flags that cause the REP[\|NE\|E] STRINS loops to yield, interrupts
627	* enabled. */
628	#define VMCPU_FF_YIELD_REPSTR_MASK ( VMCPU_FF_HIGH_PRIORITY_POST_REPSTR_MASK \
629	\| VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_UPDATE_APIC \| VMCPU_FF_INTERRUPT_PIC \
630	\| VMCPU_FF_INTERRUPT_NMI \| VMCPU_FF_INTERRUPT_SMI \| VMCPU_FF_PDM_CRITSECT \
631	\| VMCPU_FF_TIMER \| VMCPU_FF_REQUEST )
632	/** VMCPU flags that cause the REP[\|NE\|E] STRINS loops to yield, interrupts
633	* disabled. */
634	#define VMCPU_FF_YIELD_REPSTR_NOINT_MASK ( VMCPU_FF_YIELD_REPSTR_MASK \
635	& ~(VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_UPDATE_APIC \| VMCPU_FF_INTERRUPT_PIC) )
636
637	/** VM Flags that cause the HM loops to go back to ring-3. */
638	#define VM_FF_HM_TO_R3_MASK ( VM_FF_TM_VIRTUAL_SYNC \| VM_FF_PGM_NEED_HANDY_PAGES \| VM_FF_PGM_NO_MEMORY \
639	\| VM_FF_PDM_QUEUES \| VM_FF_EMT_RENDEZVOUS)
640	/** VMCPU Flags that cause the HM loops to go back to ring-3. */
641	#define VMCPU_FF_HM_TO_R3_MASK ( VMCPU_FF_TO_R3 \| VMCPU_FF_TIMER \| VMCPU_FF_PDM_CRITSECT \
642	\| VMCPU_FF_IEM \| VMCPU_FF_IOM)
643
644	/** High priority ring-0 VM pre HM-mode execution mask. */
645	#define VM_FF_HP_R0_PRE_HM_MASK (VM_FF_HM_TO_R3_MASK \| VM_FF_REQUEST \| VM_FF_PGM_POOL_FLUSH_PENDING \| VM_FF_PDM_DMA)
646	/** High priority ring-0 VMCPU pre HM-mode execution mask. */
647	#define VMCPU_FF_HP_R0_PRE_HM_MASK ( VMCPU_FF_HM_TO_R3_MASK \| VMCPU_FF_PGM_SYNC_CR3 \
648	\| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL \| VMCPU_FF_REQUEST)
649	/** High priority ring-0 VM pre HM-mode execution mask, single stepping. */
650	#define VM_FF_HP_R0_PRE_HM_STEP_MASK (VM_FF_HP_R0_PRE_HM_MASK & ~( VM_FF_TM_VIRTUAL_SYNC \| VM_FF_PDM_QUEUES \
651	\| VM_FF_EMT_RENDEZVOUS \| VM_FF_REQUEST \
652	\| VM_FF_PDM_DMA) )
653	/** High priority ring-0 VMCPU pre HM-mode execution mask, single stepping. */
654	#define VMCPU_FF_HP_R0_PRE_HM_STEP_MASK (VMCPU_FF_HP_R0_PRE_HM_MASK & ~( VMCPU_FF_TO_R3 \| VMCPU_FF_TIMER \
655	\| VMCPU_FF_PDM_CRITSECT \| VMCPU_FF_REQUEST) )
656
657	/** All the forced VM flags. */
658	#define VM_FF_ALL_MASK (UINT32_MAX)
659	/** All the forced VMCPU flags. */
660	#define VMCPU_FF_ALL_MASK (UINT32_MAX)
661
662	/** All the forced VM flags except those related to raw-mode and hardware
663	* assisted execution. */
664	#define VM_FF_ALL_REM_MASK (~(VM_FF_HIGH_PRIORITY_PRE_RAW_MASK) \| VM_FF_PGM_NEED_HANDY_PAGES \| VM_FF_PGM_NO_MEMORY)
665	/** All the forced VMCPU flags except those related to raw-mode and hardware
666	* assisted execution. */
667	#define VMCPU_FF_ALL_REM_MASK (~( VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK \| VMCPU_FF_PDM_CRITSECT \
668	\| VMCPU_FF_TLB_FLUSH \| VM_WHEN_RAW_MODE(VMCPU_FF_CSAM_PENDING_ACTION, 0) ))
669	/** @} */
670
671	/** @def VM_FF_SET
672	* Sets a single force action flag.
673	*
674	* @param pVM The cross context VM structure.
675	* @param fFlag The flag to set.
676	*/
677	#define VM_FF_SET(pVM, fFlag) do { \
678	AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
679	AssertCompile((fFlag) == RT_BIT_32(fFlag##_BIT)); \
680	ASMAtomicOrU32(&(pVM)->fGlobalForcedActions, (fFlag)); \
681	} while (0)
682
683	/** @def VMCPU_FF_SET
684	* Sets a single force action flag for the given VCPU.
685	*
686	* @param pVCpu The cross context virtual CPU structure.
687	* @param fFlag The flag to set.
688	* @sa VMCPU_FF_SET_MASK
689	*/
690	#ifdef VMCPU_WITH_64_BIT_FFS
691	# define VMCPU_FF_SET(pVCpu, fFlag) do { \
692	AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
693	AssertCompile((fFlag) == RT_BIT_64(fFlag##_BIT)); \
694	ASMAtomicBitSet(&(pVCpu)->fLocalForcedActions, fFlag##_BIT); \
695	} while (0)
696	#else
697	# define VMCPU_FF_SET(pVCpu, fFlag) do { \
698	AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
699	AssertCompile((fFlag) == RT_BIT_32(fFlag##_BIT)); \
700	ASMAtomicOrU32(&(pVCpu)->fLocalForcedActions, (fFlag)); \
701	} while (0)
702	#endif
703
704	/** @def VMCPU_FF_SET_MASK
705	* Sets a two or more force action flag for the given VCPU.
706	*
707	* @param pVCpu The cross context virtual CPU structure.
708	* @param fFlags The flags to set.
709	* @sa VMCPU_FF_SET
710	*/
711	#ifdef VMCPU_WITH_64_BIT_FFS
712	# if ARCH_BITS > 32
713	# define VMCPU_FF_SET_MASK(pVCpu, fFlags) \
714	do { ASMAtomicOrU64(&pVCpu->fLocalForcedActions, (fFlags)); } while (0)
715	# else
716	# define VMCPU_FF_SET_MASK(pVCpu, fFlags) do { \
717	if (!((fFlags) >> 32)) ASMAtomicOrU32((uint32_t volatile *)&pVCpu->fLocalForcedActions, (uint32_t)(fFlags)); \
718	else ASMAtomicOrU64(&pVCpu->fLocalForcedActions, (fFlags)); \
719	} while (0)
720	# endif
721	#else
722	# define VMCPU_FF_SET_MASK(pVCpu, fFlags) \
723	do { ASMAtomicOrU32(&pVCpu->fLocalForcedActions, (fFlags)); } while (0)
724	#endif
725
726	/** @def VM_FF_CLEAR
727	* Clears a single force action flag.
728	*
729	* @param pVM The cross context VM structure.
730	* @param fFlag The flag to clear.
731	*/
732	#define VM_FF_CLEAR(pVM, fFlag) do { \
733	AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
734	AssertCompile((fFlag) == RT_BIT_32(fFlag##_BIT)); \
735	ASMAtomicAndU32(&(pVM)->fGlobalForcedActions, ~(fFlag)); \
736	} while (0)
737
738	/** @def VMCPU_FF_CLEAR
739	* Clears a single force action flag for the given VCPU.
740	*
741	* @param pVCpu The cross context virtual CPU structure.
742	* @param fFlag The flag to clear.
743	*/
744	#ifdef VMCPU_WITH_64_BIT_FFS
745	# define VMCPU_FF_CLEAR(pVCpu, fFlag) do { \
746	AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
747	AssertCompile((fFlag) == RT_BIT_64(fFlag##_BIT)); \
748	ASMAtomicBitClear(&(pVCpu)->fLocalForcedActions, fFlag##_BIT); \
749	} while (0)
750	#else
751	# define VMCPU_FF_CLEAR(pVCpu, fFlag) do { \
752	AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
753	AssertCompile((fFlag) == RT_BIT_32(fFlag##_BIT)); \
754	ASMAtomicAndU32(&(pVCpu)->fLocalForcedActions, ~(fFlag)); \
755	} while (0)
756	#endif
757
758	/** @def VMCPU_FF_CLEAR_MASK
759	* Clears two or more force action flags for the given VCPU.
760	*
761	* @param pVCpu The cross context virtual CPU structure.
762	* @param fFlags The flags to clear.
763	*/
764	#ifdef VMCPU_WITH_64_BIT_FFS
765	# if ARCH_BITS > 32
766	# define VMCPU_FF_CLEAR_MASK(pVCpu, fFlags) \
767	do { ASMAtomicAndU64(&(pVCpu)->fLocalForcedActions, ~(fFlags)); } while (0)
768	# else
769	# define VMCPU_FF_CLEAR_MASK(pVCpu, fFlags) do { \
770	if (!((fFlags) >> 32)) ASMAtomicAndU32((uint32_t volatile *)&(pVCpu)->fLocalForcedActions, ~(uint32_t)(fFlags)); \
771	else ASMAtomicAndU64(&(pVCpu)->fLocalForcedActions, ~(fFlags)); \
772	} while (0)
773	# endif
774	#else
775	# define VMCPU_FF_CLEAR_MASK(pVCpu, fFlags) \
776	do { ASMAtomicAndU32(&(pVCpu)->fLocalForcedActions, ~(fFlags)); } while (0)
777	#endif
778
779	/** @def VM_FF_IS_SET
780	* Checks if single a force action flag is set.
781	*
782	* @param pVM The cross context VM structure.
783	* @param fFlag The flag to check.
784	* @sa VM_FF_IS_ANY_SET
785	*/
786	#if !defined(VBOX_STRICT) \|\| !defined(RT_COMPILER_SUPPORTS_LAMBDA)
787	# define VM_FF_IS_SET(pVM, fFlag) RT_BOOL((pVM)->fGlobalForcedActions & (fFlag))
788	#else
789	# define VM_FF_IS_SET(pVM, fFlag) \
790	([](PVM a_pVM) -> bool \
791	{ \
792	AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
793	AssertCompile((fFlag) == RT_BIT_32(fFlag##_BIT)); \
794	return RT_BOOL(a_pVM->fGlobalForcedActions & (fFlag)); \
795	}(pVM))
796	#endif
797
798	/** @def VMCPU_FF_IS_SET
799	* Checks if a single force action flag is set for the given VCPU.
800	*
801	* @param pVCpu The cross context virtual CPU structure.
802	* @param fFlag The flag to check.
803	* @sa VMCPU_FF_IS_ANY_SET
804	*/
805	#if !defined(VBOX_STRICT) \|\| !defined(RT_COMPILER_SUPPORTS_LAMBDA)
806	# define VMCPU_FF_IS_SET(pVCpu, fFlag) RT_BOOL((pVCpu)->fLocalForcedActions & (fFlag))
807	#else
808	# define VMCPU_FF_IS_SET(pVCpu, fFlag) \
809	([](PVMCPU a_pVCpu) -> bool \
810	{ \
811	AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
812	AssertCompile((fFlag) == RT_BIT_64(fFlag##_BIT)); \
813	return RT_BOOL(a_pVCpu->fLocalForcedActions & (fFlag)); \
814	}(pVCpu))
815	#endif
816
817	/** @def VM_FF_IS_ANY_SET
818	* Checks if one or more force action in the specified set is pending.
819	*
820	* @param pVM The cross context VM structure.
821	* @param fFlags The flags to check for.
822	* @sa VM_FF_IS_SET
823	*/
824	#define VM_FF_IS_ANY_SET(pVM, fFlags) RT_BOOL((pVM)->fGlobalForcedActions & (fFlags))
825
826	/** @def VMCPU_FF_IS_ANY_SET
827	* Checks if two or more force action flags in the specified set is set for the given VCPU.
828	*
829	* @param pVCpu The cross context virtual CPU structure.
830	* @param fFlags The flags to check for.
831	* @sa VMCPU_FF_IS_SET
832	*/
833	#define VMCPU_FF_IS_ANY_SET(pVCpu, fFlags) RT_BOOL((pVCpu)->fLocalForcedActions & (fFlags))
834
835	/** @def VM_FF_TEST_AND_CLEAR
836	* Checks if one (!) force action in the specified set is pending and clears it atomically
837	*
838	* @returns true if the bit was set.
839	* @returns false if the bit was clear.
840	* @param pVM The cross context VM structure.
841	* @param fFlag Flag constant to check and clear (_BIT is appended).
842	*/
843	#define VM_FF_TEST_AND_CLEAR(pVM, fFlag) (ASMAtomicBitTestAndClear(&(pVM)->fGlobalForcedActions, fFlag##_BIT))
844
845	/** @def VMCPU_FF_TEST_AND_CLEAR
846	* Checks if one (!) force action in the specified set is pending and clears it atomically
847	*
848	* @returns true if the bit was set.
849	* @returns false if the bit was clear.
850	* @param pVCpu The cross context virtual CPU structure.
851	* @param fFlag Flag constant to check and clear (_BIT is appended).
852	*/
853	#define VMCPU_FF_TEST_AND_CLEAR(pVCpu, fFlag) (ASMAtomicBitTestAndClear(&(pVCpu)->fLocalForcedActions, fFlag##_BIT))
854
855	/** @def VM_FF_IS_PENDING_EXCEPT
856	* Checks if one or more force action in the specified set is pending while one
857	* or more other ones are not.
858	*
859	* @param pVM The cross context VM structure.
860	* @param fFlags The flags to check for.
861	* @param fExcpt The flags that should not be set.
862	*/
863	#define VM_FF_IS_PENDING_EXCEPT(pVM, fFlags, fExcpt) \
864	( ((pVM)->fGlobalForcedActions & (fFlags)) && !((pVM)->fGlobalForcedActions & (fExcpt)) )
865
866	/** @def VM_IS_EMT
867	* Checks if the current thread is the emulation thread (EMT).
868	*
869	* @remark The ring-0 variation will need attention if we expand the ring-0
870	* code to let threads other than EMT mess around with the VM.
871	*/
872	#ifdef IN_RC
873	# define VM_IS_EMT(pVM) true
874	#else
875	# define VM_IS_EMT(pVM) (VMMGetCpu(pVM) != NULL)
876	#endif
877
878	/** @def VMCPU_IS_EMT
879	* Checks if the current thread is the emulation thread (EMT) for the specified
880	* virtual CPU.
881	*/
882	#ifdef IN_RC
883	# define VMCPU_IS_EMT(pVCpu) true
884	#else
885	# define VMCPU_IS_EMT(pVCpu) ((pVCpu) && ((pVCpu) == VMMGetCpu((pVCpu)->CTX_SUFF(pVM))))
886	#endif
887
888	/** @def VM_ASSERT_EMT
889	* Asserts that the current thread IS the emulation thread (EMT).
890	*/
891	#ifdef IN_RC
892	# define VM_ASSERT_EMT(pVM) Assert(VM_IS_EMT(pVM))
893	#elif defined(IN_RING0)
894	# define VM_ASSERT_EMT(pVM) Assert(VM_IS_EMT(pVM))
895	#else
896	# define VM_ASSERT_EMT(pVM) \
897	AssertMsg(VM_IS_EMT(pVM), \
898	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd\n", RTThreadNativeSelf(), VMR3GetVMCPUNativeThread(pVM)))
899	#endif
900
901	/** @def VMCPU_ASSERT_EMT
902	* Asserts that the current thread IS the emulation thread (EMT) of the
903	* specified virtual CPU.
904	*/
905	#ifdef IN_RC
906	# define VMCPU_ASSERT_EMT(pVCpu) Assert(VMCPU_IS_EMT(pVCpu))
907	#elif defined(IN_RING0)
908	# define VMCPU_ASSERT_EMT(pVCpu) AssertMsg(VMCPU_IS_EMT(pVCpu), \
909	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd idCpu=%u\n", \
910	RTThreadNativeSelf(), (pVCpu) ? (pVCpu)->hNativeThreadR0 : 0, \
911	(pVCpu) ? (pVCpu)->idCpu : 0))
912	#else
913	# define VMCPU_ASSERT_EMT(pVCpu) AssertMsg(VMCPU_IS_EMT(pVCpu), \
914	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd idCpu=%#x\n", \
915	RTThreadNativeSelf(), (pVCpu)->hNativeThread, (pVCpu)->idCpu))
916	#endif
917
918	/** @def VM_ASSERT_EMT_RETURN
919	* Asserts that the current thread IS the emulation thread (EMT) and returns if it isn't.
920	*/
921	#ifdef IN_RC
922	# define VM_ASSERT_EMT_RETURN(pVM, rc) AssertReturn(VM_IS_EMT(pVM), (rc))
923	#elif defined(IN_RING0)
924	# define VM_ASSERT_EMT_RETURN(pVM, rc) AssertReturn(VM_IS_EMT(pVM), (rc))
925	#else
926	# define VM_ASSERT_EMT_RETURN(pVM, rc) \
927	AssertMsgReturn(VM_IS_EMT(pVM), \
928	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd\n", RTThreadNativeSelf(), VMR3GetVMCPUNativeThread(pVM)), \
929	(rc))
930	#endif
931
932	/** @def VMCPU_ASSERT_EMT_RETURN
933	* Asserts that the current thread IS the emulation thread (EMT) and returns if it isn't.
934	*/
935	#ifdef IN_RC
936	# define VMCPU_ASSERT_EMT_RETURN(pVCpu, rc) AssertReturn(VMCPU_IS_EMT(pVCpu), (rc))
937	#elif defined(IN_RING0)
938	# define VMCPU_ASSERT_EMT_RETURN(pVCpu, rc) AssertReturn(VMCPU_IS_EMT(pVCpu), (rc))
939	#else
940	# define VMCPU_ASSERT_EMT_RETURN(pVCpu, rc) \
941	AssertMsgReturn(VMCPU_IS_EMT(pVCpu), \
942	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd idCpu=%#x\n", \
943	RTThreadNativeSelf(), (pVCpu)->hNativeThread, (pVCpu)->idCpu), \
944	(rc))
945	#endif
946
947	/** @def VMCPU_ASSERT_EMT_OR_GURU
948	* Asserts that the current thread IS the emulation thread (EMT) of the
949	* specified virtual CPU.
950	*/
951	#if defined(IN_RC) \|\| defined(IN_RING0)
952	# define VMCPU_ASSERT_EMT_OR_GURU(pVCpu) Assert( VMCPU_IS_EMT(pVCpu) \
953	\|\| pVCpu->CTX_SUFF(pVM)->enmVMState == VMSTATE_GURU_MEDITATION \
954	\|\| pVCpu->CTX_SUFF(pVM)->enmVMState == VMSTATE_GURU_MEDITATION_LS )
955	#else
956	# define VMCPU_ASSERT_EMT_OR_GURU(pVCpu) \
957	AssertMsg( VMCPU_IS_EMT(pVCpu) \
958	\|\| pVCpu->CTX_SUFF(pVM)->enmVMState == VMSTATE_GURU_MEDITATION \
959	\|\| pVCpu->CTX_SUFF(pVM)->enmVMState == VMSTATE_GURU_MEDITATION_LS, \
960	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd idCpu=%#x\n", \
961	RTThreadNativeSelf(), (pVCpu)->hNativeThread, (pVCpu)->idCpu))
962	#endif
963
964	/** @def VMCPU_ASSERT_EMT_OR_NOT_RUNNING
965	* Asserts that the current thread IS the emulation thread (EMT) of the
966	* specified virtual CPU or the VM is not running.
967	*/
968	#if defined(IN_RC) \|\| defined(IN_RING0)
969	# define VMCPU_ASSERT_EMT_OR_NOT_RUNNING(pVCpu) \
970	Assert( VMCPU_IS_EMT(pVCpu) \
971	\|\| !VM_IS_RUNNING_FOR_ASSERTIONS_ONLY((pVCpu)->CTX_SUFF(pVM)) )
972	#else
973	# define VMCPU_ASSERT_EMT_OR_NOT_RUNNING(pVCpu) \
974	AssertMsg( VMCPU_IS_EMT(pVCpu) \
975	\|\| !VM_IS_RUNNING_FOR_ASSERTIONS_ONLY((pVCpu)->CTX_SUFF(pVM)), \
976	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd idCpu=%#x\n", \
977	RTThreadNativeSelf(), (pVCpu)->hNativeThread, (pVCpu)->idCpu))
978	#endif
979
980	/** @def VMSTATE_IS_RUNNING
981	* Checks if the given state indicates a running VM.
982	*/
983	#define VMSTATE_IS_RUNNING(a_enmVMState) \
984	( (enmVMState) == VMSTATE_RUNNING \
985	\|\| (enmVMState) == VMSTATE_RUNNING_LS \
986	\|\| (enmVMState) == VMSTATE_RUNNING_FT )
987
988	/** @def VM_IS_RUNNING_FOR_ASSERTIONS_ONLY
989	* Checks if the VM is running.
990	* @note This is only for pure debug assertions. No AssertReturn or similar!
991	* @sa VMSTATE_IS_RUNNING
992	*/
993	#define VM_IS_RUNNING_FOR_ASSERTIONS_ONLY(pVM) \
994	( (pVM)->enmVMState == VMSTATE_RUNNING \
995	\|\| (pVM)->enmVMState == VMSTATE_RUNNING_LS \
996	\|\| (pVM)->enmVMState == VMSTATE_RUNNING_FT )
997
998	/** @def VM_ASSERT_IS_NOT_RUNNING
999	* Asserts that the VM is not running.
1000	*/
1001	#if defined(IN_RC) \|\| defined(IN_RING0)
1002	#define VM_ASSERT_IS_NOT_RUNNING(pVM) Assert(!VM_IS_RUNNING_FOR_ASSERTIONS_ONLY(pVM))
1003	#else
1004	#define VM_ASSERT_IS_NOT_RUNNING(pVM) AssertMsg(!VM_IS_RUNNING_FOR_ASSERTIONS_ONLY(pVM), \
1005	("VM is running. enmVMState=%d\n", (pVM)->enmVMState))
1006	#endif
1007
1008	/** @def VM_ASSERT_EMT0
1009	* Asserts that the current thread IS emulation thread \#0 (EMT0).
1010	*/
1011	#define VM_ASSERT_EMT0(pVM) VMCPU_ASSERT_EMT(&(pVM)->aCpus[0])
1012
1013	/** @def VM_ASSERT_EMT0_RETURN
1014	* Asserts that the current thread IS emulation thread \#0 (EMT0) and returns if
1015	* it isn't.
1016	*/
1017	#define VM_ASSERT_EMT0_RETURN(pVM, rc) VMCPU_ASSERT_EMT_RETURN(&(pVM)->aCpus[0], (rc))
1018
1019
1020	/**
1021	* Asserts that the current thread is NOT the emulation thread.
1022	*/
1023	#define VM_ASSERT_OTHER_THREAD(pVM) \
1024	AssertMsg(!VM_IS_EMT(pVM), ("Not other thread!!\n"))
1025
1026
1027	/** @def VM_ASSERT_STATE
1028	* Asserts a certain VM state.
1029	*/
1030	#define VM_ASSERT_STATE(pVM, _enmState) \
1031	AssertMsg((pVM)->enmVMState == (_enmState), \
1032	("state %s, expected %s\n", VMGetStateName((pVM)->enmVMState), VMGetStateName(_enmState)))
1033
1034	/** @def VM_ASSERT_STATE_RETURN
1035	* Asserts a certain VM state and returns if it doesn't match.
1036	*/
1037	#define VM_ASSERT_STATE_RETURN(pVM, _enmState, rc) \
1038	AssertMsgReturn((pVM)->enmVMState == (_enmState), \
1039	("state %s, expected %s\n", VMGetStateName((pVM)->enmVMState), VMGetStateName(_enmState)), \
1040	(rc))
1041
1042	/** @def VM_IS_VALID_EXT
1043	* Asserts a the VM handle is valid for external access, i.e. not being destroy
1044	* or terminated. */
1045	#define VM_IS_VALID_EXT(pVM) \
1046	( RT_VALID_ALIGNED_PTR(pVM, PAGE_SIZE) \
1047	&& ( (unsigned)(pVM)->enmVMState < (unsigned)VMSTATE_DESTROYING \
1048	\|\| ( (unsigned)(pVM)->enmVMState == (unsigned)VMSTATE_DESTROYING \
1049	&& VM_IS_EMT(pVM))) )
1050
1051	/** @def VM_ASSERT_VALID_EXT_RETURN
1052	* Asserts a the VM handle is valid for external access, i.e. not being
1053	* destroy or terminated.
1054	*/
1055	#define VM_ASSERT_VALID_EXT_RETURN(pVM, rc) \
1056	AssertMsgReturn(VM_IS_VALID_EXT(pVM), \
1057	("pVM=%p state %s\n", (pVM), RT_VALID_ALIGNED_PTR(pVM, PAGE_SIZE) \
1058	? VMGetStateName(pVM->enmVMState) : ""), \
1059	(rc))
1060
1061	/** @def VMCPU_ASSERT_VALID_EXT_RETURN
1062	* Asserts a the VMCPU handle is valid for external access, i.e. not being
1063	* destroy or terminated.
1064	*/
1065	#define VMCPU_ASSERT_VALID_EXT_RETURN(pVCpu, rc) \
1066	AssertMsgReturn( RT_VALID_ALIGNED_PTR(pVCpu, 64) \
1067	&& RT_VALID_ALIGNED_PTR((pVCpu)->CTX_SUFF(pVM), PAGE_SIZE) \
1068	&& (unsigned)(pVCpu)->CTX_SUFF(pVM)->enmVMState < (unsigned)VMSTATE_DESTROYING, \
1069	("pVCpu=%p pVM=%p state %s\n", (pVCpu), RT_VALID_ALIGNED_PTR(pVCpu, 64) ? (pVCpu)->CTX_SUFF(pVM) : NULL, \
1070	RT_VALID_ALIGNED_PTR(pVCpu, 64) && RT_VALID_ALIGNED_PTR((pVCpu)->CTX_SUFF(pVM), PAGE_SIZE) \
1071	? VMGetStateName((pVCpu)->pVMR3->enmVMState) : ""), \
1072	(rc))
1073
1074	#endif /* !VBOX_FOR_DTRACE_LIB */
1075
1076
1077	/**
1078	* Helper that HM and NEM uses for safely modifying VM::bMainExecutionEngine.
1079	*
1080	* ONLY HM and NEM MAY USE THIS!
1081	*
1082	* @param a_pVM The cross context VM structure.
1083	* @param a_bValue The new value.
1084	* @internal
1085	*/
1086	#define VM_SET_MAIN_EXECUTION_ENGINE(a_pVM, a_bValue) \
1087	do { \
1088	const_cast<uint8_t >(&(a_pVM)->bMainExecutionEngine) = (a_bValue); \
1089	ASMCompilerBarrier(); /* just to be on the safe side */ \
1090	} while (0)
1091
1092	/**
1093	* Checks whether raw-mode is used.
1094	*
1095	* @retval true if either is used.
1096	* @retval false if software virtualization (raw-mode) is used.
1097	*
1098	* @param a_pVM The cross context VM structure.
1099	* @sa VM_IS_HM_OR_NEM_ENABLED, VM_IS_HM_ENABLED, VM_IS_NEM_ENABLED.
1100	* @internal
1101	*/
1102	#ifdef VBOX_WITH_RAW_MODE
1103	# define VM_IS_RAW_MODE_ENABLED(a_pVM) ((a_pVM)->bMainExecutionEngine == VM_EXEC_ENGINE_RAW_MODE)
1104	#else
1105	# define VM_IS_RAW_MODE_ENABLED(a_pVM) (false)
1106	#endif
1107
1108	/**
1109	* Checks whether HM (VT-x/AMD-V) or NEM is being used by this VM.
1110	*
1111	* @retval true if either is used.
1112	* @retval false if software virtualization (raw-mode) is used.
1113	*
1114	* @param a_pVM The cross context VM structure.
1115	* @sa VM_IS_RAW_MODE_ENABLED, VM_IS_HM_ENABLED, VM_IS_NEM_ENABLED.
1116	* @internal
1117	*/
1118	#define VM_IS_HM_OR_NEM_ENABLED(a_pVM) ((a_pVM)->bMainExecutionEngine != VM_EXEC_ENGINE_RAW_MODE)
1119
1120	/**
1121	* Checks whether HM is being used by this VM.
1122	*
1123	* @retval true if HM (VT-x/AMD-v) is used.
1124	* @retval false if not.
1125	*
1126	* @param a_pVM The cross context VM structure.
1127	* @sa VM_IS_NEM_ENABLED, VM_IS_RAW_MODE_ENABLED, VM_IS_HM_OR_NEM_ENABLED.
1128	* @internal
1129	*/
1130	#define VM_IS_HM_ENABLED(a_pVM) ((a_pVM)->bMainExecutionEngine == VM_EXEC_ENGINE_HW_VIRT)
1131
1132	/**
1133	* Checks whether NEM is being used by this VM.
1134	*
1135	* @retval true if a native hypervisor API is used.
1136	* @retval false if not.
1137	*
1138	* @param a_pVM The cross context VM structure.
1139	* @sa VM_IS_HM_ENABLED, VM_IS_RAW_MODE_ENABLED, VM_IS_HM_OR_NEM_ENABLED.
1140	* @internal
1141	*/
1142	#define VM_IS_NEM_ENABLED(a_pVM) ((a_pVM)->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API)
1143
1144
1145	/**
1146	* The cross context VM structure.
1147	*
1148	* It contains all the VM data which have to be available in all contexts.
1149	* Even if it contains all the data the idea is to use APIs not to modify all
1150	* the members all around the place. Therefore we make use of unions to hide
1151	* everything which isn't local to the current source module. This means we'll
1152	* have to pay a little bit of attention when adding new members to structures
1153	* in the unions and make sure to keep the padding sizes up to date.
1154	*
1155	* Run 'kmk run-struct-tests' (from src/VBox/VMM if you like) after updating!
1156	*/
1157	typedef struct VM
1158	{
1159	/** The state of the VM.
1160	* This field is read only to everyone except the VM and EM. */
1161	VMSTATE volatile enmVMState;
1162	/** Forced action flags.
1163	* See the VM_FF_* \#defines. Updated atomically.
1164	*/
1165	volatile uint32_t fGlobalForcedActions;
1166	/** Pointer to the array of page descriptors for the VM structure allocation. */
1167	R3PTRTYPE(PSUPPAGE) paVMPagesR3;
1168	/** Session handle. For use when calling SUPR0 APIs. */
1169	PSUPDRVSESSION pSession;
1170	/** Pointer to the ring-3 VM structure. */
1171	PUVM pUVM;
1172	/** Ring-3 Host Context VM Pointer. */
1173	R3PTRTYPE(struct VM *) pVMR3;
1174	/** Ring-0 Host Context VM Pointer. */
1175	R0PTRTYPE(struct VM *) pVMR0;
1176	/** Raw-mode Context VM Pointer. */
1177	RCPTRTYPE(struct VM *) pVMRC;
1178
1179	/** The GVM VM handle. Only the GVM should modify this field. */
1180	uint32_t hSelf;
1181	/** Number of virtual CPUs. */
1182	uint32_t cCpus;
1183	/** CPU excution cap (1-100) */
1184	uint32_t uCpuExecutionCap;
1185
1186	/** Size of the VM structure including the VMCPU array. */
1187	uint32_t cbSelf;
1188
1189	/** Offset to the VMCPU array starting from beginning of this structure. */
1190	uint32_t offVMCPU;
1191
1192	/**
1193	* VMMSwitcher assembly entry point returning to host context.
1194	*
1195	* Depending on how the host handles the rc status given in @a eax, this may
1196	* return and let the caller resume whatever it was doing prior to the call.
1197	*
1198	*
1199	* @param eax The return code, register.
1200	* @remark Assume interrupts disabled.
1201	* @remark This method pointer lives here because TRPM needs it.
1202	*/
1203	RTRCPTR pfnVMMRCToHostAsm/(int32_t eax)/;
1204
1205	/**
1206	* VMMSwitcher assembly entry point returning to host context without saving the
1207	* raw-mode context (hyper) registers.
1208	*
1209	* Unlike pfnVMMRC2HCAsm, this will not return to the caller. Instead it
1210	* expects the caller to save a RC context in CPUM where one might return if the
1211	* return code indicate that this is possible.
1212	*
1213	* This method pointer lives here because TRPM needs it.
1214	*
1215	* @param eax The return code, register.
1216	* @remark Assume interrupts disabled.
1217	* @remark This method pointer lives here because TRPM needs it.
1218	*/
1219	RTRCPTR pfnVMMRCToHostAsmNoReturn/(int32_t eax)/;
1220
1221	/** @name Various items that are frequently accessed.
1222	* @{ */
1223	/** The main execution engine, VM_EXEC_ENGINE_XXX.
1224	* This is set early during vmR3InitRing3 by HM or NEM. */
1225	uint8_t const bMainExecutionEngine;
1226
1227	/** Whether to recompile user mode code or run it raw/hm/nem.
1228	* In non-raw-mode both fRecompileUser and fRecompileSupervisor must be set
1229	* to recompiler stuff. */
1230	bool fRecompileUser;
1231	/** Whether to recompile supervisor mode code or run it raw/hm/nem.
1232	* In non-raw-mode both fRecompileUser and fRecompileSupervisor must be set
1233	* to recompiler stuff. */
1234	bool fRecompileSupervisor;
1235	/** Whether raw mode supports ring-1 code or not.
1236	* This will be cleared when not in raw-mode. */
1237	bool fRawRing1Enabled;
1238	/** PATM enabled flag.
1239	* This is placed here for performance reasons.
1240	* This will be cleared when not in raw-mode. */
1241	bool fPATMEnabled;
1242	/** CSAM enabled flag.
1243	* This is placed here for performance reasons.
1244	* This will be cleared when not in raw-mode. */
1245	bool fCSAMEnabled;
1246
1247	/** Hardware VM support is available and enabled.
1248	* Determined very early during init.
1249	* This is placed here for performance reasons.
1250	* @todo obsoleted by bMainExecutionEngine, eliminate. */
1251	bool fHMEnabled;
1252	/** Hardware VM support requires a minimal raw-mode context.
1253	* This is never set on 64-bit hosts, only 32-bit hosts requires it. */
1254	bool fHMNeedRawModeCtx;
1255
1256	/** Set when this VM is the master FT node.
1257	* @todo This doesn't need to be here, FTM should store it in it's own
1258	* structures instead. */
1259	bool fFaultTolerantMaster;
1260	/** Large page enabled flag.
1261	* @todo This doesn't need to be here, PGM should store it in it's own
1262	* structures instead. */
1263	bool fUseLargePages;
1264	/** @} */
1265
1266	/** Alignment padding. */
1267	uint8_t uPadding1[2];
1268
1269	/** @name Debugging
1270	* @{ */
1271	/** Raw-mode Context VM Pointer. */
1272	RCPTRTYPE(RTTRACEBUF) hTraceBufRC;
1273	/** Ring-3 Host Context VM Pointer. */
1274	R3PTRTYPE(RTTRACEBUF) hTraceBufR3;
1275	/** Ring-0 Host Context VM Pointer. */
1276	R0PTRTYPE(RTTRACEBUF) hTraceBufR0;
1277	/** @} */
1278
1279	#if HC_ARCH_BITS == 32
1280	/** Alignment padding. */
1281	uint32_t uPadding2;
1282	#endif
1283
1284	/** @name Switcher statistics (remove)
1285	* @{ */
1286	/** Profiling the total time from Qemu to GC. */
1287	STAMPROFILEADV StatTotalQemuToGC;
1288	/** Profiling the total time from GC to Qemu. */
1289	STAMPROFILEADV StatTotalGCToQemu;
1290	/** Profiling the total time spent in GC. */
1291	STAMPROFILEADV StatTotalInGC;
1292	/** Profiling the total time spent not in Qemu. */
1293	STAMPROFILEADV StatTotalInQemu;
1294	/** Profiling the VMMSwitcher code for going to GC. */
1295	STAMPROFILEADV StatSwitcherToGC;
1296	/** Profiling the VMMSwitcher code for going to HC. */
1297	STAMPROFILEADV StatSwitcherToHC;
1298	STAMPROFILEADV StatSwitcherSaveRegs;
1299	STAMPROFILEADV StatSwitcherSysEnter;
1300	STAMPROFILEADV StatSwitcherDebug;
1301	STAMPROFILEADV StatSwitcherCR0;
1302	STAMPROFILEADV StatSwitcherCR4;
1303	STAMPROFILEADV StatSwitcherJmpCR3;
1304	STAMPROFILEADV StatSwitcherRstrRegs;
1305	STAMPROFILEADV StatSwitcherLgdt;
1306	STAMPROFILEADV StatSwitcherLidt;
1307	STAMPROFILEADV StatSwitcherLldt;
1308	STAMPROFILEADV StatSwitcherTSS;
1309	/** @} */
1310
1311	/** Padding - the unions must be aligned on a 64 bytes boundary and the unions
1312	* must start at the same offset on both 64-bit and 32-bit hosts. */
1313	uint8_t abAlignment3[(HC_ARCH_BITS == 32 ? 24 : 0) + 40];
1314
1315	/** CPUM part. */
1316	union
1317	{
1318	#ifdef ___CPUMInternal_h
1319	struct CPUM s;
1320	#endif
1321	#ifdef ___VBox_vmm_cpum_h
1322	/** Read only info exposed about the host and guest CPUs. */
1323	struct
1324	{
1325	/** Padding for hidden fields. */
1326	uint8_t abHidden0[64];
1327	/** Host CPU feature information. */
1328	CPUMFEATURES HostFeatures;
1329	/** Guest CPU feature information. */
1330	CPUMFEATURES GuestFeatures;
1331	} const ro;
1332	#endif
1333	uint8_t padding[1536]; /* multiple of 64 */
1334	} cpum;
1335
1336	/** VMM part. */
1337	union
1338	{
1339	#ifdef ___VMMInternal_h
1340	struct VMM s;
1341	#endif
1342	uint8_t padding[1600]; /* multiple of 64 */
1343	} vmm;
1344
1345	/** PGM part. */
1346	union
1347	{
1348	#ifdef ___PGMInternal_h
1349	struct PGM s;
1350	#endif
1351	uint8_t padding[40962+6080]; / multiple of 64 */
1352	} pgm;
1353
1354	/** HM part. */
1355	union
1356	{
1357	#ifdef ___HMInternal_h
1358	struct HM s;
1359	#endif
1360	uint8_t padding[5440]; /* multiple of 64 */
1361	} hm;
1362
1363	/** TRPM part. */
1364	union
1365	{
1366	#ifdef ___TRPMInternal_h
1367	struct TRPM s;
1368	#endif
1369	uint8_t padding[5248]; /* multiple of 64 */
1370	} trpm;
1371
1372	/** SELM part. */
1373	union
1374	{
1375	#ifdef ___SELMInternal_h
1376	struct SELM s;
1377	#endif
1378	uint8_t padding[768]; /* multiple of 64 */
1379	} selm;
1380
1381	/** MM part. */
1382	union
1383	{
1384	#ifdef ___MMInternal_h
1385	struct MM s;
1386	#endif
1387	uint8_t padding[192]; /* multiple of 64 */
1388	} mm;
1389
1390	/** PDM part. */
1391	union
1392	{
1393	#ifdef ___PDMInternal_h
1394	struct PDM s;
1395	#endif
1396	uint8_t padding[1920]; /* multiple of 64 */
1397	} pdm;
1398
1399	/** IOM part. */
1400	union
1401	{
1402	#ifdef ___IOMInternal_h
1403	struct IOM s;
1404	#endif
1405	uint8_t padding[896]; /* multiple of 64 */
1406	} iom;
1407
1408	/** EM part. */
1409	union
1410	{
1411	#ifdef ___EMInternal_h
1412	struct EM s;
1413	#endif
1414	uint8_t padding[256]; /* multiple of 64 */
1415	} em;
1416
1417	/** NEM part. */
1418	union
1419	{
1420	#ifdef ___NEMInternal_h
1421	struct NEM s;
1422	#endif
1423	uint8_t padding[128]; /* multiple of 64 */
1424	} nem;
1425
1426	/** TM part. */
1427	union
1428	{
1429	#ifdef ___TMInternal_h
1430	struct TM s;
1431	#endif
1432	uint8_t padding[2496]; /* multiple of 64 */
1433	} tm;
1434
1435	/** DBGF part. */
1436	union
1437	{
1438	#ifdef ___DBGFInternal_h
1439	struct DBGF s;
1440	#endif
1441	#ifdef ___VBox_vmm_dbgf_h
1442	/** Read only info exposed about interrupt breakpoints and selected events. */
1443	struct
1444	{
1445	/** Bitmap of enabled hardware interrupt breakpoints. */
1446	uint32_t bmHardIntBreakpoints[256 / 32];
1447	/** Bitmap of enabled software interrupt breakpoints. */
1448	uint32_t bmSoftIntBreakpoints[256 / 32];
1449	/** Bitmap of selected events.
1450	* This includes non-selectable events too for simplicity, we maintain the
1451	* state for some of these, as it may come in handy. */
1452	uint64_t bmSelectedEvents[(DBGFEVENT_END + 63) / 64];
1453	/** Enabled hardware interrupt breakpoints. */
1454	uint32_t cHardIntBreakpoints;
1455	/** Enabled software interrupt breakpoints. */
1456	uint32_t cSoftIntBreakpoints;
1457	/** The number of selected events. */
1458	uint32_t cSelectedEvents;
1459	/** The number of enabled hardware breakpoints. */
1460	uint8_t cEnabledHwBreakpoints;
1461	/** The number of enabled hardware I/O breakpoints. */
1462	uint8_t cEnabledHwIoBreakpoints;
1463	/** The number of enabled INT3 breakpoints. */
1464	uint8_t cEnabledInt3Breakpoints;
1465	uint8_t abPadding[1]; /*< Unused padding space up for grabs. /
1466	} const ro;
1467	#endif
1468	uint8_t padding[2432]; /* multiple of 64 */
1469	} dbgf;
1470
1471	/** SSM part. */
1472	union
1473	{
1474	#ifdef ___SSMInternal_h
1475	struct SSM s;
1476	#endif
1477	uint8_t padding[128]; /* multiple of 64 */
1478	} ssm;
1479
1480	/** FTM part. */
1481	union
1482	{
1483	#ifdef ___FTMInternal_h
1484	struct FTM s;
1485	#endif
1486	uint8_t padding[512]; /* multiple of 64 */
1487	} ftm;
1488
1489	#ifdef VBOX_WITH_RAW_MODE
1490	/** PATM part. */
1491	union
1492	{
1493	# ifdef ___PATMInternal_h
1494	struct PATM s;
1495	# endif
1496	uint8_t padding[768]; /* multiple of 64 */
1497	} patm;
1498
1499	/** CSAM part. */
1500	union
1501	{
1502	# ifdef ___CSAMInternal_h
1503	struct CSAM s;
1504	# endif
1505	uint8_t padding[1088]; /* multiple of 64 */
1506	} csam;
1507	#endif
1508
1509	#ifdef VBOX_WITH_REM
1510	/** REM part. */
1511	union
1512	{
1513	# ifdef ___REMInternal_h
1514	struct REM s;
1515	# endif
1516	uint8_t padding[0x11100]; /* multiple of 64 */
1517	} rem;
1518	#endif
1519
1520	union
1521	{
1522	#ifdef ___GIMInternal_h
1523	struct GIM s;
1524	#endif
1525	uint8_t padding[448]; /* multiple of 64 */
1526	} gim;
1527
1528	union
1529	{
1530	#ifdef ___APICInternal_h
1531	struct APIC s;
1532	#endif
1533	uint8_t padding[128]; /* multiple of 8 */
1534	} apic;
1535
1536	/* ---- begin small stuff ---- */
1537
1538	/** VM part. */
1539	union
1540	{
1541	#ifdef ___VMInternal_h
1542	struct VMINT s;
1543	#endif
1544	uint8_t padding[32]; /* multiple of 8 */
1545	} vm;
1546
1547	/** CFGM part. */
1548	union
1549	{
1550	#ifdef ___CFGMInternal_h
1551	struct CFGM s;
1552	#endif
1553	uint8_t padding[8]; /* multiple of 8 */
1554	} cfgm;
1555
1556	/** Padding for aligning the cpu array on a page boundary. */
1557	#if defined(VBOX_WITH_REM) && defined(VBOX_WITH_RAW_MODE)
1558	uint8_t abAlignment2[3670];
1559	#elif defined(VBOX_WITH_REM) && !defined(VBOX_WITH_RAW_MODE)
1560	uint8_t abAlignment2[1430];
1561	#elif !defined(VBOX_WITH_REM) && defined(VBOX_WITH_RAW_MODE)
1562	uint8_t abAlignment2[3926];
1563	#else
1564	uint8_t abAlignment2[1686];
1565	#endif
1566
1567	/* ---- end small stuff ---- */
1568
1569	/** VMCPU array for the configured number of virtual CPUs.
1570	* Must be aligned on a page boundary for TLB hit reasons as well as
1571	* alignment of VMCPU members. */
1572	VMCPU aCpus[1];
1573	} VM;
1574
1575
1576	#ifdef IN_RC
1577	RT_C_DECLS_BEGIN
1578
1579	/** The VM structure.
1580	* This is imported from the VMMRCBuiltin module, i.e. it's a one of those magic
1581	* globals which we should avoid using.
1582	*/
1583	extern DECLIMPORT(VM) g_VM;
1584
1585	RT_C_DECLS_END
1586	#endif
1587
1588	/** @} */
1589
1590	#endif
1591

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source: vbox/trunk/include/VBox/vmm/vm.h@ 75671

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