vm.h@ 76507

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1	/** @file
2	* VM - The Virtual Machine, data.
3	*/
4
5	/*
6	* Copyright (C) 2006-2017 Oracle Corporation
7	*
8	* This file is part of VirtualBox Open Source Edition (OSE), as
9	* available from http://www.virtualbox.org. This file is free software;
10	* you can redistribute it and/or modify it under the terms of the GNU
11	* General Public License (GPL) as published by the Free Software
12	* Foundation, in version 2 as it comes in the "COPYING" file of the
13	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15	*
16	* The contents of this file may alternatively be used under the terms
17	* of the Common Development and Distribution License Version 1.0
18	* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19	* VirtualBox OSE distribution, in which case the provisions of the
20	* CDDL are applicable instead of those of the GPL.
21	*
22	* You may elect to license modified versions of this file under the
23	* terms and conditions of either the GPL or the CDDL or both.
24	*/
25
26	#ifndef ___VBox_vmm_vm_h
27	#define ___VBox_vmm_vm_h
28	#ifndef RT_WITHOUT_PRAGMA_ONCE
29	# pragma once
30	#endif
31
32	#ifndef VBOX_FOR_DTRACE_LIB
33	# include <iprt/param.h>
34	# include <VBox/types.h>
35	# include <VBox/vmm/cpum.h>
36	# include <VBox/vmm/stam.h>
37	# include <VBox/vmm/vmapi.h>
38	# include <VBox/vmm/vmm.h>
39	# include <VBox/sup.h>
40	#else
41	# pragma D depends_on library vbox-types.d
42	# pragma D depends_on library CPUMInternal.d
43	# define ___CPUMInternal_h
44	#endif
45
46
47
48	/** @defgroup grp_vm The Virtual Machine
49	* @ingroup grp_vmm
50	* @{
51	*/
52
53	/**
54	* The state of a Virtual CPU.
55	*
56	* The basic state indicated here is whether the CPU has been started or not. In
57	* addition, there are sub-states when started for assisting scheduling (GVMM
58	* mostly).
59	*
60	* The transition out of the STOPPED state is done by a vmR3PowerOn.
61	* The transition back to the STOPPED state is done by vmR3PowerOff.
62	*
63	* (Alternatively we could let vmR3PowerOn start CPU 0 only and let the SPIP
64	* handling switch on the other CPUs. Then vmR3Reset would stop all but CPU 0.)
65	*/
66	typedef enum VMCPUSTATE
67	{
68	/** The customary invalid zero. */
69	VMCPUSTATE_INVALID = 0,
70
71	/** Virtual CPU has not yet been started. */
72	VMCPUSTATE_STOPPED,
73
74	/** CPU started. */
75	VMCPUSTATE_STARTED,
76	/** CPU started in HM context. */
77	VMCPUSTATE_STARTED_HM,
78	/** Executing guest code and can be poked (RC or STI bits of HM). */
79	VMCPUSTATE_STARTED_EXEC,
80	/** Executing guest code in the recompiler. */
81	VMCPUSTATE_STARTED_EXEC_REM,
82	/** Executing guest code using NEM. */
83	VMCPUSTATE_STARTED_EXEC_NEM,
84	VMCPUSTATE_STARTED_EXEC_NEM_WAIT,
85	VMCPUSTATE_STARTED_EXEC_NEM_CANCELED,
86	/** Halted. */
87	VMCPUSTATE_STARTED_HALTED,
88
89	/** The end of valid virtual CPU states. */
90	VMCPUSTATE_END,
91
92	/** Ensure 32-bit type. */
93	VMCPUSTATE_32BIT_HACK = 0x7fffffff
94	} VMCPUSTATE;
95
96	/** Enables 64-bit FFs. */
97	#define VMCPU_WITH_64_BIT_FFS
98
99
100	/**
101	* The cross context virtual CPU structure.
102	*
103	* Run 'kmk run-struct-tests' (from src/VBox/VMM if you like) after updating!
104	*/
105	typedef struct VMCPU
106	{
107	/** @name Volatile per-cpu data.
108	* @{ */
109	/** Per CPU forced action.
110	* See the VMCPU_FF_* \#defines. Updated atomically. */
111	#ifdef VMCPU_WITH_64_BIT_FFS
112	uint64_t volatile fLocalForcedActions;
113	#else
114	uint32_t volatile fLocalForcedActions;
115	uint32_t fForLocalForcedActionsExpansion;
116	#endif
117	/** The CPU state. */
118	VMCPUSTATE volatile enmState;
119
120	/** Which host CPU ID is this EMT running on.
121	* Only valid when in RC or HMR0 with scheduling disabled. */
122	RTCPUID volatile idHostCpu;
123	/** The CPU set index corresponding to idHostCpu, UINT32_MAX if not valid.
124	* @remarks Best to make sure iHostCpuSet shares cache line with idHostCpu! */
125	uint32_t volatile iHostCpuSet;
126	/** Padding up to 64 bytes. */
127	uint8_t abAlignment0[64 - 20];
128	/** @} */
129
130	/** IEM part.
131	* @remarks This comes first as it allows the use of 8-bit immediates for the
132	* first 64 bytes of the structure, reducing code size a wee bit. */
133	#ifdef ___IEMInternal_h /* For PDB hacking. */
134	union VMCPUUNIONIEMFULL
135	#else
136	union VMCPUUNIONIEMSTUB
137	#endif
138	{
139	#ifdef ___IEMInternal_h
140	struct IEMCPU s;
141	#endif
142	uint8_t padding[18496]; /* multiple of 64 */
143	} iem;
144
145	/** @name Static per-cpu data.
146	* (Putting this after IEM, hoping that it's less frequently used than it.)
147	* @{ */
148	/** The CPU ID.
149	* This is the index into the VM::aCpu array. */
150	VMCPUID idCpu;
151	/** Raw-mode Context VM Pointer. */
152	PVMRC pVMRC;
153	/** Ring-3 Host Context VM Pointer. */
154	PVMR3 pVMR3;
155	/** Ring-0 Host Context VM Pointer. */
156	PVMR0 pVMR0;
157	/** Pointer to the ring-3 UVMCPU structure. */
158	PUVMCPU pUVCpu;
159	/** The native thread handle. */
160	RTNATIVETHREAD hNativeThread;
161	/** The native R0 thread handle. (different from the R3 handle!) */
162	RTNATIVETHREAD hNativeThreadR0;
163	/** Align the structures below bit on a 64-byte boundary and make sure it starts
164	* at the same offset in both 64-bit and 32-bit builds.
165	*
166	* @remarks The alignments of the members that are larger than 48 bytes should be
167	* 64-byte for cache line reasons. structs containing small amounts of
168	* data could be lumped together at the end with a < 64 byte padding
169	* following it (to grow into and align the struct size).
170	*/
171	uint8_t abAlignment1[64 - 4 - 4 - 5 * (HC_ARCH_BITS == 64 ? 8 : 4)];
172	/** @} */
173
174	/** HM part. */
175	union VMCPUUNIONHM
176	{
177	#ifdef ___HMInternal_h
178	struct HMCPU s;
179	#endif
180	uint8_t padding[5888]; /* multiple of 64 */
181	} hm;
182
183	/** NEM part. */
184	union VMCPUUNIONNEM
185	{
186	#ifdef ___NEMInternal_h
187	struct NEMCPU s;
188	#endif
189	uint8_t padding[512]; /* multiple of 64 */
190	} nem;
191
192	/** TRPM part. */
193	union VMCPUUNIONTRPM
194	{
195	#ifdef ___TRPMInternal_h
196	struct TRPMCPU s;
197	#endif
198	uint8_t padding[128]; /* multiple of 64 */
199	} trpm;
200
201	/** TM part. */
202	union VMCPUUNIONTM
203	{
204	#ifdef ___TMInternal_h
205	struct TMCPU s;
206	#endif
207	uint8_t padding[384]; /* multiple of 64 */
208	} tm;
209
210	/** VMM part. */
211	union VMCPUUNIONVMM
212	{
213	#ifdef ___VMMInternal_h
214	struct VMMCPU s;
215	#endif
216	uint8_t padding[896]; /* multiple of 64 */
217	} vmm;
218
219	/** PDM part. */
220	union VMCPUUNIONPDM
221	{
222	#ifdef ___PDMInternal_h
223	struct PDMCPU s;
224	#endif
225	uint8_t padding[256]; /* multiple of 64 */
226	} pdm;
227
228	/** IOM part. */
229	union VMCPUUNIONIOM
230	{
231	#ifdef ___IOMInternal_h
232	struct IOMCPU s;
233	#endif
234	uint8_t padding[512]; /* multiple of 64 */
235	} iom;
236
237	/** DBGF part.
238	* @todo Combine this with other tiny structures. */
239	union VMCPUUNIONDBGF
240	{
241	#ifdef ___DBGFInternal_h
242	struct DBGFCPU s;
243	#endif
244	uint8_t padding[256]; /* multiple of 64 */
245	} dbgf;
246
247	/** GIM part. */
248	union VMCPUUNIONGIM
249	{
250	#ifdef ___GIMInternal_h
251	struct GIMCPU s;
252	#endif
253	uint8_t padding[512]; /* multiple of 64 */
254	} gim;
255
256	/** APIC part. */
257	union VMCPUUNIONAPIC
258	{
259	#ifdef ___APICInternal_h
260	struct APICCPU s;
261	#endif
262	uint8_t padding[1792]; /* multiple of 64 */
263	} apic;
264
265	/*
266	* Some less frequently used global members that doesn't need to take up
267	* precious space at the head of the structure.
268	*/
269
270	/** Trace groups enable flags. */
271	uint32_t fTraceGroups; /* 64 / 44 */
272	/** State data for use by ad hoc profiling. */
273	uint32_t uAdHoc;
274	/** Profiling samples for use by ad hoc profiling. */
275	STAMPROFILEADV aStatAdHoc[8]; /* size: 408 = 320 /
276
277	/** Align the following members on page boundary. */
278	uint8_t abAlignment2[2680];
279
280	/** PGM part. */
281	union VMCPUUNIONPGM
282	{
283	#ifdef ___PGMInternal_h
284	struct PGMCPU s;
285	#endif
286	uint8_t padding[4096]; /* multiple of 4096 */
287	} pgm;
288
289	/** CPUM part. */
290	union VMCPUUNIONCPUM
291	{
292	#ifdef ___CPUMInternal_h
293	struct CPUMCPU s;
294	#endif
295	#ifdef VMCPU_INCL_CPUM_GST_CTX
296	/** The guest CPUM context for direct use by execution engines.
297	* This is not for general consumption, but for HM, REM, IEM, and maybe a few
298	* others. The rest will use the function based CPUM API. */
299	CPUMCTX GstCtx;
300	#endif
301	uint8_t padding[4096]; /* multiple of 4096 */
302	} cpum;
303
304	/** EM part. */
305	union VMCPUUNIONEM
306	{
307	#ifdef ___EMInternal_h
308	struct EMCPU s;
309	#endif
310	uint8_t padding[40960]; /* multiple of 4096 */
311	} em;
312	} VMCPU;
313
314
315	#ifndef VBOX_FOR_DTRACE_LIB
316
317	/** @name Operations on VMCPU::enmState
318	* @{ */
319	/** Gets the VMCPU state. */
320	#define VMCPU_GET_STATE(pVCpu) ( (pVCpu)->enmState )
321	/** Sets the VMCPU state. */
322	#define VMCPU_SET_STATE(pVCpu, enmNewState) \
323	ASMAtomicWriteU32((uint32_t volatile *)&(pVCpu)->enmState, (enmNewState))
324	/** Cmpares and sets the VMCPU state. */
325	#define VMCPU_CMPXCHG_STATE(pVCpu, enmNewState, enmOldState) \
326	ASMAtomicCmpXchgU32((uint32_t volatile *)&(pVCpu)->enmState, (enmNewState), (enmOldState))
327	/** Checks the VMCPU state. */
328	#ifdef VBOX_STRICT
329	# define VMCPU_ASSERT_STATE(pVCpu, enmExpectedState) \
330	do { \
331	VMCPUSTATE enmState = VMCPU_GET_STATE(pVCpu); \
332	AssertMsg(enmState == (enmExpectedState), \
333	("enmState=%d enmExpectedState=%d idCpu=%u\n", \
334	enmState, enmExpectedState, (pVCpu)->idCpu)); \
335	} while (0)
336	#else
337	# define VMCPU_ASSERT_STATE(pVCpu, enmExpectedState) do { } while (0)
338	#endif
339	/** Tests if the state means that the CPU is started. */
340	#define VMCPUSTATE_IS_STARTED(enmState) ( (enmState) > VMCPUSTATE_STOPPED )
341	/** Tests if the state means that the CPU is stopped. */
342	#define VMCPUSTATE_IS_STOPPED(enmState) ( (enmState) == VMCPUSTATE_STOPPED )
343	/** @} */
344
345
346	/** The name of the raw-mode context VMM Core module. */
347	#define VMMRC_MAIN_MODULE_NAME "VMMRC.rc"
348	/** The name of the ring-0 context VMM Core module. */
349	#define VMMR0_MAIN_MODULE_NAME "VMMR0.r0"
350
351	/**
352	* Wrapper macro for avoiding too much \#ifdef VBOX_WITH_RAW_MODE.
353	*/
354	#ifdef VBOX_WITH_RAW_MODE
355	# define VM_WHEN_RAW_MODE(a_WithExpr, a_WithoutExpr) a_WithExpr
356	#else
357	# define VM_WHEN_RAW_MODE(a_WithExpr, a_WithoutExpr) a_WithoutExpr
358	#endif
359
360
361	/** VM Forced Action Flags.
362	*
363	* Use the VM_FF_SET() and VM_FF_CLEAR() macros to change the force
364	* action mask of a VM.
365	*
366	* Available VM bits:
367	* 0, 1, 5, 6, 7, 13, 14, 15, 16, 17, 21, 22, 23, 24, 25, 26, 27, 28, 30
368	*
369	*
370	* Available VMCPU bits:
371	* 14, 15, 34 to 63
372	*
373	* @todo If we run low on VMCPU, we may consider merging the SELM bits
374	*
375	* @{
376	*/
377	/** The virtual sync clock has been stopped, go to TM until it has been
378	* restarted... */
379	#define VM_FF_TM_VIRTUAL_SYNC RT_BIT_32(VM_FF_TM_VIRTUAL_SYNC_BIT)
380	#define VM_FF_TM_VIRTUAL_SYNC_BIT 2
381	/** PDM Queues are pending. */
382	#define VM_FF_PDM_QUEUES RT_BIT_32(VM_FF_PDM_QUEUES_BIT)
383	/** The bit number for VM_FF_PDM_QUEUES. */
384	#define VM_FF_PDM_QUEUES_BIT 3
385	/** PDM DMA transfers are pending. */
386	#define VM_FF_PDM_DMA RT_BIT_32(VM_FF_PDM_DMA_BIT)
387	/** The bit number for VM_FF_PDM_DMA. */
388	#define VM_FF_PDM_DMA_BIT 4
389	/** This action forces the VM to call DBGF so DBGF can service debugger
390	* requests in the emulation thread.
391	* This action flag stays asserted till DBGF clears it.*/
392	#define VM_FF_DBGF RT_BIT_32(VM_FF_DBGF_BIT)
393	/** The bit number for VM_FF_DBGF. */
394	#define VM_FF_DBGF_BIT 8
395	/** This action forces the VM to service pending requests from other
396	* thread or requests which must be executed in another context. */
397	#define VM_FF_REQUEST RT_BIT_32(VM_FF_REQUEST_BIT)
398	#define VM_FF_REQUEST_BIT 9
399	/** Check for VM state changes and take appropriate action. */
400	#define VM_FF_CHECK_VM_STATE RT_BIT_32(VM_FF_CHECK_VM_STATE_BIT)
401	/** The bit number for VM_FF_CHECK_VM_STATE. */
402	#define VM_FF_CHECK_VM_STATE_BIT 10
403	/** Reset the VM. (postponed) */
404	#define VM_FF_RESET RT_BIT_32(VM_FF_RESET_BIT)
405	/** The bit number for VM_FF_RESET. */
406	#define VM_FF_RESET_BIT 11
407	/** EMT rendezvous in VMM. */
408	#define VM_FF_EMT_RENDEZVOUS RT_BIT_32(VM_FF_EMT_RENDEZVOUS_BIT)
409	/** The bit number for VM_FF_EMT_RENDEZVOUS. */
410	#define VM_FF_EMT_RENDEZVOUS_BIT 12
411
412	/** PGM needs to allocate handy pages. */
413	#define VM_FF_PGM_NEED_HANDY_PAGES RT_BIT_32(VM_FF_PGM_NEED_HANDY_PAGES_BIT)
414	#define VM_FF_PGM_NEED_HANDY_PAGES_BIT 18
415	/** PGM is out of memory.
416	* Abandon all loops and code paths which can be resumed and get up to the EM
417	* loops. */
418	#define VM_FF_PGM_NO_MEMORY RT_BIT_32(VM_FF_PGM_NO_MEMORY_BIT)
419	#define VM_FF_PGM_NO_MEMORY_BIT 19
420	/** PGM is about to perform a lightweight pool flush
421	* Guest SMP: all EMT threads should return to ring 3
422	*/
423	#define VM_FF_PGM_POOL_FLUSH_PENDING RT_BIT_32(VM_FF_PGM_POOL_FLUSH_PENDING_BIT)
424	#define VM_FF_PGM_POOL_FLUSH_PENDING_BIT 20
425	/** REM needs to be informed about handler changes. */
426	#define VM_FF_REM_HANDLER_NOTIFY RT_BIT_32(VM_FF_REM_HANDLER_NOTIFY_BIT)
427	/** The bit number for VM_FF_REM_HANDLER_NOTIFY. */
428	#define VM_FF_REM_HANDLER_NOTIFY_BIT 29
429	/** Suspend the VM - debug only. */
430	#define VM_FF_DEBUG_SUSPEND RT_BIT_32(VM_FF_DEBUG_SUSPEND_BIT)
431	#define VM_FF_DEBUG_SUSPEND_BIT 31
432
433
434	/** This action forces the VM to check any pending interrupts on the APIC. */
435	#define VMCPU_FF_INTERRUPT_APIC RT_BIT_64(VMCPU_FF_INTERRUPT_APIC_BIT)
436	#define VMCPU_FF_INTERRUPT_APIC_BIT 0
437	/** This action forces the VM to check any pending interrups on the PIC. */
438	#define VMCPU_FF_INTERRUPT_PIC RT_BIT_64(VMCPU_FF_INTERRUPT_PIC_BIT)
439	#define VMCPU_FF_INTERRUPT_PIC_BIT 1
440	/** This action forces the VM to schedule and run pending timer (TM).
441	* @remarks Don't move - PATM compatibility. */
442	#define VMCPU_FF_TIMER RT_BIT_64(VMCPU_FF_TIMER_BIT)
443	#define VMCPU_FF_TIMER_BIT 2
444	/** This action forces the VM to check any pending NMIs. */
445	#define VMCPU_FF_INTERRUPT_NMI RT_BIT_64(VMCPU_FF_INTERRUPT_NMI_BIT)
446	#define VMCPU_FF_INTERRUPT_NMI_BIT 3
447	/** This action forces the VM to check any pending SMIs. */
448	#define VMCPU_FF_INTERRUPT_SMI RT_BIT_64(VMCPU_FF_INTERRUPT_SMI_BIT)
449	#define VMCPU_FF_INTERRUPT_SMI_BIT 4
450	/** PDM critical section unlocking is pending, process promptly upon return to R3. */
451	#define VMCPU_FF_PDM_CRITSECT RT_BIT_64(VMCPU_FF_PDM_CRITSECT_BIT)
452	#define VMCPU_FF_PDM_CRITSECT_BIT 5
453	/** Special EM internal force flag that is used by EMUnhaltAndWakeUp() to force
454	* the virtual CPU out of the next (/current) halted state. It is not processed
455	* nor cleared by emR3ForcedActions (similar to VMCPU_FF_BLOCK_NMIS), instead it
456	* is cleared the next time EM leaves the HALTED state. */
457	#define VMCPU_FF_UNHALT RT_BIT_64(VMCPU_FF_UNHALT_BIT)
458	#define VMCPU_FF_UNHALT_BIT 6
459	/** Pending IEM action (mask). */
460	#define VMCPU_FF_IEM RT_BIT_64(VMCPU_FF_IEM_BIT)
461	/** Pending IEM action (bit number). */
462	#define VMCPU_FF_IEM_BIT 7
463	/** Pending APIC action (bit number). */
464	#define VMCPU_FF_UPDATE_APIC_BIT 8
465	/** This action forces the VM to update APIC's asynchronously arrived
466	* interrupts as pending interrupts. */
467	#define VMCPU_FF_UPDATE_APIC RT_BIT_64(VMCPU_FF_UPDATE_APIC_BIT)
468	/** This action forces the VM to service pending requests from other
469	* thread or requests which must be executed in another context. */
470	#define VMCPU_FF_REQUEST RT_BIT_64(VMCPU_FF_REQUEST_BIT)
471	#define VMCPU_FF_REQUEST_BIT 9
472	/** Pending DBGF event (alternative to passing VINF_EM_DBG_EVENT around). */
473	#define VMCPU_FF_DBGF RT_BIT_64(VMCPU_FF_DBGF_BIT)
474	/** The bit number for VMCPU_FF_DBGF. */
475	#define VMCPU_FF_DBGF_BIT 10
476	/** This action forces the VM to service any pending updates to CR3 (used only
477	* by HM). */
478	/** Hardware virtualized nested-guest interrupt pending. */
479	#define VMCPU_FF_INTERRUPT_NESTED_GUEST RT_BIT_64(VMCPU_FF_INTERRUPT_NESTED_GUEST_BIT)
480	#define VMCPU_FF_INTERRUPT_NESTED_GUEST_BIT 11
481	#define VMCPU_FF_HM_UPDATE_CR3 RT_BIT_64(VMCPU_FF_HM_UPDATE_CR3_BIT)
482	#define VMCPU_FF_HM_UPDATE_CR3_BIT 12
483	/** This action forces the VM to service any pending updates to PAE PDPEs (used
484	* only by HM). */
485	#define VMCPU_FF_HM_UPDATE_PAE_PDPES RT_BIT_64(VMCPU_FF_HM_UPDATE_PAE_PDPES_BIT)
486	#define VMCPU_FF_HM_UPDATE_PAE_PDPES_BIT 13
487	/** This action forces the VM to resync the page tables before going
488	* back to execute guest code. (GLOBAL FLUSH) */
489	#define VMCPU_FF_PGM_SYNC_CR3 RT_BIT_64(VMCPU_FF_PGM_SYNC_CR3_BIT)
490	#define VMCPU_FF_PGM_SYNC_CR3_BIT 16
491	/** Same as VM_FF_PGM_SYNC_CR3 except that global pages can be skipped.
492	* (NON-GLOBAL FLUSH) */
493	#define VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL RT_BIT_64(VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL_BIT)
494	#define VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL_BIT 17
495	/** Check for pending TLB shootdown actions (deprecated)
496	* Reserved for furture HM re-use if necessary / safe.
497	* Consumer: HM */
498	#define VMCPU_FF_TLB_SHOOTDOWN_UNUSED RT_BIT_64(VMCPU_FF_TLB_SHOOTDOWN_UNUSED_BIT)
499	#define VMCPU_FF_TLB_SHOOTDOWN_UNUSED_BIT 18
500	/** Check for pending TLB flush action.
501	* Consumer: HM
502	* @todo rename to VMCPU_FF_HM_TLB_FLUSH */
503	#define VMCPU_FF_TLB_FLUSH RT_BIT_64(VMCPU_FF_TLB_FLUSH_BIT)
504	/** The bit number for VMCPU_FF_TLB_FLUSH. */
505	#define VMCPU_FF_TLB_FLUSH_BIT 19
506	#ifdef VBOX_WITH_RAW_MODE
507	/** Check the interrupt and trap gates */
508	# define VMCPU_FF_TRPM_SYNC_IDT RT_BIT_64(VMCPU_FF_TRPM_SYNC_IDT_BIT)
509	# define VMCPU_FF_TRPM_SYNC_IDT_BIT 20
510	/** Check Guest's TSS ring 0 stack */
511	# define VMCPU_FF_SELM_SYNC_TSS RT_BIT_64(VMCPU_FF_SELM_SYNC_TSS_BIT)
512	# define VMCPU_FF_SELM_SYNC_TSS_BIT 21
513	/** Check Guest's GDT table */
514	# define VMCPU_FF_SELM_SYNC_GDT RT_BIT_64(VMCPU_FF_SELM_SYNC_GDT_BIT)
515	# define VMCPU_FF_SELM_SYNC_GDT_BIT 22
516	/** Check Guest's LDT table */
517	# define VMCPU_FF_SELM_SYNC_LDT RT_BIT_64(VMCPU_FF_SELM_SYNC_LDT_BIT)
518	# define VMCPU_FF_SELM_SYNC_LDT_BIT 23
519	#endif /* VBOX_WITH_RAW_MODE */
520	/** Inhibit interrupts pending. See EMGetInhibitInterruptsPC(). */
521	#define VMCPU_FF_INHIBIT_INTERRUPTS RT_BIT_64(VMCPU_FF_INHIBIT_INTERRUPTS_BIT)
522	#define VMCPU_FF_INHIBIT_INTERRUPTS_BIT 24
523	/** Block injection of non-maskable interrupts to the guest. */
524	#define VMCPU_FF_BLOCK_NMIS RT_BIT_64(VMCPU_FF_BLOCK_NMIS_BIT)
525	#define VMCPU_FF_BLOCK_NMIS_BIT 25
526	#ifdef VBOX_WITH_RAW_MODE
527	/** CSAM needs to scan the page that's being executed */
528	# define VMCPU_FF_CSAM_SCAN_PAGE RT_BIT_64(VMCPU_FF_CSAM_SCAN_PAGE_BIT)
529	# define VMCPU_FF_CSAM_SCAN_PAGE_BIT 26
530	/** CSAM needs to do some homework. */
531	# define VMCPU_FF_CSAM_PENDING_ACTION RT_BIT_64(VMCPU_FF_CSAM_PENDING_ACTION_BIT)
532	# define VMCPU_FF_CSAM_PENDING_ACTION_BIT 27
533	#endif /* VBOX_WITH_RAW_MODE */
534	/** Force return to Ring-3. */
535	#define VMCPU_FF_TO_R3 RT_BIT_64(VMCPU_FF_TO_R3_BIT)
536	#define VMCPU_FF_TO_R3_BIT 28
537	/** Force return to ring-3 to service pending I/O or MMIO write.
538	* This is a backup for mechanism VINF_IOM_R3_IOPORT_COMMIT_WRITE and
539	* VINF_IOM_R3_MMIO_COMMIT_WRITE, allowing VINF_EM_DBG_BREAKPOINT and similar
540	* status codes to be propagated at the same time without loss. */
541	#define VMCPU_FF_IOM RT_BIT_64(VMCPU_FF_IOM_BIT)
542	#define VMCPU_FF_IOM_BIT 29
543	#ifdef VBOX_WITH_RAW_MODE
544	/** CPUM need to adjust CR0.TS/EM before executing raw-mode code again. */
545	# define VMCPU_FF_CPUM RT_BIT_64(VMCPU_FF_CPUM_BIT)
546	/** The bit number for VMCPU_FF_CPUM. */
547	# define VMCPU_FF_CPUM_BIT 30
548	#endif /* VBOX_WITH_RAW_MODE */
549	/** VMX-preemption timer in effect. */
550	#define VMCPU_FF_VMX_PREEMPT_TIMER RT_BIT_64(VMCPU_FF_VMX_PREEMPT_TIMER_BIT)
551	#define VMCPU_FF_VMX_PREEMPT_TIMER_BIT 31
552	/** Pending MTF (Monitor Trap Flag) event. */
553	#define VMCPU_FF_VMX_MTF RT_BIT_64(VMCPU_FF_VMX_MTF_BIT)
554	#define VMCPU_FF_VMX_MTF_BIT 32
555	/** VMX APIC-write emulation pending. */
556	#define VMCPU_FF_VMX_APIC_WRITE RT_BIT_64(VMCPU_FF_VMX_APIC_WRITE_BIT)
557	#define VMCPU_FF_VMX_APIC_WRITE_BIT 33
558
559
560	/** Externally VM forced actions. Used to quit the idle/wait loop. */
561	#define VM_FF_EXTERNAL_SUSPENDED_MASK ( VM_FF_CHECK_VM_STATE \| VM_FF_DBGF \| VM_FF_REQUEST \| VM_FF_EMT_RENDEZVOUS )
562	/** Externally VMCPU forced actions. Used to quit the idle/wait loop. */
563	#define VMCPU_FF_EXTERNAL_SUSPENDED_MASK ( VMCPU_FF_REQUEST \| VMCPU_FF_DBGF )
564
565	/** Externally forced VM actions. Used to quit the idle/wait loop. */
566	#define VM_FF_EXTERNAL_HALTED_MASK ( VM_FF_CHECK_VM_STATE \| VM_FF_DBGF \| VM_FF_REQUEST \
567	\| VM_FF_PDM_QUEUES \| VM_FF_PDM_DMA \| VM_FF_EMT_RENDEZVOUS )
568	/** Externally forced VMCPU actions. Used to quit the idle/wait loop. */
569	#define VMCPU_FF_EXTERNAL_HALTED_MASK ( VMCPU_FF_UPDATE_APIC \| VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC \
570	\| VMCPU_FF_REQUEST \| VMCPU_FF_INTERRUPT_NMI \| VMCPU_FF_INTERRUPT_SMI \
571	\| VMCPU_FF_UNHALT \| VMCPU_FF_TIMER \| VMCPU_FF_DBGF \
572	\| VMCPU_FF_INTERRUPT_NESTED_GUEST)
573
574	/** High priority VM pre-execution actions. */
575	#define VM_FF_HIGH_PRIORITY_PRE_MASK ( VM_FF_CHECK_VM_STATE \| VM_FF_DBGF \| VM_FF_TM_VIRTUAL_SYNC \
576	\| VM_FF_DEBUG_SUSPEND \| VM_FF_PGM_NEED_HANDY_PAGES \| VM_FF_PGM_NO_MEMORY \
577	\| VM_FF_EMT_RENDEZVOUS )
578	/** High priority VMCPU pre-execution actions. */
579	#define VMCPU_FF_HIGH_PRIORITY_PRE_MASK ( VMCPU_FF_TIMER \| VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC \
580	\| VMCPU_FF_UPDATE_APIC \| VMCPU_FF_INHIBIT_INTERRUPTS \| VMCPU_FF_DBGF \
581	\| VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL \
582	\| VMCPU_FF_INTERRUPT_NESTED_GUEST \| VMCPU_FF_VMX_MTF \
583	\| VM_WHEN_RAW_MODE( VMCPU_FF_SELM_SYNC_TSS \| VMCPU_FF_TRPM_SYNC_IDT \
584	\| VMCPU_FF_SELM_SYNC_GDT \| VMCPU_FF_SELM_SYNC_LDT, 0 ) )
585
586	/** High priority VM pre raw-mode execution mask. */
587	#define VM_FF_HIGH_PRIORITY_PRE_RAW_MASK ( VM_FF_PGM_NEED_HANDY_PAGES \| VM_FF_PGM_NO_MEMORY )
588	/** High priority VMCPU pre raw-mode execution mask. */
589	#define VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK ( VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL \
590	\| VMCPU_FF_INHIBIT_INTERRUPTS \
591	\| VM_WHEN_RAW_MODE( VMCPU_FF_SELM_SYNC_TSS \| VMCPU_FF_TRPM_SYNC_IDT \
592	\| VMCPU_FF_SELM_SYNC_GDT \| VMCPU_FF_SELM_SYNC_LDT, 0) )
593
594	/** High priority post-execution actions. */
595	#define VM_FF_HIGH_PRIORITY_POST_MASK ( VM_FF_PGM_NO_MEMORY )
596	/** High priority post-execution actions. */
597	#define VMCPU_FF_HIGH_PRIORITY_POST_MASK ( VMCPU_FF_PDM_CRITSECT \| VM_WHEN_RAW_MODE(VMCPU_FF_CSAM_PENDING_ACTION, 0) \
598	\| VMCPU_FF_HM_UPDATE_CR3 \| VMCPU_FF_HM_UPDATE_PAE_PDPES \
599	\| VMCPU_FF_VMX_APIC_WRITE \| VMCPU_FF_IEM \| VMCPU_FF_IOM )
600
601	/** Normal priority VM post-execution actions. */
602	#define VM_FF_NORMAL_PRIORITY_POST_MASK ( VM_FF_CHECK_VM_STATE \| VM_FF_DBGF \| VM_FF_RESET \
603	\| VM_FF_PGM_NO_MEMORY \| VM_FF_EMT_RENDEZVOUS)
604	/** Normal priority VMCPU post-execution actions. */
605	#define VMCPU_FF_NORMAL_PRIORITY_POST_MASK ( VM_WHEN_RAW_MODE(VMCPU_FF_CSAM_SCAN_PAGE, 0) \| VMCPU_FF_DBGF )
606
607	/** Normal priority VM actions. */
608	#define VM_FF_NORMAL_PRIORITY_MASK ( VM_FF_REQUEST \| VM_FF_PDM_QUEUES \| VM_FF_PDM_DMA \
609	\| VM_FF_REM_HANDLER_NOTIFY \| VM_FF_EMT_RENDEZVOUS)
610	/** Normal priority VMCPU actions. */
611	#define VMCPU_FF_NORMAL_PRIORITY_MASK ( VMCPU_FF_REQUEST )
612
613	/** Flags to clear before resuming guest execution. */
614	#define VMCPU_FF_RESUME_GUEST_MASK ( VMCPU_FF_TO_R3 )
615
616
617	/** VM flags that cause the REP[\|NE\|E] STRINS loops to yield immediately. */
618	#define VM_FF_HIGH_PRIORITY_POST_REPSTR_MASK ( VM_FF_TM_VIRTUAL_SYNC \| VM_FF_PGM_NEED_HANDY_PAGES \| VM_FF_PGM_NO_MEMORY \
619	\| VM_FF_EMT_RENDEZVOUS \| VM_FF_PGM_POOL_FLUSH_PENDING \| VM_FF_RESET)
620	/** VM flags that cause the REP[\|NE\|E] STRINS loops to yield. */
621	#define VM_FF_YIELD_REPSTR_MASK ( VM_FF_HIGH_PRIORITY_POST_REPSTR_MASK \
622	\| VM_FF_PDM_QUEUES \| VM_FF_PDM_DMA \| VM_FF_DBGF \| VM_FF_DEBUG_SUSPEND )
623	/** VMCPU flags that cause the REP[\|NE\|E] STRINS loops to yield immediately. */
624	#ifdef IN_RING3
625	# define VMCPU_FF_HIGH_PRIORITY_POST_REPSTR_MASK ( VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL \| VMCPU_FF_DBGF \
626	\| VMCPU_FF_VMX_MTF )
627	#else
628	# define VMCPU_FF_HIGH_PRIORITY_POST_REPSTR_MASK ( VMCPU_FF_TO_R3 \| VMCPU_FF_IEM \| VMCPU_FF_IOM \| VMCPU_FF_PGM_SYNC_CR3 \
629	\| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL \| VMCPU_FF_DBGF \| VMCPU_FF_VMX_MTF )
630	#endif
631	/** VMCPU flags that cause the REP[\|NE\|E] STRINS loops to yield, interrupts
632	* enabled. */
633	#define VMCPU_FF_YIELD_REPSTR_MASK ( VMCPU_FF_HIGH_PRIORITY_POST_REPSTR_MASK \
634	\| VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_UPDATE_APIC \| VMCPU_FF_INTERRUPT_PIC \
635	\| VMCPU_FF_INTERRUPT_NMI \| VMCPU_FF_INTERRUPT_SMI \| VMCPU_FF_PDM_CRITSECT \
636	\| VMCPU_FF_TIMER \| VMCPU_FF_REQUEST \
637	\| VMCPU_FF_INTERRUPT_NESTED_GUEST )
638	/** VMCPU flags that cause the REP[\|NE\|E] STRINS loops to yield, interrupts
639	* disabled. */
640	#define VMCPU_FF_YIELD_REPSTR_NOINT_MASK ( VMCPU_FF_YIELD_REPSTR_MASK \
641	& ~( VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_UPDATE_APIC \| VMCPU_FF_INTERRUPT_PIC \
642	\| VMCPU_FF_INTERRUPT_NESTED_GUEST) )
643
644	/** VM Flags that cause the HM loops to go back to ring-3. */
645	#define VM_FF_HM_TO_R3_MASK ( VM_FF_TM_VIRTUAL_SYNC \| VM_FF_PGM_NEED_HANDY_PAGES \| VM_FF_PGM_NO_MEMORY \
646	\| VM_FF_PDM_QUEUES \| VM_FF_EMT_RENDEZVOUS)
647	/** VMCPU Flags that cause the HM loops to go back to ring-3. */
648	#define VMCPU_FF_HM_TO_R3_MASK ( VMCPU_FF_TO_R3 \| VMCPU_FF_TIMER \| VMCPU_FF_PDM_CRITSECT \
649	\| VMCPU_FF_IEM \| VMCPU_FF_IOM)
650
651	/** High priority ring-0 VM pre HM-mode execution mask. */
652	#define VM_FF_HP_R0_PRE_HM_MASK (VM_FF_HM_TO_R3_MASK \| VM_FF_REQUEST \| VM_FF_PGM_POOL_FLUSH_PENDING \| VM_FF_PDM_DMA)
653	/** High priority ring-0 VMCPU pre HM-mode execution mask. */
654	#define VMCPU_FF_HP_R0_PRE_HM_MASK ( VMCPU_FF_HM_TO_R3_MASK \| VMCPU_FF_PGM_SYNC_CR3 \
655	\| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL \| VMCPU_FF_REQUEST)
656	/** High priority ring-0 VM pre HM-mode execution mask, single stepping. */
657	#define VM_FF_HP_R0_PRE_HM_STEP_MASK (VM_FF_HP_R0_PRE_HM_MASK & ~( VM_FF_TM_VIRTUAL_SYNC \| VM_FF_PDM_QUEUES \
658	\| VM_FF_EMT_RENDEZVOUS \| VM_FF_REQUEST \
659	\| VM_FF_PDM_DMA) )
660	/** High priority ring-0 VMCPU pre HM-mode execution mask, single stepping. */
661	#define VMCPU_FF_HP_R0_PRE_HM_STEP_MASK (VMCPU_FF_HP_R0_PRE_HM_MASK & ~( VMCPU_FF_TO_R3 \| VMCPU_FF_TIMER \
662	\| VMCPU_FF_PDM_CRITSECT \| VMCPU_FF_REQUEST) )
663
664	/** All the forced VM flags. */
665	#define VM_FF_ALL_MASK (UINT32_MAX)
666	/** All the forced VMCPU flags. */
667	#define VMCPU_FF_ALL_MASK (UINT32_MAX)
668
669	/** All the forced VM flags except those related to raw-mode and hardware
670	* assisted execution. */
671	#define VM_FF_ALL_REM_MASK (~(VM_FF_HIGH_PRIORITY_PRE_RAW_MASK) \| VM_FF_PGM_NEED_HANDY_PAGES \| VM_FF_PGM_NO_MEMORY)
672	/** All the forced VMCPU flags except those related to raw-mode and hardware
673	* assisted execution. */
674	#define VMCPU_FF_ALL_REM_MASK (~( VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK \| VMCPU_FF_PDM_CRITSECT \
675	\| VMCPU_FF_TLB_FLUSH \| VM_WHEN_RAW_MODE(VMCPU_FF_CSAM_PENDING_ACTION, 0) ))
676	/** @} */
677
678	/** @def VM_FF_SET
679	* Sets a single force action flag.
680	*
681	* @param pVM The cross context VM structure.
682	* @param fFlag The flag to set.
683	*/
684	#define VM_FF_SET(pVM, fFlag) do { \
685	AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
686	AssertCompile((fFlag) == RT_BIT_32(fFlag##_BIT)); \
687	ASMAtomicOrU32(&(pVM)->fGlobalForcedActions, (fFlag)); \
688	} while (0)
689
690	/** @def VMCPU_FF_SET
691	* Sets a single force action flag for the given VCPU.
692	*
693	* @param pVCpu The cross context virtual CPU structure.
694	* @param fFlag The flag to set.
695	* @sa VMCPU_FF_SET_MASK
696	*/
697	#ifdef VMCPU_WITH_64_BIT_FFS
698	# define VMCPU_FF_SET(pVCpu, fFlag) do { \
699	AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
700	AssertCompile((fFlag) == RT_BIT_64(fFlag##_BIT)); \
701	ASMAtomicBitSet(&(pVCpu)->fLocalForcedActions, fFlag##_BIT); \
702	} while (0)
703	#else
704	# define VMCPU_FF_SET(pVCpu, fFlag) do { \
705	AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
706	AssertCompile((fFlag) == RT_BIT_32(fFlag##_BIT)); \
707	ASMAtomicOrU32(&(pVCpu)->fLocalForcedActions, (fFlag)); \
708	} while (0)
709	#endif
710
711	/** @def VMCPU_FF_SET_MASK
712	* Sets a two or more force action flag for the given VCPU.
713	*
714	* @param pVCpu The cross context virtual CPU structure.
715	* @param fFlags The flags to set.
716	* @sa VMCPU_FF_SET
717	*/
718	#ifdef VMCPU_WITH_64_BIT_FFS
719	# if ARCH_BITS > 32
720	# define VMCPU_FF_SET_MASK(pVCpu, fFlags) \
721	do { ASMAtomicOrU64(&pVCpu->fLocalForcedActions, (fFlags)); } while (0)
722	# else
723	# define VMCPU_FF_SET_MASK(pVCpu, fFlags) do { \
724	if (!((fFlags) >> 32)) ASMAtomicOrU32((uint32_t volatile *)&pVCpu->fLocalForcedActions, (uint32_t)(fFlags)); \
725	else ASMAtomicOrU64(&pVCpu->fLocalForcedActions, (fFlags)); \
726	} while (0)
727	# endif
728	#else
729	# define VMCPU_FF_SET_MASK(pVCpu, fFlags) \
730	do { ASMAtomicOrU32(&pVCpu->fLocalForcedActions, (fFlags)); } while (0)
731	#endif
732
733	/** @def VM_FF_CLEAR
734	* Clears a single force action flag.
735	*
736	* @param pVM The cross context VM structure.
737	* @param fFlag The flag to clear.
738	*/
739	#define VM_FF_CLEAR(pVM, fFlag) do { \
740	AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
741	AssertCompile((fFlag) == RT_BIT_32(fFlag##_BIT)); \
742	ASMAtomicAndU32(&(pVM)->fGlobalForcedActions, ~(fFlag)); \
743	} while (0)
744
745	/** @def VMCPU_FF_CLEAR
746	* Clears a single force action flag for the given VCPU.
747	*
748	* @param pVCpu The cross context virtual CPU structure.
749	* @param fFlag The flag to clear.
750	*/
751	#ifdef VMCPU_WITH_64_BIT_FFS
752	# define VMCPU_FF_CLEAR(pVCpu, fFlag) do { \
753	AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
754	AssertCompile((fFlag) == RT_BIT_64(fFlag##_BIT)); \
755	ASMAtomicBitClear(&(pVCpu)->fLocalForcedActions, fFlag##_BIT); \
756	} while (0)
757	#else
758	# define VMCPU_FF_CLEAR(pVCpu, fFlag) do { \
759	AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
760	AssertCompile((fFlag) == RT_BIT_32(fFlag##_BIT)); \
761	ASMAtomicAndU32(&(pVCpu)->fLocalForcedActions, ~(fFlag)); \
762	} while (0)
763	#endif
764
765	/** @def VMCPU_FF_CLEAR_MASK
766	* Clears two or more force action flags for the given VCPU.
767	*
768	* @param pVCpu The cross context virtual CPU structure.
769	* @param fFlags The flags to clear.
770	*/
771	#ifdef VMCPU_WITH_64_BIT_FFS
772	# if ARCH_BITS > 32
773	# define VMCPU_FF_CLEAR_MASK(pVCpu, fFlags) \
774	do { ASMAtomicAndU64(&(pVCpu)->fLocalForcedActions, ~(fFlags)); } while (0)
775	# else
776	# define VMCPU_FF_CLEAR_MASK(pVCpu, fFlags) do { \
777	if (!((fFlags) >> 32)) ASMAtomicAndU32((uint32_t volatile *)&(pVCpu)->fLocalForcedActions, ~(uint32_t)(fFlags)); \
778	else ASMAtomicAndU64(&(pVCpu)->fLocalForcedActions, ~(fFlags)); \
779	} while (0)
780	# endif
781	#else
782	# define VMCPU_FF_CLEAR_MASK(pVCpu, fFlags) \
783	do { ASMAtomicAndU32(&(pVCpu)->fLocalForcedActions, ~(fFlags)); } while (0)
784	#endif
785
786	/** @def VM_FF_IS_SET
787	* Checks if single a force action flag is set.
788	*
789	* @param pVM The cross context VM structure.
790	* @param fFlag The flag to check.
791	* @sa VM_FF_IS_ANY_SET
792	*/
793	#if !defined(VBOX_STRICT) \|\| !defined(RT_COMPILER_SUPPORTS_LAMBDA)
794	# define VM_FF_IS_SET(pVM, fFlag) RT_BOOL((pVM)->fGlobalForcedActions & (fFlag))
795	#else
796	# define VM_FF_IS_SET(pVM, fFlag) \
797	([](PVM a_pVM) -> bool \
798	{ \
799	AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
800	AssertCompile((fFlag) == RT_BIT_32(fFlag##_BIT)); \
801	return RT_BOOL(a_pVM->fGlobalForcedActions & (fFlag)); \
802	}(pVM))
803	#endif
804
805	/** @def VMCPU_FF_IS_SET
806	* Checks if a single force action flag is set for the given VCPU.
807	*
808	* @param pVCpu The cross context virtual CPU structure.
809	* @param fFlag The flag to check.
810	* @sa VMCPU_FF_IS_ANY_SET
811	*/
812	#if !defined(VBOX_STRICT) \|\| !defined(RT_COMPILER_SUPPORTS_LAMBDA)
813	# define VMCPU_FF_IS_SET(pVCpu, fFlag) RT_BOOL((pVCpu)->fLocalForcedActions & (fFlag))
814	#else
815	# define VMCPU_FF_IS_SET(pVCpu, fFlag) \
816	([](PVMCPU a_pVCpu) -> bool \
817	{ \
818	AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
819	AssertCompile((fFlag) == RT_BIT_64(fFlag##_BIT)); \
820	return RT_BOOL(a_pVCpu->fLocalForcedActions & (fFlag)); \
821	}(pVCpu))
822	#endif
823
824	/** @def VM_FF_IS_ANY_SET
825	* Checks if one or more force action in the specified set is pending.
826	*
827	* @param pVM The cross context VM structure.
828	* @param fFlags The flags to check for.
829	* @sa VM_FF_IS_SET
830	*/
831	#define VM_FF_IS_ANY_SET(pVM, fFlags) RT_BOOL((pVM)->fGlobalForcedActions & (fFlags))
832
833	/** @def VMCPU_FF_IS_ANY_SET
834	* Checks if two or more force action flags in the specified set is set for the given VCPU.
835	*
836	* @param pVCpu The cross context virtual CPU structure.
837	* @param fFlags The flags to check for.
838	* @sa VMCPU_FF_IS_SET
839	*/
840	#define VMCPU_FF_IS_ANY_SET(pVCpu, fFlags) RT_BOOL((pVCpu)->fLocalForcedActions & (fFlags))
841
842	/** @def VM_FF_TEST_AND_CLEAR
843	* Checks if one (!) force action in the specified set is pending and clears it atomically
844	*
845	* @returns true if the bit was set.
846	* @returns false if the bit was clear.
847	* @param pVM The cross context VM structure.
848	* @param fFlag Flag constant to check and clear (_BIT is appended).
849	*/
850	#define VM_FF_TEST_AND_CLEAR(pVM, fFlag) (ASMAtomicBitTestAndClear(&(pVM)->fGlobalForcedActions, fFlag##_BIT))
851
852	/** @def VMCPU_FF_TEST_AND_CLEAR
853	* Checks if one (!) force action in the specified set is pending and clears it atomically
854	*
855	* @returns true if the bit was set.
856	* @returns false if the bit was clear.
857	* @param pVCpu The cross context virtual CPU structure.
858	* @param fFlag Flag constant to check and clear (_BIT is appended).
859	*/
860	#define VMCPU_FF_TEST_AND_CLEAR(pVCpu, fFlag) (ASMAtomicBitTestAndClear(&(pVCpu)->fLocalForcedActions, fFlag##_BIT))
861
862	/** @def VM_FF_IS_PENDING_EXCEPT
863	* Checks if one or more force action in the specified set is pending while one
864	* or more other ones are not.
865	*
866	* @param pVM The cross context VM structure.
867	* @param fFlags The flags to check for.
868	* @param fExcpt The flags that should not be set.
869	*/
870	#define VM_FF_IS_PENDING_EXCEPT(pVM, fFlags, fExcpt) \
871	( ((pVM)->fGlobalForcedActions & (fFlags)) && !((pVM)->fGlobalForcedActions & (fExcpt)) )
872
873	/** @def VM_IS_EMT
874	* Checks if the current thread is the emulation thread (EMT).
875	*
876	* @remark The ring-0 variation will need attention if we expand the ring-0
877	* code to let threads other than EMT mess around with the VM.
878	*/
879	#ifdef IN_RC
880	# define VM_IS_EMT(pVM) true
881	#else
882	# define VM_IS_EMT(pVM) (VMMGetCpu(pVM) != NULL)
883	#endif
884
885	/** @def VMCPU_IS_EMT
886	* Checks if the current thread is the emulation thread (EMT) for the specified
887	* virtual CPU.
888	*/
889	#ifdef IN_RC
890	# define VMCPU_IS_EMT(pVCpu) true
891	#else
892	# define VMCPU_IS_EMT(pVCpu) ((pVCpu) && ((pVCpu) == VMMGetCpu((pVCpu)->CTX_SUFF(pVM))))
893	#endif
894
895	/** @def VM_ASSERT_EMT
896	* Asserts that the current thread IS the emulation thread (EMT).
897	*/
898	#ifdef IN_RC
899	# define VM_ASSERT_EMT(pVM) Assert(VM_IS_EMT(pVM))
900	#elif defined(IN_RING0)
901	# define VM_ASSERT_EMT(pVM) Assert(VM_IS_EMT(pVM))
902	#else
903	# define VM_ASSERT_EMT(pVM) \
904	AssertMsg(VM_IS_EMT(pVM), \
905	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd\n", RTThreadNativeSelf(), VMR3GetVMCPUNativeThread(pVM)))
906	#endif
907
908	/** @def VMCPU_ASSERT_EMT
909	* Asserts that the current thread IS the emulation thread (EMT) of the
910	* specified virtual CPU.
911	*/
912	#ifdef IN_RC
913	# define VMCPU_ASSERT_EMT(pVCpu) Assert(VMCPU_IS_EMT(pVCpu))
914	#elif defined(IN_RING0)
915	# define VMCPU_ASSERT_EMT(pVCpu) AssertMsg(VMCPU_IS_EMT(pVCpu), \
916	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd idCpu=%u\n", \
917	RTThreadNativeSelf(), (pVCpu) ? (pVCpu)->hNativeThreadR0 : 0, \
918	(pVCpu) ? (pVCpu)->idCpu : 0))
919	#else
920	# define VMCPU_ASSERT_EMT(pVCpu) AssertMsg(VMCPU_IS_EMT(pVCpu), \
921	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd idCpu=%#x\n", \
922	RTThreadNativeSelf(), (pVCpu)->hNativeThread, (pVCpu)->idCpu))
923	#endif
924
925	/** @def VM_ASSERT_EMT_RETURN
926	* Asserts that the current thread IS the emulation thread (EMT) and returns if it isn't.
927	*/
928	#ifdef IN_RC
929	# define VM_ASSERT_EMT_RETURN(pVM, rc) AssertReturn(VM_IS_EMT(pVM), (rc))
930	#elif defined(IN_RING0)
931	# define VM_ASSERT_EMT_RETURN(pVM, rc) AssertReturn(VM_IS_EMT(pVM), (rc))
932	#else
933	# define VM_ASSERT_EMT_RETURN(pVM, rc) \
934	AssertMsgReturn(VM_IS_EMT(pVM), \
935	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd\n", RTThreadNativeSelf(), VMR3GetVMCPUNativeThread(pVM)), \
936	(rc))
937	#endif
938
939	/** @def VMCPU_ASSERT_EMT_RETURN
940	* Asserts that the current thread IS the emulation thread (EMT) and returns if it isn't.
941	*/
942	#ifdef IN_RC
943	# define VMCPU_ASSERT_EMT_RETURN(pVCpu, rc) AssertReturn(VMCPU_IS_EMT(pVCpu), (rc))
944	#elif defined(IN_RING0)
945	# define VMCPU_ASSERT_EMT_RETURN(pVCpu, rc) AssertReturn(VMCPU_IS_EMT(pVCpu), (rc))
946	#else
947	# define VMCPU_ASSERT_EMT_RETURN(pVCpu, rc) \
948	AssertMsgReturn(VMCPU_IS_EMT(pVCpu), \
949	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd idCpu=%#x\n", \
950	RTThreadNativeSelf(), (pVCpu)->hNativeThread, (pVCpu)->idCpu), \
951	(rc))
952	#endif
953
954	/** @def VMCPU_ASSERT_EMT_OR_GURU
955	* Asserts that the current thread IS the emulation thread (EMT) of the
956	* specified virtual CPU.
957	*/
958	#if defined(IN_RC) \|\| defined(IN_RING0)
959	# define VMCPU_ASSERT_EMT_OR_GURU(pVCpu) Assert( VMCPU_IS_EMT(pVCpu) \
960	\|\| pVCpu->CTX_SUFF(pVM)->enmVMState == VMSTATE_GURU_MEDITATION \
961	\|\| pVCpu->CTX_SUFF(pVM)->enmVMState == VMSTATE_GURU_MEDITATION_LS )
962	#else
963	# define VMCPU_ASSERT_EMT_OR_GURU(pVCpu) \
964	AssertMsg( VMCPU_IS_EMT(pVCpu) \
965	\|\| pVCpu->CTX_SUFF(pVM)->enmVMState == VMSTATE_GURU_MEDITATION \
966	\|\| pVCpu->CTX_SUFF(pVM)->enmVMState == VMSTATE_GURU_MEDITATION_LS, \
967	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd idCpu=%#x\n", \
968	RTThreadNativeSelf(), (pVCpu)->hNativeThread, (pVCpu)->idCpu))
969	#endif
970
971	/** @def VMCPU_ASSERT_EMT_OR_NOT_RUNNING
972	* Asserts that the current thread IS the emulation thread (EMT) of the
973	* specified virtual CPU or the VM is not running.
974	*/
975	#if defined(IN_RC) \|\| defined(IN_RING0)
976	# define VMCPU_ASSERT_EMT_OR_NOT_RUNNING(pVCpu) \
977	Assert( VMCPU_IS_EMT(pVCpu) \
978	\|\| !VM_IS_RUNNING_FOR_ASSERTIONS_ONLY((pVCpu)->CTX_SUFF(pVM)) )
979	#else
980	# define VMCPU_ASSERT_EMT_OR_NOT_RUNNING(pVCpu) \
981	AssertMsg( VMCPU_IS_EMT(pVCpu) \
982	\|\| !VM_IS_RUNNING_FOR_ASSERTIONS_ONLY((pVCpu)->CTX_SUFF(pVM)), \
983	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd idCpu=%#x\n", \
984	RTThreadNativeSelf(), (pVCpu)->hNativeThread, (pVCpu)->idCpu))
985	#endif
986
987	/** @def VMSTATE_IS_RUNNING
988	* Checks if the given state indicates a running VM.
989	*/
990	#define VMSTATE_IS_RUNNING(a_enmVMState) \
991	( (enmVMState) == VMSTATE_RUNNING \
992	\|\| (enmVMState) == VMSTATE_RUNNING_LS \
993	\|\| (enmVMState) == VMSTATE_RUNNING_FT )
994
995	/** @def VM_IS_RUNNING_FOR_ASSERTIONS_ONLY
996	* Checks if the VM is running.
997	* @note This is only for pure debug assertions. No AssertReturn or similar!
998	* @sa VMSTATE_IS_RUNNING
999	*/
1000	#define VM_IS_RUNNING_FOR_ASSERTIONS_ONLY(pVM) \
1001	( (pVM)->enmVMState == VMSTATE_RUNNING \
1002	\|\| (pVM)->enmVMState == VMSTATE_RUNNING_LS \
1003	\|\| (pVM)->enmVMState == VMSTATE_RUNNING_FT )
1004
1005	/** @def VM_ASSERT_IS_NOT_RUNNING
1006	* Asserts that the VM is not running.
1007	*/
1008	#if defined(IN_RC) \|\| defined(IN_RING0)
1009	#define VM_ASSERT_IS_NOT_RUNNING(pVM) Assert(!VM_IS_RUNNING_FOR_ASSERTIONS_ONLY(pVM))
1010	#else
1011	#define VM_ASSERT_IS_NOT_RUNNING(pVM) AssertMsg(!VM_IS_RUNNING_FOR_ASSERTIONS_ONLY(pVM), \
1012	("VM is running. enmVMState=%d\n", (pVM)->enmVMState))
1013	#endif
1014
1015	/** @def VM_ASSERT_EMT0
1016	* Asserts that the current thread IS emulation thread \#0 (EMT0).
1017	*/
1018	#define VM_ASSERT_EMT0(pVM) VMCPU_ASSERT_EMT(&(pVM)->aCpus[0])
1019
1020	/** @def VM_ASSERT_EMT0_RETURN
1021	* Asserts that the current thread IS emulation thread \#0 (EMT0) and returns if
1022	* it isn't.
1023	*/
1024	#define VM_ASSERT_EMT0_RETURN(pVM, rc) VMCPU_ASSERT_EMT_RETURN(&(pVM)->aCpus[0], (rc))
1025
1026
1027	/**
1028	* Asserts that the current thread is NOT the emulation thread.
1029	*/
1030	#define VM_ASSERT_OTHER_THREAD(pVM) \
1031	AssertMsg(!VM_IS_EMT(pVM), ("Not other thread!!\n"))
1032
1033
1034	/** @def VM_ASSERT_STATE
1035	* Asserts a certain VM state.
1036	*/
1037	#define VM_ASSERT_STATE(pVM, _enmState) \
1038	AssertMsg((pVM)->enmVMState == (_enmState), \
1039	("state %s, expected %s\n", VMGetStateName((pVM)->enmVMState), VMGetStateName(_enmState)))
1040
1041	/** @def VM_ASSERT_STATE_RETURN
1042	* Asserts a certain VM state and returns if it doesn't match.
1043	*/
1044	#define VM_ASSERT_STATE_RETURN(pVM, _enmState, rc) \
1045	AssertMsgReturn((pVM)->enmVMState == (_enmState), \
1046	("state %s, expected %s\n", VMGetStateName((pVM)->enmVMState), VMGetStateName(_enmState)), \
1047	(rc))
1048
1049	/** @def VM_IS_VALID_EXT
1050	* Asserts a the VM handle is valid for external access, i.e. not being destroy
1051	* or terminated. */
1052	#define VM_IS_VALID_EXT(pVM) \
1053	( RT_VALID_ALIGNED_PTR(pVM, PAGE_SIZE) \
1054	&& ( (unsigned)(pVM)->enmVMState < (unsigned)VMSTATE_DESTROYING \
1055	\|\| ( (unsigned)(pVM)->enmVMState == (unsigned)VMSTATE_DESTROYING \
1056	&& VM_IS_EMT(pVM))) )
1057
1058	/** @def VM_ASSERT_VALID_EXT_RETURN
1059	* Asserts a the VM handle is valid for external access, i.e. not being
1060	* destroy or terminated.
1061	*/
1062	#define VM_ASSERT_VALID_EXT_RETURN(pVM, rc) \
1063	AssertMsgReturn(VM_IS_VALID_EXT(pVM), \
1064	("pVM=%p state %s\n", (pVM), RT_VALID_ALIGNED_PTR(pVM, PAGE_SIZE) \
1065	? VMGetStateName(pVM->enmVMState) : ""), \
1066	(rc))
1067
1068	/** @def VMCPU_ASSERT_VALID_EXT_RETURN
1069	* Asserts a the VMCPU handle is valid for external access, i.e. not being
1070	* destroy or terminated.
1071	*/
1072	#define VMCPU_ASSERT_VALID_EXT_RETURN(pVCpu, rc) \
1073	AssertMsgReturn( RT_VALID_ALIGNED_PTR(pVCpu, 64) \
1074	&& RT_VALID_ALIGNED_PTR((pVCpu)->CTX_SUFF(pVM), PAGE_SIZE) \
1075	&& (unsigned)(pVCpu)->CTX_SUFF(pVM)->enmVMState < (unsigned)VMSTATE_DESTROYING, \
1076	("pVCpu=%p pVM=%p state %s\n", (pVCpu), RT_VALID_ALIGNED_PTR(pVCpu, 64) ? (pVCpu)->CTX_SUFF(pVM) : NULL, \
1077	RT_VALID_ALIGNED_PTR(pVCpu, 64) && RT_VALID_ALIGNED_PTR((pVCpu)->CTX_SUFF(pVM), PAGE_SIZE) \
1078	? VMGetStateName((pVCpu)->pVMR3->enmVMState) : ""), \
1079	(rc))
1080
1081	#endif /* !VBOX_FOR_DTRACE_LIB */
1082
1083
1084	/**
1085	* Helper that HM and NEM uses for safely modifying VM::bMainExecutionEngine.
1086	*
1087	* ONLY HM and NEM MAY USE THIS!
1088	*
1089	* @param a_pVM The cross context VM structure.
1090	* @param a_bValue The new value.
1091	* @internal
1092	*/
1093	#define VM_SET_MAIN_EXECUTION_ENGINE(a_pVM, a_bValue) \
1094	do { \
1095	const_cast<uint8_t >(&(a_pVM)->bMainExecutionEngine) = (a_bValue); \
1096	ASMCompilerBarrier(); /* just to be on the safe side */ \
1097	} while (0)
1098
1099	/**
1100	* Checks whether raw-mode is used.
1101	*
1102	* @retval true if either is used.
1103	* @retval false if software virtualization (raw-mode) is used.
1104	*
1105	* @param a_pVM The cross context VM structure.
1106	* @sa VM_IS_HM_OR_NEM_ENABLED, VM_IS_HM_ENABLED, VM_IS_NEM_ENABLED.
1107	* @internal
1108	*/
1109	#ifdef VBOX_WITH_RAW_MODE
1110	# define VM_IS_RAW_MODE_ENABLED(a_pVM) ((a_pVM)->bMainExecutionEngine == VM_EXEC_ENGINE_RAW_MODE)
1111	#else
1112	# define VM_IS_RAW_MODE_ENABLED(a_pVM) (false)
1113	#endif
1114
1115	/**
1116	* Checks whether HM (VT-x/AMD-V) or NEM is being used by this VM.
1117	*
1118	* @retval true if either is used.
1119	* @retval false if software virtualization (raw-mode) is used.
1120	*
1121	* @param a_pVM The cross context VM structure.
1122	* @sa VM_IS_RAW_MODE_ENABLED, VM_IS_HM_ENABLED, VM_IS_NEM_ENABLED.
1123	* @internal
1124	*/
1125	#define VM_IS_HM_OR_NEM_ENABLED(a_pVM) ((a_pVM)->bMainExecutionEngine != VM_EXEC_ENGINE_RAW_MODE)
1126
1127	/**
1128	* Checks whether HM is being used by this VM.
1129	*
1130	* @retval true if HM (VT-x/AMD-v) is used.
1131	* @retval false if not.
1132	*
1133	* @param a_pVM The cross context VM structure.
1134	* @sa VM_IS_NEM_ENABLED, VM_IS_RAW_MODE_ENABLED, VM_IS_HM_OR_NEM_ENABLED.
1135	* @internal
1136	*/
1137	#define VM_IS_HM_ENABLED(a_pVM) ((a_pVM)->bMainExecutionEngine == VM_EXEC_ENGINE_HW_VIRT)
1138
1139	/**
1140	* Checks whether NEM is being used by this VM.
1141	*
1142	* @retval true if a native hypervisor API is used.
1143	* @retval false if not.
1144	*
1145	* @param a_pVM The cross context VM structure.
1146	* @sa VM_IS_HM_ENABLED, VM_IS_RAW_MODE_ENABLED, VM_IS_HM_OR_NEM_ENABLED.
1147	* @internal
1148	*/
1149	#define VM_IS_NEM_ENABLED(a_pVM) ((a_pVM)->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API)
1150
1151
1152	/**
1153	* The cross context VM structure.
1154	*
1155	* It contains all the VM data which have to be available in all contexts.
1156	* Even if it contains all the data the idea is to use APIs not to modify all
1157	* the members all around the place. Therefore we make use of unions to hide
1158	* everything which isn't local to the current source module. This means we'll
1159	* have to pay a little bit of attention when adding new members to structures
1160	* in the unions and make sure to keep the padding sizes up to date.
1161	*
1162	* Run 'kmk run-struct-tests' (from src/VBox/VMM if you like) after updating!
1163	*/
1164	typedef struct VM
1165	{
1166	/** The state of the VM.
1167	* This field is read only to everyone except the VM and EM. */
1168	VMSTATE volatile enmVMState;
1169	/** Forced action flags.
1170	* See the VM_FF_* \#defines. Updated atomically.
1171	*/
1172	volatile uint32_t fGlobalForcedActions;
1173	/** Pointer to the array of page descriptors for the VM structure allocation. */
1174	R3PTRTYPE(PSUPPAGE) paVMPagesR3;
1175	/** Session handle. For use when calling SUPR0 APIs. */
1176	PSUPDRVSESSION pSession;
1177	/** Pointer to the ring-3 VM structure. */
1178	PUVM pUVM;
1179	/** Ring-3 Host Context VM Pointer. */
1180	R3PTRTYPE(struct VM *) pVMR3;
1181	/** Ring-0 Host Context VM Pointer. */
1182	R0PTRTYPE(struct VM *) pVMR0;
1183	/** Raw-mode Context VM Pointer. */
1184	RCPTRTYPE(struct VM *) pVMRC;
1185
1186	/** The GVM VM handle. Only the GVM should modify this field. */
1187	uint32_t hSelf;
1188	/** Number of virtual CPUs. */
1189	uint32_t cCpus;
1190	/** CPU excution cap (1-100) */
1191	uint32_t uCpuExecutionCap;
1192
1193	/** Size of the VM structure including the VMCPU array. */
1194	uint32_t cbSelf;
1195
1196	/** Offset to the VMCPU array starting from beginning of this structure. */
1197	uint32_t offVMCPU;
1198
1199	/**
1200	* VMMSwitcher assembly entry point returning to host context.
1201	*
1202	* Depending on how the host handles the rc status given in @a eax, this may
1203	* return and let the caller resume whatever it was doing prior to the call.
1204	*
1205	*
1206	* @param eax The return code, register.
1207	* @remark Assume interrupts disabled.
1208	* @remark This method pointer lives here because TRPM needs it.
1209	*/
1210	RTRCPTR pfnVMMRCToHostAsm/(int32_t eax)/;
1211
1212	/**
1213	* VMMSwitcher assembly entry point returning to host context without saving the
1214	* raw-mode context (hyper) registers.
1215	*
1216	* Unlike pfnVMMRC2HCAsm, this will not return to the caller. Instead it
1217	* expects the caller to save a RC context in CPUM where one might return if the
1218	* return code indicate that this is possible.
1219	*
1220	* This method pointer lives here because TRPM needs it.
1221	*
1222	* @param eax The return code, register.
1223	* @remark Assume interrupts disabled.
1224	* @remark This method pointer lives here because TRPM needs it.
1225	*/
1226	RTRCPTR pfnVMMRCToHostAsmNoReturn/(int32_t eax)/;
1227
1228	/** @name Various items that are frequently accessed.
1229	* @{ */
1230	/** The main execution engine, VM_EXEC_ENGINE_XXX.
1231	* This is set early during vmR3InitRing3 by HM or NEM. */
1232	uint8_t const bMainExecutionEngine;
1233
1234	/** Whether to recompile user mode code or run it raw/hm/nem.
1235	* In non-raw-mode both fRecompileUser and fRecompileSupervisor must be set
1236	* to recompiler stuff. */
1237	bool fRecompileUser;
1238	/** Whether to recompile supervisor mode code or run it raw/hm/nem.
1239	* In non-raw-mode both fRecompileUser and fRecompileSupervisor must be set
1240	* to recompiler stuff. */
1241	bool fRecompileSupervisor;
1242	/** Whether raw mode supports ring-1 code or not.
1243	* This will be cleared when not in raw-mode. */
1244	bool fRawRing1Enabled;
1245	/** PATM enabled flag.
1246	* This is placed here for performance reasons.
1247	* This will be cleared when not in raw-mode. */
1248	bool fPATMEnabled;
1249	/** CSAM enabled flag.
1250	* This is placed here for performance reasons.
1251	* This will be cleared when not in raw-mode. */
1252	bool fCSAMEnabled;
1253
1254	/** Hardware VM support is available and enabled.
1255	* Determined very early during init.
1256	* This is placed here for performance reasons.
1257	* @todo obsoleted by bMainExecutionEngine, eliminate. */
1258	bool fHMEnabled;
1259	/** Hardware VM support requires a minimal raw-mode context.
1260	* This is never set on 64-bit hosts, only 32-bit hosts requires it. */
1261	bool fHMNeedRawModeCtx;
1262
1263	/** Set when this VM is the master FT node.
1264	* @todo This doesn't need to be here, FTM should store it in it's own
1265	* structures instead. */
1266	bool fFaultTolerantMaster;
1267	/** Large page enabled flag.
1268	* @todo This doesn't need to be here, PGM should store it in it's own
1269	* structures instead. */
1270	bool fUseLargePages;
1271	/** @} */
1272
1273	/** Alignment padding. */
1274	uint8_t uPadding1[2];
1275
1276	/** @name Debugging
1277	* @{ */
1278	/** Raw-mode Context VM Pointer. */
1279	RCPTRTYPE(RTTRACEBUF) hTraceBufRC;
1280	/** Ring-3 Host Context VM Pointer. */
1281	R3PTRTYPE(RTTRACEBUF) hTraceBufR3;
1282	/** Ring-0 Host Context VM Pointer. */
1283	R0PTRTYPE(RTTRACEBUF) hTraceBufR0;
1284	/** @} */
1285
1286	#if HC_ARCH_BITS == 32
1287	/** Alignment padding. */
1288	uint32_t uPadding2;
1289	#endif
1290
1291	/** @name Switcher statistics (remove)
1292	* @{ */
1293	/** Profiling the total time from Qemu to GC. */
1294	STAMPROFILEADV StatTotalQemuToGC;
1295	/** Profiling the total time from GC to Qemu. */
1296	STAMPROFILEADV StatTotalGCToQemu;
1297	/** Profiling the total time spent in GC. */
1298	STAMPROFILEADV StatTotalInGC;
1299	/** Profiling the total time spent not in Qemu. */
1300	STAMPROFILEADV StatTotalInQemu;
1301	/** Profiling the VMMSwitcher code for going to GC. */
1302	STAMPROFILEADV StatSwitcherToGC;
1303	/** Profiling the VMMSwitcher code for going to HC. */
1304	STAMPROFILEADV StatSwitcherToHC;
1305	STAMPROFILEADV StatSwitcherSaveRegs;
1306	STAMPROFILEADV StatSwitcherSysEnter;
1307	STAMPROFILEADV StatSwitcherDebug;
1308	STAMPROFILEADV StatSwitcherCR0;
1309	STAMPROFILEADV StatSwitcherCR4;
1310	STAMPROFILEADV StatSwitcherJmpCR3;
1311	STAMPROFILEADV StatSwitcherRstrRegs;
1312	STAMPROFILEADV StatSwitcherLgdt;
1313	STAMPROFILEADV StatSwitcherLidt;
1314	STAMPROFILEADV StatSwitcherLldt;
1315	STAMPROFILEADV StatSwitcherTSS;
1316	/** @} */
1317
1318	/** Padding - the unions must be aligned on a 64 bytes boundary and the unions
1319	* must start at the same offset on both 64-bit and 32-bit hosts. */
1320	uint8_t abAlignment3[(HC_ARCH_BITS == 32 ? 24 : 0) + 40];
1321
1322	/** CPUM part. */
1323	union
1324	{
1325	#ifdef ___CPUMInternal_h
1326	struct CPUM s;
1327	#endif
1328	#ifdef ___VBox_vmm_cpum_h
1329	/** Read only info exposed about the host and guest CPUs. */
1330	struct
1331	{
1332	/** Padding for hidden fields. */
1333	uint8_t abHidden0[64];
1334	/** Host CPU feature information. */
1335	CPUMFEATURES HostFeatures;
1336	/** Guest CPU feature information. */
1337	CPUMFEATURES GuestFeatures;
1338	} const ro;
1339	#endif
1340	uint8_t padding[1536]; /* multiple of 64 */
1341	} cpum;
1342
1343	/** VMM part. */
1344	union
1345	{
1346	#ifdef ___VMMInternal_h
1347	struct VMM s;
1348	#endif
1349	uint8_t padding[1600]; /* multiple of 64 */
1350	} vmm;
1351
1352	/** PGM part. */
1353	union
1354	{
1355	#ifdef ___PGMInternal_h
1356	struct PGM s;
1357	#endif
1358	uint8_t padding[40962+6080]; / multiple of 64 */
1359	} pgm;
1360
1361	/** HM part. */
1362	union
1363	{
1364	#ifdef ___HMInternal_h
1365	struct HM s;
1366	#endif
1367	uint8_t padding[5440]; /* multiple of 64 */
1368	} hm;
1369
1370	/** TRPM part. */
1371	union
1372	{
1373	#ifdef ___TRPMInternal_h
1374	struct TRPM s;
1375	#endif
1376	uint8_t padding[5248]; /* multiple of 64 */
1377	} trpm;
1378
1379	/** SELM part. */
1380	union
1381	{
1382	#ifdef ___SELMInternal_h
1383	struct SELM s;
1384	#endif
1385	uint8_t padding[768]; /* multiple of 64 */
1386	} selm;
1387
1388	/** MM part. */
1389	union
1390	{
1391	#ifdef ___MMInternal_h
1392	struct MM s;
1393	#endif
1394	uint8_t padding[192]; /* multiple of 64 */
1395	} mm;
1396
1397	/** PDM part. */
1398	union
1399	{
1400	#ifdef ___PDMInternal_h
1401	struct PDM s;
1402	#endif
1403	uint8_t padding[1920]; /* multiple of 64 */
1404	} pdm;
1405
1406	/** IOM part. */
1407	union
1408	{
1409	#ifdef ___IOMInternal_h
1410	struct IOM s;
1411	#endif
1412	uint8_t padding[896]; /* multiple of 64 */
1413	} iom;
1414
1415	/** EM part. */
1416	union
1417	{
1418	#ifdef ___EMInternal_h
1419	struct EM s;
1420	#endif
1421	uint8_t padding[256]; /* multiple of 64 */
1422	} em;
1423
1424	/** NEM part. */
1425	union
1426	{
1427	#ifdef ___NEMInternal_h
1428	struct NEM s;
1429	#endif
1430	uint8_t padding[128]; /* multiple of 64 */
1431	} nem;
1432
1433	/** TM part. */
1434	union
1435	{
1436	#ifdef ___TMInternal_h
1437	struct TM s;
1438	#endif
1439	uint8_t padding[2496]; /* multiple of 64 */
1440	} tm;
1441
1442	/** DBGF part. */
1443	union
1444	{
1445	#ifdef ___DBGFInternal_h
1446	struct DBGF s;
1447	#endif
1448	#ifdef ___VBox_vmm_dbgf_h
1449	/** Read only info exposed about interrupt breakpoints and selected events. */
1450	struct
1451	{
1452	/** Bitmap of enabled hardware interrupt breakpoints. */
1453	uint32_t bmHardIntBreakpoints[256 / 32];
1454	/** Bitmap of enabled software interrupt breakpoints. */
1455	uint32_t bmSoftIntBreakpoints[256 / 32];
1456	/** Bitmap of selected events.
1457	* This includes non-selectable events too for simplicity, we maintain the
1458	* state for some of these, as it may come in handy. */
1459	uint64_t bmSelectedEvents[(DBGFEVENT_END + 63) / 64];
1460	/** Enabled hardware interrupt breakpoints. */
1461	uint32_t cHardIntBreakpoints;
1462	/** Enabled software interrupt breakpoints. */
1463	uint32_t cSoftIntBreakpoints;
1464	/** The number of selected events. */
1465	uint32_t cSelectedEvents;
1466	/** The number of enabled hardware breakpoints. */
1467	uint8_t cEnabledHwBreakpoints;
1468	/** The number of enabled hardware I/O breakpoints. */
1469	uint8_t cEnabledHwIoBreakpoints;
1470	/** The number of enabled INT3 breakpoints. */
1471	uint8_t cEnabledInt3Breakpoints;
1472	uint8_t abPadding[1]; /*< Unused padding space up for grabs. /
1473	} const ro;
1474	#endif
1475	uint8_t padding[2432]; /* multiple of 64 */
1476	} dbgf;
1477
1478	/** SSM part. */
1479	union
1480	{
1481	#ifdef ___SSMInternal_h
1482	struct SSM s;
1483	#endif
1484	uint8_t padding[128]; /* multiple of 64 */
1485	} ssm;
1486
1487	/** FTM part. */
1488	union
1489	{
1490	#ifdef ___FTMInternal_h
1491	struct FTM s;
1492	#endif
1493	uint8_t padding[512]; /* multiple of 64 */
1494	} ftm;
1495
1496	#ifdef VBOX_WITH_RAW_MODE
1497	/** PATM part. */
1498	union
1499	{
1500	# ifdef ___PATMInternal_h
1501	struct PATM s;
1502	# endif
1503	uint8_t padding[768]; /* multiple of 64 */
1504	} patm;
1505
1506	/** CSAM part. */
1507	union
1508	{
1509	# ifdef ___CSAMInternal_h
1510	struct CSAM s;
1511	# endif
1512	uint8_t padding[1088]; /* multiple of 64 */
1513	} csam;
1514	#endif
1515
1516	#ifdef VBOX_WITH_REM
1517	/** REM part. */
1518	union
1519	{
1520	# ifdef ___REMInternal_h
1521	struct REM s;
1522	# endif
1523	uint8_t padding[0x11100]; /* multiple of 64 */
1524	} rem;
1525	#endif
1526
1527	union
1528	{
1529	#ifdef ___GIMInternal_h
1530	struct GIM s;
1531	#endif
1532	uint8_t padding[448]; /* multiple of 64 */
1533	} gim;
1534
1535	union
1536	{
1537	#ifdef ___APICInternal_h
1538	struct APIC s;
1539	#endif
1540	uint8_t padding[128]; /* multiple of 8 */
1541	} apic;
1542
1543	/* ---- begin small stuff ---- */
1544
1545	/** VM part. */
1546	union
1547	{
1548	#ifdef ___VMInternal_h
1549	struct VMINT s;
1550	#endif
1551	uint8_t padding[32]; /* multiple of 8 */
1552	} vm;
1553
1554	/** CFGM part. */
1555	union
1556	{
1557	#ifdef ___CFGMInternal_h
1558	struct CFGM s;
1559	#endif
1560	uint8_t padding[8]; /* multiple of 8 */
1561	} cfgm;
1562
1563	/** Padding for aligning the cpu array on a page boundary. */
1564	#if defined(VBOX_WITH_REM) && defined(VBOX_WITH_RAW_MODE)
1565	uint8_t abAlignment2[3670];
1566	#elif defined(VBOX_WITH_REM) && !defined(VBOX_WITH_RAW_MODE)
1567	uint8_t abAlignment2[1430];
1568	#elif !defined(VBOX_WITH_REM) && defined(VBOX_WITH_RAW_MODE)
1569	uint8_t abAlignment2[3926];
1570	#else
1571	uint8_t abAlignment2[1686];
1572	#endif
1573
1574	/* ---- end small stuff ---- */
1575
1576	/** VMCPU array for the configured number of virtual CPUs.
1577	* Must be aligned on a page boundary for TLB hit reasons as well as
1578	* alignment of VMCPU members. */
1579	VMCPU aCpus[1];
1580	} VM;
1581
1582
1583	#ifdef IN_RC
1584	RT_C_DECLS_BEGIN
1585
1586	/** The VM structure.
1587	* This is imported from the VMMRCBuiltin module, i.e. it's a one of those magic
1588	* globals which we should avoid using.
1589	*/
1590	extern DECLIMPORT(VM) g_VM;
1591
1592	RT_C_DECLS_END
1593	#endif
1594
1595	/** @} */
1596
1597	#endif
1598

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source: vbox/trunk/include/VBox/vmm/vm.h@ 76507

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