vm.h@ 78431

Last change on this file since 78431 was 78431, checked in by vboxsync, 6 years ago
VMM: Started refactoring GVM & VM structures for bugref:9217
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1	/** @file
2	* VM - The Virtual Machine, data.
3	*/
4
5	/*
6	* Copyright (C) 2006-2019 Oracle Corporation
7	*
8	* This file is part of VirtualBox Open Source Edition (OSE), as
9	* available from http://www.virtualbox.org. This file is free software;
10	* you can redistribute it and/or modify it under the terms of the GNU
11	* General Public License (GPL) as published by the Free Software
12	* Foundation, in version 2 as it comes in the "COPYING" file of the
13	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15	*
16	* The contents of this file may alternatively be used under the terms
17	* of the Common Development and Distribution License Version 1.0
18	* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19	* VirtualBox OSE distribution, in which case the provisions of the
20	* CDDL are applicable instead of those of the GPL.
21	*
22	* You may elect to license modified versions of this file under the
23	* terms and conditions of either the GPL or the CDDL or both.
24	*/
25
26	#ifndef VBOX_INCLUDED_vmm_vm_h
27	#define VBOX_INCLUDED_vmm_vm_h
28	#ifndef RT_WITHOUT_PRAGMA_ONCE
29	# pragma once
30	#endif
31
32	#ifndef VBOX_FOR_DTRACE_LIB
33	# include <iprt/param.h>
34	# include <VBox/param.h>
35	# include <VBox/types.h>
36	# include <VBox/vmm/cpum.h>
37	# include <VBox/vmm/stam.h>
38	# include <VBox/vmm/vmapi.h>
39	# include <VBox/vmm/vmm.h>
40	# include <VBox/sup.h>
41	#else
42	# pragma D depends_on library vbox-types.d
43	# pragma D depends_on library CPUMInternal.d
44	# define VMM_INCLUDED_SRC_include_CPUMInternal_h
45	#endif
46
47
48
49	/** @defgroup grp_vm The Virtual Machine
50	* @ingroup grp_vmm
51	* @{
52	*/
53
54	/**
55	* The state of a Virtual CPU.
56	*
57	* The basic state indicated here is whether the CPU has been started or not. In
58	* addition, there are sub-states when started for assisting scheduling (GVMM
59	* mostly).
60	*
61	* The transition out of the STOPPED state is done by a vmR3PowerOn.
62	* The transition back to the STOPPED state is done by vmR3PowerOff.
63	*
64	* (Alternatively we could let vmR3PowerOn start CPU 0 only and let the SPIP
65	* handling switch on the other CPUs. Then vmR3Reset would stop all but CPU 0.)
66	*/
67	typedef enum VMCPUSTATE
68	{
69	/** The customary invalid zero. */
70	VMCPUSTATE_INVALID = 0,
71
72	/** Virtual CPU has not yet been started. */
73	VMCPUSTATE_STOPPED,
74
75	/** CPU started. */
76	VMCPUSTATE_STARTED,
77	/** CPU started in HM context. */
78	VMCPUSTATE_STARTED_HM,
79	/** Executing guest code and can be poked (RC or STI bits of HM). */
80	VMCPUSTATE_STARTED_EXEC,
81	/** Executing guest code in the recompiler. */
82	VMCPUSTATE_STARTED_EXEC_REM,
83	/** Executing guest code using NEM. */
84	VMCPUSTATE_STARTED_EXEC_NEM,
85	VMCPUSTATE_STARTED_EXEC_NEM_WAIT,
86	VMCPUSTATE_STARTED_EXEC_NEM_CANCELED,
87	/** Halted. */
88	VMCPUSTATE_STARTED_HALTED,
89
90	/** The end of valid virtual CPU states. */
91	VMCPUSTATE_END,
92
93	/** Ensure 32-bit type. */
94	VMCPUSTATE_32BIT_HACK = 0x7fffffff
95	} VMCPUSTATE;
96
97	/** Enables 64-bit FFs. */
98	#define VMCPU_WITH_64_BIT_FFS
99
100
101	/**
102	* The cross context virtual CPU structure.
103	*
104	* Run 'kmk run-struct-tests' (from src/VBox/VMM if you like) after updating!
105	*/
106	typedef struct VMCPU
107	{
108	/** @name Volatile per-cpu data.
109	* @{ */
110	/** Per CPU forced action.
111	* See the VMCPU_FF_* \#defines. Updated atomically. */
112	#ifdef VMCPU_WITH_64_BIT_FFS
113	uint64_t volatile fLocalForcedActions;
114	#else
115	uint32_t volatile fLocalForcedActions;
116	uint32_t fForLocalForcedActionsExpansion;
117	#endif
118	/** The CPU state. */
119	VMCPUSTATE volatile enmState;
120
121	/** Which host CPU ID is this EMT running on.
122	* Only valid when in RC or HMR0 with scheduling disabled. */
123	RTCPUID volatile idHostCpu;
124	/** The CPU set index corresponding to idHostCpu, UINT32_MAX if not valid.
125	* @remarks Best to make sure iHostCpuSet shares cache line with idHostCpu! */
126	uint32_t volatile iHostCpuSet;
127	/** Padding up to 64 bytes. */
128	uint8_t abAlignment0[64 - 20];
129	/** @} */
130
131	/** IEM part.
132	* @remarks This comes first as it allows the use of 8-bit immediates for the
133	* first 64 bytes of the structure, reducing code size a wee bit. */
134	#ifdef VMM_INCLUDED_SRC_include_IEMInternal_h /* For PDB hacking. */
135	union VMCPUUNIONIEMFULL
136	#else
137	union VMCPUUNIONIEMSTUB
138	#endif
139	{
140	#ifdef VMM_INCLUDED_SRC_include_IEMInternal_h
141	struct IEMCPU s;
142	#endif
143	uint8_t padding[18496]; /* multiple of 64 */
144	} iem;
145
146	/** @name Static per-cpu data.
147	* (Putting this after IEM, hoping that it's less frequently used than it.)
148	* @{ */
149	/** The CPU ID.
150	* This is the index into the VM::aCpu array. */
151	VMCPUID idCpu;
152	/** Raw-mode Context VM Pointer. */
153	PVMRC pVMRC;
154	/** Ring-3 Host Context VM Pointer. */
155	PVMR3 pVMR3;
156	/** Ring-0 Host Context VM Pointer. */
157	PVMR0 pVMR0;
158	/** Pointer to the ring-3 UVMCPU structure. */
159	PUVMCPU pUVCpu;
160	/** The native thread handle. */
161	RTNATIVETHREAD hNativeThread;
162	/** The native R0 thread handle. (different from the R3 handle!) */
163	RTNATIVETHREAD hNativeThreadR0;
164	/** Align the structures below bit on a 64-byte boundary and make sure it starts
165	* at the same offset in both 64-bit and 32-bit builds.
166	*
167	* @remarks The alignments of the members that are larger than 48 bytes should be
168	* 64-byte for cache line reasons. structs containing small amounts of
169	* data could be lumped together at the end with a < 64 byte padding
170	* following it (to grow into and align the struct size).
171	*/
172	uint8_t abAlignment1[64 - 4 - 4 - 5 * (HC_ARCH_BITS == 64 ? 8 : 4)];
173	/** @} */
174
175	/** HM part. */
176	union VMCPUUNIONHM
177	{
178	#ifdef VMM_INCLUDED_SRC_include_HMInternal_h
179	struct HMCPU s;
180	#endif
181	uint8_t padding[5888]; /* multiple of 64 */
182	} hm;
183
184	/** NEM part. */
185	union VMCPUUNIONNEM
186	{
187	#ifdef VMM_INCLUDED_SRC_include_NEMInternal_h
188	struct NEMCPU s;
189	#endif
190	uint8_t padding[512]; /* multiple of 64 */
191	} nem;
192
193	/** TRPM part. */
194	union VMCPUUNIONTRPM
195	{
196	#ifdef VMM_INCLUDED_SRC_include_TRPMInternal_h
197	struct TRPMCPU s;
198	#endif
199	uint8_t padding[128]; /* multiple of 64 */
200	} trpm;
201
202	/** TM part. */
203	union VMCPUUNIONTM
204	{
205	#ifdef VMM_INCLUDED_SRC_include_TMInternal_h
206	struct TMCPU s;
207	#endif
208	uint8_t padding[384]; /* multiple of 64 */
209	} tm;
210
211	/** VMM part. */
212	union VMCPUUNIONVMM
213	{
214	#ifdef VMM_INCLUDED_SRC_include_VMMInternal_h
215	struct VMMCPU s;
216	#endif
217	uint8_t padding[896]; /* multiple of 64 */
218	} vmm;
219
220	/** PDM part. */
221	union VMCPUUNIONPDM
222	{
223	#ifdef VMM_INCLUDED_SRC_include_PDMInternal_h
224	struct PDMCPU s;
225	#endif
226	uint8_t padding[256]; /* multiple of 64 */
227	} pdm;
228
229	/** IOM part. */
230	union VMCPUUNIONIOM
231	{
232	#ifdef VMM_INCLUDED_SRC_include_IOMInternal_h
233	struct IOMCPU s;
234	#endif
235	uint8_t padding[512]; /* multiple of 64 */
236	} iom;
237
238	/** DBGF part.
239	* @todo Combine this with other tiny structures. */
240	union VMCPUUNIONDBGF
241	{
242	#ifdef VMM_INCLUDED_SRC_include_DBGFInternal_h
243	struct DBGFCPU s;
244	#endif
245	uint8_t padding[256]; /* multiple of 64 */
246	} dbgf;
247
248	/** GIM part. */
249	union VMCPUUNIONGIM
250	{
251	#ifdef VMM_INCLUDED_SRC_include_GIMInternal_h
252	struct GIMCPU s;
253	#endif
254	uint8_t padding[512]; /* multiple of 64 */
255	} gim;
256
257	/** APIC part. */
258	union VMCPUUNIONAPIC
259	{
260	#ifdef VMM_INCLUDED_SRC_include_APICInternal_h
261	struct APICCPU s;
262	#endif
263	uint8_t padding[1792]; /* multiple of 64 */
264	} apic;
265
266	/*
267	* Some less frequently used global members that doesn't need to take up
268	* precious space at the head of the structure.
269	*/
270
271	/** Trace groups enable flags. */
272	uint32_t fTraceGroups; /* 64 / 44 */
273	/** State data for use by ad hoc profiling. */
274	uint32_t uAdHoc;
275	/** Profiling samples for use by ad hoc profiling. */
276	STAMPROFILEADV aStatAdHoc[8]; /* size: 408 = 320 /
277
278	/** Align the following members on page boundary. */
279	uint8_t abAlignment2[2680];
280
281	/** PGM part. */
282	union VMCPUUNIONPGM
283	{
284	#ifdef VMM_INCLUDED_SRC_include_PGMInternal_h
285	struct PGMCPU s;
286	#endif
287	uint8_t padding[4096]; /* multiple of 4096 */
288	} pgm;
289
290	/** CPUM part. */
291	union VMCPUUNIONCPUM
292	{
293	#ifdef VMM_INCLUDED_SRC_include_CPUMInternal_h
294	struct CPUMCPU s;
295	#endif
296	#ifdef VMCPU_INCL_CPUM_GST_CTX
297	/** The guest CPUM context for direct use by execution engines.
298	* This is not for general consumption, but for HM, REM, IEM, and maybe a few
299	* others. The rest will use the function based CPUM API. */
300	CPUMCTX GstCtx;
301	#endif
302	uint8_t padding[4096]; /* multiple of 4096 */
303	} cpum;
304
305	/** EM part. */
306	union VMCPUUNIONEM
307	{
308	#ifdef VMM_INCLUDED_SRC_include_EMInternal_h
309	struct EMCPU s;
310	#endif
311	uint8_t padding[40960]; /* multiple of 4096 */
312	} em;
313	} VMCPU;
314
315
316	#ifndef VBOX_FOR_DTRACE_LIB
317
318	/** @name Operations on VMCPU::enmState
319	* @{ */
320	/** Gets the VMCPU state. */
321	#define VMCPU_GET_STATE(pVCpu) ( (pVCpu)->enmState )
322	/** Sets the VMCPU state. */
323	#define VMCPU_SET_STATE(pVCpu, enmNewState) \
324	ASMAtomicWriteU32((uint32_t volatile *)&(pVCpu)->enmState, (enmNewState))
325	/** Cmpares and sets the VMCPU state. */
326	#define VMCPU_CMPXCHG_STATE(pVCpu, enmNewState, enmOldState) \
327	ASMAtomicCmpXchgU32((uint32_t volatile *)&(pVCpu)->enmState, (enmNewState), (enmOldState))
328	/** Checks the VMCPU state. */
329	#ifdef VBOX_STRICT
330	# define VMCPU_ASSERT_STATE(pVCpu, enmExpectedState) \
331	do { \
332	VMCPUSTATE enmState = VMCPU_GET_STATE(pVCpu); \
333	AssertMsg(enmState == (enmExpectedState), \
334	("enmState=%d enmExpectedState=%d idCpu=%u\n", \
335	enmState, enmExpectedState, (pVCpu)->idCpu)); \
336	} while (0)
337	#else
338	# define VMCPU_ASSERT_STATE(pVCpu, enmExpectedState) do { } while (0)
339	#endif
340	/** Tests if the state means that the CPU is started. */
341	#define VMCPUSTATE_IS_STARTED(enmState) ( (enmState) > VMCPUSTATE_STOPPED )
342	/** Tests if the state means that the CPU is stopped. */
343	#define VMCPUSTATE_IS_STOPPED(enmState) ( (enmState) == VMCPUSTATE_STOPPED )
344	/** @} */
345
346
347	/** The name of the raw-mode context VMM Core module. */
348	#define VMMRC_MAIN_MODULE_NAME "VMMRC.rc"
349	/** The name of the ring-0 context VMM Core module. */
350	#define VMMR0_MAIN_MODULE_NAME "VMMR0.r0"
351
352	/**
353	* Wrapper macro for avoiding too much \#ifdef VBOX_WITH_RAW_MODE.
354	*/
355	#ifdef VBOX_WITH_RAW_MODE
356	# define VM_WHEN_RAW_MODE(a_WithExpr, a_WithoutExpr) a_WithExpr
357	#else
358	# define VM_WHEN_RAW_MODE(a_WithExpr, a_WithoutExpr) a_WithoutExpr
359	#endif
360
361
362	/** VM Forced Action Flags.
363	*
364	* Use the VM_FF_SET() and VM_FF_CLEAR() macros to change the force
365	* action mask of a VM.
366	*
367	* Available VM bits:
368	* 0, 1, 5, 6, 7, 13, 14, 15, 16, 17, 21, 22, 23, 24, 25, 26, 27, 28, 30
369	*
370	*
371	* Available VMCPU bits:
372	* 14, 15, 36 to 63
373	*
374	* @todo If we run low on VMCPU, we may consider merging the SELM bits
375	*
376	* @{
377	*/
378	/** The virtual sync clock has been stopped, go to TM until it has been
379	* restarted... */
380	#define VM_FF_TM_VIRTUAL_SYNC RT_BIT_32(VM_FF_TM_VIRTUAL_SYNC_BIT)
381	#define VM_FF_TM_VIRTUAL_SYNC_BIT 2
382	/** PDM Queues are pending. */
383	#define VM_FF_PDM_QUEUES RT_BIT_32(VM_FF_PDM_QUEUES_BIT)
384	/** The bit number for VM_FF_PDM_QUEUES. */
385	#define VM_FF_PDM_QUEUES_BIT 3
386	/** PDM DMA transfers are pending. */
387	#define VM_FF_PDM_DMA RT_BIT_32(VM_FF_PDM_DMA_BIT)
388	/** The bit number for VM_FF_PDM_DMA. */
389	#define VM_FF_PDM_DMA_BIT 4
390	/** This action forces the VM to call DBGF so DBGF can service debugger
391	* requests in the emulation thread.
392	* This action flag stays asserted till DBGF clears it.*/
393	#define VM_FF_DBGF RT_BIT_32(VM_FF_DBGF_BIT)
394	/** The bit number for VM_FF_DBGF. */
395	#define VM_FF_DBGF_BIT 8
396	/** This action forces the VM to service pending requests from other
397	* thread or requests which must be executed in another context. */
398	#define VM_FF_REQUEST RT_BIT_32(VM_FF_REQUEST_BIT)
399	#define VM_FF_REQUEST_BIT 9
400	/** Check for VM state changes and take appropriate action. */
401	#define VM_FF_CHECK_VM_STATE RT_BIT_32(VM_FF_CHECK_VM_STATE_BIT)
402	/** The bit number for VM_FF_CHECK_VM_STATE. */
403	#define VM_FF_CHECK_VM_STATE_BIT 10
404	/** Reset the VM. (postponed) */
405	#define VM_FF_RESET RT_BIT_32(VM_FF_RESET_BIT)
406	/** The bit number for VM_FF_RESET. */
407	#define VM_FF_RESET_BIT 11
408	/** EMT rendezvous in VMM. */
409	#define VM_FF_EMT_RENDEZVOUS RT_BIT_32(VM_FF_EMT_RENDEZVOUS_BIT)
410	/** The bit number for VM_FF_EMT_RENDEZVOUS. */
411	#define VM_FF_EMT_RENDEZVOUS_BIT 12
412
413	/** PGM needs to allocate handy pages. */
414	#define VM_FF_PGM_NEED_HANDY_PAGES RT_BIT_32(VM_FF_PGM_NEED_HANDY_PAGES_BIT)
415	#define VM_FF_PGM_NEED_HANDY_PAGES_BIT 18
416	/** PGM is out of memory.
417	* Abandon all loops and code paths which can be resumed and get up to the EM
418	* loops. */
419	#define VM_FF_PGM_NO_MEMORY RT_BIT_32(VM_FF_PGM_NO_MEMORY_BIT)
420	#define VM_FF_PGM_NO_MEMORY_BIT 19
421	/** PGM is about to perform a lightweight pool flush
422	* Guest SMP: all EMT threads should return to ring 3
423	*/
424	#define VM_FF_PGM_POOL_FLUSH_PENDING RT_BIT_32(VM_FF_PGM_POOL_FLUSH_PENDING_BIT)
425	#define VM_FF_PGM_POOL_FLUSH_PENDING_BIT 20
426	/** REM needs to be informed about handler changes. */
427	#define VM_FF_REM_HANDLER_NOTIFY RT_BIT_32(VM_FF_REM_HANDLER_NOTIFY_BIT)
428	/** The bit number for VM_FF_REM_HANDLER_NOTIFY. */
429	#define VM_FF_REM_HANDLER_NOTIFY_BIT 29
430	/** Suspend the VM - debug only. */
431	#define VM_FF_DEBUG_SUSPEND RT_BIT_32(VM_FF_DEBUG_SUSPEND_BIT)
432	#define VM_FF_DEBUG_SUSPEND_BIT 31
433
434
435	/** This action forces the VM to check any pending interrupts on the APIC. */
436	#define VMCPU_FF_INTERRUPT_APIC RT_BIT_64(VMCPU_FF_INTERRUPT_APIC_BIT)
437	#define VMCPU_FF_INTERRUPT_APIC_BIT 0
438	/** This action forces the VM to check any pending interrups on the PIC. */
439	#define VMCPU_FF_INTERRUPT_PIC RT_BIT_64(VMCPU_FF_INTERRUPT_PIC_BIT)
440	#define VMCPU_FF_INTERRUPT_PIC_BIT 1
441	/** This action forces the VM to schedule and run pending timer (TM).
442	* @remarks Don't move - PATM compatibility. */
443	#define VMCPU_FF_TIMER RT_BIT_64(VMCPU_FF_TIMER_BIT)
444	#define VMCPU_FF_TIMER_BIT 2
445	/** This action forces the VM to check any pending NMIs. */
446	#define VMCPU_FF_INTERRUPT_NMI RT_BIT_64(VMCPU_FF_INTERRUPT_NMI_BIT)
447	#define VMCPU_FF_INTERRUPT_NMI_BIT 3
448	/** This action forces the VM to check any pending SMIs. */
449	#define VMCPU_FF_INTERRUPT_SMI RT_BIT_64(VMCPU_FF_INTERRUPT_SMI_BIT)
450	#define VMCPU_FF_INTERRUPT_SMI_BIT 4
451	/** PDM critical section unlocking is pending, process promptly upon return to R3. */
452	#define VMCPU_FF_PDM_CRITSECT RT_BIT_64(VMCPU_FF_PDM_CRITSECT_BIT)
453	#define VMCPU_FF_PDM_CRITSECT_BIT 5
454	/** Special EM internal force flag that is used by EMUnhaltAndWakeUp() to force
455	* the virtual CPU out of the next (/current) halted state. It is not processed
456	* nor cleared by emR3ForcedActions (similar to VMCPU_FF_BLOCK_NMIS), instead it
457	* is cleared the next time EM leaves the HALTED state. */
458	#define VMCPU_FF_UNHALT RT_BIT_64(VMCPU_FF_UNHALT_BIT)
459	#define VMCPU_FF_UNHALT_BIT 6
460	/** Pending IEM action (mask). */
461	#define VMCPU_FF_IEM RT_BIT_64(VMCPU_FF_IEM_BIT)
462	/** Pending IEM action (bit number). */
463	#define VMCPU_FF_IEM_BIT 7
464	/** Pending APIC action (bit number). */
465	#define VMCPU_FF_UPDATE_APIC_BIT 8
466	/** This action forces the VM to update APIC's asynchronously arrived
467	* interrupts as pending interrupts. */
468	#define VMCPU_FF_UPDATE_APIC RT_BIT_64(VMCPU_FF_UPDATE_APIC_BIT)
469	/** This action forces the VM to service pending requests from other
470	* thread or requests which must be executed in another context. */
471	#define VMCPU_FF_REQUEST RT_BIT_64(VMCPU_FF_REQUEST_BIT)
472	#define VMCPU_FF_REQUEST_BIT 9
473	/** Pending DBGF event (alternative to passing VINF_EM_DBG_EVENT around). */
474	#define VMCPU_FF_DBGF RT_BIT_64(VMCPU_FF_DBGF_BIT)
475	/** The bit number for VMCPU_FF_DBGF. */
476	#define VMCPU_FF_DBGF_BIT 10
477	/** This action forces the VM to service any pending updates to CR3 (used only
478	* by HM). */
479	/** Hardware virtualized nested-guest interrupt pending. */
480	#define VMCPU_FF_INTERRUPT_NESTED_GUEST RT_BIT_64(VMCPU_FF_INTERRUPT_NESTED_GUEST_BIT)
481	#define VMCPU_FF_INTERRUPT_NESTED_GUEST_BIT 11
482	#define VMCPU_FF_HM_UPDATE_CR3 RT_BIT_64(VMCPU_FF_HM_UPDATE_CR3_BIT)
483	#define VMCPU_FF_HM_UPDATE_CR3_BIT 12
484	/** This action forces the VM to service any pending updates to PAE PDPEs (used
485	* only by HM). */
486	#define VMCPU_FF_HM_UPDATE_PAE_PDPES RT_BIT_64(VMCPU_FF_HM_UPDATE_PAE_PDPES_BIT)
487	#define VMCPU_FF_HM_UPDATE_PAE_PDPES_BIT 13
488	/** This action forces the VM to resync the page tables before going
489	* back to execute guest code. (GLOBAL FLUSH) */
490	#define VMCPU_FF_PGM_SYNC_CR3 RT_BIT_64(VMCPU_FF_PGM_SYNC_CR3_BIT)
491	#define VMCPU_FF_PGM_SYNC_CR3_BIT 16
492	/** Same as VM_FF_PGM_SYNC_CR3 except that global pages can be skipped.
493	* (NON-GLOBAL FLUSH) */
494	#define VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL RT_BIT_64(VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL_BIT)
495	#define VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL_BIT 17
496	/** Check for pending TLB shootdown actions (deprecated)
497	* Reserved for furture HM re-use if necessary / safe.
498	* Consumer: HM */
499	#define VMCPU_FF_TLB_SHOOTDOWN_UNUSED RT_BIT_64(VMCPU_FF_TLB_SHOOTDOWN_UNUSED_BIT)
500	#define VMCPU_FF_TLB_SHOOTDOWN_UNUSED_BIT 18
501	/** Check for pending TLB flush action.
502	* Consumer: HM
503	* @todo rename to VMCPU_FF_HM_TLB_FLUSH */
504	#define VMCPU_FF_TLB_FLUSH RT_BIT_64(VMCPU_FF_TLB_FLUSH_BIT)
505	/** The bit number for VMCPU_FF_TLB_FLUSH. */
506	#define VMCPU_FF_TLB_FLUSH_BIT 19
507	#ifdef VBOX_WITH_RAW_MODE
508	/** Check the interrupt and trap gates */
509	# define VMCPU_FF_TRPM_SYNC_IDT RT_BIT_64(VMCPU_FF_TRPM_SYNC_IDT_BIT)
510	# define VMCPU_FF_TRPM_SYNC_IDT_BIT 20
511	/** Check Guest's TSS ring 0 stack */
512	# define VMCPU_FF_SELM_SYNC_TSS RT_BIT_64(VMCPU_FF_SELM_SYNC_TSS_BIT)
513	# define VMCPU_FF_SELM_SYNC_TSS_BIT 21
514	/** Check Guest's GDT table */
515	# define VMCPU_FF_SELM_SYNC_GDT RT_BIT_64(VMCPU_FF_SELM_SYNC_GDT_BIT)
516	# define VMCPU_FF_SELM_SYNC_GDT_BIT 22
517	/** Check Guest's LDT table */
518	# define VMCPU_FF_SELM_SYNC_LDT RT_BIT_64(VMCPU_FF_SELM_SYNC_LDT_BIT)
519	# define VMCPU_FF_SELM_SYNC_LDT_BIT 23
520	#endif /* VBOX_WITH_RAW_MODE */
521	/** Inhibit interrupts pending. See EMGetInhibitInterruptsPC(). */
522	#define VMCPU_FF_INHIBIT_INTERRUPTS RT_BIT_64(VMCPU_FF_INHIBIT_INTERRUPTS_BIT)
523	#define VMCPU_FF_INHIBIT_INTERRUPTS_BIT 24
524	/** Block injection of non-maskable interrupts to the guest. */
525	#define VMCPU_FF_BLOCK_NMIS RT_BIT_64(VMCPU_FF_BLOCK_NMIS_BIT)
526	#define VMCPU_FF_BLOCK_NMIS_BIT 25
527	#ifdef VBOX_WITH_RAW_MODE
528	/** CSAM needs to scan the page that's being executed */
529	# define VMCPU_FF_CSAM_SCAN_PAGE RT_BIT_64(VMCPU_FF_CSAM_SCAN_PAGE_BIT)
530	# define VMCPU_FF_CSAM_SCAN_PAGE_BIT 26
531	/** CSAM needs to do some homework. */
532	# define VMCPU_FF_CSAM_PENDING_ACTION RT_BIT_64(VMCPU_FF_CSAM_PENDING_ACTION_BIT)
533	# define VMCPU_FF_CSAM_PENDING_ACTION_BIT 27
534	#endif /* VBOX_WITH_RAW_MODE */
535	/** Force return to Ring-3. */
536	#define VMCPU_FF_TO_R3 RT_BIT_64(VMCPU_FF_TO_R3_BIT)
537	#define VMCPU_FF_TO_R3_BIT 28
538	/** Force return to ring-3 to service pending I/O or MMIO write.
539	* This is a backup for mechanism VINF_IOM_R3_IOPORT_COMMIT_WRITE and
540	* VINF_IOM_R3_MMIO_COMMIT_WRITE, allowing VINF_EM_DBG_BREAKPOINT and similar
541	* status codes to be propagated at the same time without loss. */
542	#define VMCPU_FF_IOM RT_BIT_64(VMCPU_FF_IOM_BIT)
543	#define VMCPU_FF_IOM_BIT 29
544	#ifdef VBOX_WITH_RAW_MODE
545	/** CPUM need to adjust CR0.TS/EM before executing raw-mode code again. */
546	# define VMCPU_FF_CPUM RT_BIT_64(VMCPU_FF_CPUM_BIT)
547	/** The bit number for VMCPU_FF_CPUM. */
548	# define VMCPU_FF_CPUM_BIT 30
549	#endif /* VBOX_WITH_RAW_MODE */
550	/** VMX-preemption timer in effect. */
551	#define VMCPU_FF_VMX_PREEMPT_TIMER RT_BIT_64(VMCPU_FF_VMX_PREEMPT_TIMER_BIT)
552	#define VMCPU_FF_VMX_PREEMPT_TIMER_BIT 31
553	/** Pending MTF (Monitor Trap Flag) event. */
554	#define VMCPU_FF_VMX_MTF RT_BIT_64(VMCPU_FF_VMX_MTF_BIT)
555	#define VMCPU_FF_VMX_MTF_BIT 32
556	/** VMX APIC-write emulation pending. */
557	#define VMCPU_FF_VMX_APIC_WRITE RT_BIT_64(VMCPU_FF_VMX_APIC_WRITE_BIT)
558	#define VMCPU_FF_VMX_APIC_WRITE_BIT 33
559	/** VMX interrupt-window event pending. */
560	#define VMCPU_FF_VMX_INT_WINDOW RT_BIT_64(VMCPU_FF_VMX_INT_WINDOW_BIT)
561	#define VMCPU_FF_VMX_INT_WINDOW_BIT 34
562	/** VMX NMI-window event pending. */
563	#define VMCPU_FF_VMX_NMI_WINDOW RT_BIT_64(VMCPU_FF_VMX_NMI_WINDOW_BIT)
564	#define VMCPU_FF_VMX_NMI_WINDOW_BIT 35
565
566
567	/** Externally VM forced actions. Used to quit the idle/wait loop. */
568	#define VM_FF_EXTERNAL_SUSPENDED_MASK ( VM_FF_CHECK_VM_STATE \| VM_FF_DBGF \| VM_FF_REQUEST \| VM_FF_EMT_RENDEZVOUS )
569	/** Externally VMCPU forced actions. Used to quit the idle/wait loop. */
570	#define VMCPU_FF_EXTERNAL_SUSPENDED_MASK ( VMCPU_FF_REQUEST \| VMCPU_FF_DBGF )
571
572	/** Externally forced VM actions. Used to quit the idle/wait loop. */
573	#define VM_FF_EXTERNAL_HALTED_MASK ( VM_FF_CHECK_VM_STATE \| VM_FF_DBGF \| VM_FF_REQUEST \
574	\| VM_FF_PDM_QUEUES \| VM_FF_PDM_DMA \| VM_FF_EMT_RENDEZVOUS )
575	/** Externally forced VMCPU actions. Used to quit the idle/wait loop. */
576	#define VMCPU_FF_EXTERNAL_HALTED_MASK ( VMCPU_FF_UPDATE_APIC \| VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC \
577	\| VMCPU_FF_REQUEST \| VMCPU_FF_INTERRUPT_NMI \| VMCPU_FF_INTERRUPT_SMI \
578	\| VMCPU_FF_UNHALT \| VMCPU_FF_TIMER \| VMCPU_FF_DBGF \
579	\| VMCPU_FF_INTERRUPT_NESTED_GUEST)
580
581	/** High priority VM pre-execution actions. */
582	#define VM_FF_HIGH_PRIORITY_PRE_MASK ( VM_FF_CHECK_VM_STATE \| VM_FF_DBGF \| VM_FF_TM_VIRTUAL_SYNC \
583	\| VM_FF_DEBUG_SUSPEND \| VM_FF_PGM_NEED_HANDY_PAGES \| VM_FF_PGM_NO_MEMORY \
584	\| VM_FF_EMT_RENDEZVOUS )
585	/** High priority VMCPU pre-execution actions. */
586	#define VMCPU_FF_HIGH_PRIORITY_PRE_MASK ( VMCPU_FF_TIMER \| VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC \
587	\| VMCPU_FF_UPDATE_APIC \| VMCPU_FF_INHIBIT_INTERRUPTS \| VMCPU_FF_DBGF \
588	\| VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL \
589	\| VMCPU_FF_INTERRUPT_NESTED_GUEST \| VMCPU_FF_VMX_MTF \| VMCPU_FF_VMX_APIC_WRITE \
590	\| VMCPU_FF_VMX_PREEMPT_TIMER \| VMCPU_FF_VMX_NMI_WINDOW \| VMCPU_FF_VMX_INT_WINDOW \
591	\| VM_WHEN_RAW_MODE( VMCPU_FF_SELM_SYNC_TSS \| VMCPU_FF_TRPM_SYNC_IDT \
592	\| VMCPU_FF_SELM_SYNC_GDT \| VMCPU_FF_SELM_SYNC_LDT, 0 ) )
593
594	/** High priority VM pre raw-mode execution mask. */
595	#define VM_FF_HIGH_PRIORITY_PRE_RAW_MASK ( VM_FF_PGM_NEED_HANDY_PAGES \| VM_FF_PGM_NO_MEMORY )
596	/** High priority VMCPU pre raw-mode execution mask. */
597	#define VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK ( VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL \
598	\| VMCPU_FF_INHIBIT_INTERRUPTS \
599	\| VM_WHEN_RAW_MODE( VMCPU_FF_SELM_SYNC_TSS \| VMCPU_FF_TRPM_SYNC_IDT \
600	\| VMCPU_FF_SELM_SYNC_GDT \| VMCPU_FF_SELM_SYNC_LDT, 0) )
601
602	/** High priority post-execution actions. */
603	#define VM_FF_HIGH_PRIORITY_POST_MASK ( VM_FF_PGM_NO_MEMORY )
604	/** High priority post-execution actions. */
605	#define VMCPU_FF_HIGH_PRIORITY_POST_MASK ( VMCPU_FF_PDM_CRITSECT \| VM_WHEN_RAW_MODE(VMCPU_FF_CSAM_PENDING_ACTION, 0) \
606	\| VMCPU_FF_HM_UPDATE_CR3 \| VMCPU_FF_HM_UPDATE_PAE_PDPES \
607	\| VMCPU_FF_IEM \| VMCPU_FF_IOM )
608
609	/** Normal priority VM post-execution actions. */
610	#define VM_FF_NORMAL_PRIORITY_POST_MASK ( VM_FF_CHECK_VM_STATE \| VM_FF_DBGF \| VM_FF_RESET \
611	\| VM_FF_PGM_NO_MEMORY \| VM_FF_EMT_RENDEZVOUS)
612	/** Normal priority VMCPU post-execution actions. */
613	#define VMCPU_FF_NORMAL_PRIORITY_POST_MASK ( VM_WHEN_RAW_MODE(VMCPU_FF_CSAM_SCAN_PAGE, 0) \| VMCPU_FF_DBGF )
614
615	/** Normal priority VM actions. */
616	#define VM_FF_NORMAL_PRIORITY_MASK ( VM_FF_REQUEST \| VM_FF_PDM_QUEUES \| VM_FF_PDM_DMA \
617	\| VM_FF_REM_HANDLER_NOTIFY \| VM_FF_EMT_RENDEZVOUS)
618	/** Normal priority VMCPU actions. */
619	#define VMCPU_FF_NORMAL_PRIORITY_MASK ( VMCPU_FF_REQUEST )
620
621	/** Flags to clear before resuming guest execution. */
622	#define VMCPU_FF_RESUME_GUEST_MASK ( VMCPU_FF_TO_R3 )
623
624
625	/** VM flags that cause the REP[\|NE\|E] STRINS loops to yield immediately. */
626	#define VM_FF_HIGH_PRIORITY_POST_REPSTR_MASK ( VM_FF_TM_VIRTUAL_SYNC \| VM_FF_PGM_NEED_HANDY_PAGES \| VM_FF_PGM_NO_MEMORY \
627	\| VM_FF_EMT_RENDEZVOUS \| VM_FF_PGM_POOL_FLUSH_PENDING \| VM_FF_RESET)
628	/** VM flags that cause the REP[\|NE\|E] STRINS loops to yield. */
629	#define VM_FF_YIELD_REPSTR_MASK ( VM_FF_HIGH_PRIORITY_POST_REPSTR_MASK \
630	\| VM_FF_PDM_QUEUES \| VM_FF_PDM_DMA \| VM_FF_DBGF \| VM_FF_DEBUG_SUSPEND )
631	/** VMCPU flags that cause the REP[\|NE\|E] STRINS loops to yield immediately. */
632	#ifdef IN_RING3
633	# define VMCPU_FF_HIGH_PRIORITY_POST_REPSTR_MASK ( VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL \| VMCPU_FF_DBGF \
634	\| VMCPU_FF_VMX_MTF )
635	#else
636	# define VMCPU_FF_HIGH_PRIORITY_POST_REPSTR_MASK ( VMCPU_FF_TO_R3 \| VMCPU_FF_IEM \| VMCPU_FF_IOM \| VMCPU_FF_PGM_SYNC_CR3 \
637	\| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL \| VMCPU_FF_DBGF \| VMCPU_FF_VMX_MTF )
638	#endif
639	/** VMCPU flags that cause the REP[\|NE\|E] STRINS loops to yield, interrupts
640	* enabled. */
641	#define VMCPU_FF_YIELD_REPSTR_MASK ( VMCPU_FF_HIGH_PRIORITY_POST_REPSTR_MASK \
642	\| VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_UPDATE_APIC \| VMCPU_FF_INTERRUPT_PIC \
643	\| VMCPU_FF_INTERRUPT_NMI \| VMCPU_FF_INTERRUPT_SMI \| VMCPU_FF_PDM_CRITSECT \
644	\| VMCPU_FF_TIMER \| VMCPU_FF_REQUEST \
645	\| VMCPU_FF_INTERRUPT_NESTED_GUEST )
646	/** VMCPU flags that cause the REP[\|NE\|E] STRINS loops to yield, interrupts
647	* disabled. */
648	#define VMCPU_FF_YIELD_REPSTR_NOINT_MASK ( VMCPU_FF_YIELD_REPSTR_MASK \
649	& ~( VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_UPDATE_APIC \| VMCPU_FF_INTERRUPT_PIC \
650	\| VMCPU_FF_INTERRUPT_NESTED_GUEST) )
651
652	/** VM Flags that cause the HM loops to go back to ring-3. */
653	#define VM_FF_HM_TO_R3_MASK ( VM_FF_TM_VIRTUAL_SYNC \| VM_FF_PGM_NEED_HANDY_PAGES \| VM_FF_PGM_NO_MEMORY \
654	\| VM_FF_PDM_QUEUES \| VM_FF_EMT_RENDEZVOUS)
655	/** VMCPU Flags that cause the HM loops to go back to ring-3. */
656	#define VMCPU_FF_HM_TO_R3_MASK ( VMCPU_FF_TO_R3 \| VMCPU_FF_TIMER \| VMCPU_FF_PDM_CRITSECT \
657	\| VMCPU_FF_IEM \| VMCPU_FF_IOM)
658
659	/** High priority ring-0 VM pre HM-mode execution mask. */
660	#define VM_FF_HP_R0_PRE_HM_MASK (VM_FF_HM_TO_R3_MASK \| VM_FF_REQUEST \| VM_FF_PGM_POOL_FLUSH_PENDING \| VM_FF_PDM_DMA)
661	/** High priority ring-0 VMCPU pre HM-mode execution mask. */
662	#define VMCPU_FF_HP_R0_PRE_HM_MASK ( VMCPU_FF_HM_TO_R3_MASK \| VMCPU_FF_PGM_SYNC_CR3 \
663	\| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL \| VMCPU_FF_REQUEST)
664	/** High priority ring-0 VM pre HM-mode execution mask, single stepping. */
665	#define VM_FF_HP_R0_PRE_HM_STEP_MASK (VM_FF_HP_R0_PRE_HM_MASK & ~( VM_FF_TM_VIRTUAL_SYNC \| VM_FF_PDM_QUEUES \
666	\| VM_FF_EMT_RENDEZVOUS \| VM_FF_REQUEST \
667	\| VM_FF_PDM_DMA) )
668	/** High priority ring-0 VMCPU pre HM-mode execution mask, single stepping. */
669	#define VMCPU_FF_HP_R0_PRE_HM_STEP_MASK (VMCPU_FF_HP_R0_PRE_HM_MASK & ~( VMCPU_FF_TO_R3 \| VMCPU_FF_TIMER \
670	\| VMCPU_FF_PDM_CRITSECT \| VMCPU_FF_REQUEST) )
671
672	/** All the forced VM flags. */
673	#define VM_FF_ALL_MASK (UINT32_MAX)
674	/** All the forced VMCPU flags. */
675	#define VMCPU_FF_ALL_MASK (UINT32_MAX)
676
677	/** All the forced VM flags except those related to raw-mode and hardware
678	* assisted execution. */
679	#define VM_FF_ALL_REM_MASK (~(VM_FF_HIGH_PRIORITY_PRE_RAW_MASK) \| VM_FF_PGM_NEED_HANDY_PAGES \| VM_FF_PGM_NO_MEMORY)
680	/** All the forced VMCPU flags except those related to raw-mode and hardware
681	* assisted execution. */
682	#define VMCPU_FF_ALL_REM_MASK (~( VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK \| VMCPU_FF_PDM_CRITSECT \
683	\| VMCPU_FF_TLB_FLUSH \| VM_WHEN_RAW_MODE(VMCPU_FF_CSAM_PENDING_ACTION, 0) ))
684	/** @} */
685
686	/** @def VM_FF_SET
687	* Sets a single force action flag.
688	*
689	* @param pVM The cross context VM structure.
690	* @param fFlag The flag to set.
691	*/
692	#define VM_FF_SET(pVM, fFlag) do { \
693	AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
694	AssertCompile((fFlag) == RT_BIT_32(fFlag##_BIT)); \
695	ASMAtomicOrU32(&(pVM)->fGlobalForcedActions, (fFlag)); \
696	} while (0)
697
698	/** @def VMCPU_FF_SET
699	* Sets a single force action flag for the given VCPU.
700	*
701	* @param pVCpu The cross context virtual CPU structure.
702	* @param fFlag The flag to set.
703	* @sa VMCPU_FF_SET_MASK
704	*/
705	#ifdef VMCPU_WITH_64_BIT_FFS
706	# define VMCPU_FF_SET(pVCpu, fFlag) do { \
707	AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
708	AssertCompile((fFlag) == RT_BIT_64(fFlag##_BIT)); \
709	ASMAtomicBitSet(&(pVCpu)->fLocalForcedActions, fFlag##_BIT); \
710	} while (0)
711	#else
712	# define VMCPU_FF_SET(pVCpu, fFlag) do { \
713	AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
714	AssertCompile((fFlag) == RT_BIT_32(fFlag##_BIT)); \
715	ASMAtomicOrU32(&(pVCpu)->fLocalForcedActions, (fFlag)); \
716	} while (0)
717	#endif
718
719	/** @def VMCPU_FF_SET_MASK
720	* Sets a two or more force action flag for the given VCPU.
721	*
722	* @param pVCpu The cross context virtual CPU structure.
723	* @param fFlags The flags to set.
724	* @sa VMCPU_FF_SET
725	*/
726	#ifdef VMCPU_WITH_64_BIT_FFS
727	# if ARCH_BITS > 32
728	# define VMCPU_FF_SET_MASK(pVCpu, fFlags) \
729	do { ASMAtomicOrU64(&pVCpu->fLocalForcedActions, (fFlags)); } while (0)
730	# else
731	# define VMCPU_FF_SET_MASK(pVCpu, fFlags) do { \
732	if (!((fFlags) >> 32)) ASMAtomicOrU32((uint32_t volatile *)&pVCpu->fLocalForcedActions, (uint32_t)(fFlags)); \
733	else ASMAtomicOrU64(&pVCpu->fLocalForcedActions, (fFlags)); \
734	} while (0)
735	# endif
736	#else
737	# define VMCPU_FF_SET_MASK(pVCpu, fFlags) \
738	do { ASMAtomicOrU32(&pVCpu->fLocalForcedActions, (fFlags)); } while (0)
739	#endif
740
741	/** @def VM_FF_CLEAR
742	* Clears a single force action flag.
743	*
744	* @param pVM The cross context VM structure.
745	* @param fFlag The flag to clear.
746	*/
747	#define VM_FF_CLEAR(pVM, fFlag) do { \
748	AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
749	AssertCompile((fFlag) == RT_BIT_32(fFlag##_BIT)); \
750	ASMAtomicAndU32(&(pVM)->fGlobalForcedActions, ~(fFlag)); \
751	} while (0)
752
753	/** @def VMCPU_FF_CLEAR
754	* Clears a single force action flag for the given VCPU.
755	*
756	* @param pVCpu The cross context virtual CPU structure.
757	* @param fFlag The flag to clear.
758	*/
759	#ifdef VMCPU_WITH_64_BIT_FFS
760	# define VMCPU_FF_CLEAR(pVCpu, fFlag) do { \
761	AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
762	AssertCompile((fFlag) == RT_BIT_64(fFlag##_BIT)); \
763	ASMAtomicBitClear(&(pVCpu)->fLocalForcedActions, fFlag##_BIT); \
764	} while (0)
765	#else
766	# define VMCPU_FF_CLEAR(pVCpu, fFlag) do { \
767	AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
768	AssertCompile((fFlag) == RT_BIT_32(fFlag##_BIT)); \
769	ASMAtomicAndU32(&(pVCpu)->fLocalForcedActions, ~(fFlag)); \
770	} while (0)
771	#endif
772
773	/** @def VMCPU_FF_CLEAR_MASK
774	* Clears two or more force action flags for the given VCPU.
775	*
776	* @param pVCpu The cross context virtual CPU structure.
777	* @param fFlags The flags to clear.
778	*/
779	#ifdef VMCPU_WITH_64_BIT_FFS
780	# if ARCH_BITS > 32
781	# define VMCPU_FF_CLEAR_MASK(pVCpu, fFlags) \
782	do { ASMAtomicAndU64(&(pVCpu)->fLocalForcedActions, ~(fFlags)); } while (0)
783	# else
784	# define VMCPU_FF_CLEAR_MASK(pVCpu, fFlags) do { \
785	if (!((fFlags) >> 32)) ASMAtomicAndU32((uint32_t volatile *)&(pVCpu)->fLocalForcedActions, ~(uint32_t)(fFlags)); \
786	else ASMAtomicAndU64(&(pVCpu)->fLocalForcedActions, ~(fFlags)); \
787	} while (0)
788	# endif
789	#else
790	# define VMCPU_FF_CLEAR_MASK(pVCpu, fFlags) \
791	do { ASMAtomicAndU32(&(pVCpu)->fLocalForcedActions, ~(fFlags)); } while (0)
792	#endif
793
794	/** @def VM_FF_IS_SET
795	* Checks if single a force action flag is set.
796	*
797	* @param pVM The cross context VM structure.
798	* @param fFlag The flag to check.
799	* @sa VM_FF_IS_ANY_SET
800	*/
801	#if !defined(VBOX_STRICT) \|\| !defined(RT_COMPILER_SUPPORTS_LAMBDA)
802	# define VM_FF_IS_SET(pVM, fFlag) RT_BOOL((pVM)->fGlobalForcedActions & (fFlag))
803	#else
804	# define VM_FF_IS_SET(pVM, fFlag) \
805	([](PVM a_pVM) -> bool \
806	{ \
807	AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
808	AssertCompile((fFlag) == RT_BIT_32(fFlag##_BIT)); \
809	return RT_BOOL(a_pVM->fGlobalForcedActions & (fFlag)); \
810	}(pVM))
811	#endif
812
813	/** @def VMCPU_FF_IS_SET
814	* Checks if a single force action flag is set for the given VCPU.
815	*
816	* @param pVCpu The cross context virtual CPU structure.
817	* @param fFlag The flag to check.
818	* @sa VMCPU_FF_IS_ANY_SET
819	*/
820	#if !defined(VBOX_STRICT) \|\| !defined(RT_COMPILER_SUPPORTS_LAMBDA)
821	# define VMCPU_FF_IS_SET(pVCpu, fFlag) RT_BOOL((pVCpu)->fLocalForcedActions & (fFlag))
822	#else
823	# define VMCPU_FF_IS_SET(pVCpu, fFlag) \
824	([](PVMCPU a_pVCpu) -> bool \
825	{ \
826	AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
827	AssertCompile((fFlag) == RT_BIT_64(fFlag##_BIT)); \
828	return RT_BOOL(a_pVCpu->fLocalForcedActions & (fFlag)); \
829	}(pVCpu))
830	#endif
831
832	/** @def VM_FF_IS_ANY_SET
833	* Checks if one or more force action in the specified set is pending.
834	*
835	* @param pVM The cross context VM structure.
836	* @param fFlags The flags to check for.
837	* @sa VM_FF_IS_SET
838	*/
839	#define VM_FF_IS_ANY_SET(pVM, fFlags) RT_BOOL((pVM)->fGlobalForcedActions & (fFlags))
840
841	/** @def VMCPU_FF_IS_ANY_SET
842	* Checks if two or more force action flags in the specified set is set for the given VCPU.
843	*
844	* @param pVCpu The cross context virtual CPU structure.
845	* @param fFlags The flags to check for.
846	* @sa VMCPU_FF_IS_SET
847	*/
848	#define VMCPU_FF_IS_ANY_SET(pVCpu, fFlags) RT_BOOL((pVCpu)->fLocalForcedActions & (fFlags))
849
850	/** @def VM_FF_TEST_AND_CLEAR
851	* Checks if one (!) force action in the specified set is pending and clears it atomically
852	*
853	* @returns true if the bit was set.
854	* @returns false if the bit was clear.
855	* @param pVM The cross context VM structure.
856	* @param fFlag Flag constant to check and clear (_BIT is appended).
857	*/
858	#define VM_FF_TEST_AND_CLEAR(pVM, fFlag) (ASMAtomicBitTestAndClear(&(pVM)->fGlobalForcedActions, fFlag##_BIT))
859
860	/** @def VMCPU_FF_TEST_AND_CLEAR
861	* Checks if one (!) force action in the specified set is pending and clears it atomically
862	*
863	* @returns true if the bit was set.
864	* @returns false if the bit was clear.
865	* @param pVCpu The cross context virtual CPU structure.
866	* @param fFlag Flag constant to check and clear (_BIT is appended).
867	*/
868	#define VMCPU_FF_TEST_AND_CLEAR(pVCpu, fFlag) (ASMAtomicBitTestAndClear(&(pVCpu)->fLocalForcedActions, fFlag##_BIT))
869
870	/** @def VM_FF_IS_PENDING_EXCEPT
871	* Checks if one or more force action in the specified set is pending while one
872	* or more other ones are not.
873	*
874	* @param pVM The cross context VM structure.
875	* @param fFlags The flags to check for.
876	* @param fExcpt The flags that should not be set.
877	*/
878	#define VM_FF_IS_PENDING_EXCEPT(pVM, fFlags, fExcpt) \
879	( ((pVM)->fGlobalForcedActions & (fFlags)) && !((pVM)->fGlobalForcedActions & (fExcpt)) )
880
881	/** @def VM_IS_EMT
882	* Checks if the current thread is the emulation thread (EMT).
883	*
884	* @remark The ring-0 variation will need attention if we expand the ring-0
885	* code to let threads other than EMT mess around with the VM.
886	*/
887	#ifdef IN_RC
888	# define VM_IS_EMT(pVM) true
889	#else
890	# define VM_IS_EMT(pVM) (VMMGetCpu(pVM) != NULL)
891	#endif
892
893	/** @def VMCPU_IS_EMT
894	* Checks if the current thread is the emulation thread (EMT) for the specified
895	* virtual CPU.
896	*/
897	#ifdef IN_RC
898	# define VMCPU_IS_EMT(pVCpu) true
899	#else
900	# define VMCPU_IS_EMT(pVCpu) ((pVCpu) && ((pVCpu) == VMMGetCpu((pVCpu)->CTX_SUFF(pVM))))
901	#endif
902
903	/** @def VM_ASSERT_EMT
904	* Asserts that the current thread IS the emulation thread (EMT).
905	*/
906	#ifdef IN_RC
907	# define VM_ASSERT_EMT(pVM) Assert(VM_IS_EMT(pVM))
908	#elif defined(IN_RING0)
909	# define VM_ASSERT_EMT(pVM) Assert(VM_IS_EMT(pVM))
910	#else
911	# define VM_ASSERT_EMT(pVM) \
912	AssertMsg(VM_IS_EMT(pVM), \
913	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd\n", RTThreadNativeSelf(), VMR3GetVMCPUNativeThread(pVM)))
914	#endif
915
916	/** @def VMCPU_ASSERT_EMT
917	* Asserts that the current thread IS the emulation thread (EMT) of the
918	* specified virtual CPU.
919	*/
920	#ifdef IN_RC
921	# define VMCPU_ASSERT_EMT(pVCpu) Assert(VMCPU_IS_EMT(pVCpu))
922	#elif defined(IN_RING0)
923	# define VMCPU_ASSERT_EMT(pVCpu) AssertMsg(VMCPU_IS_EMT(pVCpu), \
924	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd idCpu=%u\n", \
925	RTThreadNativeSelf(), (pVCpu) ? (pVCpu)->hNativeThreadR0 : 0, \
926	(pVCpu) ? (pVCpu)->idCpu : 0))
927	#else
928	# define VMCPU_ASSERT_EMT(pVCpu) AssertMsg(VMCPU_IS_EMT(pVCpu), \
929	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd idCpu=%#x\n", \
930	RTThreadNativeSelf(), (pVCpu)->hNativeThread, (pVCpu)->idCpu))
931	#endif
932
933	/** @def VM_ASSERT_EMT_RETURN
934	* Asserts that the current thread IS the emulation thread (EMT) and returns if it isn't.
935	*/
936	#ifdef IN_RC
937	# define VM_ASSERT_EMT_RETURN(pVM, rc) AssertReturn(VM_IS_EMT(pVM), (rc))
938	#elif defined(IN_RING0)
939	# define VM_ASSERT_EMT_RETURN(pVM, rc) AssertReturn(VM_IS_EMT(pVM), (rc))
940	#else
941	# define VM_ASSERT_EMT_RETURN(pVM, rc) \
942	AssertMsgReturn(VM_IS_EMT(pVM), \
943	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd\n", RTThreadNativeSelf(), VMR3GetVMCPUNativeThread(pVM)), \
944	(rc))
945	#endif
946
947	/** @def VMCPU_ASSERT_EMT_RETURN
948	* Asserts that the current thread IS the emulation thread (EMT) and returns if it isn't.
949	*/
950	#ifdef IN_RC
951	# define VMCPU_ASSERT_EMT_RETURN(pVCpu, rc) AssertReturn(VMCPU_IS_EMT(pVCpu), (rc))
952	#elif defined(IN_RING0)
953	# define VMCPU_ASSERT_EMT_RETURN(pVCpu, rc) AssertReturn(VMCPU_IS_EMT(pVCpu), (rc))
954	#else
955	# define VMCPU_ASSERT_EMT_RETURN(pVCpu, rc) \
956	AssertMsgReturn(VMCPU_IS_EMT(pVCpu), \
957	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd idCpu=%#x\n", \
958	RTThreadNativeSelf(), (pVCpu)->hNativeThread, (pVCpu)->idCpu), \
959	(rc))
960	#endif
961
962	/** @def VMCPU_ASSERT_EMT_OR_GURU
963	* Asserts that the current thread IS the emulation thread (EMT) of the
964	* specified virtual CPU.
965	*/
966	#if defined(IN_RC) \|\| defined(IN_RING0)
967	# define VMCPU_ASSERT_EMT_OR_GURU(pVCpu) Assert( VMCPU_IS_EMT(pVCpu) \
968	\|\| pVCpu->CTX_SUFF(pVM)->enmVMState == VMSTATE_GURU_MEDITATION \
969	\|\| pVCpu->CTX_SUFF(pVM)->enmVMState == VMSTATE_GURU_MEDITATION_LS )
970	#else
971	# define VMCPU_ASSERT_EMT_OR_GURU(pVCpu) \
972	AssertMsg( VMCPU_IS_EMT(pVCpu) \
973	\|\| pVCpu->CTX_SUFF(pVM)->enmVMState == VMSTATE_GURU_MEDITATION \
974	\|\| pVCpu->CTX_SUFF(pVM)->enmVMState == VMSTATE_GURU_MEDITATION_LS, \
975	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd idCpu=%#x\n", \
976	RTThreadNativeSelf(), (pVCpu)->hNativeThread, (pVCpu)->idCpu))
977	#endif
978
979	/** @def VMCPU_ASSERT_EMT_OR_NOT_RUNNING
980	* Asserts that the current thread IS the emulation thread (EMT) of the
981	* specified virtual CPU or the VM is not running.
982	*/
983	#if defined(IN_RC) \|\| defined(IN_RING0)
984	# define VMCPU_ASSERT_EMT_OR_NOT_RUNNING(pVCpu) \
985	Assert( VMCPU_IS_EMT(pVCpu) \
986	\|\| !VM_IS_RUNNING_FOR_ASSERTIONS_ONLY((pVCpu)->CTX_SUFF(pVM)) )
987	#else
988	# define VMCPU_ASSERT_EMT_OR_NOT_RUNNING(pVCpu) \
989	AssertMsg( VMCPU_IS_EMT(pVCpu) \
990	\|\| !VM_IS_RUNNING_FOR_ASSERTIONS_ONLY((pVCpu)->CTX_SUFF(pVM)), \
991	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd idCpu=%#x\n", \
992	RTThreadNativeSelf(), (pVCpu)->hNativeThread, (pVCpu)->idCpu))
993	#endif
994
995	/** @def VMSTATE_IS_RUNNING
996	* Checks if the given state indicates a running VM.
997	*/
998	#define VMSTATE_IS_RUNNING(a_enmVMState) \
999	( (enmVMState) == VMSTATE_RUNNING \
1000	\|\| (enmVMState) == VMSTATE_RUNNING_LS \
1001	\|\| (enmVMState) == VMSTATE_RUNNING_FT )
1002
1003	/** @def VM_IS_RUNNING_FOR_ASSERTIONS_ONLY
1004	* Checks if the VM is running.
1005	* @note This is only for pure debug assertions. No AssertReturn or similar!
1006	* @sa VMSTATE_IS_RUNNING
1007	*/
1008	#define VM_IS_RUNNING_FOR_ASSERTIONS_ONLY(pVM) \
1009	( (pVM)->enmVMState == VMSTATE_RUNNING \
1010	\|\| (pVM)->enmVMState == VMSTATE_RUNNING_LS \
1011	\|\| (pVM)->enmVMState == VMSTATE_RUNNING_FT )
1012
1013	/** @def VM_ASSERT_IS_NOT_RUNNING
1014	* Asserts that the VM is not running.
1015	*/
1016	#if defined(IN_RC) \|\| defined(IN_RING0)
1017	#define VM_ASSERT_IS_NOT_RUNNING(pVM) Assert(!VM_IS_RUNNING_FOR_ASSERTIONS_ONLY(pVM))
1018	#else
1019	#define VM_ASSERT_IS_NOT_RUNNING(pVM) AssertMsg(!VM_IS_RUNNING_FOR_ASSERTIONS_ONLY(pVM), \
1020	("VM is running. enmVMState=%d\n", (pVM)->enmVMState))
1021	#endif
1022
1023	/** @def VM_ASSERT_EMT0
1024	* Asserts that the current thread IS emulation thread \#0 (EMT0).
1025	*/
1026	#define VM_ASSERT_EMT0(pVM) VMCPU_ASSERT_EMT(&(pVM)->aCpus[0])
1027
1028	/** @def VM_ASSERT_EMT0_RETURN
1029	* Asserts that the current thread IS emulation thread \#0 (EMT0) and returns if
1030	* it isn't.
1031	*/
1032	#define VM_ASSERT_EMT0_RETURN(pVM, rc) VMCPU_ASSERT_EMT_RETURN(&(pVM)->aCpus[0], (rc))
1033
1034
1035	/**
1036	* Asserts that the current thread is NOT the emulation thread.
1037	*/
1038	#define VM_ASSERT_OTHER_THREAD(pVM) \
1039	AssertMsg(!VM_IS_EMT(pVM), ("Not other thread!!\n"))
1040
1041
1042	/** @def VM_ASSERT_STATE
1043	* Asserts a certain VM state.
1044	*/
1045	#define VM_ASSERT_STATE(pVM, _enmState) \
1046	AssertMsg((pVM)->enmVMState == (_enmState), \
1047	("state %s, expected %s\n", VMGetStateName((pVM)->enmVMState), VMGetStateName(_enmState)))
1048
1049	/** @def VM_ASSERT_STATE_RETURN
1050	* Asserts a certain VM state and returns if it doesn't match.
1051	*/
1052	#define VM_ASSERT_STATE_RETURN(pVM, _enmState, rc) \
1053	AssertMsgReturn((pVM)->enmVMState == (_enmState), \
1054	("state %s, expected %s\n", VMGetStateName((pVM)->enmVMState), VMGetStateName(_enmState)), \
1055	(rc))
1056
1057	/** @def VM_IS_VALID_EXT
1058	* Asserts a the VM handle is valid for external access, i.e. not being destroy
1059	* or terminated. */
1060	#define VM_IS_VALID_EXT(pVM) \
1061	( RT_VALID_ALIGNED_PTR(pVM, PAGE_SIZE) \
1062	&& ( (unsigned)(pVM)->enmVMState < (unsigned)VMSTATE_DESTROYING \
1063	\|\| ( (unsigned)(pVM)->enmVMState == (unsigned)VMSTATE_DESTROYING \
1064	&& VM_IS_EMT(pVM))) )
1065
1066	/** @def VM_ASSERT_VALID_EXT_RETURN
1067	* Asserts a the VM handle is valid for external access, i.e. not being
1068	* destroy or terminated.
1069	*/
1070	#define VM_ASSERT_VALID_EXT_RETURN(pVM, rc) \
1071	AssertMsgReturn(VM_IS_VALID_EXT(pVM), \
1072	("pVM=%p state %s\n", (pVM), RT_VALID_ALIGNED_PTR(pVM, PAGE_SIZE) \
1073	? VMGetStateName(pVM->enmVMState) : ""), \
1074	(rc))
1075
1076	/** @def VMCPU_ASSERT_VALID_EXT_RETURN
1077	* Asserts a the VMCPU handle is valid for external access, i.e. not being
1078	* destroy or terminated.
1079	*/
1080	#define VMCPU_ASSERT_VALID_EXT_RETURN(pVCpu, rc) \
1081	AssertMsgReturn( RT_VALID_ALIGNED_PTR(pVCpu, 64) \
1082	&& RT_VALID_ALIGNED_PTR((pVCpu)->CTX_SUFF(pVM), PAGE_SIZE) \
1083	&& (unsigned)(pVCpu)->CTX_SUFF(pVM)->enmVMState < (unsigned)VMSTATE_DESTROYING, \
1084	("pVCpu=%p pVM=%p state %s\n", (pVCpu), RT_VALID_ALIGNED_PTR(pVCpu, 64) ? (pVCpu)->CTX_SUFF(pVM) : NULL, \
1085	RT_VALID_ALIGNED_PTR(pVCpu, 64) && RT_VALID_ALIGNED_PTR((pVCpu)->CTX_SUFF(pVM), PAGE_SIZE) \
1086	? VMGetStateName((pVCpu)->pVMR3->enmVMState) : ""), \
1087	(rc))
1088
1089	#endif /* !VBOX_FOR_DTRACE_LIB */
1090
1091
1092	/**
1093	* Helper that HM and NEM uses for safely modifying VM::bMainExecutionEngine.
1094	*
1095	* ONLY HM and NEM MAY USE THIS!
1096	*
1097	* @param a_pVM The cross context VM structure.
1098	* @param a_bValue The new value.
1099	* @internal
1100	*/
1101	#define VM_SET_MAIN_EXECUTION_ENGINE(a_pVM, a_bValue) \
1102	do { \
1103	const_cast<uint8_t >(&(a_pVM)->bMainExecutionEngine) = (a_bValue); \
1104	ASMCompilerBarrier(); /* just to be on the safe side */ \
1105	} while (0)
1106
1107	/**
1108	* Checks whether raw-mode is used.
1109	*
1110	* @retval true if either is used.
1111	* @retval false if software virtualization (raw-mode) is used.
1112	*
1113	* @param a_pVM The cross context VM structure.
1114	* @sa VM_IS_HM_OR_NEM_ENABLED, VM_IS_HM_ENABLED, VM_IS_NEM_ENABLED.
1115	* @internal
1116	*/
1117	#ifdef VBOX_WITH_RAW_MODE
1118	# define VM_IS_RAW_MODE_ENABLED(a_pVM) ((a_pVM)->bMainExecutionEngine == VM_EXEC_ENGINE_RAW_MODE)
1119	#else
1120	# define VM_IS_RAW_MODE_ENABLED(a_pVM) (false)
1121	#endif
1122
1123	/**
1124	* Checks whether HM (VT-x/AMD-V) or NEM is being used by this VM.
1125	*
1126	* @retval true if either is used.
1127	* @retval false if software virtualization (raw-mode) is used.
1128	*
1129	* @param a_pVM The cross context VM structure.
1130	* @sa VM_IS_RAW_MODE_ENABLED, VM_IS_HM_ENABLED, VM_IS_NEM_ENABLED.
1131	* @internal
1132	*/
1133	#define VM_IS_HM_OR_NEM_ENABLED(a_pVM) ((a_pVM)->bMainExecutionEngine != VM_EXEC_ENGINE_RAW_MODE)
1134
1135	/**
1136	* Checks whether HM is being used by this VM.
1137	*
1138	* @retval true if HM (VT-x/AMD-v) is used.
1139	* @retval false if not.
1140	*
1141	* @param a_pVM The cross context VM structure.
1142	* @sa VM_IS_NEM_ENABLED, VM_IS_RAW_MODE_ENABLED, VM_IS_HM_OR_NEM_ENABLED.
1143	* @internal
1144	*/
1145	#define VM_IS_HM_ENABLED(a_pVM) ((a_pVM)->bMainExecutionEngine == VM_EXEC_ENGINE_HW_VIRT)
1146
1147	/**
1148	* Checks whether NEM is being used by this VM.
1149	*
1150	* @retval true if a native hypervisor API is used.
1151	* @retval false if not.
1152	*
1153	* @param a_pVM The cross context VM structure.
1154	* @sa VM_IS_HM_ENABLED, VM_IS_RAW_MODE_ENABLED, VM_IS_HM_OR_NEM_ENABLED.
1155	* @internal
1156	*/
1157	#define VM_IS_NEM_ENABLED(a_pVM) ((a_pVM)->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API)
1158
1159
1160	/**
1161	* The cross context VM structure.
1162	*
1163	* It contains all the VM data which have to be available in all contexts.
1164	* Even if it contains all the data the idea is to use APIs not to modify all
1165	* the members all around the place. Therefore we make use of unions to hide
1166	* everything which isn't local to the current source module. This means we'll
1167	* have to pay a little bit of attention when adding new members to structures
1168	* in the unions and make sure to keep the padding sizes up to date.
1169	*
1170	* Run 'kmk run-struct-tests' (from src/VBox/VMM if you like) after updating!
1171	*/
1172	typedef struct VM
1173	{
1174	/** The state of the VM.
1175	* This field is read only to everyone except the VM and EM. */
1176	VMSTATE volatile enmVMState;
1177	/** Forced action flags.
1178	* See the VM_FF_* \#defines. Updated atomically.
1179	*/
1180	volatile uint32_t fGlobalForcedActions;
1181	/** Pointer to the array of page descriptors for the VM structure allocation. */
1182	R3PTRTYPE(PSUPPAGE) paVMPagesR3;
1183	/** Session handle. For use when calling SUPR0 APIs. */
1184	PSUPDRVSESSION pSession;
1185	/** Pointer to the ring-3 VM structure. */
1186	PUVM pUVM;
1187	/** Ring-3 Host Context VM Pointer. */
1188	R3PTRTYPE(struct VM *) pVMR3;
1189	/** Ring-0 Host Context VM Pointer. */
1190	R0PTRTYPE(struct VM *) pVMR0;
1191	/** Raw-mode Context VM Pointer. */
1192	RCPTRTYPE(struct VM *) pVMRC;
1193
1194	/** The GVM VM handle. Only the GVM should modify this field. */
1195	uint32_t hSelf;
1196	/** Number of virtual CPUs. */
1197	uint32_t cCpus;
1198	/** CPU excution cap (1-100) */
1199	uint32_t uCpuExecutionCap;
1200
1201	#ifdef VBOX_BUGREF_9217
1202	/** Structure version number (TBD). */
1203	uint32_t uStructVersion;
1204	/** Size of the VM structure. */
1205	uint32_t cbSelf;
1206	/** Size of the VMCPU structure. */
1207	uint32_t cbVCpu;
1208	#else
1209	/** Size of the VM structure including the VMCPU array. */
1210	uint32_t cbSelf;
1211	#endif
1212
1213	#ifdef VBOX_WITH_RAW_MODE
1214	/** Offset to the VMCPU array starting from beginning of this structure,
1215	* for raw-mode assembly code. */
1216	uint32_t offVMCPU;
1217	#else
1218	uint32_t u32Unused;
1219	#endif
1220
1221	/**
1222	* VMMSwitcher assembly entry point returning to host context.
1223	*
1224	* Depending on how the host handles the rc status given in @a eax, this may
1225	* return and let the caller resume whatever it was doing prior to the call.
1226	*
1227	* @param eax The return code, register.
1228	* @remark Assume interrupts disabled.
1229	* @remark This method pointer lives here because TRPM needs it.
1230	*/
1231	RTRCPTR pfnVMMRCToHostAsm/(int32_t eax)/;
1232
1233	/**
1234	* VMMSwitcher assembly entry point returning to host context without saving the
1235	* raw-mode context (hyper) registers.
1236	*
1237	* Unlike pfnVMMRC2HCAsm, this will not return to the caller. Instead it
1238	* expects the caller to save a RC context in CPUM where one might return if the
1239	* return code indicate that this is possible.
1240	*
1241	* This method pointer lives here because TRPM needs it.
1242	*
1243	* @param eax The return code, register.
1244	* @remark Assume interrupts disabled.
1245	* @remark This method pointer lives here because TRPM needs it.
1246	*/
1247	RTRCPTR pfnVMMRCToHostAsmNoReturn/(int32_t eax)/;
1248
1249	/** @name Various items that are frequently accessed.
1250	* @{ */
1251	/** The main execution engine, VM_EXEC_ENGINE_XXX.
1252	* This is set early during vmR3InitRing3 by HM or NEM. */
1253	uint8_t const bMainExecutionEngine;
1254
1255	/** Whether to recompile user mode code or run it raw/hm/nem.
1256	* In non-raw-mode both fRecompileUser and fRecompileSupervisor must be set
1257	* to recompiler stuff. */
1258	bool fRecompileUser;
1259	/** Whether to recompile supervisor mode code or run it raw/hm/nem.
1260	* In non-raw-mode both fRecompileUser and fRecompileSupervisor must be set
1261	* to recompiler stuff. */
1262	bool fRecompileSupervisor;
1263	/** Whether raw mode supports ring-1 code or not.
1264	* This will be cleared when not in raw-mode. */
1265	bool fRawRing1Enabled;
1266	/** PATM enabled flag.
1267	* This is placed here for performance reasons.
1268	* This will be cleared when not in raw-mode. */
1269	bool fPATMEnabled;
1270	/** CSAM enabled flag.
1271	* This is placed here for performance reasons.
1272	* This will be cleared when not in raw-mode. */
1273	bool fCSAMEnabled;
1274
1275	/** Hardware VM support is available and enabled.
1276	* Determined very early during init.
1277	* This is placed here for performance reasons.
1278	* @todo obsoleted by bMainExecutionEngine, eliminate. */
1279	bool fHMEnabled;
1280	/** Hardware VM support requires a minimal raw-mode context.
1281	* This is never set on 64-bit hosts, only 32-bit hosts requires it. */
1282	bool fHMNeedRawModeCtx;
1283
1284	/** Set when this VM is the master FT node.
1285	* @todo This doesn't need to be here, FTM should store it in it's own
1286	* structures instead. */
1287	bool fFaultTolerantMaster;
1288	/** Large page enabled flag.
1289	* @todo This doesn't need to be here, PGM should store it in it's own
1290	* structures instead. */
1291	bool fUseLargePages;
1292	/** @} */
1293
1294	/** Alignment padding. */
1295	uint8_t uPadding1[2];
1296
1297	/** @name Debugging
1298	* @{ */
1299	/** Raw-mode Context VM Pointer. */
1300	RCPTRTYPE(RTTRACEBUF) hTraceBufRC;
1301	/** Ring-3 Host Context VM Pointer. */
1302	R3PTRTYPE(RTTRACEBUF) hTraceBufR3;
1303	/** Ring-0 Host Context VM Pointer. */
1304	R0PTRTYPE(RTTRACEBUF) hTraceBufR0;
1305	/** @} */
1306
1307	#if HC_ARCH_BITS == 32
1308	/** Alignment padding. */
1309	uint32_t uPadding2;
1310	#endif
1311
1312	/** @name Switcher statistics (remove)
1313	* @{ */
1314	/** Profiling the total time from Qemu to GC. */
1315	STAMPROFILEADV StatTotalQemuToGC;
1316	/** Profiling the total time from GC to Qemu. */
1317	STAMPROFILEADV StatTotalGCToQemu;
1318	/** Profiling the total time spent in GC. */
1319	STAMPROFILEADV StatTotalInGC;
1320	/** Profiling the total time spent not in Qemu. */
1321	STAMPROFILEADV StatTotalInQemu;
1322	/** Profiling the VMMSwitcher code for going to GC. */
1323	STAMPROFILEADV StatSwitcherToGC;
1324	/** Profiling the VMMSwitcher code for going to HC. */
1325	STAMPROFILEADV StatSwitcherToHC;
1326	STAMPROFILEADV StatSwitcherSaveRegs;
1327	STAMPROFILEADV StatSwitcherSysEnter;
1328	STAMPROFILEADV StatSwitcherDebug;
1329	STAMPROFILEADV StatSwitcherCR0;
1330	STAMPROFILEADV StatSwitcherCR4;
1331	STAMPROFILEADV StatSwitcherJmpCR3;
1332	STAMPROFILEADV StatSwitcherRstrRegs;
1333	STAMPROFILEADV StatSwitcherLgdt;
1334	STAMPROFILEADV StatSwitcherLidt;
1335	STAMPROFILEADV StatSwitcherLldt;
1336	STAMPROFILEADV StatSwitcherTSS;
1337	/** @} */
1338
1339	/** Padding - the unions must be aligned on a 64 bytes boundary and the unions
1340	* must start at the same offset on both 64-bit and 32-bit hosts. */
1341	#ifdef VBOX_BUGREF_9217
1342	uint8_t abAlignment3[(HC_ARCH_BITS == 32 ? 24 : 0) + 32];
1343	#else
1344	uint8_t abAlignment3[(HC_ARCH_BITS == 32 ? 24 : 0) + 40];
1345	#endif
1346
1347	/** CPUM part. */
1348	union
1349	{
1350	#ifdef VMM_INCLUDED_SRC_include_CPUMInternal_h
1351	struct CPUM s;
1352	#endif
1353	#ifdef VBOX_INCLUDED_vmm_cpum_h
1354	/** Read only info exposed about the host and guest CPUs. */
1355	struct
1356	{
1357	/** Padding for hidden fields. */
1358	uint8_t abHidden0[64];
1359	/** Host CPU feature information. */
1360	CPUMFEATURES HostFeatures;
1361	/** Guest CPU feature information. */
1362	CPUMFEATURES GuestFeatures;
1363	} const ro;
1364	#endif
1365	uint8_t padding[1536]; /* multiple of 64 */
1366	} cpum;
1367
1368	/** VMM part. */
1369	union
1370	{
1371	#ifdef VMM_INCLUDED_SRC_include_VMMInternal_h
1372	struct VMM s;
1373	#endif
1374	uint8_t padding[1600]; /* multiple of 64 */
1375	} vmm;
1376
1377	/** PGM part. */
1378	union
1379	{
1380	#ifdef VMM_INCLUDED_SRC_include_PGMInternal_h
1381	struct PGM s;
1382	#endif
1383	uint8_t padding[40962+6080]; / multiple of 64 */
1384	} pgm;
1385
1386	/** HM part. */
1387	union
1388	{
1389	#ifdef VMM_INCLUDED_SRC_include_HMInternal_h
1390	struct HM s;
1391	#endif
1392	uint8_t padding[5440]; /* multiple of 64 */
1393	} hm;
1394
1395	/** TRPM part. */
1396	union
1397	{
1398	#ifdef VMM_INCLUDED_SRC_include_TRPMInternal_h
1399	struct TRPM s;
1400	#endif
1401	uint8_t padding[5248]; /* multiple of 64 */
1402	} trpm;
1403
1404	/** SELM part. */
1405	union
1406	{
1407	#ifdef VMM_INCLUDED_SRC_include_SELMInternal_h
1408	struct SELM s;
1409	#endif
1410	uint8_t padding[768]; /* multiple of 64 */
1411	} selm;
1412
1413	/** MM part. */
1414	union
1415	{
1416	#ifdef VMM_INCLUDED_SRC_include_MMInternal_h
1417	struct MM s;
1418	#endif
1419	uint8_t padding[192]; /* multiple of 64 */
1420	} mm;
1421
1422	/** PDM part. */
1423	union
1424	{
1425	#ifdef VMM_INCLUDED_SRC_include_PDMInternal_h
1426	struct PDM s;
1427	#endif
1428	uint8_t padding[1920]; /* multiple of 64 */
1429	} pdm;
1430
1431	/** IOM part. */
1432	union
1433	{
1434	#ifdef VMM_INCLUDED_SRC_include_IOMInternal_h
1435	struct IOM s;
1436	#endif
1437	uint8_t padding[896]; /* multiple of 64 */
1438	} iom;
1439
1440	/** EM part. */
1441	union
1442	{
1443	#ifdef VMM_INCLUDED_SRC_include_EMInternal_h
1444	struct EM s;
1445	#endif
1446	uint8_t padding[256]; /* multiple of 64 */
1447	} em;
1448
1449	/** NEM part. */
1450	union
1451	{
1452	#ifdef VMM_INCLUDED_SRC_include_NEMInternal_h
1453	struct NEM s;
1454	#endif
1455	uint8_t padding[128]; /* multiple of 64 */
1456	} nem;
1457
1458	/** TM part. */
1459	union
1460	{
1461	#ifdef VMM_INCLUDED_SRC_include_TMInternal_h
1462	struct TM s;
1463	#endif
1464	uint8_t padding[2496]; /* multiple of 64 */
1465	} tm;
1466
1467	/** DBGF part. */
1468	union
1469	{
1470	#ifdef VMM_INCLUDED_SRC_include_DBGFInternal_h
1471	struct DBGF s;
1472	#endif
1473	#ifdef VBOX_INCLUDED_vmm_dbgf_h
1474	/** Read only info exposed about interrupt breakpoints and selected events. */
1475	struct
1476	{
1477	/** Bitmap of enabled hardware interrupt breakpoints. */
1478	uint32_t bmHardIntBreakpoints[256 / 32];
1479	/** Bitmap of enabled software interrupt breakpoints. */
1480	uint32_t bmSoftIntBreakpoints[256 / 32];
1481	/** Bitmap of selected events.
1482	* This includes non-selectable events too for simplicity, we maintain the
1483	* state for some of these, as it may come in handy. */
1484	uint64_t bmSelectedEvents[(DBGFEVENT_END + 63) / 64];
1485	/** Enabled hardware interrupt breakpoints. */
1486	uint32_t cHardIntBreakpoints;
1487	/** Enabled software interrupt breakpoints. */
1488	uint32_t cSoftIntBreakpoints;
1489	/** The number of selected events. */
1490	uint32_t cSelectedEvents;
1491	/** The number of enabled hardware breakpoints. */
1492	uint8_t cEnabledHwBreakpoints;
1493	/** The number of enabled hardware I/O breakpoints. */
1494	uint8_t cEnabledHwIoBreakpoints;
1495	/** The number of enabled INT3 breakpoints. */
1496	uint8_t cEnabledInt3Breakpoints;
1497	uint8_t abPadding[1]; /*< Unused padding space up for grabs. /
1498	} const ro;
1499	#endif
1500	uint8_t padding[2432]; /* multiple of 64 */
1501	} dbgf;
1502
1503	/** SSM part. */
1504	union
1505	{
1506	#ifdef VMM_INCLUDED_SRC_include_SSMInternal_h
1507	struct SSM s;
1508	#endif
1509	uint8_t padding[128]; /* multiple of 64 */
1510	} ssm;
1511
1512	/** FTM part. */
1513	union
1514	{
1515	#ifdef VMM_INCLUDED_SRC_include_FTMInternal_h
1516	struct FTM s;
1517	#endif
1518	uint8_t padding[512]; /* multiple of 64 */
1519	} ftm;
1520
1521	#ifdef VBOX_WITH_RAW_MODE
1522	/** PATM part. */
1523	union
1524	{
1525	# ifdef VMM_INCLUDED_SRC_include_PATMInternal_h
1526	struct PATM s;
1527	# endif
1528	uint8_t padding[768]; /* multiple of 64 */
1529	} patm;
1530
1531	/** CSAM part. */
1532	union
1533	{
1534	# ifdef VMM_INCLUDED_SRC_include_CSAMInternal_h
1535	struct CSAM s;
1536	# endif
1537	uint8_t padding[1088]; /* multiple of 64 */
1538	} csam;
1539	#endif
1540
1541	#ifdef VBOX_WITH_REM
1542	/** REM part. */
1543	union
1544	{
1545	# ifdef VMM_INCLUDED_SRC_include_REMInternal_h
1546	struct REM s;
1547	# endif
1548	uint8_t padding[0x11100]; /* multiple of 64 */
1549	} rem;
1550	#endif
1551
1552	union
1553	{
1554	#ifdef VMM_INCLUDED_SRC_include_GIMInternal_h
1555	struct GIM s;
1556	#endif
1557	uint8_t padding[448]; /* multiple of 64 */
1558	} gim;
1559
1560	union
1561	{
1562	#ifdef VMM_INCLUDED_SRC_include_APICInternal_h
1563	struct APIC s;
1564	#endif
1565	uint8_t padding[128]; /* multiple of 8 */
1566	} apic;
1567
1568	/* ---- begin small stuff ---- */
1569
1570	/** VM part. */
1571	union
1572	{
1573	#ifdef VMM_INCLUDED_SRC_include_VMInternal_h
1574	struct VMINT s;
1575	#endif
1576	uint8_t padding[32]; /* multiple of 8 */
1577	} vm;
1578
1579	/** CFGM part. */
1580	union
1581	{
1582	#ifdef VMM_INCLUDED_SRC_include_CFGMInternal_h
1583	struct CFGM s;
1584	#endif
1585	uint8_t padding[8]; /* multiple of 8 */
1586	} cfgm;
1587
1588	#ifdef VBOX_BUGREF_9217
1589	/** Padding for aligning the structure size on a page boundrary. */
1590	# if defined(VBOX_WITH_REM) && defined(VBOX_WITH_RAW_MODE)
1591	uint8_t abAlignment2[3670 - sizeof(PVMCPUR3) * VMM_MAX_CPU_COUNT];
1592	# elif defined(VBOX_WITH_REM) && !defined(VBOX_WITH_RAW_MODE)
1593	uint8_t abAlignment2[1430 - sizeof(PVMCPUR3) * VMM_MAX_CPU_COUNT];
1594	# elif !defined(VBOX_WITH_REM) && defined(VBOX_WITH_RAW_MODE)
1595	uint8_t abAlignment2[3926 - sizeof(PVMCPUR3) * VMM_MAX_CPU_COUNT];
1596	# else
1597	uint8_t abAlignment2[1686 - sizeof(PVMCPUR3) * VMM_MAX_CPU_COUNT];
1598	# endif
1599	#else
1600	/** Padding for aligning the cpu array on a page boundary. */
1601	# if defined(VBOX_WITH_REM) && defined(VBOX_WITH_RAW_MODE)
1602	uint8_t abAlignment2[3670];
1603	# elif defined(VBOX_WITH_REM) && !defined(VBOX_WITH_RAW_MODE)
1604	uint8_t abAlignment2[1430];
1605	# elif !defined(VBOX_WITH_REM) && defined(VBOX_WITH_RAW_MODE)
1606	uint8_t abAlignment2[3926];
1607	# else
1608	uint8_t abAlignment2[1686];
1609	# endif
1610	#endif
1611
1612	/* ---- end small stuff ---- */
1613
1614	#ifdef VBOX_BUGREF_9217
1615	/** Array of VMCPU pointers. */
1616	PVMCPUR3 apCpus[VMM_MAX_CPU_COUNT];
1617	#else
1618	/** VMCPU array for the configured number of virtual CPUs.
1619	* Must be aligned on a page boundary for TLB hit reasons as well as
1620	* alignment of VMCPU members. */
1621	VMCPU aCpus[1];
1622	#endif
1623	} VM;
1624
1625
1626	#ifdef IN_RC
1627	RT_C_DECLS_BEGIN
1628
1629	/** The VM structure.
1630	* This is imported from the VMMRCBuiltin module, i.e. it's a one of those magic
1631	* globals which we should avoid using.
1632	*/
1633	extern DECLIMPORT(VM) g_VM;
1634
1635	RT_C_DECLS_END
1636	#endif
1637
1638	/** @} */
1639
1640	#endif /* !VBOX_INCLUDED_vmm_vm_h */
1641

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source: vbox/trunk/include/VBox/vmm/vm.h@ 78431

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