vm.h@ 79146

Last change on this file since 79146 was 78438, checked in by vboxsync, 6 years ago
VMM: More refactoring of GVM & VM structures for bugref:9217
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1	/** @file
2	* VM - The Virtual Machine, data.
3	*/
4
5	/*
6	* Copyright (C) 2006-2019 Oracle Corporation
7	*
8	* This file is part of VirtualBox Open Source Edition (OSE), as
9	* available from http://www.virtualbox.org. This file is free software;
10	* you can redistribute it and/or modify it under the terms of the GNU
11	* General Public License (GPL) as published by the Free Software
12	* Foundation, in version 2 as it comes in the "COPYING" file of the
13	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15	*
16	* The contents of this file may alternatively be used under the terms
17	* of the Common Development and Distribution License Version 1.0
18	* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19	* VirtualBox OSE distribution, in which case the provisions of the
20	* CDDL are applicable instead of those of the GPL.
21	*
22	* You may elect to license modified versions of this file under the
23	* terms and conditions of either the GPL or the CDDL or both.
24	*/
25
26	#ifndef VBOX_INCLUDED_vmm_vm_h
27	#define VBOX_INCLUDED_vmm_vm_h
28	#ifndef RT_WITHOUT_PRAGMA_ONCE
29	# pragma once
30	#endif
31
32	#ifndef VBOX_FOR_DTRACE_LIB
33	# include <iprt/param.h>
34	# include <VBox/param.h>
35	# include <VBox/types.h>
36	# include <VBox/vmm/cpum.h>
37	# include <VBox/vmm/stam.h>
38	# include <VBox/vmm/vmapi.h>
39	# include <VBox/vmm/vmm.h>
40	# include <VBox/sup.h>
41	#else
42	# pragma D depends_on library vbox-types.d
43	# pragma D depends_on library CPUMInternal.d
44	# define VMM_INCLUDED_SRC_include_CPUMInternal_h
45	#endif
46
47
48
49	/** @defgroup grp_vm The Virtual Machine
50	* @ingroup grp_vmm
51	* @{
52	*/
53
54	/**
55	* The state of a Virtual CPU.
56	*
57	* The basic state indicated here is whether the CPU has been started or not. In
58	* addition, there are sub-states when started for assisting scheduling (GVMM
59	* mostly).
60	*
61	* The transition out of the STOPPED state is done by a vmR3PowerOn.
62	* The transition back to the STOPPED state is done by vmR3PowerOff.
63	*
64	* (Alternatively we could let vmR3PowerOn start CPU 0 only and let the SPIP
65	* handling switch on the other CPUs. Then vmR3Reset would stop all but CPU 0.)
66	*/
67	typedef enum VMCPUSTATE
68	{
69	/** The customary invalid zero. */
70	VMCPUSTATE_INVALID = 0,
71
72	/** Virtual CPU has not yet been started. */
73	VMCPUSTATE_STOPPED,
74
75	/** CPU started. */
76	VMCPUSTATE_STARTED,
77	/** CPU started in HM context. */
78	VMCPUSTATE_STARTED_HM,
79	/** Executing guest code and can be poked (RC or STI bits of HM). */
80	VMCPUSTATE_STARTED_EXEC,
81	/** Executing guest code in the recompiler. */
82	VMCPUSTATE_STARTED_EXEC_REM,
83	/** Executing guest code using NEM. */
84	VMCPUSTATE_STARTED_EXEC_NEM,
85	VMCPUSTATE_STARTED_EXEC_NEM_WAIT,
86	VMCPUSTATE_STARTED_EXEC_NEM_CANCELED,
87	/** Halted. */
88	VMCPUSTATE_STARTED_HALTED,
89
90	/** The end of valid virtual CPU states. */
91	VMCPUSTATE_END,
92
93	/** Ensure 32-bit type. */
94	VMCPUSTATE_32BIT_HACK = 0x7fffffff
95	} VMCPUSTATE;
96
97	/** Enables 64-bit FFs. */
98	#define VMCPU_WITH_64_BIT_FFS
99
100
101	/**
102	* The cross context virtual CPU structure.
103	*
104	* Run 'kmk run-struct-tests' (from src/VBox/VMM if you like) after updating!
105	*/
106	typedef struct VMCPU
107	{
108	/** @name Volatile per-cpu data.
109	* @{ */
110	/** Per CPU forced action.
111	* See the VMCPU_FF_* \#defines. Updated atomically. */
112	#ifdef VMCPU_WITH_64_BIT_FFS
113	uint64_t volatile fLocalForcedActions;
114	#else
115	uint32_t volatile fLocalForcedActions;
116	uint32_t fForLocalForcedActionsExpansion;
117	#endif
118	/** The CPU state. */
119	VMCPUSTATE volatile enmState;
120
121	/** Which host CPU ID is this EMT running on.
122	* Only valid when in RC or HMR0 with scheduling disabled. */
123	RTCPUID volatile idHostCpu;
124	/** The CPU set index corresponding to idHostCpu, UINT32_MAX if not valid.
125	* @remarks Best to make sure iHostCpuSet shares cache line with idHostCpu! */
126	uint32_t volatile iHostCpuSet;
127	/** Padding up to 64 bytes. */
128	uint8_t abAlignment0[64 - 20];
129	/** @} */
130
131	/** IEM part.
132	* @remarks This comes first as it allows the use of 8-bit immediates for the
133	* first 64 bytes of the structure, reducing code size a wee bit. */
134	#ifdef VMM_INCLUDED_SRC_include_IEMInternal_h /* For PDB hacking. */
135	union VMCPUUNIONIEMFULL
136	#else
137	union VMCPUUNIONIEMSTUB
138	#endif
139	{
140	#ifdef VMM_INCLUDED_SRC_include_IEMInternal_h
141	struct IEMCPU s;
142	#endif
143	uint8_t padding[18496]; /* multiple of 64 */
144	} iem;
145
146	/** @name Static per-cpu data.
147	* (Putting this after IEM, hoping that it's less frequently used than it.)
148	* @{ */
149	/** The CPU ID.
150	* This is the index into the VM::aCpu array. */
151	VMCPUID idCpu;
152	/** Raw-mode Context VM Pointer. */
153	PVMRC pVMRC;
154	/** Ring-3 Host Context VM Pointer. */
155	PVMR3 pVMR3;
156	/** Ring-0 Host Context VM Pointer. */
157	PVMR0 pVMR0;
158	/** Pointer to the ring-3 UVMCPU structure. */
159	PUVMCPU pUVCpu;
160	/** The native thread handle. */
161	RTNATIVETHREAD hNativeThread;
162	/** The native R0 thread handle. (different from the R3 handle!) */
163	RTNATIVETHREAD hNativeThreadR0;
164	/** Align the structures below bit on a 64-byte boundary and make sure it starts
165	* at the same offset in both 64-bit and 32-bit builds.
166	*
167	* @remarks The alignments of the members that are larger than 48 bytes should be
168	* 64-byte for cache line reasons. structs containing small amounts of
169	* data could be lumped together at the end with a < 64 byte padding
170	* following it (to grow into and align the struct size).
171	*/
172	uint8_t abAlignment1[64 - 4 - 4 - 5 * (HC_ARCH_BITS == 64 ? 8 : 4)];
173	/** @} */
174
175	/** HM part. */
176	union VMCPUUNIONHM
177	{
178	#ifdef VMM_INCLUDED_SRC_include_HMInternal_h
179	struct HMCPU s;
180	#endif
181	uint8_t padding[5888]; /* multiple of 64 */
182	} hm;
183
184	/** NEM part. */
185	union VMCPUUNIONNEM
186	{
187	#ifdef VMM_INCLUDED_SRC_include_NEMInternal_h
188	struct NEMCPU s;
189	#endif
190	uint8_t padding[512]; /* multiple of 64 */
191	} nem;
192
193	/** TRPM part. */
194	union VMCPUUNIONTRPM
195	{
196	#ifdef VMM_INCLUDED_SRC_include_TRPMInternal_h
197	struct TRPMCPU s;
198	#endif
199	uint8_t padding[128]; /* multiple of 64 */
200	} trpm;
201
202	/** TM part. */
203	union VMCPUUNIONTM
204	{
205	#ifdef VMM_INCLUDED_SRC_include_TMInternal_h
206	struct TMCPU s;
207	#endif
208	uint8_t padding[384]; /* multiple of 64 */
209	} tm;
210
211	/** VMM part. */
212	union VMCPUUNIONVMM
213	{
214	#ifdef VMM_INCLUDED_SRC_include_VMMInternal_h
215	struct VMMCPU s;
216	#endif
217	uint8_t padding[896]; /* multiple of 64 */
218	} vmm;
219
220	/** PDM part. */
221	union VMCPUUNIONPDM
222	{
223	#ifdef VMM_INCLUDED_SRC_include_PDMInternal_h
224	struct PDMCPU s;
225	#endif
226	uint8_t padding[256]; /* multiple of 64 */
227	} pdm;
228
229	/** IOM part. */
230	union VMCPUUNIONIOM
231	{
232	#ifdef VMM_INCLUDED_SRC_include_IOMInternal_h
233	struct IOMCPU s;
234	#endif
235	uint8_t padding[512]; /* multiple of 64 */
236	} iom;
237
238	/** DBGF part.
239	* @todo Combine this with other tiny structures. */
240	union VMCPUUNIONDBGF
241	{
242	#ifdef VMM_INCLUDED_SRC_include_DBGFInternal_h
243	struct DBGFCPU s;
244	#endif
245	uint8_t padding[256]; /* multiple of 64 */
246	} dbgf;
247
248	/** GIM part. */
249	union VMCPUUNIONGIM
250	{
251	#ifdef VMM_INCLUDED_SRC_include_GIMInternal_h
252	struct GIMCPU s;
253	#endif
254	uint8_t padding[512]; /* multiple of 64 */
255	} gim;
256
257	/** APIC part. */
258	union VMCPUUNIONAPIC
259	{
260	#ifdef VMM_INCLUDED_SRC_include_APICInternal_h
261	struct APICCPU s;
262	#endif
263	uint8_t padding[1792]; /* multiple of 64 */
264	} apic;
265
266	/*
267	* Some less frequently used global members that doesn't need to take up
268	* precious space at the head of the structure.
269	*/
270
271	/** Trace groups enable flags. */
272	uint32_t fTraceGroups; /* 64 / 44 */
273	/** State data for use by ad hoc profiling. */
274	uint32_t uAdHoc;
275	/** Profiling samples for use by ad hoc profiling. */
276	STAMPROFILEADV aStatAdHoc[8]; /* size: 408 = 320 /
277
278	/** Align the following members on page boundary. */
279	uint8_t abAlignment2[2680];
280
281	/** PGM part. */
282	union VMCPUUNIONPGM
283	{
284	#ifdef VMM_INCLUDED_SRC_include_PGMInternal_h
285	struct PGMCPU s;
286	#endif
287	uint8_t padding[4096]; /* multiple of 4096 */
288	} pgm;
289
290	/** CPUM part. */
291	union VMCPUUNIONCPUM
292	{
293	#ifdef VMM_INCLUDED_SRC_include_CPUMInternal_h
294	struct CPUMCPU s;
295	#endif
296	#ifdef VMCPU_INCL_CPUM_GST_CTX
297	/** The guest CPUM context for direct use by execution engines.
298	* This is not for general consumption, but for HM, REM, IEM, and maybe a few
299	* others. The rest will use the function based CPUM API. */
300	CPUMCTX GstCtx;
301	#endif
302	uint8_t padding[4096]; /* multiple of 4096 */
303	} cpum;
304
305	/** EM part. */
306	union VMCPUUNIONEM
307	{
308	#ifdef VMM_INCLUDED_SRC_include_EMInternal_h
309	struct EMCPU s;
310	#endif
311	uint8_t padding[40960]; /* multiple of 4096 */
312	} em;
313	} VMCPU;
314
315
316	#ifndef VBOX_FOR_DTRACE_LIB
317	AssertCompileSizeAlignment(VMCPU, 4096);
318
319	/** @name Operations on VMCPU::enmState
320	* @{ */
321	/** Gets the VMCPU state. */
322	#define VMCPU_GET_STATE(pVCpu) ( (pVCpu)->enmState )
323	/** Sets the VMCPU state. */
324	#define VMCPU_SET_STATE(pVCpu, enmNewState) \
325	ASMAtomicWriteU32((uint32_t volatile *)&(pVCpu)->enmState, (enmNewState))
326	/** Cmpares and sets the VMCPU state. */
327	#define VMCPU_CMPXCHG_STATE(pVCpu, enmNewState, enmOldState) \
328	ASMAtomicCmpXchgU32((uint32_t volatile *)&(pVCpu)->enmState, (enmNewState), (enmOldState))
329	/** Checks the VMCPU state. */
330	#ifdef VBOX_STRICT
331	# define VMCPU_ASSERT_STATE(pVCpu, enmExpectedState) \
332	do { \
333	VMCPUSTATE enmState = VMCPU_GET_STATE(pVCpu); \
334	AssertMsg(enmState == (enmExpectedState), \
335	("enmState=%d enmExpectedState=%d idCpu=%u\n", \
336	enmState, enmExpectedState, (pVCpu)->idCpu)); \
337	} while (0)
338	#else
339	# define VMCPU_ASSERT_STATE(pVCpu, enmExpectedState) do { } while (0)
340	#endif
341	/** Tests if the state means that the CPU is started. */
342	#define VMCPUSTATE_IS_STARTED(enmState) ( (enmState) > VMCPUSTATE_STOPPED )
343	/** Tests if the state means that the CPU is stopped. */
344	#define VMCPUSTATE_IS_STOPPED(enmState) ( (enmState) == VMCPUSTATE_STOPPED )
345	/** @} */
346
347
348	/** The name of the raw-mode context VMM Core module. */
349	#define VMMRC_MAIN_MODULE_NAME "VMMRC.rc"
350	/** The name of the ring-0 context VMM Core module. */
351	#define VMMR0_MAIN_MODULE_NAME "VMMR0.r0"
352
353	/**
354	* Wrapper macro for avoiding too much \#ifdef VBOX_WITH_RAW_MODE.
355	*/
356	#ifdef VBOX_WITH_RAW_MODE
357	# define VM_WHEN_RAW_MODE(a_WithExpr, a_WithoutExpr) a_WithExpr
358	#else
359	# define VM_WHEN_RAW_MODE(a_WithExpr, a_WithoutExpr) a_WithoutExpr
360	#endif
361
362
363	/** VM Forced Action Flags.
364	*
365	* Use the VM_FF_SET() and VM_FF_CLEAR() macros to change the force
366	* action mask of a VM.
367	*
368	* Available VM bits:
369	* 0, 1, 5, 6, 7, 13, 14, 15, 16, 17, 21, 22, 23, 24, 25, 26, 27, 28, 30
370	*
371	*
372	* Available VMCPU bits:
373	* 14, 15, 36 to 63
374	*
375	* @todo If we run low on VMCPU, we may consider merging the SELM bits
376	*
377	* @{
378	*/
379	/** The virtual sync clock has been stopped, go to TM until it has been
380	* restarted... */
381	#define VM_FF_TM_VIRTUAL_SYNC RT_BIT_32(VM_FF_TM_VIRTUAL_SYNC_BIT)
382	#define VM_FF_TM_VIRTUAL_SYNC_BIT 2
383	/** PDM Queues are pending. */
384	#define VM_FF_PDM_QUEUES RT_BIT_32(VM_FF_PDM_QUEUES_BIT)
385	/** The bit number for VM_FF_PDM_QUEUES. */
386	#define VM_FF_PDM_QUEUES_BIT 3
387	/** PDM DMA transfers are pending. */
388	#define VM_FF_PDM_DMA RT_BIT_32(VM_FF_PDM_DMA_BIT)
389	/** The bit number for VM_FF_PDM_DMA. */
390	#define VM_FF_PDM_DMA_BIT 4
391	/** This action forces the VM to call DBGF so DBGF can service debugger
392	* requests in the emulation thread.
393	* This action flag stays asserted till DBGF clears it.*/
394	#define VM_FF_DBGF RT_BIT_32(VM_FF_DBGF_BIT)
395	/** The bit number for VM_FF_DBGF. */
396	#define VM_FF_DBGF_BIT 8
397	/** This action forces the VM to service pending requests from other
398	* thread or requests which must be executed in another context. */
399	#define VM_FF_REQUEST RT_BIT_32(VM_FF_REQUEST_BIT)
400	#define VM_FF_REQUEST_BIT 9
401	/** Check for VM state changes and take appropriate action. */
402	#define VM_FF_CHECK_VM_STATE RT_BIT_32(VM_FF_CHECK_VM_STATE_BIT)
403	/** The bit number for VM_FF_CHECK_VM_STATE. */
404	#define VM_FF_CHECK_VM_STATE_BIT 10
405	/** Reset the VM. (postponed) */
406	#define VM_FF_RESET RT_BIT_32(VM_FF_RESET_BIT)
407	/** The bit number for VM_FF_RESET. */
408	#define VM_FF_RESET_BIT 11
409	/** EMT rendezvous in VMM. */
410	#define VM_FF_EMT_RENDEZVOUS RT_BIT_32(VM_FF_EMT_RENDEZVOUS_BIT)
411	/** The bit number for VM_FF_EMT_RENDEZVOUS. */
412	#define VM_FF_EMT_RENDEZVOUS_BIT 12
413
414	/** PGM needs to allocate handy pages. */
415	#define VM_FF_PGM_NEED_HANDY_PAGES RT_BIT_32(VM_FF_PGM_NEED_HANDY_PAGES_BIT)
416	#define VM_FF_PGM_NEED_HANDY_PAGES_BIT 18
417	/** PGM is out of memory.
418	* Abandon all loops and code paths which can be resumed and get up to the EM
419	* loops. */
420	#define VM_FF_PGM_NO_MEMORY RT_BIT_32(VM_FF_PGM_NO_MEMORY_BIT)
421	#define VM_FF_PGM_NO_MEMORY_BIT 19
422	/** PGM is about to perform a lightweight pool flush
423	* Guest SMP: all EMT threads should return to ring 3
424	*/
425	#define VM_FF_PGM_POOL_FLUSH_PENDING RT_BIT_32(VM_FF_PGM_POOL_FLUSH_PENDING_BIT)
426	#define VM_FF_PGM_POOL_FLUSH_PENDING_BIT 20
427	/** REM needs to be informed about handler changes. */
428	#define VM_FF_REM_HANDLER_NOTIFY RT_BIT_32(VM_FF_REM_HANDLER_NOTIFY_BIT)
429	/** The bit number for VM_FF_REM_HANDLER_NOTIFY. */
430	#define VM_FF_REM_HANDLER_NOTIFY_BIT 29
431	/** Suspend the VM - debug only. */
432	#define VM_FF_DEBUG_SUSPEND RT_BIT_32(VM_FF_DEBUG_SUSPEND_BIT)
433	#define VM_FF_DEBUG_SUSPEND_BIT 31
434
435
436	/** This action forces the VM to check any pending interrupts on the APIC. */
437	#define VMCPU_FF_INTERRUPT_APIC RT_BIT_64(VMCPU_FF_INTERRUPT_APIC_BIT)
438	#define VMCPU_FF_INTERRUPT_APIC_BIT 0
439	/** This action forces the VM to check any pending interrups on the PIC. */
440	#define VMCPU_FF_INTERRUPT_PIC RT_BIT_64(VMCPU_FF_INTERRUPT_PIC_BIT)
441	#define VMCPU_FF_INTERRUPT_PIC_BIT 1
442	/** This action forces the VM to schedule and run pending timer (TM).
443	* @remarks Don't move - PATM compatibility. */
444	#define VMCPU_FF_TIMER RT_BIT_64(VMCPU_FF_TIMER_BIT)
445	#define VMCPU_FF_TIMER_BIT 2
446	/** This action forces the VM to check any pending NMIs. */
447	#define VMCPU_FF_INTERRUPT_NMI RT_BIT_64(VMCPU_FF_INTERRUPT_NMI_BIT)
448	#define VMCPU_FF_INTERRUPT_NMI_BIT 3
449	/** This action forces the VM to check any pending SMIs. */
450	#define VMCPU_FF_INTERRUPT_SMI RT_BIT_64(VMCPU_FF_INTERRUPT_SMI_BIT)
451	#define VMCPU_FF_INTERRUPT_SMI_BIT 4
452	/** PDM critical section unlocking is pending, process promptly upon return to R3. */
453	#define VMCPU_FF_PDM_CRITSECT RT_BIT_64(VMCPU_FF_PDM_CRITSECT_BIT)
454	#define VMCPU_FF_PDM_CRITSECT_BIT 5
455	/** Special EM internal force flag that is used by EMUnhaltAndWakeUp() to force
456	* the virtual CPU out of the next (/current) halted state. It is not processed
457	* nor cleared by emR3ForcedActions (similar to VMCPU_FF_BLOCK_NMIS), instead it
458	* is cleared the next time EM leaves the HALTED state. */
459	#define VMCPU_FF_UNHALT RT_BIT_64(VMCPU_FF_UNHALT_BIT)
460	#define VMCPU_FF_UNHALT_BIT 6
461	/** Pending IEM action (mask). */
462	#define VMCPU_FF_IEM RT_BIT_64(VMCPU_FF_IEM_BIT)
463	/** Pending IEM action (bit number). */
464	#define VMCPU_FF_IEM_BIT 7
465	/** Pending APIC action (bit number). */
466	#define VMCPU_FF_UPDATE_APIC_BIT 8
467	/** This action forces the VM to update APIC's asynchronously arrived
468	* interrupts as pending interrupts. */
469	#define VMCPU_FF_UPDATE_APIC RT_BIT_64(VMCPU_FF_UPDATE_APIC_BIT)
470	/** This action forces the VM to service pending requests from other
471	* thread or requests which must be executed in another context. */
472	#define VMCPU_FF_REQUEST RT_BIT_64(VMCPU_FF_REQUEST_BIT)
473	#define VMCPU_FF_REQUEST_BIT 9
474	/** Pending DBGF event (alternative to passing VINF_EM_DBG_EVENT around). */
475	#define VMCPU_FF_DBGF RT_BIT_64(VMCPU_FF_DBGF_BIT)
476	/** The bit number for VMCPU_FF_DBGF. */
477	#define VMCPU_FF_DBGF_BIT 10
478	/** This action forces the VM to service any pending updates to CR3 (used only
479	* by HM). */
480	/** Hardware virtualized nested-guest interrupt pending. */
481	#define VMCPU_FF_INTERRUPT_NESTED_GUEST RT_BIT_64(VMCPU_FF_INTERRUPT_NESTED_GUEST_BIT)
482	#define VMCPU_FF_INTERRUPT_NESTED_GUEST_BIT 11
483	#define VMCPU_FF_HM_UPDATE_CR3 RT_BIT_64(VMCPU_FF_HM_UPDATE_CR3_BIT)
484	#define VMCPU_FF_HM_UPDATE_CR3_BIT 12
485	/** This action forces the VM to service any pending updates to PAE PDPEs (used
486	* only by HM). */
487	#define VMCPU_FF_HM_UPDATE_PAE_PDPES RT_BIT_64(VMCPU_FF_HM_UPDATE_PAE_PDPES_BIT)
488	#define VMCPU_FF_HM_UPDATE_PAE_PDPES_BIT 13
489	/** This action forces the VM to resync the page tables before going
490	* back to execute guest code. (GLOBAL FLUSH) */
491	#define VMCPU_FF_PGM_SYNC_CR3 RT_BIT_64(VMCPU_FF_PGM_SYNC_CR3_BIT)
492	#define VMCPU_FF_PGM_SYNC_CR3_BIT 16
493	/** Same as VM_FF_PGM_SYNC_CR3 except that global pages can be skipped.
494	* (NON-GLOBAL FLUSH) */
495	#define VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL RT_BIT_64(VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL_BIT)
496	#define VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL_BIT 17
497	/** Check for pending TLB shootdown actions (deprecated)
498	* Reserved for furture HM re-use if necessary / safe.
499	* Consumer: HM */
500	#define VMCPU_FF_TLB_SHOOTDOWN_UNUSED RT_BIT_64(VMCPU_FF_TLB_SHOOTDOWN_UNUSED_BIT)
501	#define VMCPU_FF_TLB_SHOOTDOWN_UNUSED_BIT 18
502	/** Check for pending TLB flush action.
503	* Consumer: HM
504	* @todo rename to VMCPU_FF_HM_TLB_FLUSH */
505	#define VMCPU_FF_TLB_FLUSH RT_BIT_64(VMCPU_FF_TLB_FLUSH_BIT)
506	/** The bit number for VMCPU_FF_TLB_FLUSH. */
507	#define VMCPU_FF_TLB_FLUSH_BIT 19
508	#ifdef VBOX_WITH_RAW_MODE
509	/** Check the interrupt and trap gates */
510	# define VMCPU_FF_TRPM_SYNC_IDT RT_BIT_64(VMCPU_FF_TRPM_SYNC_IDT_BIT)
511	# define VMCPU_FF_TRPM_SYNC_IDT_BIT 20
512	/** Check Guest's TSS ring 0 stack */
513	# define VMCPU_FF_SELM_SYNC_TSS RT_BIT_64(VMCPU_FF_SELM_SYNC_TSS_BIT)
514	# define VMCPU_FF_SELM_SYNC_TSS_BIT 21
515	/** Check Guest's GDT table */
516	# define VMCPU_FF_SELM_SYNC_GDT RT_BIT_64(VMCPU_FF_SELM_SYNC_GDT_BIT)
517	# define VMCPU_FF_SELM_SYNC_GDT_BIT 22
518	/** Check Guest's LDT table */
519	# define VMCPU_FF_SELM_SYNC_LDT RT_BIT_64(VMCPU_FF_SELM_SYNC_LDT_BIT)
520	# define VMCPU_FF_SELM_SYNC_LDT_BIT 23
521	#endif /* VBOX_WITH_RAW_MODE */
522	/** Inhibit interrupts pending. See EMGetInhibitInterruptsPC(). */
523	#define VMCPU_FF_INHIBIT_INTERRUPTS RT_BIT_64(VMCPU_FF_INHIBIT_INTERRUPTS_BIT)
524	#define VMCPU_FF_INHIBIT_INTERRUPTS_BIT 24
525	/** Block injection of non-maskable interrupts to the guest. */
526	#define VMCPU_FF_BLOCK_NMIS RT_BIT_64(VMCPU_FF_BLOCK_NMIS_BIT)
527	#define VMCPU_FF_BLOCK_NMIS_BIT 25
528	#ifdef VBOX_WITH_RAW_MODE
529	/** CSAM needs to scan the page that's being executed */
530	# define VMCPU_FF_CSAM_SCAN_PAGE RT_BIT_64(VMCPU_FF_CSAM_SCAN_PAGE_BIT)
531	# define VMCPU_FF_CSAM_SCAN_PAGE_BIT 26
532	/** CSAM needs to do some homework. */
533	# define VMCPU_FF_CSAM_PENDING_ACTION RT_BIT_64(VMCPU_FF_CSAM_PENDING_ACTION_BIT)
534	# define VMCPU_FF_CSAM_PENDING_ACTION_BIT 27
535	#endif /* VBOX_WITH_RAW_MODE */
536	/** Force return to Ring-3. */
537	#define VMCPU_FF_TO_R3 RT_BIT_64(VMCPU_FF_TO_R3_BIT)
538	#define VMCPU_FF_TO_R3_BIT 28
539	/** Force return to ring-3 to service pending I/O or MMIO write.
540	* This is a backup for mechanism VINF_IOM_R3_IOPORT_COMMIT_WRITE and
541	* VINF_IOM_R3_MMIO_COMMIT_WRITE, allowing VINF_EM_DBG_BREAKPOINT and similar
542	* status codes to be propagated at the same time without loss. */
543	#define VMCPU_FF_IOM RT_BIT_64(VMCPU_FF_IOM_BIT)
544	#define VMCPU_FF_IOM_BIT 29
545	#ifdef VBOX_WITH_RAW_MODE
546	/** CPUM need to adjust CR0.TS/EM before executing raw-mode code again. */
547	# define VMCPU_FF_CPUM RT_BIT_64(VMCPU_FF_CPUM_BIT)
548	/** The bit number for VMCPU_FF_CPUM. */
549	# define VMCPU_FF_CPUM_BIT 30
550	#endif /* VBOX_WITH_RAW_MODE */
551	/** VMX-preemption timer in effect. */
552	#define VMCPU_FF_VMX_PREEMPT_TIMER RT_BIT_64(VMCPU_FF_VMX_PREEMPT_TIMER_BIT)
553	#define VMCPU_FF_VMX_PREEMPT_TIMER_BIT 31
554	/** Pending MTF (Monitor Trap Flag) event. */
555	#define VMCPU_FF_VMX_MTF RT_BIT_64(VMCPU_FF_VMX_MTF_BIT)
556	#define VMCPU_FF_VMX_MTF_BIT 32
557	/** VMX APIC-write emulation pending. */
558	#define VMCPU_FF_VMX_APIC_WRITE RT_BIT_64(VMCPU_FF_VMX_APIC_WRITE_BIT)
559	#define VMCPU_FF_VMX_APIC_WRITE_BIT 33
560	/** VMX interrupt-window event pending. */
561	#define VMCPU_FF_VMX_INT_WINDOW RT_BIT_64(VMCPU_FF_VMX_INT_WINDOW_BIT)
562	#define VMCPU_FF_VMX_INT_WINDOW_BIT 34
563	/** VMX NMI-window event pending. */
564	#define VMCPU_FF_VMX_NMI_WINDOW RT_BIT_64(VMCPU_FF_VMX_NMI_WINDOW_BIT)
565	#define VMCPU_FF_VMX_NMI_WINDOW_BIT 35
566
567
568	/** Externally VM forced actions. Used to quit the idle/wait loop. */
569	#define VM_FF_EXTERNAL_SUSPENDED_MASK ( VM_FF_CHECK_VM_STATE \| VM_FF_DBGF \| VM_FF_REQUEST \| VM_FF_EMT_RENDEZVOUS )
570	/** Externally VMCPU forced actions. Used to quit the idle/wait loop. */
571	#define VMCPU_FF_EXTERNAL_SUSPENDED_MASK ( VMCPU_FF_REQUEST \| VMCPU_FF_DBGF )
572
573	/** Externally forced VM actions. Used to quit the idle/wait loop. */
574	#define VM_FF_EXTERNAL_HALTED_MASK ( VM_FF_CHECK_VM_STATE \| VM_FF_DBGF \| VM_FF_REQUEST \
575	\| VM_FF_PDM_QUEUES \| VM_FF_PDM_DMA \| VM_FF_EMT_RENDEZVOUS )
576	/** Externally forced VMCPU actions. Used to quit the idle/wait loop. */
577	#define VMCPU_FF_EXTERNAL_HALTED_MASK ( VMCPU_FF_UPDATE_APIC \| VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC \
578	\| VMCPU_FF_REQUEST \| VMCPU_FF_INTERRUPT_NMI \| VMCPU_FF_INTERRUPT_SMI \
579	\| VMCPU_FF_UNHALT \| VMCPU_FF_TIMER \| VMCPU_FF_DBGF \
580	\| VMCPU_FF_INTERRUPT_NESTED_GUEST)
581
582	/** High priority VM pre-execution actions. */
583	#define VM_FF_HIGH_PRIORITY_PRE_MASK ( VM_FF_CHECK_VM_STATE \| VM_FF_DBGF \| VM_FF_TM_VIRTUAL_SYNC \
584	\| VM_FF_DEBUG_SUSPEND \| VM_FF_PGM_NEED_HANDY_PAGES \| VM_FF_PGM_NO_MEMORY \
585	\| VM_FF_EMT_RENDEZVOUS )
586	/** High priority VMCPU pre-execution actions. */
587	#define VMCPU_FF_HIGH_PRIORITY_PRE_MASK ( VMCPU_FF_TIMER \| VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC \
588	\| VMCPU_FF_UPDATE_APIC \| VMCPU_FF_INHIBIT_INTERRUPTS \| VMCPU_FF_DBGF \
589	\| VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL \
590	\| VMCPU_FF_INTERRUPT_NESTED_GUEST \| VMCPU_FF_VMX_MTF \| VMCPU_FF_VMX_APIC_WRITE \
591	\| VMCPU_FF_VMX_PREEMPT_TIMER \| VMCPU_FF_VMX_NMI_WINDOW \| VMCPU_FF_VMX_INT_WINDOW \
592	\| VM_WHEN_RAW_MODE( VMCPU_FF_SELM_SYNC_TSS \| VMCPU_FF_TRPM_SYNC_IDT \
593	\| VMCPU_FF_SELM_SYNC_GDT \| VMCPU_FF_SELM_SYNC_LDT, 0 ) )
594
595	/** High priority VM pre raw-mode execution mask. */
596	#define VM_FF_HIGH_PRIORITY_PRE_RAW_MASK ( VM_FF_PGM_NEED_HANDY_PAGES \| VM_FF_PGM_NO_MEMORY )
597	/** High priority VMCPU pre raw-mode execution mask. */
598	#define VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK ( VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL \
599	\| VMCPU_FF_INHIBIT_INTERRUPTS \
600	\| VM_WHEN_RAW_MODE( VMCPU_FF_SELM_SYNC_TSS \| VMCPU_FF_TRPM_SYNC_IDT \
601	\| VMCPU_FF_SELM_SYNC_GDT \| VMCPU_FF_SELM_SYNC_LDT, 0) )
602
603	/** High priority post-execution actions. */
604	#define VM_FF_HIGH_PRIORITY_POST_MASK ( VM_FF_PGM_NO_MEMORY )
605	/** High priority post-execution actions. */
606	#define VMCPU_FF_HIGH_PRIORITY_POST_MASK ( VMCPU_FF_PDM_CRITSECT \| VM_WHEN_RAW_MODE(VMCPU_FF_CSAM_PENDING_ACTION, 0) \
607	\| VMCPU_FF_HM_UPDATE_CR3 \| VMCPU_FF_HM_UPDATE_PAE_PDPES \
608	\| VMCPU_FF_IEM \| VMCPU_FF_IOM )
609
610	/** Normal priority VM post-execution actions. */
611	#define VM_FF_NORMAL_PRIORITY_POST_MASK ( VM_FF_CHECK_VM_STATE \| VM_FF_DBGF \| VM_FF_RESET \
612	\| VM_FF_PGM_NO_MEMORY \| VM_FF_EMT_RENDEZVOUS)
613	/** Normal priority VMCPU post-execution actions. */
614	#define VMCPU_FF_NORMAL_PRIORITY_POST_MASK ( VM_WHEN_RAW_MODE(VMCPU_FF_CSAM_SCAN_PAGE, 0) \| VMCPU_FF_DBGF )
615
616	/** Normal priority VM actions. */
617	#define VM_FF_NORMAL_PRIORITY_MASK ( VM_FF_REQUEST \| VM_FF_PDM_QUEUES \| VM_FF_PDM_DMA \
618	\| VM_FF_REM_HANDLER_NOTIFY \| VM_FF_EMT_RENDEZVOUS)
619	/** Normal priority VMCPU actions. */
620	#define VMCPU_FF_NORMAL_PRIORITY_MASK ( VMCPU_FF_REQUEST )
621
622	/** Flags to clear before resuming guest execution. */
623	#define VMCPU_FF_RESUME_GUEST_MASK ( VMCPU_FF_TO_R3 )
624
625
626	/** VM flags that cause the REP[\|NE\|E] STRINS loops to yield immediately. */
627	#define VM_FF_HIGH_PRIORITY_POST_REPSTR_MASK ( VM_FF_TM_VIRTUAL_SYNC \| VM_FF_PGM_NEED_HANDY_PAGES \| VM_FF_PGM_NO_MEMORY \
628	\| VM_FF_EMT_RENDEZVOUS \| VM_FF_PGM_POOL_FLUSH_PENDING \| VM_FF_RESET)
629	/** VM flags that cause the REP[\|NE\|E] STRINS loops to yield. */
630	#define VM_FF_YIELD_REPSTR_MASK ( VM_FF_HIGH_PRIORITY_POST_REPSTR_MASK \
631	\| VM_FF_PDM_QUEUES \| VM_FF_PDM_DMA \| VM_FF_DBGF \| VM_FF_DEBUG_SUSPEND )
632	/** VMCPU flags that cause the REP[\|NE\|E] STRINS loops to yield immediately. */
633	#ifdef IN_RING3
634	# define VMCPU_FF_HIGH_PRIORITY_POST_REPSTR_MASK ( VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL \| VMCPU_FF_DBGF \
635	\| VMCPU_FF_VMX_MTF )
636	#else
637	# define VMCPU_FF_HIGH_PRIORITY_POST_REPSTR_MASK ( VMCPU_FF_TO_R3 \| VMCPU_FF_IEM \| VMCPU_FF_IOM \| VMCPU_FF_PGM_SYNC_CR3 \
638	\| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL \| VMCPU_FF_DBGF \| VMCPU_FF_VMX_MTF )
639	#endif
640	/** VMCPU flags that cause the REP[\|NE\|E] STRINS loops to yield, interrupts
641	* enabled. */
642	#define VMCPU_FF_YIELD_REPSTR_MASK ( VMCPU_FF_HIGH_PRIORITY_POST_REPSTR_MASK \
643	\| VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_UPDATE_APIC \| VMCPU_FF_INTERRUPT_PIC \
644	\| VMCPU_FF_INTERRUPT_NMI \| VMCPU_FF_INTERRUPT_SMI \| VMCPU_FF_PDM_CRITSECT \
645	\| VMCPU_FF_TIMER \| VMCPU_FF_REQUEST \
646	\| VMCPU_FF_INTERRUPT_NESTED_GUEST )
647	/** VMCPU flags that cause the REP[\|NE\|E] STRINS loops to yield, interrupts
648	* disabled. */
649	#define VMCPU_FF_YIELD_REPSTR_NOINT_MASK ( VMCPU_FF_YIELD_REPSTR_MASK \
650	& ~( VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_UPDATE_APIC \| VMCPU_FF_INTERRUPT_PIC \
651	\| VMCPU_FF_INTERRUPT_NESTED_GUEST) )
652
653	/** VM Flags that cause the HM loops to go back to ring-3. */
654	#define VM_FF_HM_TO_R3_MASK ( VM_FF_TM_VIRTUAL_SYNC \| VM_FF_PGM_NEED_HANDY_PAGES \| VM_FF_PGM_NO_MEMORY \
655	\| VM_FF_PDM_QUEUES \| VM_FF_EMT_RENDEZVOUS)
656	/** VMCPU Flags that cause the HM loops to go back to ring-3. */
657	#define VMCPU_FF_HM_TO_R3_MASK ( VMCPU_FF_TO_R3 \| VMCPU_FF_TIMER \| VMCPU_FF_PDM_CRITSECT \
658	\| VMCPU_FF_IEM \| VMCPU_FF_IOM)
659
660	/** High priority ring-0 VM pre HM-mode execution mask. */
661	#define VM_FF_HP_R0_PRE_HM_MASK (VM_FF_HM_TO_R3_MASK \| VM_FF_REQUEST \| VM_FF_PGM_POOL_FLUSH_PENDING \| VM_FF_PDM_DMA)
662	/** High priority ring-0 VMCPU pre HM-mode execution mask. */
663	#define VMCPU_FF_HP_R0_PRE_HM_MASK ( VMCPU_FF_HM_TO_R3_MASK \| VMCPU_FF_PGM_SYNC_CR3 \
664	\| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL \| VMCPU_FF_REQUEST)
665	/** High priority ring-0 VM pre HM-mode execution mask, single stepping. */
666	#define VM_FF_HP_R0_PRE_HM_STEP_MASK (VM_FF_HP_R0_PRE_HM_MASK & ~( VM_FF_TM_VIRTUAL_SYNC \| VM_FF_PDM_QUEUES \
667	\| VM_FF_EMT_RENDEZVOUS \| VM_FF_REQUEST \
668	\| VM_FF_PDM_DMA) )
669	/** High priority ring-0 VMCPU pre HM-mode execution mask, single stepping. */
670	#define VMCPU_FF_HP_R0_PRE_HM_STEP_MASK (VMCPU_FF_HP_R0_PRE_HM_MASK & ~( VMCPU_FF_TO_R3 \| VMCPU_FF_TIMER \
671	\| VMCPU_FF_PDM_CRITSECT \| VMCPU_FF_REQUEST) )
672
673	/** All the forced VM flags. */
674	#define VM_FF_ALL_MASK (UINT32_MAX)
675	/** All the forced VMCPU flags. */
676	#define VMCPU_FF_ALL_MASK (UINT32_MAX)
677
678	/** All the forced VM flags except those related to raw-mode and hardware
679	* assisted execution. */
680	#define VM_FF_ALL_REM_MASK (~(VM_FF_HIGH_PRIORITY_PRE_RAW_MASK) \| VM_FF_PGM_NEED_HANDY_PAGES \| VM_FF_PGM_NO_MEMORY)
681	/** All the forced VMCPU flags except those related to raw-mode and hardware
682	* assisted execution. */
683	#define VMCPU_FF_ALL_REM_MASK (~( VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK \| VMCPU_FF_PDM_CRITSECT \
684	\| VMCPU_FF_TLB_FLUSH \| VM_WHEN_RAW_MODE(VMCPU_FF_CSAM_PENDING_ACTION, 0) ))
685	/** @} */
686
687	/** @def VM_FF_SET
688	* Sets a single force action flag.
689	*
690	* @param pVM The cross context VM structure.
691	* @param fFlag The flag to set.
692	*/
693	#define VM_FF_SET(pVM, fFlag) do { \
694	AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
695	AssertCompile((fFlag) == RT_BIT_32(fFlag##_BIT)); \
696	ASMAtomicOrU32(&(pVM)->fGlobalForcedActions, (fFlag)); \
697	} while (0)
698
699	/** @def VMCPU_FF_SET
700	* Sets a single force action flag for the given VCPU.
701	*
702	* @param pVCpu The cross context virtual CPU structure.
703	* @param fFlag The flag to set.
704	* @sa VMCPU_FF_SET_MASK
705	*/
706	#ifdef VMCPU_WITH_64_BIT_FFS
707	# define VMCPU_FF_SET(pVCpu, fFlag) do { \
708	AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
709	AssertCompile((fFlag) == RT_BIT_64(fFlag##_BIT)); \
710	ASMAtomicBitSet(&(pVCpu)->fLocalForcedActions, fFlag##_BIT); \
711	} while (0)
712	#else
713	# define VMCPU_FF_SET(pVCpu, fFlag) do { \
714	AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
715	AssertCompile((fFlag) == RT_BIT_32(fFlag##_BIT)); \
716	ASMAtomicOrU32(&(pVCpu)->fLocalForcedActions, (fFlag)); \
717	} while (0)
718	#endif
719
720	/** @def VMCPU_FF_SET_MASK
721	* Sets a two or more force action flag for the given VCPU.
722	*
723	* @param pVCpu The cross context virtual CPU structure.
724	* @param fFlags The flags to set.
725	* @sa VMCPU_FF_SET
726	*/
727	#ifdef VMCPU_WITH_64_BIT_FFS
728	# if ARCH_BITS > 32
729	# define VMCPU_FF_SET_MASK(pVCpu, fFlags) \
730	do { ASMAtomicOrU64(&pVCpu->fLocalForcedActions, (fFlags)); } while (0)
731	# else
732	# define VMCPU_FF_SET_MASK(pVCpu, fFlags) do { \
733	if (!((fFlags) >> 32)) ASMAtomicOrU32((uint32_t volatile *)&pVCpu->fLocalForcedActions, (uint32_t)(fFlags)); \
734	else ASMAtomicOrU64(&pVCpu->fLocalForcedActions, (fFlags)); \
735	} while (0)
736	# endif
737	#else
738	# define VMCPU_FF_SET_MASK(pVCpu, fFlags) \
739	do { ASMAtomicOrU32(&pVCpu->fLocalForcedActions, (fFlags)); } while (0)
740	#endif
741
742	/** @def VM_FF_CLEAR
743	* Clears a single force action flag.
744	*
745	* @param pVM The cross context VM structure.
746	* @param fFlag The flag to clear.
747	*/
748	#define VM_FF_CLEAR(pVM, fFlag) do { \
749	AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
750	AssertCompile((fFlag) == RT_BIT_32(fFlag##_BIT)); \
751	ASMAtomicAndU32(&(pVM)->fGlobalForcedActions, ~(fFlag)); \
752	} while (0)
753
754	/** @def VMCPU_FF_CLEAR
755	* Clears a single force action flag for the given VCPU.
756	*
757	* @param pVCpu The cross context virtual CPU structure.
758	* @param fFlag The flag to clear.
759	*/
760	#ifdef VMCPU_WITH_64_BIT_FFS
761	# define VMCPU_FF_CLEAR(pVCpu, fFlag) do { \
762	AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
763	AssertCompile((fFlag) == RT_BIT_64(fFlag##_BIT)); \
764	ASMAtomicBitClear(&(pVCpu)->fLocalForcedActions, fFlag##_BIT); \
765	} while (0)
766	#else
767	# define VMCPU_FF_CLEAR(pVCpu, fFlag) do { \
768	AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
769	AssertCompile((fFlag) == RT_BIT_32(fFlag##_BIT)); \
770	ASMAtomicAndU32(&(pVCpu)->fLocalForcedActions, ~(fFlag)); \
771	} while (0)
772	#endif
773
774	/** @def VMCPU_FF_CLEAR_MASK
775	* Clears two or more force action flags for the given VCPU.
776	*
777	* @param pVCpu The cross context virtual CPU structure.
778	* @param fFlags The flags to clear.
779	*/
780	#ifdef VMCPU_WITH_64_BIT_FFS
781	# if ARCH_BITS > 32
782	# define VMCPU_FF_CLEAR_MASK(pVCpu, fFlags) \
783	do { ASMAtomicAndU64(&(pVCpu)->fLocalForcedActions, ~(fFlags)); } while (0)
784	# else
785	# define VMCPU_FF_CLEAR_MASK(pVCpu, fFlags) do { \
786	if (!((fFlags) >> 32)) ASMAtomicAndU32((uint32_t volatile *)&(pVCpu)->fLocalForcedActions, ~(uint32_t)(fFlags)); \
787	else ASMAtomicAndU64(&(pVCpu)->fLocalForcedActions, ~(fFlags)); \
788	} while (0)
789	# endif
790	#else
791	# define VMCPU_FF_CLEAR_MASK(pVCpu, fFlags) \
792	do { ASMAtomicAndU32(&(pVCpu)->fLocalForcedActions, ~(fFlags)); } while (0)
793	#endif
794
795	/** @def VM_FF_IS_SET
796	* Checks if single a force action flag is set.
797	*
798	* @param pVM The cross context VM structure.
799	* @param fFlag The flag to check.
800	* @sa VM_FF_IS_ANY_SET
801	*/
802	#if !defined(VBOX_STRICT) \|\| !defined(RT_COMPILER_SUPPORTS_LAMBDA)
803	# define VM_FF_IS_SET(pVM, fFlag) RT_BOOL((pVM)->fGlobalForcedActions & (fFlag))
804	#else
805	# define VM_FF_IS_SET(pVM, fFlag) \
806	([](PVM a_pVM) -> bool \
807	{ \
808	AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
809	AssertCompile((fFlag) == RT_BIT_32(fFlag##_BIT)); \
810	return RT_BOOL(a_pVM->fGlobalForcedActions & (fFlag)); \
811	}(pVM))
812	#endif
813
814	/** @def VMCPU_FF_IS_SET
815	* Checks if a single force action flag is set for the given VCPU.
816	*
817	* @param pVCpu The cross context virtual CPU structure.
818	* @param fFlag The flag to check.
819	* @sa VMCPU_FF_IS_ANY_SET
820	*/
821	#if !defined(VBOX_STRICT) \|\| !defined(RT_COMPILER_SUPPORTS_LAMBDA)
822	# define VMCPU_FF_IS_SET(pVCpu, fFlag) RT_BOOL((pVCpu)->fLocalForcedActions & (fFlag))
823	#else
824	# define VMCPU_FF_IS_SET(pVCpu, fFlag) \
825	([](PVMCPU a_pVCpu) -> bool \
826	{ \
827	AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
828	AssertCompile((fFlag) == RT_BIT_64(fFlag##_BIT)); \
829	return RT_BOOL(a_pVCpu->fLocalForcedActions & (fFlag)); \
830	}(pVCpu))
831	#endif
832
833	/** @def VM_FF_IS_ANY_SET
834	* Checks if one or more force action in the specified set is pending.
835	*
836	* @param pVM The cross context VM structure.
837	* @param fFlags The flags to check for.
838	* @sa VM_FF_IS_SET
839	*/
840	#define VM_FF_IS_ANY_SET(pVM, fFlags) RT_BOOL((pVM)->fGlobalForcedActions & (fFlags))
841
842	/** @def VMCPU_FF_IS_ANY_SET
843	* Checks if two or more force action flags in the specified set is set for the given VCPU.
844	*
845	* @param pVCpu The cross context virtual CPU structure.
846	* @param fFlags The flags to check for.
847	* @sa VMCPU_FF_IS_SET
848	*/
849	#define VMCPU_FF_IS_ANY_SET(pVCpu, fFlags) RT_BOOL((pVCpu)->fLocalForcedActions & (fFlags))
850
851	/** @def VM_FF_TEST_AND_CLEAR
852	* Checks if one (!) force action in the specified set is pending and clears it atomically
853	*
854	* @returns true if the bit was set.
855	* @returns false if the bit was clear.
856	* @param pVM The cross context VM structure.
857	* @param fFlag Flag constant to check and clear (_BIT is appended).
858	*/
859	#define VM_FF_TEST_AND_CLEAR(pVM, fFlag) (ASMAtomicBitTestAndClear(&(pVM)->fGlobalForcedActions, fFlag##_BIT))
860
861	/** @def VMCPU_FF_TEST_AND_CLEAR
862	* Checks if one (!) force action in the specified set is pending and clears it atomically
863	*
864	* @returns true if the bit was set.
865	* @returns false if the bit was clear.
866	* @param pVCpu The cross context virtual CPU structure.
867	* @param fFlag Flag constant to check and clear (_BIT is appended).
868	*/
869	#define VMCPU_FF_TEST_AND_CLEAR(pVCpu, fFlag) (ASMAtomicBitTestAndClear(&(pVCpu)->fLocalForcedActions, fFlag##_BIT))
870
871	/** @def VM_FF_IS_PENDING_EXCEPT
872	* Checks if one or more force action in the specified set is pending while one
873	* or more other ones are not.
874	*
875	* @param pVM The cross context VM structure.
876	* @param fFlags The flags to check for.
877	* @param fExcpt The flags that should not be set.
878	*/
879	#define VM_FF_IS_PENDING_EXCEPT(pVM, fFlags, fExcpt) \
880	( ((pVM)->fGlobalForcedActions & (fFlags)) && !((pVM)->fGlobalForcedActions & (fExcpt)) )
881
882	/** @def VM_IS_EMT
883	* Checks if the current thread is the emulation thread (EMT).
884	*
885	* @remark The ring-0 variation will need attention if we expand the ring-0
886	* code to let threads other than EMT mess around with the VM.
887	*/
888	#ifdef IN_RC
889	# define VM_IS_EMT(pVM) true
890	#else
891	# define VM_IS_EMT(pVM) (VMMGetCpu(pVM) != NULL)
892	#endif
893
894	/** @def VMCPU_IS_EMT
895	* Checks if the current thread is the emulation thread (EMT) for the specified
896	* virtual CPU.
897	*/
898	#ifdef IN_RC
899	# define VMCPU_IS_EMT(pVCpu) true
900	#else
901	# define VMCPU_IS_EMT(pVCpu) ((pVCpu) && ((pVCpu) == VMMGetCpu((pVCpu)->CTX_SUFF(pVM))))
902	#endif
903
904	/** @def VM_ASSERT_EMT
905	* Asserts that the current thread IS the emulation thread (EMT).
906	*/
907	#ifdef IN_RC
908	# define VM_ASSERT_EMT(pVM) Assert(VM_IS_EMT(pVM))
909	#elif defined(IN_RING0)
910	# define VM_ASSERT_EMT(pVM) Assert(VM_IS_EMT(pVM))
911	#else
912	# define VM_ASSERT_EMT(pVM) \
913	AssertMsg(VM_IS_EMT(pVM), \
914	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd\n", RTThreadNativeSelf(), VMR3GetVMCPUNativeThread(pVM)))
915	#endif
916
917	/** @def VMCPU_ASSERT_EMT
918	* Asserts that the current thread IS the emulation thread (EMT) of the
919	* specified virtual CPU.
920	*/
921	#ifdef IN_RC
922	# define VMCPU_ASSERT_EMT(pVCpu) Assert(VMCPU_IS_EMT(pVCpu))
923	#elif defined(IN_RING0)
924	# define VMCPU_ASSERT_EMT(pVCpu) AssertMsg(VMCPU_IS_EMT(pVCpu), \
925	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd idCpu=%u\n", \
926	RTThreadNativeSelf(), (pVCpu) ? (pVCpu)->hNativeThreadR0 : 0, \
927	(pVCpu) ? (pVCpu)->idCpu : 0))
928	#else
929	# define VMCPU_ASSERT_EMT(pVCpu) AssertMsg(VMCPU_IS_EMT(pVCpu), \
930	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd idCpu=%#x\n", \
931	RTThreadNativeSelf(), (pVCpu)->hNativeThread, (pVCpu)->idCpu))
932	#endif
933
934	/** @def VM_ASSERT_EMT_RETURN
935	* Asserts that the current thread IS the emulation thread (EMT) and returns if it isn't.
936	*/
937	#ifdef IN_RC
938	# define VM_ASSERT_EMT_RETURN(pVM, rc) AssertReturn(VM_IS_EMT(pVM), (rc))
939	#elif defined(IN_RING0)
940	# define VM_ASSERT_EMT_RETURN(pVM, rc) AssertReturn(VM_IS_EMT(pVM), (rc))
941	#else
942	# define VM_ASSERT_EMT_RETURN(pVM, rc) \
943	AssertMsgReturn(VM_IS_EMT(pVM), \
944	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd\n", RTThreadNativeSelf(), VMR3GetVMCPUNativeThread(pVM)), \
945	(rc))
946	#endif
947
948	/** @def VMCPU_ASSERT_EMT_RETURN
949	* Asserts that the current thread IS the emulation thread (EMT) and returns if it isn't.
950	*/
951	#ifdef IN_RC
952	# define VMCPU_ASSERT_EMT_RETURN(pVCpu, rc) AssertReturn(VMCPU_IS_EMT(pVCpu), (rc))
953	#elif defined(IN_RING0)
954	# define VMCPU_ASSERT_EMT_RETURN(pVCpu, rc) AssertReturn(VMCPU_IS_EMT(pVCpu), (rc))
955	#else
956	# define VMCPU_ASSERT_EMT_RETURN(pVCpu, rc) \
957	AssertMsgReturn(VMCPU_IS_EMT(pVCpu), \
958	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd idCpu=%#x\n", \
959	RTThreadNativeSelf(), (pVCpu)->hNativeThread, (pVCpu)->idCpu), \
960	(rc))
961	#endif
962
963	/** @def VMCPU_ASSERT_EMT_OR_GURU
964	* Asserts that the current thread IS the emulation thread (EMT) of the
965	* specified virtual CPU.
966	*/
967	#if defined(IN_RC) \|\| defined(IN_RING0)
968	# define VMCPU_ASSERT_EMT_OR_GURU(pVCpu) Assert( VMCPU_IS_EMT(pVCpu) \
969	\|\| pVCpu->CTX_SUFF(pVM)->enmVMState == VMSTATE_GURU_MEDITATION \
970	\|\| pVCpu->CTX_SUFF(pVM)->enmVMState == VMSTATE_GURU_MEDITATION_LS )
971	#else
972	# define VMCPU_ASSERT_EMT_OR_GURU(pVCpu) \
973	AssertMsg( VMCPU_IS_EMT(pVCpu) \
974	\|\| pVCpu->CTX_SUFF(pVM)->enmVMState == VMSTATE_GURU_MEDITATION \
975	\|\| pVCpu->CTX_SUFF(pVM)->enmVMState == VMSTATE_GURU_MEDITATION_LS, \
976	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd idCpu=%#x\n", \
977	RTThreadNativeSelf(), (pVCpu)->hNativeThread, (pVCpu)->idCpu))
978	#endif
979
980	/** @def VMCPU_ASSERT_EMT_OR_NOT_RUNNING
981	* Asserts that the current thread IS the emulation thread (EMT) of the
982	* specified virtual CPU or the VM is not running.
983	*/
984	#if defined(IN_RC) \|\| defined(IN_RING0)
985	# define VMCPU_ASSERT_EMT_OR_NOT_RUNNING(pVCpu) \
986	Assert( VMCPU_IS_EMT(pVCpu) \
987	\|\| !VM_IS_RUNNING_FOR_ASSERTIONS_ONLY((pVCpu)->CTX_SUFF(pVM)) )
988	#else
989	# define VMCPU_ASSERT_EMT_OR_NOT_RUNNING(pVCpu) \
990	AssertMsg( VMCPU_IS_EMT(pVCpu) \
991	\|\| !VM_IS_RUNNING_FOR_ASSERTIONS_ONLY((pVCpu)->CTX_SUFF(pVM)), \
992	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd idCpu=%#x\n", \
993	RTThreadNativeSelf(), (pVCpu)->hNativeThread, (pVCpu)->idCpu))
994	#endif
995
996	/** @def VMSTATE_IS_RUNNING
997	* Checks if the given state indicates a running VM.
998	*/
999	#define VMSTATE_IS_RUNNING(a_enmVMState) \
1000	( (enmVMState) == VMSTATE_RUNNING \
1001	\|\| (enmVMState) == VMSTATE_RUNNING_LS \
1002	\|\| (enmVMState) == VMSTATE_RUNNING_FT )
1003
1004	/** @def VM_IS_RUNNING_FOR_ASSERTIONS_ONLY
1005	* Checks if the VM is running.
1006	* @note This is only for pure debug assertions. No AssertReturn or similar!
1007	* @sa VMSTATE_IS_RUNNING
1008	*/
1009	#define VM_IS_RUNNING_FOR_ASSERTIONS_ONLY(pVM) \
1010	( (pVM)->enmVMState == VMSTATE_RUNNING \
1011	\|\| (pVM)->enmVMState == VMSTATE_RUNNING_LS \
1012	\|\| (pVM)->enmVMState == VMSTATE_RUNNING_FT )
1013
1014	/** @def VM_ASSERT_IS_NOT_RUNNING
1015	* Asserts that the VM is not running.
1016	*/
1017	#if defined(IN_RC) \|\| defined(IN_RING0)
1018	#define VM_ASSERT_IS_NOT_RUNNING(pVM) Assert(!VM_IS_RUNNING_FOR_ASSERTIONS_ONLY(pVM))
1019	#else
1020	#define VM_ASSERT_IS_NOT_RUNNING(pVM) AssertMsg(!VM_IS_RUNNING_FOR_ASSERTIONS_ONLY(pVM), \
1021	("VM is running. enmVMState=%d\n", (pVM)->enmVMState))
1022	#endif
1023
1024	/** @def VM_ASSERT_EMT0
1025	* Asserts that the current thread IS emulation thread \#0 (EMT0).
1026	*/
1027	#define VM_ASSERT_EMT0(pVM) VMCPU_ASSERT_EMT(&(pVM)->aCpus[0])
1028
1029	/** @def VM_ASSERT_EMT0_RETURN
1030	* Asserts that the current thread IS emulation thread \#0 (EMT0) and returns if
1031	* it isn't.
1032	*/
1033	#define VM_ASSERT_EMT0_RETURN(pVM, rc) VMCPU_ASSERT_EMT_RETURN(&(pVM)->aCpus[0], (rc))
1034
1035
1036	/**
1037	* Asserts that the current thread is NOT the emulation thread.
1038	*/
1039	#define VM_ASSERT_OTHER_THREAD(pVM) \
1040	AssertMsg(!VM_IS_EMT(pVM), ("Not other thread!!\n"))
1041
1042
1043	/** @def VM_ASSERT_STATE
1044	* Asserts a certain VM state.
1045	*/
1046	#define VM_ASSERT_STATE(pVM, _enmState) \
1047	AssertMsg((pVM)->enmVMState == (_enmState), \
1048	("state %s, expected %s\n", VMGetStateName((pVM)->enmVMState), VMGetStateName(_enmState)))
1049
1050	/** @def VM_ASSERT_STATE_RETURN
1051	* Asserts a certain VM state and returns if it doesn't match.
1052	*/
1053	#define VM_ASSERT_STATE_RETURN(pVM, _enmState, rc) \
1054	AssertMsgReturn((pVM)->enmVMState == (_enmState), \
1055	("state %s, expected %s\n", VMGetStateName((pVM)->enmVMState), VMGetStateName(_enmState)), \
1056	(rc))
1057
1058	/** @def VM_IS_VALID_EXT
1059	* Asserts a the VM handle is valid for external access, i.e. not being destroy
1060	* or terminated. */
1061	#define VM_IS_VALID_EXT(pVM) \
1062	( RT_VALID_ALIGNED_PTR(pVM, PAGE_SIZE) \
1063	&& ( (unsigned)(pVM)->enmVMState < (unsigned)VMSTATE_DESTROYING \
1064	\|\| ( (unsigned)(pVM)->enmVMState == (unsigned)VMSTATE_DESTROYING \
1065	&& VM_IS_EMT(pVM))) )
1066
1067	/** @def VM_ASSERT_VALID_EXT_RETURN
1068	* Asserts a the VM handle is valid for external access, i.e. not being
1069	* destroy or terminated.
1070	*/
1071	#define VM_ASSERT_VALID_EXT_RETURN(pVM, rc) \
1072	AssertMsgReturn(VM_IS_VALID_EXT(pVM), \
1073	("pVM=%p state %s\n", (pVM), RT_VALID_ALIGNED_PTR(pVM, PAGE_SIZE) \
1074	? VMGetStateName(pVM->enmVMState) : ""), \
1075	(rc))
1076
1077	/** @def VMCPU_ASSERT_VALID_EXT_RETURN
1078	* Asserts a the VMCPU handle is valid for external access, i.e. not being
1079	* destroy or terminated.
1080	*/
1081	#define VMCPU_ASSERT_VALID_EXT_RETURN(pVCpu, rc) \
1082	AssertMsgReturn( RT_VALID_ALIGNED_PTR(pVCpu, 64) \
1083	&& RT_VALID_ALIGNED_PTR((pVCpu)->CTX_SUFF(pVM), PAGE_SIZE) \
1084	&& (unsigned)(pVCpu)->CTX_SUFF(pVM)->enmVMState < (unsigned)VMSTATE_DESTROYING, \
1085	("pVCpu=%p pVM=%p state %s\n", (pVCpu), RT_VALID_ALIGNED_PTR(pVCpu, 64) ? (pVCpu)->CTX_SUFF(pVM) : NULL, \
1086	RT_VALID_ALIGNED_PTR(pVCpu, 64) && RT_VALID_ALIGNED_PTR((pVCpu)->CTX_SUFF(pVM), PAGE_SIZE) \
1087	? VMGetStateName((pVCpu)->pVMR3->enmVMState) : ""), \
1088	(rc))
1089
1090	#endif /* !VBOX_FOR_DTRACE_LIB */
1091
1092
1093	/**
1094	* Helper that HM and NEM uses for safely modifying VM::bMainExecutionEngine.
1095	*
1096	* ONLY HM and NEM MAY USE THIS!
1097	*
1098	* @param a_pVM The cross context VM structure.
1099	* @param a_bValue The new value.
1100	* @internal
1101	*/
1102	#define VM_SET_MAIN_EXECUTION_ENGINE(a_pVM, a_bValue) \
1103	do { \
1104	const_cast<uint8_t >(&(a_pVM)->bMainExecutionEngine) = (a_bValue); \
1105	ASMCompilerBarrier(); /* just to be on the safe side */ \
1106	} while (0)
1107
1108	/**
1109	* Checks whether raw-mode is used.
1110	*
1111	* @retval true if either is used.
1112	* @retval false if software virtualization (raw-mode) is used.
1113	*
1114	* @param a_pVM The cross context VM structure.
1115	* @sa VM_IS_HM_OR_NEM_ENABLED, VM_IS_HM_ENABLED, VM_IS_NEM_ENABLED.
1116	* @internal
1117	*/
1118	#ifdef VBOX_WITH_RAW_MODE
1119	# define VM_IS_RAW_MODE_ENABLED(a_pVM) ((a_pVM)->bMainExecutionEngine == VM_EXEC_ENGINE_RAW_MODE)
1120	#else
1121	# define VM_IS_RAW_MODE_ENABLED(a_pVM) (false)
1122	#endif
1123
1124	/**
1125	* Checks whether HM (VT-x/AMD-V) or NEM is being used by this VM.
1126	*
1127	* @retval true if either is used.
1128	* @retval false if software virtualization (raw-mode) is used.
1129	*
1130	* @param a_pVM The cross context VM structure.
1131	* @sa VM_IS_RAW_MODE_ENABLED, VM_IS_HM_ENABLED, VM_IS_NEM_ENABLED.
1132	* @internal
1133	*/
1134	#define VM_IS_HM_OR_NEM_ENABLED(a_pVM) ((a_pVM)->bMainExecutionEngine != VM_EXEC_ENGINE_RAW_MODE)
1135
1136	/**
1137	* Checks whether HM is being used by this VM.
1138	*
1139	* @retval true if HM (VT-x/AMD-v) is used.
1140	* @retval false if not.
1141	*
1142	* @param a_pVM The cross context VM structure.
1143	* @sa VM_IS_NEM_ENABLED, VM_IS_RAW_MODE_ENABLED, VM_IS_HM_OR_NEM_ENABLED.
1144	* @internal
1145	*/
1146	#define VM_IS_HM_ENABLED(a_pVM) ((a_pVM)->bMainExecutionEngine == VM_EXEC_ENGINE_HW_VIRT)
1147
1148	/**
1149	* Checks whether NEM is being used by this VM.
1150	*
1151	* @retval true if a native hypervisor API is used.
1152	* @retval false if not.
1153	*
1154	* @param a_pVM The cross context VM structure.
1155	* @sa VM_IS_HM_ENABLED, VM_IS_RAW_MODE_ENABLED, VM_IS_HM_OR_NEM_ENABLED.
1156	* @internal
1157	*/
1158	#define VM_IS_NEM_ENABLED(a_pVM) ((a_pVM)->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API)
1159
1160
1161	/**
1162	* The cross context VM structure.
1163	*
1164	* It contains all the VM data which have to be available in all contexts.
1165	* Even if it contains all the data the idea is to use APIs not to modify all
1166	* the members all around the place. Therefore we make use of unions to hide
1167	* everything which isn't local to the current source module. This means we'll
1168	* have to pay a little bit of attention when adding new members to structures
1169	* in the unions and make sure to keep the padding sizes up to date.
1170	*
1171	* Run 'kmk run-struct-tests' (from src/VBox/VMM if you like) after updating!
1172	*/
1173	typedef struct VM
1174	{
1175	/** The state of the VM.
1176	* This field is read only to everyone except the VM and EM. */
1177	VMSTATE volatile enmVMState;
1178	/** Forced action flags.
1179	* See the VM_FF_* \#defines. Updated atomically.
1180	*/
1181	volatile uint32_t fGlobalForcedActions;
1182	/** Pointer to the array of page descriptors for the VM structure allocation. */
1183	R3PTRTYPE(PSUPPAGE) paVMPagesR3;
1184	/** Session handle. For use when calling SUPR0 APIs. */
1185	PSUPDRVSESSION pSession;
1186	/** Pointer to the ring-3 VM structure. */
1187	PUVM pUVM;
1188	/** Ring-3 Host Context VM Pointer. */
1189	R3PTRTYPE(struct VM *) pVMR3;
1190	/** Ring-0 Host Context VM Pointer. */
1191	R0PTRTYPE(struct VM *) pVMR0;
1192	/** Raw-mode Context VM Pointer. */
1193	RCPTRTYPE(struct VM *) pVMRC;
1194
1195	/** The GVM VM handle. Only the GVM should modify this field. */
1196	uint32_t hSelf;
1197	/** Number of virtual CPUs. */
1198	uint32_t cCpus;
1199	/** CPU excution cap (1-100) */
1200	uint32_t uCpuExecutionCap;
1201
1202	#ifdef VBOX_BUGREF_9217
1203	/** Structure version number (TBD). */
1204	uint32_t uStructVersion;
1205	/** Size of the VM structure. */
1206	uint32_t cbSelf;
1207	/** Size of the VMCPU structure. */
1208	uint32_t cbVCpu;
1209	#else
1210	/** Size of the VM structure including the VMCPU array. */
1211	uint32_t cbSelf;
1212	#endif
1213
1214	#ifdef VBOX_WITH_RAW_MODE
1215	/** Offset to the VMCPU array starting from beginning of this structure,
1216	* for raw-mode assembly code. */
1217	uint32_t offVMCPU;
1218	#else
1219	uint32_t u32Unused;
1220	#endif
1221
1222	/**
1223	* VMMSwitcher assembly entry point returning to host context.
1224	*
1225	* Depending on how the host handles the rc status given in @a eax, this may
1226	* return and let the caller resume whatever it was doing prior to the call.
1227	*
1228	* @param eax The return code, register.
1229	* @remark Assume interrupts disabled.
1230	* @remark This method pointer lives here because TRPM needs it.
1231	*/
1232	RTRCPTR pfnVMMRCToHostAsm/(int32_t eax)/;
1233
1234	/**
1235	* VMMSwitcher assembly entry point returning to host context without saving the
1236	* raw-mode context (hyper) registers.
1237	*
1238	* Unlike pfnVMMRC2HCAsm, this will not return to the caller. Instead it
1239	* expects the caller to save a RC context in CPUM where one might return if the
1240	* return code indicate that this is possible.
1241	*
1242	* This method pointer lives here because TRPM needs it.
1243	*
1244	* @param eax The return code, register.
1245	* @remark Assume interrupts disabled.
1246	* @remark This method pointer lives here because TRPM needs it.
1247	*/
1248	RTRCPTR pfnVMMRCToHostAsmNoReturn/(int32_t eax)/;
1249
1250	/** @name Various items that are frequently accessed.
1251	* @{ */
1252	/** The main execution engine, VM_EXEC_ENGINE_XXX.
1253	* This is set early during vmR3InitRing3 by HM or NEM. */
1254	uint8_t const bMainExecutionEngine;
1255
1256	/** Whether to recompile user mode code or run it raw/hm/nem.
1257	* In non-raw-mode both fRecompileUser and fRecompileSupervisor must be set
1258	* to recompiler stuff. */
1259	bool fRecompileUser;
1260	/** Whether to recompile supervisor mode code or run it raw/hm/nem.
1261	* In non-raw-mode both fRecompileUser and fRecompileSupervisor must be set
1262	* to recompiler stuff. */
1263	bool fRecompileSupervisor;
1264	/** Whether raw mode supports ring-1 code or not.
1265	* This will be cleared when not in raw-mode. */
1266	bool fRawRing1Enabled;
1267	/** PATM enabled flag.
1268	* This is placed here for performance reasons.
1269	* This will be cleared when not in raw-mode. */
1270	bool fPATMEnabled;
1271	/** CSAM enabled flag.
1272	* This is placed here for performance reasons.
1273	* This will be cleared when not in raw-mode. */
1274	bool fCSAMEnabled;
1275
1276	/** Hardware VM support is available and enabled.
1277	* Determined very early during init.
1278	* This is placed here for performance reasons.
1279	* @todo obsoleted by bMainExecutionEngine, eliminate. */
1280	bool fHMEnabled;
1281	/** Hardware VM support requires a minimal raw-mode context.
1282	* This is never set on 64-bit hosts, only 32-bit hosts requires it. */
1283	bool fHMNeedRawModeCtx;
1284
1285	/** Set when this VM is the master FT node.
1286	* @todo This doesn't need to be here, FTM should store it in it's own
1287	* structures instead. */
1288	bool fFaultTolerantMaster;
1289	/** Large page enabled flag.
1290	* @todo This doesn't need to be here, PGM should store it in it's own
1291	* structures instead. */
1292	bool fUseLargePages;
1293	/** @} */
1294
1295	/** Alignment padding. */
1296	uint8_t uPadding1[2];
1297
1298	/** @name Debugging
1299	* @{ */
1300	/** Raw-mode Context VM Pointer. */
1301	RCPTRTYPE(RTTRACEBUF) hTraceBufRC;
1302	/** Ring-3 Host Context VM Pointer. */
1303	R3PTRTYPE(RTTRACEBUF) hTraceBufR3;
1304	/** Ring-0 Host Context VM Pointer. */
1305	R0PTRTYPE(RTTRACEBUF) hTraceBufR0;
1306	/** @} */
1307
1308	#if HC_ARCH_BITS == 32
1309	/** Alignment padding. */
1310	uint32_t uPadding2;
1311	#endif
1312
1313	/** @name Switcher statistics (remove)
1314	* @{ */
1315	/** Profiling the total time from Qemu to GC. */
1316	STAMPROFILEADV StatTotalQemuToGC;
1317	/** Profiling the total time from GC to Qemu. */
1318	STAMPROFILEADV StatTotalGCToQemu;
1319	/** Profiling the total time spent in GC. */
1320	STAMPROFILEADV StatTotalInGC;
1321	/** Profiling the total time spent not in Qemu. */
1322	STAMPROFILEADV StatTotalInQemu;
1323	/** Profiling the VMMSwitcher code for going to GC. */
1324	STAMPROFILEADV StatSwitcherToGC;
1325	/** Profiling the VMMSwitcher code for going to HC. */
1326	STAMPROFILEADV StatSwitcherToHC;
1327	STAMPROFILEADV StatSwitcherSaveRegs;
1328	STAMPROFILEADV StatSwitcherSysEnter;
1329	STAMPROFILEADV StatSwitcherDebug;
1330	STAMPROFILEADV StatSwitcherCR0;
1331	STAMPROFILEADV StatSwitcherCR4;
1332	STAMPROFILEADV StatSwitcherJmpCR3;
1333	STAMPROFILEADV StatSwitcherRstrRegs;
1334	STAMPROFILEADV StatSwitcherLgdt;
1335	STAMPROFILEADV StatSwitcherLidt;
1336	STAMPROFILEADV StatSwitcherLldt;
1337	STAMPROFILEADV StatSwitcherTSS;
1338	/** @} */
1339
1340	/** Padding - the unions must be aligned on a 64 bytes boundary and the unions
1341	* must start at the same offset on both 64-bit and 32-bit hosts. */
1342	#ifdef VBOX_BUGREF_9217
1343	uint8_t abAlignment3[(HC_ARCH_BITS == 32 ? 24 : 0) + 32];
1344	#else
1345	uint8_t abAlignment3[(HC_ARCH_BITS == 32 ? 24 : 0) + 40];
1346	#endif
1347
1348	/** CPUM part. */
1349	union
1350	{
1351	#ifdef VMM_INCLUDED_SRC_include_CPUMInternal_h
1352	struct CPUM s;
1353	#endif
1354	#ifdef VBOX_INCLUDED_vmm_cpum_h
1355	/** Read only info exposed about the host and guest CPUs. */
1356	struct
1357	{
1358	/** Padding for hidden fields. */
1359	uint8_t abHidden0[64];
1360	/** Host CPU feature information. */
1361	CPUMFEATURES HostFeatures;
1362	/** Guest CPU feature information. */
1363	CPUMFEATURES GuestFeatures;
1364	} const ro;
1365	#endif
1366	uint8_t padding[1536]; /* multiple of 64 */
1367	} cpum;
1368
1369	/** VMM part. */
1370	union
1371	{
1372	#ifdef VMM_INCLUDED_SRC_include_VMMInternal_h
1373	struct VMM s;
1374	#endif
1375	uint8_t padding[1600]; /* multiple of 64 */
1376	} vmm;
1377
1378	/** PGM part. */
1379	union
1380	{
1381	#ifdef VMM_INCLUDED_SRC_include_PGMInternal_h
1382	struct PGM s;
1383	#endif
1384	uint8_t padding[40962+6080]; / multiple of 64 */
1385	} pgm;
1386
1387	/** HM part. */
1388	union
1389	{
1390	#ifdef VMM_INCLUDED_SRC_include_HMInternal_h
1391	struct HM s;
1392	#endif
1393	uint8_t padding[5440]; /* multiple of 64 */
1394	} hm;
1395
1396	/** TRPM part. */
1397	union
1398	{
1399	#ifdef VMM_INCLUDED_SRC_include_TRPMInternal_h
1400	struct TRPM s;
1401	#endif
1402	uint8_t padding[5248]; /* multiple of 64 */
1403	} trpm;
1404
1405	/** SELM part. */
1406	union
1407	{
1408	#ifdef VMM_INCLUDED_SRC_include_SELMInternal_h
1409	struct SELM s;
1410	#endif
1411	uint8_t padding[768]; /* multiple of 64 */
1412	} selm;
1413
1414	/** MM part. */
1415	union
1416	{
1417	#ifdef VMM_INCLUDED_SRC_include_MMInternal_h
1418	struct MM s;
1419	#endif
1420	uint8_t padding[192]; /* multiple of 64 */
1421	} mm;
1422
1423	/** PDM part. */
1424	union
1425	{
1426	#ifdef VMM_INCLUDED_SRC_include_PDMInternal_h
1427	struct PDM s;
1428	#endif
1429	uint8_t padding[1920]; /* multiple of 64 */
1430	} pdm;
1431
1432	/** IOM part. */
1433	union
1434	{
1435	#ifdef VMM_INCLUDED_SRC_include_IOMInternal_h
1436	struct IOM s;
1437	#endif
1438	uint8_t padding[896]; /* multiple of 64 */
1439	} iom;
1440
1441	/** EM part. */
1442	union
1443	{
1444	#ifdef VMM_INCLUDED_SRC_include_EMInternal_h
1445	struct EM s;
1446	#endif
1447	uint8_t padding[256]; /* multiple of 64 */
1448	} em;
1449
1450	/** NEM part. */
1451	union
1452	{
1453	#ifdef VMM_INCLUDED_SRC_include_NEMInternal_h
1454	struct NEM s;
1455	#endif
1456	uint8_t padding[128]; /* multiple of 64 */
1457	} nem;
1458
1459	/** TM part. */
1460	union
1461	{
1462	#ifdef VMM_INCLUDED_SRC_include_TMInternal_h
1463	struct TM s;
1464	#endif
1465	uint8_t padding[2496]; /* multiple of 64 */
1466	} tm;
1467
1468	/** DBGF part. */
1469	union
1470	{
1471	#ifdef VMM_INCLUDED_SRC_include_DBGFInternal_h
1472	struct DBGF s;
1473	#endif
1474	#ifdef VBOX_INCLUDED_vmm_dbgf_h
1475	/** Read only info exposed about interrupt breakpoints and selected events. */
1476	struct
1477	{
1478	/** Bitmap of enabled hardware interrupt breakpoints. */
1479	uint32_t bmHardIntBreakpoints[256 / 32];
1480	/** Bitmap of enabled software interrupt breakpoints. */
1481	uint32_t bmSoftIntBreakpoints[256 / 32];
1482	/** Bitmap of selected events.
1483	* This includes non-selectable events too for simplicity, we maintain the
1484	* state for some of these, as it may come in handy. */
1485	uint64_t bmSelectedEvents[(DBGFEVENT_END + 63) / 64];
1486	/** Enabled hardware interrupt breakpoints. */
1487	uint32_t cHardIntBreakpoints;
1488	/** Enabled software interrupt breakpoints. */
1489	uint32_t cSoftIntBreakpoints;
1490	/** The number of selected events. */
1491	uint32_t cSelectedEvents;
1492	/** The number of enabled hardware breakpoints. */
1493	uint8_t cEnabledHwBreakpoints;
1494	/** The number of enabled hardware I/O breakpoints. */
1495	uint8_t cEnabledHwIoBreakpoints;
1496	/** The number of enabled INT3 breakpoints. */
1497	uint8_t cEnabledInt3Breakpoints;
1498	uint8_t abPadding[1]; /*< Unused padding space up for grabs. /
1499	} const ro;
1500	#endif
1501	uint8_t padding[2432]; /* multiple of 64 */
1502	} dbgf;
1503
1504	/** SSM part. */
1505	union
1506	{
1507	#ifdef VMM_INCLUDED_SRC_include_SSMInternal_h
1508	struct SSM s;
1509	#endif
1510	uint8_t padding[128]; /* multiple of 64 */
1511	} ssm;
1512
1513	/** FTM part. */
1514	union
1515	{
1516	#ifdef VMM_INCLUDED_SRC_include_FTMInternal_h
1517	struct FTM s;
1518	#endif
1519	uint8_t padding[512]; /* multiple of 64 */
1520	} ftm;
1521
1522	#ifdef VBOX_WITH_RAW_MODE
1523	/** PATM part. */
1524	union
1525	{
1526	# ifdef VMM_INCLUDED_SRC_include_PATMInternal_h
1527	struct PATM s;
1528	# endif
1529	uint8_t padding[768]; /* multiple of 64 */
1530	} patm;
1531
1532	/** CSAM part. */
1533	union
1534	{
1535	# ifdef VMM_INCLUDED_SRC_include_CSAMInternal_h
1536	struct CSAM s;
1537	# endif
1538	uint8_t padding[1088]; /* multiple of 64 */
1539	} csam;
1540	#endif
1541
1542	#ifdef VBOX_WITH_REM
1543	/** REM part. */
1544	union
1545	{
1546	# ifdef VMM_INCLUDED_SRC_include_REMInternal_h
1547	struct REM s;
1548	# endif
1549	uint8_t padding[0x11100]; /* multiple of 64 */
1550	} rem;
1551	#endif
1552
1553	union
1554	{
1555	#ifdef VMM_INCLUDED_SRC_include_GIMInternal_h
1556	struct GIM s;
1557	#endif
1558	uint8_t padding[448]; /* multiple of 64 */
1559	} gim;
1560
1561	union
1562	{
1563	#ifdef VMM_INCLUDED_SRC_include_APICInternal_h
1564	struct APIC s;
1565	#endif
1566	uint8_t padding[128]; /* multiple of 8 */
1567	} apic;
1568
1569	/* ---- begin small stuff ---- */
1570
1571	/** VM part. */
1572	union
1573	{
1574	#ifdef VMM_INCLUDED_SRC_include_VMInternal_h
1575	struct VMINT s;
1576	#endif
1577	uint8_t padding[32]; /* multiple of 8 */
1578	} vm;
1579
1580	/** CFGM part. */
1581	union
1582	{
1583	#ifdef VMM_INCLUDED_SRC_include_CFGMInternal_h
1584	struct CFGM s;
1585	#endif
1586	uint8_t padding[8]; /* multiple of 8 */
1587	} cfgm;
1588
1589	#ifdef VBOX_BUGREF_9217
1590	/** Padding for aligning the structure size on a page boundrary. */
1591	# if defined(VBOX_WITH_REM) && defined(VBOX_WITH_RAW_MODE)
1592	uint8_t abAlignment2[3670 - sizeof(PVMCPUR3) * VMM_MAX_CPU_COUNT];
1593	# elif defined(VBOX_WITH_REM) && !defined(VBOX_WITH_RAW_MODE)
1594	uint8_t abAlignment2[1430 - sizeof(PVMCPUR3) * VMM_MAX_CPU_COUNT];
1595	# elif !defined(VBOX_WITH_REM) && defined(VBOX_WITH_RAW_MODE)
1596	uint8_t abAlignment2[3926 - sizeof(PVMCPUR3) * VMM_MAX_CPU_COUNT];
1597	# else
1598	uint8_t abAlignment2[1686 - sizeof(PVMCPUR3) * VMM_MAX_CPU_COUNT];
1599	# endif
1600	#else
1601	/** Padding for aligning the cpu array on a page boundary. */
1602	# if defined(VBOX_WITH_REM) && defined(VBOX_WITH_RAW_MODE)
1603	uint8_t abAlignment2[3670];
1604	# elif defined(VBOX_WITH_REM) && !defined(VBOX_WITH_RAW_MODE)
1605	uint8_t abAlignment2[1430];
1606	# elif !defined(VBOX_WITH_REM) && defined(VBOX_WITH_RAW_MODE)
1607	uint8_t abAlignment2[3926];
1608	# else
1609	uint8_t abAlignment2[1686];
1610	# endif
1611	#endif
1612
1613	/* ---- end small stuff ---- */
1614
1615	#ifdef VBOX_BUGREF_9217
1616	/** Array of VMCPU pointers. */
1617	PVMCPUR3 apCpus[VMM_MAX_CPU_COUNT];
1618	#else
1619	/** VMCPU array for the configured number of virtual CPUs.
1620	* Must be aligned on a page boundary for TLB hit reasons as well as
1621	* alignment of VMCPU members. */
1622	VMCPU aCpus[1];
1623	#endif
1624	} VM;
1625
1626
1627	#ifdef IN_RC
1628	RT_C_DECLS_BEGIN
1629
1630	/** The VM structure.
1631	* This is imported from the VMMRCBuiltin module, i.e. it's a one of those magic
1632	* globals which we should avoid using.
1633	*/
1634	extern DECLIMPORT(VM) g_VM;
1635
1636	/** The VMCPU structure for virtual CPU \#0.
1637	* This is imported from the VMMRCBuiltin module, i.e. it's a one of those magic
1638	* globals which we should avoid using.
1639	*/
1640	extern DECLIMPORT(VMCPU) g_VCpu0;
1641
1642	RT_C_DECLS_END
1643	#endif
1644
1645	/** @} */
1646
1647	#endif /* !VBOX_INCLUDED_vmm_vm_h */
1648

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source: vbox/trunk/include/VBox/vmm/vm.h@ 79146

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