VirtualBox

source: vbox/trunk/include/VBox/vmm/vm.h@ 80024

Last change on this file since 80024 was 80024, checked in by vboxsync, 5 years ago

VMM: Kicking out raw-mode (work in progress) - em config. bugref:9517
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1/** @file
2 * VM - The Virtual Machine, data.
3 */
4
5/*
6 * Copyright (C) 2006-2019 Oracle Corporation
7 *
8 * This file is part of VirtualBox Open Source Edition (OSE), as
9 * available from http://www.virtualbox.org. This file is free software;
10 * you can redistribute it and/or modify it under the terms of the GNU
11 * General Public License (GPL) as published by the Free Software
12 * Foundation, in version 2 as it comes in the "COPYING" file of the
13 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15 *
16 * The contents of this file may alternatively be used under the terms
17 * of the Common Development and Distribution License Version 1.0
18 * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19 * VirtualBox OSE distribution, in which case the provisions of the
20 * CDDL are applicable instead of those of the GPL.
21 *
22 * You may elect to license modified versions of this file under the
23 * terms and conditions of either the GPL or the CDDL or both.
24 */
25
26#ifndef VBOX_INCLUDED_vmm_vm_h
27#define VBOX_INCLUDED_vmm_vm_h
28#ifndef RT_WITHOUT_PRAGMA_ONCE
29# pragma once
30#endif
31
32#ifndef VBOX_FOR_DTRACE_LIB
33# include <iprt/param.h>
34# include <VBox/param.h>
35# include <VBox/types.h>
36# include <VBox/vmm/cpum.h>
37# include <VBox/vmm/stam.h>
38# include <VBox/vmm/vmapi.h>
39# include <VBox/vmm/vmm.h>
40# include <VBox/sup.h>
41#else
42# pragma D depends_on library vbox-types.d
43# pragma D depends_on library CPUMInternal.d
44# define VMM_INCLUDED_SRC_include_CPUMInternal_h
45#endif
46
47
48
49/** @defgroup grp_vm The Virtual Machine
50 * @ingroup grp_vmm
51 * @{
52 */
53
54/**
55 * The state of a Virtual CPU.
56 *
57 * The basic state indicated here is whether the CPU has been started or not. In
58 * addition, there are sub-states when started for assisting scheduling (GVMM
59 * mostly).
60 *
61 * The transition out of the STOPPED state is done by a vmR3PowerOn.
62 * The transition back to the STOPPED state is done by vmR3PowerOff.
63 *
64 * (Alternatively we could let vmR3PowerOn start CPU 0 only and let the SPIP
65 * handling switch on the other CPUs. Then vmR3Reset would stop all but CPU 0.)
66 */
67typedef enum VMCPUSTATE
68{
69 /** The customary invalid zero. */
70 VMCPUSTATE_INVALID = 0,
71
72 /** Virtual CPU has not yet been started. */
73 VMCPUSTATE_STOPPED,
74
75 /** CPU started. */
76 VMCPUSTATE_STARTED,
77 /** CPU started in HM context. */
78 VMCPUSTATE_STARTED_HM,
79 /** Executing guest code and can be poked (RC or STI bits of HM). */
80 VMCPUSTATE_STARTED_EXEC,
81 /** Executing guest code in the recompiler. */
82 VMCPUSTATE_STARTED_EXEC_REM,
83 /** Executing guest code using NEM. */
84 VMCPUSTATE_STARTED_EXEC_NEM,
85 VMCPUSTATE_STARTED_EXEC_NEM_WAIT,
86 VMCPUSTATE_STARTED_EXEC_NEM_CANCELED,
87 /** Halted. */
88 VMCPUSTATE_STARTED_HALTED,
89
90 /** The end of valid virtual CPU states. */
91 VMCPUSTATE_END,
92
93 /** Ensure 32-bit type. */
94 VMCPUSTATE_32BIT_HACK = 0x7fffffff
95} VMCPUSTATE;
96
97/** Enables 64-bit FFs. */
98#define VMCPU_WITH_64_BIT_FFS
99
100
101/**
102 * The cross context virtual CPU structure.
103 *
104 * Run 'kmk run-struct-tests' (from src/VBox/VMM if you like) after updating!
105 */
106typedef struct VMCPU
107{
108 /** @name Volatile per-cpu data.
109 * @{ */
110 /** Per CPU forced action.
111 * See the VMCPU_FF_* \#defines. Updated atomically. */
112#ifdef VMCPU_WITH_64_BIT_FFS
113 uint64_t volatile fLocalForcedActions;
114#else
115 uint32_t volatile fLocalForcedActions;
116 uint32_t fForLocalForcedActionsExpansion;
117#endif
118 /** The CPU state. */
119 VMCPUSTATE volatile enmState;
120
121 /** Which host CPU ID is this EMT running on.
122 * Only valid when in RC or HMR0 with scheduling disabled. */
123 RTCPUID volatile idHostCpu;
124 /** The CPU set index corresponding to idHostCpu, UINT32_MAX if not valid.
125 * @remarks Best to make sure iHostCpuSet shares cache line with idHostCpu! */
126 uint32_t volatile iHostCpuSet;
127 /** Padding up to 64 bytes. */
128 uint8_t abAlignment0[64 - 20];
129 /** @} */
130
131 /** IEM part.
132 * @remarks This comes first as it allows the use of 8-bit immediates for the
133 * first 64 bytes of the structure, reducing code size a wee bit. */
134#ifdef VMM_INCLUDED_SRC_include_IEMInternal_h /* For PDB hacking. */
135 union VMCPUUNIONIEMFULL
136#else
137 union VMCPUUNIONIEMSTUB
138#endif
139 {
140#ifdef VMM_INCLUDED_SRC_include_IEMInternal_h
141 struct IEMCPU s;
142#endif
143 uint8_t padding[18496]; /* multiple of 64 */
144 } iem;
145
146 /** @name Static per-cpu data.
147 * (Putting this after IEM, hoping that it's less frequently used than it.)
148 * @{ */
149 /** The CPU ID.
150 * This is the index into the VM::aCpu array. */
151 VMCPUID idCpu;
152 /** Raw-mode Context VM Pointer. */
153 PVMRC pVMRC;
154 /** Ring-3 Host Context VM Pointer. */
155 PVMR3 pVMR3;
156 /** Ring-0 Host Context VM Pointer. */
157 PVMR0 pVMR0;
158 /** Pointer to the ring-3 UVMCPU structure. */
159 PUVMCPU pUVCpu;
160 /** The native thread handle. */
161 RTNATIVETHREAD hNativeThread;
162 /** The native R0 thread handle. (different from the R3 handle!) */
163 RTNATIVETHREAD hNativeThreadR0;
164 /** Align the structures below bit on a 64-byte boundary and make sure it starts
165 * at the same offset in both 64-bit and 32-bit builds.
166 *
167 * @remarks The alignments of the members that are larger than 48 bytes should be
168 * 64-byte for cache line reasons. structs containing small amounts of
169 * data could be lumped together at the end with a < 64 byte padding
170 * following it (to grow into and align the struct size).
171 */
172 uint8_t abAlignment1[64 - 4 - 4 - 5 * (HC_ARCH_BITS == 64 ? 8 : 4)];
173 /** @} */
174
175 /** HM part. */
176 union VMCPUUNIONHM
177 {
178#ifdef VMM_INCLUDED_SRC_include_HMInternal_h
179 struct HMCPU s;
180#endif
181 uint8_t padding[5888]; /* multiple of 64 */
182 } hm;
183
184 /** NEM part. */
185 union VMCPUUNIONNEM
186 {
187#ifdef VMM_INCLUDED_SRC_include_NEMInternal_h
188 struct NEMCPU s;
189#endif
190 uint8_t padding[512]; /* multiple of 64 */
191 } nem;
192
193 /** TRPM part. */
194 union VMCPUUNIONTRPM
195 {
196#ifdef VMM_INCLUDED_SRC_include_TRPMInternal_h
197 struct TRPMCPU s;
198#endif
199 uint8_t padding[128]; /* multiple of 64 */
200 } trpm;
201
202 /** TM part. */
203 union VMCPUUNIONTM
204 {
205#ifdef VMM_INCLUDED_SRC_include_TMInternal_h
206 struct TMCPU s;
207#endif
208 uint8_t padding[384]; /* multiple of 64 */
209 } tm;
210
211 /** VMM part. */
212 union VMCPUUNIONVMM
213 {
214#ifdef VMM_INCLUDED_SRC_include_VMMInternal_h
215 struct VMMCPU s;
216#endif
217 uint8_t padding[896]; /* multiple of 64 */
218 } vmm;
219
220 /** PDM part. */
221 union VMCPUUNIONPDM
222 {
223#ifdef VMM_INCLUDED_SRC_include_PDMInternal_h
224 struct PDMCPU s;
225#endif
226 uint8_t padding[256]; /* multiple of 64 */
227 } pdm;
228
229 /** IOM part. */
230 union VMCPUUNIONIOM
231 {
232#ifdef VMM_INCLUDED_SRC_include_IOMInternal_h
233 struct IOMCPU s;
234#endif
235 uint8_t padding[512]; /* multiple of 64 */
236 } iom;
237
238 /** DBGF part.
239 * @todo Combine this with other tiny structures. */
240 union VMCPUUNIONDBGF
241 {
242#ifdef VMM_INCLUDED_SRC_include_DBGFInternal_h
243 struct DBGFCPU s;
244#endif
245 uint8_t padding[256]; /* multiple of 64 */
246 } dbgf;
247
248 /** GIM part. */
249 union VMCPUUNIONGIM
250 {
251#ifdef VMM_INCLUDED_SRC_include_GIMInternal_h
252 struct GIMCPU s;
253#endif
254 uint8_t padding[512]; /* multiple of 64 */
255 } gim;
256
257 /** APIC part. */
258 union VMCPUUNIONAPIC
259 {
260#ifdef VMM_INCLUDED_SRC_include_APICInternal_h
261 struct APICCPU s;
262#endif
263 uint8_t padding[1792]; /* multiple of 64 */
264 } apic;
265
266 /*
267 * Some less frequently used global members that doesn't need to take up
268 * precious space at the head of the structure.
269 */
270
271 /** Trace groups enable flags. */
272 uint32_t fTraceGroups; /* 64 / 44 */
273 /** State data for use by ad hoc profiling. */
274 uint32_t uAdHoc;
275 /** Profiling samples for use by ad hoc profiling. */
276 STAMPROFILEADV aStatAdHoc[8]; /* size: 40*8 = 320 */
277
278 /** Align the following members on page boundary. */
279 uint8_t abAlignment2[2680];
280
281 /** PGM part. */
282 union VMCPUUNIONPGM
283 {
284#ifdef VMM_INCLUDED_SRC_include_PGMInternal_h
285 struct PGMCPU s;
286#endif
287 uint8_t padding[4096]; /* multiple of 4096 */
288 } pgm;
289
290 /** CPUM part. */
291 union VMCPUUNIONCPUM
292 {
293#ifdef VMM_INCLUDED_SRC_include_CPUMInternal_h
294 struct CPUMCPU s;
295#endif
296#ifdef VMCPU_INCL_CPUM_GST_CTX
297 /** The guest CPUM context for direct use by execution engines.
298 * This is not for general consumption, but for HM, REM, IEM, and maybe a few
299 * others. The rest will use the function based CPUM API. */
300 CPUMCTX GstCtx;
301#endif
302 uint8_t padding[4096]; /* multiple of 4096 */
303 } cpum;
304
305 /** EM part. */
306 union VMCPUUNIONEM
307 {
308#ifdef VMM_INCLUDED_SRC_include_EMInternal_h
309 struct EMCPU s;
310#endif
311 uint8_t padding[40960]; /* multiple of 4096 */
312 } em;
313} VMCPU;
314
315
316#ifndef VBOX_FOR_DTRACE_LIB
317AssertCompileSizeAlignment(VMCPU, 4096);
318
319/** @name Operations on VMCPU::enmState
320 * @{ */
321/** Gets the VMCPU state. */
322#define VMCPU_GET_STATE(pVCpu) ( (pVCpu)->enmState )
323/** Sets the VMCPU state. */
324#define VMCPU_SET_STATE(pVCpu, enmNewState) \
325 ASMAtomicWriteU32((uint32_t volatile *)&(pVCpu)->enmState, (enmNewState))
326/** Cmpares and sets the VMCPU state. */
327#define VMCPU_CMPXCHG_STATE(pVCpu, enmNewState, enmOldState) \
328 ASMAtomicCmpXchgU32((uint32_t volatile *)&(pVCpu)->enmState, (enmNewState), (enmOldState))
329/** Checks the VMCPU state. */
330#ifdef VBOX_STRICT
331# define VMCPU_ASSERT_STATE(pVCpu, enmExpectedState) \
332 do { \
333 VMCPUSTATE enmState = VMCPU_GET_STATE(pVCpu); \
334 AssertMsg(enmState == (enmExpectedState), \
335 ("enmState=%d enmExpectedState=%d idCpu=%u\n", \
336 enmState, enmExpectedState, (pVCpu)->idCpu)); \
337 } while (0)
338#else
339# define VMCPU_ASSERT_STATE(pVCpu, enmExpectedState) do { } while (0)
340#endif
341/** Tests if the state means that the CPU is started. */
342#define VMCPUSTATE_IS_STARTED(enmState) ( (enmState) > VMCPUSTATE_STOPPED )
343/** Tests if the state means that the CPU is stopped. */
344#define VMCPUSTATE_IS_STOPPED(enmState) ( (enmState) == VMCPUSTATE_STOPPED )
345/** @} */
346
347
348/** The name of the raw-mode context VMM Core module. */
349#define VMMRC_MAIN_MODULE_NAME "VMMRC.rc"
350/** The name of the ring-0 context VMM Core module. */
351#define VMMR0_MAIN_MODULE_NAME "VMMR0.r0"
352
353
354/** VM Forced Action Flags.
355 *
356 * Use the VM_FF_SET() and VM_FF_CLEAR() macros to change the force
357 * action mask of a VM.
358 *
359 * Available VM bits:
360 * 0, 1, 5, 6, 7, 13, 14, 15, 16, 17, 21, 22, 23, 24, 25, 26, 27, 28, 30
361 *
362 *
363 * Available VMCPU bits:
364 * 14, 15, 36 to 63
365 *
366 * @todo If we run low on VMCPU, we may consider merging the SELM bits
367 *
368 * @{
369 */
370/** The virtual sync clock has been stopped, go to TM until it has been
371 * restarted... */
372#define VM_FF_TM_VIRTUAL_SYNC RT_BIT_32(VM_FF_TM_VIRTUAL_SYNC_BIT)
373#define VM_FF_TM_VIRTUAL_SYNC_BIT 2
374/** PDM Queues are pending. */
375#define VM_FF_PDM_QUEUES RT_BIT_32(VM_FF_PDM_QUEUES_BIT)
376/** The bit number for VM_FF_PDM_QUEUES. */
377#define VM_FF_PDM_QUEUES_BIT 3
378/** PDM DMA transfers are pending. */
379#define VM_FF_PDM_DMA RT_BIT_32(VM_FF_PDM_DMA_BIT)
380/** The bit number for VM_FF_PDM_DMA. */
381#define VM_FF_PDM_DMA_BIT 4
382/** This action forces the VM to call DBGF so DBGF can service debugger
383 * requests in the emulation thread.
384 * This action flag stays asserted till DBGF clears it.*/
385#define VM_FF_DBGF RT_BIT_32(VM_FF_DBGF_BIT)
386/** The bit number for VM_FF_DBGF. */
387#define VM_FF_DBGF_BIT 8
388/** This action forces the VM to service pending requests from other
389 * thread or requests which must be executed in another context. */
390#define VM_FF_REQUEST RT_BIT_32(VM_FF_REQUEST_BIT)
391#define VM_FF_REQUEST_BIT 9
392/** Check for VM state changes and take appropriate action. */
393#define VM_FF_CHECK_VM_STATE RT_BIT_32(VM_FF_CHECK_VM_STATE_BIT)
394/** The bit number for VM_FF_CHECK_VM_STATE. */
395#define VM_FF_CHECK_VM_STATE_BIT 10
396/** Reset the VM. (postponed) */
397#define VM_FF_RESET RT_BIT_32(VM_FF_RESET_BIT)
398/** The bit number for VM_FF_RESET. */
399#define VM_FF_RESET_BIT 11
400/** EMT rendezvous in VMM. */
401#define VM_FF_EMT_RENDEZVOUS RT_BIT_32(VM_FF_EMT_RENDEZVOUS_BIT)
402/** The bit number for VM_FF_EMT_RENDEZVOUS. */
403#define VM_FF_EMT_RENDEZVOUS_BIT 12
404
405/** PGM needs to allocate handy pages. */
406#define VM_FF_PGM_NEED_HANDY_PAGES RT_BIT_32(VM_FF_PGM_NEED_HANDY_PAGES_BIT)
407#define VM_FF_PGM_NEED_HANDY_PAGES_BIT 18
408/** PGM is out of memory.
409 * Abandon all loops and code paths which can be resumed and get up to the EM
410 * loops. */
411#define VM_FF_PGM_NO_MEMORY RT_BIT_32(VM_FF_PGM_NO_MEMORY_BIT)
412#define VM_FF_PGM_NO_MEMORY_BIT 19
413 /** PGM is about to perform a lightweight pool flush
414 * Guest SMP: all EMT threads should return to ring 3
415 */
416#define VM_FF_PGM_POOL_FLUSH_PENDING RT_BIT_32(VM_FF_PGM_POOL_FLUSH_PENDING_BIT)
417#define VM_FF_PGM_POOL_FLUSH_PENDING_BIT 20
418/** REM needs to be informed about handler changes. */
419#define VM_FF_REM_HANDLER_NOTIFY RT_BIT_32(VM_FF_REM_HANDLER_NOTIFY_BIT)
420/** The bit number for VM_FF_REM_HANDLER_NOTIFY. */
421#define VM_FF_REM_HANDLER_NOTIFY_BIT 29
422/** Suspend the VM - debug only. */
423#define VM_FF_DEBUG_SUSPEND RT_BIT_32(VM_FF_DEBUG_SUSPEND_BIT)
424#define VM_FF_DEBUG_SUSPEND_BIT 31
425
426
427/** This action forces the VM to check any pending interrupts on the APIC. */
428#define VMCPU_FF_INTERRUPT_APIC RT_BIT_64(VMCPU_FF_INTERRUPT_APIC_BIT)
429#define VMCPU_FF_INTERRUPT_APIC_BIT 0
430/** This action forces the VM to check any pending interrups on the PIC. */
431#define VMCPU_FF_INTERRUPT_PIC RT_BIT_64(VMCPU_FF_INTERRUPT_PIC_BIT)
432#define VMCPU_FF_INTERRUPT_PIC_BIT 1
433/** This action forces the VM to schedule and run pending timer (TM).
434 * @remarks Don't move - PATM compatibility. */
435#define VMCPU_FF_TIMER RT_BIT_64(VMCPU_FF_TIMER_BIT)
436#define VMCPU_FF_TIMER_BIT 2
437/** This action forces the VM to check any pending NMIs. */
438#define VMCPU_FF_INTERRUPT_NMI RT_BIT_64(VMCPU_FF_INTERRUPT_NMI_BIT)
439#define VMCPU_FF_INTERRUPT_NMI_BIT 3
440/** This action forces the VM to check any pending SMIs. */
441#define VMCPU_FF_INTERRUPT_SMI RT_BIT_64(VMCPU_FF_INTERRUPT_SMI_BIT)
442#define VMCPU_FF_INTERRUPT_SMI_BIT 4
443/** PDM critical section unlocking is pending, process promptly upon return to R3. */
444#define VMCPU_FF_PDM_CRITSECT RT_BIT_64(VMCPU_FF_PDM_CRITSECT_BIT)
445#define VMCPU_FF_PDM_CRITSECT_BIT 5
446/** Special EM internal force flag that is used by EMUnhaltAndWakeUp() to force
447 * the virtual CPU out of the next (/current) halted state. It is not processed
448 * nor cleared by emR3ForcedActions (similar to VMCPU_FF_BLOCK_NMIS), instead it
449 * is cleared the next time EM leaves the HALTED state. */
450#define VMCPU_FF_UNHALT RT_BIT_64(VMCPU_FF_UNHALT_BIT)
451#define VMCPU_FF_UNHALT_BIT 6
452/** Pending IEM action (mask). */
453#define VMCPU_FF_IEM RT_BIT_64(VMCPU_FF_IEM_BIT)
454/** Pending IEM action (bit number). */
455#define VMCPU_FF_IEM_BIT 7
456/** Pending APIC action (bit number). */
457#define VMCPU_FF_UPDATE_APIC_BIT 8
458/** This action forces the VM to update APIC's asynchronously arrived
459 * interrupts as pending interrupts. */
460#define VMCPU_FF_UPDATE_APIC RT_BIT_64(VMCPU_FF_UPDATE_APIC_BIT)
461/** This action forces the VM to service pending requests from other
462 * thread or requests which must be executed in another context. */
463#define VMCPU_FF_REQUEST RT_BIT_64(VMCPU_FF_REQUEST_BIT)
464#define VMCPU_FF_REQUEST_BIT 9
465/** Pending DBGF event (alternative to passing VINF_EM_DBG_EVENT around). */
466#define VMCPU_FF_DBGF RT_BIT_64(VMCPU_FF_DBGF_BIT)
467/** The bit number for VMCPU_FF_DBGF. */
468#define VMCPU_FF_DBGF_BIT 10
469/** This action forces the VM to service any pending updates to CR3 (used only
470 * by HM). */
471/** Hardware virtualized nested-guest interrupt pending. */
472#define VMCPU_FF_INTERRUPT_NESTED_GUEST RT_BIT_64(VMCPU_FF_INTERRUPT_NESTED_GUEST_BIT)
473#define VMCPU_FF_INTERRUPT_NESTED_GUEST_BIT 11
474#define VMCPU_FF_HM_UPDATE_CR3 RT_BIT_64(VMCPU_FF_HM_UPDATE_CR3_BIT)
475#define VMCPU_FF_HM_UPDATE_CR3_BIT 12
476/** This action forces the VM to service any pending updates to PAE PDPEs (used
477 * only by HM). */
478#define VMCPU_FF_HM_UPDATE_PAE_PDPES RT_BIT_64(VMCPU_FF_HM_UPDATE_PAE_PDPES_BIT)
479#define VMCPU_FF_HM_UPDATE_PAE_PDPES_BIT 13
480/** This action forces the VM to resync the page tables before going
481 * back to execute guest code. (GLOBAL FLUSH) */
482#define VMCPU_FF_PGM_SYNC_CR3 RT_BIT_64(VMCPU_FF_PGM_SYNC_CR3_BIT)
483#define VMCPU_FF_PGM_SYNC_CR3_BIT 16
484/** Same as VM_FF_PGM_SYNC_CR3 except that global pages can be skipped.
485 * (NON-GLOBAL FLUSH) */
486#define VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL RT_BIT_64(VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL_BIT)
487#define VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL_BIT 17
488/** Check for pending TLB shootdown actions (deprecated)
489 * Reserved for furture HM re-use if necessary / safe.
490 * Consumer: HM */
491#define VMCPU_FF_TLB_SHOOTDOWN_UNUSED RT_BIT_64(VMCPU_FF_TLB_SHOOTDOWN_UNUSED_BIT)
492#define VMCPU_FF_TLB_SHOOTDOWN_UNUSED_BIT 18
493/** Check for pending TLB flush action.
494 * Consumer: HM
495 * @todo rename to VMCPU_FF_HM_TLB_FLUSH */
496#define VMCPU_FF_TLB_FLUSH RT_BIT_64(VMCPU_FF_TLB_FLUSH_BIT)
497/** The bit number for VMCPU_FF_TLB_FLUSH. */
498#define VMCPU_FF_TLB_FLUSH_BIT 19
499/* 20 used to be VMCPU_FF_TRPM_SYNC_IDT (raw-mode only). */
500/* 21 used to be VMCPU_FF_SELM_SYNC_TSS (raw-mode only). */
501/* 22 used to be VMCPU_FF_SELM_SYNC_GDT (raw-mode only). */
502/* 23 used to be VMCPU_FF_SELM_SYNC_LDT (raw-mode only). */
503/** Inhibit interrupts pending. See EMGetInhibitInterruptsPC(). */
504#define VMCPU_FF_INHIBIT_INTERRUPTS RT_BIT_64(VMCPU_FF_INHIBIT_INTERRUPTS_BIT)
505#define VMCPU_FF_INHIBIT_INTERRUPTS_BIT 24
506/** Block injection of non-maskable interrupts to the guest. */
507#define VMCPU_FF_BLOCK_NMIS RT_BIT_64(VMCPU_FF_BLOCK_NMIS_BIT)
508#define VMCPU_FF_BLOCK_NMIS_BIT 25
509/** Force return to Ring-3. */
510#define VMCPU_FF_TO_R3 RT_BIT_64(VMCPU_FF_TO_R3_BIT)
511#define VMCPU_FF_TO_R3_BIT 28
512/** Force return to ring-3 to service pending I/O or MMIO write.
513 * This is a backup for mechanism VINF_IOM_R3_IOPORT_COMMIT_WRITE and
514 * VINF_IOM_R3_MMIO_COMMIT_WRITE, allowing VINF_EM_DBG_BREAKPOINT and similar
515 * status codes to be propagated at the same time without loss. */
516#define VMCPU_FF_IOM RT_BIT_64(VMCPU_FF_IOM_BIT)
517#define VMCPU_FF_IOM_BIT 29
518/* 30 used to be VMCPU_FF_CPUM */
519/** VMX-preemption timer in effect. */
520#define VMCPU_FF_VMX_PREEMPT_TIMER RT_BIT_64(VMCPU_FF_VMX_PREEMPT_TIMER_BIT)
521#define VMCPU_FF_VMX_PREEMPT_TIMER_BIT 31
522/** Pending MTF (Monitor Trap Flag) event. */
523#define VMCPU_FF_VMX_MTF RT_BIT_64(VMCPU_FF_VMX_MTF_BIT)
524#define VMCPU_FF_VMX_MTF_BIT 32
525/** VMX APIC-write emulation pending. */
526#define VMCPU_FF_VMX_APIC_WRITE RT_BIT_64(VMCPU_FF_VMX_APIC_WRITE_BIT)
527#define VMCPU_FF_VMX_APIC_WRITE_BIT 33
528/** VMX interrupt-window event pending. */
529#define VMCPU_FF_VMX_INT_WINDOW RT_BIT_64(VMCPU_FF_VMX_INT_WINDOW_BIT)
530#define VMCPU_FF_VMX_INT_WINDOW_BIT 34
531/** VMX NMI-window event pending. */
532#define VMCPU_FF_VMX_NMI_WINDOW RT_BIT_64(VMCPU_FF_VMX_NMI_WINDOW_BIT)
533#define VMCPU_FF_VMX_NMI_WINDOW_BIT 35
534
535
536/** Externally VM forced actions. Used to quit the idle/wait loop. */
537#define VM_FF_EXTERNAL_SUSPENDED_MASK ( VM_FF_CHECK_VM_STATE | VM_FF_DBGF | VM_FF_REQUEST | VM_FF_EMT_RENDEZVOUS )
538/** Externally VMCPU forced actions. Used to quit the idle/wait loop. */
539#define VMCPU_FF_EXTERNAL_SUSPENDED_MASK ( VMCPU_FF_REQUEST | VMCPU_FF_DBGF )
540
541/** Externally forced VM actions. Used to quit the idle/wait loop. */
542#define VM_FF_EXTERNAL_HALTED_MASK ( VM_FF_CHECK_VM_STATE | VM_FF_DBGF | VM_FF_REQUEST \
543 | VM_FF_PDM_QUEUES | VM_FF_PDM_DMA | VM_FF_EMT_RENDEZVOUS )
544/** Externally forced VMCPU actions. Used to quit the idle/wait loop. */
545#define VMCPU_FF_EXTERNAL_HALTED_MASK ( VMCPU_FF_UPDATE_APIC | VMCPU_FF_INTERRUPT_APIC | VMCPU_FF_INTERRUPT_PIC \
546 | VMCPU_FF_REQUEST | VMCPU_FF_INTERRUPT_NMI | VMCPU_FF_INTERRUPT_SMI \
547 | VMCPU_FF_UNHALT | VMCPU_FF_TIMER | VMCPU_FF_DBGF \
548 | VMCPU_FF_INTERRUPT_NESTED_GUEST)
549
550/** High priority VM pre-execution actions. */
551#define VM_FF_HIGH_PRIORITY_PRE_MASK ( VM_FF_CHECK_VM_STATE | VM_FF_DBGF | VM_FF_TM_VIRTUAL_SYNC \
552 | VM_FF_DEBUG_SUSPEND | VM_FF_PGM_NEED_HANDY_PAGES | VM_FF_PGM_NO_MEMORY \
553 | VM_FF_EMT_RENDEZVOUS )
554/** High priority VMCPU pre-execution actions. */
555#define VMCPU_FF_HIGH_PRIORITY_PRE_MASK ( VMCPU_FF_TIMER | VMCPU_FF_INTERRUPT_APIC | VMCPU_FF_INTERRUPT_PIC \
556 | VMCPU_FF_UPDATE_APIC | VMCPU_FF_INHIBIT_INTERRUPTS | VMCPU_FF_DBGF \
557 | VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL \
558 | VMCPU_FF_INTERRUPT_NESTED_GUEST | VMCPU_FF_VMX_MTF | VMCPU_FF_VMX_APIC_WRITE \
559 | VMCPU_FF_VMX_PREEMPT_TIMER | VMCPU_FF_VMX_NMI_WINDOW | VMCPU_FF_VMX_INT_WINDOW )
560
561/** High priority VM pre raw-mode execution mask. */
562#define VM_FF_HIGH_PRIORITY_PRE_RAW_MASK ( VM_FF_PGM_NEED_HANDY_PAGES | VM_FF_PGM_NO_MEMORY )
563/** High priority VMCPU pre raw-mode execution mask. */
564#define VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK ( VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL \
565 | VMCPU_FF_INHIBIT_INTERRUPTS )
566
567/** High priority post-execution actions. */
568#define VM_FF_HIGH_PRIORITY_POST_MASK ( VM_FF_PGM_NO_MEMORY )
569/** High priority post-execution actions. */
570#define VMCPU_FF_HIGH_PRIORITY_POST_MASK ( VMCPU_FF_PDM_CRITSECT \
571 | VMCPU_FF_HM_UPDATE_CR3 | VMCPU_FF_HM_UPDATE_PAE_PDPES \
572 | VMCPU_FF_IEM | VMCPU_FF_IOM )
573
574/** Normal priority VM post-execution actions. */
575#define VM_FF_NORMAL_PRIORITY_POST_MASK ( VM_FF_CHECK_VM_STATE | VM_FF_DBGF | VM_FF_RESET \
576 | VM_FF_PGM_NO_MEMORY | VM_FF_EMT_RENDEZVOUS)
577/** Normal priority VMCPU post-execution actions. */
578#define VMCPU_FF_NORMAL_PRIORITY_POST_MASK ( VMCPU_FF_DBGF )
579
580/** Normal priority VM actions. */
581#define VM_FF_NORMAL_PRIORITY_MASK ( VM_FF_REQUEST | VM_FF_PDM_QUEUES | VM_FF_PDM_DMA \
582 | VM_FF_REM_HANDLER_NOTIFY | VM_FF_EMT_RENDEZVOUS)
583/** Normal priority VMCPU actions. */
584#define VMCPU_FF_NORMAL_PRIORITY_MASK ( VMCPU_FF_REQUEST )
585
586/** Flags to clear before resuming guest execution. */
587#define VMCPU_FF_RESUME_GUEST_MASK ( VMCPU_FF_TO_R3 )
588
589
590/** VM flags that cause the REP[|NE|E] STRINS loops to yield immediately. */
591#define VM_FF_HIGH_PRIORITY_POST_REPSTR_MASK ( VM_FF_TM_VIRTUAL_SYNC | VM_FF_PGM_NEED_HANDY_PAGES | VM_FF_PGM_NO_MEMORY \
592 | VM_FF_EMT_RENDEZVOUS | VM_FF_PGM_POOL_FLUSH_PENDING | VM_FF_RESET)
593/** VM flags that cause the REP[|NE|E] STRINS loops to yield. */
594#define VM_FF_YIELD_REPSTR_MASK ( VM_FF_HIGH_PRIORITY_POST_REPSTR_MASK \
595 | VM_FF_PDM_QUEUES | VM_FF_PDM_DMA | VM_FF_DBGF | VM_FF_DEBUG_SUSPEND )
596/** VMCPU flags that cause the REP[|NE|E] STRINS loops to yield immediately. */
597#ifdef IN_RING3
598# define VMCPU_FF_HIGH_PRIORITY_POST_REPSTR_MASK ( VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL | VMCPU_FF_DBGF \
599 | VMCPU_FF_VMX_MTF )
600#else
601# define VMCPU_FF_HIGH_PRIORITY_POST_REPSTR_MASK ( VMCPU_FF_TO_R3 | VMCPU_FF_IEM | VMCPU_FF_IOM | VMCPU_FF_PGM_SYNC_CR3 \
602 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL | VMCPU_FF_DBGF | VMCPU_FF_VMX_MTF )
603#endif
604/** VMCPU flags that cause the REP[|NE|E] STRINS loops to yield, interrupts
605 * enabled. */
606#define VMCPU_FF_YIELD_REPSTR_MASK ( VMCPU_FF_HIGH_PRIORITY_POST_REPSTR_MASK \
607 | VMCPU_FF_INTERRUPT_APIC | VMCPU_FF_UPDATE_APIC | VMCPU_FF_INTERRUPT_PIC \
608 | VMCPU_FF_INTERRUPT_NMI | VMCPU_FF_INTERRUPT_SMI | VMCPU_FF_PDM_CRITSECT \
609 | VMCPU_FF_TIMER | VMCPU_FF_REQUEST \
610 | VMCPU_FF_INTERRUPT_NESTED_GUEST )
611/** VMCPU flags that cause the REP[|NE|E] STRINS loops to yield, interrupts
612 * disabled. */
613#define VMCPU_FF_YIELD_REPSTR_NOINT_MASK ( VMCPU_FF_YIELD_REPSTR_MASK \
614 & ~( VMCPU_FF_INTERRUPT_APIC | VMCPU_FF_UPDATE_APIC | VMCPU_FF_INTERRUPT_PIC \
615 | VMCPU_FF_INTERRUPT_NESTED_GUEST) )
616
617/** VM Flags that cause the HM loops to go back to ring-3. */
618#define VM_FF_HM_TO_R3_MASK ( VM_FF_TM_VIRTUAL_SYNC | VM_FF_PGM_NEED_HANDY_PAGES | VM_FF_PGM_NO_MEMORY \
619 | VM_FF_PDM_QUEUES | VM_FF_EMT_RENDEZVOUS)
620/** VMCPU Flags that cause the HM loops to go back to ring-3. */
621#define VMCPU_FF_HM_TO_R3_MASK ( VMCPU_FF_TO_R3 | VMCPU_FF_TIMER | VMCPU_FF_PDM_CRITSECT \
622 | VMCPU_FF_IEM | VMCPU_FF_IOM)
623
624/** High priority ring-0 VM pre HM-mode execution mask. */
625#define VM_FF_HP_R0_PRE_HM_MASK (VM_FF_HM_TO_R3_MASK | VM_FF_REQUEST | VM_FF_PGM_POOL_FLUSH_PENDING | VM_FF_PDM_DMA)
626/** High priority ring-0 VMCPU pre HM-mode execution mask. */
627#define VMCPU_FF_HP_R0_PRE_HM_MASK ( VMCPU_FF_HM_TO_R3_MASK | VMCPU_FF_PGM_SYNC_CR3 \
628 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL | VMCPU_FF_REQUEST)
629/** High priority ring-0 VM pre HM-mode execution mask, single stepping. */
630#define VM_FF_HP_R0_PRE_HM_STEP_MASK (VM_FF_HP_R0_PRE_HM_MASK & ~( VM_FF_TM_VIRTUAL_SYNC | VM_FF_PDM_QUEUES \
631 | VM_FF_EMT_RENDEZVOUS | VM_FF_REQUEST \
632 | VM_FF_PDM_DMA) )
633/** High priority ring-0 VMCPU pre HM-mode execution mask, single stepping. */
634#define VMCPU_FF_HP_R0_PRE_HM_STEP_MASK (VMCPU_FF_HP_R0_PRE_HM_MASK & ~( VMCPU_FF_TO_R3 | VMCPU_FF_TIMER \
635 | VMCPU_FF_PDM_CRITSECT | VMCPU_FF_REQUEST) )
636
637/** All the forced VM flags. */
638#define VM_FF_ALL_MASK (UINT32_MAX)
639/** All the forced VMCPU flags. */
640#define VMCPU_FF_ALL_MASK (UINT32_MAX)
641
642/** All the forced VM flags except those related to raw-mode and hardware
643 * assisted execution. */
644#define VM_FF_ALL_REM_MASK (~(VM_FF_HIGH_PRIORITY_PRE_RAW_MASK) | VM_FF_PGM_NEED_HANDY_PAGES | VM_FF_PGM_NO_MEMORY)
645/** All the forced VMCPU flags except those related to raw-mode and hardware
646 * assisted execution. */
647#define VMCPU_FF_ALL_REM_MASK (~(VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK | VMCPU_FF_PDM_CRITSECT | VMCPU_FF_TLB_FLUSH))
648/** @} */
649
650/** @def VM_FF_SET
651 * Sets a single force action flag.
652 *
653 * @param pVM The cross context VM structure.
654 * @param fFlag The flag to set.
655 */
656#define VM_FF_SET(pVM, fFlag) do { \
657 AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
658 AssertCompile((fFlag) == RT_BIT_32(fFlag##_BIT)); \
659 ASMAtomicOrU32(&(pVM)->fGlobalForcedActions, (fFlag)); \
660 } while (0)
661
662/** @def VMCPU_FF_SET
663 * Sets a single force action flag for the given VCPU.
664 *
665 * @param pVCpu The cross context virtual CPU structure.
666 * @param fFlag The flag to set.
667 * @sa VMCPU_FF_SET_MASK
668 */
669#ifdef VMCPU_WITH_64_BIT_FFS
670# define VMCPU_FF_SET(pVCpu, fFlag) do { \
671 AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
672 AssertCompile((fFlag) == RT_BIT_64(fFlag##_BIT)); \
673 ASMAtomicBitSet(&(pVCpu)->fLocalForcedActions, fFlag##_BIT); \
674 } while (0)
675#else
676# define VMCPU_FF_SET(pVCpu, fFlag) do { \
677 AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
678 AssertCompile((fFlag) == RT_BIT_32(fFlag##_BIT)); \
679 ASMAtomicOrU32(&(pVCpu)->fLocalForcedActions, (fFlag)); \
680 } while (0)
681#endif
682
683/** @def VMCPU_FF_SET_MASK
684 * Sets a two or more force action flag for the given VCPU.
685 *
686 * @param pVCpu The cross context virtual CPU structure.
687 * @param fFlags The flags to set.
688 * @sa VMCPU_FF_SET
689 */
690#ifdef VMCPU_WITH_64_BIT_FFS
691# if ARCH_BITS > 32
692# define VMCPU_FF_SET_MASK(pVCpu, fFlags) \
693 do { ASMAtomicOrU64(&pVCpu->fLocalForcedActions, (fFlags)); } while (0)
694# else
695# define VMCPU_FF_SET_MASK(pVCpu, fFlags) do { \
696 if (!((fFlags) >> 32)) ASMAtomicOrU32((uint32_t volatile *)&pVCpu->fLocalForcedActions, (uint32_t)(fFlags)); \
697 else ASMAtomicOrU64(&pVCpu->fLocalForcedActions, (fFlags)); \
698 } while (0)
699# endif
700#else
701# define VMCPU_FF_SET_MASK(pVCpu, fFlags) \
702 do { ASMAtomicOrU32(&pVCpu->fLocalForcedActions, (fFlags)); } while (0)
703#endif
704
705/** @def VM_FF_CLEAR
706 * Clears a single force action flag.
707 *
708 * @param pVM The cross context VM structure.
709 * @param fFlag The flag to clear.
710 */
711#define VM_FF_CLEAR(pVM, fFlag) do { \
712 AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
713 AssertCompile((fFlag) == RT_BIT_32(fFlag##_BIT)); \
714 ASMAtomicAndU32(&(pVM)->fGlobalForcedActions, ~(fFlag)); \
715 } while (0)
716
717/** @def VMCPU_FF_CLEAR
718 * Clears a single force action flag for the given VCPU.
719 *
720 * @param pVCpu The cross context virtual CPU structure.
721 * @param fFlag The flag to clear.
722 */
723#ifdef VMCPU_WITH_64_BIT_FFS
724# define VMCPU_FF_CLEAR(pVCpu, fFlag) do { \
725 AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
726 AssertCompile((fFlag) == RT_BIT_64(fFlag##_BIT)); \
727 ASMAtomicBitClear(&(pVCpu)->fLocalForcedActions, fFlag##_BIT); \
728 } while (0)
729#else
730# define VMCPU_FF_CLEAR(pVCpu, fFlag) do { \
731 AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
732 AssertCompile((fFlag) == RT_BIT_32(fFlag##_BIT)); \
733 ASMAtomicAndU32(&(pVCpu)->fLocalForcedActions, ~(fFlag)); \
734 } while (0)
735#endif
736
737/** @def VMCPU_FF_CLEAR_MASK
738 * Clears two or more force action flags for the given VCPU.
739 *
740 * @param pVCpu The cross context virtual CPU structure.
741 * @param fFlags The flags to clear.
742 */
743#ifdef VMCPU_WITH_64_BIT_FFS
744# if ARCH_BITS > 32
745# define VMCPU_FF_CLEAR_MASK(pVCpu, fFlags) \
746 do { ASMAtomicAndU64(&(pVCpu)->fLocalForcedActions, ~(fFlags)); } while (0)
747# else
748# define VMCPU_FF_CLEAR_MASK(pVCpu, fFlags) do { \
749 if (!((fFlags) >> 32)) ASMAtomicAndU32((uint32_t volatile *)&(pVCpu)->fLocalForcedActions, ~(uint32_t)(fFlags)); \
750 else ASMAtomicAndU64(&(pVCpu)->fLocalForcedActions, ~(fFlags)); \
751 } while (0)
752# endif
753#else
754# define VMCPU_FF_CLEAR_MASK(pVCpu, fFlags) \
755 do { ASMAtomicAndU32(&(pVCpu)->fLocalForcedActions, ~(fFlags)); } while (0)
756#endif
757
758/** @def VM_FF_IS_SET
759 * Checks if single a force action flag is set.
760 *
761 * @param pVM The cross context VM structure.
762 * @param fFlag The flag to check.
763 * @sa VM_FF_IS_ANY_SET
764 */
765#if !defined(VBOX_STRICT) || !defined(RT_COMPILER_SUPPORTS_LAMBDA)
766# define VM_FF_IS_SET(pVM, fFlag) RT_BOOL((pVM)->fGlobalForcedActions & (fFlag))
767#else
768# define VM_FF_IS_SET(pVM, fFlag) \
769 ([](PVM a_pVM) -> bool \
770 { \
771 AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
772 AssertCompile((fFlag) == RT_BIT_32(fFlag##_BIT)); \
773 return RT_BOOL(a_pVM->fGlobalForcedActions & (fFlag)); \
774 }(pVM))
775#endif
776
777/** @def VMCPU_FF_IS_SET
778 * Checks if a single force action flag is set for the given VCPU.
779 *
780 * @param pVCpu The cross context virtual CPU structure.
781 * @param fFlag The flag to check.
782 * @sa VMCPU_FF_IS_ANY_SET
783 */
784#if !defined(VBOX_STRICT) || !defined(RT_COMPILER_SUPPORTS_LAMBDA)
785# define VMCPU_FF_IS_SET(pVCpu, fFlag) RT_BOOL((pVCpu)->fLocalForcedActions & (fFlag))
786#else
787# define VMCPU_FF_IS_SET(pVCpu, fFlag) \
788 ([](PCVMCPU a_pVCpu) -> bool \
789 { \
790 AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
791 AssertCompile((fFlag) == RT_BIT_64(fFlag##_BIT)); \
792 return RT_BOOL(a_pVCpu->fLocalForcedActions & (fFlag)); \
793 }(pVCpu))
794#endif
795
796/** @def VM_FF_IS_ANY_SET
797 * Checks if one or more force action in the specified set is pending.
798 *
799 * @param pVM The cross context VM structure.
800 * @param fFlags The flags to check for.
801 * @sa VM_FF_IS_SET
802 */
803#define VM_FF_IS_ANY_SET(pVM, fFlags) RT_BOOL((pVM)->fGlobalForcedActions & (fFlags))
804
805/** @def VMCPU_FF_IS_ANY_SET
806 * Checks if two or more force action flags in the specified set is set for the given VCPU.
807 *
808 * @param pVCpu The cross context virtual CPU structure.
809 * @param fFlags The flags to check for.
810 * @sa VMCPU_FF_IS_SET
811 */
812#define VMCPU_FF_IS_ANY_SET(pVCpu, fFlags) RT_BOOL((pVCpu)->fLocalForcedActions & (fFlags))
813
814/** @def VM_FF_TEST_AND_CLEAR
815 * Checks if one (!) force action in the specified set is pending and clears it atomically
816 *
817 * @returns true if the bit was set.
818 * @returns false if the bit was clear.
819 * @param pVM The cross context VM structure.
820 * @param fFlag Flag constant to check and clear (_BIT is appended).
821 */
822#define VM_FF_TEST_AND_CLEAR(pVM, fFlag) (ASMAtomicBitTestAndClear(&(pVM)->fGlobalForcedActions, fFlag##_BIT))
823
824/** @def VMCPU_FF_TEST_AND_CLEAR
825 * Checks if one (!) force action in the specified set is pending and clears it atomically
826 *
827 * @returns true if the bit was set.
828 * @returns false if the bit was clear.
829 * @param pVCpu The cross context virtual CPU structure.
830 * @param fFlag Flag constant to check and clear (_BIT is appended).
831 */
832#define VMCPU_FF_TEST_AND_CLEAR(pVCpu, fFlag) (ASMAtomicBitTestAndClear(&(pVCpu)->fLocalForcedActions, fFlag##_BIT))
833
834/** @def VM_FF_IS_PENDING_EXCEPT
835 * Checks if one or more force action in the specified set is pending while one
836 * or more other ones are not.
837 *
838 * @param pVM The cross context VM structure.
839 * @param fFlags The flags to check for.
840 * @param fExcpt The flags that should not be set.
841 */
842#define VM_FF_IS_PENDING_EXCEPT(pVM, fFlags, fExcpt) \
843 ( ((pVM)->fGlobalForcedActions & (fFlags)) && !((pVM)->fGlobalForcedActions & (fExcpt)) )
844
845/** @def VM_IS_EMT
846 * Checks if the current thread is the emulation thread (EMT).
847 *
848 * @remark The ring-0 variation will need attention if we expand the ring-0
849 * code to let threads other than EMT mess around with the VM.
850 */
851#ifdef IN_RC
852# define VM_IS_EMT(pVM) true
853#else
854# define VM_IS_EMT(pVM) (VMMGetCpu(pVM) != NULL)
855#endif
856
857/** @def VMCPU_IS_EMT
858 * Checks if the current thread is the emulation thread (EMT) for the specified
859 * virtual CPU.
860 */
861#ifdef IN_RC
862# define VMCPU_IS_EMT(pVCpu) true
863#else
864# define VMCPU_IS_EMT(pVCpu) ((pVCpu) && ((pVCpu) == VMMGetCpu((pVCpu)->CTX_SUFF(pVM))))
865#endif
866
867/** @def VM_ASSERT_EMT
868 * Asserts that the current thread IS the emulation thread (EMT).
869 */
870#ifdef IN_RC
871# define VM_ASSERT_EMT(pVM) Assert(VM_IS_EMT(pVM))
872#elif defined(IN_RING0)
873# define VM_ASSERT_EMT(pVM) Assert(VM_IS_EMT(pVM))
874#else
875# define VM_ASSERT_EMT(pVM) \
876 AssertMsg(VM_IS_EMT(pVM), \
877 ("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd\n", RTThreadNativeSelf(), VMR3GetVMCPUNativeThread(pVM)))
878#endif
879
880/** @def VMCPU_ASSERT_EMT
881 * Asserts that the current thread IS the emulation thread (EMT) of the
882 * specified virtual CPU.
883 */
884#ifdef IN_RC
885# define VMCPU_ASSERT_EMT(pVCpu) Assert(VMCPU_IS_EMT(pVCpu))
886#elif defined(IN_RING0)
887# define VMCPU_ASSERT_EMT(pVCpu) AssertMsg(VMCPU_IS_EMT(pVCpu), \
888 ("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd idCpu=%u\n", \
889 RTThreadNativeSelf(), (pVCpu) ? (pVCpu)->hNativeThreadR0 : 0, \
890 (pVCpu) ? (pVCpu)->idCpu : 0))
891#else
892# define VMCPU_ASSERT_EMT(pVCpu) AssertMsg(VMCPU_IS_EMT(pVCpu), \
893 ("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd idCpu=%#x\n", \
894 RTThreadNativeSelf(), (pVCpu)->hNativeThread, (pVCpu)->idCpu))
895#endif
896
897/** @def VM_ASSERT_EMT_RETURN
898 * Asserts that the current thread IS the emulation thread (EMT) and returns if it isn't.
899 */
900#ifdef IN_RC
901# define VM_ASSERT_EMT_RETURN(pVM, rc) AssertReturn(VM_IS_EMT(pVM), (rc))
902#elif defined(IN_RING0)
903# define VM_ASSERT_EMT_RETURN(pVM, rc) AssertReturn(VM_IS_EMT(pVM), (rc))
904#else
905# define VM_ASSERT_EMT_RETURN(pVM, rc) \
906 AssertMsgReturn(VM_IS_EMT(pVM), \
907 ("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd\n", RTThreadNativeSelf(), VMR3GetVMCPUNativeThread(pVM)), \
908 (rc))
909#endif
910
911/** @def VMCPU_ASSERT_EMT_RETURN
912 * Asserts that the current thread IS the emulation thread (EMT) and returns if it isn't.
913 */
914#ifdef IN_RC
915# define VMCPU_ASSERT_EMT_RETURN(pVCpu, rc) AssertReturn(VMCPU_IS_EMT(pVCpu), (rc))
916#elif defined(IN_RING0)
917# define VMCPU_ASSERT_EMT_RETURN(pVCpu, rc) AssertReturn(VMCPU_IS_EMT(pVCpu), (rc))
918#else
919# define VMCPU_ASSERT_EMT_RETURN(pVCpu, rc) \
920 AssertMsgReturn(VMCPU_IS_EMT(pVCpu), \
921 ("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd idCpu=%#x\n", \
922 RTThreadNativeSelf(), (pVCpu)->hNativeThread, (pVCpu)->idCpu), \
923 (rc))
924#endif
925
926/** @def VMCPU_ASSERT_EMT_OR_GURU
927 * Asserts that the current thread IS the emulation thread (EMT) of the
928 * specified virtual CPU.
929 */
930#if defined(IN_RC) || defined(IN_RING0)
931# define VMCPU_ASSERT_EMT_OR_GURU(pVCpu) Assert( VMCPU_IS_EMT(pVCpu) \
932 || pVCpu->CTX_SUFF(pVM)->enmVMState == VMSTATE_GURU_MEDITATION \
933 || pVCpu->CTX_SUFF(pVM)->enmVMState == VMSTATE_GURU_MEDITATION_LS )
934#else
935# define VMCPU_ASSERT_EMT_OR_GURU(pVCpu) \
936 AssertMsg( VMCPU_IS_EMT(pVCpu) \
937 || pVCpu->CTX_SUFF(pVM)->enmVMState == VMSTATE_GURU_MEDITATION \
938 || pVCpu->CTX_SUFF(pVM)->enmVMState == VMSTATE_GURU_MEDITATION_LS, \
939 ("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd idCpu=%#x\n", \
940 RTThreadNativeSelf(), (pVCpu)->hNativeThread, (pVCpu)->idCpu))
941#endif
942
943/** @def VMCPU_ASSERT_EMT_OR_NOT_RUNNING
944 * Asserts that the current thread IS the emulation thread (EMT) of the
945 * specified virtual CPU or the VM is not running.
946 */
947#if defined(IN_RC) || defined(IN_RING0)
948# define VMCPU_ASSERT_EMT_OR_NOT_RUNNING(pVCpu) \
949 Assert( VMCPU_IS_EMT(pVCpu) \
950 || !VM_IS_RUNNING_FOR_ASSERTIONS_ONLY((pVCpu)->CTX_SUFF(pVM)) )
951#else
952# define VMCPU_ASSERT_EMT_OR_NOT_RUNNING(pVCpu) \
953 AssertMsg( VMCPU_IS_EMT(pVCpu) \
954 || !VM_IS_RUNNING_FOR_ASSERTIONS_ONLY((pVCpu)->CTX_SUFF(pVM)), \
955 ("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd idCpu=%#x\n", \
956 RTThreadNativeSelf(), (pVCpu)->hNativeThread, (pVCpu)->idCpu))
957#endif
958
959/** @def VMSTATE_IS_RUNNING
960 * Checks if the given state indicates a running VM.
961 */
962#define VMSTATE_IS_RUNNING(a_enmVMState) \
963 ( (enmVMState) == VMSTATE_RUNNING \
964 || (enmVMState) == VMSTATE_RUNNING_LS \
965 || (enmVMState) == VMSTATE_RUNNING_FT )
966
967/** @def VM_IS_RUNNING_FOR_ASSERTIONS_ONLY
968 * Checks if the VM is running.
969 * @note This is only for pure debug assertions. No AssertReturn or similar!
970 * @sa VMSTATE_IS_RUNNING
971 */
972#define VM_IS_RUNNING_FOR_ASSERTIONS_ONLY(pVM) \
973 ( (pVM)->enmVMState == VMSTATE_RUNNING \
974 || (pVM)->enmVMState == VMSTATE_RUNNING_LS \
975 || (pVM)->enmVMState == VMSTATE_RUNNING_FT )
976
977/** @def VM_ASSERT_IS_NOT_RUNNING
978 * Asserts that the VM is not running.
979 */
980#if defined(IN_RC) || defined(IN_RING0)
981#define VM_ASSERT_IS_NOT_RUNNING(pVM) Assert(!VM_IS_RUNNING_FOR_ASSERTIONS_ONLY(pVM))
982#else
983#define VM_ASSERT_IS_NOT_RUNNING(pVM) AssertMsg(!VM_IS_RUNNING_FOR_ASSERTIONS_ONLY(pVM), \
984 ("VM is running. enmVMState=%d\n", (pVM)->enmVMState))
985#endif
986
987/** @def VM_ASSERT_EMT0
988 * Asserts that the current thread IS emulation thread \#0 (EMT0).
989 */
990#define VM_ASSERT_EMT0(pVM) VMCPU_ASSERT_EMT(&(pVM)->aCpus[0])
991
992/** @def VM_ASSERT_EMT0_RETURN
993 * Asserts that the current thread IS emulation thread \#0 (EMT0) and returns if
994 * it isn't.
995 */
996#define VM_ASSERT_EMT0_RETURN(pVM, rc) VMCPU_ASSERT_EMT_RETURN(&(pVM)->aCpus[0], (rc))
997
998
999/**
1000 * Asserts that the current thread is NOT the emulation thread.
1001 */
1002#define VM_ASSERT_OTHER_THREAD(pVM) \
1003 AssertMsg(!VM_IS_EMT(pVM), ("Not other thread!!\n"))
1004
1005
1006/** @def VM_ASSERT_STATE
1007 * Asserts a certain VM state.
1008 */
1009#define VM_ASSERT_STATE(pVM, _enmState) \
1010 AssertMsg((pVM)->enmVMState == (_enmState), \
1011 ("state %s, expected %s\n", VMGetStateName((pVM)->enmVMState), VMGetStateName(_enmState)))
1012
1013/** @def VM_ASSERT_STATE_RETURN
1014 * Asserts a certain VM state and returns if it doesn't match.
1015 */
1016#define VM_ASSERT_STATE_RETURN(pVM, _enmState, rc) \
1017 AssertMsgReturn((pVM)->enmVMState == (_enmState), \
1018 ("state %s, expected %s\n", VMGetStateName((pVM)->enmVMState), VMGetStateName(_enmState)), \
1019 (rc))
1020
1021/** @def VM_IS_VALID_EXT
1022 * Asserts a the VM handle is valid for external access, i.e. not being destroy
1023 * or terminated. */
1024#define VM_IS_VALID_EXT(pVM) \
1025 ( RT_VALID_ALIGNED_PTR(pVM, PAGE_SIZE) \
1026 && ( (unsigned)(pVM)->enmVMState < (unsigned)VMSTATE_DESTROYING \
1027 || ( (unsigned)(pVM)->enmVMState == (unsigned)VMSTATE_DESTROYING \
1028 && VM_IS_EMT(pVM))) )
1029
1030/** @def VM_ASSERT_VALID_EXT_RETURN
1031 * Asserts a the VM handle is valid for external access, i.e. not being
1032 * destroy or terminated.
1033 */
1034#define VM_ASSERT_VALID_EXT_RETURN(pVM, rc) \
1035 AssertMsgReturn(VM_IS_VALID_EXT(pVM), \
1036 ("pVM=%p state %s\n", (pVM), RT_VALID_ALIGNED_PTR(pVM, PAGE_SIZE) \
1037 ? VMGetStateName(pVM->enmVMState) : ""), \
1038 (rc))
1039
1040/** @def VMCPU_ASSERT_VALID_EXT_RETURN
1041 * Asserts a the VMCPU handle is valid for external access, i.e. not being
1042 * destroy or terminated.
1043 */
1044#define VMCPU_ASSERT_VALID_EXT_RETURN(pVCpu, rc) \
1045 AssertMsgReturn( RT_VALID_ALIGNED_PTR(pVCpu, 64) \
1046 && RT_VALID_ALIGNED_PTR((pVCpu)->CTX_SUFF(pVM), PAGE_SIZE) \
1047 && (unsigned)(pVCpu)->CTX_SUFF(pVM)->enmVMState < (unsigned)VMSTATE_DESTROYING, \
1048 ("pVCpu=%p pVM=%p state %s\n", (pVCpu), RT_VALID_ALIGNED_PTR(pVCpu, 64) ? (pVCpu)->CTX_SUFF(pVM) : NULL, \
1049 RT_VALID_ALIGNED_PTR(pVCpu, 64) && RT_VALID_ALIGNED_PTR((pVCpu)->CTX_SUFF(pVM), PAGE_SIZE) \
1050 ? VMGetStateName((pVCpu)->pVMR3->enmVMState) : ""), \
1051 (rc))
1052
1053#endif /* !VBOX_FOR_DTRACE_LIB */
1054
1055
1056/**
1057 * Helper that HM and NEM uses for safely modifying VM::bMainExecutionEngine.
1058 *
1059 * ONLY HM and NEM MAY USE THIS!
1060 *
1061 * @param a_pVM The cross context VM structure.
1062 * @param a_bValue The new value.
1063 * @internal
1064 */
1065#define VM_SET_MAIN_EXECUTION_ENGINE(a_pVM, a_bValue) \
1066 do { \
1067 *const_cast<uint8_t *>(&(a_pVM)->bMainExecutionEngine) = (a_bValue); \
1068 ASMCompilerBarrier(); /* just to be on the safe side */ \
1069 } while (0)
1070
1071/**
1072 * Checks whether raw-mode is used.
1073 *
1074 * @retval true if either is used.
1075 * @retval false if software virtualization (raw-mode) is used.
1076 *
1077 * @param a_pVM The cross context VM structure.
1078 * @sa VM_IS_HM_OR_NEM_ENABLED, VM_IS_HM_ENABLED, VM_IS_NEM_ENABLED.
1079 * @internal
1080 */
1081#ifdef VBOX_WITH_RAW_MODE
1082# define VM_IS_RAW_MODE_ENABLED(a_pVM) ((a_pVM)->bMainExecutionEngine == VM_EXEC_ENGINE_RAW_MODE)
1083#else
1084# define VM_IS_RAW_MODE_ENABLED(a_pVM) (false)
1085#endif
1086
1087/**
1088 * Checks whether HM (VT-x/AMD-V) or NEM is being used by this VM.
1089 *
1090 * @retval true if either is used.
1091 * @retval false if software virtualization (raw-mode) is used.
1092 *
1093 * @param a_pVM The cross context VM structure.
1094 * @sa VM_IS_RAW_MODE_ENABLED, VM_IS_HM_ENABLED, VM_IS_NEM_ENABLED.
1095 * @internal
1096 */
1097#define VM_IS_HM_OR_NEM_ENABLED(a_pVM) ((a_pVM)->bMainExecutionEngine != VM_EXEC_ENGINE_RAW_MODE)
1098
1099/**
1100 * Checks whether HM is being used by this VM.
1101 *
1102 * @retval true if HM (VT-x/AMD-v) is used.
1103 * @retval false if not.
1104 *
1105 * @param a_pVM The cross context VM structure.
1106 * @sa VM_IS_NEM_ENABLED, VM_IS_RAW_MODE_ENABLED, VM_IS_HM_OR_NEM_ENABLED.
1107 * @internal
1108 */
1109#define VM_IS_HM_ENABLED(a_pVM) ((a_pVM)->bMainExecutionEngine == VM_EXEC_ENGINE_HW_VIRT)
1110
1111/**
1112 * Checks whether NEM is being used by this VM.
1113 *
1114 * @retval true if a native hypervisor API is used.
1115 * @retval false if not.
1116 *
1117 * @param a_pVM The cross context VM structure.
1118 * @sa VM_IS_HM_ENABLED, VM_IS_RAW_MODE_ENABLED, VM_IS_HM_OR_NEM_ENABLED.
1119 * @internal
1120 */
1121#define VM_IS_NEM_ENABLED(a_pVM) ((a_pVM)->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API)
1122
1123
1124/**
1125 * The cross context VM structure.
1126 *
1127 * It contains all the VM data which have to be available in all contexts.
1128 * Even if it contains all the data the idea is to use APIs not to modify all
1129 * the members all around the place. Therefore we make use of unions to hide
1130 * everything which isn't local to the current source module. This means we'll
1131 * have to pay a little bit of attention when adding new members to structures
1132 * in the unions and make sure to keep the padding sizes up to date.
1133 *
1134 * Run 'kmk run-struct-tests' (from src/VBox/VMM if you like) after updating!
1135 */
1136typedef struct VM
1137{
1138 /** The state of the VM.
1139 * This field is read only to everyone except the VM and EM. */
1140 VMSTATE volatile enmVMState;
1141 /** Forced action flags.
1142 * See the VM_FF_* \#defines. Updated atomically.
1143 */
1144 volatile uint32_t fGlobalForcedActions;
1145 /** Pointer to the array of page descriptors for the VM structure allocation. */
1146 R3PTRTYPE(PSUPPAGE) paVMPagesR3;
1147 /** Session handle. For use when calling SUPR0 APIs. */
1148 PSUPDRVSESSION pSession;
1149 /** Pointer to the ring-3 VM structure. */
1150 PUVM pUVM;
1151 /** Ring-3 Host Context VM Pointer. */
1152 R3PTRTYPE(struct VM *) pVMR3;
1153 /** Ring-0 Host Context VM Pointer. */
1154 R0PTRTYPE(struct VM *) pVMR0;
1155 /** Raw-mode Context VM Pointer. */
1156 RCPTRTYPE(struct VM *) pVMRC;
1157
1158 /** The GVM VM handle. Only the GVM should modify this field. */
1159 uint32_t hSelf;
1160 /** Number of virtual CPUs. */
1161 uint32_t cCpus;
1162 /** CPU excution cap (1-100) */
1163 uint32_t uCpuExecutionCap;
1164
1165#ifdef VBOX_BUGREF_9217
1166 /** Size of the VM structure. */
1167 uint32_t cbSelf;
1168 /** Size of the VMCPU structure. */
1169 uint32_t cbVCpu;
1170 /** Structure version number (TBD). */
1171 uint32_t uStructVersion;
1172#else
1173 /** Size of the VM structure including the VMCPU array. */
1174 uint32_t cbSelf;
1175 uint32_t uUnused0;
1176 uint32_t uUnused1;
1177#endif
1178
1179 /** @name Various items that are frequently accessed.
1180 * @{ */
1181 /** The main execution engine, VM_EXEC_ENGINE_XXX.
1182 * This is set early during vmR3InitRing3 by HM or NEM. */
1183 uint8_t const bMainExecutionEngine;
1184
1185 /** Hardware VM support is available and enabled.
1186 * Determined very early during init.
1187 * This is placed here for performance reasons.
1188 * @todo obsoleted by bMainExecutionEngine, eliminate. */
1189 bool fHMEnabled;
1190 /** Hardware VM support requires a minimal raw-mode context.
1191 * This is never set on 64-bit hosts, only 32-bit hosts requires it. */
1192 bool fHMNeedRawModeCtx;
1193
1194 /** Set when this VM is the master FT node.
1195 * @todo This doesn't need to be here, FTM should store it in it's own
1196 * structures instead. */
1197 bool fFaultTolerantMaster;
1198 /** Large page enabled flag.
1199 * @todo This doesn't need to be here, PGM should store it in it's own
1200 * structures instead. */
1201 bool fUseLargePages;
1202 /** @} */
1203
1204 /** Alignment padding. */
1205 uint8_t uPadding1[7];
1206
1207 /** @name Debugging
1208 * @{ */
1209 /** Ring-3 Host Context VM Pointer. */
1210 R3PTRTYPE(RTTRACEBUF) hTraceBufR3;
1211 /** Ring-0 Host Context VM Pointer. */
1212 R0PTRTYPE(RTTRACEBUF) hTraceBufR0;
1213 /** @} */
1214
1215 /** Padding - the unions must be aligned on a 64 bytes boundary. */
1216 uint8_t abAlignment3[24];
1217
1218 /** CPUM part. */
1219 union
1220 {
1221#ifdef VMM_INCLUDED_SRC_include_CPUMInternal_h
1222 struct CPUM s;
1223#endif
1224#ifdef VBOX_INCLUDED_vmm_cpum_h
1225 /** Read only info exposed about the host and guest CPUs. */
1226 struct
1227 {
1228 /** Padding for hidden fields. */
1229 uint8_t abHidden0[64];
1230 /** Host CPU feature information. */
1231 CPUMFEATURES HostFeatures;
1232 /** Guest CPU feature information. */
1233 CPUMFEATURES GuestFeatures;
1234 } const ro;
1235#endif
1236 uint8_t padding[1536]; /* multiple of 64 */
1237 } cpum;
1238
1239 /** VMM part. */
1240 union
1241 {
1242#ifdef VMM_INCLUDED_SRC_include_VMMInternal_h
1243 struct VMM s;
1244#endif
1245 uint8_t padding[1600]; /* multiple of 64 */
1246 } vmm;
1247
1248 /** PGM part. */
1249 union
1250 {
1251#ifdef VMM_INCLUDED_SRC_include_PGMInternal_h
1252 struct PGM s;
1253#endif
1254 uint8_t padding[4096*2+6080]; /* multiple of 64 */
1255 } pgm;
1256
1257 /** HM part. */
1258 union
1259 {
1260#ifdef VMM_INCLUDED_SRC_include_HMInternal_h
1261 struct HM s;
1262#endif
1263 uint8_t padding[5440]; /* multiple of 64 */
1264 } hm;
1265
1266 /** TRPM part. */
1267 union
1268 {
1269#ifdef VMM_INCLUDED_SRC_include_TRPMInternal_h
1270 struct TRPM s;
1271#endif
1272 uint8_t padding[5248]; /* multiple of 64 */
1273 } trpm;
1274
1275 /** SELM part. */
1276 union
1277 {
1278#ifdef VMM_INCLUDED_SRC_include_SELMInternal_h
1279 struct SELM s;
1280#endif
1281 uint8_t padding[768]; /* multiple of 64 */
1282 } selm;
1283
1284 /** MM part. */
1285 union
1286 {
1287#ifdef VMM_INCLUDED_SRC_include_MMInternal_h
1288 struct MM s;
1289#endif
1290 uint8_t padding[192]; /* multiple of 64 */
1291 } mm;
1292
1293 /** PDM part. */
1294 union
1295 {
1296#ifdef VMM_INCLUDED_SRC_include_PDMInternal_h
1297 struct PDM s;
1298#endif
1299 uint8_t padding[1920]; /* multiple of 64 */
1300 } pdm;
1301
1302 /** IOM part. */
1303 union
1304 {
1305#ifdef VMM_INCLUDED_SRC_include_IOMInternal_h
1306 struct IOM s;
1307#endif
1308 uint8_t padding[896]; /* multiple of 64 */
1309 } iom;
1310
1311 /** EM part. */
1312 union
1313 {
1314#ifdef VMM_INCLUDED_SRC_include_EMInternal_h
1315 struct EM s;
1316#endif
1317 uint8_t padding[256]; /* multiple of 64 */
1318 } em;
1319
1320 /** NEM part. */
1321 union
1322 {
1323#ifdef VMM_INCLUDED_SRC_include_NEMInternal_h
1324 struct NEM s;
1325#endif
1326 uint8_t padding[128]; /* multiple of 64 */
1327 } nem;
1328
1329 /** TM part. */
1330 union
1331 {
1332#ifdef VMM_INCLUDED_SRC_include_TMInternal_h
1333 struct TM s;
1334#endif
1335 uint8_t padding[2496]; /* multiple of 64 */
1336 } tm;
1337
1338 /** DBGF part. */
1339 union
1340 {
1341#ifdef VMM_INCLUDED_SRC_include_DBGFInternal_h
1342 struct DBGF s;
1343#endif
1344#ifdef VBOX_INCLUDED_vmm_dbgf_h
1345 /** Read only info exposed about interrupt breakpoints and selected events. */
1346 struct
1347 {
1348 /** Bitmap of enabled hardware interrupt breakpoints. */
1349 uint32_t bmHardIntBreakpoints[256 / 32];
1350 /** Bitmap of enabled software interrupt breakpoints. */
1351 uint32_t bmSoftIntBreakpoints[256 / 32];
1352 /** Bitmap of selected events.
1353 * This includes non-selectable events too for simplicity, we maintain the
1354 * state for some of these, as it may come in handy. */
1355 uint64_t bmSelectedEvents[(DBGFEVENT_END + 63) / 64];
1356 /** Enabled hardware interrupt breakpoints. */
1357 uint32_t cHardIntBreakpoints;
1358 /** Enabled software interrupt breakpoints. */
1359 uint32_t cSoftIntBreakpoints;
1360 /** The number of selected events. */
1361 uint32_t cSelectedEvents;
1362 /** The number of enabled hardware breakpoints. */
1363 uint8_t cEnabledHwBreakpoints;
1364 /** The number of enabled hardware I/O breakpoints. */
1365 uint8_t cEnabledHwIoBreakpoints;
1366 /** The number of enabled INT3 breakpoints. */
1367 uint8_t cEnabledInt3Breakpoints;
1368 uint8_t abPadding[1]; /**< Unused padding space up for grabs. */
1369 } const ro;
1370#endif
1371 uint8_t padding[2432]; /* multiple of 64 */
1372 } dbgf;
1373
1374 /** SSM part. */
1375 union
1376 {
1377#ifdef VMM_INCLUDED_SRC_include_SSMInternal_h
1378 struct SSM s;
1379#endif
1380 uint8_t padding[128]; /* multiple of 64 */
1381 } ssm;
1382
1383 /** FTM part. */
1384 union
1385 {
1386#ifdef VMM_INCLUDED_SRC_include_FTMInternal_h
1387 struct FTM s;
1388#endif
1389 uint8_t padding[512]; /* multiple of 64 */
1390 } ftm;
1391
1392#ifdef VBOX_WITH_REM
1393 /** REM part. */
1394 union
1395 {
1396# ifdef VMM_INCLUDED_SRC_include_REMInternal_h
1397 struct REM s;
1398# endif
1399 uint8_t padding[0x11100]; /* multiple of 64 */
1400 } rem;
1401#endif
1402
1403 union
1404 {
1405#ifdef VMM_INCLUDED_SRC_include_GIMInternal_h
1406 struct GIM s;
1407#endif
1408 uint8_t padding[448]; /* multiple of 64 */
1409 } gim;
1410
1411 union
1412 {
1413#ifdef VMM_INCLUDED_SRC_include_APICInternal_h
1414 struct APIC s;
1415#endif
1416 uint8_t padding[128]; /* multiple of 8 */
1417 } apic;
1418
1419 /* ---- begin small stuff ---- */
1420
1421 /** VM part. */
1422 union
1423 {
1424#ifdef VMM_INCLUDED_SRC_include_VMInternal_h
1425 struct VMINT s;
1426#endif
1427 uint8_t padding[32]; /* multiple of 8 */
1428 } vm;
1429
1430 /** CFGM part. */
1431 union
1432 {
1433#ifdef VMM_INCLUDED_SRC_include_CFGMInternal_h
1434 struct CFGM s;
1435#endif
1436 uint8_t padding[8]; /* multiple of 8 */
1437 } cfgm;
1438
1439#ifdef VBOX_BUGREF_9217
1440 /** Padding for aligning the structure size on a page boundrary. */
1441# ifdef VBOX_WITH_REM
1442 uint8_t abAlignment2[2134 - sizeof(PVMCPUR3) * VMM_MAX_CPU_COUNT];
1443# else
1444 uint8_t abAlignment2[2390 - sizeof(PVMCPUR3) * VMM_MAX_CPU_COUNT];
1445# endif
1446#else
1447 /** Padding for aligning the cpu array on a page boundary. */
1448# ifdef VBOX_WITH_REM
1449 uint8_t abAlignment2[2134];
1450# else
1451 uint8_t abAlignment2[2390];
1452# endif
1453#endif
1454
1455 /* ---- end small stuff ---- */
1456
1457#ifdef VBOX_BUGREF_9217
1458 /** Array of VMCPU pointers. */
1459 PVMCPUR3 apCpus[VMM_MAX_CPU_COUNT];
1460#else
1461 /** VMCPU array for the configured number of virtual CPUs.
1462 * Must be aligned on a page boundary for TLB hit reasons as well as
1463 * alignment of VMCPU members. */
1464 VMCPU aCpus[1];
1465#endif
1466} VM;
1467
1468
1469#ifdef IN_RC
1470RT_C_DECLS_BEGIN
1471
1472/** The VM structure.
1473 * This is imported from the VMMRCBuiltin module, i.e. it's a one of those magic
1474 * globals which we should avoid using.
1475 */
1476extern DECLIMPORT(VM) g_VM;
1477
1478/** The VMCPU structure for virtual CPU \#0.
1479 * This is imported from the VMMRCBuiltin module, i.e. it's a one of those magic
1480 * globals which we should avoid using.
1481 */
1482extern DECLIMPORT(VMCPU) g_VCpu0;
1483
1484RT_C_DECLS_END
1485#endif
1486
1487/** @} */
1488
1489#endif /* !VBOX_INCLUDED_vmm_vm_h */
1490
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