VirtualBox

source: vbox/trunk/include/VBox/vmm/vm.h@ 80074

Last change on this file since 80074 was 80074, checked in by vboxsync, 6 years ago

VMM,Main,++: Retired the unfinished FTM component.
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1/** @file
2 * VM - The Virtual Machine, data.
3 */
4
5/*
6 * Copyright (C) 2006-2019 Oracle Corporation
7 *
8 * This file is part of VirtualBox Open Source Edition (OSE), as
9 * available from http://www.virtualbox.org. This file is free software;
10 * you can redistribute it and/or modify it under the terms of the GNU
11 * General Public License (GPL) as published by the Free Software
12 * Foundation, in version 2 as it comes in the "COPYING" file of the
13 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15 *
16 * The contents of this file may alternatively be used under the terms
17 * of the Common Development and Distribution License Version 1.0
18 * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19 * VirtualBox OSE distribution, in which case the provisions of the
20 * CDDL are applicable instead of those of the GPL.
21 *
22 * You may elect to license modified versions of this file under the
23 * terms and conditions of either the GPL or the CDDL or both.
24 */
25
26#ifndef VBOX_INCLUDED_vmm_vm_h
27#define VBOX_INCLUDED_vmm_vm_h
28#ifndef RT_WITHOUT_PRAGMA_ONCE
29# pragma once
30#endif
31
32#ifndef VBOX_FOR_DTRACE_LIB
33# include <iprt/param.h>
34# include <VBox/param.h>
35# include <VBox/types.h>
36# include <VBox/vmm/cpum.h>
37# include <VBox/vmm/stam.h>
38# include <VBox/vmm/vmapi.h>
39# include <VBox/vmm/vmm.h>
40# include <VBox/sup.h>
41#else
42# pragma D depends_on library vbox-types.d
43# pragma D depends_on library CPUMInternal.d
44# define VMM_INCLUDED_SRC_include_CPUMInternal_h
45#endif
46
47
48
49/** @defgroup grp_vm The Virtual Machine
50 * @ingroup grp_vmm
51 * @{
52 */
53
54/**
55 * The state of a Virtual CPU.
56 *
57 * The basic state indicated here is whether the CPU has been started or not. In
58 * addition, there are sub-states when started for assisting scheduling (GVMM
59 * mostly).
60 *
61 * The transition out of the STOPPED state is done by a vmR3PowerOn.
62 * The transition back to the STOPPED state is done by vmR3PowerOff.
63 *
64 * (Alternatively we could let vmR3PowerOn start CPU 0 only and let the SPIP
65 * handling switch on the other CPUs. Then vmR3Reset would stop all but CPU 0.)
66 */
67typedef enum VMCPUSTATE
68{
69 /** The customary invalid zero. */
70 VMCPUSTATE_INVALID = 0,
71
72 /** Virtual CPU has not yet been started. */
73 VMCPUSTATE_STOPPED,
74
75 /** CPU started. */
76 VMCPUSTATE_STARTED,
77 /** CPU started in HM context. */
78 VMCPUSTATE_STARTED_HM,
79 /** Executing guest code and can be poked (RC or STI bits of HM). */
80 VMCPUSTATE_STARTED_EXEC,
81 /** Executing guest code in the recompiler. */
82 VMCPUSTATE_STARTED_EXEC_REM,
83 /** Executing guest code using NEM. */
84 VMCPUSTATE_STARTED_EXEC_NEM,
85 VMCPUSTATE_STARTED_EXEC_NEM_WAIT,
86 VMCPUSTATE_STARTED_EXEC_NEM_CANCELED,
87 /** Halted. */
88 VMCPUSTATE_STARTED_HALTED,
89
90 /** The end of valid virtual CPU states. */
91 VMCPUSTATE_END,
92
93 /** Ensure 32-bit type. */
94 VMCPUSTATE_32BIT_HACK = 0x7fffffff
95} VMCPUSTATE;
96
97/** Enables 64-bit FFs. */
98#define VMCPU_WITH_64_BIT_FFS
99
100
101/**
102 * The cross context virtual CPU structure.
103 *
104 * Run 'kmk run-struct-tests' (from src/VBox/VMM if you like) after updating!
105 */
106typedef struct VMCPU
107{
108 /** @name Volatile per-cpu data.
109 * @{ */
110 /** Per CPU forced action.
111 * See the VMCPU_FF_* \#defines. Updated atomically. */
112#ifdef VMCPU_WITH_64_BIT_FFS
113 uint64_t volatile fLocalForcedActions;
114#else
115 uint32_t volatile fLocalForcedActions;
116 uint32_t fForLocalForcedActionsExpansion;
117#endif
118 /** The CPU state. */
119 VMCPUSTATE volatile enmState;
120
121 /** Which host CPU ID is this EMT running on.
122 * Only valid when in RC or HMR0 with scheduling disabled. */
123 RTCPUID volatile idHostCpu;
124 /** The CPU set index corresponding to idHostCpu, UINT32_MAX if not valid.
125 * @remarks Best to make sure iHostCpuSet shares cache line with idHostCpu! */
126 uint32_t volatile iHostCpuSet;
127 /** Padding up to 64 bytes. */
128 uint8_t abAlignment0[64 - 20];
129 /** @} */
130
131 /** IEM part.
132 * @remarks This comes first as it allows the use of 8-bit immediates for the
133 * first 64 bytes of the structure, reducing code size a wee bit. */
134#ifdef VMM_INCLUDED_SRC_include_IEMInternal_h /* For PDB hacking. */
135 union VMCPUUNIONIEMFULL
136#else
137 union VMCPUUNIONIEMSTUB
138#endif
139 {
140#ifdef VMM_INCLUDED_SRC_include_IEMInternal_h
141 struct IEMCPU s;
142#endif
143 uint8_t padding[18496]; /* multiple of 64 */
144 } iem;
145
146 /** @name Static per-cpu data.
147 * (Putting this after IEM, hoping that it's less frequently used than it.)
148 * @{ */
149 /** The CPU ID.
150 * This is the index into the VM::aCpu array. */
151 VMCPUID idCpu;
152 /** Raw-mode Context VM Pointer. */
153 PVMRC pVMRC;
154 /** Ring-3 Host Context VM Pointer. */
155 PVMR3 pVMR3;
156 /** Ring-0 Host Context VM Pointer. */
157 PVMR0 pVMR0;
158 /** Pointer to the ring-3 UVMCPU structure. */
159 PUVMCPU pUVCpu;
160 /** The native thread handle. */
161 RTNATIVETHREAD hNativeThread;
162 /** The native R0 thread handle. (different from the R3 handle!) */
163 RTNATIVETHREAD hNativeThreadR0;
164 /** Align the structures below bit on a 64-byte boundary and make sure it starts
165 * at the same offset in both 64-bit and 32-bit builds.
166 *
167 * @remarks The alignments of the members that are larger than 48 bytes should be
168 * 64-byte for cache line reasons. structs containing small amounts of
169 * data could be lumped together at the end with a < 64 byte padding
170 * following it (to grow into and align the struct size).
171 */
172 uint8_t abAlignment1[64 - 4 - 4 - 5 * (HC_ARCH_BITS == 64 ? 8 : 4)];
173 /** @} */
174
175 /** HM part. */
176 union VMCPUUNIONHM
177 {
178#ifdef VMM_INCLUDED_SRC_include_HMInternal_h
179 struct HMCPU s;
180#endif
181 uint8_t padding[5888]; /* multiple of 64 */
182 } hm;
183
184 /** NEM part. */
185 union VMCPUUNIONNEM
186 {
187#ifdef VMM_INCLUDED_SRC_include_NEMInternal_h
188 struct NEMCPU s;
189#endif
190 uint8_t padding[512]; /* multiple of 64 */
191 } nem;
192
193 /** TRPM part. */
194 union VMCPUUNIONTRPM
195 {
196#ifdef VMM_INCLUDED_SRC_include_TRPMInternal_h
197 struct TRPMCPU s;
198#endif
199 uint8_t padding[128]; /* multiple of 64 */
200 } trpm;
201
202 /** TM part. */
203 union VMCPUUNIONTM
204 {
205#ifdef VMM_INCLUDED_SRC_include_TMInternal_h
206 struct TMCPU s;
207#endif
208 uint8_t padding[384]; /* multiple of 64 */
209 } tm;
210
211 /** VMM part. */
212 union VMCPUUNIONVMM
213 {
214#ifdef VMM_INCLUDED_SRC_include_VMMInternal_h
215 struct VMMCPU s;
216#endif
217 uint8_t padding[896]; /* multiple of 64 */
218 } vmm;
219
220 /** PDM part. */
221 union VMCPUUNIONPDM
222 {
223#ifdef VMM_INCLUDED_SRC_include_PDMInternal_h
224 struct PDMCPU s;
225#endif
226 uint8_t padding[256]; /* multiple of 64 */
227 } pdm;
228
229 /** IOM part. */
230 union VMCPUUNIONIOM
231 {
232#ifdef VMM_INCLUDED_SRC_include_IOMInternal_h
233 struct IOMCPU s;
234#endif
235 uint8_t padding[512]; /* multiple of 64 */
236 } iom;
237
238 /** DBGF part.
239 * @todo Combine this with other tiny structures. */
240 union VMCPUUNIONDBGF
241 {
242#ifdef VMM_INCLUDED_SRC_include_DBGFInternal_h
243 struct DBGFCPU s;
244#endif
245 uint8_t padding[256]; /* multiple of 64 */
246 } dbgf;
247
248 /** GIM part. */
249 union VMCPUUNIONGIM
250 {
251#ifdef VMM_INCLUDED_SRC_include_GIMInternal_h
252 struct GIMCPU s;
253#endif
254 uint8_t padding[512]; /* multiple of 64 */
255 } gim;
256
257 /** APIC part. */
258 union VMCPUUNIONAPIC
259 {
260#ifdef VMM_INCLUDED_SRC_include_APICInternal_h
261 struct APICCPU s;
262#endif
263 uint8_t padding[1792]; /* multiple of 64 */
264 } apic;
265
266 /*
267 * Some less frequently used global members that doesn't need to take up
268 * precious space at the head of the structure.
269 */
270
271 /** Trace groups enable flags. */
272 uint32_t fTraceGroups; /* 64 / 44 */
273 /** State data for use by ad hoc profiling. */
274 uint32_t uAdHoc;
275 /** Profiling samples for use by ad hoc profiling. */
276 STAMPROFILEADV aStatAdHoc[8]; /* size: 40*8 = 320 */
277
278 /** Align the following members on page boundary. */
279 uint8_t abAlignment2[2680];
280
281 /** PGM part. */
282 union VMCPUUNIONPGM
283 {
284#ifdef VMM_INCLUDED_SRC_include_PGMInternal_h
285 struct PGMCPU s;
286#endif
287 uint8_t padding[4096]; /* multiple of 4096 */
288 } pgm;
289
290 /** CPUM part. */
291 union VMCPUUNIONCPUM
292 {
293#ifdef VMM_INCLUDED_SRC_include_CPUMInternal_h
294 struct CPUMCPU s;
295#endif
296#ifdef VMCPU_INCL_CPUM_GST_CTX
297 /** The guest CPUM context for direct use by execution engines.
298 * This is not for general consumption, but for HM, REM, IEM, and maybe a few
299 * others. The rest will use the function based CPUM API. */
300 CPUMCTX GstCtx;
301#endif
302 uint8_t padding[4096]; /* multiple of 4096 */
303 } cpum;
304
305 /** EM part. */
306 union VMCPUUNIONEM
307 {
308#ifdef VMM_INCLUDED_SRC_include_EMInternal_h
309 struct EMCPU s;
310#endif
311 uint8_t padding[40960]; /* multiple of 4096 */
312 } em;
313} VMCPU;
314
315
316#ifndef VBOX_FOR_DTRACE_LIB
317AssertCompileSizeAlignment(VMCPU, 4096);
318
319/** @name Operations on VMCPU::enmState
320 * @{ */
321/** Gets the VMCPU state. */
322#define VMCPU_GET_STATE(pVCpu) ( (pVCpu)->enmState )
323/** Sets the VMCPU state. */
324#define VMCPU_SET_STATE(pVCpu, enmNewState) \
325 ASMAtomicWriteU32((uint32_t volatile *)&(pVCpu)->enmState, (enmNewState))
326/** Cmpares and sets the VMCPU state. */
327#define VMCPU_CMPXCHG_STATE(pVCpu, enmNewState, enmOldState) \
328 ASMAtomicCmpXchgU32((uint32_t volatile *)&(pVCpu)->enmState, (enmNewState), (enmOldState))
329/** Checks the VMCPU state. */
330#ifdef VBOX_STRICT
331# define VMCPU_ASSERT_STATE(pVCpu, enmExpectedState) \
332 do { \
333 VMCPUSTATE enmState = VMCPU_GET_STATE(pVCpu); \
334 AssertMsg(enmState == (enmExpectedState), \
335 ("enmState=%d enmExpectedState=%d idCpu=%u\n", \
336 enmState, enmExpectedState, (pVCpu)->idCpu)); \
337 } while (0)
338#else
339# define VMCPU_ASSERT_STATE(pVCpu, enmExpectedState) do { } while (0)
340#endif
341/** Tests if the state means that the CPU is started. */
342#define VMCPUSTATE_IS_STARTED(enmState) ( (enmState) > VMCPUSTATE_STOPPED )
343/** Tests if the state means that the CPU is stopped. */
344#define VMCPUSTATE_IS_STOPPED(enmState) ( (enmState) == VMCPUSTATE_STOPPED )
345/** @} */
346
347
348/** The name of the raw-mode context VMM Core module. */
349#define VMMRC_MAIN_MODULE_NAME "VMMRC.rc"
350/** The name of the ring-0 context VMM Core module. */
351#define VMMR0_MAIN_MODULE_NAME "VMMR0.r0"
352
353
354/** VM Forced Action Flags.
355 *
356 * Use the VM_FF_SET() and VM_FF_CLEAR() macros to change the force
357 * action mask of a VM.
358 *
359 * Available VM bits:
360 * 0, 1, 5, 6, 7, 13, 14, 15, 16, 17, 21, 22, 23, 24, 25, 26, 27, 28, 30
361 *
362 *
363 * Available VMCPU bits:
364 * 14, 15, 36 to 63
365 *
366 * @todo If we run low on VMCPU, we may consider merging the SELM bits
367 *
368 * @{
369 */
370/** The virtual sync clock has been stopped, go to TM until it has been
371 * restarted... */
372#define VM_FF_TM_VIRTUAL_SYNC RT_BIT_32(VM_FF_TM_VIRTUAL_SYNC_BIT)
373#define VM_FF_TM_VIRTUAL_SYNC_BIT 2
374/** PDM Queues are pending. */
375#define VM_FF_PDM_QUEUES RT_BIT_32(VM_FF_PDM_QUEUES_BIT)
376/** The bit number for VM_FF_PDM_QUEUES. */
377#define VM_FF_PDM_QUEUES_BIT 3
378/** PDM DMA transfers are pending. */
379#define VM_FF_PDM_DMA RT_BIT_32(VM_FF_PDM_DMA_BIT)
380/** The bit number for VM_FF_PDM_DMA. */
381#define VM_FF_PDM_DMA_BIT 4
382/** This action forces the VM to call DBGF so DBGF can service debugger
383 * requests in the emulation thread.
384 * This action flag stays asserted till DBGF clears it.*/
385#define VM_FF_DBGF RT_BIT_32(VM_FF_DBGF_BIT)
386/** The bit number for VM_FF_DBGF. */
387#define VM_FF_DBGF_BIT 8
388/** This action forces the VM to service pending requests from other
389 * thread or requests which must be executed in another context. */
390#define VM_FF_REQUEST RT_BIT_32(VM_FF_REQUEST_BIT)
391#define VM_FF_REQUEST_BIT 9
392/** Check for VM state changes and take appropriate action. */
393#define VM_FF_CHECK_VM_STATE RT_BIT_32(VM_FF_CHECK_VM_STATE_BIT)
394/** The bit number for VM_FF_CHECK_VM_STATE. */
395#define VM_FF_CHECK_VM_STATE_BIT 10
396/** Reset the VM. (postponed) */
397#define VM_FF_RESET RT_BIT_32(VM_FF_RESET_BIT)
398/** The bit number for VM_FF_RESET. */
399#define VM_FF_RESET_BIT 11
400/** EMT rendezvous in VMM. */
401#define VM_FF_EMT_RENDEZVOUS RT_BIT_32(VM_FF_EMT_RENDEZVOUS_BIT)
402/** The bit number for VM_FF_EMT_RENDEZVOUS. */
403#define VM_FF_EMT_RENDEZVOUS_BIT 12
404
405/** PGM needs to allocate handy pages. */
406#define VM_FF_PGM_NEED_HANDY_PAGES RT_BIT_32(VM_FF_PGM_NEED_HANDY_PAGES_BIT)
407#define VM_FF_PGM_NEED_HANDY_PAGES_BIT 18
408/** PGM is out of memory.
409 * Abandon all loops and code paths which can be resumed and get up to the EM
410 * loops. */
411#define VM_FF_PGM_NO_MEMORY RT_BIT_32(VM_FF_PGM_NO_MEMORY_BIT)
412#define VM_FF_PGM_NO_MEMORY_BIT 19
413 /** PGM is about to perform a lightweight pool flush
414 * Guest SMP: all EMT threads should return to ring 3
415 */
416#define VM_FF_PGM_POOL_FLUSH_PENDING RT_BIT_32(VM_FF_PGM_POOL_FLUSH_PENDING_BIT)
417#define VM_FF_PGM_POOL_FLUSH_PENDING_BIT 20
418/** REM needs to be informed about handler changes. */
419#define VM_FF_REM_HANDLER_NOTIFY RT_BIT_32(VM_FF_REM_HANDLER_NOTIFY_BIT)
420/** The bit number for VM_FF_REM_HANDLER_NOTIFY. */
421#define VM_FF_REM_HANDLER_NOTIFY_BIT 29
422/** Suspend the VM - debug only. */
423#define VM_FF_DEBUG_SUSPEND RT_BIT_32(VM_FF_DEBUG_SUSPEND_BIT)
424#define VM_FF_DEBUG_SUSPEND_BIT 31
425
426
427/** This action forces the VM to check any pending interrupts on the APIC. */
428#define VMCPU_FF_INTERRUPT_APIC RT_BIT_64(VMCPU_FF_INTERRUPT_APIC_BIT)
429#define VMCPU_FF_INTERRUPT_APIC_BIT 0
430/** This action forces the VM to check any pending interrups on the PIC. */
431#define VMCPU_FF_INTERRUPT_PIC RT_BIT_64(VMCPU_FF_INTERRUPT_PIC_BIT)
432#define VMCPU_FF_INTERRUPT_PIC_BIT 1
433/** This action forces the VM to schedule and run pending timer (TM).
434 * @remarks Don't move - PATM compatibility. */
435#define VMCPU_FF_TIMER RT_BIT_64(VMCPU_FF_TIMER_BIT)
436#define VMCPU_FF_TIMER_BIT 2
437/** This action forces the VM to check any pending NMIs. */
438#define VMCPU_FF_INTERRUPT_NMI RT_BIT_64(VMCPU_FF_INTERRUPT_NMI_BIT)
439#define VMCPU_FF_INTERRUPT_NMI_BIT 3
440/** This action forces the VM to check any pending SMIs. */
441#define VMCPU_FF_INTERRUPT_SMI RT_BIT_64(VMCPU_FF_INTERRUPT_SMI_BIT)
442#define VMCPU_FF_INTERRUPT_SMI_BIT 4
443/** PDM critical section unlocking is pending, process promptly upon return to R3. */
444#define VMCPU_FF_PDM_CRITSECT RT_BIT_64(VMCPU_FF_PDM_CRITSECT_BIT)
445#define VMCPU_FF_PDM_CRITSECT_BIT 5
446/** Special EM internal force flag that is used by EMUnhaltAndWakeUp() to force
447 * the virtual CPU out of the next (/current) halted state. It is not processed
448 * nor cleared by emR3ForcedActions (similar to VMCPU_FF_BLOCK_NMIS), instead it
449 * is cleared the next time EM leaves the HALTED state. */
450#define VMCPU_FF_UNHALT RT_BIT_64(VMCPU_FF_UNHALT_BIT)
451#define VMCPU_FF_UNHALT_BIT 6
452/** Pending IEM action (mask). */
453#define VMCPU_FF_IEM RT_BIT_64(VMCPU_FF_IEM_BIT)
454/** Pending IEM action (bit number). */
455#define VMCPU_FF_IEM_BIT 7
456/** Pending APIC action (bit number). */
457#define VMCPU_FF_UPDATE_APIC_BIT 8
458/** This action forces the VM to update APIC's asynchronously arrived
459 * interrupts as pending interrupts. */
460#define VMCPU_FF_UPDATE_APIC RT_BIT_64(VMCPU_FF_UPDATE_APIC_BIT)
461/** This action forces the VM to service pending requests from other
462 * thread or requests which must be executed in another context. */
463#define VMCPU_FF_REQUEST RT_BIT_64(VMCPU_FF_REQUEST_BIT)
464#define VMCPU_FF_REQUEST_BIT 9
465/** Pending DBGF event (alternative to passing VINF_EM_DBG_EVENT around). */
466#define VMCPU_FF_DBGF RT_BIT_64(VMCPU_FF_DBGF_BIT)
467/** The bit number for VMCPU_FF_DBGF. */
468#define VMCPU_FF_DBGF_BIT 10
469/** This action forces the VM to service any pending updates to CR3 (used only
470 * by HM). */
471/** Hardware virtualized nested-guest interrupt pending. */
472#define VMCPU_FF_INTERRUPT_NESTED_GUEST RT_BIT_64(VMCPU_FF_INTERRUPT_NESTED_GUEST_BIT)
473#define VMCPU_FF_INTERRUPT_NESTED_GUEST_BIT 11
474#define VMCPU_FF_HM_UPDATE_CR3 RT_BIT_64(VMCPU_FF_HM_UPDATE_CR3_BIT)
475#define VMCPU_FF_HM_UPDATE_CR3_BIT 12
476/** This action forces the VM to service any pending updates to PAE PDPEs (used
477 * only by HM). */
478#define VMCPU_FF_HM_UPDATE_PAE_PDPES RT_BIT_64(VMCPU_FF_HM_UPDATE_PAE_PDPES_BIT)
479#define VMCPU_FF_HM_UPDATE_PAE_PDPES_BIT 13
480/** This action forces the VM to resync the page tables before going
481 * back to execute guest code. (GLOBAL FLUSH) */
482#define VMCPU_FF_PGM_SYNC_CR3 RT_BIT_64(VMCPU_FF_PGM_SYNC_CR3_BIT)
483#define VMCPU_FF_PGM_SYNC_CR3_BIT 16
484/** Same as VM_FF_PGM_SYNC_CR3 except that global pages can be skipped.
485 * (NON-GLOBAL FLUSH) */
486#define VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL RT_BIT_64(VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL_BIT)
487#define VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL_BIT 17
488/** Check for pending TLB shootdown actions (deprecated)
489 * Reserved for furture HM re-use if necessary / safe.
490 * Consumer: HM */
491#define VMCPU_FF_TLB_SHOOTDOWN_UNUSED RT_BIT_64(VMCPU_FF_TLB_SHOOTDOWN_UNUSED_BIT)
492#define VMCPU_FF_TLB_SHOOTDOWN_UNUSED_BIT 18
493/** Check for pending TLB flush action.
494 * Consumer: HM
495 * @todo rename to VMCPU_FF_HM_TLB_FLUSH */
496#define VMCPU_FF_TLB_FLUSH RT_BIT_64(VMCPU_FF_TLB_FLUSH_BIT)
497/** The bit number for VMCPU_FF_TLB_FLUSH. */
498#define VMCPU_FF_TLB_FLUSH_BIT 19
499/* 20 used to be VMCPU_FF_TRPM_SYNC_IDT (raw-mode only). */
500/* 21 used to be VMCPU_FF_SELM_SYNC_TSS (raw-mode only). */
501/* 22 used to be VMCPU_FF_SELM_SYNC_GDT (raw-mode only). */
502/* 23 used to be VMCPU_FF_SELM_SYNC_LDT (raw-mode only). */
503/** Inhibit interrupts pending. See EMGetInhibitInterruptsPC(). */
504#define VMCPU_FF_INHIBIT_INTERRUPTS RT_BIT_64(VMCPU_FF_INHIBIT_INTERRUPTS_BIT)
505#define VMCPU_FF_INHIBIT_INTERRUPTS_BIT 24
506/** Block injection of non-maskable interrupts to the guest. */
507#define VMCPU_FF_BLOCK_NMIS RT_BIT_64(VMCPU_FF_BLOCK_NMIS_BIT)
508#define VMCPU_FF_BLOCK_NMIS_BIT 25
509/** Force return to Ring-3. */
510#define VMCPU_FF_TO_R3 RT_BIT_64(VMCPU_FF_TO_R3_BIT)
511#define VMCPU_FF_TO_R3_BIT 28
512/** Force return to ring-3 to service pending I/O or MMIO write.
513 * This is a backup for mechanism VINF_IOM_R3_IOPORT_COMMIT_WRITE and
514 * VINF_IOM_R3_MMIO_COMMIT_WRITE, allowing VINF_EM_DBG_BREAKPOINT and similar
515 * status codes to be propagated at the same time without loss. */
516#define VMCPU_FF_IOM RT_BIT_64(VMCPU_FF_IOM_BIT)
517#define VMCPU_FF_IOM_BIT 29
518/* 30 used to be VMCPU_FF_CPUM */
519/** VMX-preemption timer in effect. */
520#define VMCPU_FF_VMX_PREEMPT_TIMER RT_BIT_64(VMCPU_FF_VMX_PREEMPT_TIMER_BIT)
521#define VMCPU_FF_VMX_PREEMPT_TIMER_BIT 31
522/** Pending MTF (Monitor Trap Flag) event. */
523#define VMCPU_FF_VMX_MTF RT_BIT_64(VMCPU_FF_VMX_MTF_BIT)
524#define VMCPU_FF_VMX_MTF_BIT 32
525/** VMX APIC-write emulation pending. */
526#define VMCPU_FF_VMX_APIC_WRITE RT_BIT_64(VMCPU_FF_VMX_APIC_WRITE_BIT)
527#define VMCPU_FF_VMX_APIC_WRITE_BIT 33
528/** VMX interrupt-window event pending. */
529#define VMCPU_FF_VMX_INT_WINDOW RT_BIT_64(VMCPU_FF_VMX_INT_WINDOW_BIT)
530#define VMCPU_FF_VMX_INT_WINDOW_BIT 34
531/** VMX NMI-window event pending. */
532#define VMCPU_FF_VMX_NMI_WINDOW RT_BIT_64(VMCPU_FF_VMX_NMI_WINDOW_BIT)
533#define VMCPU_FF_VMX_NMI_WINDOW_BIT 35
534
535
536/** Externally VM forced actions. Used to quit the idle/wait loop. */
537#define VM_FF_EXTERNAL_SUSPENDED_MASK ( VM_FF_CHECK_VM_STATE | VM_FF_DBGF | VM_FF_REQUEST | VM_FF_EMT_RENDEZVOUS )
538/** Externally VMCPU forced actions. Used to quit the idle/wait loop. */
539#define VMCPU_FF_EXTERNAL_SUSPENDED_MASK ( VMCPU_FF_REQUEST | VMCPU_FF_DBGF )
540
541/** Externally forced VM actions. Used to quit the idle/wait loop. */
542#define VM_FF_EXTERNAL_HALTED_MASK ( VM_FF_CHECK_VM_STATE | VM_FF_DBGF | VM_FF_REQUEST \
543 | VM_FF_PDM_QUEUES | VM_FF_PDM_DMA | VM_FF_EMT_RENDEZVOUS )
544/** Externally forced VMCPU actions. Used to quit the idle/wait loop. */
545#define VMCPU_FF_EXTERNAL_HALTED_MASK ( VMCPU_FF_UPDATE_APIC | VMCPU_FF_INTERRUPT_APIC | VMCPU_FF_INTERRUPT_PIC \
546 | VMCPU_FF_REQUEST | VMCPU_FF_INTERRUPT_NMI | VMCPU_FF_INTERRUPT_SMI \
547 | VMCPU_FF_UNHALT | VMCPU_FF_TIMER | VMCPU_FF_DBGF \
548 | VMCPU_FF_INTERRUPT_NESTED_GUEST)
549
550/** High priority VM pre-execution actions. */
551#define VM_FF_HIGH_PRIORITY_PRE_MASK ( VM_FF_CHECK_VM_STATE | VM_FF_DBGF | VM_FF_TM_VIRTUAL_SYNC \
552 | VM_FF_DEBUG_SUSPEND | VM_FF_PGM_NEED_HANDY_PAGES | VM_FF_PGM_NO_MEMORY \
553 | VM_FF_EMT_RENDEZVOUS )
554/** High priority VMCPU pre-execution actions. */
555#define VMCPU_FF_HIGH_PRIORITY_PRE_MASK ( VMCPU_FF_TIMER | VMCPU_FF_INTERRUPT_APIC | VMCPU_FF_INTERRUPT_PIC \
556 | VMCPU_FF_UPDATE_APIC | VMCPU_FF_INHIBIT_INTERRUPTS | VMCPU_FF_DBGF \
557 | VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL \
558 | VMCPU_FF_INTERRUPT_NESTED_GUEST | VMCPU_FF_VMX_MTF | VMCPU_FF_VMX_APIC_WRITE \
559 | VMCPU_FF_VMX_PREEMPT_TIMER | VMCPU_FF_VMX_NMI_WINDOW | VMCPU_FF_VMX_INT_WINDOW )
560
561/** High priority VM pre raw-mode execution mask. */
562#define VM_FF_HIGH_PRIORITY_PRE_RAW_MASK ( VM_FF_PGM_NEED_HANDY_PAGES | VM_FF_PGM_NO_MEMORY )
563/** High priority VMCPU pre raw-mode execution mask. */
564#define VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK ( VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL \
565 | VMCPU_FF_INHIBIT_INTERRUPTS )
566
567/** High priority post-execution actions. */
568#define VM_FF_HIGH_PRIORITY_POST_MASK ( VM_FF_PGM_NO_MEMORY )
569/** High priority post-execution actions. */
570#define VMCPU_FF_HIGH_PRIORITY_POST_MASK ( VMCPU_FF_PDM_CRITSECT \
571 | VMCPU_FF_HM_UPDATE_CR3 | VMCPU_FF_HM_UPDATE_PAE_PDPES \
572 | VMCPU_FF_IEM | VMCPU_FF_IOM )
573
574/** Normal priority VM post-execution actions. */
575#define VM_FF_NORMAL_PRIORITY_POST_MASK ( VM_FF_CHECK_VM_STATE | VM_FF_DBGF | VM_FF_RESET \
576 | VM_FF_PGM_NO_MEMORY | VM_FF_EMT_RENDEZVOUS)
577/** Normal priority VMCPU post-execution actions. */
578#define VMCPU_FF_NORMAL_PRIORITY_POST_MASK ( VMCPU_FF_DBGF )
579
580/** Normal priority VM actions. */
581#define VM_FF_NORMAL_PRIORITY_MASK ( VM_FF_REQUEST | VM_FF_PDM_QUEUES | VM_FF_PDM_DMA \
582 | VM_FF_REM_HANDLER_NOTIFY | VM_FF_EMT_RENDEZVOUS)
583/** Normal priority VMCPU actions. */
584#define VMCPU_FF_NORMAL_PRIORITY_MASK ( VMCPU_FF_REQUEST )
585
586/** Flags to clear before resuming guest execution. */
587#define VMCPU_FF_RESUME_GUEST_MASK ( VMCPU_FF_TO_R3 )
588
589
590/** VM flags that cause the REP[|NE|E] STRINS loops to yield immediately. */
591#define VM_FF_HIGH_PRIORITY_POST_REPSTR_MASK ( VM_FF_TM_VIRTUAL_SYNC | VM_FF_PGM_NEED_HANDY_PAGES | VM_FF_PGM_NO_MEMORY \
592 | VM_FF_EMT_RENDEZVOUS | VM_FF_PGM_POOL_FLUSH_PENDING | VM_FF_RESET)
593/** VM flags that cause the REP[|NE|E] STRINS loops to yield. */
594#define VM_FF_YIELD_REPSTR_MASK ( VM_FF_HIGH_PRIORITY_POST_REPSTR_MASK \
595 | VM_FF_PDM_QUEUES | VM_FF_PDM_DMA | VM_FF_DBGF | VM_FF_DEBUG_SUSPEND )
596/** VMCPU flags that cause the REP[|NE|E] STRINS loops to yield immediately. */
597#ifdef IN_RING3
598# define VMCPU_FF_HIGH_PRIORITY_POST_REPSTR_MASK ( VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL | VMCPU_FF_DBGF \
599 | VMCPU_FF_VMX_MTF )
600#else
601# define VMCPU_FF_HIGH_PRIORITY_POST_REPSTR_MASK ( VMCPU_FF_TO_R3 | VMCPU_FF_IEM | VMCPU_FF_IOM | VMCPU_FF_PGM_SYNC_CR3 \
602 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL | VMCPU_FF_DBGF | VMCPU_FF_VMX_MTF )
603#endif
604/** VMCPU flags that cause the REP[|NE|E] STRINS loops to yield, interrupts
605 * enabled. */
606#define VMCPU_FF_YIELD_REPSTR_MASK ( VMCPU_FF_HIGH_PRIORITY_POST_REPSTR_MASK \
607 | VMCPU_FF_INTERRUPT_APIC | VMCPU_FF_UPDATE_APIC | VMCPU_FF_INTERRUPT_PIC \
608 | VMCPU_FF_INTERRUPT_NMI | VMCPU_FF_INTERRUPT_SMI | VMCPU_FF_PDM_CRITSECT \
609 | VMCPU_FF_TIMER | VMCPU_FF_REQUEST \
610 | VMCPU_FF_INTERRUPT_NESTED_GUEST )
611/** VMCPU flags that cause the REP[|NE|E] STRINS loops to yield, interrupts
612 * disabled. */
613#define VMCPU_FF_YIELD_REPSTR_NOINT_MASK ( VMCPU_FF_YIELD_REPSTR_MASK \
614 & ~( VMCPU_FF_INTERRUPT_APIC | VMCPU_FF_UPDATE_APIC | VMCPU_FF_INTERRUPT_PIC \
615 | VMCPU_FF_INTERRUPT_NESTED_GUEST) )
616
617/** VM Flags that cause the HM loops to go back to ring-3. */
618#define VM_FF_HM_TO_R3_MASK ( VM_FF_TM_VIRTUAL_SYNC | VM_FF_PGM_NEED_HANDY_PAGES | VM_FF_PGM_NO_MEMORY \
619 | VM_FF_PDM_QUEUES | VM_FF_EMT_RENDEZVOUS)
620/** VMCPU Flags that cause the HM loops to go back to ring-3. */
621#define VMCPU_FF_HM_TO_R3_MASK ( VMCPU_FF_TO_R3 | VMCPU_FF_TIMER | VMCPU_FF_PDM_CRITSECT \
622 | VMCPU_FF_IEM | VMCPU_FF_IOM)
623
624/** High priority ring-0 VM pre HM-mode execution mask. */
625#define VM_FF_HP_R0_PRE_HM_MASK (VM_FF_HM_TO_R3_MASK | VM_FF_REQUEST | VM_FF_PGM_POOL_FLUSH_PENDING | VM_FF_PDM_DMA)
626/** High priority ring-0 VMCPU pre HM-mode execution mask. */
627#define VMCPU_FF_HP_R0_PRE_HM_MASK ( VMCPU_FF_HM_TO_R3_MASK | VMCPU_FF_PGM_SYNC_CR3 \
628 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL | VMCPU_FF_REQUEST \
629 | VMCPU_FF_VMX_APIC_WRITE | VMCPU_FF_VMX_MTF | VMCPU_FF_VMX_PREEMPT_TIMER)
630/** High priority ring-0 VM pre HM-mode execution mask, single stepping. */
631#define VM_FF_HP_R0_PRE_HM_STEP_MASK (VM_FF_HP_R0_PRE_HM_MASK & ~( VM_FF_TM_VIRTUAL_SYNC | VM_FF_PDM_QUEUES \
632 | VM_FF_EMT_RENDEZVOUS | VM_FF_REQUEST \
633 | VM_FF_PDM_DMA) )
634/** High priority ring-0 VMCPU pre HM-mode execution mask, single stepping. */
635#define VMCPU_FF_HP_R0_PRE_HM_STEP_MASK (VMCPU_FF_HP_R0_PRE_HM_MASK & ~( VMCPU_FF_TO_R3 | VMCPU_FF_TIMER \
636 | VMCPU_FF_PDM_CRITSECT | VMCPU_FF_REQUEST) )
637
638/** All the forced VM flags. */
639#define VM_FF_ALL_MASK (UINT32_MAX)
640/** All the forced VMCPU flags. */
641#define VMCPU_FF_ALL_MASK (UINT32_MAX)
642
643/** All the forced VM flags except those related to raw-mode and hardware
644 * assisted execution. */
645#define VM_FF_ALL_REM_MASK (~(VM_FF_HIGH_PRIORITY_PRE_RAW_MASK) | VM_FF_PGM_NEED_HANDY_PAGES | VM_FF_PGM_NO_MEMORY)
646/** All the forced VMCPU flags except those related to raw-mode and hardware
647 * assisted execution. */
648#define VMCPU_FF_ALL_REM_MASK (~(VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK | VMCPU_FF_PDM_CRITSECT | VMCPU_FF_TLB_FLUSH))
649/** @} */
650
651/** @def VM_FF_SET
652 * Sets a single force action flag.
653 *
654 * @param pVM The cross context VM structure.
655 * @param fFlag The flag to set.
656 */
657#define VM_FF_SET(pVM, fFlag) do { \
658 AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
659 AssertCompile((fFlag) == RT_BIT_32(fFlag##_BIT)); \
660 ASMAtomicOrU32(&(pVM)->fGlobalForcedActions, (fFlag)); \
661 } while (0)
662
663/** @def VMCPU_FF_SET
664 * Sets a single force action flag for the given VCPU.
665 *
666 * @param pVCpu The cross context virtual CPU structure.
667 * @param fFlag The flag to set.
668 * @sa VMCPU_FF_SET_MASK
669 */
670#ifdef VMCPU_WITH_64_BIT_FFS
671# define VMCPU_FF_SET(pVCpu, fFlag) do { \
672 AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
673 AssertCompile((fFlag) == RT_BIT_64(fFlag##_BIT)); \
674 ASMAtomicBitSet(&(pVCpu)->fLocalForcedActions, fFlag##_BIT); \
675 } while (0)
676#else
677# define VMCPU_FF_SET(pVCpu, fFlag) do { \
678 AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
679 AssertCompile((fFlag) == RT_BIT_32(fFlag##_BIT)); \
680 ASMAtomicOrU32(&(pVCpu)->fLocalForcedActions, (fFlag)); \
681 } while (0)
682#endif
683
684/** @def VMCPU_FF_SET_MASK
685 * Sets a two or more force action flag for the given VCPU.
686 *
687 * @param pVCpu The cross context virtual CPU structure.
688 * @param fFlags The flags to set.
689 * @sa VMCPU_FF_SET
690 */
691#ifdef VMCPU_WITH_64_BIT_FFS
692# if ARCH_BITS > 32
693# define VMCPU_FF_SET_MASK(pVCpu, fFlags) \
694 do { ASMAtomicOrU64(&pVCpu->fLocalForcedActions, (fFlags)); } while (0)
695# else
696# define VMCPU_FF_SET_MASK(pVCpu, fFlags) do { \
697 if (!((fFlags) >> 32)) ASMAtomicOrU32((uint32_t volatile *)&pVCpu->fLocalForcedActions, (uint32_t)(fFlags)); \
698 else ASMAtomicOrU64(&pVCpu->fLocalForcedActions, (fFlags)); \
699 } while (0)
700# endif
701#else
702# define VMCPU_FF_SET_MASK(pVCpu, fFlags) \
703 do { ASMAtomicOrU32(&pVCpu->fLocalForcedActions, (fFlags)); } while (0)
704#endif
705
706/** @def VM_FF_CLEAR
707 * Clears a single force action flag.
708 *
709 * @param pVM The cross context VM structure.
710 * @param fFlag The flag to clear.
711 */
712#define VM_FF_CLEAR(pVM, fFlag) do { \
713 AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
714 AssertCompile((fFlag) == RT_BIT_32(fFlag##_BIT)); \
715 ASMAtomicAndU32(&(pVM)->fGlobalForcedActions, ~(fFlag)); \
716 } while (0)
717
718/** @def VMCPU_FF_CLEAR
719 * Clears a single force action flag for the given VCPU.
720 *
721 * @param pVCpu The cross context virtual CPU structure.
722 * @param fFlag The flag to clear.
723 */
724#ifdef VMCPU_WITH_64_BIT_FFS
725# define VMCPU_FF_CLEAR(pVCpu, fFlag) do { \
726 AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
727 AssertCompile((fFlag) == RT_BIT_64(fFlag##_BIT)); \
728 ASMAtomicBitClear(&(pVCpu)->fLocalForcedActions, fFlag##_BIT); \
729 } while (0)
730#else
731# define VMCPU_FF_CLEAR(pVCpu, fFlag) do { \
732 AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
733 AssertCompile((fFlag) == RT_BIT_32(fFlag##_BIT)); \
734 ASMAtomicAndU32(&(pVCpu)->fLocalForcedActions, ~(fFlag)); \
735 } while (0)
736#endif
737
738/** @def VMCPU_FF_CLEAR_MASK
739 * Clears two or more force action flags for the given VCPU.
740 *
741 * @param pVCpu The cross context virtual CPU structure.
742 * @param fFlags The flags to clear.
743 */
744#ifdef VMCPU_WITH_64_BIT_FFS
745# if ARCH_BITS > 32
746# define VMCPU_FF_CLEAR_MASK(pVCpu, fFlags) \
747 do { ASMAtomicAndU64(&(pVCpu)->fLocalForcedActions, ~(fFlags)); } while (0)
748# else
749# define VMCPU_FF_CLEAR_MASK(pVCpu, fFlags) do { \
750 if (!((fFlags) >> 32)) ASMAtomicAndU32((uint32_t volatile *)&(pVCpu)->fLocalForcedActions, ~(uint32_t)(fFlags)); \
751 else ASMAtomicAndU64(&(pVCpu)->fLocalForcedActions, ~(fFlags)); \
752 } while (0)
753# endif
754#else
755# define VMCPU_FF_CLEAR_MASK(pVCpu, fFlags) \
756 do { ASMAtomicAndU32(&(pVCpu)->fLocalForcedActions, ~(fFlags)); } while (0)
757#endif
758
759/** @def VM_FF_IS_SET
760 * Checks if single a force action flag is set.
761 *
762 * @param pVM The cross context VM structure.
763 * @param fFlag The flag to check.
764 * @sa VM_FF_IS_ANY_SET
765 */
766#if !defined(VBOX_STRICT) || !defined(RT_COMPILER_SUPPORTS_LAMBDA)
767# define VM_FF_IS_SET(pVM, fFlag) RT_BOOL((pVM)->fGlobalForcedActions & (fFlag))
768#else
769# define VM_FF_IS_SET(pVM, fFlag) \
770 ([](PVM a_pVM) -> bool \
771 { \
772 AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
773 AssertCompile((fFlag) == RT_BIT_32(fFlag##_BIT)); \
774 return RT_BOOL(a_pVM->fGlobalForcedActions & (fFlag)); \
775 }(pVM))
776#endif
777
778/** @def VMCPU_FF_IS_SET
779 * Checks if a single force action flag is set for the given VCPU.
780 *
781 * @param pVCpu The cross context virtual CPU structure.
782 * @param fFlag The flag to check.
783 * @sa VMCPU_FF_IS_ANY_SET
784 */
785#if !defined(VBOX_STRICT) || !defined(RT_COMPILER_SUPPORTS_LAMBDA)
786# define VMCPU_FF_IS_SET(pVCpu, fFlag) RT_BOOL((pVCpu)->fLocalForcedActions & (fFlag))
787#else
788# define VMCPU_FF_IS_SET(pVCpu, fFlag) \
789 ([](PCVMCPU a_pVCpu) -> bool \
790 { \
791 AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
792 AssertCompile((fFlag) == RT_BIT_64(fFlag##_BIT)); \
793 return RT_BOOL(a_pVCpu->fLocalForcedActions & (fFlag)); \
794 }(pVCpu))
795#endif
796
797/** @def VM_FF_IS_ANY_SET
798 * Checks if one or more force action in the specified set is pending.
799 *
800 * @param pVM The cross context VM structure.
801 * @param fFlags The flags to check for.
802 * @sa VM_FF_IS_SET
803 */
804#define VM_FF_IS_ANY_SET(pVM, fFlags) RT_BOOL((pVM)->fGlobalForcedActions & (fFlags))
805
806/** @def VMCPU_FF_IS_ANY_SET
807 * Checks if two or more force action flags in the specified set is set for the given VCPU.
808 *
809 * @param pVCpu The cross context virtual CPU structure.
810 * @param fFlags The flags to check for.
811 * @sa VMCPU_FF_IS_SET
812 */
813#define VMCPU_FF_IS_ANY_SET(pVCpu, fFlags) RT_BOOL((pVCpu)->fLocalForcedActions & (fFlags))
814
815/** @def VM_FF_TEST_AND_CLEAR
816 * Checks if one (!) force action in the specified set is pending and clears it atomically
817 *
818 * @returns true if the bit was set.
819 * @returns false if the bit was clear.
820 * @param pVM The cross context VM structure.
821 * @param fFlag Flag constant to check and clear (_BIT is appended).
822 */
823#define VM_FF_TEST_AND_CLEAR(pVM, fFlag) (ASMAtomicBitTestAndClear(&(pVM)->fGlobalForcedActions, fFlag##_BIT))
824
825/** @def VMCPU_FF_TEST_AND_CLEAR
826 * Checks if one (!) force action in the specified set is pending and clears it atomically
827 *
828 * @returns true if the bit was set.
829 * @returns false if the bit was clear.
830 * @param pVCpu The cross context virtual CPU structure.
831 * @param fFlag Flag constant to check and clear (_BIT is appended).
832 */
833#define VMCPU_FF_TEST_AND_CLEAR(pVCpu, fFlag) (ASMAtomicBitTestAndClear(&(pVCpu)->fLocalForcedActions, fFlag##_BIT))
834
835/** @def VM_FF_IS_PENDING_EXCEPT
836 * Checks if one or more force action in the specified set is pending while one
837 * or more other ones are not.
838 *
839 * @param pVM The cross context VM structure.
840 * @param fFlags The flags to check for.
841 * @param fExcpt The flags that should not be set.
842 */
843#define VM_FF_IS_PENDING_EXCEPT(pVM, fFlags, fExcpt) \
844 ( ((pVM)->fGlobalForcedActions & (fFlags)) && !((pVM)->fGlobalForcedActions & (fExcpt)) )
845
846/** @def VM_IS_EMT
847 * Checks if the current thread is the emulation thread (EMT).
848 *
849 * @remark The ring-0 variation will need attention if we expand the ring-0
850 * code to let threads other than EMT mess around with the VM.
851 */
852#ifdef IN_RC
853# define VM_IS_EMT(pVM) true
854#else
855# define VM_IS_EMT(pVM) (VMMGetCpu(pVM) != NULL)
856#endif
857
858/** @def VMCPU_IS_EMT
859 * Checks if the current thread is the emulation thread (EMT) for the specified
860 * virtual CPU.
861 */
862#ifdef IN_RC
863# define VMCPU_IS_EMT(pVCpu) true
864#else
865# define VMCPU_IS_EMT(pVCpu) ((pVCpu) && ((pVCpu) == VMMGetCpu((pVCpu)->CTX_SUFF(pVM))))
866#endif
867
868/** @def VM_ASSERT_EMT
869 * Asserts that the current thread IS the emulation thread (EMT).
870 */
871#ifdef IN_RC
872# define VM_ASSERT_EMT(pVM) Assert(VM_IS_EMT(pVM))
873#elif defined(IN_RING0)
874# define VM_ASSERT_EMT(pVM) Assert(VM_IS_EMT(pVM))
875#else
876# define VM_ASSERT_EMT(pVM) \
877 AssertMsg(VM_IS_EMT(pVM), \
878 ("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd\n", RTThreadNativeSelf(), VMR3GetVMCPUNativeThread(pVM)))
879#endif
880
881/** @def VMCPU_ASSERT_EMT
882 * Asserts that the current thread IS the emulation thread (EMT) of the
883 * specified virtual CPU.
884 */
885#ifdef IN_RC
886# define VMCPU_ASSERT_EMT(pVCpu) Assert(VMCPU_IS_EMT(pVCpu))
887#elif defined(IN_RING0)
888# define VMCPU_ASSERT_EMT(pVCpu) AssertMsg(VMCPU_IS_EMT(pVCpu), \
889 ("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd idCpu=%u\n", \
890 RTThreadNativeSelf(), (pVCpu) ? (pVCpu)->hNativeThreadR0 : 0, \
891 (pVCpu) ? (pVCpu)->idCpu : 0))
892#else
893# define VMCPU_ASSERT_EMT(pVCpu) AssertMsg(VMCPU_IS_EMT(pVCpu), \
894 ("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd idCpu=%#x\n", \
895 RTThreadNativeSelf(), (pVCpu)->hNativeThread, (pVCpu)->idCpu))
896#endif
897
898/** @def VM_ASSERT_EMT_RETURN
899 * Asserts that the current thread IS the emulation thread (EMT) and returns if it isn't.
900 */
901#ifdef IN_RC
902# define VM_ASSERT_EMT_RETURN(pVM, rc) AssertReturn(VM_IS_EMT(pVM), (rc))
903#elif defined(IN_RING0)
904# define VM_ASSERT_EMT_RETURN(pVM, rc) AssertReturn(VM_IS_EMT(pVM), (rc))
905#else
906# define VM_ASSERT_EMT_RETURN(pVM, rc) \
907 AssertMsgReturn(VM_IS_EMT(pVM), \
908 ("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd\n", RTThreadNativeSelf(), VMR3GetVMCPUNativeThread(pVM)), \
909 (rc))
910#endif
911
912/** @def VMCPU_ASSERT_EMT_RETURN
913 * Asserts that the current thread IS the emulation thread (EMT) and returns if it isn't.
914 */
915#ifdef IN_RC
916# define VMCPU_ASSERT_EMT_RETURN(pVCpu, rc) AssertReturn(VMCPU_IS_EMT(pVCpu), (rc))
917#elif defined(IN_RING0)
918# define VMCPU_ASSERT_EMT_RETURN(pVCpu, rc) AssertReturn(VMCPU_IS_EMT(pVCpu), (rc))
919#else
920# define VMCPU_ASSERT_EMT_RETURN(pVCpu, rc) \
921 AssertMsgReturn(VMCPU_IS_EMT(pVCpu), \
922 ("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd idCpu=%#x\n", \
923 RTThreadNativeSelf(), (pVCpu)->hNativeThread, (pVCpu)->idCpu), \
924 (rc))
925#endif
926
927/** @def VMCPU_ASSERT_EMT_OR_GURU
928 * Asserts that the current thread IS the emulation thread (EMT) of the
929 * specified virtual CPU.
930 */
931#if defined(IN_RC) || defined(IN_RING0)
932# define VMCPU_ASSERT_EMT_OR_GURU(pVCpu) Assert( VMCPU_IS_EMT(pVCpu) \
933 || pVCpu->CTX_SUFF(pVM)->enmVMState == VMSTATE_GURU_MEDITATION \
934 || pVCpu->CTX_SUFF(pVM)->enmVMState == VMSTATE_GURU_MEDITATION_LS )
935#else
936# define VMCPU_ASSERT_EMT_OR_GURU(pVCpu) \
937 AssertMsg( VMCPU_IS_EMT(pVCpu) \
938 || pVCpu->CTX_SUFF(pVM)->enmVMState == VMSTATE_GURU_MEDITATION \
939 || pVCpu->CTX_SUFF(pVM)->enmVMState == VMSTATE_GURU_MEDITATION_LS, \
940 ("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd idCpu=%#x\n", \
941 RTThreadNativeSelf(), (pVCpu)->hNativeThread, (pVCpu)->idCpu))
942#endif
943
944/** @def VMCPU_ASSERT_EMT_OR_NOT_RUNNING
945 * Asserts that the current thread IS the emulation thread (EMT) of the
946 * specified virtual CPU or the VM is not running.
947 */
948#if defined(IN_RC) || defined(IN_RING0)
949# define VMCPU_ASSERT_EMT_OR_NOT_RUNNING(pVCpu) \
950 Assert( VMCPU_IS_EMT(pVCpu) \
951 || !VM_IS_RUNNING_FOR_ASSERTIONS_ONLY((pVCpu)->CTX_SUFF(pVM)) )
952#else
953# define VMCPU_ASSERT_EMT_OR_NOT_RUNNING(pVCpu) \
954 AssertMsg( VMCPU_IS_EMT(pVCpu) \
955 || !VM_IS_RUNNING_FOR_ASSERTIONS_ONLY((pVCpu)->CTX_SUFF(pVM)), \
956 ("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd idCpu=%#x\n", \
957 RTThreadNativeSelf(), (pVCpu)->hNativeThread, (pVCpu)->idCpu))
958#endif
959
960/** @def VMSTATE_IS_RUNNING
961 * Checks if the given state indicates a running VM.
962 */
963#define VMSTATE_IS_RUNNING(a_enmVMState) \
964 ( (enmVMState) == VMSTATE_RUNNING \
965 || (enmVMState) == VMSTATE_RUNNING_LS )
966
967/** @def VM_IS_RUNNING_FOR_ASSERTIONS_ONLY
968 * Checks if the VM is running.
969 * @note This is only for pure debug assertions. No AssertReturn or similar!
970 * @sa VMSTATE_IS_RUNNING
971 */
972#define VM_IS_RUNNING_FOR_ASSERTIONS_ONLY(pVM) \
973 ( (pVM)->enmVMState == VMSTATE_RUNNING \
974 || (pVM)->enmVMState == VMSTATE_RUNNING_LS )
975
976/** @def VM_ASSERT_IS_NOT_RUNNING
977 * Asserts that the VM is not running.
978 */
979#if defined(IN_RC) || defined(IN_RING0)
980#define VM_ASSERT_IS_NOT_RUNNING(pVM) Assert(!VM_IS_RUNNING_FOR_ASSERTIONS_ONLY(pVM))
981#else
982#define VM_ASSERT_IS_NOT_RUNNING(pVM) AssertMsg(!VM_IS_RUNNING_FOR_ASSERTIONS_ONLY(pVM), \
983 ("VM is running. enmVMState=%d\n", (pVM)->enmVMState))
984#endif
985
986/** @def VM_ASSERT_EMT0
987 * Asserts that the current thread IS emulation thread \#0 (EMT0).
988 */
989#define VM_ASSERT_EMT0(pVM) VMCPU_ASSERT_EMT(&(pVM)->aCpus[0])
990
991/** @def VM_ASSERT_EMT0_RETURN
992 * Asserts that the current thread IS emulation thread \#0 (EMT0) and returns if
993 * it isn't.
994 */
995#define VM_ASSERT_EMT0_RETURN(pVM, rc) VMCPU_ASSERT_EMT_RETURN(&(pVM)->aCpus[0], (rc))
996
997
998/**
999 * Asserts that the current thread is NOT the emulation thread.
1000 */
1001#define VM_ASSERT_OTHER_THREAD(pVM) \
1002 AssertMsg(!VM_IS_EMT(pVM), ("Not other thread!!\n"))
1003
1004
1005/** @def VM_ASSERT_STATE
1006 * Asserts a certain VM state.
1007 */
1008#define VM_ASSERT_STATE(pVM, _enmState) \
1009 AssertMsg((pVM)->enmVMState == (_enmState), \
1010 ("state %s, expected %s\n", VMGetStateName((pVM)->enmVMState), VMGetStateName(_enmState)))
1011
1012/** @def VM_ASSERT_STATE_RETURN
1013 * Asserts a certain VM state and returns if it doesn't match.
1014 */
1015#define VM_ASSERT_STATE_RETURN(pVM, _enmState, rc) \
1016 AssertMsgReturn((pVM)->enmVMState == (_enmState), \
1017 ("state %s, expected %s\n", VMGetStateName((pVM)->enmVMState), VMGetStateName(_enmState)), \
1018 (rc))
1019
1020/** @def VM_IS_VALID_EXT
1021 * Asserts a the VM handle is valid for external access, i.e. not being destroy
1022 * or terminated. */
1023#define VM_IS_VALID_EXT(pVM) \
1024 ( RT_VALID_ALIGNED_PTR(pVM, PAGE_SIZE) \
1025 && ( (unsigned)(pVM)->enmVMState < (unsigned)VMSTATE_DESTROYING \
1026 || ( (unsigned)(pVM)->enmVMState == (unsigned)VMSTATE_DESTROYING \
1027 && VM_IS_EMT(pVM))) )
1028
1029/** @def VM_ASSERT_VALID_EXT_RETURN
1030 * Asserts a the VM handle is valid for external access, i.e. not being
1031 * destroy or terminated.
1032 */
1033#define VM_ASSERT_VALID_EXT_RETURN(pVM, rc) \
1034 AssertMsgReturn(VM_IS_VALID_EXT(pVM), \
1035 ("pVM=%p state %s\n", (pVM), RT_VALID_ALIGNED_PTR(pVM, PAGE_SIZE) \
1036 ? VMGetStateName(pVM->enmVMState) : ""), \
1037 (rc))
1038
1039/** @def VMCPU_ASSERT_VALID_EXT_RETURN
1040 * Asserts a the VMCPU handle is valid for external access, i.e. not being
1041 * destroy or terminated.
1042 */
1043#define VMCPU_ASSERT_VALID_EXT_RETURN(pVCpu, rc) \
1044 AssertMsgReturn( RT_VALID_ALIGNED_PTR(pVCpu, 64) \
1045 && RT_VALID_ALIGNED_PTR((pVCpu)->CTX_SUFF(pVM), PAGE_SIZE) \
1046 && (unsigned)(pVCpu)->CTX_SUFF(pVM)->enmVMState < (unsigned)VMSTATE_DESTROYING, \
1047 ("pVCpu=%p pVM=%p state %s\n", (pVCpu), RT_VALID_ALIGNED_PTR(pVCpu, 64) ? (pVCpu)->CTX_SUFF(pVM) : NULL, \
1048 RT_VALID_ALIGNED_PTR(pVCpu, 64) && RT_VALID_ALIGNED_PTR((pVCpu)->CTX_SUFF(pVM), PAGE_SIZE) \
1049 ? VMGetStateName((pVCpu)->pVMR3->enmVMState) : ""), \
1050 (rc))
1051
1052#endif /* !VBOX_FOR_DTRACE_LIB */
1053
1054
1055/**
1056 * Helper that HM and NEM uses for safely modifying VM::bMainExecutionEngine.
1057 *
1058 * ONLY HM and NEM MAY USE THIS!
1059 *
1060 * @param a_pVM The cross context VM structure.
1061 * @param a_bValue The new value.
1062 * @internal
1063 */
1064#define VM_SET_MAIN_EXECUTION_ENGINE(a_pVM, a_bValue) \
1065 do { \
1066 *const_cast<uint8_t *>(&(a_pVM)->bMainExecutionEngine) = (a_bValue); \
1067 ASMCompilerBarrier(); /* just to be on the safe side */ \
1068 } while (0)
1069
1070/**
1071 * Checks whether raw-mode is used.
1072 *
1073 * @retval true if either is used.
1074 * @retval false if software virtualization (raw-mode) is used.
1075 *
1076 * @param a_pVM The cross context VM structure.
1077 * @sa VM_IS_HM_OR_NEM_ENABLED, VM_IS_HM_ENABLED, VM_IS_NEM_ENABLED.
1078 * @internal
1079 */
1080#ifdef VBOX_WITH_RAW_MODE
1081# define VM_IS_RAW_MODE_ENABLED(a_pVM) ((a_pVM)->bMainExecutionEngine == VM_EXEC_ENGINE_RAW_MODE)
1082#else
1083# define VM_IS_RAW_MODE_ENABLED(a_pVM) (false)
1084#endif
1085
1086/**
1087 * Checks whether HM (VT-x/AMD-V) or NEM is being used by this VM.
1088 *
1089 * @retval true if either is used.
1090 * @retval false if software virtualization (raw-mode) is used.
1091 *
1092 * @param a_pVM The cross context VM structure.
1093 * @sa VM_IS_RAW_MODE_ENABLED, VM_IS_HM_ENABLED, VM_IS_NEM_ENABLED.
1094 * @internal
1095 */
1096#define VM_IS_HM_OR_NEM_ENABLED(a_pVM) ((a_pVM)->bMainExecutionEngine != VM_EXEC_ENGINE_RAW_MODE)
1097
1098/**
1099 * Checks whether HM is being used by this VM.
1100 *
1101 * @retval true if HM (VT-x/AMD-v) is used.
1102 * @retval false if not.
1103 *
1104 * @param a_pVM The cross context VM structure.
1105 * @sa VM_IS_NEM_ENABLED, VM_IS_RAW_MODE_ENABLED, VM_IS_HM_OR_NEM_ENABLED.
1106 * @internal
1107 */
1108#define VM_IS_HM_ENABLED(a_pVM) ((a_pVM)->bMainExecutionEngine == VM_EXEC_ENGINE_HW_VIRT)
1109
1110/**
1111 * Checks whether NEM is being used by this VM.
1112 *
1113 * @retval true if a native hypervisor API is used.
1114 * @retval false if not.
1115 *
1116 * @param a_pVM The cross context VM structure.
1117 * @sa VM_IS_HM_ENABLED, VM_IS_RAW_MODE_ENABLED, VM_IS_HM_OR_NEM_ENABLED.
1118 * @internal
1119 */
1120#define VM_IS_NEM_ENABLED(a_pVM) ((a_pVM)->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API)
1121
1122
1123/**
1124 * The cross context VM structure.
1125 *
1126 * It contains all the VM data which have to be available in all contexts.
1127 * Even if it contains all the data the idea is to use APIs not to modify all
1128 * the members all around the place. Therefore we make use of unions to hide
1129 * everything which isn't local to the current source module. This means we'll
1130 * have to pay a little bit of attention when adding new members to structures
1131 * in the unions and make sure to keep the padding sizes up to date.
1132 *
1133 * Run 'kmk run-struct-tests' (from src/VBox/VMM if you like) after updating!
1134 */
1135typedef struct VM
1136{
1137 /** The state of the VM.
1138 * This field is read only to everyone except the VM and EM. */
1139 VMSTATE volatile enmVMState;
1140 /** Forced action flags.
1141 * See the VM_FF_* \#defines. Updated atomically.
1142 */
1143 volatile uint32_t fGlobalForcedActions;
1144 /** Pointer to the array of page descriptors for the VM structure allocation. */
1145 R3PTRTYPE(PSUPPAGE) paVMPagesR3;
1146 /** Session handle. For use when calling SUPR0 APIs. */
1147 PSUPDRVSESSION pSession;
1148 /** Pointer to the ring-3 VM structure. */
1149 PUVM pUVM;
1150 /** Ring-3 Host Context VM Pointer. */
1151 R3PTRTYPE(struct VM *) pVMR3;
1152 /** Ring-0 Host Context VM Pointer. */
1153 R0PTRTYPE(struct VM *) pVMR0;
1154 /** Raw-mode Context VM Pointer. */
1155 RCPTRTYPE(struct VM *) pVMRC;
1156
1157 /** The GVM VM handle. Only the GVM should modify this field. */
1158 uint32_t hSelf;
1159 /** Number of virtual CPUs. */
1160 uint32_t cCpus;
1161 /** CPU excution cap (1-100) */
1162 uint32_t uCpuExecutionCap;
1163
1164#ifdef VBOX_BUGREF_9217
1165 /** Size of the VM structure. */
1166 uint32_t cbSelf;
1167 /** Size of the VMCPU structure. */
1168 uint32_t cbVCpu;
1169 /** Structure version number (TBD). */
1170 uint32_t uStructVersion;
1171#else
1172 /** Size of the VM structure including the VMCPU array. */
1173 uint32_t cbSelf;
1174 uint32_t uUnused0;
1175 uint32_t uUnused1;
1176#endif
1177
1178 /** @name Various items that are frequently accessed.
1179 * @{ */
1180 /** The main execution engine, VM_EXEC_ENGINE_XXX.
1181 * This is set early during vmR3InitRing3 by HM or NEM. */
1182 uint8_t const bMainExecutionEngine;
1183
1184 /** Hardware VM support is available and enabled.
1185 * Determined very early during init.
1186 * This is placed here for performance reasons.
1187 * @todo obsoleted by bMainExecutionEngine, eliminate. */
1188 bool fHMEnabled;
1189 /** Hardware VM support requires a minimal raw-mode context.
1190 * This is never set on 64-bit hosts, only 32-bit hosts requires it. */
1191 bool fHMNeedRawModeCtx;
1192
1193 /** Set when this VM is the master FT node.
1194 * @todo This doesn't need to be here, FTM should store it in it's own
1195 * structures instead. */
1196 bool fFaultTolerantMaster;
1197 /** Large page enabled flag.
1198 * @todo This doesn't need to be here, PGM should store it in it's own
1199 * structures instead. */
1200 bool fUseLargePages;
1201 /** @} */
1202
1203 /** Alignment padding. */
1204 uint8_t uPadding1[7];
1205
1206 /** @name Debugging
1207 * @{ */
1208 /** Ring-3 Host Context VM Pointer. */
1209 R3PTRTYPE(RTTRACEBUF) hTraceBufR3;
1210 /** Ring-0 Host Context VM Pointer. */
1211 R0PTRTYPE(RTTRACEBUF) hTraceBufR0;
1212 /** @} */
1213
1214 /** Padding - the unions must be aligned on a 64 bytes boundary. */
1215 uint8_t abAlignment3[24];
1216
1217 /** CPUM part. */
1218 union
1219 {
1220#ifdef VMM_INCLUDED_SRC_include_CPUMInternal_h
1221 struct CPUM s;
1222#endif
1223#ifdef VBOX_INCLUDED_vmm_cpum_h
1224 /** Read only info exposed about the host and guest CPUs. */
1225 struct
1226 {
1227 /** Padding for hidden fields. */
1228 uint8_t abHidden0[64];
1229 /** Host CPU feature information. */
1230 CPUMFEATURES HostFeatures;
1231 /** Guest CPU feature information. */
1232 CPUMFEATURES GuestFeatures;
1233 } const ro;
1234#endif
1235 uint8_t padding[1536]; /* multiple of 64 */
1236 } cpum;
1237
1238 /** VMM part. */
1239 union
1240 {
1241#ifdef VMM_INCLUDED_SRC_include_VMMInternal_h
1242 struct VMM s;
1243#endif
1244 uint8_t padding[1600]; /* multiple of 64 */
1245 } vmm;
1246
1247 /** PGM part. */
1248 union
1249 {
1250#ifdef VMM_INCLUDED_SRC_include_PGMInternal_h
1251 struct PGM s;
1252#endif
1253 uint8_t padding[4096*2+6080]; /* multiple of 64 */
1254 } pgm;
1255
1256 /** HM part. */
1257 union
1258 {
1259#ifdef VMM_INCLUDED_SRC_include_HMInternal_h
1260 struct HM s;
1261#endif
1262 uint8_t padding[5440]; /* multiple of 64 */
1263 } hm;
1264
1265 /** TRPM part. */
1266 union
1267 {
1268#ifdef VMM_INCLUDED_SRC_include_TRPMInternal_h
1269 struct TRPM s;
1270#endif
1271 uint8_t padding[5248]; /* multiple of 64 */
1272 } trpm;
1273
1274 /** SELM part. */
1275 union
1276 {
1277#ifdef VMM_INCLUDED_SRC_include_SELMInternal_h
1278 struct SELM s;
1279#endif
1280 uint8_t padding[768]; /* multiple of 64 */
1281 } selm;
1282
1283 /** MM part. */
1284 union
1285 {
1286#ifdef VMM_INCLUDED_SRC_include_MMInternal_h
1287 struct MM s;
1288#endif
1289 uint8_t padding[192]; /* multiple of 64 */
1290 } mm;
1291
1292 /** PDM part. */
1293 union
1294 {
1295#ifdef VMM_INCLUDED_SRC_include_PDMInternal_h
1296 struct PDM s;
1297#endif
1298 uint8_t padding[1920]; /* multiple of 64 */
1299 } pdm;
1300
1301 /** IOM part. */
1302 union
1303 {
1304#ifdef VMM_INCLUDED_SRC_include_IOMInternal_h
1305 struct IOM s;
1306#endif
1307 uint8_t padding[896]; /* multiple of 64 */
1308 } iom;
1309
1310 /** EM part. */
1311 union
1312 {
1313#ifdef VMM_INCLUDED_SRC_include_EMInternal_h
1314 struct EM s;
1315#endif
1316 uint8_t padding[256]; /* multiple of 64 */
1317 } em;
1318
1319 /** NEM part. */
1320 union
1321 {
1322#ifdef VMM_INCLUDED_SRC_include_NEMInternal_h
1323 struct NEM s;
1324#endif
1325 uint8_t padding[128]; /* multiple of 64 */
1326 } nem;
1327
1328 /** TM part. */
1329 union
1330 {
1331#ifdef VMM_INCLUDED_SRC_include_TMInternal_h
1332 struct TM s;
1333#endif
1334 uint8_t padding[2496]; /* multiple of 64 */
1335 } tm;
1336
1337 /** DBGF part. */
1338 union
1339 {
1340#ifdef VMM_INCLUDED_SRC_include_DBGFInternal_h
1341 struct DBGF s;
1342#endif
1343#ifdef VBOX_INCLUDED_vmm_dbgf_h
1344 /** Read only info exposed about interrupt breakpoints and selected events. */
1345 struct
1346 {
1347 /** Bitmap of enabled hardware interrupt breakpoints. */
1348 uint32_t bmHardIntBreakpoints[256 / 32];
1349 /** Bitmap of enabled software interrupt breakpoints. */
1350 uint32_t bmSoftIntBreakpoints[256 / 32];
1351 /** Bitmap of selected events.
1352 * This includes non-selectable events too for simplicity, we maintain the
1353 * state for some of these, as it may come in handy. */
1354 uint64_t bmSelectedEvents[(DBGFEVENT_END + 63) / 64];
1355 /** Enabled hardware interrupt breakpoints. */
1356 uint32_t cHardIntBreakpoints;
1357 /** Enabled software interrupt breakpoints. */
1358 uint32_t cSoftIntBreakpoints;
1359 /** The number of selected events. */
1360 uint32_t cSelectedEvents;
1361 /** The number of enabled hardware breakpoints. */
1362 uint8_t cEnabledHwBreakpoints;
1363 /** The number of enabled hardware I/O breakpoints. */
1364 uint8_t cEnabledHwIoBreakpoints;
1365 /** The number of enabled INT3 breakpoints. */
1366 uint8_t cEnabledInt3Breakpoints;
1367 uint8_t abPadding[1]; /**< Unused padding space up for grabs. */
1368 } const ro;
1369#endif
1370 uint8_t padding[2432]; /* multiple of 64 */
1371 } dbgf;
1372
1373 /** SSM part. */
1374 union
1375 {
1376#ifdef VMM_INCLUDED_SRC_include_SSMInternal_h
1377 struct SSM s;
1378#endif
1379 uint8_t padding[128]; /* multiple of 64 */
1380 } ssm;
1381
1382 /** FTM part. */
1383 union
1384 {
1385#ifdef VMM_INCLUDED_SRC_include_FTMInternal_h
1386 struct FTM s;
1387#endif
1388 uint8_t padding[512]; /* multiple of 64 */
1389 } ftm;
1390
1391#ifdef VBOX_WITH_REM
1392 /** REM part. */
1393 union
1394 {
1395# ifdef VMM_INCLUDED_SRC_include_REMInternal_h
1396 struct REM s;
1397# endif
1398 uint8_t padding[0x11100]; /* multiple of 64 */
1399 } rem;
1400#endif
1401
1402 union
1403 {
1404#ifdef VMM_INCLUDED_SRC_include_GIMInternal_h
1405 struct GIM s;
1406#endif
1407 uint8_t padding[448]; /* multiple of 64 */
1408 } gim;
1409
1410 union
1411 {
1412#ifdef VMM_INCLUDED_SRC_include_APICInternal_h
1413 struct APIC s;
1414#endif
1415 uint8_t padding[128]; /* multiple of 8 */
1416 } apic;
1417
1418 /* ---- begin small stuff ---- */
1419
1420 /** VM part. */
1421 union
1422 {
1423#ifdef VMM_INCLUDED_SRC_include_VMInternal_h
1424 struct VMINT s;
1425#endif
1426 uint8_t padding[32]; /* multiple of 8 */
1427 } vm;
1428
1429 /** CFGM part. */
1430 union
1431 {
1432#ifdef VMM_INCLUDED_SRC_include_CFGMInternal_h
1433 struct CFGM s;
1434#endif
1435 uint8_t padding[8]; /* multiple of 8 */
1436 } cfgm;
1437
1438#ifdef VBOX_BUGREF_9217
1439 /** Padding for aligning the structure size on a page boundrary. */
1440# ifdef VBOX_WITH_REM
1441 uint8_t abAlignment2[2134 - sizeof(PVMCPUR3) * VMM_MAX_CPU_COUNT];
1442# else
1443 uint8_t abAlignment2[2390 - sizeof(PVMCPUR3) * VMM_MAX_CPU_COUNT];
1444# endif
1445#else
1446 /** Padding for aligning the cpu array on a page boundary. */
1447# ifdef VBOX_WITH_REM
1448 uint8_t abAlignment2[2134];
1449# else
1450 uint8_t abAlignment2[2390];
1451# endif
1452#endif
1453
1454 /* ---- end small stuff ---- */
1455
1456#ifdef VBOX_BUGREF_9217
1457 /** Array of VMCPU pointers. */
1458 PVMCPUR3 apCpus[VMM_MAX_CPU_COUNT];
1459#else
1460 /** VMCPU array for the configured number of virtual CPUs.
1461 * Must be aligned on a page boundary for TLB hit reasons as well as
1462 * alignment of VMCPU members. */
1463 VMCPU aCpus[1];
1464#endif
1465} VM;
1466
1467
1468#ifdef IN_RC
1469RT_C_DECLS_BEGIN
1470
1471/** The VM structure.
1472 * This is imported from the VMMRCBuiltin module, i.e. it's a one of those magic
1473 * globals which we should avoid using.
1474 */
1475extern DECLIMPORT(VM) g_VM;
1476
1477/** The VMCPU structure for virtual CPU \#0.
1478 * This is imported from the VMMRCBuiltin module, i.e. it's a one of those magic
1479 * globals which we should avoid using.
1480 */
1481extern DECLIMPORT(VMCPU) g_VCpu0;
1482
1483RT_C_DECLS_END
1484#endif
1485
1486/** @} */
1487
1488#endif /* !VBOX_INCLUDED_vmm_vm_h */
1489
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