VirtualBox

source: vbox/trunk/include/VBox/vmm/vm.h@ 80253

Last change on this file since 80253 was 80253, checked in by vboxsync, 6 years ago

VMM: Started refactoring VMMAll/* for bugref:9217
  • Property svn:eol-style set to native
  • Property svn:keywords set to Author Date Id Revision
File size: 56.9 KB
Line 
1/** @file
2 * VM - The Virtual Machine, data.
3 */
4
5/*
6 * Copyright (C) 2006-2019 Oracle Corporation
7 *
8 * This file is part of VirtualBox Open Source Edition (OSE), as
9 * available from http://www.virtualbox.org. This file is free software;
10 * you can redistribute it and/or modify it under the terms of the GNU
11 * General Public License (GPL) as published by the Free Software
12 * Foundation, in version 2 as it comes in the "COPYING" file of the
13 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15 *
16 * The contents of this file may alternatively be used under the terms
17 * of the Common Development and Distribution License Version 1.0
18 * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19 * VirtualBox OSE distribution, in which case the provisions of the
20 * CDDL are applicable instead of those of the GPL.
21 *
22 * You may elect to license modified versions of this file under the
23 * terms and conditions of either the GPL or the CDDL or both.
24 */
25
26#ifndef VBOX_INCLUDED_vmm_vm_h
27#define VBOX_INCLUDED_vmm_vm_h
28#ifndef RT_WITHOUT_PRAGMA_ONCE
29# pragma once
30#endif
31
32#ifndef VBOX_FOR_DTRACE_LIB
33# include <iprt/param.h>
34# include <VBox/param.h>
35# include <VBox/types.h>
36# include <VBox/vmm/cpum.h>
37# include <VBox/vmm/stam.h>
38# include <VBox/vmm/vmapi.h>
39# include <VBox/vmm/vmm.h>
40# include <VBox/sup.h>
41#else
42# pragma D depends_on library vbox-types.d
43# pragma D depends_on library CPUMInternal.d
44# define VMM_INCLUDED_SRC_include_CPUMInternal_h
45#endif
46
47
48
49/** @defgroup grp_vm The Virtual Machine
50 * @ingroup grp_vmm
51 * @{
52 */
53
54/**
55 * The state of a Virtual CPU.
56 *
57 * The basic state indicated here is whether the CPU has been started or not. In
58 * addition, there are sub-states when started for assisting scheduling (GVMM
59 * mostly).
60 *
61 * The transition out of the STOPPED state is done by a vmR3PowerOn.
62 * The transition back to the STOPPED state is done by vmR3PowerOff.
63 *
64 * (Alternatively we could let vmR3PowerOn start CPU 0 only and let the SPIP
65 * handling switch on the other CPUs. Then vmR3Reset would stop all but CPU 0.)
66 */
67typedef enum VMCPUSTATE
68{
69 /** The customary invalid zero. */
70 VMCPUSTATE_INVALID = 0,
71
72 /** Virtual CPU has not yet been started. */
73 VMCPUSTATE_STOPPED,
74
75 /** CPU started. */
76 VMCPUSTATE_STARTED,
77 /** CPU started in HM context. */
78 VMCPUSTATE_STARTED_HM,
79 /** Executing guest code and can be poked (RC or STI bits of HM). */
80 VMCPUSTATE_STARTED_EXEC,
81 /** Executing guest code in the recompiler. */
82 VMCPUSTATE_STARTED_EXEC_REM,
83 /** Executing guest code using NEM. */
84 VMCPUSTATE_STARTED_EXEC_NEM,
85 VMCPUSTATE_STARTED_EXEC_NEM_WAIT,
86 VMCPUSTATE_STARTED_EXEC_NEM_CANCELED,
87 /** Halted. */
88 VMCPUSTATE_STARTED_HALTED,
89
90 /** The end of valid virtual CPU states. */
91 VMCPUSTATE_END,
92
93 /** Ensure 32-bit type. */
94 VMCPUSTATE_32BIT_HACK = 0x7fffffff
95} VMCPUSTATE;
96
97/** Enables 64-bit FFs. */
98#define VMCPU_WITH_64_BIT_FFS
99
100
101/**
102 * The cross context virtual CPU structure.
103 *
104 * Run 'kmk run-struct-tests' (from src/VBox/VMM if you like) after updating!
105 */
106typedef struct VMCPU
107{
108 /** @name Volatile per-cpu data.
109 * @{ */
110 /** Per CPU forced action.
111 * See the VMCPU_FF_* \#defines. Updated atomically. */
112#ifdef VMCPU_WITH_64_BIT_FFS
113 uint64_t volatile fLocalForcedActions;
114#else
115 uint32_t volatile fLocalForcedActions;
116 uint32_t fForLocalForcedActionsExpansion;
117#endif
118 /** The CPU state. */
119 VMCPUSTATE volatile enmState;
120
121 /** Which host CPU ID is this EMT running on.
122 * Only valid when in RC or HMR0 with scheduling disabled. */
123 RTCPUID volatile idHostCpu;
124 /** The CPU set index corresponding to idHostCpu, UINT32_MAX if not valid.
125 * @remarks Best to make sure iHostCpuSet shares cache line with idHostCpu! */
126 uint32_t volatile iHostCpuSet;
127 /** Padding up to 64 bytes. */
128 uint8_t abAlignment0[64 - 20];
129 /** @} */
130
131 /** IEM part.
132 * @remarks This comes first as it allows the use of 8-bit immediates for the
133 * first 64 bytes of the structure, reducing code size a wee bit. */
134#ifdef VMM_INCLUDED_SRC_include_IEMInternal_h /* For PDB hacking. */
135 union VMCPUUNIONIEMFULL
136#else
137 union VMCPUUNIONIEMSTUB
138#endif
139 {
140#ifdef VMM_INCLUDED_SRC_include_IEMInternal_h
141 struct IEMCPU s;
142#endif
143 uint8_t padding[18496]; /* multiple of 64 */
144 } iem;
145
146 /** @name Static per-cpu data.
147 * (Putting this after IEM, hoping that it's less frequently used than it.)
148 * @{ */
149 /** Ring-3 Host Context VM Pointer. */
150 PVMR3 pVMR3;
151#ifndef VBOX_BUGREF_9217
152 /** Ring-0 Host Context VM Pointer. */
153 PVMR0 pVMR0;
154#else
155 RTR0PTR R0PtrUnused1;
156#endif
157 /** Raw-mode Context VM Pointer. */
158 uint32_t pVMRC;
159 /** Padding for new raw-mode (long mode). */
160 uint32_t pVMRCPadding;
161 /** Pointer to the ring-3 UVMCPU structure. */
162 PUVMCPU pUVCpu;
163 /** The native thread handle. */
164 RTNATIVETHREAD hNativeThread;
165 /** The native R0 thread handle. (different from the R3 handle!) */
166 RTNATIVETHREAD hNativeThreadR0;
167 /** The CPU ID.
168 * This is the index into the VM::aCpu array. */
169 VMCPUID idCpu;
170
171 /** Align the structures below bit on a 64-byte boundary and make sure it starts
172 * at the same offset in both 64-bit and 32-bit builds.
173 *
174 * @remarks The alignments of the members that are larger than 48 bytes should be
175 * 64-byte for cache line reasons. structs containing small amounts of
176 * data could be lumped together at the end with a < 64 byte padding
177 * following it (to grow into and align the struct size).
178 */
179 uint8_t abAlignment1[64 - 5 * (HC_ARCH_BITS == 32 ? 4 : 8) - 8 - 4];
180 /** @} */
181
182 /** HM part. */
183 union VMCPUUNIONHM
184 {
185#ifdef VMM_INCLUDED_SRC_include_HMInternal_h
186 struct HMCPU s;
187#endif
188 uint8_t padding[5888]; /* multiple of 64 */
189 } hm;
190
191 /** NEM part. */
192 union VMCPUUNIONNEM
193 {
194#ifdef VMM_INCLUDED_SRC_include_NEMInternal_h
195 struct NEMCPU s;
196#endif
197 uint8_t padding[512]; /* multiple of 64 */
198 } nem;
199
200 /** TRPM part. */
201 union VMCPUUNIONTRPM
202 {
203#ifdef VMM_INCLUDED_SRC_include_TRPMInternal_h
204 struct TRPMCPU s;
205#endif
206 uint8_t padding[128]; /* multiple of 64 */
207 } trpm;
208
209 /** TM part. */
210 union VMCPUUNIONTM
211 {
212#ifdef VMM_INCLUDED_SRC_include_TMInternal_h
213 struct TMCPU s;
214#endif
215 uint8_t padding[5760]; /* multiple of 64 */
216 } tm;
217
218 /** VMM part. */
219 union VMCPUUNIONVMM
220 {
221#ifdef VMM_INCLUDED_SRC_include_VMMInternal_h
222 struct VMMCPU s;
223#endif
224 uint8_t padding[896]; /* multiple of 64 */
225 } vmm;
226
227 /** PDM part. */
228 union VMCPUUNIONPDM
229 {
230#ifdef VMM_INCLUDED_SRC_include_PDMInternal_h
231 struct PDMCPU s;
232#endif
233 uint8_t padding[256]; /* multiple of 64 */
234 } pdm;
235
236 /** IOM part. */
237 union VMCPUUNIONIOM
238 {
239#ifdef VMM_INCLUDED_SRC_include_IOMInternal_h
240 struct IOMCPU s;
241#endif
242 uint8_t padding[512]; /* multiple of 64 */
243 } iom;
244
245 /** DBGF part.
246 * @todo Combine this with other tiny structures. */
247 union VMCPUUNIONDBGF
248 {
249#ifdef VMM_INCLUDED_SRC_include_DBGFInternal_h
250 struct DBGFCPU s;
251#endif
252 uint8_t padding[256]; /* multiple of 64 */
253 } dbgf;
254
255 /** GIM part. */
256 union VMCPUUNIONGIM
257 {
258#ifdef VMM_INCLUDED_SRC_include_GIMInternal_h
259 struct GIMCPU s;
260#endif
261 uint8_t padding[512]; /* multiple of 64 */
262 } gim;
263
264 /** APIC part. */
265 union VMCPUUNIONAPIC
266 {
267#ifdef VMM_INCLUDED_SRC_include_APICInternal_h
268 struct APICCPU s;
269#endif
270 uint8_t padding[1792]; /* multiple of 64 */
271 } apic;
272
273 /*
274 * Some less frequently used global members that doesn't need to take up
275 * precious space at the head of the structure.
276 */
277
278 /** Trace groups enable flags. */
279 uint32_t fTraceGroups; /* 64 / 44 */
280 /** State data for use by ad hoc profiling. */
281 uint32_t uAdHoc;
282 /** Profiling samples for use by ad hoc profiling. */
283 STAMPROFILEADV aStatAdHoc[8]; /* size: 40*8 = 320 */
284
285 /** Align the following members on page boundary. */
286 uint8_t abAlignment2[1400];
287
288 /** PGM part. */
289 union VMCPUUNIONPGM
290 {
291#ifdef VMM_INCLUDED_SRC_include_PGMInternal_h
292 struct PGMCPU s;
293#endif
294 uint8_t padding[4096]; /* multiple of 4096 */
295 } pgm;
296
297 /** CPUM part. */
298 union VMCPUUNIONCPUM
299 {
300#ifdef VMM_INCLUDED_SRC_include_CPUMInternal_h
301 struct CPUMCPU s;
302#endif
303#ifdef VMCPU_INCL_CPUM_GST_CTX
304 /** The guest CPUM context for direct use by execution engines.
305 * This is not for general consumption, but for HM, REM, IEM, and maybe a few
306 * others. The rest will use the function based CPUM API. */
307 CPUMCTX GstCtx;
308#endif
309 uint8_t padding[4096]; /* multiple of 4096 */
310 } cpum;
311
312 /** EM part. */
313 union VMCPUUNIONEM
314 {
315#ifdef VMM_INCLUDED_SRC_include_EMInternal_h
316 struct EMCPU s;
317#endif
318 uint8_t padding[40960]; /* multiple of 4096 */
319 } em;
320} VMCPU;
321
322
323#ifndef VBOX_FOR_DTRACE_LIB
324AssertCompileSizeAlignment(VMCPU, 4096);
325
326/** @name Operations on VMCPU::enmState
327 * @{ */
328/** Gets the VMCPU state. */
329#define VMCPU_GET_STATE(pVCpu) ( (pVCpu)->enmState )
330/** Sets the VMCPU state. */
331#define VMCPU_SET_STATE(pVCpu, enmNewState) \
332 ASMAtomicWriteU32((uint32_t volatile *)&(pVCpu)->enmState, (enmNewState))
333/** Cmpares and sets the VMCPU state. */
334#define VMCPU_CMPXCHG_STATE(pVCpu, enmNewState, enmOldState) \
335 ASMAtomicCmpXchgU32((uint32_t volatile *)&(pVCpu)->enmState, (enmNewState), (enmOldState))
336/** Checks the VMCPU state. */
337#ifdef VBOX_STRICT
338# define VMCPU_ASSERT_STATE(pVCpu, enmExpectedState) \
339 do { \
340 VMCPUSTATE enmState = VMCPU_GET_STATE(pVCpu); \
341 AssertMsg(enmState == (enmExpectedState), \
342 ("enmState=%d enmExpectedState=%d idCpu=%u\n", \
343 enmState, enmExpectedState, (pVCpu)->idCpu)); \
344 } while (0)
345#else
346# define VMCPU_ASSERT_STATE(pVCpu, enmExpectedState) do { } while (0)
347#endif
348/** Tests if the state means that the CPU is started. */
349#define VMCPUSTATE_IS_STARTED(enmState) ( (enmState) > VMCPUSTATE_STOPPED )
350/** Tests if the state means that the CPU is stopped. */
351#define VMCPUSTATE_IS_STOPPED(enmState) ( (enmState) == VMCPUSTATE_STOPPED )
352/** @} */
353
354
355/** The name of the raw-mode context VMM Core module. */
356#define VMMRC_MAIN_MODULE_NAME "VMMRC.rc"
357/** The name of the ring-0 context VMM Core module. */
358#define VMMR0_MAIN_MODULE_NAME "VMMR0.r0"
359
360
361/** VM Forced Action Flags.
362 *
363 * Use the VM_FF_SET() and VM_FF_CLEAR() macros to change the force
364 * action mask of a VM.
365 *
366 * Available VM bits:
367 * 0, 1, 5, 6, 7, 13, 14, 15, 16, 17, 21, 22, 23, 24, 25, 26, 27, 28, 30
368 *
369 *
370 * Available VMCPU bits:
371 * 14, 15, 36 to 63
372 *
373 * @todo If we run low on VMCPU, we may consider merging the SELM bits
374 *
375 * @{
376 */
377/** The virtual sync clock has been stopped, go to TM until it has been
378 * restarted... */
379#define VM_FF_TM_VIRTUAL_SYNC RT_BIT_32(VM_FF_TM_VIRTUAL_SYNC_BIT)
380#define VM_FF_TM_VIRTUAL_SYNC_BIT 2
381/** PDM Queues are pending. */
382#define VM_FF_PDM_QUEUES RT_BIT_32(VM_FF_PDM_QUEUES_BIT)
383/** The bit number for VM_FF_PDM_QUEUES. */
384#define VM_FF_PDM_QUEUES_BIT 3
385/** PDM DMA transfers are pending. */
386#define VM_FF_PDM_DMA RT_BIT_32(VM_FF_PDM_DMA_BIT)
387/** The bit number for VM_FF_PDM_DMA. */
388#define VM_FF_PDM_DMA_BIT 4
389/** This action forces the VM to call DBGF so DBGF can service debugger
390 * requests in the emulation thread.
391 * This action flag stays asserted till DBGF clears it.*/
392#define VM_FF_DBGF RT_BIT_32(VM_FF_DBGF_BIT)
393/** The bit number for VM_FF_DBGF. */
394#define VM_FF_DBGF_BIT 8
395/** This action forces the VM to service pending requests from other
396 * thread or requests which must be executed in another context. */
397#define VM_FF_REQUEST RT_BIT_32(VM_FF_REQUEST_BIT)
398#define VM_FF_REQUEST_BIT 9
399/** Check for VM state changes and take appropriate action. */
400#define VM_FF_CHECK_VM_STATE RT_BIT_32(VM_FF_CHECK_VM_STATE_BIT)
401/** The bit number for VM_FF_CHECK_VM_STATE. */
402#define VM_FF_CHECK_VM_STATE_BIT 10
403/** Reset the VM. (postponed) */
404#define VM_FF_RESET RT_BIT_32(VM_FF_RESET_BIT)
405/** The bit number for VM_FF_RESET. */
406#define VM_FF_RESET_BIT 11
407/** EMT rendezvous in VMM. */
408#define VM_FF_EMT_RENDEZVOUS RT_BIT_32(VM_FF_EMT_RENDEZVOUS_BIT)
409/** The bit number for VM_FF_EMT_RENDEZVOUS. */
410#define VM_FF_EMT_RENDEZVOUS_BIT 12
411
412/** PGM needs to allocate handy pages. */
413#define VM_FF_PGM_NEED_HANDY_PAGES RT_BIT_32(VM_FF_PGM_NEED_HANDY_PAGES_BIT)
414#define VM_FF_PGM_NEED_HANDY_PAGES_BIT 18
415/** PGM is out of memory.
416 * Abandon all loops and code paths which can be resumed and get up to the EM
417 * loops. */
418#define VM_FF_PGM_NO_MEMORY RT_BIT_32(VM_FF_PGM_NO_MEMORY_BIT)
419#define VM_FF_PGM_NO_MEMORY_BIT 19
420 /** PGM is about to perform a lightweight pool flush
421 * Guest SMP: all EMT threads should return to ring 3
422 */
423#define VM_FF_PGM_POOL_FLUSH_PENDING RT_BIT_32(VM_FF_PGM_POOL_FLUSH_PENDING_BIT)
424#define VM_FF_PGM_POOL_FLUSH_PENDING_BIT 20
425/** REM needs to be informed about handler changes. */
426#define VM_FF_REM_HANDLER_NOTIFY RT_BIT_32(VM_FF_REM_HANDLER_NOTIFY_BIT)
427/** The bit number for VM_FF_REM_HANDLER_NOTIFY. */
428#define VM_FF_REM_HANDLER_NOTIFY_BIT 29
429/** Suspend the VM - debug only. */
430#define VM_FF_DEBUG_SUSPEND RT_BIT_32(VM_FF_DEBUG_SUSPEND_BIT)
431#define VM_FF_DEBUG_SUSPEND_BIT 31
432
433
434/** This action forces the VM to check any pending interrupts on the APIC. */
435#define VMCPU_FF_INTERRUPT_APIC RT_BIT_64(VMCPU_FF_INTERRUPT_APIC_BIT)
436#define VMCPU_FF_INTERRUPT_APIC_BIT 0
437/** This action forces the VM to check any pending interrups on the PIC. */
438#define VMCPU_FF_INTERRUPT_PIC RT_BIT_64(VMCPU_FF_INTERRUPT_PIC_BIT)
439#define VMCPU_FF_INTERRUPT_PIC_BIT 1
440/** This action forces the VM to schedule and run pending timer (TM).
441 * @remarks Don't move - PATM compatibility. */
442#define VMCPU_FF_TIMER RT_BIT_64(VMCPU_FF_TIMER_BIT)
443#define VMCPU_FF_TIMER_BIT 2
444/** This action forces the VM to check any pending NMIs. */
445#define VMCPU_FF_INTERRUPT_NMI RT_BIT_64(VMCPU_FF_INTERRUPT_NMI_BIT)
446#define VMCPU_FF_INTERRUPT_NMI_BIT 3
447/** This action forces the VM to check any pending SMIs. */
448#define VMCPU_FF_INTERRUPT_SMI RT_BIT_64(VMCPU_FF_INTERRUPT_SMI_BIT)
449#define VMCPU_FF_INTERRUPT_SMI_BIT 4
450/** PDM critical section unlocking is pending, process promptly upon return to R3. */
451#define VMCPU_FF_PDM_CRITSECT RT_BIT_64(VMCPU_FF_PDM_CRITSECT_BIT)
452#define VMCPU_FF_PDM_CRITSECT_BIT 5
453/** Special EM internal force flag that is used by EMUnhaltAndWakeUp() to force
454 * the virtual CPU out of the next (/current) halted state. It is not processed
455 * nor cleared by emR3ForcedActions (similar to VMCPU_FF_BLOCK_NMIS), instead it
456 * is cleared the next time EM leaves the HALTED state. */
457#define VMCPU_FF_UNHALT RT_BIT_64(VMCPU_FF_UNHALT_BIT)
458#define VMCPU_FF_UNHALT_BIT 6
459/** Pending IEM action (mask). */
460#define VMCPU_FF_IEM RT_BIT_64(VMCPU_FF_IEM_BIT)
461/** Pending IEM action (bit number). */
462#define VMCPU_FF_IEM_BIT 7
463/** Pending APIC action (bit number). */
464#define VMCPU_FF_UPDATE_APIC_BIT 8
465/** This action forces the VM to update APIC's asynchronously arrived
466 * interrupts as pending interrupts. */
467#define VMCPU_FF_UPDATE_APIC RT_BIT_64(VMCPU_FF_UPDATE_APIC_BIT)
468/** This action forces the VM to service pending requests from other
469 * thread or requests which must be executed in another context. */
470#define VMCPU_FF_REQUEST RT_BIT_64(VMCPU_FF_REQUEST_BIT)
471#define VMCPU_FF_REQUEST_BIT 9
472/** Pending DBGF event (alternative to passing VINF_EM_DBG_EVENT around). */
473#define VMCPU_FF_DBGF RT_BIT_64(VMCPU_FF_DBGF_BIT)
474/** The bit number for VMCPU_FF_DBGF. */
475#define VMCPU_FF_DBGF_BIT 10
476/** This action forces the VM to service any pending updates to CR3 (used only
477 * by HM). */
478/** Hardware virtualized nested-guest interrupt pending. */
479#define VMCPU_FF_INTERRUPT_NESTED_GUEST RT_BIT_64(VMCPU_FF_INTERRUPT_NESTED_GUEST_BIT)
480#define VMCPU_FF_INTERRUPT_NESTED_GUEST_BIT 11
481#define VMCPU_FF_HM_UPDATE_CR3 RT_BIT_64(VMCPU_FF_HM_UPDATE_CR3_BIT)
482#define VMCPU_FF_HM_UPDATE_CR3_BIT 12
483/** This action forces the VM to service any pending updates to PAE PDPEs (used
484 * only by HM). */
485#define VMCPU_FF_HM_UPDATE_PAE_PDPES RT_BIT_64(VMCPU_FF_HM_UPDATE_PAE_PDPES_BIT)
486#define VMCPU_FF_HM_UPDATE_PAE_PDPES_BIT 13
487/** This action forces the VM to resync the page tables before going
488 * back to execute guest code. (GLOBAL FLUSH) */
489#define VMCPU_FF_PGM_SYNC_CR3 RT_BIT_64(VMCPU_FF_PGM_SYNC_CR3_BIT)
490#define VMCPU_FF_PGM_SYNC_CR3_BIT 16
491/** Same as VM_FF_PGM_SYNC_CR3 except that global pages can be skipped.
492 * (NON-GLOBAL FLUSH) */
493#define VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL RT_BIT_64(VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL_BIT)
494#define VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL_BIT 17
495/** Check for pending TLB shootdown actions (deprecated)
496 * Reserved for furture HM re-use if necessary / safe.
497 * Consumer: HM */
498#define VMCPU_FF_TLB_SHOOTDOWN_UNUSED RT_BIT_64(VMCPU_FF_TLB_SHOOTDOWN_UNUSED_BIT)
499#define VMCPU_FF_TLB_SHOOTDOWN_UNUSED_BIT 18
500/** Check for pending TLB flush action.
501 * Consumer: HM
502 * @todo rename to VMCPU_FF_HM_TLB_FLUSH */
503#define VMCPU_FF_TLB_FLUSH RT_BIT_64(VMCPU_FF_TLB_FLUSH_BIT)
504/** The bit number for VMCPU_FF_TLB_FLUSH. */
505#define VMCPU_FF_TLB_FLUSH_BIT 19
506/* 20 used to be VMCPU_FF_TRPM_SYNC_IDT (raw-mode only). */
507/* 21 used to be VMCPU_FF_SELM_SYNC_TSS (raw-mode only). */
508/* 22 used to be VMCPU_FF_SELM_SYNC_GDT (raw-mode only). */
509/* 23 used to be VMCPU_FF_SELM_SYNC_LDT (raw-mode only). */
510/** Inhibit interrupts pending. See EMGetInhibitInterruptsPC(). */
511#define VMCPU_FF_INHIBIT_INTERRUPTS RT_BIT_64(VMCPU_FF_INHIBIT_INTERRUPTS_BIT)
512#define VMCPU_FF_INHIBIT_INTERRUPTS_BIT 24
513/** Block injection of non-maskable interrupts to the guest. */
514#define VMCPU_FF_BLOCK_NMIS RT_BIT_64(VMCPU_FF_BLOCK_NMIS_BIT)
515#define VMCPU_FF_BLOCK_NMIS_BIT 25
516/** Force return to Ring-3. */
517#define VMCPU_FF_TO_R3 RT_BIT_64(VMCPU_FF_TO_R3_BIT)
518#define VMCPU_FF_TO_R3_BIT 28
519/** Force return to ring-3 to service pending I/O or MMIO write.
520 * This is a backup for mechanism VINF_IOM_R3_IOPORT_COMMIT_WRITE and
521 * VINF_IOM_R3_MMIO_COMMIT_WRITE, allowing VINF_EM_DBG_BREAKPOINT and similar
522 * status codes to be propagated at the same time without loss. */
523#define VMCPU_FF_IOM RT_BIT_64(VMCPU_FF_IOM_BIT)
524#define VMCPU_FF_IOM_BIT 29
525/* 30 used to be VMCPU_FF_CPUM */
526/** VMX-preemption timer in effect. */
527#define VMCPU_FF_VMX_PREEMPT_TIMER RT_BIT_64(VMCPU_FF_VMX_PREEMPT_TIMER_BIT)
528#define VMCPU_FF_VMX_PREEMPT_TIMER_BIT 31
529/** Pending MTF (Monitor Trap Flag) event. */
530#define VMCPU_FF_VMX_MTF RT_BIT_64(VMCPU_FF_VMX_MTF_BIT)
531#define VMCPU_FF_VMX_MTF_BIT 32
532/** VMX APIC-write emulation pending. */
533#define VMCPU_FF_VMX_APIC_WRITE RT_BIT_64(VMCPU_FF_VMX_APIC_WRITE_BIT)
534#define VMCPU_FF_VMX_APIC_WRITE_BIT 33
535/** VMX interrupt-window event pending. */
536#define VMCPU_FF_VMX_INT_WINDOW RT_BIT_64(VMCPU_FF_VMX_INT_WINDOW_BIT)
537#define VMCPU_FF_VMX_INT_WINDOW_BIT 34
538/** VMX NMI-window event pending. */
539#define VMCPU_FF_VMX_NMI_WINDOW RT_BIT_64(VMCPU_FF_VMX_NMI_WINDOW_BIT)
540#define VMCPU_FF_VMX_NMI_WINDOW_BIT 35
541
542
543/** Externally VM forced actions. Used to quit the idle/wait loop. */
544#define VM_FF_EXTERNAL_SUSPENDED_MASK ( VM_FF_CHECK_VM_STATE | VM_FF_DBGF | VM_FF_REQUEST | VM_FF_EMT_RENDEZVOUS )
545/** Externally VMCPU forced actions. Used to quit the idle/wait loop. */
546#define VMCPU_FF_EXTERNAL_SUSPENDED_MASK ( VMCPU_FF_REQUEST | VMCPU_FF_DBGF )
547
548/** Externally forced VM actions. Used to quit the idle/wait loop. */
549#define VM_FF_EXTERNAL_HALTED_MASK ( VM_FF_CHECK_VM_STATE | VM_FF_DBGF | VM_FF_REQUEST \
550 | VM_FF_PDM_QUEUES | VM_FF_PDM_DMA | VM_FF_EMT_RENDEZVOUS )
551/** Externally forced VMCPU actions. Used to quit the idle/wait loop. */
552#define VMCPU_FF_EXTERNAL_HALTED_MASK ( VMCPU_FF_UPDATE_APIC | VMCPU_FF_INTERRUPT_APIC | VMCPU_FF_INTERRUPT_PIC \
553 | VMCPU_FF_REQUEST | VMCPU_FF_INTERRUPT_NMI | VMCPU_FF_INTERRUPT_SMI \
554 | VMCPU_FF_UNHALT | VMCPU_FF_TIMER | VMCPU_FF_DBGF \
555 | VMCPU_FF_INTERRUPT_NESTED_GUEST)
556
557/** High priority VM pre-execution actions. */
558#define VM_FF_HIGH_PRIORITY_PRE_MASK ( VM_FF_CHECK_VM_STATE | VM_FF_DBGF | VM_FF_TM_VIRTUAL_SYNC \
559 | VM_FF_DEBUG_SUSPEND | VM_FF_PGM_NEED_HANDY_PAGES | VM_FF_PGM_NO_MEMORY \
560 | VM_FF_EMT_RENDEZVOUS )
561/** High priority VMCPU pre-execution actions. */
562#define VMCPU_FF_HIGH_PRIORITY_PRE_MASK ( VMCPU_FF_TIMER | VMCPU_FF_INTERRUPT_APIC | VMCPU_FF_INTERRUPT_PIC \
563 | VMCPU_FF_UPDATE_APIC | VMCPU_FF_INHIBIT_INTERRUPTS | VMCPU_FF_DBGF \
564 | VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL \
565 | VMCPU_FF_INTERRUPT_NESTED_GUEST | VMCPU_FF_VMX_MTF | VMCPU_FF_VMX_APIC_WRITE \
566 | VMCPU_FF_VMX_PREEMPT_TIMER | VMCPU_FF_VMX_NMI_WINDOW | VMCPU_FF_VMX_INT_WINDOW )
567
568/** High priority VM pre raw-mode execution mask. */
569#define VM_FF_HIGH_PRIORITY_PRE_RAW_MASK ( VM_FF_PGM_NEED_HANDY_PAGES | VM_FF_PGM_NO_MEMORY )
570/** High priority VMCPU pre raw-mode execution mask. */
571#define VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK ( VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL \
572 | VMCPU_FF_INHIBIT_INTERRUPTS )
573
574/** High priority post-execution actions. */
575#define VM_FF_HIGH_PRIORITY_POST_MASK ( VM_FF_PGM_NO_MEMORY )
576/** High priority post-execution actions. */
577#define VMCPU_FF_HIGH_PRIORITY_POST_MASK ( VMCPU_FF_PDM_CRITSECT \
578 | VMCPU_FF_HM_UPDATE_CR3 | VMCPU_FF_HM_UPDATE_PAE_PDPES \
579 | VMCPU_FF_IEM | VMCPU_FF_IOM )
580
581/** Normal priority VM post-execution actions. */
582#define VM_FF_NORMAL_PRIORITY_POST_MASK ( VM_FF_CHECK_VM_STATE | VM_FF_DBGF | VM_FF_RESET \
583 | VM_FF_PGM_NO_MEMORY | VM_FF_EMT_RENDEZVOUS)
584/** Normal priority VMCPU post-execution actions. */
585#define VMCPU_FF_NORMAL_PRIORITY_POST_MASK ( VMCPU_FF_DBGF )
586
587/** Normal priority VM actions. */
588#define VM_FF_NORMAL_PRIORITY_MASK ( VM_FF_REQUEST | VM_FF_PDM_QUEUES | VM_FF_PDM_DMA \
589 | VM_FF_REM_HANDLER_NOTIFY | VM_FF_EMT_RENDEZVOUS)
590/** Normal priority VMCPU actions. */
591#define VMCPU_FF_NORMAL_PRIORITY_MASK ( VMCPU_FF_REQUEST )
592
593/** Flags to clear before resuming guest execution. */
594#define VMCPU_FF_RESUME_GUEST_MASK ( VMCPU_FF_TO_R3 )
595
596
597/** VM flags that cause the REP[|NE|E] STRINS loops to yield immediately. */
598#define VM_FF_HIGH_PRIORITY_POST_REPSTR_MASK ( VM_FF_TM_VIRTUAL_SYNC | VM_FF_PGM_NEED_HANDY_PAGES | VM_FF_PGM_NO_MEMORY \
599 | VM_FF_EMT_RENDEZVOUS | VM_FF_PGM_POOL_FLUSH_PENDING | VM_FF_RESET)
600/** VM flags that cause the REP[|NE|E] STRINS loops to yield. */
601#define VM_FF_YIELD_REPSTR_MASK ( VM_FF_HIGH_PRIORITY_POST_REPSTR_MASK \
602 | VM_FF_PDM_QUEUES | VM_FF_PDM_DMA | VM_FF_DBGF | VM_FF_DEBUG_SUSPEND )
603/** VMCPU flags that cause the REP[|NE|E] STRINS loops to yield immediately. */
604#ifdef IN_RING3
605# define VMCPU_FF_HIGH_PRIORITY_POST_REPSTR_MASK ( VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL | VMCPU_FF_DBGF \
606 | VMCPU_FF_VMX_MTF )
607#else
608# define VMCPU_FF_HIGH_PRIORITY_POST_REPSTR_MASK ( VMCPU_FF_TO_R3 | VMCPU_FF_IEM | VMCPU_FF_IOM | VMCPU_FF_PGM_SYNC_CR3 \
609 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL | VMCPU_FF_DBGF | VMCPU_FF_VMX_MTF )
610#endif
611/** VMCPU flags that cause the REP[|NE|E] STRINS loops to yield, interrupts
612 * enabled. */
613#define VMCPU_FF_YIELD_REPSTR_MASK ( VMCPU_FF_HIGH_PRIORITY_POST_REPSTR_MASK \
614 | VMCPU_FF_INTERRUPT_APIC | VMCPU_FF_UPDATE_APIC | VMCPU_FF_INTERRUPT_PIC \
615 | VMCPU_FF_INTERRUPT_NMI | VMCPU_FF_INTERRUPT_SMI | VMCPU_FF_PDM_CRITSECT \
616 | VMCPU_FF_TIMER | VMCPU_FF_REQUEST \
617 | VMCPU_FF_INTERRUPT_NESTED_GUEST )
618/** VMCPU flags that cause the REP[|NE|E] STRINS loops to yield, interrupts
619 * disabled. */
620#define VMCPU_FF_YIELD_REPSTR_NOINT_MASK ( VMCPU_FF_YIELD_REPSTR_MASK \
621 & ~( VMCPU_FF_INTERRUPT_APIC | VMCPU_FF_UPDATE_APIC | VMCPU_FF_INTERRUPT_PIC \
622 | VMCPU_FF_INTERRUPT_NESTED_GUEST) )
623
624/** VM Flags that cause the HM loops to go back to ring-3. */
625#define VM_FF_HM_TO_R3_MASK ( VM_FF_TM_VIRTUAL_SYNC | VM_FF_PGM_NEED_HANDY_PAGES | VM_FF_PGM_NO_MEMORY \
626 | VM_FF_PDM_QUEUES | VM_FF_EMT_RENDEZVOUS)
627/** VMCPU Flags that cause the HM loops to go back to ring-3. */
628#define VMCPU_FF_HM_TO_R3_MASK ( VMCPU_FF_TO_R3 | VMCPU_FF_TIMER | VMCPU_FF_PDM_CRITSECT \
629 | VMCPU_FF_IEM | VMCPU_FF_IOM)
630
631/** High priority ring-0 VM pre HM-mode execution mask. */
632#define VM_FF_HP_R0_PRE_HM_MASK (VM_FF_HM_TO_R3_MASK | VM_FF_REQUEST | VM_FF_PGM_POOL_FLUSH_PENDING | VM_FF_PDM_DMA)
633/** High priority ring-0 VMCPU pre HM-mode execution mask. */
634#define VMCPU_FF_HP_R0_PRE_HM_MASK ( VMCPU_FF_HM_TO_R3_MASK | VMCPU_FF_PGM_SYNC_CR3 \
635 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL | VMCPU_FF_REQUEST \
636 | VMCPU_FF_VMX_APIC_WRITE | VMCPU_FF_VMX_MTF | VMCPU_FF_VMX_PREEMPT_TIMER)
637/** High priority ring-0 VM pre HM-mode execution mask, single stepping. */
638#define VM_FF_HP_R0_PRE_HM_STEP_MASK (VM_FF_HP_R0_PRE_HM_MASK & ~( VM_FF_TM_VIRTUAL_SYNC | VM_FF_PDM_QUEUES \
639 | VM_FF_EMT_RENDEZVOUS | VM_FF_REQUEST \
640 | VM_FF_PDM_DMA) )
641/** High priority ring-0 VMCPU pre HM-mode execution mask, single stepping. */
642#define VMCPU_FF_HP_R0_PRE_HM_STEP_MASK (VMCPU_FF_HP_R0_PRE_HM_MASK & ~( VMCPU_FF_TO_R3 | VMCPU_FF_TIMER \
643 | VMCPU_FF_PDM_CRITSECT | VMCPU_FF_REQUEST) )
644
645/** All the forced VM flags. */
646#define VM_FF_ALL_MASK (UINT32_MAX)
647/** All the forced VMCPU flags. */
648#define VMCPU_FF_ALL_MASK (UINT32_MAX)
649
650/** All the forced VM flags except those related to raw-mode and hardware
651 * assisted execution. */
652#define VM_FF_ALL_REM_MASK (~(VM_FF_HIGH_PRIORITY_PRE_RAW_MASK) | VM_FF_PGM_NEED_HANDY_PAGES | VM_FF_PGM_NO_MEMORY)
653/** All the forced VMCPU flags except those related to raw-mode and hardware
654 * assisted execution. */
655#define VMCPU_FF_ALL_REM_MASK (~(VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK | VMCPU_FF_PDM_CRITSECT | VMCPU_FF_TLB_FLUSH))
656/** @} */
657
658/** @def VM_FF_SET
659 * Sets a single force action flag.
660 *
661 * @param pVM The cross context VM structure.
662 * @param fFlag The flag to set.
663 */
664#define VM_FF_SET(pVM, fFlag) do { \
665 AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
666 AssertCompile((fFlag) == RT_BIT_32(fFlag##_BIT)); \
667 ASMAtomicOrU32(&(pVM)->fGlobalForcedActions, (fFlag)); \
668 } while (0)
669
670/** @def VMCPU_FF_SET
671 * Sets a single force action flag for the given VCPU.
672 *
673 * @param pVCpu The cross context virtual CPU structure.
674 * @param fFlag The flag to set.
675 * @sa VMCPU_FF_SET_MASK
676 */
677#ifdef VMCPU_WITH_64_BIT_FFS
678# define VMCPU_FF_SET(pVCpu, fFlag) do { \
679 AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
680 AssertCompile((fFlag) == RT_BIT_64(fFlag##_BIT)); \
681 ASMAtomicBitSet(&(pVCpu)->fLocalForcedActions, fFlag##_BIT); \
682 } while (0)
683#else
684# define VMCPU_FF_SET(pVCpu, fFlag) do { \
685 AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
686 AssertCompile((fFlag) == RT_BIT_32(fFlag##_BIT)); \
687 ASMAtomicOrU32(&(pVCpu)->fLocalForcedActions, (fFlag)); \
688 } while (0)
689#endif
690
691/** @def VMCPU_FF_SET_MASK
692 * Sets a two or more force action flag for the given VCPU.
693 *
694 * @param pVCpu The cross context virtual CPU structure.
695 * @param fFlags The flags to set.
696 * @sa VMCPU_FF_SET
697 */
698#ifdef VMCPU_WITH_64_BIT_FFS
699# if ARCH_BITS > 32
700# define VMCPU_FF_SET_MASK(pVCpu, fFlags) \
701 do { ASMAtomicOrU64(&pVCpu->fLocalForcedActions, (fFlags)); } while (0)
702# else
703# define VMCPU_FF_SET_MASK(pVCpu, fFlags) do { \
704 if (!((fFlags) >> 32)) ASMAtomicOrU32((uint32_t volatile *)&pVCpu->fLocalForcedActions, (uint32_t)(fFlags)); \
705 else ASMAtomicOrU64(&pVCpu->fLocalForcedActions, (fFlags)); \
706 } while (0)
707# endif
708#else
709# define VMCPU_FF_SET_MASK(pVCpu, fFlags) \
710 do { ASMAtomicOrU32(&pVCpu->fLocalForcedActions, (fFlags)); } while (0)
711#endif
712
713/** @def VM_FF_CLEAR
714 * Clears a single force action flag.
715 *
716 * @param pVM The cross context VM structure.
717 * @param fFlag The flag to clear.
718 */
719#define VM_FF_CLEAR(pVM, fFlag) do { \
720 AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
721 AssertCompile((fFlag) == RT_BIT_32(fFlag##_BIT)); \
722 ASMAtomicAndU32(&(pVM)->fGlobalForcedActions, ~(fFlag)); \
723 } while (0)
724
725/** @def VMCPU_FF_CLEAR
726 * Clears a single force action flag for the given VCPU.
727 *
728 * @param pVCpu The cross context virtual CPU structure.
729 * @param fFlag The flag to clear.
730 */
731#ifdef VMCPU_WITH_64_BIT_FFS
732# define VMCPU_FF_CLEAR(pVCpu, fFlag) do { \
733 AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
734 AssertCompile((fFlag) == RT_BIT_64(fFlag##_BIT)); \
735 ASMAtomicBitClear(&(pVCpu)->fLocalForcedActions, fFlag##_BIT); \
736 } while (0)
737#else
738# define VMCPU_FF_CLEAR(pVCpu, fFlag) do { \
739 AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
740 AssertCompile((fFlag) == RT_BIT_32(fFlag##_BIT)); \
741 ASMAtomicAndU32(&(pVCpu)->fLocalForcedActions, ~(fFlag)); \
742 } while (0)
743#endif
744
745/** @def VMCPU_FF_CLEAR_MASK
746 * Clears two or more force action flags for the given VCPU.
747 *
748 * @param pVCpu The cross context virtual CPU structure.
749 * @param fFlags The flags to clear.
750 */
751#ifdef VMCPU_WITH_64_BIT_FFS
752# if ARCH_BITS > 32
753# define VMCPU_FF_CLEAR_MASK(pVCpu, fFlags) \
754 do { ASMAtomicAndU64(&(pVCpu)->fLocalForcedActions, ~(fFlags)); } while (0)
755# else
756# define VMCPU_FF_CLEAR_MASK(pVCpu, fFlags) do { \
757 if (!((fFlags) >> 32)) ASMAtomicAndU32((uint32_t volatile *)&(pVCpu)->fLocalForcedActions, ~(uint32_t)(fFlags)); \
758 else ASMAtomicAndU64(&(pVCpu)->fLocalForcedActions, ~(fFlags)); \
759 } while (0)
760# endif
761#else
762# define VMCPU_FF_CLEAR_MASK(pVCpu, fFlags) \
763 do { ASMAtomicAndU32(&(pVCpu)->fLocalForcedActions, ~(fFlags)); } while (0)
764#endif
765
766/** @def VM_FF_IS_SET
767 * Checks if single a force action flag is set.
768 *
769 * @param pVM The cross context VM structure.
770 * @param fFlag The flag to check.
771 * @sa VM_FF_IS_ANY_SET
772 */
773#if !defined(VBOX_STRICT) || !defined(RT_COMPILER_SUPPORTS_LAMBDA)
774# define VM_FF_IS_SET(pVM, fFlag) RT_BOOL((pVM)->fGlobalForcedActions & (fFlag))
775#else
776# define VM_FF_IS_SET(pVM, fFlag) \
777 ([](PVM a_pVM) -> bool \
778 { \
779 AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
780 AssertCompile((fFlag) == RT_BIT_32(fFlag##_BIT)); \
781 return RT_BOOL(a_pVM->fGlobalForcedActions & (fFlag)); \
782 }(pVM))
783#endif
784
785/** @def VMCPU_FF_IS_SET
786 * Checks if a single force action flag is set for the given VCPU.
787 *
788 * @param pVCpu The cross context virtual CPU structure.
789 * @param fFlag The flag to check.
790 * @sa VMCPU_FF_IS_ANY_SET
791 */
792#if !defined(VBOX_STRICT) || !defined(RT_COMPILER_SUPPORTS_LAMBDA)
793# define VMCPU_FF_IS_SET(pVCpu, fFlag) RT_BOOL((pVCpu)->fLocalForcedActions & (fFlag))
794#else
795# define VMCPU_FF_IS_SET(pVCpu, fFlag) \
796 ([](PCVMCPU a_pVCpu) -> bool \
797 { \
798 AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
799 AssertCompile((fFlag) == RT_BIT_64(fFlag##_BIT)); \
800 return RT_BOOL(a_pVCpu->fLocalForcedActions & (fFlag)); \
801 }(pVCpu))
802#endif
803
804/** @def VM_FF_IS_ANY_SET
805 * Checks if one or more force action in the specified set is pending.
806 *
807 * @param pVM The cross context VM structure.
808 * @param fFlags The flags to check for.
809 * @sa VM_FF_IS_SET
810 */
811#define VM_FF_IS_ANY_SET(pVM, fFlags) RT_BOOL((pVM)->fGlobalForcedActions & (fFlags))
812
813/** @def VMCPU_FF_IS_ANY_SET
814 * Checks if two or more force action flags in the specified set is set for the given VCPU.
815 *
816 * @param pVCpu The cross context virtual CPU structure.
817 * @param fFlags The flags to check for.
818 * @sa VMCPU_FF_IS_SET
819 */
820#define VMCPU_FF_IS_ANY_SET(pVCpu, fFlags) RT_BOOL((pVCpu)->fLocalForcedActions & (fFlags))
821
822/** @def VM_FF_TEST_AND_CLEAR
823 * Checks if one (!) force action in the specified set is pending and clears it atomically
824 *
825 * @returns true if the bit was set.
826 * @returns false if the bit was clear.
827 * @param pVM The cross context VM structure.
828 * @param fFlag Flag constant to check and clear (_BIT is appended).
829 */
830#define VM_FF_TEST_AND_CLEAR(pVM, fFlag) (ASMAtomicBitTestAndClear(&(pVM)->fGlobalForcedActions, fFlag##_BIT))
831
832/** @def VMCPU_FF_TEST_AND_CLEAR
833 * Checks if one (!) force action in the specified set is pending and clears it atomically
834 *
835 * @returns true if the bit was set.
836 * @returns false if the bit was clear.
837 * @param pVCpu The cross context virtual CPU structure.
838 * @param fFlag Flag constant to check and clear (_BIT is appended).
839 */
840#define VMCPU_FF_TEST_AND_CLEAR(pVCpu, fFlag) (ASMAtomicBitTestAndClear(&(pVCpu)->fLocalForcedActions, fFlag##_BIT))
841
842/** @def VM_FF_IS_PENDING_EXCEPT
843 * Checks if one or more force action in the specified set is pending while one
844 * or more other ones are not.
845 *
846 * @param pVM The cross context VM structure.
847 * @param fFlags The flags to check for.
848 * @param fExcpt The flags that should not be set.
849 */
850#define VM_FF_IS_PENDING_EXCEPT(pVM, fFlags, fExcpt) \
851 ( ((pVM)->fGlobalForcedActions & (fFlags)) && !((pVM)->fGlobalForcedActions & (fExcpt)) )
852
853/** @def VM_IS_EMT
854 * Checks if the current thread is the emulation thread (EMT).
855 *
856 * @remark The ring-0 variation will need attention if we expand the ring-0
857 * code to let threads other than EMT mess around with the VM.
858 */
859#ifdef IN_RC
860# define VM_IS_EMT(pVM) true
861#else
862# define VM_IS_EMT(pVM) (VMMGetCpu(pVM) != NULL)
863#endif
864
865/** @def VMCPU_IS_EMT
866 * Checks if the current thread is the emulation thread (EMT) for the specified
867 * virtual CPU.
868 */
869#ifdef IN_RC
870# define VMCPU_IS_EMT(pVCpu) true
871#else
872# define VMCPU_IS_EMT(pVCpu) ((pVCpu) && ((pVCpu) == VMMGetCpu((pVCpu)->CTX_SUFF(pVM))))
873#endif
874
875/** @def VM_ASSERT_EMT
876 * Asserts that the current thread IS the emulation thread (EMT).
877 */
878#ifdef IN_RC
879# define VM_ASSERT_EMT(pVM) Assert(VM_IS_EMT(pVM))
880#elif defined(IN_RING0)
881# define VM_ASSERT_EMT(pVM) Assert(VM_IS_EMT(pVM))
882#else
883# define VM_ASSERT_EMT(pVM) \
884 AssertMsg(VM_IS_EMT(pVM), \
885 ("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd\n", RTThreadNativeSelf(), VMR3GetVMCPUNativeThread(pVM)))
886#endif
887
888/** @def VMCPU_ASSERT_EMT
889 * Asserts that the current thread IS the emulation thread (EMT) of the
890 * specified virtual CPU.
891 */
892#ifdef IN_RC
893# define VMCPU_ASSERT_EMT(pVCpu) Assert(VMCPU_IS_EMT(pVCpu))
894#elif defined(IN_RING0)
895# define VMCPU_ASSERT_EMT(pVCpu) AssertMsg(VMCPU_IS_EMT(pVCpu), \
896 ("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd idCpu=%u\n", \
897 RTThreadNativeSelf(), (pVCpu) ? (pVCpu)->hNativeThreadR0 : 0, \
898 (pVCpu) ? (pVCpu)->idCpu : 0))
899#else
900# define VMCPU_ASSERT_EMT(pVCpu) AssertMsg(VMCPU_IS_EMT(pVCpu), \
901 ("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd idCpu=%#x\n", \
902 RTThreadNativeSelf(), (pVCpu)->hNativeThread, (pVCpu)->idCpu))
903#endif
904
905/** @def VM_ASSERT_EMT_RETURN
906 * Asserts that the current thread IS the emulation thread (EMT) and returns if it isn't.
907 */
908#ifdef IN_RC
909# define VM_ASSERT_EMT_RETURN(pVM, rc) AssertReturn(VM_IS_EMT(pVM), (rc))
910#elif defined(IN_RING0)
911# define VM_ASSERT_EMT_RETURN(pVM, rc) AssertReturn(VM_IS_EMT(pVM), (rc))
912#else
913# define VM_ASSERT_EMT_RETURN(pVM, rc) \
914 AssertMsgReturn(VM_IS_EMT(pVM), \
915 ("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd\n", RTThreadNativeSelf(), VMR3GetVMCPUNativeThread(pVM)), \
916 (rc))
917#endif
918
919/** @def VMCPU_ASSERT_EMT_RETURN
920 * Asserts that the current thread IS the emulation thread (EMT) and returns if it isn't.
921 */
922#ifdef IN_RC
923# define VMCPU_ASSERT_EMT_RETURN(pVCpu, rc) AssertReturn(VMCPU_IS_EMT(pVCpu), (rc))
924#elif defined(IN_RING0)
925# define VMCPU_ASSERT_EMT_RETURN(pVCpu, rc) AssertReturn(VMCPU_IS_EMT(pVCpu), (rc))
926#else
927# define VMCPU_ASSERT_EMT_RETURN(pVCpu, rc) \
928 AssertMsgReturn(VMCPU_IS_EMT(pVCpu), \
929 ("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd idCpu=%#x\n", \
930 RTThreadNativeSelf(), (pVCpu)->hNativeThread, (pVCpu)->idCpu), \
931 (rc))
932#endif
933
934/** @def VMCPU_ASSERT_EMT_OR_GURU
935 * Asserts that the current thread IS the emulation thread (EMT) of the
936 * specified virtual CPU.
937 */
938#if defined(IN_RC) || defined(IN_RING0)
939# define VMCPU_ASSERT_EMT_OR_GURU(pVCpu) Assert( VMCPU_IS_EMT(pVCpu) \
940 || pVCpu->CTX_SUFF(pVM)->enmVMState == VMSTATE_GURU_MEDITATION \
941 || pVCpu->CTX_SUFF(pVM)->enmVMState == VMSTATE_GURU_MEDITATION_LS )
942#else
943# define VMCPU_ASSERT_EMT_OR_GURU(pVCpu) \
944 AssertMsg( VMCPU_IS_EMT(pVCpu) \
945 || pVCpu->CTX_SUFF(pVM)->enmVMState == VMSTATE_GURU_MEDITATION \
946 || pVCpu->CTX_SUFF(pVM)->enmVMState == VMSTATE_GURU_MEDITATION_LS, \
947 ("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd idCpu=%#x\n", \
948 RTThreadNativeSelf(), (pVCpu)->hNativeThread, (pVCpu)->idCpu))
949#endif
950
951/** @def VMCPU_ASSERT_EMT_OR_NOT_RUNNING
952 * Asserts that the current thread IS the emulation thread (EMT) of the
953 * specified virtual CPU or the VM is not running.
954 */
955#if defined(IN_RC) || defined(IN_RING0)
956# define VMCPU_ASSERT_EMT_OR_NOT_RUNNING(pVCpu) \
957 Assert( VMCPU_IS_EMT(pVCpu) \
958 || !VM_IS_RUNNING_FOR_ASSERTIONS_ONLY((pVCpu)->CTX_SUFF(pVM)) )
959#else
960# define VMCPU_ASSERT_EMT_OR_NOT_RUNNING(pVCpu) \
961 AssertMsg( VMCPU_IS_EMT(pVCpu) \
962 || !VM_IS_RUNNING_FOR_ASSERTIONS_ONLY((pVCpu)->CTX_SUFF(pVM)), \
963 ("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd idCpu=%#x\n", \
964 RTThreadNativeSelf(), (pVCpu)->hNativeThread, (pVCpu)->idCpu))
965#endif
966
967/** @def VMSTATE_IS_RUNNING
968 * Checks if the given state indicates a running VM.
969 */
970#define VMSTATE_IS_RUNNING(a_enmVMState) \
971 ( (enmVMState) == VMSTATE_RUNNING \
972 || (enmVMState) == VMSTATE_RUNNING_LS )
973
974/** @def VM_IS_RUNNING_FOR_ASSERTIONS_ONLY
975 * Checks if the VM is running.
976 * @note This is only for pure debug assertions. No AssertReturn or similar!
977 * @sa VMSTATE_IS_RUNNING
978 */
979#define VM_IS_RUNNING_FOR_ASSERTIONS_ONLY(pVM) \
980 ( (pVM)->enmVMState == VMSTATE_RUNNING \
981 || (pVM)->enmVMState == VMSTATE_RUNNING_LS )
982
983/** @def VM_ASSERT_IS_NOT_RUNNING
984 * Asserts that the VM is not running.
985 */
986#if defined(IN_RC) || defined(IN_RING0)
987#define VM_ASSERT_IS_NOT_RUNNING(pVM) Assert(!VM_IS_RUNNING_FOR_ASSERTIONS_ONLY(pVM))
988#else
989#define VM_ASSERT_IS_NOT_RUNNING(pVM) AssertMsg(!VM_IS_RUNNING_FOR_ASSERTIONS_ONLY(pVM), \
990 ("VM is running. enmVMState=%d\n", (pVM)->enmVMState))
991#endif
992
993/** @def VM_ASSERT_EMT0
994 * Asserts that the current thread IS emulation thread \#0 (EMT0).
995 */
996#if defined(VBOX_BUGREF_9217_PART_I) && defined(IN_RING3)
997# define VM_ASSERT_EMT0(a_pVM) VMCPU_ASSERT_EMT((a_pVM)->apCpusR3[0])
998#else
999# define VM_ASSERT_EMT0(a_pVM) VMCPU_ASSERT_EMT(&(a_pVM)->aCpus[0])
1000#endif
1001
1002/** @def VM_ASSERT_EMT0_RETURN
1003 * Asserts that the current thread IS emulation thread \#0 (EMT0) and returns if
1004 * it isn't.
1005 */
1006#define VM_ASSERT_EMT0_RETURN(pVM, rc) VMCPU_ASSERT_EMT_RETURN(&(pVM)->aCpus[0], (rc))
1007
1008
1009/**
1010 * Asserts that the current thread is NOT the emulation thread.
1011 */
1012#define VM_ASSERT_OTHER_THREAD(pVM) \
1013 AssertMsg(!VM_IS_EMT(pVM), ("Not other thread!!\n"))
1014
1015
1016/** @def VM_ASSERT_STATE
1017 * Asserts a certain VM state.
1018 */
1019#define VM_ASSERT_STATE(pVM, _enmState) \
1020 AssertMsg((pVM)->enmVMState == (_enmState), \
1021 ("state %s, expected %s\n", VMGetStateName((pVM)->enmVMState), VMGetStateName(_enmState)))
1022
1023/** @def VM_ASSERT_STATE_RETURN
1024 * Asserts a certain VM state and returns if it doesn't match.
1025 */
1026#define VM_ASSERT_STATE_RETURN(pVM, _enmState, rc) \
1027 AssertMsgReturn((pVM)->enmVMState == (_enmState), \
1028 ("state %s, expected %s\n", VMGetStateName((pVM)->enmVMState), VMGetStateName(_enmState)), \
1029 (rc))
1030
1031/** @def VM_IS_VALID_EXT
1032 * Asserts a the VM handle is valid for external access, i.e. not being destroy
1033 * or terminated. */
1034#define VM_IS_VALID_EXT(pVM) \
1035 ( RT_VALID_ALIGNED_PTR(pVM, PAGE_SIZE) \
1036 && ( (unsigned)(pVM)->enmVMState < (unsigned)VMSTATE_DESTROYING \
1037 || ( (unsigned)(pVM)->enmVMState == (unsigned)VMSTATE_DESTROYING \
1038 && VM_IS_EMT(pVM))) )
1039
1040/** @def VM_ASSERT_VALID_EXT_RETURN
1041 * Asserts a the VM handle is valid for external access, i.e. not being
1042 * destroy or terminated.
1043 */
1044#define VM_ASSERT_VALID_EXT_RETURN(pVM, rc) \
1045 AssertMsgReturn(VM_IS_VALID_EXT(pVM), \
1046 ("pVM=%p state %s\n", (pVM), RT_VALID_ALIGNED_PTR(pVM, PAGE_SIZE) \
1047 ? VMGetStateName(pVM->enmVMState) : ""), \
1048 (rc))
1049
1050/** @def VMCPU_ASSERT_VALID_EXT_RETURN
1051 * Asserts a the VMCPU handle is valid for external access, i.e. not being
1052 * destroy or terminated.
1053 */
1054#define VMCPU_ASSERT_VALID_EXT_RETURN(pVCpu, rc) \
1055 AssertMsgReturn( RT_VALID_ALIGNED_PTR(pVCpu, 64) \
1056 && RT_VALID_ALIGNED_PTR((pVCpu)->CTX_SUFF(pVM), PAGE_SIZE) \
1057 && (unsigned)(pVCpu)->CTX_SUFF(pVM)->enmVMState < (unsigned)VMSTATE_DESTROYING, \
1058 ("pVCpu=%p pVM=%p state %s\n", (pVCpu), RT_VALID_ALIGNED_PTR(pVCpu, 64) ? (pVCpu)->CTX_SUFF(pVM) : NULL, \
1059 RT_VALID_ALIGNED_PTR(pVCpu, 64) && RT_VALID_ALIGNED_PTR((pVCpu)->CTX_SUFF(pVM), PAGE_SIZE) \
1060 ? VMGetStateName((pVCpu)->pVMR3->enmVMState) : ""), \
1061 (rc))
1062
1063#endif /* !VBOX_FOR_DTRACE_LIB */
1064
1065
1066/**
1067 * Helper that HM and NEM uses for safely modifying VM::bMainExecutionEngine.
1068 *
1069 * ONLY HM and NEM MAY USE THIS!
1070 *
1071 * @param a_pVM The cross context VM structure.
1072 * @param a_bValue The new value.
1073 * @internal
1074 */
1075#define VM_SET_MAIN_EXECUTION_ENGINE(a_pVM, a_bValue) \
1076 do { \
1077 *const_cast<uint8_t *>(&(a_pVM)->bMainExecutionEngine) = (a_bValue); \
1078 ASMCompilerBarrier(); /* just to be on the safe side */ \
1079 } while (0)
1080
1081/**
1082 * Checks whether raw-mode is used.
1083 *
1084 * @retval true if either is used.
1085 * @retval false if software virtualization (raw-mode) is used.
1086 *
1087 * @param a_pVM The cross context VM structure.
1088 * @sa VM_IS_HM_OR_NEM_ENABLED, VM_IS_HM_ENABLED, VM_IS_NEM_ENABLED.
1089 * @internal
1090 */
1091#ifdef VBOX_WITH_RAW_MODE
1092# define VM_IS_RAW_MODE_ENABLED(a_pVM) ((a_pVM)->bMainExecutionEngine == VM_EXEC_ENGINE_RAW_MODE)
1093#else
1094# define VM_IS_RAW_MODE_ENABLED(a_pVM) (false)
1095#endif
1096
1097/**
1098 * Checks whether HM (VT-x/AMD-V) or NEM is being used by this VM.
1099 *
1100 * @retval true if either is used.
1101 * @retval false if software virtualization (raw-mode) is used.
1102 *
1103 * @param a_pVM The cross context VM structure.
1104 * @sa VM_IS_RAW_MODE_ENABLED, VM_IS_HM_ENABLED, VM_IS_NEM_ENABLED.
1105 * @internal
1106 */
1107#define VM_IS_HM_OR_NEM_ENABLED(a_pVM) ((a_pVM)->bMainExecutionEngine != VM_EXEC_ENGINE_RAW_MODE)
1108
1109/**
1110 * Checks whether HM is being used by this VM.
1111 *
1112 * @retval true if HM (VT-x/AMD-v) is used.
1113 * @retval false if not.
1114 *
1115 * @param a_pVM The cross context VM structure.
1116 * @sa VM_IS_NEM_ENABLED, VM_IS_RAW_MODE_ENABLED, VM_IS_HM_OR_NEM_ENABLED.
1117 * @internal
1118 */
1119#define VM_IS_HM_ENABLED(a_pVM) ((a_pVM)->bMainExecutionEngine == VM_EXEC_ENGINE_HW_VIRT)
1120
1121/**
1122 * Checks whether NEM is being used by this VM.
1123 *
1124 * @retval true if a native hypervisor API is used.
1125 * @retval false if not.
1126 *
1127 * @param a_pVM The cross context VM structure.
1128 * @sa VM_IS_HM_ENABLED, VM_IS_RAW_MODE_ENABLED, VM_IS_HM_OR_NEM_ENABLED.
1129 * @internal
1130 */
1131#define VM_IS_NEM_ENABLED(a_pVM) ((a_pVM)->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API)
1132
1133
1134/**
1135 * The cross context VM structure.
1136 *
1137 * It contains all the VM data which have to be available in all contexts.
1138 * Even if it contains all the data the idea is to use APIs not to modify all
1139 * the members all around the place. Therefore we make use of unions to hide
1140 * everything which isn't local to the current source module. This means we'll
1141 * have to pay a little bit of attention when adding new members to structures
1142 * in the unions and make sure to keep the padding sizes up to date.
1143 *
1144 * Run 'kmk run-struct-tests' (from src/VBox/VMM if you like) after updating!
1145 */
1146typedef struct VM
1147{
1148 /** The state of the VM.
1149 * This field is read only to everyone except the VM and EM. */
1150 VMSTATE volatile enmVMState;
1151 /** Forced action flags.
1152 * See the VM_FF_* \#defines. Updated atomically.
1153 */
1154 volatile uint32_t fGlobalForcedActions;
1155 /** Pointer to the array of page descriptors for the VM structure allocation. */
1156 R3PTRTYPE(PSUPPAGE) paVMPagesR3;
1157 /** Session handle. For use when calling SUPR0 APIs. */
1158 PSUPDRVSESSION pSession;
1159 /** Pointer to the ring-3 VM structure. */
1160 PUVM pUVM;
1161 /** Ring-3 Host Context VM Pointer. */
1162 R3PTRTYPE(struct VM *) pVMR3;
1163 /** Ring-0 Host Context VM Pointer. */
1164 R0PTRTYPE(struct VM *) pVMR0;
1165 /** Raw-mode Context VM Pointer. */
1166 uint32_t pVMRC;
1167 /** Padding for new raw-mode (long mode). */
1168 uint32_t pVMRCPadding;
1169
1170 /** The GVM VM handle. Only the GVM should modify this field. */
1171 uint32_t hSelf;
1172 /** Number of virtual CPUs. */
1173 uint32_t cCpus;
1174 /** CPU excution cap (1-100) */
1175 uint32_t uCpuExecutionCap;
1176
1177#ifdef VBOX_BUGREF_9217
1178 /** Size of the VM structure. */
1179 uint32_t cbSelf;
1180 /** Size of the VMCPU structure. */
1181 uint32_t cbVCpu;
1182 /** Structure version number (TBD). */
1183 uint32_t uStructVersion;
1184#else
1185 /** Size of the VM structure including the VMCPU array. */
1186 uint32_t cbSelf;
1187 uint32_t uUnused0;
1188 uint32_t uUnused1;
1189#endif
1190
1191 /** @name Various items that are frequently accessed.
1192 * @{ */
1193 /** The main execution engine, VM_EXEC_ENGINE_XXX.
1194 * This is set early during vmR3InitRing3 by HM or NEM. */
1195 uint8_t const bMainExecutionEngine;
1196
1197 /** Hardware VM support is available and enabled.
1198 * Determined very early during init.
1199 * This is placed here for performance reasons.
1200 * @todo obsoleted by bMainExecutionEngine, eliminate. */
1201 bool fHMEnabled;
1202
1203 /** Large page enabled flag.
1204 * @todo This doesn't need to be here, PGM should store it in it's own
1205 * structures instead. */
1206 bool fUseLargePages;
1207 /** @} */
1208
1209 /** Alignment padding. */
1210 uint8_t uPadding1[5];
1211
1212 /** @name Debugging
1213 * @{ */
1214 /** Ring-3 Host Context VM Pointer. */
1215 R3PTRTYPE(RTTRACEBUF) hTraceBufR3;
1216 /** Ring-0 Host Context VM Pointer. */
1217 R0PTRTYPE(RTTRACEBUF) hTraceBufR0;
1218 /** @} */
1219
1220 /** Padding - the unions must be aligned on a 64 bytes boundary. */
1221 uint8_t abAlignment3[24];
1222
1223 /** CPUM part. */
1224 union
1225 {
1226#ifdef VMM_INCLUDED_SRC_include_CPUMInternal_h
1227 struct CPUM s;
1228#endif
1229#ifdef VBOX_INCLUDED_vmm_cpum_h
1230 /** Read only info exposed about the host and guest CPUs. */
1231 struct
1232 {
1233 /** Padding for hidden fields. */
1234 uint8_t abHidden0[64];
1235 /** Host CPU feature information. */
1236 CPUMFEATURES HostFeatures;
1237 /** Guest CPU feature information. */
1238 CPUMFEATURES GuestFeatures;
1239 } const ro;
1240#endif
1241 uint8_t padding[1536]; /* multiple of 64 */
1242 } cpum;
1243
1244 /** VMM part. */
1245 union
1246 {
1247#ifdef VMM_INCLUDED_SRC_include_VMMInternal_h
1248 struct VMM s;
1249#endif
1250 uint8_t padding[1600]; /* multiple of 64 */
1251 } vmm;
1252
1253 /** PGM part. */
1254 union
1255 {
1256#ifdef VMM_INCLUDED_SRC_include_PGMInternal_h
1257 struct PGM s;
1258#endif
1259 uint8_t padding[20800]; /* multiple of 64 */
1260 } pgm;
1261
1262 /** HM part. */
1263 union
1264 {
1265#ifdef VMM_INCLUDED_SRC_include_HMInternal_h
1266 struct HM s;
1267#endif
1268 uint8_t padding[5440]; /* multiple of 64 */
1269 } hm;
1270
1271 /** TRPM part. */
1272 union
1273 {
1274#ifdef VMM_INCLUDED_SRC_include_TRPMInternal_h
1275 struct TRPM s;
1276#endif
1277 uint8_t padding[5248]; /* multiple of 64 */
1278 } trpm;
1279
1280 /** SELM part. */
1281 union
1282 {
1283#ifdef VMM_INCLUDED_SRC_include_SELMInternal_h
1284 struct SELM s;
1285#endif
1286 uint8_t padding[768]; /* multiple of 64 */
1287 } selm;
1288
1289 /** MM part. */
1290 union
1291 {
1292#ifdef VMM_INCLUDED_SRC_include_MMInternal_h
1293 struct MM s;
1294#endif
1295 uint8_t padding[192]; /* multiple of 64 */
1296 } mm;
1297
1298 /** PDM part. */
1299 union
1300 {
1301#ifdef VMM_INCLUDED_SRC_include_PDMInternal_h
1302 struct PDM s;
1303#endif
1304 uint8_t padding[1920]; /* multiple of 64 */
1305 } pdm;
1306
1307 /** IOM part. */
1308 union
1309 {
1310#ifdef VMM_INCLUDED_SRC_include_IOMInternal_h
1311 struct IOM s;
1312#endif
1313 uint8_t padding[896]; /* multiple of 64 */
1314 } iom;
1315
1316 /** EM part. */
1317 union
1318 {
1319#ifdef VMM_INCLUDED_SRC_include_EMInternal_h
1320 struct EM s;
1321#endif
1322 uint8_t padding[256]; /* multiple of 64 */
1323 } em;
1324
1325 /** NEM part. */
1326 union
1327 {
1328#ifdef VMM_INCLUDED_SRC_include_NEMInternal_h
1329 struct NEM s;
1330#endif
1331 uint8_t padding[128]; /* multiple of 64 */
1332 } nem;
1333
1334 /** TM part. */
1335 union
1336 {
1337#ifdef VMM_INCLUDED_SRC_include_TMInternal_h
1338 struct TM s;
1339#endif
1340 uint8_t padding[7872]; /* multiple of 64 */
1341 } tm;
1342
1343 /** DBGF part. */
1344 union
1345 {
1346#ifdef VMM_INCLUDED_SRC_include_DBGFInternal_h
1347 struct DBGF s;
1348#endif
1349#ifdef VBOX_INCLUDED_vmm_dbgf_h
1350 /** Read only info exposed about interrupt breakpoints and selected events. */
1351 struct
1352 {
1353 /** Bitmap of enabled hardware interrupt breakpoints. */
1354 uint32_t bmHardIntBreakpoints[256 / 32];
1355 /** Bitmap of enabled software interrupt breakpoints. */
1356 uint32_t bmSoftIntBreakpoints[256 / 32];
1357 /** Bitmap of selected events.
1358 * This includes non-selectable events too for simplicity, we maintain the
1359 * state for some of these, as it may come in handy. */
1360 uint64_t bmSelectedEvents[(DBGFEVENT_END + 63) / 64];
1361 /** Enabled hardware interrupt breakpoints. */
1362 uint32_t cHardIntBreakpoints;
1363 /** Enabled software interrupt breakpoints. */
1364 uint32_t cSoftIntBreakpoints;
1365 /** The number of selected events. */
1366 uint32_t cSelectedEvents;
1367 /** The number of enabled hardware breakpoints. */
1368 uint8_t cEnabledHwBreakpoints;
1369 /** The number of enabled hardware I/O breakpoints. */
1370 uint8_t cEnabledHwIoBreakpoints;
1371 /** The number of enabled INT3 breakpoints. */
1372 uint8_t cEnabledInt3Breakpoints;
1373 uint8_t abPadding[1]; /**< Unused padding space up for grabs. */
1374 } const ro;
1375#endif
1376 uint8_t padding[2432]; /* multiple of 64 */
1377 } dbgf;
1378
1379 /** SSM part. */
1380 union
1381 {
1382#ifdef VMM_INCLUDED_SRC_include_SSMInternal_h
1383 struct SSM s;
1384#endif
1385 uint8_t padding[128]; /* multiple of 64 */
1386 } ssm;
1387
1388#ifdef VBOX_WITH_REM
1389 /** REM part. */
1390 union
1391 {
1392# ifdef VMM_INCLUDED_SRC_include_REMInternal_h
1393 struct REM s;
1394# endif
1395 uint8_t padding[0x11100]; /* multiple of 64 */
1396 } rem;
1397#endif
1398
1399 union
1400 {
1401#ifdef VMM_INCLUDED_SRC_include_GIMInternal_h
1402 struct GIM s;
1403#endif
1404 uint8_t padding[448]; /* multiple of 64 */
1405 } gim;
1406
1407 union
1408 {
1409#ifdef VMM_INCLUDED_SRC_include_APICInternal_h
1410 struct APIC s;
1411#endif
1412 uint8_t padding[128]; /* multiple of 8 */
1413 } apic;
1414
1415 /* ---- begin small stuff ---- */
1416
1417 /** VM part. */
1418 union
1419 {
1420#ifdef VMM_INCLUDED_SRC_include_VMInternal_h
1421 struct VMINT s;
1422#endif
1423 uint8_t padding[32]; /* multiple of 8 */
1424 } vm;
1425
1426 /** CFGM part. */
1427 union
1428 {
1429#ifdef VMM_INCLUDED_SRC_include_CFGMInternal_h
1430 struct CFGM s;
1431#endif
1432 uint8_t padding[8]; /* multiple of 8 */
1433 } cfgm;
1434
1435 /** Padding for aligning the structure size on a page boundrary. */
1436#ifdef VBOX_WITH_REM
1437 uint8_t abAlignment2[2520 - sizeof(PVMCPUR0) * VMM_MAX_CPU_COUNT];
1438#else
1439 uint8_t abAlignment2[2520 + 256 - sizeof(PVMCPUR0) * VMM_MAX_CPU_COUNT];
1440#endif
1441
1442 /* ---- end small stuff ---- */
1443#if !defined(VBOX_BUGREF_9217)
1444 /** Array of VMCPU ring-0 pointers. This is temporary as these will
1445 * live in GVM. */
1446 PVMCPUR0 apCpusR0[VMM_MAX_CPU_COUNT];
1447#else
1448 PVMCPUR0 apPaddingR0[VMM_MAX_CPU_COUNT];
1449#endif
1450
1451 /** Array of VMCPU ring-3 pointers. */
1452 PVMCPUR3 apCpusR3[VMM_MAX_CPU_COUNT];
1453#if !defined(VBOX_BUGREF_9217) && !defined(VBOX_BUGREF_9217_PART_I)
1454 /** VMCPU array for the configured number of virtual CPUs.
1455 * Must be aligned on a page boundary for TLB hit reasons as well as
1456 * alignment of VMCPU members. */
1457 VMCPU aCpus[1];
1458#endif
1459} VM;
1460
1461
1462#ifdef IN_RC
1463RT_C_DECLS_BEGIN
1464
1465/** The VM structure.
1466 * This is imported from the VMMRCBuiltin module, i.e. it's a one of those magic
1467 * globals which we should avoid using.
1468 */
1469extern DECLIMPORT(VM) g_VM;
1470
1471/** The VMCPU structure for virtual CPU \#0.
1472 * This is imported from the VMMRCBuiltin module, i.e. it's a one of those magic
1473 * globals which we should avoid using.
1474 */
1475extern DECLIMPORT(VMCPU) g_VCpu0;
1476
1477RT_C_DECLS_END
1478#endif
1479
1480/** @} */
1481
1482#endif /* !VBOX_INCLUDED_vmm_vm_h */
1483
Note: See TracBrowser for help on using the repository browser.

© 2025 Oracle Support Privacy / Do Not Sell My Info Terms of Use Trademark Policy Automated Access Etiquette