VirtualBox

source: vbox/trunk/include/VBox/vmm/vm.h@ 80274

Last change on this file since 80274 was 80274, checked in by vboxsync, 6 years ago

VMM: Refactoring VMMR0/* and VMMRZ/* to use VMCC & VMMCPUCC. bugref:9217
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1/** @file
2 * VM - The Virtual Machine, data.
3 */
4
5/*
6 * Copyright (C) 2006-2019 Oracle Corporation
7 *
8 * This file is part of VirtualBox Open Source Edition (OSE), as
9 * available from http://www.virtualbox.org. This file is free software;
10 * you can redistribute it and/or modify it under the terms of the GNU
11 * General Public License (GPL) as published by the Free Software
12 * Foundation, in version 2 as it comes in the "COPYING" file of the
13 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15 *
16 * The contents of this file may alternatively be used under the terms
17 * of the Common Development and Distribution License Version 1.0
18 * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19 * VirtualBox OSE distribution, in which case the provisions of the
20 * CDDL are applicable instead of those of the GPL.
21 *
22 * You may elect to license modified versions of this file under the
23 * terms and conditions of either the GPL or the CDDL or both.
24 */
25
26#ifndef VBOX_INCLUDED_vmm_vm_h
27#define VBOX_INCLUDED_vmm_vm_h
28#ifndef RT_WITHOUT_PRAGMA_ONCE
29# pragma once
30#endif
31
32#ifndef VBOX_FOR_DTRACE_LIB
33# include <iprt/param.h>
34# include <VBox/param.h>
35# include <VBox/types.h>
36# include <VBox/vmm/cpum.h>
37# include <VBox/vmm/stam.h>
38# include <VBox/vmm/vmapi.h>
39# include <VBox/vmm/vmm.h>
40# include <VBox/sup.h>
41#else
42# pragma D depends_on library vbox-types.d
43# pragma D depends_on library CPUMInternal.d
44# define VMM_INCLUDED_SRC_include_CPUMInternal_h
45#endif
46
47
48
49/** @defgroup grp_vm The Virtual Machine
50 * @ingroup grp_vmm
51 * @{
52 */
53
54/**
55 * The state of a Virtual CPU.
56 *
57 * The basic state indicated here is whether the CPU has been started or not. In
58 * addition, there are sub-states when started for assisting scheduling (GVMM
59 * mostly).
60 *
61 * The transition out of the STOPPED state is done by a vmR3PowerOn.
62 * The transition back to the STOPPED state is done by vmR3PowerOff.
63 *
64 * (Alternatively we could let vmR3PowerOn start CPU 0 only and let the SPIP
65 * handling switch on the other CPUs. Then vmR3Reset would stop all but CPU 0.)
66 */
67typedef enum VMCPUSTATE
68{
69 /** The customary invalid zero. */
70 VMCPUSTATE_INVALID = 0,
71
72 /** Virtual CPU has not yet been started. */
73 VMCPUSTATE_STOPPED,
74
75 /** CPU started. */
76 VMCPUSTATE_STARTED,
77 /** CPU started in HM context. */
78 VMCPUSTATE_STARTED_HM,
79 /** Executing guest code and can be poked (RC or STI bits of HM). */
80 VMCPUSTATE_STARTED_EXEC,
81 /** Executing guest code in the recompiler. */
82 VMCPUSTATE_STARTED_EXEC_REM,
83 /** Executing guest code using NEM. */
84 VMCPUSTATE_STARTED_EXEC_NEM,
85 VMCPUSTATE_STARTED_EXEC_NEM_WAIT,
86 VMCPUSTATE_STARTED_EXEC_NEM_CANCELED,
87 /** Halted. */
88 VMCPUSTATE_STARTED_HALTED,
89
90 /** The end of valid virtual CPU states. */
91 VMCPUSTATE_END,
92
93 /** Ensure 32-bit type. */
94 VMCPUSTATE_32BIT_HACK = 0x7fffffff
95} VMCPUSTATE;
96
97/** Enables 64-bit FFs. */
98#define VMCPU_WITH_64_BIT_FFS
99
100
101/**
102 * The cross context virtual CPU structure.
103 *
104 * Run 'kmk run-struct-tests' (from src/VBox/VMM if you like) after updating!
105 */
106typedef struct VMCPU
107{
108 /** @name Volatile per-cpu data.
109 * @{ */
110 /** Per CPU forced action.
111 * See the VMCPU_FF_* \#defines. Updated atomically. */
112#ifdef VMCPU_WITH_64_BIT_FFS
113 uint64_t volatile fLocalForcedActions;
114#else
115 uint32_t volatile fLocalForcedActions;
116 uint32_t fForLocalForcedActionsExpansion;
117#endif
118 /** The CPU state. */
119 VMCPUSTATE volatile enmState;
120
121 /** Which host CPU ID is this EMT running on.
122 * Only valid when in RC or HMR0 with scheduling disabled. */
123 RTCPUID volatile idHostCpu;
124 /** The CPU set index corresponding to idHostCpu, UINT32_MAX if not valid.
125 * @remarks Best to make sure iHostCpuSet shares cache line with idHostCpu! */
126 uint32_t volatile iHostCpuSet;
127 /** Padding up to 64 bytes. */
128 uint8_t abAlignment0[64 - 20];
129 /** @} */
130
131 /** IEM part.
132 * @remarks This comes first as it allows the use of 8-bit immediates for the
133 * first 64 bytes of the structure, reducing code size a wee bit. */
134#ifdef VMM_INCLUDED_SRC_include_IEMInternal_h /* For PDB hacking. */
135 union VMCPUUNIONIEMFULL
136#else
137 union VMCPUUNIONIEMSTUB
138#endif
139 {
140#ifdef VMM_INCLUDED_SRC_include_IEMInternal_h
141 struct IEMCPU s;
142#endif
143 uint8_t padding[18496]; /* multiple of 64 */
144 } iem;
145
146 /** @name Static per-cpu data.
147 * (Putting this after IEM, hoping that it's less frequently used than it.)
148 * @{ */
149 /** Ring-3 Host Context VM Pointer. */
150 PVMR3 pVMR3;
151#ifndef VBOX_BUGREF_9217
152 /** Ring-0 Host Context VM Pointer. */
153 PVMR0 pVMR0;
154#else
155 RTR0PTR R0PtrUnused0;
156#endif
157 /** Raw-mode Context VM Pointer. */
158 uint32_t pVMRC;
159 /** Padding for new raw-mode (long mode). */
160 uint32_t pVMRCPadding;
161 /** Pointer to the ring-3 UVMCPU structure. */
162 PUVMCPU pUVCpu;
163 /** The native thread handle. */
164 RTNATIVETHREAD hNativeThread;
165 /** The native R0 thread handle. (different from the R3 handle!) */
166 RTNATIVETHREAD hNativeThreadR0;
167 /** The CPU ID.
168 * This is the index into the VM::aCpu array. */
169#ifdef VBOX_BUGREF_9217
170 VMCPUID idCpuUnsafe;
171#else
172 VMCPUID idCpu;
173#endif
174
175 /** Align the structures below bit on a 64-byte boundary and make sure it starts
176 * at the same offset in both 64-bit and 32-bit builds.
177 *
178 * @remarks The alignments of the members that are larger than 48 bytes should be
179 * 64-byte for cache line reasons. structs containing small amounts of
180 * data could be lumped together at the end with a < 64 byte padding
181 * following it (to grow into and align the struct size).
182 */
183 uint8_t abAlignment1[64 - 5 * (HC_ARCH_BITS == 32 ? 4 : 8) - 8 - 4];
184 /** @} */
185
186 /** HM part. */
187 union VMCPUUNIONHM
188 {
189#ifdef VMM_INCLUDED_SRC_include_HMInternal_h
190 struct HMCPU s;
191#endif
192 uint8_t padding[5888]; /* multiple of 64 */
193 } hm;
194
195 /** NEM part. */
196 union VMCPUUNIONNEM
197 {
198#ifdef VMM_INCLUDED_SRC_include_NEMInternal_h
199 struct NEMCPU s;
200#endif
201 uint8_t padding[512]; /* multiple of 64 */
202 } nem;
203
204 /** TRPM part. */
205 union VMCPUUNIONTRPM
206 {
207#ifdef VMM_INCLUDED_SRC_include_TRPMInternal_h
208 struct TRPMCPU s;
209#endif
210 uint8_t padding[128]; /* multiple of 64 */
211 } trpm;
212
213 /** TM part. */
214 union VMCPUUNIONTM
215 {
216#ifdef VMM_INCLUDED_SRC_include_TMInternal_h
217 struct TMCPU s;
218#endif
219 uint8_t padding[5760]; /* multiple of 64 */
220 } tm;
221
222 /** VMM part. */
223 union VMCPUUNIONVMM
224 {
225#ifdef VMM_INCLUDED_SRC_include_VMMInternal_h
226 struct VMMCPU s;
227#endif
228 uint8_t padding[896]; /* multiple of 64 */
229 } vmm;
230
231 /** PDM part. */
232 union VMCPUUNIONPDM
233 {
234#ifdef VMM_INCLUDED_SRC_include_PDMInternal_h
235 struct PDMCPU s;
236#endif
237 uint8_t padding[256]; /* multiple of 64 */
238 } pdm;
239
240 /** IOM part. */
241 union VMCPUUNIONIOM
242 {
243#ifdef VMM_INCLUDED_SRC_include_IOMInternal_h
244 struct IOMCPU s;
245#endif
246 uint8_t padding[512]; /* multiple of 64 */
247 } iom;
248
249 /** DBGF part.
250 * @todo Combine this with other tiny structures. */
251 union VMCPUUNIONDBGF
252 {
253#ifdef VMM_INCLUDED_SRC_include_DBGFInternal_h
254 struct DBGFCPU s;
255#endif
256 uint8_t padding[256]; /* multiple of 64 */
257 } dbgf;
258
259 /** GIM part. */
260 union VMCPUUNIONGIM
261 {
262#ifdef VMM_INCLUDED_SRC_include_GIMInternal_h
263 struct GIMCPU s;
264#endif
265 uint8_t padding[512]; /* multiple of 64 */
266 } gim;
267
268 /** APIC part. */
269 union VMCPUUNIONAPIC
270 {
271#ifdef VMM_INCLUDED_SRC_include_APICInternal_h
272 struct APICCPU s;
273#endif
274 uint8_t padding[1792]; /* multiple of 64 */
275 } apic;
276
277 /*
278 * Some less frequently used global members that doesn't need to take up
279 * precious space at the head of the structure.
280 */
281
282 /** Trace groups enable flags. */
283 uint32_t fTraceGroups; /* 64 / 44 */
284 /** State data for use by ad hoc profiling. */
285 uint32_t uAdHoc;
286 /** Profiling samples for use by ad hoc profiling. */
287 STAMPROFILEADV aStatAdHoc[8]; /* size: 40*8 = 320 */
288
289 /** Align the following members on page boundary. */
290 uint8_t abAlignment2[1400];
291
292 /** PGM part. */
293 union VMCPUUNIONPGM
294 {
295#ifdef VMM_INCLUDED_SRC_include_PGMInternal_h
296 struct PGMCPU s;
297#endif
298 uint8_t padding[4096]; /* multiple of 4096 */
299 } pgm;
300
301 /** CPUM part. */
302 union VMCPUUNIONCPUM
303 {
304#ifdef VMM_INCLUDED_SRC_include_CPUMInternal_h
305 struct CPUMCPU s;
306#endif
307#ifdef VMCPU_INCL_CPUM_GST_CTX
308 /** The guest CPUM context for direct use by execution engines.
309 * This is not for general consumption, but for HM, REM, IEM, and maybe a few
310 * others. The rest will use the function based CPUM API. */
311 CPUMCTX GstCtx;
312#endif
313 uint8_t padding[4096]; /* multiple of 4096 */
314 } cpum;
315
316 /** EM part. */
317 union VMCPUUNIONEM
318 {
319#ifdef VMM_INCLUDED_SRC_include_EMInternal_h
320 struct EMCPU s;
321#endif
322 uint8_t padding[40960]; /* multiple of 4096 */
323 } em;
324} VMCPU;
325
326
327#ifndef VBOX_FOR_DTRACE_LIB
328AssertCompileSizeAlignment(VMCPU, 4096);
329
330/** @name Operations on VMCPU::enmState
331 * @{ */
332/** Gets the VMCPU state. */
333#define VMCPU_GET_STATE(pVCpu) ( (pVCpu)->enmState )
334/** Sets the VMCPU state. */
335#define VMCPU_SET_STATE(pVCpu, enmNewState) \
336 ASMAtomicWriteU32((uint32_t volatile *)&(pVCpu)->enmState, (enmNewState))
337/** Cmpares and sets the VMCPU state. */
338#define VMCPU_CMPXCHG_STATE(pVCpu, enmNewState, enmOldState) \
339 ASMAtomicCmpXchgU32((uint32_t volatile *)&(pVCpu)->enmState, (enmNewState), (enmOldState))
340/** Checks the VMCPU state. */
341#ifdef VBOX_STRICT
342# define VMCPU_ASSERT_STATE(pVCpu, enmExpectedState) \
343 do { \
344 VMCPUSTATE enmState = VMCPU_GET_STATE(pVCpu); \
345 AssertMsg(enmState == (enmExpectedState), \
346 ("enmState=%d enmExpectedState=%d idCpu=%u\n", \
347 enmState, enmExpectedState, (pVCpu)->idCpu)); \
348 } while (0)
349#else
350# define VMCPU_ASSERT_STATE(pVCpu, enmExpectedState) do { } while (0)
351#endif
352/** Tests if the state means that the CPU is started. */
353#define VMCPUSTATE_IS_STARTED(enmState) ( (enmState) > VMCPUSTATE_STOPPED )
354/** Tests if the state means that the CPU is stopped. */
355#define VMCPUSTATE_IS_STOPPED(enmState) ( (enmState) == VMCPUSTATE_STOPPED )
356/** @} */
357
358
359/** The name of the raw-mode context VMM Core module. */
360#define VMMRC_MAIN_MODULE_NAME "VMMRC.rc"
361/** The name of the ring-0 context VMM Core module. */
362#define VMMR0_MAIN_MODULE_NAME "VMMR0.r0"
363
364
365/** VM Forced Action Flags.
366 *
367 * Use the VM_FF_SET() and VM_FF_CLEAR() macros to change the force
368 * action mask of a VM.
369 *
370 * Available VM bits:
371 * 0, 1, 5, 6, 7, 13, 14, 15, 16, 17, 21, 22, 23, 24, 25, 26, 27, 28, 30
372 *
373 *
374 * Available VMCPU bits:
375 * 14, 15, 36 to 63
376 *
377 * @todo If we run low on VMCPU, we may consider merging the SELM bits
378 *
379 * @{
380 */
381/** The virtual sync clock has been stopped, go to TM until it has been
382 * restarted... */
383#define VM_FF_TM_VIRTUAL_SYNC RT_BIT_32(VM_FF_TM_VIRTUAL_SYNC_BIT)
384#define VM_FF_TM_VIRTUAL_SYNC_BIT 2
385/** PDM Queues are pending. */
386#define VM_FF_PDM_QUEUES RT_BIT_32(VM_FF_PDM_QUEUES_BIT)
387/** The bit number for VM_FF_PDM_QUEUES. */
388#define VM_FF_PDM_QUEUES_BIT 3
389/** PDM DMA transfers are pending. */
390#define VM_FF_PDM_DMA RT_BIT_32(VM_FF_PDM_DMA_BIT)
391/** The bit number for VM_FF_PDM_DMA. */
392#define VM_FF_PDM_DMA_BIT 4
393/** This action forces the VM to call DBGF so DBGF can service debugger
394 * requests in the emulation thread.
395 * This action flag stays asserted till DBGF clears it.*/
396#define VM_FF_DBGF RT_BIT_32(VM_FF_DBGF_BIT)
397/** The bit number for VM_FF_DBGF. */
398#define VM_FF_DBGF_BIT 8
399/** This action forces the VM to service pending requests from other
400 * thread or requests which must be executed in another context. */
401#define VM_FF_REQUEST RT_BIT_32(VM_FF_REQUEST_BIT)
402#define VM_FF_REQUEST_BIT 9
403/** Check for VM state changes and take appropriate action. */
404#define VM_FF_CHECK_VM_STATE RT_BIT_32(VM_FF_CHECK_VM_STATE_BIT)
405/** The bit number for VM_FF_CHECK_VM_STATE. */
406#define VM_FF_CHECK_VM_STATE_BIT 10
407/** Reset the VM. (postponed) */
408#define VM_FF_RESET RT_BIT_32(VM_FF_RESET_BIT)
409/** The bit number for VM_FF_RESET. */
410#define VM_FF_RESET_BIT 11
411/** EMT rendezvous in VMM. */
412#define VM_FF_EMT_RENDEZVOUS RT_BIT_32(VM_FF_EMT_RENDEZVOUS_BIT)
413/** The bit number for VM_FF_EMT_RENDEZVOUS. */
414#define VM_FF_EMT_RENDEZVOUS_BIT 12
415
416/** PGM needs to allocate handy pages. */
417#define VM_FF_PGM_NEED_HANDY_PAGES RT_BIT_32(VM_FF_PGM_NEED_HANDY_PAGES_BIT)
418#define VM_FF_PGM_NEED_HANDY_PAGES_BIT 18
419/** PGM is out of memory.
420 * Abandon all loops and code paths which can be resumed and get up to the EM
421 * loops. */
422#define VM_FF_PGM_NO_MEMORY RT_BIT_32(VM_FF_PGM_NO_MEMORY_BIT)
423#define VM_FF_PGM_NO_MEMORY_BIT 19
424 /** PGM is about to perform a lightweight pool flush
425 * Guest SMP: all EMT threads should return to ring 3
426 */
427#define VM_FF_PGM_POOL_FLUSH_PENDING RT_BIT_32(VM_FF_PGM_POOL_FLUSH_PENDING_BIT)
428#define VM_FF_PGM_POOL_FLUSH_PENDING_BIT 20
429/** REM needs to be informed about handler changes. */
430#define VM_FF_REM_HANDLER_NOTIFY RT_BIT_32(VM_FF_REM_HANDLER_NOTIFY_BIT)
431/** The bit number for VM_FF_REM_HANDLER_NOTIFY. */
432#define VM_FF_REM_HANDLER_NOTIFY_BIT 29
433/** Suspend the VM - debug only. */
434#define VM_FF_DEBUG_SUSPEND RT_BIT_32(VM_FF_DEBUG_SUSPEND_BIT)
435#define VM_FF_DEBUG_SUSPEND_BIT 31
436
437
438/** This action forces the VM to check any pending interrupts on the APIC. */
439#define VMCPU_FF_INTERRUPT_APIC RT_BIT_64(VMCPU_FF_INTERRUPT_APIC_BIT)
440#define VMCPU_FF_INTERRUPT_APIC_BIT 0
441/** This action forces the VM to check any pending interrups on the PIC. */
442#define VMCPU_FF_INTERRUPT_PIC RT_BIT_64(VMCPU_FF_INTERRUPT_PIC_BIT)
443#define VMCPU_FF_INTERRUPT_PIC_BIT 1
444/** This action forces the VM to schedule and run pending timer (TM).
445 * @remarks Don't move - PATM compatibility. */
446#define VMCPU_FF_TIMER RT_BIT_64(VMCPU_FF_TIMER_BIT)
447#define VMCPU_FF_TIMER_BIT 2
448/** This action forces the VM to check any pending NMIs. */
449#define VMCPU_FF_INTERRUPT_NMI RT_BIT_64(VMCPU_FF_INTERRUPT_NMI_BIT)
450#define VMCPU_FF_INTERRUPT_NMI_BIT 3
451/** This action forces the VM to check any pending SMIs. */
452#define VMCPU_FF_INTERRUPT_SMI RT_BIT_64(VMCPU_FF_INTERRUPT_SMI_BIT)
453#define VMCPU_FF_INTERRUPT_SMI_BIT 4
454/** PDM critical section unlocking is pending, process promptly upon return to R3. */
455#define VMCPU_FF_PDM_CRITSECT RT_BIT_64(VMCPU_FF_PDM_CRITSECT_BIT)
456#define VMCPU_FF_PDM_CRITSECT_BIT 5
457/** Special EM internal force flag that is used by EMUnhaltAndWakeUp() to force
458 * the virtual CPU out of the next (/current) halted state. It is not processed
459 * nor cleared by emR3ForcedActions (similar to VMCPU_FF_BLOCK_NMIS), instead it
460 * is cleared the next time EM leaves the HALTED state. */
461#define VMCPU_FF_UNHALT RT_BIT_64(VMCPU_FF_UNHALT_BIT)
462#define VMCPU_FF_UNHALT_BIT 6
463/** Pending IEM action (mask). */
464#define VMCPU_FF_IEM RT_BIT_64(VMCPU_FF_IEM_BIT)
465/** Pending IEM action (bit number). */
466#define VMCPU_FF_IEM_BIT 7
467/** Pending APIC action (bit number). */
468#define VMCPU_FF_UPDATE_APIC_BIT 8
469/** This action forces the VM to update APIC's asynchronously arrived
470 * interrupts as pending interrupts. */
471#define VMCPU_FF_UPDATE_APIC RT_BIT_64(VMCPU_FF_UPDATE_APIC_BIT)
472/** This action forces the VM to service pending requests from other
473 * thread or requests which must be executed in another context. */
474#define VMCPU_FF_REQUEST RT_BIT_64(VMCPU_FF_REQUEST_BIT)
475#define VMCPU_FF_REQUEST_BIT 9
476/** Pending DBGF event (alternative to passing VINF_EM_DBG_EVENT around). */
477#define VMCPU_FF_DBGF RT_BIT_64(VMCPU_FF_DBGF_BIT)
478/** The bit number for VMCPU_FF_DBGF. */
479#define VMCPU_FF_DBGF_BIT 10
480/** This action forces the VM to service any pending updates to CR3 (used only
481 * by HM). */
482/** Hardware virtualized nested-guest interrupt pending. */
483#define VMCPU_FF_INTERRUPT_NESTED_GUEST RT_BIT_64(VMCPU_FF_INTERRUPT_NESTED_GUEST_BIT)
484#define VMCPU_FF_INTERRUPT_NESTED_GUEST_BIT 11
485#define VMCPU_FF_HM_UPDATE_CR3 RT_BIT_64(VMCPU_FF_HM_UPDATE_CR3_BIT)
486#define VMCPU_FF_HM_UPDATE_CR3_BIT 12
487/** This action forces the VM to service any pending updates to PAE PDPEs (used
488 * only by HM). */
489#define VMCPU_FF_HM_UPDATE_PAE_PDPES RT_BIT_64(VMCPU_FF_HM_UPDATE_PAE_PDPES_BIT)
490#define VMCPU_FF_HM_UPDATE_PAE_PDPES_BIT 13
491/** This action forces the VM to resync the page tables before going
492 * back to execute guest code. (GLOBAL FLUSH) */
493#define VMCPU_FF_PGM_SYNC_CR3 RT_BIT_64(VMCPU_FF_PGM_SYNC_CR3_BIT)
494#define VMCPU_FF_PGM_SYNC_CR3_BIT 16
495/** Same as VM_FF_PGM_SYNC_CR3 except that global pages can be skipped.
496 * (NON-GLOBAL FLUSH) */
497#define VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL RT_BIT_64(VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL_BIT)
498#define VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL_BIT 17
499/** Check for pending TLB shootdown actions (deprecated)
500 * Reserved for furture HM re-use if necessary / safe.
501 * Consumer: HM */
502#define VMCPU_FF_TLB_SHOOTDOWN_UNUSED RT_BIT_64(VMCPU_FF_TLB_SHOOTDOWN_UNUSED_BIT)
503#define VMCPU_FF_TLB_SHOOTDOWN_UNUSED_BIT 18
504/** Check for pending TLB flush action.
505 * Consumer: HM
506 * @todo rename to VMCPU_FF_HM_TLB_FLUSH */
507#define VMCPU_FF_TLB_FLUSH RT_BIT_64(VMCPU_FF_TLB_FLUSH_BIT)
508/** The bit number for VMCPU_FF_TLB_FLUSH. */
509#define VMCPU_FF_TLB_FLUSH_BIT 19
510/* 20 used to be VMCPU_FF_TRPM_SYNC_IDT (raw-mode only). */
511/* 21 used to be VMCPU_FF_SELM_SYNC_TSS (raw-mode only). */
512/* 22 used to be VMCPU_FF_SELM_SYNC_GDT (raw-mode only). */
513/* 23 used to be VMCPU_FF_SELM_SYNC_LDT (raw-mode only). */
514/** Inhibit interrupts pending. See EMGetInhibitInterruptsPC(). */
515#define VMCPU_FF_INHIBIT_INTERRUPTS RT_BIT_64(VMCPU_FF_INHIBIT_INTERRUPTS_BIT)
516#define VMCPU_FF_INHIBIT_INTERRUPTS_BIT 24
517/** Block injection of non-maskable interrupts to the guest. */
518#define VMCPU_FF_BLOCK_NMIS RT_BIT_64(VMCPU_FF_BLOCK_NMIS_BIT)
519#define VMCPU_FF_BLOCK_NMIS_BIT 25
520/** Force return to Ring-3. */
521#define VMCPU_FF_TO_R3 RT_BIT_64(VMCPU_FF_TO_R3_BIT)
522#define VMCPU_FF_TO_R3_BIT 28
523/** Force return to ring-3 to service pending I/O or MMIO write.
524 * This is a backup for mechanism VINF_IOM_R3_IOPORT_COMMIT_WRITE and
525 * VINF_IOM_R3_MMIO_COMMIT_WRITE, allowing VINF_EM_DBG_BREAKPOINT and similar
526 * status codes to be propagated at the same time without loss. */
527#define VMCPU_FF_IOM RT_BIT_64(VMCPU_FF_IOM_BIT)
528#define VMCPU_FF_IOM_BIT 29
529/* 30 used to be VMCPU_FF_CPUM */
530/** VMX-preemption timer in effect. */
531#define VMCPU_FF_VMX_PREEMPT_TIMER RT_BIT_64(VMCPU_FF_VMX_PREEMPT_TIMER_BIT)
532#define VMCPU_FF_VMX_PREEMPT_TIMER_BIT 31
533/** Pending MTF (Monitor Trap Flag) event. */
534#define VMCPU_FF_VMX_MTF RT_BIT_64(VMCPU_FF_VMX_MTF_BIT)
535#define VMCPU_FF_VMX_MTF_BIT 32
536/** VMX APIC-write emulation pending. */
537#define VMCPU_FF_VMX_APIC_WRITE RT_BIT_64(VMCPU_FF_VMX_APIC_WRITE_BIT)
538#define VMCPU_FF_VMX_APIC_WRITE_BIT 33
539/** VMX interrupt-window event pending. */
540#define VMCPU_FF_VMX_INT_WINDOW RT_BIT_64(VMCPU_FF_VMX_INT_WINDOW_BIT)
541#define VMCPU_FF_VMX_INT_WINDOW_BIT 34
542/** VMX NMI-window event pending. */
543#define VMCPU_FF_VMX_NMI_WINDOW RT_BIT_64(VMCPU_FF_VMX_NMI_WINDOW_BIT)
544#define VMCPU_FF_VMX_NMI_WINDOW_BIT 35
545
546
547/** Externally VM forced actions. Used to quit the idle/wait loop. */
548#define VM_FF_EXTERNAL_SUSPENDED_MASK ( VM_FF_CHECK_VM_STATE | VM_FF_DBGF | VM_FF_REQUEST | VM_FF_EMT_RENDEZVOUS )
549/** Externally VMCPU forced actions. Used to quit the idle/wait loop. */
550#define VMCPU_FF_EXTERNAL_SUSPENDED_MASK ( VMCPU_FF_REQUEST | VMCPU_FF_DBGF )
551
552/** Externally forced VM actions. Used to quit the idle/wait loop. */
553#define VM_FF_EXTERNAL_HALTED_MASK ( VM_FF_CHECK_VM_STATE | VM_FF_DBGF | VM_FF_REQUEST \
554 | VM_FF_PDM_QUEUES | VM_FF_PDM_DMA | VM_FF_EMT_RENDEZVOUS )
555/** Externally forced VMCPU actions. Used to quit the idle/wait loop. */
556#define VMCPU_FF_EXTERNAL_HALTED_MASK ( VMCPU_FF_UPDATE_APIC | VMCPU_FF_INTERRUPT_APIC | VMCPU_FF_INTERRUPT_PIC \
557 | VMCPU_FF_REQUEST | VMCPU_FF_INTERRUPT_NMI | VMCPU_FF_INTERRUPT_SMI \
558 | VMCPU_FF_UNHALT | VMCPU_FF_TIMER | VMCPU_FF_DBGF \
559 | VMCPU_FF_INTERRUPT_NESTED_GUEST)
560
561/** High priority VM pre-execution actions. */
562#define VM_FF_HIGH_PRIORITY_PRE_MASK ( VM_FF_CHECK_VM_STATE | VM_FF_DBGF | VM_FF_TM_VIRTUAL_SYNC \
563 | VM_FF_DEBUG_SUSPEND | VM_FF_PGM_NEED_HANDY_PAGES | VM_FF_PGM_NO_MEMORY \
564 | VM_FF_EMT_RENDEZVOUS )
565/** High priority VMCPU pre-execution actions. */
566#define VMCPU_FF_HIGH_PRIORITY_PRE_MASK ( VMCPU_FF_TIMER | VMCPU_FF_INTERRUPT_APIC | VMCPU_FF_INTERRUPT_PIC \
567 | VMCPU_FF_UPDATE_APIC | VMCPU_FF_INHIBIT_INTERRUPTS | VMCPU_FF_DBGF \
568 | VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL \
569 | VMCPU_FF_INTERRUPT_NESTED_GUEST | VMCPU_FF_VMX_MTF | VMCPU_FF_VMX_APIC_WRITE \
570 | VMCPU_FF_VMX_PREEMPT_TIMER | VMCPU_FF_VMX_NMI_WINDOW | VMCPU_FF_VMX_INT_WINDOW )
571
572/** High priority VM pre raw-mode execution mask. */
573#define VM_FF_HIGH_PRIORITY_PRE_RAW_MASK ( VM_FF_PGM_NEED_HANDY_PAGES | VM_FF_PGM_NO_MEMORY )
574/** High priority VMCPU pre raw-mode execution mask. */
575#define VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK ( VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL \
576 | VMCPU_FF_INHIBIT_INTERRUPTS )
577
578/** High priority post-execution actions. */
579#define VM_FF_HIGH_PRIORITY_POST_MASK ( VM_FF_PGM_NO_MEMORY )
580/** High priority post-execution actions. */
581#define VMCPU_FF_HIGH_PRIORITY_POST_MASK ( VMCPU_FF_PDM_CRITSECT \
582 | VMCPU_FF_HM_UPDATE_CR3 | VMCPU_FF_HM_UPDATE_PAE_PDPES \
583 | VMCPU_FF_IEM | VMCPU_FF_IOM )
584
585/** Normal priority VM post-execution actions. */
586#define VM_FF_NORMAL_PRIORITY_POST_MASK ( VM_FF_CHECK_VM_STATE | VM_FF_DBGF | VM_FF_RESET \
587 | VM_FF_PGM_NO_MEMORY | VM_FF_EMT_RENDEZVOUS)
588/** Normal priority VMCPU post-execution actions. */
589#define VMCPU_FF_NORMAL_PRIORITY_POST_MASK ( VMCPU_FF_DBGF )
590
591/** Normal priority VM actions. */
592#define VM_FF_NORMAL_PRIORITY_MASK ( VM_FF_REQUEST | VM_FF_PDM_QUEUES | VM_FF_PDM_DMA \
593 | VM_FF_REM_HANDLER_NOTIFY | VM_FF_EMT_RENDEZVOUS)
594/** Normal priority VMCPU actions. */
595#define VMCPU_FF_NORMAL_PRIORITY_MASK ( VMCPU_FF_REQUEST )
596
597/** Flags to clear before resuming guest execution. */
598#define VMCPU_FF_RESUME_GUEST_MASK ( VMCPU_FF_TO_R3 )
599
600
601/** VM flags that cause the REP[|NE|E] STRINS loops to yield immediately. */
602#define VM_FF_HIGH_PRIORITY_POST_REPSTR_MASK ( VM_FF_TM_VIRTUAL_SYNC | VM_FF_PGM_NEED_HANDY_PAGES | VM_FF_PGM_NO_MEMORY \
603 | VM_FF_EMT_RENDEZVOUS | VM_FF_PGM_POOL_FLUSH_PENDING | VM_FF_RESET)
604/** VM flags that cause the REP[|NE|E] STRINS loops to yield. */
605#define VM_FF_YIELD_REPSTR_MASK ( VM_FF_HIGH_PRIORITY_POST_REPSTR_MASK \
606 | VM_FF_PDM_QUEUES | VM_FF_PDM_DMA | VM_FF_DBGF | VM_FF_DEBUG_SUSPEND )
607/** VMCPU flags that cause the REP[|NE|E] STRINS loops to yield immediately. */
608#ifdef IN_RING3
609# define VMCPU_FF_HIGH_PRIORITY_POST_REPSTR_MASK ( VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL | VMCPU_FF_DBGF \
610 | VMCPU_FF_VMX_MTF )
611#else
612# define VMCPU_FF_HIGH_PRIORITY_POST_REPSTR_MASK ( VMCPU_FF_TO_R3 | VMCPU_FF_IEM | VMCPU_FF_IOM | VMCPU_FF_PGM_SYNC_CR3 \
613 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL | VMCPU_FF_DBGF | VMCPU_FF_VMX_MTF )
614#endif
615/** VMCPU flags that cause the REP[|NE|E] STRINS loops to yield, interrupts
616 * enabled. */
617#define VMCPU_FF_YIELD_REPSTR_MASK ( VMCPU_FF_HIGH_PRIORITY_POST_REPSTR_MASK \
618 | VMCPU_FF_INTERRUPT_APIC | VMCPU_FF_UPDATE_APIC | VMCPU_FF_INTERRUPT_PIC \
619 | VMCPU_FF_INTERRUPT_NMI | VMCPU_FF_INTERRUPT_SMI | VMCPU_FF_PDM_CRITSECT \
620 | VMCPU_FF_TIMER | VMCPU_FF_REQUEST \
621 | VMCPU_FF_INTERRUPT_NESTED_GUEST )
622/** VMCPU flags that cause the REP[|NE|E] STRINS loops to yield, interrupts
623 * disabled. */
624#define VMCPU_FF_YIELD_REPSTR_NOINT_MASK ( VMCPU_FF_YIELD_REPSTR_MASK \
625 & ~( VMCPU_FF_INTERRUPT_APIC | VMCPU_FF_UPDATE_APIC | VMCPU_FF_INTERRUPT_PIC \
626 | VMCPU_FF_INTERRUPT_NESTED_GUEST) )
627
628/** VM Flags that cause the HM loops to go back to ring-3. */
629#define VM_FF_HM_TO_R3_MASK ( VM_FF_TM_VIRTUAL_SYNC | VM_FF_PGM_NEED_HANDY_PAGES | VM_FF_PGM_NO_MEMORY \
630 | VM_FF_PDM_QUEUES | VM_FF_EMT_RENDEZVOUS)
631/** VMCPU Flags that cause the HM loops to go back to ring-3. */
632#define VMCPU_FF_HM_TO_R3_MASK ( VMCPU_FF_TO_R3 | VMCPU_FF_TIMER | VMCPU_FF_PDM_CRITSECT \
633 | VMCPU_FF_IEM | VMCPU_FF_IOM)
634
635/** High priority ring-0 VM pre HM-mode execution mask. */
636#define VM_FF_HP_R0_PRE_HM_MASK (VM_FF_HM_TO_R3_MASK | VM_FF_REQUEST | VM_FF_PGM_POOL_FLUSH_PENDING | VM_FF_PDM_DMA)
637/** High priority ring-0 VMCPU pre HM-mode execution mask. */
638#define VMCPU_FF_HP_R0_PRE_HM_MASK ( VMCPU_FF_HM_TO_R3_MASK | VMCPU_FF_PGM_SYNC_CR3 \
639 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL | VMCPU_FF_REQUEST \
640 | VMCPU_FF_VMX_APIC_WRITE | VMCPU_FF_VMX_MTF | VMCPU_FF_VMX_PREEMPT_TIMER)
641/** High priority ring-0 VM pre HM-mode execution mask, single stepping. */
642#define VM_FF_HP_R0_PRE_HM_STEP_MASK (VM_FF_HP_R0_PRE_HM_MASK & ~( VM_FF_TM_VIRTUAL_SYNC | VM_FF_PDM_QUEUES \
643 | VM_FF_EMT_RENDEZVOUS | VM_FF_REQUEST \
644 | VM_FF_PDM_DMA) )
645/** High priority ring-0 VMCPU pre HM-mode execution mask, single stepping. */
646#define VMCPU_FF_HP_R0_PRE_HM_STEP_MASK (VMCPU_FF_HP_R0_PRE_HM_MASK & ~( VMCPU_FF_TO_R3 | VMCPU_FF_TIMER \
647 | VMCPU_FF_PDM_CRITSECT | VMCPU_FF_REQUEST) )
648
649/** All the forced VM flags. */
650#define VM_FF_ALL_MASK (UINT32_MAX)
651/** All the forced VMCPU flags. */
652#define VMCPU_FF_ALL_MASK (UINT32_MAX)
653
654/** All the forced VM flags except those related to raw-mode and hardware
655 * assisted execution. */
656#define VM_FF_ALL_REM_MASK (~(VM_FF_HIGH_PRIORITY_PRE_RAW_MASK) | VM_FF_PGM_NEED_HANDY_PAGES | VM_FF_PGM_NO_MEMORY)
657/** All the forced VMCPU flags except those related to raw-mode and hardware
658 * assisted execution. */
659#define VMCPU_FF_ALL_REM_MASK (~(VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK | VMCPU_FF_PDM_CRITSECT | VMCPU_FF_TLB_FLUSH))
660/** @} */
661
662/** @def VM_FF_SET
663 * Sets a single force action flag.
664 *
665 * @param pVM The cross context VM structure.
666 * @param fFlag The flag to set.
667 */
668#define VM_FF_SET(pVM, fFlag) do { \
669 AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
670 AssertCompile((fFlag) == RT_BIT_32(fFlag##_BIT)); \
671 ASMAtomicOrU32(&(pVM)->fGlobalForcedActions, (fFlag)); \
672 } while (0)
673
674/** @def VMCPU_FF_SET
675 * Sets a single force action flag for the given VCPU.
676 *
677 * @param pVCpu The cross context virtual CPU structure.
678 * @param fFlag The flag to set.
679 * @sa VMCPU_FF_SET_MASK
680 */
681#ifdef VMCPU_WITH_64_BIT_FFS
682# define VMCPU_FF_SET(pVCpu, fFlag) do { \
683 AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
684 AssertCompile((fFlag) == RT_BIT_64(fFlag##_BIT)); \
685 ASMAtomicBitSet(&(pVCpu)->fLocalForcedActions, fFlag##_BIT); \
686 } while (0)
687#else
688# define VMCPU_FF_SET(pVCpu, fFlag) do { \
689 AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
690 AssertCompile((fFlag) == RT_BIT_32(fFlag##_BIT)); \
691 ASMAtomicOrU32(&(pVCpu)->fLocalForcedActions, (fFlag)); \
692 } while (0)
693#endif
694
695/** @def VMCPU_FF_SET_MASK
696 * Sets a two or more force action flag for the given VCPU.
697 *
698 * @param pVCpu The cross context virtual CPU structure.
699 * @param fFlags The flags to set.
700 * @sa VMCPU_FF_SET
701 */
702#ifdef VMCPU_WITH_64_BIT_FFS
703# if ARCH_BITS > 32
704# define VMCPU_FF_SET_MASK(pVCpu, fFlags) \
705 do { ASMAtomicOrU64(&pVCpu->fLocalForcedActions, (fFlags)); } while (0)
706# else
707# define VMCPU_FF_SET_MASK(pVCpu, fFlags) do { \
708 if (!((fFlags) >> 32)) ASMAtomicOrU32((uint32_t volatile *)&pVCpu->fLocalForcedActions, (uint32_t)(fFlags)); \
709 else ASMAtomicOrU64(&pVCpu->fLocalForcedActions, (fFlags)); \
710 } while (0)
711# endif
712#else
713# define VMCPU_FF_SET_MASK(pVCpu, fFlags) \
714 do { ASMAtomicOrU32(&pVCpu->fLocalForcedActions, (fFlags)); } while (0)
715#endif
716
717/** @def VM_FF_CLEAR
718 * Clears a single force action flag.
719 *
720 * @param pVM The cross context VM structure.
721 * @param fFlag The flag to clear.
722 */
723#define VM_FF_CLEAR(pVM, fFlag) do { \
724 AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
725 AssertCompile((fFlag) == RT_BIT_32(fFlag##_BIT)); \
726 ASMAtomicAndU32(&(pVM)->fGlobalForcedActions, ~(fFlag)); \
727 } while (0)
728
729/** @def VMCPU_FF_CLEAR
730 * Clears a single force action flag for the given VCPU.
731 *
732 * @param pVCpu The cross context virtual CPU structure.
733 * @param fFlag The flag to clear.
734 */
735#ifdef VMCPU_WITH_64_BIT_FFS
736# define VMCPU_FF_CLEAR(pVCpu, fFlag) do { \
737 AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
738 AssertCompile((fFlag) == RT_BIT_64(fFlag##_BIT)); \
739 ASMAtomicBitClear(&(pVCpu)->fLocalForcedActions, fFlag##_BIT); \
740 } while (0)
741#else
742# define VMCPU_FF_CLEAR(pVCpu, fFlag) do { \
743 AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
744 AssertCompile((fFlag) == RT_BIT_32(fFlag##_BIT)); \
745 ASMAtomicAndU32(&(pVCpu)->fLocalForcedActions, ~(fFlag)); \
746 } while (0)
747#endif
748
749/** @def VMCPU_FF_CLEAR_MASK
750 * Clears two or more force action flags for the given VCPU.
751 *
752 * @param pVCpu The cross context virtual CPU structure.
753 * @param fFlags The flags to clear.
754 */
755#ifdef VMCPU_WITH_64_BIT_FFS
756# if ARCH_BITS > 32
757# define VMCPU_FF_CLEAR_MASK(pVCpu, fFlags) \
758 do { ASMAtomicAndU64(&(pVCpu)->fLocalForcedActions, ~(fFlags)); } while (0)
759# else
760# define VMCPU_FF_CLEAR_MASK(pVCpu, fFlags) do { \
761 if (!((fFlags) >> 32)) ASMAtomicAndU32((uint32_t volatile *)&(pVCpu)->fLocalForcedActions, ~(uint32_t)(fFlags)); \
762 else ASMAtomicAndU64(&(pVCpu)->fLocalForcedActions, ~(fFlags)); \
763 } while (0)
764# endif
765#else
766# define VMCPU_FF_CLEAR_MASK(pVCpu, fFlags) \
767 do { ASMAtomicAndU32(&(pVCpu)->fLocalForcedActions, ~(fFlags)); } while (0)
768#endif
769
770/** @def VM_FF_IS_SET
771 * Checks if single a force action flag is set.
772 *
773 * @param pVM The cross context VM structure.
774 * @param fFlag The flag to check.
775 * @sa VM_FF_IS_ANY_SET
776 */
777#if !defined(VBOX_STRICT) || !defined(RT_COMPILER_SUPPORTS_LAMBDA)
778# define VM_FF_IS_SET(pVM, fFlag) RT_BOOL((pVM)->fGlobalForcedActions & (fFlag))
779#else
780# define VM_FF_IS_SET(pVM, fFlag) \
781 ([](PVM a_pVM) -> bool \
782 { \
783 AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
784 AssertCompile((fFlag) == RT_BIT_32(fFlag##_BIT)); \
785 return RT_BOOL(a_pVM->fGlobalForcedActions & (fFlag)); \
786 }(pVM))
787#endif
788
789/** @def VMCPU_FF_IS_SET
790 * Checks if a single force action flag is set for the given VCPU.
791 *
792 * @param pVCpu The cross context virtual CPU structure.
793 * @param fFlag The flag to check.
794 * @sa VMCPU_FF_IS_ANY_SET
795 */
796#if !defined(VBOX_STRICT) || !defined(RT_COMPILER_SUPPORTS_LAMBDA)
797# define VMCPU_FF_IS_SET(pVCpu, fFlag) RT_BOOL((pVCpu)->fLocalForcedActions & (fFlag))
798#else
799# define VMCPU_FF_IS_SET(pVCpu, fFlag) \
800 ([](PCVMCPU a_pVCpu) -> bool \
801 { \
802 AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
803 AssertCompile((fFlag) == RT_BIT_64(fFlag##_BIT)); \
804 return RT_BOOL(a_pVCpu->fLocalForcedActions & (fFlag)); \
805 }(pVCpu))
806#endif
807
808/** @def VM_FF_IS_ANY_SET
809 * Checks if one or more force action in the specified set is pending.
810 *
811 * @param pVM The cross context VM structure.
812 * @param fFlags The flags to check for.
813 * @sa VM_FF_IS_SET
814 */
815#define VM_FF_IS_ANY_SET(pVM, fFlags) RT_BOOL((pVM)->fGlobalForcedActions & (fFlags))
816
817/** @def VMCPU_FF_IS_ANY_SET
818 * Checks if two or more force action flags in the specified set is set for the given VCPU.
819 *
820 * @param pVCpu The cross context virtual CPU structure.
821 * @param fFlags The flags to check for.
822 * @sa VMCPU_FF_IS_SET
823 */
824#define VMCPU_FF_IS_ANY_SET(pVCpu, fFlags) RT_BOOL((pVCpu)->fLocalForcedActions & (fFlags))
825
826/** @def VM_FF_TEST_AND_CLEAR
827 * Checks if one (!) force action in the specified set is pending and clears it atomically
828 *
829 * @returns true if the bit was set.
830 * @returns false if the bit was clear.
831 * @param pVM The cross context VM structure.
832 * @param fFlag Flag constant to check and clear (_BIT is appended).
833 */
834#define VM_FF_TEST_AND_CLEAR(pVM, fFlag) (ASMAtomicBitTestAndClear(&(pVM)->fGlobalForcedActions, fFlag##_BIT))
835
836/** @def VMCPU_FF_TEST_AND_CLEAR
837 * Checks if one (!) force action in the specified set is pending and clears it atomically
838 *
839 * @returns true if the bit was set.
840 * @returns false if the bit was clear.
841 * @param pVCpu The cross context virtual CPU structure.
842 * @param fFlag Flag constant to check and clear (_BIT is appended).
843 */
844#define VMCPU_FF_TEST_AND_CLEAR(pVCpu, fFlag) (ASMAtomicBitTestAndClear(&(pVCpu)->fLocalForcedActions, fFlag##_BIT))
845
846/** @def VM_FF_IS_PENDING_EXCEPT
847 * Checks if one or more force action in the specified set is pending while one
848 * or more other ones are not.
849 *
850 * @param pVM The cross context VM structure.
851 * @param fFlags The flags to check for.
852 * @param fExcpt The flags that should not be set.
853 */
854#define VM_FF_IS_PENDING_EXCEPT(pVM, fFlags, fExcpt) \
855 ( ((pVM)->fGlobalForcedActions & (fFlags)) && !((pVM)->fGlobalForcedActions & (fExcpt)) )
856
857/** @def VM_IS_EMT
858 * Checks if the current thread is the emulation thread (EMT).
859 *
860 * @remark The ring-0 variation will need attention if we expand the ring-0
861 * code to let threads other than EMT mess around with the VM.
862 */
863#ifdef IN_RC
864# define VM_IS_EMT(pVM) true
865#else
866# define VM_IS_EMT(pVM) (VMMGetCpu(pVM) != NULL)
867#endif
868
869/** @def VMCPU_IS_EMT
870 * Checks if the current thread is the emulation thread (EMT) for the specified
871 * virtual CPU.
872 */
873#ifdef IN_RC
874# define VMCPU_IS_EMT(pVCpu) true
875#else
876# define VMCPU_IS_EMT(pVCpu) ((pVCpu) && ((pVCpu) == VMMGetCpu((pVCpu)->CTX_SUFF(pVM))))
877#endif
878
879/** @def VM_ASSERT_EMT
880 * Asserts that the current thread IS the emulation thread (EMT).
881 */
882#ifdef IN_RC
883# define VM_ASSERT_EMT(pVM) Assert(VM_IS_EMT(pVM))
884#elif defined(IN_RING0)
885# define VM_ASSERT_EMT(pVM) Assert(VM_IS_EMT(pVM))
886#else
887# define VM_ASSERT_EMT(pVM) \
888 AssertMsg(VM_IS_EMT(pVM), \
889 ("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd\n", RTThreadNativeSelf(), VMR3GetVMCPUNativeThread(pVM)))
890#endif
891
892/** @def VMCPU_ASSERT_EMT
893 * Asserts that the current thread IS the emulation thread (EMT) of the
894 * specified virtual CPU.
895 */
896#ifdef IN_RC
897# define VMCPU_ASSERT_EMT(pVCpu) Assert(VMCPU_IS_EMT(pVCpu))
898#elif defined(IN_RING0)
899# define VMCPU_ASSERT_EMT(pVCpu) AssertMsg(VMCPU_IS_EMT(pVCpu), \
900 ("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd idCpu=%u\n", \
901 RTThreadNativeSelf(), (pVCpu) ? (pVCpu)->hNativeThreadR0 : 0, \
902 (pVCpu) ? (pVCpu)->idCpu : 0))
903#else
904# define VMCPU_ASSERT_EMT(pVCpu) AssertMsg(VMCPU_IS_EMT(pVCpu), \
905 ("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd idCpu=%#x\n", \
906 RTThreadNativeSelf(), (pVCpu)->hNativeThread, (pVCpu)->idCpu))
907#endif
908
909/** @def VM_ASSERT_EMT_RETURN
910 * Asserts that the current thread IS the emulation thread (EMT) and returns if it isn't.
911 */
912#ifdef IN_RC
913# define VM_ASSERT_EMT_RETURN(pVM, rc) AssertReturn(VM_IS_EMT(pVM), (rc))
914#elif defined(IN_RING0)
915# define VM_ASSERT_EMT_RETURN(pVM, rc) AssertReturn(VM_IS_EMT(pVM), (rc))
916#else
917# define VM_ASSERT_EMT_RETURN(pVM, rc) \
918 AssertMsgReturn(VM_IS_EMT(pVM), \
919 ("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd\n", RTThreadNativeSelf(), VMR3GetVMCPUNativeThread(pVM)), \
920 (rc))
921#endif
922
923/** @def VMCPU_ASSERT_EMT_RETURN
924 * Asserts that the current thread IS the emulation thread (EMT) and returns if it isn't.
925 */
926#ifdef IN_RC
927# define VMCPU_ASSERT_EMT_RETURN(pVCpu, rc) AssertReturn(VMCPU_IS_EMT(pVCpu), (rc))
928#elif defined(IN_RING0)
929# define VMCPU_ASSERT_EMT_RETURN(pVCpu, rc) AssertReturn(VMCPU_IS_EMT(pVCpu), (rc))
930#else
931# define VMCPU_ASSERT_EMT_RETURN(pVCpu, rc) \
932 AssertMsgReturn(VMCPU_IS_EMT(pVCpu), \
933 ("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd idCpu=%#x\n", \
934 RTThreadNativeSelf(), (pVCpu)->hNativeThread, (pVCpu)->idCpu), \
935 (rc))
936#endif
937
938/** @def VMCPU_ASSERT_EMT_OR_GURU
939 * Asserts that the current thread IS the emulation thread (EMT) of the
940 * specified virtual CPU.
941 */
942#if defined(IN_RC) || defined(IN_RING0)
943# define VMCPU_ASSERT_EMT_OR_GURU(pVCpu) Assert( VMCPU_IS_EMT(pVCpu) \
944 || pVCpu->CTX_SUFF(pVM)->enmVMState == VMSTATE_GURU_MEDITATION \
945 || pVCpu->CTX_SUFF(pVM)->enmVMState == VMSTATE_GURU_MEDITATION_LS )
946#else
947# define VMCPU_ASSERT_EMT_OR_GURU(pVCpu) \
948 AssertMsg( VMCPU_IS_EMT(pVCpu) \
949 || pVCpu->CTX_SUFF(pVM)->enmVMState == VMSTATE_GURU_MEDITATION \
950 || pVCpu->CTX_SUFF(pVM)->enmVMState == VMSTATE_GURU_MEDITATION_LS, \
951 ("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd idCpu=%#x\n", \
952 RTThreadNativeSelf(), (pVCpu)->hNativeThread, (pVCpu)->idCpu))
953#endif
954
955/** @def VMCPU_ASSERT_EMT_OR_NOT_RUNNING
956 * Asserts that the current thread IS the emulation thread (EMT) of the
957 * specified virtual CPU or the VM is not running.
958 */
959#if defined(IN_RC) || defined(IN_RING0)
960# define VMCPU_ASSERT_EMT_OR_NOT_RUNNING(pVCpu) \
961 Assert( VMCPU_IS_EMT(pVCpu) \
962 || !VM_IS_RUNNING_FOR_ASSERTIONS_ONLY((pVCpu)->CTX_SUFF(pVM)) )
963#else
964# define VMCPU_ASSERT_EMT_OR_NOT_RUNNING(pVCpu) \
965 AssertMsg( VMCPU_IS_EMT(pVCpu) \
966 || !VM_IS_RUNNING_FOR_ASSERTIONS_ONLY((pVCpu)->CTX_SUFF(pVM)), \
967 ("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd idCpu=%#x\n", \
968 RTThreadNativeSelf(), (pVCpu)->hNativeThread, (pVCpu)->idCpu))
969#endif
970
971/** @def VMSTATE_IS_RUNNING
972 * Checks if the given state indicates a running VM.
973 */
974#define VMSTATE_IS_RUNNING(a_enmVMState) \
975 ( (enmVMState) == VMSTATE_RUNNING \
976 || (enmVMState) == VMSTATE_RUNNING_LS )
977
978/** @def VM_IS_RUNNING_FOR_ASSERTIONS_ONLY
979 * Checks if the VM is running.
980 * @note This is only for pure debug assertions. No AssertReturn or similar!
981 * @sa VMSTATE_IS_RUNNING
982 */
983#define VM_IS_RUNNING_FOR_ASSERTIONS_ONLY(pVM) \
984 ( (pVM)->enmVMState == VMSTATE_RUNNING \
985 || (pVM)->enmVMState == VMSTATE_RUNNING_LS )
986
987/** @def VM_ASSERT_IS_NOT_RUNNING
988 * Asserts that the VM is not running.
989 */
990#if defined(IN_RC) || defined(IN_RING0)
991#define VM_ASSERT_IS_NOT_RUNNING(pVM) Assert(!VM_IS_RUNNING_FOR_ASSERTIONS_ONLY(pVM))
992#else
993#define VM_ASSERT_IS_NOT_RUNNING(pVM) AssertMsg(!VM_IS_RUNNING_FOR_ASSERTIONS_ONLY(pVM), \
994 ("VM is running. enmVMState=%d\n", (pVM)->enmVMState))
995#endif
996
997/** @def VM_ASSERT_EMT0
998 * Asserts that the current thread IS emulation thread \#0 (EMT0).
999 */
1000#if (defined(VBOX_BUGREF_9217_PART_I) || defined(VBOX_BUGREF_9217)) && defined(IN_RING3)
1001# define VM_ASSERT_EMT0(a_pVM) VMCPU_ASSERT_EMT((a_pVM)->apCpusR3[0])
1002#else
1003# define VM_ASSERT_EMT0(a_pVM) VMCPU_ASSERT_EMT(&(a_pVM)->aCpus[0])
1004#endif
1005
1006/** @def VM_ASSERT_EMT0_RETURN
1007 * Asserts that the current thread IS emulation thread \#0 (EMT0) and returns if
1008 * it isn't.
1009 */
1010#define VM_ASSERT_EMT0_RETURN(pVM, rc) VMCPU_ASSERT_EMT_RETURN(&(pVM)->aCpus[0], (rc))
1011
1012
1013/**
1014 * Asserts that the current thread is NOT the emulation thread.
1015 */
1016#define VM_ASSERT_OTHER_THREAD(pVM) \
1017 AssertMsg(!VM_IS_EMT(pVM), ("Not other thread!!\n"))
1018
1019
1020/** @def VM_ASSERT_STATE
1021 * Asserts a certain VM state.
1022 */
1023#define VM_ASSERT_STATE(pVM, _enmState) \
1024 AssertMsg((pVM)->enmVMState == (_enmState), \
1025 ("state %s, expected %s\n", VMGetStateName((pVM)->enmVMState), VMGetStateName(_enmState)))
1026
1027/** @def VM_ASSERT_STATE_RETURN
1028 * Asserts a certain VM state and returns if it doesn't match.
1029 */
1030#define VM_ASSERT_STATE_RETURN(pVM, _enmState, rc) \
1031 AssertMsgReturn((pVM)->enmVMState == (_enmState), \
1032 ("state %s, expected %s\n", VMGetStateName((pVM)->enmVMState), VMGetStateName(_enmState)), \
1033 (rc))
1034
1035/** @def VM_IS_VALID_EXT
1036 * Asserts a the VM handle is valid for external access, i.e. not being destroy
1037 * or terminated. */
1038#define VM_IS_VALID_EXT(pVM) \
1039 ( RT_VALID_ALIGNED_PTR(pVM, PAGE_SIZE) \
1040 && ( (unsigned)(pVM)->enmVMState < (unsigned)VMSTATE_DESTROYING \
1041 || ( (unsigned)(pVM)->enmVMState == (unsigned)VMSTATE_DESTROYING \
1042 && VM_IS_EMT(pVM))) )
1043
1044/** @def VM_ASSERT_VALID_EXT_RETURN
1045 * Asserts a the VM handle is valid for external access, i.e. not being
1046 * destroy or terminated.
1047 */
1048#define VM_ASSERT_VALID_EXT_RETURN(pVM, rc) \
1049 AssertMsgReturn(VM_IS_VALID_EXT(pVM), \
1050 ("pVM=%p state %s\n", (pVM), RT_VALID_ALIGNED_PTR(pVM, PAGE_SIZE) \
1051 ? VMGetStateName(pVM->enmVMState) : ""), \
1052 (rc))
1053
1054/** @def VMCPU_ASSERT_VALID_EXT_RETURN
1055 * Asserts a the VMCPU handle is valid for external access, i.e. not being
1056 * destroy or terminated.
1057 */
1058#define VMCPU_ASSERT_VALID_EXT_RETURN(pVCpu, rc) \
1059 AssertMsgReturn( RT_VALID_ALIGNED_PTR(pVCpu, 64) \
1060 && RT_VALID_ALIGNED_PTR((pVCpu)->CTX_SUFF(pVM), PAGE_SIZE) \
1061 && (unsigned)(pVCpu)->CTX_SUFF(pVM)->enmVMState < (unsigned)VMSTATE_DESTROYING, \
1062 ("pVCpu=%p pVM=%p state %s\n", (pVCpu), RT_VALID_ALIGNED_PTR(pVCpu, 64) ? (pVCpu)->CTX_SUFF(pVM) : NULL, \
1063 RT_VALID_ALIGNED_PTR(pVCpu, 64) && RT_VALID_ALIGNED_PTR((pVCpu)->CTX_SUFF(pVM), PAGE_SIZE) \
1064 ? VMGetStateName((pVCpu)->pVMR3->enmVMState) : ""), \
1065 (rc))
1066
1067#endif /* !VBOX_FOR_DTRACE_LIB */
1068
1069
1070/**
1071 * Helper that HM and NEM uses for safely modifying VM::bMainExecutionEngine.
1072 *
1073 * ONLY HM and NEM MAY USE THIS!
1074 *
1075 * @param a_pVM The cross context VM structure.
1076 * @param a_bValue The new value.
1077 * @internal
1078 */
1079#define VM_SET_MAIN_EXECUTION_ENGINE(a_pVM, a_bValue) \
1080 do { \
1081 *const_cast<uint8_t *>(&(a_pVM)->bMainExecutionEngine) = (a_bValue); \
1082 ASMCompilerBarrier(); /* just to be on the safe side */ \
1083 } while (0)
1084
1085/**
1086 * Checks whether raw-mode is used.
1087 *
1088 * @retval true if either is used.
1089 * @retval false if software virtualization (raw-mode) is used.
1090 *
1091 * @param a_pVM The cross context VM structure.
1092 * @sa VM_IS_HM_OR_NEM_ENABLED, VM_IS_HM_ENABLED, VM_IS_NEM_ENABLED.
1093 * @internal
1094 */
1095#ifdef VBOX_WITH_RAW_MODE
1096# define VM_IS_RAW_MODE_ENABLED(a_pVM) ((a_pVM)->bMainExecutionEngine == VM_EXEC_ENGINE_RAW_MODE)
1097#else
1098# define VM_IS_RAW_MODE_ENABLED(a_pVM) (false)
1099#endif
1100
1101/**
1102 * Checks whether HM (VT-x/AMD-V) or NEM is being used by this VM.
1103 *
1104 * @retval true if either is used.
1105 * @retval false if software virtualization (raw-mode) is used.
1106 *
1107 * @param a_pVM The cross context VM structure.
1108 * @sa VM_IS_RAW_MODE_ENABLED, VM_IS_HM_ENABLED, VM_IS_NEM_ENABLED.
1109 * @internal
1110 */
1111#define VM_IS_HM_OR_NEM_ENABLED(a_pVM) ((a_pVM)->bMainExecutionEngine != VM_EXEC_ENGINE_RAW_MODE)
1112
1113/**
1114 * Checks whether HM is being used by this VM.
1115 *
1116 * @retval true if HM (VT-x/AMD-v) is used.
1117 * @retval false if not.
1118 *
1119 * @param a_pVM The cross context VM structure.
1120 * @sa VM_IS_NEM_ENABLED, VM_IS_RAW_MODE_ENABLED, VM_IS_HM_OR_NEM_ENABLED.
1121 * @internal
1122 */
1123#define VM_IS_HM_ENABLED(a_pVM) ((a_pVM)->bMainExecutionEngine == VM_EXEC_ENGINE_HW_VIRT)
1124
1125/**
1126 * Checks whether NEM is being used by this VM.
1127 *
1128 * @retval true if a native hypervisor API is used.
1129 * @retval false if not.
1130 *
1131 * @param a_pVM The cross context VM structure.
1132 * @sa VM_IS_HM_ENABLED, VM_IS_RAW_MODE_ENABLED, VM_IS_HM_OR_NEM_ENABLED.
1133 * @internal
1134 */
1135#define VM_IS_NEM_ENABLED(a_pVM) ((a_pVM)->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API)
1136
1137
1138/**
1139 * The cross context VM structure.
1140 *
1141 * It contains all the VM data which have to be available in all contexts.
1142 * Even if it contains all the data the idea is to use APIs not to modify all
1143 * the members all around the place. Therefore we make use of unions to hide
1144 * everything which isn't local to the current source module. This means we'll
1145 * have to pay a little bit of attention when adding new members to structures
1146 * in the unions and make sure to keep the padding sizes up to date.
1147 *
1148 * Run 'kmk run-struct-tests' (from src/VBox/VMM if you like) after updating!
1149 */
1150typedef struct VM
1151{
1152 /** The state of the VM.
1153 * This field is read only to everyone except the VM and EM. */
1154 VMSTATE volatile enmVMState;
1155 /** Forced action flags.
1156 * See the VM_FF_* \#defines. Updated atomically.
1157 */
1158 volatile uint32_t fGlobalForcedActions;
1159 /** Pointer to the array of page descriptors for the VM structure allocation. */
1160 R3PTRTYPE(PSUPPAGE) paVMPagesR3;
1161 /** Session handle. For use when calling SUPR0 APIs. */
1162#ifdef VBOX_BUGREF_9217
1163 PSUPDRVSESSION pSessionUnsafe;
1164#else
1165 PSUPDRVSESSION pSession;
1166#endif
1167 /** Pointer to the ring-3 VM structure. */
1168 PUVM pUVM;
1169 /** Ring-3 Host Context VM Pointer. */
1170 R3PTRTYPE(struct VM *) pVMR3;
1171#ifndef VBOX_BUGREF_9217
1172 /** Ring-0 Host Context VM Pointer. */
1173 R0PTRTYPE(struct VM *) pVMR0;
1174#else
1175 RTR0PTR R0PtrUnused0;
1176#endif
1177 /** Raw-mode Context VM Pointer. */
1178 uint32_t pVMRC;
1179 /** Padding for new raw-mode (long mode). */
1180 uint32_t pVMRCPadding;
1181
1182 /** The GVM VM handle. Only the GVM should modify this field. */
1183#ifdef VBOX_BUGREF_9217
1184 uint32_t hSelfUnsafe;
1185#else
1186 uint32_t hSelf;
1187#endif
1188 /** Number of virtual CPUs. */
1189#if defined(VBOX_BUGREF_9217) && defined(IN_RING0)
1190 uint32_t cCpusUnsafe;
1191#else
1192 uint32_t cCpus;
1193#endif
1194 /** CPU excution cap (1-100) */
1195 uint32_t uCpuExecutionCap;
1196
1197#ifdef VBOX_BUGREF_9217
1198 /** Size of the VM structure. */
1199 uint32_t cbSelf;
1200 /** Size of the VMCPU structure. */
1201 uint32_t cbVCpu;
1202 /** Structure version number (TBD). */
1203 uint32_t uStructVersion;
1204#else
1205 /** Size of the VM structure including the VMCPU array. */
1206 uint32_t cbSelf;
1207 uint32_t uUnused1;
1208 uint32_t uUnused2;
1209#endif
1210
1211 /** @name Various items that are frequently accessed.
1212 * @{ */
1213 /** The main execution engine, VM_EXEC_ENGINE_XXX.
1214 * This is set early during vmR3InitRing3 by HM or NEM. */
1215 uint8_t const bMainExecutionEngine;
1216
1217 /** Hardware VM support is available and enabled.
1218 * Determined very early during init.
1219 * This is placed here for performance reasons.
1220 * @todo obsoleted by bMainExecutionEngine, eliminate. */
1221 bool fHMEnabled;
1222
1223 /** Large page enabled flag.
1224 * @todo This doesn't need to be here, PGM should store it in it's own
1225 * structures instead. */
1226 bool fUseLargePages;
1227 /** @} */
1228
1229 /** Alignment padding. */
1230 uint8_t uPadding1[5];
1231
1232 /** @name Debugging
1233 * @{ */
1234 /** Ring-3 Host Context VM Pointer. */
1235 R3PTRTYPE(RTTRACEBUF) hTraceBufR3;
1236 /** Ring-0 Host Context VM Pointer. */
1237 R0PTRTYPE(RTTRACEBUF) hTraceBufR0;
1238 /** @} */
1239
1240 /** Padding - the unions must be aligned on a 64 bytes boundary. */
1241 uint8_t abAlignment3[24];
1242
1243 /** CPUM part. */
1244 union
1245 {
1246#ifdef VMM_INCLUDED_SRC_include_CPUMInternal_h
1247 struct CPUM s;
1248#endif
1249#ifdef VBOX_INCLUDED_vmm_cpum_h
1250 /** Read only info exposed about the host and guest CPUs. */
1251 struct
1252 {
1253 /** Padding for hidden fields. */
1254 uint8_t abHidden0[64];
1255 /** Host CPU feature information. */
1256 CPUMFEATURES HostFeatures;
1257 /** Guest CPU feature information. */
1258 CPUMFEATURES GuestFeatures;
1259 } const ro;
1260#endif
1261 uint8_t padding[1536]; /* multiple of 64 */
1262 } cpum;
1263
1264 /** VMM part. */
1265 union
1266 {
1267#ifdef VMM_INCLUDED_SRC_include_VMMInternal_h
1268 struct VMM s;
1269#endif
1270 uint8_t padding[1600]; /* multiple of 64 */
1271 } vmm;
1272
1273 /** PGM part. */
1274 union
1275 {
1276#ifdef VMM_INCLUDED_SRC_include_PGMInternal_h
1277 struct PGM s;
1278#endif
1279 uint8_t padding[20800]; /* multiple of 64 */
1280 } pgm;
1281
1282 /** HM part. */
1283 union
1284 {
1285#ifdef VMM_INCLUDED_SRC_include_HMInternal_h
1286 struct HM s;
1287#endif
1288 uint8_t padding[5440]; /* multiple of 64 */
1289 } hm;
1290
1291 /** TRPM part. */
1292 union
1293 {
1294#ifdef VMM_INCLUDED_SRC_include_TRPMInternal_h
1295 struct TRPM s;
1296#endif
1297 uint8_t padding[5248]; /* multiple of 64 */
1298 } trpm;
1299
1300 /** SELM part. */
1301 union
1302 {
1303#ifdef VMM_INCLUDED_SRC_include_SELMInternal_h
1304 struct SELM s;
1305#endif
1306 uint8_t padding[768]; /* multiple of 64 */
1307 } selm;
1308
1309 /** MM part. */
1310 union
1311 {
1312#ifdef VMM_INCLUDED_SRC_include_MMInternal_h
1313 struct MM s;
1314#endif
1315 uint8_t padding[192]; /* multiple of 64 */
1316 } mm;
1317
1318 /** PDM part. */
1319 union
1320 {
1321#ifdef VMM_INCLUDED_SRC_include_PDMInternal_h
1322 struct PDM s;
1323#endif
1324 uint8_t padding[1920]; /* multiple of 64 */
1325 } pdm;
1326
1327 /** IOM part. */
1328 union
1329 {
1330#ifdef VMM_INCLUDED_SRC_include_IOMInternal_h
1331 struct IOM s;
1332#endif
1333 uint8_t padding[896]; /* multiple of 64 */
1334 } iom;
1335
1336 /** EM part. */
1337 union
1338 {
1339#ifdef VMM_INCLUDED_SRC_include_EMInternal_h
1340 struct EM s;
1341#endif
1342 uint8_t padding[256]; /* multiple of 64 */
1343 } em;
1344
1345 /** NEM part. */
1346 union
1347 {
1348#ifdef VMM_INCLUDED_SRC_include_NEMInternal_h
1349 struct NEM s;
1350#endif
1351 uint8_t padding[128]; /* multiple of 64 */
1352 } nem;
1353
1354 /** TM part. */
1355 union
1356 {
1357#ifdef VMM_INCLUDED_SRC_include_TMInternal_h
1358 struct TM s;
1359#endif
1360 uint8_t padding[7872]; /* multiple of 64 */
1361 } tm;
1362
1363 /** DBGF part. */
1364 union
1365 {
1366#ifdef VMM_INCLUDED_SRC_include_DBGFInternal_h
1367 struct DBGF s;
1368#endif
1369#ifdef VBOX_INCLUDED_vmm_dbgf_h
1370 /** Read only info exposed about interrupt breakpoints and selected events. */
1371 struct
1372 {
1373 /** Bitmap of enabled hardware interrupt breakpoints. */
1374 uint32_t bmHardIntBreakpoints[256 / 32];
1375 /** Bitmap of enabled software interrupt breakpoints. */
1376 uint32_t bmSoftIntBreakpoints[256 / 32];
1377 /** Bitmap of selected events.
1378 * This includes non-selectable events too for simplicity, we maintain the
1379 * state for some of these, as it may come in handy. */
1380 uint64_t bmSelectedEvents[(DBGFEVENT_END + 63) / 64];
1381 /** Enabled hardware interrupt breakpoints. */
1382 uint32_t cHardIntBreakpoints;
1383 /** Enabled software interrupt breakpoints. */
1384 uint32_t cSoftIntBreakpoints;
1385 /** The number of selected events. */
1386 uint32_t cSelectedEvents;
1387 /** The number of enabled hardware breakpoints. */
1388 uint8_t cEnabledHwBreakpoints;
1389 /** The number of enabled hardware I/O breakpoints. */
1390 uint8_t cEnabledHwIoBreakpoints;
1391 /** The number of enabled INT3 breakpoints. */
1392 uint8_t cEnabledInt3Breakpoints;
1393 uint8_t abPadding[1]; /**< Unused padding space up for grabs. */
1394 } const ro;
1395#endif
1396 uint8_t padding[2432]; /* multiple of 64 */
1397 } dbgf;
1398
1399 /** SSM part. */
1400 union
1401 {
1402#ifdef VMM_INCLUDED_SRC_include_SSMInternal_h
1403 struct SSM s;
1404#endif
1405 uint8_t padding[128]; /* multiple of 64 */
1406 } ssm;
1407
1408#ifdef VBOX_WITH_REM
1409 /** REM part. */
1410 union
1411 {
1412# ifdef VMM_INCLUDED_SRC_include_REMInternal_h
1413 struct REM s;
1414# endif
1415 uint8_t padding[0x11100]; /* multiple of 64 */
1416 } rem;
1417#endif
1418
1419 union
1420 {
1421#ifdef VMM_INCLUDED_SRC_include_GIMInternal_h
1422 struct GIM s;
1423#endif
1424 uint8_t padding[448]; /* multiple of 64 */
1425 } gim;
1426
1427 union
1428 {
1429#ifdef VMM_INCLUDED_SRC_include_APICInternal_h
1430 struct APIC s;
1431#endif
1432 uint8_t padding[128]; /* multiple of 8 */
1433 } apic;
1434
1435 /* ---- begin small stuff ---- */
1436
1437 /** VM part. */
1438 union
1439 {
1440#ifdef VMM_INCLUDED_SRC_include_VMInternal_h
1441 struct VMINT s;
1442#endif
1443 uint8_t padding[32]; /* multiple of 8 */
1444 } vm;
1445
1446 /** CFGM part. */
1447 union
1448 {
1449#ifdef VMM_INCLUDED_SRC_include_CFGMInternal_h
1450 struct CFGM s;
1451#endif
1452 uint8_t padding[8]; /* multiple of 8 */
1453 } cfgm;
1454
1455 /** Padding for aligning the structure size on a page boundrary. */
1456#ifdef VBOX_WITH_REM
1457 uint8_t abAlignment2[2520 - sizeof(PVMCPUR0) * VMM_MAX_CPU_COUNT];
1458#else
1459 uint8_t abAlignment2[2520 + 256 - sizeof(PVMCPUR0) * VMM_MAX_CPU_COUNT];
1460#endif
1461
1462 /* ---- end small stuff ---- */
1463#if !defined(VBOX_BUGREF_9217)
1464 /** Array of VMCPU ring-0 pointers. This is temporary as these will
1465 * live in GVM. */
1466 PVMCPUR0 apCpusR0[VMM_MAX_CPU_COUNT];
1467#else
1468 PVMCPUR0 apPaddingR0[VMM_MAX_CPU_COUNT];
1469#endif
1470
1471 /** Array of VMCPU ring-3 pointers. */
1472 PVMCPUR3 apCpusR3[VMM_MAX_CPU_COUNT];
1473#if !defined(VBOX_BUGREF_9217) && !defined(VBOX_BUGREF_9217_PART_I)
1474 /** VMCPU array for the configured number of virtual CPUs.
1475 * Must be aligned on a page boundary for TLB hit reasons as well as
1476 * alignment of VMCPU members. */
1477 VMCPU aCpus[1];
1478#endif
1479} VM;
1480
1481
1482#ifdef IN_RC
1483RT_C_DECLS_BEGIN
1484
1485/** The VM structure.
1486 * This is imported from the VMMRCBuiltin module, i.e. it's a one of those magic
1487 * globals which we should avoid using.
1488 */
1489extern DECLIMPORT(VM) g_VM;
1490
1491/** The VMCPU structure for virtual CPU \#0.
1492 * This is imported from the VMMRCBuiltin module, i.e. it's a one of those magic
1493 * globals which we should avoid using.
1494 */
1495extern DECLIMPORT(VMCPU) g_VCpu0;
1496
1497RT_C_DECLS_END
1498#endif
1499
1500/** @} */
1501
1502#endif /* !VBOX_INCLUDED_vmm_vm_h */
1503
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