vm.h@ 97262

Last change on this file since 97262 was 97178, checked in by vboxsync, 2 years ago
VMM/CPUM,EM,HM,IEM,++: Moved VMCPU_FF_INHIBIT_INTERRUPTS and VMCPU_FF_BLOCK_NMIS to CPUMCTX::fInhibit. Moved ldtr and tr up to the CPUMCTXCORE area in hope for better cache alignment of rip, rflags and crX register fields. bugref:9941
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File size: 57.3 KB

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1	/** @file
2	* VM - The Virtual Machine, data.
3	*/
4
5	/*
6	* Copyright (C) 2006-2022 Oracle and/or its affiliates.
7	*
8	* This file is part of VirtualBox base platform packages, as
9	* available from https://www.virtualbox.org.
10	*
11	* This program is free software; you can redistribute it and/or
12	* modify it under the terms of the GNU General Public License
13	* as published by the Free Software Foundation, in version 3 of the
14	* License.
15	*
16	* This program is distributed in the hope that it will be useful, but
17	* WITHOUT ANY WARRANTY; without even the implied warranty of
18	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19	* General Public License for more details.
20	*
21	* You should have received a copy of the GNU General Public License
22	* along with this program; if not, see <https://www.gnu.org/licenses>.
23	*
24	* The contents of this file may alternatively be used under the terms
25	* of the Common Development and Distribution License Version 1.0
26	* (CDDL), a copy of it is provided in the "COPYING.CDDL" file included
27	* in the VirtualBox distribution, in which case the provisions of the
28	* CDDL are applicable instead of those of the GPL.
29	*
30	* You may elect to license modified versions of this file under the
31	* terms and conditions of either the GPL or the CDDL or both.
32	*
33	* SPDX-License-Identifier: GPL-3.0-only OR CDDL-1.0
34	*/
35
36	#ifndef VBOX_INCLUDED_vmm_vm_h
37	#define VBOX_INCLUDED_vmm_vm_h
38	#ifndef RT_WITHOUT_PRAGMA_ONCE
39	# pragma once
40	#endif
41
42	#ifndef VBOX_FOR_DTRACE_LIB
43	# ifndef USING_VMM_COMMON_DEFS
44	# error "Compile job does not include VMM_COMMON_DEFS from src/VBox/VMM/Config.kmk - make sure you really need to include this file!"
45	# endif
46	# include <iprt/param.h>
47	# include <VBox/param.h>
48	# include <VBox/types.h>
49	# include <VBox/vmm/cpum.h>
50	# include <VBox/vmm/stam.h>
51	# include <VBox/vmm/vmapi.h>
52	# include <VBox/vmm/vmm.h>
53	# include <VBox/sup.h>
54	#else
55	# pragma D depends_on library vbox-types.d
56	# pragma D depends_on library CPUMInternal.d
57	# define VMM_INCLUDED_SRC_include_CPUMInternal_h
58	#endif
59
60
61
62	/** @defgroup grp_vm The Virtual Machine
63	* @ingroup grp_vmm
64	* @{
65	*/
66
67	/**
68	* The state of a Virtual CPU.
69	*
70	* The basic state indicated here is whether the CPU has been started or not. In
71	* addition, there are sub-states when started for assisting scheduling (GVMM
72	* mostly).
73	*
74	* The transition out of the STOPPED state is done by a vmR3PowerOn.
75	* The transition back to the STOPPED state is done by vmR3PowerOff.
76	*
77	* (Alternatively we could let vmR3PowerOn start CPU 0 only and let the SPIP
78	* handling switch on the other CPUs. Then vmR3Reset would stop all but CPU 0.)
79	*/
80	typedef enum VMCPUSTATE
81	{
82	/** The customary invalid zero. */
83	VMCPUSTATE_INVALID = 0,
84
85	/** Virtual CPU has not yet been started. */
86	VMCPUSTATE_STOPPED,
87
88	/** CPU started. */
89	VMCPUSTATE_STARTED,
90	/** CPU started in HM context. */
91	VMCPUSTATE_STARTED_HM,
92	/** Executing guest code and can be poked (RC or STI bits of HM). */
93	VMCPUSTATE_STARTED_EXEC,
94	/** Executing guest code using NEM. */
95	VMCPUSTATE_STARTED_EXEC_NEM,
96	VMCPUSTATE_STARTED_EXEC_NEM_WAIT,
97	VMCPUSTATE_STARTED_EXEC_NEM_CANCELED,
98	/** Halted. */
99	VMCPUSTATE_STARTED_HALTED,
100
101	/** The end of valid virtual CPU states. */
102	VMCPUSTATE_END,
103
104	/** Ensure 32-bit type. */
105	VMCPUSTATE_32BIT_HACK = 0x7fffffff
106	} VMCPUSTATE;
107
108	/** Enables 64-bit FFs. */
109	#define VMCPU_WITH_64_BIT_FFS
110
111
112	/**
113	* The cross context virtual CPU structure.
114	*
115	* Run 'kmk run-struct-tests' (from src/VBox/VMM if you like) after updating!
116	*/
117	typedef struct VMCPU
118	{
119	/** @name Volatile per-cpu data.
120	* @{ */
121	/** Per CPU forced action.
122	* See the VMCPU_FF_* \#defines. Updated atomically. */
123	#ifdef VMCPU_WITH_64_BIT_FFS
124	uint64_t volatile fLocalForcedActions;
125	#else
126	uint32_t volatile fLocalForcedActions;
127	uint32_t fForLocalForcedActionsExpansion;
128	#endif
129	/** The CPU state. */
130	VMCPUSTATE volatile enmState;
131
132	/** Padding up to 64 bytes. */
133	uint8_t abAlignment0[64 - 12];
134	/** @} */
135
136	/** IEM part.
137	* @remarks This comes first as it allows the use of 8-bit immediates for the
138	* first 64 bytes of the structure, reducing code size a wee bit. */
139	#ifdef VMM_INCLUDED_SRC_include_IEMInternal_h /* For PDB hacking. */
140	union VMCPUUNIONIEMFULL
141	#else
142	union VMCPUUNIONIEMSTUB
143	#endif
144	{
145	#ifdef VMM_INCLUDED_SRC_include_IEMInternal_h
146	struct IEMCPU s;
147	#endif
148	uint8_t padding[32832]; /* multiple of 64 */
149	} iem;
150
151	/** @name Static per-cpu data.
152	* (Putting this after IEM, hoping that it's less frequently used than it.)
153	* @{ */
154	/** Ring-3 Host Context VM Pointer. */
155	PVMR3 pVMR3;
156	/** Ring-0 Host Context VM Pointer, currently used by VTG/dtrace. */
157	RTR0PTR pVCpuR0ForVtg;
158	/** Raw-mode Context VM Pointer. */
159	uint32_t pVMRC;
160	/** Padding for new raw-mode (long mode). */
161	uint32_t pVMRCPadding;
162	/** Pointer to the ring-3 UVMCPU structure. */
163	PUVMCPU pUVCpu;
164	/** The native thread handle. */
165	RTNATIVETHREAD hNativeThread;
166	/** The native R0 thread handle. (different from the R3 handle!) */
167	RTNATIVETHREAD hNativeThreadR0;
168	/** The IPRT thread handle (for VMMDevTesting). */
169	RTTHREAD hThread;
170	/** The CPU ID.
171	* This is the index into the VM::aCpu array. */
172	#ifdef IN_RING0
173	VMCPUID idCpuUnsafe;
174	#else
175	VMCPUID idCpu;
176	#endif
177
178	/** Align the structures below bit on a 64-byte boundary and make sure it starts
179	* at the same offset in both 64-bit and 32-bit builds.
180	*
181	* @remarks The alignments of the members that are larger than 48 bytes should be
182	* 64-byte for cache line reasons. structs containing small amounts of
183	* data could be lumped together at the end with a < 64 byte padding
184	* following it (to grow into and align the struct size).
185	*/
186	uint8_t abAlignment1[64 - 6 * (HC_ARCH_BITS == 32 ? 4 : 8) - 8 - 4];
187	/** @} */
188
189	/** HM part. */
190	union VMCPUUNIONHM
191	{
192	#ifdef VMM_INCLUDED_SRC_include_HMInternal_h
193	struct HMCPU s;
194	#endif
195	uint8_t padding[9984]; /* multiple of 64 */
196	} hm;
197
198	/** NEM part. */
199	union VMCPUUNIONNEM
200	{
201	#ifdef VMM_INCLUDED_SRC_include_NEMInternal_h
202	struct NEMCPU s;
203	#endif
204	uint8_t padding[4608]; /* multiple of 64 */
205	} nem;
206
207	/** TRPM part. */
208	union VMCPUUNIONTRPM
209	{
210	#ifdef VMM_INCLUDED_SRC_include_TRPMInternal_h
211	struct TRPMCPU s;
212	#endif
213	uint8_t padding[128]; /* multiple of 64 */
214	} trpm;
215
216	/** TM part. */
217	union VMCPUUNIONTM
218	{
219	#ifdef VMM_INCLUDED_SRC_include_TMInternal_h
220	struct TMCPU s;
221	#endif
222	uint8_t padding[5760]; /* multiple of 64 */
223	} tm;
224
225	/** VMM part. */
226	union VMCPUUNIONVMM
227	{
228	#ifdef VMM_INCLUDED_SRC_include_VMMInternal_h
229	struct VMMCPU s;
230	#endif
231	uint8_t padding[9536]; /* multiple of 64 */
232	} vmm;
233
234	/** PDM part. */
235	union VMCPUUNIONPDM
236	{
237	#ifdef VMM_INCLUDED_SRC_include_PDMInternal_h
238	struct PDMCPU s;
239	#endif
240	uint8_t padding[256]; /* multiple of 64 */
241	} pdm;
242
243	/** IOM part. */
244	union VMCPUUNIONIOM
245	{
246	#ifdef VMM_INCLUDED_SRC_include_IOMInternal_h
247	struct IOMCPU s;
248	#endif
249	uint8_t padding[512]; /* multiple of 64 */
250	} iom;
251
252	/** DBGF part.
253	* @todo Combine this with other tiny structures. */
254	union VMCPUUNIONDBGF
255	{
256	#ifdef VMM_INCLUDED_SRC_include_DBGFInternal_h
257	struct DBGFCPU s;
258	#endif
259	uint8_t padding[512]; /* multiple of 64 */
260	} dbgf;
261
262	/** GIM part. */
263	union VMCPUUNIONGIM
264	{
265	#ifdef VMM_INCLUDED_SRC_include_GIMInternal_h
266	struct GIMCPU s;
267	#endif
268	uint8_t padding[512]; /* multiple of 64 */
269	} gim;
270
271	/** APIC part. */
272	union VMCPUUNIONAPIC
273	{
274	#ifdef VMM_INCLUDED_SRC_include_APICInternal_h
275	struct APICCPU s;
276	#endif
277	uint8_t padding[3840]; /* multiple of 64 */
278	} apic;
279
280	/*
281	* Some less frequently used global members that doesn't need to take up
282	* precious space at the head of the structure.
283	*/
284
285	/** Trace groups enable flags. */
286	uint32_t fTraceGroups; /* 64 / 44 */
287	/** Number of collisions hashing the ring-0 EMT handle. */
288	uint8_t cEmtHashCollisions;
289	uint8_t abAdHoc[3];
290	/** Profiling samples for use by ad hoc profiling. */
291	STAMPROFILEADV aStatAdHoc[8]; /* size: 408 = 320 /
292
293	/** Align the following members on page boundary. */
294	uint8_t abAlignment2[696];
295
296	/** PGM part. */
297	union VMCPUUNIONPGM
298	{
299	#ifdef VMM_INCLUDED_SRC_include_PGMInternal_h
300	struct PGMCPU s;
301	#endif
302	uint8_t padding[4096 + 28672]; /* multiple of 4096 */
303	} pgm;
304
305	/** CPUM part. */
306	union VMCPUUNIONCPUM
307	{
308	#ifdef VMM_INCLUDED_SRC_include_CPUMInternal_h
309	struct CPUMCPU s;
310	#endif
311	#ifdef VMCPU_INCL_CPUM_GST_CTX
312	/** The guest CPUM context for direct use by execution engines.
313	* This is not for general consumption, but for HM, REM, IEM, and maybe a few
314	* others. The rest will use the function based CPUM API. */
315	CPUMCTX GstCtx;
316	#endif
317	uint8_t padding[102400]; /* multiple of 4096 */
318	} cpum;
319
320	/** EM part. */
321	union VMCPUUNIONEM
322	{
323	#ifdef VMM_INCLUDED_SRC_include_EMInternal_h
324	struct EMCPU s;
325	#endif
326	uint8_t padding[40960]; /* multiple of 4096 */
327	} em;
328
329	} VMCPU;
330
331
332	#ifndef VBOX_FOR_DTRACE_LIB
333	/* Make sure the structure size is aligned on a 16384 boundary for arm64 purposes. */
334	AssertCompileSizeAlignment(VMCPU, 16384);
335
336	/** @name Operations on VMCPU::enmState
337	* @{ */
338	/** Gets the VMCPU state. */
339	#define VMCPU_GET_STATE(pVCpu) ( (pVCpu)->enmState )
340	/** Sets the VMCPU state. */
341	#define VMCPU_SET_STATE(pVCpu, enmNewState) \
342	ASMAtomicWriteU32((uint32_t volatile *)&(pVCpu)->enmState, (enmNewState))
343	/** Cmpares and sets the VMCPU state. */
344	#define VMCPU_CMPXCHG_STATE(pVCpu, enmNewState, enmOldState) \
345	ASMAtomicCmpXchgU32((uint32_t volatile *)&(pVCpu)->enmState, (enmNewState), (enmOldState))
346	/** Checks the VMCPU state. */
347	#ifdef VBOX_STRICT
348	# define VMCPU_ASSERT_STATE(pVCpu, enmExpectedState) \
349	do { \
350	VMCPUSTATE enmState = VMCPU_GET_STATE(pVCpu); \
351	AssertMsg(enmState == (enmExpectedState), \
352	("enmState=%d enmExpectedState=%d idCpu=%u\n", \
353	enmState, enmExpectedState, (pVCpu)->idCpu)); \
354	} while (0)
355
356	# define VMCPU_ASSERT_STATE_2(pVCpu, enmExpectedState, a_enmExpectedState2) \
357	do { \
358	VMCPUSTATE enmState = VMCPU_GET_STATE(pVCpu); \
359	AssertMsg( enmState == (enmExpectedState) \
360	\|\| enmState == (a_enmExpectedState2), \
361	("enmState=%d enmExpectedState=%d enmExpectedState2=%d idCpu=%u\n", \
362	enmState, enmExpectedState, a_enmExpectedState2, (pVCpu)->idCpu)); \
363	} while (0)
364	#else
365	# define VMCPU_ASSERT_STATE(pVCpu, enmExpectedState) do { } while (0)
366	# define VMCPU_ASSERT_STATE_2(pVCpu, enmExpectedState, a_enmExpectedState2) do { } while (0)
367	#endif
368	/** Tests if the state means that the CPU is started. */
369	#define VMCPUSTATE_IS_STARTED(enmState) ( (enmState) > VMCPUSTATE_STOPPED )
370	/** Tests if the state means that the CPU is stopped. */
371	#define VMCPUSTATE_IS_STOPPED(enmState) ( (enmState) == VMCPUSTATE_STOPPED )
372	/** @} */
373
374
375	/** The name of the raw-mode context VMM Core module. */
376	#define VMMRC_MAIN_MODULE_NAME "VMMRC.rc"
377	/** The name of the ring-0 context VMM Core module. */
378	#define VMMR0_MAIN_MODULE_NAME "VMMR0.r0"
379
380
381	/** VM Forced Action Flags.
382	*
383	* Use the VM_FF_SET() and VM_FF_CLEAR() macros to change the force
384	* action mask of a VM.
385	*
386	* Available VM bits:
387	* 0, 1, 5, 6, 7, 13, 14, 15, 16, 17, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30
388	*
389	*
390	* Available VMCPU bits:
391	* 14, 15, 36 to 63
392	*
393	* @todo If we run low on VMCPU, we may consider merging the SELM bits
394	*
395	* @{
396	*/
397	/** The virtual sync clock has been stopped, go to TM until it has been
398	* restarted... */
399	#define VM_FF_TM_VIRTUAL_SYNC RT_BIT_32(VM_FF_TM_VIRTUAL_SYNC_BIT)
400	#define VM_FF_TM_VIRTUAL_SYNC_BIT 2
401	/** PDM Queues are pending. */
402	#define VM_FF_PDM_QUEUES RT_BIT_32(VM_FF_PDM_QUEUES_BIT)
403	/** The bit number for VM_FF_PDM_QUEUES. */
404	#define VM_FF_PDM_QUEUES_BIT 3
405	/** PDM DMA transfers are pending. */
406	#define VM_FF_PDM_DMA RT_BIT_32(VM_FF_PDM_DMA_BIT)
407	/** The bit number for VM_FF_PDM_DMA. */
408	#define VM_FF_PDM_DMA_BIT 4
409	/** This action forces the VM to call DBGF so DBGF can service debugger
410	* requests in the emulation thread.
411	* This action flag stays asserted till DBGF clears it.*/
412	#define VM_FF_DBGF RT_BIT_32(VM_FF_DBGF_BIT)
413	/** The bit number for VM_FF_DBGF. */
414	#define VM_FF_DBGF_BIT 8
415	/** This action forces the VM to service pending requests from other
416	* thread or requests which must be executed in another context. */
417	#define VM_FF_REQUEST RT_BIT_32(VM_FF_REQUEST_BIT)
418	#define VM_FF_REQUEST_BIT 9
419	/** Check for VM state changes and take appropriate action. */
420	#define VM_FF_CHECK_VM_STATE RT_BIT_32(VM_FF_CHECK_VM_STATE_BIT)
421	/** The bit number for VM_FF_CHECK_VM_STATE. */
422	#define VM_FF_CHECK_VM_STATE_BIT 10
423	/** Reset the VM. (postponed) */
424	#define VM_FF_RESET RT_BIT_32(VM_FF_RESET_BIT)
425	/** The bit number for VM_FF_RESET. */
426	#define VM_FF_RESET_BIT 11
427	/** EMT rendezvous in VMM. */
428	#define VM_FF_EMT_RENDEZVOUS RT_BIT_32(VM_FF_EMT_RENDEZVOUS_BIT)
429	/** The bit number for VM_FF_EMT_RENDEZVOUS. */
430	#define VM_FF_EMT_RENDEZVOUS_BIT 12
431
432	/** PGM needs to allocate handy pages. */
433	#define VM_FF_PGM_NEED_HANDY_PAGES RT_BIT_32(VM_FF_PGM_NEED_HANDY_PAGES_BIT)
434	#define VM_FF_PGM_NEED_HANDY_PAGES_BIT 18
435	/** PGM is out of memory.
436	* Abandon all loops and code paths which can be resumed and get up to the EM
437	* loops. */
438	#define VM_FF_PGM_NO_MEMORY RT_BIT_32(VM_FF_PGM_NO_MEMORY_BIT)
439	#define VM_FF_PGM_NO_MEMORY_BIT 19
440	/** PGM is about to perform a lightweight pool flush
441	* Guest SMP: all EMT threads should return to ring 3
442	*/
443	#define VM_FF_PGM_POOL_FLUSH_PENDING RT_BIT_32(VM_FF_PGM_POOL_FLUSH_PENDING_BIT)
444	#define VM_FF_PGM_POOL_FLUSH_PENDING_BIT 20
445	/** Suspend the VM - debug only. */
446	#define VM_FF_DEBUG_SUSPEND RT_BIT_32(VM_FF_DEBUG_SUSPEND_BIT)
447	#define VM_FF_DEBUG_SUSPEND_BIT 31
448
449
450	/** This action forces the VM to check any pending interrupts on the APIC. */
451	#define VMCPU_FF_INTERRUPT_APIC RT_BIT_64(VMCPU_FF_INTERRUPT_APIC_BIT)
452	#define VMCPU_FF_INTERRUPT_APIC_BIT 0
453	/** This action forces the VM to check any pending interrups on the PIC. */
454	#define VMCPU_FF_INTERRUPT_PIC RT_BIT_64(VMCPU_FF_INTERRUPT_PIC_BIT)
455	#define VMCPU_FF_INTERRUPT_PIC_BIT 1
456	/** This action forces the VM to schedule and run pending timer (TM).
457	* @remarks Don't move - PATM compatibility. */
458	#define VMCPU_FF_TIMER RT_BIT_64(VMCPU_FF_TIMER_BIT)
459	#define VMCPU_FF_TIMER_BIT 2
460	/** This action forces the VM to check any pending NMIs. */
461	#define VMCPU_FF_INTERRUPT_NMI RT_BIT_64(VMCPU_FF_INTERRUPT_NMI_BIT)
462	#define VMCPU_FF_INTERRUPT_NMI_BIT 3
463	/** This action forces the VM to check any pending SMIs. */
464	#define VMCPU_FF_INTERRUPT_SMI RT_BIT_64(VMCPU_FF_INTERRUPT_SMI_BIT)
465	#define VMCPU_FF_INTERRUPT_SMI_BIT 4
466	/** PDM critical section unlocking is pending, process promptly upon return to R3. */
467	#define VMCPU_FF_PDM_CRITSECT RT_BIT_64(VMCPU_FF_PDM_CRITSECT_BIT)
468	#define VMCPU_FF_PDM_CRITSECT_BIT 5
469	/** Special EM internal force flag that is used by EMUnhaltAndWakeUp() to force
470	* the virtual CPU out of the next (/current) halted state. It is not processed
471	* nor cleared by emR3ForcedActions (similar to VMCPU_FF_BLOCK_NMIS), instead it
472	* is cleared the next time EM leaves the HALTED state. */
473	#define VMCPU_FF_UNHALT RT_BIT_64(VMCPU_FF_UNHALT_BIT)
474	#define VMCPU_FF_UNHALT_BIT 6
475	/** Pending IEM action (mask). */
476	#define VMCPU_FF_IEM RT_BIT_64(VMCPU_FF_IEM_BIT)
477	/** Pending IEM action (bit number). */
478	#define VMCPU_FF_IEM_BIT 7
479	/** Pending APIC action (bit number). */
480	#define VMCPU_FF_UPDATE_APIC_BIT 8
481	/** This action forces the VM to update APIC's asynchronously arrived
482	* interrupts as pending interrupts. */
483	#define VMCPU_FF_UPDATE_APIC RT_BIT_64(VMCPU_FF_UPDATE_APIC_BIT)
484	/** This action forces the VM to service pending requests from other
485	* thread or requests which must be executed in another context. */
486	#define VMCPU_FF_REQUEST RT_BIT_64(VMCPU_FF_REQUEST_BIT)
487	#define VMCPU_FF_REQUEST_BIT 9
488	/** Pending DBGF event (alternative to passing VINF_EM_DBG_EVENT around). */
489	#define VMCPU_FF_DBGF RT_BIT_64(VMCPU_FF_DBGF_BIT)
490	/** The bit number for VMCPU_FF_DBGF. */
491	#define VMCPU_FF_DBGF_BIT 10
492	/** Hardware virtualized nested-guest interrupt pending. */
493	#define VMCPU_FF_INTERRUPT_NESTED_GUEST RT_BIT_64(VMCPU_FF_INTERRUPT_NESTED_GUEST_BIT)
494	#define VMCPU_FF_INTERRUPT_NESTED_GUEST_BIT 11
495	/** This action forces PGM to update changes to CR3 when the guest was in HM mode
496	* (when using nested paging). */
497	#define VMCPU_FF_HM_UPDATE_CR3 RT_BIT_64(VMCPU_FF_HM_UPDATE_CR3_BIT)
498	#define VMCPU_FF_HM_UPDATE_CR3_BIT 12
499	/* Bit 13 used to be VMCPU_FF_HM_UPDATE_PAE_PDPES. */
500	/** This action forces the VM to resync the page tables before going
501	* back to execute guest code. (GLOBAL FLUSH) */
502	#define VMCPU_FF_PGM_SYNC_CR3 RT_BIT_64(VMCPU_FF_PGM_SYNC_CR3_BIT)
503	#define VMCPU_FF_PGM_SYNC_CR3_BIT 16
504	/** Same as VM_FF_PGM_SYNC_CR3 except that global pages can be skipped.
505	* (NON-GLOBAL FLUSH) */
506	#define VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL RT_BIT_64(VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL_BIT)
507	#define VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL_BIT 17
508	/** Check for pending TLB shootdown actions (deprecated)
509	* Reserved for future HM re-use if necessary / safe.
510	* Consumer: HM */
511	#define VMCPU_FF_TLB_SHOOTDOWN_UNUSED RT_BIT_64(VMCPU_FF_TLB_SHOOTDOWN_UNUSED_BIT)
512	#define VMCPU_FF_TLB_SHOOTDOWN_UNUSED_BIT 18
513	/** Check for pending TLB flush action.
514	* Consumer: HM
515	* @todo rename to VMCPU_FF_HM_TLB_FLUSH */
516	#define VMCPU_FF_TLB_FLUSH RT_BIT_64(VMCPU_FF_TLB_FLUSH_BIT)
517	/** The bit number for VMCPU_FF_TLB_FLUSH. */
518	#define VMCPU_FF_TLB_FLUSH_BIT 19
519	/* 20 used to be VMCPU_FF_TRPM_SYNC_IDT (raw-mode only). */
520	/* 21 used to be VMCPU_FF_SELM_SYNC_TSS (raw-mode only). */
521	/* 22 used to be VMCPU_FF_SELM_SYNC_GDT (raw-mode only). */
522	/* 23 used to be VMCPU_FF_SELM_SYNC_LDT (raw-mode only). */
523	/* 24 used to be VMCPU_FF_INHIBIT_INTERRUPTS, which moved to CPUMCTX::fInhibit in v7.0.4. */
524	/* 25 used to be VMCPU_FF_BLOCK_NMIS, which moved to CPUMCTX::fInhibit in v7.0.4. */
525	/** Force return to Ring-3. */
526	#define VMCPU_FF_TO_R3 RT_BIT_64(VMCPU_FF_TO_R3_BIT)
527	#define VMCPU_FF_TO_R3_BIT 28
528	/** Force return to ring-3 to service pending I/O or MMIO write.
529	* This is a backup for mechanism VINF_IOM_R3_IOPORT_COMMIT_WRITE and
530	* VINF_IOM_R3_MMIO_COMMIT_WRITE, allowing VINF_EM_DBG_BREAKPOINT and similar
531	* status codes to be propagated at the same time without loss. */
532	#define VMCPU_FF_IOM RT_BIT_64(VMCPU_FF_IOM_BIT)
533	#define VMCPU_FF_IOM_BIT 29
534	/* 30 used to be VMCPU_FF_CPUM */
535	/** VMX-preemption timer expired. */
536	#define VMCPU_FF_VMX_PREEMPT_TIMER RT_BIT_64(VMCPU_FF_VMX_PREEMPT_TIMER_BIT)
537	#define VMCPU_FF_VMX_PREEMPT_TIMER_BIT 31
538	/** Pending MTF (Monitor Trap Flag) event. */
539	#define VMCPU_FF_VMX_MTF RT_BIT_64(VMCPU_FF_VMX_MTF_BIT)
540	#define VMCPU_FF_VMX_MTF_BIT 32
541	/** VMX APIC-write emulation pending. */
542	#define VMCPU_FF_VMX_APIC_WRITE RT_BIT_64(VMCPU_FF_VMX_APIC_WRITE_BIT)
543	#define VMCPU_FF_VMX_APIC_WRITE_BIT 33
544	/** VMX interrupt-window event pending. */
545	#define VMCPU_FF_VMX_INT_WINDOW RT_BIT_64(VMCPU_FF_VMX_INT_WINDOW_BIT)
546	#define VMCPU_FF_VMX_INT_WINDOW_BIT 34
547	/** VMX NMI-window event pending. */
548	#define VMCPU_FF_VMX_NMI_WINDOW RT_BIT_64(VMCPU_FF_VMX_NMI_WINDOW_BIT)
549	#define VMCPU_FF_VMX_NMI_WINDOW_BIT 35
550
551
552	/** Externally VM forced actions. Used to quit the idle/wait loop. */
553	#define VM_FF_EXTERNAL_SUSPENDED_MASK ( VM_FF_CHECK_VM_STATE \| VM_FF_DBGF \| VM_FF_REQUEST \| VM_FF_EMT_RENDEZVOUS )
554	/** Externally VMCPU forced actions. Used to quit the idle/wait loop. */
555	#define VMCPU_FF_EXTERNAL_SUSPENDED_MASK ( VMCPU_FF_REQUEST \| VMCPU_FF_DBGF )
556
557	/** Externally forced VM actions. Used to quit the idle/wait loop. */
558	#define VM_FF_EXTERNAL_HALTED_MASK ( VM_FF_CHECK_VM_STATE \| VM_FF_DBGF \| VM_FF_REQUEST \
559	\| VM_FF_PDM_QUEUES \| VM_FF_PDM_DMA \| VM_FF_EMT_RENDEZVOUS )
560	/** Externally forced VMCPU actions. Used to quit the idle/wait loop. */
561	#define VMCPU_FF_EXTERNAL_HALTED_MASK ( VMCPU_FF_UPDATE_APIC \| VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC \
562	\| VMCPU_FF_REQUEST \| VMCPU_FF_INTERRUPT_NMI \| VMCPU_FF_INTERRUPT_SMI \
563	\| VMCPU_FF_UNHALT \| VMCPU_FF_TIMER \| VMCPU_FF_DBGF \
564	\| VMCPU_FF_INTERRUPT_NESTED_GUEST)
565
566	/** High priority VM pre-execution actions. */
567	#define VM_FF_HIGH_PRIORITY_PRE_MASK ( VM_FF_CHECK_VM_STATE \| VM_FF_DBGF \| VM_FF_TM_VIRTUAL_SYNC \
568	\| VM_FF_DEBUG_SUSPEND \| VM_FF_PGM_NEED_HANDY_PAGES \| VM_FF_PGM_NO_MEMORY \
569	\| VM_FF_EMT_RENDEZVOUS )
570	/** High priority VMCPU pre-execution actions. */
571	#define VMCPU_FF_HIGH_PRIORITY_PRE_MASK ( VMCPU_FF_TIMER \| VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC \
572	\| VMCPU_FF_UPDATE_APIC \| VMCPU_FF_DBGF \
573	\| VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL \
574	\| VMCPU_FF_INTERRUPT_NESTED_GUEST \| VMCPU_FF_VMX_MTF \| VMCPU_FF_VMX_APIC_WRITE \
575	\| VMCPU_FF_VMX_PREEMPT_TIMER \| VMCPU_FF_VMX_NMI_WINDOW \| VMCPU_FF_VMX_INT_WINDOW )
576
577	/** High priority VM pre raw-mode execution mask. */
578	#define VM_FF_HIGH_PRIORITY_PRE_RAW_MASK ( VM_FF_PGM_NEED_HANDY_PAGES \| VM_FF_PGM_NO_MEMORY )
579	/** High priority VMCPU pre raw-mode execution mask. */
580	#define VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK ( VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL )
581
582	/** High priority post-execution actions. */
583	#define VM_FF_HIGH_PRIORITY_POST_MASK ( VM_FF_PGM_NO_MEMORY )
584	/** High priority post-execution actions. */
585	#define VMCPU_FF_HIGH_PRIORITY_POST_MASK ( VMCPU_FF_PDM_CRITSECT \| VMCPU_FF_HM_UPDATE_CR3 \| VMCPU_FF_IEM \| VMCPU_FF_IOM )
586
587	/** Normal priority VM post-execution actions. */
588	#define VM_FF_NORMAL_PRIORITY_POST_MASK ( VM_FF_CHECK_VM_STATE \| VM_FF_DBGF \| VM_FF_RESET \
589	\| VM_FF_PGM_NO_MEMORY \| VM_FF_EMT_RENDEZVOUS)
590	/** Normal priority VMCPU post-execution actions. */
591	#define VMCPU_FF_NORMAL_PRIORITY_POST_MASK ( VMCPU_FF_DBGF )
592
593	/** Normal priority VM actions. */
594	#define VM_FF_NORMAL_PRIORITY_MASK ( VM_FF_REQUEST \| VM_FF_PDM_QUEUES \| VM_FF_PDM_DMA \| VM_FF_EMT_RENDEZVOUS)
595	/** Normal priority VMCPU actions. */
596	#define VMCPU_FF_NORMAL_PRIORITY_MASK ( VMCPU_FF_REQUEST )
597
598	/** Flags to clear before resuming guest execution. */
599	#define VMCPU_FF_RESUME_GUEST_MASK ( VMCPU_FF_TO_R3 )
600
601
602	/** VM flags that cause the REP[\|NE\|E] STRINS loops to yield immediately. */
603	#define VM_FF_HIGH_PRIORITY_POST_REPSTR_MASK ( VM_FF_TM_VIRTUAL_SYNC \| VM_FF_PGM_NEED_HANDY_PAGES \| VM_FF_PGM_NO_MEMORY \
604	\| VM_FF_EMT_RENDEZVOUS \| VM_FF_PGM_POOL_FLUSH_PENDING \| VM_FF_RESET)
605	/** VM flags that cause the REP[\|NE\|E] STRINS loops to yield. */
606	#define VM_FF_YIELD_REPSTR_MASK ( VM_FF_HIGH_PRIORITY_POST_REPSTR_MASK \
607	\| VM_FF_PDM_QUEUES \| VM_FF_PDM_DMA \| VM_FF_DBGF \| VM_FF_DEBUG_SUSPEND )
608	/** VMCPU flags that cause the REP[\|NE\|E] STRINS loops to yield immediately. */
609	#ifdef IN_RING3
610	# define VMCPU_FF_HIGH_PRIORITY_POST_REPSTR_MASK ( VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL \| VMCPU_FF_DBGF \
611	\| VMCPU_FF_VMX_MTF )
612	#else
613	# define VMCPU_FF_HIGH_PRIORITY_POST_REPSTR_MASK ( VMCPU_FF_TO_R3 \| VMCPU_FF_IEM \| VMCPU_FF_IOM \| VMCPU_FF_PGM_SYNC_CR3 \
614	\| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL \| VMCPU_FF_DBGF \| VMCPU_FF_VMX_MTF )
615	#endif
616	/** VMCPU flags that cause the REP[\|NE\|E] STRINS loops to yield, interrupts
617	* enabled. */
618	#define VMCPU_FF_YIELD_REPSTR_MASK ( VMCPU_FF_HIGH_PRIORITY_POST_REPSTR_MASK \
619	\| VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_UPDATE_APIC \| VMCPU_FF_INTERRUPT_PIC \
620	\| VMCPU_FF_INTERRUPT_NMI \| VMCPU_FF_INTERRUPT_SMI \| VMCPU_FF_PDM_CRITSECT \
621	\| VMCPU_FF_TIMER \| VMCPU_FF_REQUEST \
622	\| VMCPU_FF_INTERRUPT_NESTED_GUEST )
623	/** VMCPU flags that cause the REP[\|NE\|E] STRINS loops to yield, interrupts
624	* disabled. */
625	#define VMCPU_FF_YIELD_REPSTR_NOINT_MASK ( VMCPU_FF_YIELD_REPSTR_MASK \
626	& ~( VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_UPDATE_APIC \| VMCPU_FF_INTERRUPT_PIC \
627	\| VMCPU_FF_INTERRUPT_NESTED_GUEST) )
628
629	/** VM Flags that cause the HM loops to go back to ring-3. */
630	#define VM_FF_HM_TO_R3_MASK ( VM_FF_TM_VIRTUAL_SYNC \| VM_FF_PGM_NEED_HANDY_PAGES \| VM_FF_PGM_NO_MEMORY \
631	\| VM_FF_PDM_QUEUES \| VM_FF_EMT_RENDEZVOUS)
632	/** VMCPU Flags that cause the HM loops to go back to ring-3. */
633	#define VMCPU_FF_HM_TO_R3_MASK ( VMCPU_FF_TO_R3 \| VMCPU_FF_TIMER \| VMCPU_FF_PDM_CRITSECT \
634	\| VMCPU_FF_IEM \| VMCPU_FF_IOM)
635
636	/** High priority ring-0 VM pre HM-mode execution mask. */
637	#define VM_FF_HP_R0_PRE_HM_MASK (VM_FF_HM_TO_R3_MASK \| VM_FF_REQUEST \| VM_FF_PGM_POOL_FLUSH_PENDING \| VM_FF_PDM_DMA)
638	/** High priority ring-0 VMCPU pre HM-mode execution mask. */
639	#define VMCPU_FF_HP_R0_PRE_HM_MASK ( VMCPU_FF_HM_TO_R3_MASK \| VMCPU_FF_PGM_SYNC_CR3 \
640	\| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL \| VMCPU_FF_REQUEST \
641	\| VMCPU_FF_VMX_APIC_WRITE \| VMCPU_FF_VMX_MTF \| VMCPU_FF_VMX_PREEMPT_TIMER)
642	/** High priority ring-0 VM pre HM-mode execution mask, single stepping. */
643	#define VM_FF_HP_R0_PRE_HM_STEP_MASK (VM_FF_HP_R0_PRE_HM_MASK & ~( VM_FF_TM_VIRTUAL_SYNC \| VM_FF_PDM_QUEUES \
644	\| VM_FF_EMT_RENDEZVOUS \| VM_FF_REQUEST \
645	\| VM_FF_PDM_DMA) )
646	/** High priority ring-0 VMCPU pre HM-mode execution mask, single stepping. */
647	#define VMCPU_FF_HP_R0_PRE_HM_STEP_MASK (VMCPU_FF_HP_R0_PRE_HM_MASK & ~( VMCPU_FF_TO_R3 \| VMCPU_FF_TIMER \
648	\| VMCPU_FF_PDM_CRITSECT \| VMCPU_FF_REQUEST) )
649
650	/** All the VMX nested-guest flags. */
651	#define VMCPU_FF_VMX_ALL_MASK ( VMCPU_FF_VMX_PREEMPT_TIMER \| VMCPU_FF_VMX_MTF \| VMCPU_FF_VMX_APIC_WRITE \
652	\| VMCPU_FF_VMX_INT_WINDOW \| VMCPU_FF_VMX_NMI_WINDOW )
653
654	/** All the forced VM flags. */
655	#define VM_FF_ALL_MASK (UINT32_MAX)
656	/** All the forced VMCPU flags. */
657	#define VMCPU_FF_ALL_MASK (UINT32_MAX)
658
659	/** All the forced VM flags except those related to raw-mode and hardware
660	* assisted execution. */
661	#define VM_FF_ALL_REM_MASK (~(VM_FF_HIGH_PRIORITY_PRE_RAW_MASK) \| VM_FF_PGM_NEED_HANDY_PAGES \| VM_FF_PGM_NO_MEMORY)
662	/** All the forced VMCPU flags except those related to raw-mode and hardware
663	* assisted execution. */
664	#define VMCPU_FF_ALL_REM_MASK (~(VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK \| VMCPU_FF_PDM_CRITSECT \| VMCPU_FF_TLB_FLUSH))
665	/** @} */
666
667	/** @def VM_FF_SET
668	* Sets a single force action flag.
669	*
670	* @param pVM The cross context VM structure.
671	* @param fFlag The flag to set.
672	*/
673	#define VM_FF_SET(pVM, fFlag) do { \
674	AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
675	AssertCompile((fFlag) == RT_BIT_32(fFlag##_BIT)); \
676	ASMAtomicOrU32(&(pVM)->fGlobalForcedActions, (fFlag)); \
677	} while (0)
678
679	/** @def VMCPU_FF_SET
680	* Sets a single force action flag for the given VCPU.
681	*
682	* @param pVCpu The cross context virtual CPU structure.
683	* @param fFlag The flag to set.
684	* @sa VMCPU_FF_SET_MASK
685	*/
686	#ifdef VMCPU_WITH_64_BIT_FFS
687	# define VMCPU_FF_SET(pVCpu, fFlag) do { \
688	AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
689	AssertCompile((fFlag) == RT_BIT_64(fFlag##_BIT)); \
690	ASMAtomicBitSet(&(pVCpu)->fLocalForcedActions, fFlag##_BIT); \
691	} while (0)
692	#else
693	# define VMCPU_FF_SET(pVCpu, fFlag) do { \
694	AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
695	AssertCompile((fFlag) == RT_BIT_32(fFlag##_BIT)); \
696	ASMAtomicOrU32(&(pVCpu)->fLocalForcedActions, (fFlag)); \
697	} while (0)
698	#endif
699
700	/** @def VMCPU_FF_SET_MASK
701	* Sets a two or more force action flag for the given VCPU.
702	*
703	* @param pVCpu The cross context virtual CPU structure.
704	* @param fFlags The flags to set.
705	* @sa VMCPU_FF_SET
706	*/
707	#ifdef VMCPU_WITH_64_BIT_FFS
708	# if ARCH_BITS > 32
709	# define VMCPU_FF_SET_MASK(pVCpu, fFlags) \
710	do { ASMAtomicOrU64(&pVCpu->fLocalForcedActions, (fFlags)); } while (0)
711	# else
712	# define VMCPU_FF_SET_MASK(pVCpu, fFlags) do { \
713	if (!((fFlags) >> 32)) ASMAtomicOrU32((uint32_t volatile *)&pVCpu->fLocalForcedActions, (uint32_t)(fFlags)); \
714	else ASMAtomicOrU64(&pVCpu->fLocalForcedActions, (fFlags)); \
715	} while (0)
716	# endif
717	#else
718	# define VMCPU_FF_SET_MASK(pVCpu, fFlags) \
719	do { ASMAtomicOrU32(&pVCpu->fLocalForcedActions, (fFlags)); } while (0)
720	#endif
721
722	/** @def VM_FF_CLEAR
723	* Clears a single force action flag.
724	*
725	* @param pVM The cross context VM structure.
726	* @param fFlag The flag to clear.
727	*/
728	#define VM_FF_CLEAR(pVM, fFlag) do { \
729	AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
730	AssertCompile((fFlag) == RT_BIT_32(fFlag##_BIT)); \
731	ASMAtomicAndU32(&(pVM)->fGlobalForcedActions, ~(fFlag)); \
732	} while (0)
733
734	/** @def VMCPU_FF_CLEAR
735	* Clears a single force action flag for the given VCPU.
736	*
737	* @param pVCpu The cross context virtual CPU structure.
738	* @param fFlag The flag to clear.
739	*/
740	#ifdef VMCPU_WITH_64_BIT_FFS
741	# define VMCPU_FF_CLEAR(pVCpu, fFlag) do { \
742	AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
743	AssertCompile((fFlag) == RT_BIT_64(fFlag##_BIT)); \
744	ASMAtomicBitClear(&(pVCpu)->fLocalForcedActions, fFlag##_BIT); \
745	} while (0)
746	#else
747	# define VMCPU_FF_CLEAR(pVCpu, fFlag) do { \
748	AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
749	AssertCompile((fFlag) == RT_BIT_32(fFlag##_BIT)); \
750	ASMAtomicAndU32(&(pVCpu)->fLocalForcedActions, ~(fFlag)); \
751	} while (0)
752	#endif
753
754	/** @def VMCPU_FF_CLEAR_MASK
755	* Clears two or more force action flags for the given VCPU.
756	*
757	* @param pVCpu The cross context virtual CPU structure.
758	* @param fFlags The flags to clear.
759	*/
760	#ifdef VMCPU_WITH_64_BIT_FFS
761	# if ARCH_BITS > 32
762	# define VMCPU_FF_CLEAR_MASK(pVCpu, fFlags) \
763	do { ASMAtomicAndU64(&(pVCpu)->fLocalForcedActions, ~(fFlags)); } while (0)
764	# else
765	# define VMCPU_FF_CLEAR_MASK(pVCpu, fFlags) do { \
766	if (!((fFlags) >> 32)) ASMAtomicAndU32((uint32_t volatile *)&(pVCpu)->fLocalForcedActions, ~(uint32_t)(fFlags)); \
767	else ASMAtomicAndU64(&(pVCpu)->fLocalForcedActions, ~(fFlags)); \
768	} while (0)
769	# endif
770	#else
771	# define VMCPU_FF_CLEAR_MASK(pVCpu, fFlags) \
772	do { ASMAtomicAndU32(&(pVCpu)->fLocalForcedActions, ~(fFlags)); } while (0)
773	#endif
774
775	/** @def VM_FF_IS_SET
776	* Checks if single a force action flag is set.
777	*
778	* @param pVM The cross context VM structure.
779	* @param fFlag The flag to check.
780	* @sa VM_FF_IS_ANY_SET
781	*/
782	#if !defined(VBOX_STRICT) \|\| !defined(RT_COMPILER_SUPPORTS_LAMBDA)
783	# define VM_FF_IS_SET(pVM, fFlag) RT_BOOL((pVM)->fGlobalForcedActions & (fFlag))
784	#else
785	# define VM_FF_IS_SET(pVM, fFlag) \
786	([](PVM a_pVM) -> bool \
787	{ \
788	AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
789	AssertCompile((fFlag) == RT_BIT_32(fFlag##_BIT)); \
790	return RT_BOOL(a_pVM->fGlobalForcedActions & (fFlag)); \
791	}(pVM))
792	#endif
793
794	/** @def VMCPU_FF_IS_SET
795	* Checks if a single force action flag is set for the given VCPU.
796	*
797	* @param pVCpu The cross context virtual CPU structure.
798	* @param fFlag The flag to check.
799	* @sa VMCPU_FF_IS_ANY_SET
800	*/
801	#if !defined(VBOX_STRICT) \|\| !defined(RT_COMPILER_SUPPORTS_LAMBDA)
802	# define VMCPU_FF_IS_SET(pVCpu, fFlag) RT_BOOL((pVCpu)->fLocalForcedActions & (fFlag))
803	#else
804	# define VMCPU_FF_IS_SET(pVCpu, fFlag) \
805	([](PCVMCPU a_pVCpu) -> bool \
806	{ \
807	AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
808	AssertCompile((fFlag) == RT_BIT_64(fFlag##_BIT)); \
809	return RT_BOOL(a_pVCpu->fLocalForcedActions & (fFlag)); \
810	}(pVCpu))
811	#endif
812
813	/** @def VM_FF_IS_ANY_SET
814	* Checks if one or more force action in the specified set is pending.
815	*
816	* @param pVM The cross context VM structure.
817	* @param fFlags The flags to check for.
818	* @sa VM_FF_IS_SET
819	*/
820	#define VM_FF_IS_ANY_SET(pVM, fFlags) RT_BOOL((pVM)->fGlobalForcedActions & (fFlags))
821
822	/** @def VMCPU_FF_IS_ANY_SET
823	* Checks if two or more force action flags in the specified set is set for the given VCPU.
824	*
825	* @param pVCpu The cross context virtual CPU structure.
826	* @param fFlags The flags to check for.
827	* @sa VMCPU_FF_IS_SET
828	*/
829	#define VMCPU_FF_IS_ANY_SET(pVCpu, fFlags) RT_BOOL((pVCpu)->fLocalForcedActions & (fFlags))
830
831	/** @def VM_FF_TEST_AND_CLEAR
832	* Checks if one (!) force action in the specified set is pending and clears it atomically
833	*
834	* @returns true if the bit was set.
835	* @returns false if the bit was clear.
836	* @param pVM The cross context VM structure.
837	* @param fFlag Flag constant to check and clear (_BIT is appended).
838	*/
839	#define VM_FF_TEST_AND_CLEAR(pVM, fFlag) (ASMAtomicBitTestAndClear(&(pVM)->fGlobalForcedActions, fFlag##_BIT))
840
841	/** @def VMCPU_FF_TEST_AND_CLEAR
842	* Checks if one (!) force action in the specified set is pending and clears it atomically
843	*
844	* @returns true if the bit was set.
845	* @returns false if the bit was clear.
846	* @param pVCpu The cross context virtual CPU structure.
847	* @param fFlag Flag constant to check and clear (_BIT is appended).
848	*/
849	#define VMCPU_FF_TEST_AND_CLEAR(pVCpu, fFlag) (ASMAtomicBitTestAndClear(&(pVCpu)->fLocalForcedActions, fFlag##_BIT))
850
851	/** @def VM_FF_IS_PENDING_EXCEPT
852	* Checks if one or more force action in the specified set is pending while one
853	* or more other ones are not.
854	*
855	* @param pVM The cross context VM structure.
856	* @param fFlags The flags to check for.
857	* @param fExcpt The flags that should not be set.
858	*/
859	#define VM_FF_IS_PENDING_EXCEPT(pVM, fFlags, fExcpt) \
860	( ((pVM)->fGlobalForcedActions & (fFlags)) && !((pVM)->fGlobalForcedActions & (fExcpt)) )
861
862	/** @def VM_IS_EMT
863	* Checks if the current thread is the emulation thread (EMT).
864	*
865	* @remark The ring-0 variation will need attention if we expand the ring-0
866	* code to let threads other than EMT mess around with the VM.
867	*/
868	#ifdef IN_RC
869	# define VM_IS_EMT(pVM) true
870	#else
871	# define VM_IS_EMT(pVM) (VMMGetCpu(pVM) != NULL)
872	#endif
873
874	/** @def VMCPU_IS_EMT
875	* Checks if the current thread is the emulation thread (EMT) for the specified
876	* virtual CPU.
877	*/
878	#ifdef IN_RC
879	# define VMCPU_IS_EMT(pVCpu) true
880	#else
881	# define VMCPU_IS_EMT(pVCpu) ((pVCpu) && ((pVCpu) == VMMGetCpu((pVCpu)->CTX_SUFF(pVM))))
882	#endif
883
884	/** @def VM_ASSERT_EMT
885	* Asserts that the current thread IS the emulation thread (EMT).
886	*/
887	#ifdef IN_RC
888	# define VM_ASSERT_EMT(pVM) Assert(VM_IS_EMT(pVM))
889	#elif defined(IN_RING0)
890	# define VM_ASSERT_EMT(pVM) Assert(VM_IS_EMT(pVM))
891	#else
892	# define VM_ASSERT_EMT(pVM) \
893	AssertMsg(VM_IS_EMT(pVM), \
894	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd\n", RTThreadNativeSelf(), VMR3GetVMCPUNativeThread(pVM)))
895	#endif
896
897	/** @def VMCPU_ASSERT_EMT
898	* Asserts that the current thread IS the emulation thread (EMT) of the
899	* specified virtual CPU.
900	*/
901	#ifdef IN_RC
902	# define VMCPU_ASSERT_EMT(pVCpu) Assert(VMCPU_IS_EMT(pVCpu))
903	#elif defined(IN_RING0)
904	# define VMCPU_ASSERT_EMT(pVCpu) AssertMsg(VMCPU_IS_EMT(pVCpu), \
905	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd idCpu=%u\n", \
906	RTThreadNativeSelf(), (pVCpu) ? (pVCpu)->hNativeThreadR0 : 0, \
907	(pVCpu) ? (pVCpu)->idCpu : 0))
908	#else
909	# define VMCPU_ASSERT_EMT(pVCpu) AssertMsg(VMCPU_IS_EMT(pVCpu), \
910	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd idCpu=%#x\n", \
911	RTThreadNativeSelf(), (pVCpu)->hNativeThread, (pVCpu)->idCpu))
912	#endif
913
914	/** @def VM_ASSERT_EMT_RETURN
915	* Asserts that the current thread IS the emulation thread (EMT) and returns if it isn't.
916	*/
917	#ifdef IN_RC
918	# define VM_ASSERT_EMT_RETURN(pVM, rc) AssertReturn(VM_IS_EMT(pVM), (rc))
919	#elif defined(IN_RING0)
920	# define VM_ASSERT_EMT_RETURN(pVM, rc) AssertReturn(VM_IS_EMT(pVM), (rc))
921	#else
922	# define VM_ASSERT_EMT_RETURN(pVM, rc) \
923	AssertMsgReturn(VM_IS_EMT(pVM), \
924	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd\n", RTThreadNativeSelf(), VMR3GetVMCPUNativeThread(pVM)), \
925	(rc))
926	#endif
927
928	/** @def VMCPU_ASSERT_EMT_RETURN
929	* Asserts that the current thread IS the emulation thread (EMT) and returns if it isn't.
930	*/
931	#ifdef IN_RC
932	# define VMCPU_ASSERT_EMT_RETURN(pVCpu, rc) AssertReturn(VMCPU_IS_EMT(pVCpu), (rc))
933	#elif defined(IN_RING0)
934	# define VMCPU_ASSERT_EMT_RETURN(pVCpu, rc) AssertReturn(VMCPU_IS_EMT(pVCpu), (rc))
935	#else
936	# define VMCPU_ASSERT_EMT_RETURN(pVCpu, rc) \
937	AssertMsgReturn(VMCPU_IS_EMT(pVCpu), \
938	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd idCpu=%#x\n", \
939	RTThreadNativeSelf(), (pVCpu)->hNativeThread, (pVCpu)->idCpu), \
940	(rc))
941	#endif
942
943	/** @def VMCPU_ASSERT_EMT_OR_GURU
944	* Asserts that the current thread IS the emulation thread (EMT) of the
945	* specified virtual CPU.
946	*/
947	#if defined(IN_RC) \|\| defined(IN_RING0)
948	# define VMCPU_ASSERT_EMT_OR_GURU(pVCpu) Assert( VMCPU_IS_EMT(pVCpu) \
949	\|\| pVCpu->CTX_SUFF(pVM)->enmVMState == VMSTATE_GURU_MEDITATION \
950	\|\| pVCpu->CTX_SUFF(pVM)->enmVMState == VMSTATE_GURU_MEDITATION_LS )
951	#else
952	# define VMCPU_ASSERT_EMT_OR_GURU(pVCpu) \
953	AssertMsg( VMCPU_IS_EMT(pVCpu) \
954	\|\| pVCpu->CTX_SUFF(pVM)->enmVMState == VMSTATE_GURU_MEDITATION \
955	\|\| pVCpu->CTX_SUFF(pVM)->enmVMState == VMSTATE_GURU_MEDITATION_LS, \
956	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd idCpu=%#x\n", \
957	RTThreadNativeSelf(), (pVCpu)->hNativeThread, (pVCpu)->idCpu))
958	#endif
959
960	/** @def VMCPU_ASSERT_EMT_OR_NOT_RUNNING
961	* Asserts that the current thread IS the emulation thread (EMT) of the
962	* specified virtual CPU or the VM is not running.
963	*/
964	#if defined(IN_RC) \|\| defined(IN_RING0)
965	# define VMCPU_ASSERT_EMT_OR_NOT_RUNNING(pVCpu) \
966	Assert( VMCPU_IS_EMT(pVCpu) \
967	\|\| !VM_IS_RUNNING_FOR_ASSERTIONS_ONLY((pVCpu)->CTX_SUFF(pVM)) )
968	#else
969	# define VMCPU_ASSERT_EMT_OR_NOT_RUNNING(pVCpu) \
970	AssertMsg( VMCPU_IS_EMT(pVCpu) \
971	\|\| !VM_IS_RUNNING_FOR_ASSERTIONS_ONLY((pVCpu)->CTX_SUFF(pVM)), \
972	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd idCpu=%#x\n", \
973	RTThreadNativeSelf(), (pVCpu)->hNativeThread, (pVCpu)->idCpu))
974	#endif
975
976	/** @def VMSTATE_IS_RUNNING
977	* Checks if the given state indicates a running VM.
978	*/
979	#define VMSTATE_IS_RUNNING(a_enmVMState) \
980	( (enmVMState) == VMSTATE_RUNNING \
981	\|\| (enmVMState) == VMSTATE_RUNNING_LS )
982
983	/** @def VM_IS_RUNNING_FOR_ASSERTIONS_ONLY
984	* Checks if the VM is running.
985	* @note This is only for pure debug assertions. No AssertReturn or similar!
986	* @sa VMSTATE_IS_RUNNING
987	*/
988	#define VM_IS_RUNNING_FOR_ASSERTIONS_ONLY(pVM) \
989	( (pVM)->enmVMState == VMSTATE_RUNNING \
990	\|\| (pVM)->enmVMState == VMSTATE_RUNNING_LS )
991
992	/** @def VM_ASSERT_IS_NOT_RUNNING
993	* Asserts that the VM is not running.
994	*/
995	#if defined(IN_RC) \|\| defined(IN_RING0)
996	#define VM_ASSERT_IS_NOT_RUNNING(pVM) Assert(!VM_IS_RUNNING_FOR_ASSERTIONS_ONLY(pVM))
997	#else
998	#define VM_ASSERT_IS_NOT_RUNNING(pVM) AssertMsg(!VM_IS_RUNNING_FOR_ASSERTIONS_ONLY(pVM), \
999	("VM is running. enmVMState=%d\n", (pVM)->enmVMState))
1000	#endif
1001
1002	/** @def VM_ASSERT_EMT0
1003	* Asserts that the current thread IS emulation thread \#0 (EMT0).
1004	*/
1005	#ifdef IN_RING3
1006	# define VM_ASSERT_EMT0(a_pVM) VMCPU_ASSERT_EMT((a_pVM)->apCpusR3[0])
1007	#else
1008	# define VM_ASSERT_EMT0(a_pVM) VMCPU_ASSERT_EMT(&(a_pVM)->aCpus[0])
1009	#endif
1010
1011	/** @def VM_ASSERT_EMT0_RETURN
1012	* Asserts that the current thread IS emulation thread \#0 (EMT0) and returns if
1013	* it isn't.
1014	*/
1015	#ifdef IN_RING3
1016	# define VM_ASSERT_EMT0_RETURN(pVM, rc) VMCPU_ASSERT_EMT_RETURN((pVM)->apCpusR3[0], (rc))
1017	#else
1018	# define VM_ASSERT_EMT0_RETURN(pVM, rc) VMCPU_ASSERT_EMT_RETURN(&(pVM)->aCpus[0], (rc))
1019	#endif
1020
1021
1022	/**
1023	* Asserts that the current thread is NOT the emulation thread.
1024	*/
1025	#define VM_ASSERT_OTHER_THREAD(pVM) \
1026	AssertMsg(!VM_IS_EMT(pVM), ("Not other thread!!\n"))
1027
1028
1029	/** @def VM_ASSERT_STATE
1030	* Asserts a certain VM state.
1031	*/
1032	#define VM_ASSERT_STATE(pVM, _enmState) \
1033	AssertMsg((pVM)->enmVMState == (_enmState), \
1034	("state %s, expected %s\n", VMGetStateName((pVM)->enmVMState), VMGetStateName(_enmState)))
1035
1036	/** @def VM_ASSERT_STATE_RETURN
1037	* Asserts a certain VM state and returns if it doesn't match.
1038	*/
1039	#define VM_ASSERT_STATE_RETURN(pVM, _enmState, rc) \
1040	AssertMsgReturn((pVM)->enmVMState == (_enmState), \
1041	("state %s, expected %s\n", VMGetStateName((pVM)->enmVMState), VMGetStateName(_enmState)), \
1042	(rc))
1043
1044	/** @def VM_IS_VALID_EXT
1045	* Asserts a the VM handle is valid for external access, i.e. not being destroy
1046	* or terminated. */
1047	#define VM_IS_VALID_EXT(pVM) \
1048	( RT_VALID_ALIGNED_PTR(pVM, PAGE_SIZE) \
1049	&& ( (unsigned)(pVM)->enmVMState < (unsigned)VMSTATE_DESTROYING \
1050	\|\| ( (unsigned)(pVM)->enmVMState == (unsigned)VMSTATE_DESTROYING \
1051	&& VM_IS_EMT(pVM))) )
1052
1053	/** @def VM_ASSERT_VALID_EXT_RETURN
1054	* Asserts a the VM handle is valid for external access, i.e. not being
1055	* destroy or terminated.
1056	*/
1057	#define VM_ASSERT_VALID_EXT_RETURN(pVM, rc) \
1058	AssertMsgReturn(VM_IS_VALID_EXT(pVM), \
1059	("pVM=%p state %s\n", (pVM), RT_VALID_ALIGNED_PTR(pVM, PAGE_SIZE) \
1060	? VMGetStateName(pVM->enmVMState) : ""), \
1061	(rc))
1062
1063	/** @def VMCPU_ASSERT_VALID_EXT_RETURN
1064	* Asserts a the VMCPU handle is valid for external access, i.e. not being
1065	* destroy or terminated.
1066	*/
1067	#define VMCPU_ASSERT_VALID_EXT_RETURN(pVCpu, rc) \
1068	AssertMsgReturn( RT_VALID_ALIGNED_PTR(pVCpu, 64) \
1069	&& RT_VALID_ALIGNED_PTR((pVCpu)->CTX_SUFF(pVM), PAGE_SIZE) \
1070	&& (unsigned)(pVCpu)->CTX_SUFF(pVM)->enmVMState < (unsigned)VMSTATE_DESTROYING, \
1071	("pVCpu=%p pVM=%p state %s\n", (pVCpu), RT_VALID_ALIGNED_PTR(pVCpu, 64) ? (pVCpu)->CTX_SUFF(pVM) : NULL, \
1072	RT_VALID_ALIGNED_PTR(pVCpu, 64) && RT_VALID_ALIGNED_PTR((pVCpu)->CTX_SUFF(pVM), PAGE_SIZE) \
1073	? VMGetStateName((pVCpu)->pVMR3->enmVMState) : ""), \
1074	(rc))
1075
1076	#endif /* !VBOX_FOR_DTRACE_LIB */
1077
1078
1079	/**
1080	* Helper that HM and NEM uses for safely modifying VM::bMainExecutionEngine.
1081	*
1082	* ONLY HM and NEM MAY USE THIS!
1083	*
1084	* @param a_pVM The cross context VM structure.
1085	* @param a_bValue The new value.
1086	* @internal
1087	*/
1088	#define VM_SET_MAIN_EXECUTION_ENGINE(a_pVM, a_bValue) \
1089	do { \
1090	const_cast<uint8_t >(&(a_pVM)->bMainExecutionEngine) = (a_bValue); \
1091	ASMCompilerBarrier(); /* just to be on the safe side */ \
1092	} while (0)
1093
1094	/**
1095	* Checks whether iem-executes-all-mode is used.
1096	*
1097	* @retval true if IEM is used.
1098	* @retval false if not.
1099	*
1100	* @param a_pVM The cross context VM structure.
1101	* @sa VM_IS_HM_OR_NEM_ENABLED, VM_IS_HM_ENABLED, VM_IS_NEM_ENABLED.
1102	* @internal
1103	*/
1104	#define VM_IS_EXEC_ENGINE_IEM(a_pVM) ((a_pVM)->bMainExecutionEngine == VM_EXEC_ENGINE_IEM)
1105
1106	/**
1107	* Checks whether HM (VT-x/AMD-V) or NEM is being used by this VM.
1108	*
1109	* @retval true if either is used.
1110	* @retval false if software virtualization (raw-mode) is used.
1111	*
1112	* @param a_pVM The cross context VM structure.
1113	* @sa VM_IS_EXEC_ENGINE_IEM, VM_IS_HM_ENABLED, VM_IS_NEM_ENABLED.
1114	* @internal
1115	*/
1116	#define VM_IS_HM_OR_NEM_ENABLED(a_pVM) ((a_pVM)->bMainExecutionEngine != VM_EXEC_ENGINE_IEM)
1117
1118	/**
1119	* Checks whether HM is being used by this VM.
1120	*
1121	* @retval true if HM (VT-x/AMD-v) is used.
1122	* @retval false if not.
1123	*
1124	* @param a_pVM The cross context VM structure.
1125	* @sa VM_IS_NEM_ENABLED, VM_IS_EXEC_ENGINE_IEM, VM_IS_HM_OR_NEM_ENABLED.
1126	* @internal
1127	*/
1128	#define VM_IS_HM_ENABLED(a_pVM) ((a_pVM)->bMainExecutionEngine == VM_EXEC_ENGINE_HW_VIRT)
1129
1130	/**
1131	* Checks whether NEM is being used by this VM.
1132	*
1133	* @retval true if a native hypervisor API is used.
1134	* @retval false if not.
1135	*
1136	* @param a_pVM The cross context VM structure.
1137	* @sa VM_IS_HM_ENABLED, VM_IS_EXEC_ENGINE_IEM, VM_IS_HM_OR_NEM_ENABLED.
1138	* @internal
1139	*/
1140	#define VM_IS_NEM_ENABLED(a_pVM) ((a_pVM)->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API)
1141
1142
1143	/**
1144	* The cross context VM structure.
1145	*
1146	* It contains all the VM data which have to be available in all contexts.
1147	* Even if it contains all the data the idea is to use APIs not to modify all
1148	* the members all around the place. Therefore we make use of unions to hide
1149	* everything which isn't local to the current source module. This means we'll
1150	* have to pay a little bit of attention when adding new members to structures
1151	* in the unions and make sure to keep the padding sizes up to date.
1152	*
1153	* Run 'kmk run-struct-tests' (from src/VBox/VMM if you like) after updating!
1154	*/
1155	typedef struct VM
1156	{
1157	/** The state of the VM.
1158	* This field is read only to everyone except the VM and EM. */
1159	VMSTATE volatile enmVMState;
1160	/** Forced action flags.
1161	* See the VM_FF_* \#defines. Updated atomically.
1162	*/
1163	volatile uint32_t fGlobalForcedActions;
1164	/** Pointer to the array of page descriptors for the VM structure allocation. */
1165	R3PTRTYPE(PSUPPAGE) paVMPagesR3;
1166	/** Session handle. For use when calling SUPR0 APIs. */
1167	#ifdef IN_RING0
1168	PSUPDRVSESSION pSessionUnsafe;
1169	#else
1170	PSUPDRVSESSION pSession;
1171	#endif
1172	/** Pointer to the ring-3 VM structure. */
1173	PUVM pUVM;
1174	/** Ring-3 Host Context VM Pointer. */
1175	#ifdef IN_RING0
1176	R3PTRTYPE(struct VM *) pVMR3Unsafe;
1177	#else
1178	R3PTRTYPE(struct VM *) pVMR3;
1179	#endif
1180	/** Ring-0 Host Context VM pointer for making ring-0 calls. */
1181	R0PTRTYPE(struct VM *) pVMR0ForCall;
1182	/** Raw-mode Context VM Pointer. */
1183	uint32_t pVMRC;
1184	/** Padding for new raw-mode (long mode). */
1185	uint32_t pVMRCPadding;
1186
1187	/** The GVM VM handle. Only the GVM should modify this field. */
1188	#ifdef IN_RING0
1189	uint32_t hSelfUnsafe;
1190	#else
1191	uint32_t hSelf;
1192	#endif
1193	/** Number of virtual CPUs. */
1194	#ifdef IN_RING0
1195	uint32_t cCpusUnsafe;
1196	#else
1197	uint32_t cCpus;
1198	#endif
1199	/** CPU excution cap (1-100) */
1200	uint32_t uCpuExecutionCap;
1201
1202	/** Size of the VM structure. */
1203	uint32_t cbSelf;
1204	/** Size of the VMCPU structure. */
1205	uint32_t cbVCpu;
1206	/** Structure version number (TBD). */
1207	uint32_t uStructVersion;
1208
1209	/** @name Various items that are frequently accessed.
1210	* @{ */
1211	/** The main execution engine, VM_EXEC_ENGINE_XXX.
1212	* This is set early during vmR3InitRing3 by HM or NEM. */
1213	uint8_t const bMainExecutionEngine;
1214
1215	/** Hardware VM support is available and enabled.
1216	* Determined very early during init.
1217	* This is placed here for performance reasons.
1218	* @todo obsoleted by bMainExecutionEngine, eliminate. */
1219	bool fHMEnabled;
1220	/** @} */
1221
1222	/** Alignment padding. */
1223	uint8_t uPadding1[6];
1224
1225	/** @name Debugging
1226	* @{ */
1227	/** Ring-3 Host Context VM Pointer. */
1228	R3PTRTYPE(RTTRACEBUF) hTraceBufR3;
1229	/** Ring-0 Host Context VM Pointer. */
1230	R0PTRTYPE(RTTRACEBUF) hTraceBufR0;
1231	/** @} */
1232
1233	/** Max EMT hash lookup collisions (in GVMM). */
1234	uint8_t cMaxEmtHashCollisions;
1235
1236	/** Padding - the unions must be aligned on a 64 bytes boundary. */
1237	uint8_t abAlignment3[HC_ARCH_BITS == 64 ? 23 : 51];
1238
1239	/** CPUM part. */
1240	union
1241	{
1242	#ifdef VMM_INCLUDED_SRC_include_CPUMInternal_h
1243	struct CPUM s;
1244	#endif
1245	#ifdef VBOX_INCLUDED_vmm_cpum_h
1246	/** Read only info exposed about the host and guest CPUs. */
1247	struct
1248	{
1249	/** Padding for hidden fields. */
1250	uint8_t abHidden0[64 + 48];
1251	/** Guest CPU feature information. */
1252	CPUMFEATURES GuestFeatures;
1253	} const ro;
1254	#endif
1255	/** @todo this is rather bloated because of static MSR range allocation.
1256	* Probably a good idea to move it to a separate R0 allocation... */
1257	uint8_t padding[8832 + 1288192 + 0x1d00]; / multiple of 64 */
1258	} cpum;
1259
1260	/** PGM part.
1261	* @note 16384 aligned for zero and mmio page storage. */
1262	union
1263	{
1264	#ifdef VMM_INCLUDED_SRC_include_PGMInternal_h
1265	struct PGM s;
1266	#endif
1267	uint8_t padding[53888]; /* multiple of 64 */
1268	} pgm;
1269
1270	/** VMM part. */
1271	union
1272	{
1273	#ifdef VMM_INCLUDED_SRC_include_VMMInternal_h
1274	struct VMM s;
1275	#endif
1276	uint8_t padding[1600]; /* multiple of 64 */
1277	} vmm;
1278
1279	/** HM part. */
1280	union
1281	{
1282	#ifdef VMM_INCLUDED_SRC_include_HMInternal_h
1283	struct HM s;
1284	#endif
1285	uint8_t padding[5504]; /* multiple of 64 */
1286	} hm;
1287
1288	/** TRPM part. */
1289	union
1290	{
1291	#ifdef VMM_INCLUDED_SRC_include_TRPMInternal_h
1292	struct TRPM s;
1293	#endif
1294	uint8_t padding[2048]; /* multiple of 64 */
1295	} trpm;
1296
1297	/** SELM part. */
1298	union
1299	{
1300	#ifdef VMM_INCLUDED_SRC_include_SELMInternal_h
1301	struct SELM s;
1302	#endif
1303	uint8_t padding[768]; /* multiple of 64 */
1304	} selm;
1305
1306	/** MM part. */
1307	union
1308	{
1309	#ifdef VMM_INCLUDED_SRC_include_MMInternal_h
1310	struct MM s;
1311	#endif
1312	uint8_t padding[192]; /* multiple of 64 */
1313	} mm;
1314
1315	/** PDM part. */
1316	union
1317	{
1318	#ifdef VMM_INCLUDED_SRC_include_PDMInternal_h
1319	struct PDM s;
1320	#endif
1321	uint8_t padding[22400]; /* multiple of 64 */
1322	} pdm;
1323
1324	/** IOM part. */
1325	union
1326	{
1327	#ifdef VMM_INCLUDED_SRC_include_IOMInternal_h
1328	struct IOM s;
1329	#endif
1330	uint8_t padding[1152]; /* multiple of 64 */
1331	} iom;
1332
1333	/** EM part. */
1334	union
1335	{
1336	#ifdef VMM_INCLUDED_SRC_include_EMInternal_h
1337	struct EM s;
1338	#endif
1339	uint8_t padding[256]; /* multiple of 64 */
1340	} em;
1341
1342	/** NEM part. */
1343	union
1344	{
1345	#ifdef VMM_INCLUDED_SRC_include_NEMInternal_h
1346	struct NEM s;
1347	#endif
1348	uint8_t padding[4608]; /* multiple of 64 */
1349	} nem;
1350
1351	/** TM part. */
1352	union
1353	{
1354	#ifdef VMM_INCLUDED_SRC_include_TMInternal_h
1355	struct TM s;
1356	#endif
1357	uint8_t padding[10112]; /* multiple of 64 */
1358	} tm;
1359
1360	/** DBGF part. */
1361	union
1362	{
1363	#ifdef VMM_INCLUDED_SRC_include_DBGFInternal_h
1364	struct DBGF s;
1365	#endif
1366	#ifdef VBOX_INCLUDED_vmm_dbgf_h
1367	/** Read only info exposed about interrupt breakpoints and selected events. */
1368	struct
1369	{
1370	/** Bitmap of enabled hardware interrupt breakpoints. */
1371	uint32_t bmHardIntBreakpoints[256 / 32];
1372	/** Bitmap of enabled software interrupt breakpoints. */
1373	uint32_t bmSoftIntBreakpoints[256 / 32];
1374	/** Bitmap of selected events.
1375	* This includes non-selectable events too for simplicity, we maintain the
1376	* state for some of these, as it may come in handy. */
1377	uint64_t bmSelectedEvents[(DBGFEVENT_END + 63) / 64];
1378	/** Enabled hardware interrupt breakpoints. */
1379	uint32_t cHardIntBreakpoints;
1380	/** Enabled software interrupt breakpoints. */
1381	uint32_t cSoftIntBreakpoints;
1382	/** The number of selected events. */
1383	uint32_t cSelectedEvents;
1384	/** The number of enabled hardware breakpoints. */
1385	uint8_t cEnabledHwBreakpoints;
1386	/** The number of enabled hardware I/O breakpoints. */
1387	uint8_t cEnabledHwIoBreakpoints;
1388	uint8_t au8Alignment1[2]; /*< Alignment padding. /
1389	/** The number of enabled INT3 breakpoints. */
1390	uint32_t volatile cEnabledInt3Breakpoints;
1391	} const ro;
1392	#endif
1393	uint8_t padding[2432]; /* multiple of 64 */
1394	} dbgf;
1395
1396	/** SSM part. */
1397	union
1398	{
1399	#ifdef VMM_INCLUDED_SRC_include_SSMInternal_h
1400	struct SSM s;
1401	#endif
1402	uint8_t padding[128]; /* multiple of 64 */
1403	} ssm;
1404
1405	union
1406	{
1407	#ifdef VMM_INCLUDED_SRC_include_GIMInternal_h
1408	struct GIM s;
1409	#endif
1410	uint8_t padding[448]; /* multiple of 64 */
1411	} gim;
1412
1413	union
1414	{
1415	#ifdef VMM_INCLUDED_SRC_include_APICInternal_h
1416	struct APIC s;
1417	#endif
1418	uint8_t padding[128]; /* multiple of 8 */
1419	} apic;
1420
1421	/* ---- begin small stuff ---- */
1422
1423	/** VM part. */
1424	union
1425	{
1426	#ifdef VMM_INCLUDED_SRC_include_VMInternal_h
1427	struct VMINT s;
1428	#endif
1429	uint8_t padding[32]; /* multiple of 8 */
1430	} vm;
1431
1432	/** CFGM part. */
1433	union
1434	{
1435	#ifdef VMM_INCLUDED_SRC_include_CFGMInternal_h
1436	struct CFGM s;
1437	#endif
1438	uint8_t padding[8]; /* multiple of 8 */
1439	} cfgm;
1440
1441	/** IEM part. */
1442	union
1443	{
1444	#ifdef VMM_INCLUDED_SRC_include_IEMInternal_h
1445	struct IEM s;
1446	#endif
1447	uint8_t padding[16]; /* multiple of 8 */
1448	} iem;
1449
1450	/** Statistics for ring-0 only components. */
1451	struct
1452	{
1453	/** GMMR0 stats. */
1454	struct
1455	{
1456	/** Chunk TLB hits. */
1457	uint64_t cChunkTlbHits;
1458	/** Chunk TLB misses. */
1459	uint64_t cChunkTlbMisses;
1460	} gmm;
1461	uint64_t au64Padding[6]; /* probably more comming here... */
1462	} R0Stats;
1463
1464	union
1465	{
1466	#ifdef VMM_INCLUDED_SRC_include_GCMInternal_h
1467	struct GCM s;
1468	#endif
1469	uint8_t padding[32]; /* multiple of 8 */
1470	} gcm;
1471
1472	/** Padding for aligning the structure size on a page boundrary. */
1473	uint8_t abAlignment2[8872 - sizeof(PVMCPUR3) * VMM_MAX_CPU_COUNT];
1474
1475	/* ---- end small stuff ---- */
1476
1477	/** Array of VMCPU ring-3 pointers. */
1478	PVMCPUR3 apCpusR3[VMM_MAX_CPU_COUNT];
1479
1480	/* This point is aligned on a 16384 boundrary (for arm64 purposes). */
1481	} VM;
1482	#ifndef VBOX_FOR_DTRACE_LIB
1483	//AssertCompileSizeAlignment(VM, 16384);
1484	#endif
1485
1486
1487	#ifdef IN_RC
1488	RT_C_DECLS_BEGIN
1489
1490	/** The VM structure.
1491	* This is imported from the VMMRCBuiltin module, i.e. it's a one of those magic
1492	* globals which we should avoid using.
1493	*/
1494	extern DECLIMPORT(VM) g_VM;
1495
1496	/** The VMCPU structure for virtual CPU \#0.
1497	* This is imported from the VMMRCBuiltin module, i.e. it's a one of those magic
1498	* globals which we should avoid using.
1499	*/
1500	extern DECLIMPORT(VMCPU) g_VCpu0;
1501
1502	RT_C_DECLS_END
1503	#endif
1504
1505	/** @} */
1506
1507	#endif /* !VBOX_INCLUDED_vmm_vm_h */
1508

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