vm.h@ 98122

Last change on this file since 98122 was 98122, checked in by vboxsync, 23 months ago
VMM/PDM: Fixed assertion in PDMR3ResumeUsb after attaching a virtual MSD.
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1	/** @file
2	* VM - The Virtual Machine, data.
3	*/
4
5	/*
6	* Copyright (C) 2006-2023 Oracle and/or its affiliates.
7	*
8	* This file is part of VirtualBox base platform packages, as
9	* available from https://www.virtualbox.org.
10	*
11	* This program is free software; you can redistribute it and/or
12	* modify it under the terms of the GNU General Public License
13	* as published by the Free Software Foundation, in version 3 of the
14	* License.
15	*
16	* This program is distributed in the hope that it will be useful, but
17	* WITHOUT ANY WARRANTY; without even the implied warranty of
18	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19	* General Public License for more details.
20	*
21	* You should have received a copy of the GNU General Public License
22	* along with this program; if not, see <https://www.gnu.org/licenses>.
23	*
24	* The contents of this file may alternatively be used under the terms
25	* of the Common Development and Distribution License Version 1.0
26	* (CDDL), a copy of it is provided in the "COPYING.CDDL" file included
27	* in the VirtualBox distribution, in which case the provisions of the
28	* CDDL are applicable instead of those of the GPL.
29	*
30	* You may elect to license modified versions of this file under the
31	* terms and conditions of either the GPL or the CDDL or both.
32	*
33	* SPDX-License-Identifier: GPL-3.0-only OR CDDL-1.0
34	*/
35
36	#ifndef VBOX_INCLUDED_vmm_vm_h
37	#define VBOX_INCLUDED_vmm_vm_h
38	#ifndef RT_WITHOUT_PRAGMA_ONCE
39	# pragma once
40	#endif
41
42	#ifndef VBOX_FOR_DTRACE_LIB
43	# ifndef USING_VMM_COMMON_DEFS
44	# error "Compile job does not include VMM_COMMON_DEFS from src/VBox/VMM/Config.kmk - make sure you really need to include this file!"
45	# endif
46	# include <iprt/param.h>
47	# include <VBox/param.h>
48	# include <VBox/types.h>
49	# include <VBox/vmm/cpum.h>
50	# include <VBox/vmm/stam.h>
51	# include <VBox/vmm/vmapi.h>
52	# include <VBox/vmm/vmm.h>
53	# include <VBox/sup.h>
54	#else
55	# pragma D depends_on library vbox-types.d
56	# pragma D depends_on library CPUMInternal.d
57	# define VMM_INCLUDED_SRC_include_CPUMInternal_h
58	#endif
59
60
61
62	/** @defgroup grp_vm The Virtual Machine
63	* @ingroup grp_vmm
64	* @{
65	*/
66
67	/**
68	* The state of a Virtual CPU.
69	*
70	* The basic state indicated here is whether the CPU has been started or not. In
71	* addition, there are sub-states when started for assisting scheduling (GVMM
72	* mostly).
73	*
74	* The transition out of the STOPPED state is done by a vmR3PowerOn.
75	* The transition back to the STOPPED state is done by vmR3PowerOff.
76	*
77	* (Alternatively we could let vmR3PowerOn start CPU 0 only and let the SPIP
78	* handling switch on the other CPUs. Then vmR3Reset would stop all but CPU 0.)
79	*/
80	typedef enum VMCPUSTATE
81	{
82	/** The customary invalid zero. */
83	VMCPUSTATE_INVALID = 0,
84
85	/** Virtual CPU has not yet been started. */
86	VMCPUSTATE_STOPPED,
87
88	/** CPU started. */
89	VMCPUSTATE_STARTED,
90	/** CPU started in HM context. */
91	VMCPUSTATE_STARTED_HM,
92	/** Executing guest code and can be poked (RC or STI bits of HM). */
93	VMCPUSTATE_STARTED_EXEC,
94	/** Executing guest code using NEM. */
95	VMCPUSTATE_STARTED_EXEC_NEM,
96	VMCPUSTATE_STARTED_EXEC_NEM_WAIT,
97	VMCPUSTATE_STARTED_EXEC_NEM_CANCELED,
98	/** Halted. */
99	VMCPUSTATE_STARTED_HALTED,
100
101	/** The end of valid virtual CPU states. */
102	VMCPUSTATE_END,
103
104	/** Ensure 32-bit type. */
105	VMCPUSTATE_32BIT_HACK = 0x7fffffff
106	} VMCPUSTATE;
107
108	/** Enables 64-bit FFs. */
109	#define VMCPU_WITH_64_BIT_FFS
110
111
112	/**
113	* The cross context virtual CPU structure.
114	*
115	* Run 'kmk run-struct-tests' (from src/VBox/VMM if you like) after updating!
116	*/
117	typedef struct VMCPU
118	{
119	/** @name Volatile per-cpu data.
120	* @{ */
121	/** Per CPU forced action.
122	* See the VMCPU_FF_* \#defines. Updated atomically. */
123	#ifdef VMCPU_WITH_64_BIT_FFS
124	uint64_t volatile fLocalForcedActions;
125	#else
126	uint32_t volatile fLocalForcedActions;
127	uint32_t fForLocalForcedActionsExpansion;
128	#endif
129	/** The CPU state. */
130	VMCPUSTATE volatile enmState;
131
132	/** Padding up to 64 bytes. */
133	uint8_t abAlignment0[64 - 12];
134	/** @} */
135
136	/** IEM part.
137	* @remarks This comes first as it allows the use of 8-bit immediates for the
138	* first 64 bytes of the structure, reducing code size a wee bit. */
139	#ifdef VMM_INCLUDED_SRC_include_IEMInternal_h /* For PDB hacking. */
140	union VMCPUUNIONIEMFULL
141	#else
142	union VMCPUUNIONIEMSTUB
143	#endif
144	{
145	#ifdef VMM_INCLUDED_SRC_include_IEMInternal_h
146	struct IEMCPU s;
147	#endif
148	uint8_t padding[32832]; /* multiple of 64 */
149	} iem;
150
151	/** @name Static per-cpu data.
152	* (Putting this after IEM, hoping that it's less frequently used than it.)
153	* @{ */
154	/** Ring-3 Host Context VM Pointer. */
155	PVMR3 pVMR3;
156	/** Ring-0 Host Context VM Pointer, currently used by VTG/dtrace. */
157	RTR0PTR pVCpuR0ForVtg;
158	/** Raw-mode Context VM Pointer. */
159	uint32_t pVMRC;
160	/** Padding for new raw-mode (long mode). */
161	uint32_t pVMRCPadding;
162	/** Pointer to the ring-3 UVMCPU structure. */
163	PUVMCPU pUVCpu;
164	/** The native thread handle. */
165	RTNATIVETHREAD hNativeThread;
166	/** The native R0 thread handle. (different from the R3 handle!) */
167	RTNATIVETHREAD hNativeThreadR0;
168	/** The IPRT thread handle (for VMMDevTesting). */
169	RTTHREAD hThread;
170	/** The CPU ID.
171	* This is the index into the VM::aCpu array. */
172	#ifdef IN_RING0
173	VMCPUID idCpuUnsafe;
174	#else
175	VMCPUID idCpu;
176	#endif
177
178	/** Align the structures below bit on a 64-byte boundary and make sure it starts
179	* at the same offset in both 64-bit and 32-bit builds.
180	*
181	* @remarks The alignments of the members that are larger than 48 bytes should be
182	* 64-byte for cache line reasons. structs containing small amounts of
183	* data could be lumped together at the end with a < 64 byte padding
184	* following it (to grow into and align the struct size).
185	*/
186	uint8_t abAlignment1[64 - 6 * (HC_ARCH_BITS == 32 ? 4 : 8) - 8 - 4];
187	/** @} */
188
189	/** HM part. */
190	union VMCPUUNIONHM
191	{
192	#ifdef VMM_INCLUDED_SRC_include_HMInternal_h
193	struct HMCPU s;
194	#endif
195	uint8_t padding[9984]; /* multiple of 64 */
196	} hm;
197
198	/** NEM part. */
199	union VMCPUUNIONNEM
200	{
201	#ifdef VMM_INCLUDED_SRC_include_NEMInternal_h
202	struct NEMCPU s;
203	#endif
204	uint8_t padding[4608]; /* multiple of 64 */
205	} nem;
206
207	/** TRPM part. */
208	union VMCPUUNIONTRPM
209	{
210	#ifdef VMM_INCLUDED_SRC_include_TRPMInternal_h
211	struct TRPMCPU s;
212	#endif
213	uint8_t padding[128]; /* multiple of 64 */
214	} trpm;
215
216	/** TM part. */
217	union VMCPUUNIONTM
218	{
219	#ifdef VMM_INCLUDED_SRC_include_TMInternal_h
220	struct TMCPU s;
221	#endif
222	uint8_t padding[5760]; /* multiple of 64 */
223	} tm;
224
225	/** VMM part. */
226	union VMCPUUNIONVMM
227	{
228	#ifdef VMM_INCLUDED_SRC_include_VMMInternal_h
229	struct VMMCPU s;
230	#endif
231	uint8_t padding[9536]; /* multiple of 64 */
232	} vmm;
233
234	/** PDM part. */
235	union VMCPUUNIONPDM
236	{
237	#ifdef VMM_INCLUDED_SRC_include_PDMInternal_h
238	struct PDMCPU s;
239	#endif
240	uint8_t padding[256]; /* multiple of 64 */
241	} pdm;
242
243	/** IOM part. */
244	union VMCPUUNIONIOM
245	{
246	#ifdef VMM_INCLUDED_SRC_include_IOMInternal_h
247	struct IOMCPU s;
248	#endif
249	uint8_t padding[512]; /* multiple of 64 */
250	} iom;
251
252	/** DBGF part.
253	* @todo Combine this with other tiny structures. */
254	union VMCPUUNIONDBGF
255	{
256	#ifdef VMM_INCLUDED_SRC_include_DBGFInternal_h
257	struct DBGFCPU s;
258	#endif
259	uint8_t padding[512]; /* multiple of 64 */
260	} dbgf;
261
262	/** GIM part. */
263	union VMCPUUNIONGIM
264	{
265	#ifdef VMM_INCLUDED_SRC_include_GIMInternal_h
266	struct GIMCPU s;
267	#endif
268	uint8_t padding[512]; /* multiple of 64 */
269	} gim;
270
271	/** APIC part. */
272	union VMCPUUNIONAPIC
273	{
274	#ifdef VMM_INCLUDED_SRC_include_APICInternal_h
275	struct APICCPU s;
276	#endif
277	uint8_t padding[3840]; /* multiple of 64 */
278	} apic;
279
280	/*
281	* Some less frequently used global members that doesn't need to take up
282	* precious space at the head of the structure.
283	*/
284
285	/** Trace groups enable flags. */
286	uint32_t fTraceGroups; /* 64 / 44 */
287	/** Number of collisions hashing the ring-0 EMT handle. */
288	uint8_t cEmtHashCollisions;
289	uint8_t abAdHoc[3];
290	/** Profiling samples for use by ad hoc profiling. */
291	STAMPROFILEADV aStatAdHoc[8]; /* size: 408 = 320 /
292
293	/** Align the following members on page boundary. */
294	uint8_t abAlignment2[696];
295
296	/** PGM part. */
297	union VMCPUUNIONPGM
298	{
299	#ifdef VMM_INCLUDED_SRC_include_PGMInternal_h
300	struct PGMCPU s;
301	#endif
302	uint8_t padding[4096 + 28672]; /* multiple of 4096 */
303	} pgm;
304
305	/** CPUM part. */
306	union VMCPUUNIONCPUM
307	{
308	#ifdef VMM_INCLUDED_SRC_include_CPUMInternal_h
309	struct CPUMCPU s;
310	#endif
311	#ifdef VMCPU_INCL_CPUM_GST_CTX
312	/** The guest CPUM context for direct use by execution engines.
313	* This is not for general consumption, but for HM, REM, IEM, and maybe a few
314	* others. The rest will use the function based CPUM API. */
315	CPUMCTX GstCtx;
316	#endif
317	uint8_t padding[102400]; /* multiple of 4096 */
318	} cpum;
319
320	/** EM part. */
321	union VMCPUUNIONEM
322	{
323	#ifdef VMM_INCLUDED_SRC_include_EMInternal_h
324	struct EMCPU s;
325	#endif
326	uint8_t padding[40960]; /* multiple of 4096 */
327	} em;
328
329	} VMCPU;
330
331
332	#ifndef VBOX_FOR_DTRACE_LIB
333	/* Make sure the structure size is aligned on a 16384 boundary for arm64 purposes. */
334	AssertCompileSizeAlignment(VMCPU, 16384);
335
336	/** @name Operations on VMCPU::enmState
337	* @{ */
338	/** Gets the VMCPU state. */
339	#define VMCPU_GET_STATE(pVCpu) ( (pVCpu)->enmState )
340	/** Sets the VMCPU state. */
341	#define VMCPU_SET_STATE(pVCpu, enmNewState) \
342	ASMAtomicWriteU32((uint32_t volatile *)&(pVCpu)->enmState, (enmNewState))
343	/** Cmpares and sets the VMCPU state. */
344	#define VMCPU_CMPXCHG_STATE(pVCpu, enmNewState, enmOldState) \
345	ASMAtomicCmpXchgU32((uint32_t volatile *)&(pVCpu)->enmState, (enmNewState), (enmOldState))
346	/** Checks the VMCPU state. */
347	#ifdef VBOX_STRICT
348	# define VMCPU_ASSERT_STATE(pVCpu, enmExpectedState) \
349	do { \
350	VMCPUSTATE enmState = VMCPU_GET_STATE(pVCpu); \
351	AssertMsg(enmState == (enmExpectedState), \
352	("enmState=%d enmExpectedState=%d idCpu=%u\n", \
353	enmState, enmExpectedState, (pVCpu)->idCpu)); \
354	} while (0)
355
356	# define VMCPU_ASSERT_STATE_2(pVCpu, enmExpectedState, a_enmExpectedState2) \
357	do { \
358	VMCPUSTATE enmState = VMCPU_GET_STATE(pVCpu); \
359	AssertMsg( enmState == (enmExpectedState) \
360	\|\| enmState == (a_enmExpectedState2), \
361	("enmState=%d enmExpectedState=%d enmExpectedState2=%d idCpu=%u\n", \
362	enmState, enmExpectedState, a_enmExpectedState2, (pVCpu)->idCpu)); \
363	} while (0)
364	#else
365	# define VMCPU_ASSERT_STATE(pVCpu, enmExpectedState) do { } while (0)
366	# define VMCPU_ASSERT_STATE_2(pVCpu, enmExpectedState, a_enmExpectedState2) do { } while (0)
367	#endif
368	/** Tests if the state means that the CPU is started. */
369	#define VMCPUSTATE_IS_STARTED(enmState) ( (enmState) > VMCPUSTATE_STOPPED )
370	/** Tests if the state means that the CPU is stopped. */
371	#define VMCPUSTATE_IS_STOPPED(enmState) ( (enmState) == VMCPUSTATE_STOPPED )
372	/** @} */
373
374
375	/** The name of the raw-mode context VMM Core module. */
376	#define VMMRC_MAIN_MODULE_NAME "VMMRC.rc"
377	/** The name of the ring-0 context VMM Core module. */
378	#define VMMR0_MAIN_MODULE_NAME "VMMR0.r0"
379
380
381	/** VM Forced Action Flags.
382	*
383	* Use the VM_FF_SET() and VM_FF_CLEAR() macros to change the force
384	* action mask of a VM.
385	*
386	* Available VM bits:
387	* 0, 1, 5, 6, 7, 13, 14, 15, 16, 17, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30
388	*
389	*
390	* Available VMCPU bits:
391	* 14, 15, 36 to 63
392	*
393	* @todo If we run low on VMCPU, we may consider merging the SELM bits
394	*
395	* @{
396	*/
397	/** The virtual sync clock has been stopped, go to TM until it has been
398	* restarted... */
399	#define VM_FF_TM_VIRTUAL_SYNC RT_BIT_32(VM_FF_TM_VIRTUAL_SYNC_BIT)
400	#define VM_FF_TM_VIRTUAL_SYNC_BIT 2
401	/** PDM Queues are pending. */
402	#define VM_FF_PDM_QUEUES RT_BIT_32(VM_FF_PDM_QUEUES_BIT)
403	/** The bit number for VM_FF_PDM_QUEUES. */
404	#define VM_FF_PDM_QUEUES_BIT 3
405	/** PDM DMA transfers are pending. */
406	#define VM_FF_PDM_DMA RT_BIT_32(VM_FF_PDM_DMA_BIT)
407	/** The bit number for VM_FF_PDM_DMA. */
408	#define VM_FF_PDM_DMA_BIT 4
409	/** This action forces the VM to call DBGF so DBGF can service debugger
410	* requests in the emulation thread.
411	* This action flag stays asserted till DBGF clears it.*/
412	#define VM_FF_DBGF RT_BIT_32(VM_FF_DBGF_BIT)
413	/** The bit number for VM_FF_DBGF. */
414	#define VM_FF_DBGF_BIT 8
415	/** This action forces the VM to service pending requests from other
416	* thread or requests which must be executed in another context. */
417	#define VM_FF_REQUEST RT_BIT_32(VM_FF_REQUEST_BIT)
418	#define VM_FF_REQUEST_BIT 9
419	/** Check for VM state changes and take appropriate action. */
420	#define VM_FF_CHECK_VM_STATE RT_BIT_32(VM_FF_CHECK_VM_STATE_BIT)
421	/** The bit number for VM_FF_CHECK_VM_STATE. */
422	#define VM_FF_CHECK_VM_STATE_BIT 10
423	/** Reset the VM. (postponed) */
424	#define VM_FF_RESET RT_BIT_32(VM_FF_RESET_BIT)
425	/** The bit number for VM_FF_RESET. */
426	#define VM_FF_RESET_BIT 11
427	/** EMT rendezvous in VMM. */
428	#define VM_FF_EMT_RENDEZVOUS RT_BIT_32(VM_FF_EMT_RENDEZVOUS_BIT)
429	/** The bit number for VM_FF_EMT_RENDEZVOUS. */
430	#define VM_FF_EMT_RENDEZVOUS_BIT 12
431
432	/** PGM needs to allocate handy pages. */
433	#define VM_FF_PGM_NEED_HANDY_PAGES RT_BIT_32(VM_FF_PGM_NEED_HANDY_PAGES_BIT)
434	#define VM_FF_PGM_NEED_HANDY_PAGES_BIT 18
435	/** PGM is out of memory.
436	* Abandon all loops and code paths which can be resumed and get up to the EM
437	* loops. */
438	#define VM_FF_PGM_NO_MEMORY RT_BIT_32(VM_FF_PGM_NO_MEMORY_BIT)
439	#define VM_FF_PGM_NO_MEMORY_BIT 19
440	/** PGM is about to perform a lightweight pool flush
441	* Guest SMP: all EMT threads should return to ring 3
442	*/
443	#define VM_FF_PGM_POOL_FLUSH_PENDING RT_BIT_32(VM_FF_PGM_POOL_FLUSH_PENDING_BIT)
444	#define VM_FF_PGM_POOL_FLUSH_PENDING_BIT 20
445	/** Suspend the VM - debug only. */
446	#define VM_FF_DEBUG_SUSPEND RT_BIT_32(VM_FF_DEBUG_SUSPEND_BIT)
447	#define VM_FF_DEBUG_SUSPEND_BIT 31
448
449
450	/** This action forces the VM to check any pending interrupts on the APIC. */
451	#define VMCPU_FF_INTERRUPT_APIC RT_BIT_64(VMCPU_FF_INTERRUPT_APIC_BIT)
452	#define VMCPU_FF_INTERRUPT_APIC_BIT 0
453	/** This action forces the VM to check any pending interrups on the PIC. */
454	#define VMCPU_FF_INTERRUPT_PIC RT_BIT_64(VMCPU_FF_INTERRUPT_PIC_BIT)
455	#define VMCPU_FF_INTERRUPT_PIC_BIT 1
456	/** This action forces the VM to schedule and run pending timer (TM).
457	* @remarks Don't move - PATM compatibility. */
458	#define VMCPU_FF_TIMER RT_BIT_64(VMCPU_FF_TIMER_BIT)
459	#define VMCPU_FF_TIMER_BIT 2
460	/** This action forces the VM to check any pending NMIs. */
461	#define VMCPU_FF_INTERRUPT_NMI RT_BIT_64(VMCPU_FF_INTERRUPT_NMI_BIT)
462	#define VMCPU_FF_INTERRUPT_NMI_BIT 3
463	/** This action forces the VM to check any pending SMIs. */
464	#define VMCPU_FF_INTERRUPT_SMI RT_BIT_64(VMCPU_FF_INTERRUPT_SMI_BIT)
465	#define VMCPU_FF_INTERRUPT_SMI_BIT 4
466	/** PDM critical section unlocking is pending, process promptly upon return to R3. */
467	#define VMCPU_FF_PDM_CRITSECT RT_BIT_64(VMCPU_FF_PDM_CRITSECT_BIT)
468	#define VMCPU_FF_PDM_CRITSECT_BIT 5
469	/** Special EM internal force flag that is used by EMUnhaltAndWakeUp() to force
470	* the virtual CPU out of the next (/current) halted state. It is not processed
471	* nor cleared by emR3ForcedActions (similar to VMCPU_FF_BLOCK_NMIS), instead it
472	* is cleared the next time EM leaves the HALTED state. */
473	#define VMCPU_FF_UNHALT RT_BIT_64(VMCPU_FF_UNHALT_BIT)
474	#define VMCPU_FF_UNHALT_BIT 6
475	/** Pending IEM action (mask). */
476	#define VMCPU_FF_IEM RT_BIT_64(VMCPU_FF_IEM_BIT)
477	/** Pending IEM action (bit number). */
478	#define VMCPU_FF_IEM_BIT 7
479	/** Pending APIC action (bit number). */
480	#define VMCPU_FF_UPDATE_APIC_BIT 8
481	/** This action forces the VM to update APIC's asynchronously arrived
482	* interrupts as pending interrupts. */
483	#define VMCPU_FF_UPDATE_APIC RT_BIT_64(VMCPU_FF_UPDATE_APIC_BIT)
484	/** This action forces the VM to service pending requests from other
485	* thread or requests which must be executed in another context. */
486	#define VMCPU_FF_REQUEST RT_BIT_64(VMCPU_FF_REQUEST_BIT)
487	#define VMCPU_FF_REQUEST_BIT 9
488	/** Pending DBGF event (alternative to passing VINF_EM_DBG_EVENT around). */
489	#define VMCPU_FF_DBGF RT_BIT_64(VMCPU_FF_DBGF_BIT)
490	/** The bit number for VMCPU_FF_DBGF. */
491	#define VMCPU_FF_DBGF_BIT 10
492	/** Hardware virtualized nested-guest interrupt pending. */
493	#define VMCPU_FF_INTERRUPT_NESTED_GUEST RT_BIT_64(VMCPU_FF_INTERRUPT_NESTED_GUEST_BIT)
494	#define VMCPU_FF_INTERRUPT_NESTED_GUEST_BIT 11
495	/** This action forces PGM to update changes to CR3 when the guest was in HM mode
496	* (when using nested paging). */
497	#define VMCPU_FF_HM_UPDATE_CR3 RT_BIT_64(VMCPU_FF_HM_UPDATE_CR3_BIT)
498	#define VMCPU_FF_HM_UPDATE_CR3_BIT 12
499	/* Bit 13 used to be VMCPU_FF_HM_UPDATE_PAE_PDPES. */
500	/** This action forces the VM to resync the page tables before going
501	* back to execute guest code. (GLOBAL FLUSH) */
502	#define VMCPU_FF_PGM_SYNC_CR3 RT_BIT_64(VMCPU_FF_PGM_SYNC_CR3_BIT)
503	#define VMCPU_FF_PGM_SYNC_CR3_BIT 16
504	/** Same as VM_FF_PGM_SYNC_CR3 except that global pages can be skipped.
505	* (NON-GLOBAL FLUSH) */
506	#define VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL RT_BIT_64(VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL_BIT)
507	#define VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL_BIT 17
508	/** Check for pending TLB shootdown actions (deprecated)
509	* Reserved for future HM re-use if necessary / safe.
510	* Consumer: HM */
511	#define VMCPU_FF_TLB_SHOOTDOWN_UNUSED RT_BIT_64(VMCPU_FF_TLB_SHOOTDOWN_UNUSED_BIT)
512	#define VMCPU_FF_TLB_SHOOTDOWN_UNUSED_BIT 18
513	/** Check for pending TLB flush action.
514	* Consumer: HM
515	* @todo rename to VMCPU_FF_HM_TLB_FLUSH */
516	#define VMCPU_FF_TLB_FLUSH RT_BIT_64(VMCPU_FF_TLB_FLUSH_BIT)
517	/** The bit number for VMCPU_FF_TLB_FLUSH. */
518	#define VMCPU_FF_TLB_FLUSH_BIT 19
519	/* 20 used to be VMCPU_FF_TRPM_SYNC_IDT (raw-mode only). */
520	/* 21 used to be VMCPU_FF_SELM_SYNC_TSS (raw-mode only). */
521	/* 22 used to be VMCPU_FF_SELM_SYNC_GDT (raw-mode only). */
522	/* 23 used to be VMCPU_FF_SELM_SYNC_LDT (raw-mode only). */
523	/* 24 used to be VMCPU_FF_INHIBIT_INTERRUPTS, which moved to CPUMCTX::eflags.uBoth in v7.0.4. */
524	/* 25 used to be VMCPU_FF_BLOCK_NMIS, which moved to CPUMCTX::eflags.uBoth in v7.0.4. */
525	/** Force return to Ring-3. */
526	#define VMCPU_FF_TO_R3 RT_BIT_64(VMCPU_FF_TO_R3_BIT)
527	#define VMCPU_FF_TO_R3_BIT 28
528	/** Force return to ring-3 to service pending I/O or MMIO write.
529	* This is a backup for mechanism VINF_IOM_R3_IOPORT_COMMIT_WRITE and
530	* VINF_IOM_R3_MMIO_COMMIT_WRITE, allowing VINF_EM_DBG_BREAKPOINT and similar
531	* status codes to be propagated at the same time without loss. */
532	#define VMCPU_FF_IOM RT_BIT_64(VMCPU_FF_IOM_BIT)
533	#define VMCPU_FF_IOM_BIT 29
534	/* 30 used to be VMCPU_FF_CPUM */
535	/** VMX-preemption timer expired. */
536	#define VMCPU_FF_VMX_PREEMPT_TIMER RT_BIT_64(VMCPU_FF_VMX_PREEMPT_TIMER_BIT)
537	#define VMCPU_FF_VMX_PREEMPT_TIMER_BIT 31
538	/** Pending MTF (Monitor Trap Flag) event. */
539	#define VMCPU_FF_VMX_MTF RT_BIT_64(VMCPU_FF_VMX_MTF_BIT)
540	#define VMCPU_FF_VMX_MTF_BIT 32
541	/** VMX APIC-write emulation pending.
542	* @todo possible candidate for internal EFLAGS, or maybe just a summary bit
543	* (see also VMCPU_FF_VMX_INT_WINDOW). */
544	#define VMCPU_FF_VMX_APIC_WRITE RT_BIT_64(VMCPU_FF_VMX_APIC_WRITE_BIT)
545	#define VMCPU_FF_VMX_APIC_WRITE_BIT 33
546	/** VMX interrupt-window event pending.
547	*
548	* "Pending" is misleading here, it would be better to say that the event need
549	* to be generated at the next opportunity and that this flag causes it to be
550	* polled for on every instruction boundrary and such.
551	*
552	* @todo Change the IEM side of this to not poll but to track down the places
553	* where it can be generated and set an internal EFLAGS bit that causes it
554	* to be checked out when finishing the current instruction. */
555	#define VMCPU_FF_VMX_INT_WINDOW RT_BIT_64(VMCPU_FF_VMX_INT_WINDOW_BIT)
556	#define VMCPU_FF_VMX_INT_WINDOW_BIT 34
557	/** VMX NMI-window event pending.
558	* Same "pending" comment and todo in VMCPU_FF_VMX_INT_WINDOW. */
559	#define VMCPU_FF_VMX_NMI_WINDOW RT_BIT_64(VMCPU_FF_VMX_NMI_WINDOW_BIT)
560	#define VMCPU_FF_VMX_NMI_WINDOW_BIT 35
561
562
563	/** Externally VM forced actions. Used to quit the idle/wait loop. */
564	#define VM_FF_EXTERNAL_SUSPENDED_MASK ( VM_FF_CHECK_VM_STATE \| VM_FF_DBGF \| VM_FF_REQUEST \| VM_FF_EMT_RENDEZVOUS )
565	/** Externally VMCPU forced actions. Used to quit the idle/wait loop. */
566	#define VMCPU_FF_EXTERNAL_SUSPENDED_MASK ( VMCPU_FF_REQUEST \| VMCPU_FF_DBGF )
567
568	/** Externally forced VM actions. Used to quit the idle/wait loop. */
569	#define VM_FF_EXTERNAL_HALTED_MASK ( VM_FF_CHECK_VM_STATE \| VM_FF_DBGF \| VM_FF_REQUEST \
570	\| VM_FF_PDM_QUEUES \| VM_FF_PDM_DMA \| VM_FF_EMT_RENDEZVOUS )
571	/** Externally forced VMCPU actions. Used to quit the idle/wait loop. */
572	#define VMCPU_FF_EXTERNAL_HALTED_MASK ( VMCPU_FF_UPDATE_APIC \| VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC \
573	\| VMCPU_FF_REQUEST \| VMCPU_FF_INTERRUPT_NMI \| VMCPU_FF_INTERRUPT_SMI \
574	\| VMCPU_FF_UNHALT \| VMCPU_FF_TIMER \| VMCPU_FF_DBGF \
575	\| VMCPU_FF_INTERRUPT_NESTED_GUEST)
576
577	/** High priority VM pre-execution actions. */
578	#define VM_FF_HIGH_PRIORITY_PRE_MASK ( VM_FF_CHECK_VM_STATE \| VM_FF_DBGF \| VM_FF_TM_VIRTUAL_SYNC \
579	\| VM_FF_DEBUG_SUSPEND \| VM_FF_PGM_NEED_HANDY_PAGES \| VM_FF_PGM_NO_MEMORY \
580	\| VM_FF_EMT_RENDEZVOUS )
581	/** High priority VMCPU pre-execution actions. */
582	#define VMCPU_FF_HIGH_PRIORITY_PRE_MASK ( VMCPU_FF_TIMER \| VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC \
583	\| VMCPU_FF_UPDATE_APIC \| VMCPU_FF_DBGF \
584	\| VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL \
585	\| VMCPU_FF_INTERRUPT_NESTED_GUEST \| VMCPU_FF_VMX_MTF \| VMCPU_FF_VMX_APIC_WRITE \
586	\| VMCPU_FF_VMX_PREEMPT_TIMER \| VMCPU_FF_VMX_NMI_WINDOW \| VMCPU_FF_VMX_INT_WINDOW )
587
588	/** High priority VM pre raw-mode execution mask. */
589	#define VM_FF_HIGH_PRIORITY_PRE_RAW_MASK ( VM_FF_PGM_NEED_HANDY_PAGES \| VM_FF_PGM_NO_MEMORY )
590	/** High priority VMCPU pre raw-mode execution mask. */
591	#define VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK ( VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL )
592
593	/** High priority post-execution actions. */
594	#define VM_FF_HIGH_PRIORITY_POST_MASK ( VM_FF_PGM_NO_MEMORY )
595	/** High priority post-execution actions. */
596	#define VMCPU_FF_HIGH_PRIORITY_POST_MASK ( VMCPU_FF_PDM_CRITSECT \| VMCPU_FF_HM_UPDATE_CR3 \| VMCPU_FF_IEM \| VMCPU_FF_IOM )
597
598	/** Normal priority VM post-execution actions. */
599	#define VM_FF_NORMAL_PRIORITY_POST_MASK ( VM_FF_CHECK_VM_STATE \| VM_FF_DBGF \| VM_FF_RESET \
600	\| VM_FF_PGM_NO_MEMORY \| VM_FF_EMT_RENDEZVOUS)
601	/** Normal priority VMCPU post-execution actions. */
602	#define VMCPU_FF_NORMAL_PRIORITY_POST_MASK ( VMCPU_FF_DBGF )
603
604	/** Normal priority VM actions. */
605	#define VM_FF_NORMAL_PRIORITY_MASK ( VM_FF_REQUEST \| VM_FF_PDM_QUEUES \| VM_FF_PDM_DMA \| VM_FF_EMT_RENDEZVOUS)
606	/** Normal priority VMCPU actions. */
607	#define VMCPU_FF_NORMAL_PRIORITY_MASK ( VMCPU_FF_REQUEST )
608
609	/** Flags to clear before resuming guest execution. */
610	#define VMCPU_FF_RESUME_GUEST_MASK ( VMCPU_FF_TO_R3 )
611
612
613	/** VM flags that cause the REP[\|NE\|E] STRINS loops to yield immediately. */
614	#define VM_FF_HIGH_PRIORITY_POST_REPSTR_MASK ( VM_FF_TM_VIRTUAL_SYNC \| VM_FF_PGM_NEED_HANDY_PAGES \| VM_FF_PGM_NO_MEMORY \
615	\| VM_FF_EMT_RENDEZVOUS \| VM_FF_PGM_POOL_FLUSH_PENDING \| VM_FF_RESET)
616	/** VM flags that cause the REP[\|NE\|E] STRINS loops to yield. */
617	#define VM_FF_YIELD_REPSTR_MASK ( VM_FF_HIGH_PRIORITY_POST_REPSTR_MASK \
618	\| VM_FF_PDM_QUEUES \| VM_FF_PDM_DMA \| VM_FF_DBGF \| VM_FF_DEBUG_SUSPEND )
619	/** VMCPU flags that cause the REP[\|NE\|E] STRINS loops to yield immediately. */
620	#ifdef IN_RING3
621	# define VMCPU_FF_HIGH_PRIORITY_POST_REPSTR_MASK ( VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL \| VMCPU_FF_DBGF \
622	\| VMCPU_FF_VMX_MTF )
623	#else
624	# define VMCPU_FF_HIGH_PRIORITY_POST_REPSTR_MASK ( VMCPU_FF_TO_R3 \| VMCPU_FF_IEM \| VMCPU_FF_IOM \| VMCPU_FF_PGM_SYNC_CR3 \
625	\| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL \| VMCPU_FF_DBGF \| VMCPU_FF_VMX_MTF )
626	#endif
627	/** VMCPU flags that cause the REP[\|NE\|E] STRINS loops to yield, interrupts
628	* enabled. */
629	#define VMCPU_FF_YIELD_REPSTR_MASK ( VMCPU_FF_HIGH_PRIORITY_POST_REPSTR_MASK \
630	\| VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_UPDATE_APIC \| VMCPU_FF_INTERRUPT_PIC \
631	\| VMCPU_FF_INTERRUPT_NMI \| VMCPU_FF_INTERRUPT_SMI \| VMCPU_FF_PDM_CRITSECT \
632	\| VMCPU_FF_TIMER \| VMCPU_FF_REQUEST \
633	\| VMCPU_FF_INTERRUPT_NESTED_GUEST )
634	/** VMCPU flags that cause the REP[\|NE\|E] STRINS loops to yield, interrupts
635	* disabled. */
636	#define VMCPU_FF_YIELD_REPSTR_NOINT_MASK ( VMCPU_FF_YIELD_REPSTR_MASK \
637	& ~( VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_UPDATE_APIC \| VMCPU_FF_INTERRUPT_PIC \
638	\| VMCPU_FF_INTERRUPT_NESTED_GUEST) )
639
640	/** VM Flags that cause the HM loops to go back to ring-3. */
641	#define VM_FF_HM_TO_R3_MASK ( VM_FF_TM_VIRTUAL_SYNC \| VM_FF_PGM_NEED_HANDY_PAGES \| VM_FF_PGM_NO_MEMORY \
642	\| VM_FF_PDM_QUEUES \| VM_FF_EMT_RENDEZVOUS)
643	/** VMCPU Flags that cause the HM loops to go back to ring-3. */
644	#define VMCPU_FF_HM_TO_R3_MASK ( VMCPU_FF_TO_R3 \| VMCPU_FF_TIMER \| VMCPU_FF_PDM_CRITSECT \
645	\| VMCPU_FF_IEM \| VMCPU_FF_IOM)
646
647	/** High priority ring-0 VM pre HM-mode execution mask. */
648	#define VM_FF_HP_R0_PRE_HM_MASK (VM_FF_HM_TO_R3_MASK \| VM_FF_REQUEST \| VM_FF_PGM_POOL_FLUSH_PENDING \| VM_FF_PDM_DMA)
649	/** High priority ring-0 VMCPU pre HM-mode execution mask. */
650	#define VMCPU_FF_HP_R0_PRE_HM_MASK ( VMCPU_FF_HM_TO_R3_MASK \| VMCPU_FF_PGM_SYNC_CR3 \
651	\| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL \| VMCPU_FF_REQUEST \
652	\| VMCPU_FF_VMX_APIC_WRITE \| VMCPU_FF_VMX_MTF \| VMCPU_FF_VMX_PREEMPT_TIMER)
653	/** High priority ring-0 VM pre HM-mode execution mask, single stepping. */
654	#define VM_FF_HP_R0_PRE_HM_STEP_MASK (VM_FF_HP_R0_PRE_HM_MASK & ~( VM_FF_TM_VIRTUAL_SYNC \| VM_FF_PDM_QUEUES \
655	\| VM_FF_EMT_RENDEZVOUS \| VM_FF_REQUEST \
656	\| VM_FF_PDM_DMA) )
657	/** High priority ring-0 VMCPU pre HM-mode execution mask, single stepping. */
658	#define VMCPU_FF_HP_R0_PRE_HM_STEP_MASK (VMCPU_FF_HP_R0_PRE_HM_MASK & ~( VMCPU_FF_TO_R3 \| VMCPU_FF_TIMER \
659	\| VMCPU_FF_PDM_CRITSECT \| VMCPU_FF_REQUEST) )
660
661	/** All the VMX nested-guest flags. */
662	#define VMCPU_FF_VMX_ALL_MASK ( VMCPU_FF_VMX_PREEMPT_TIMER \| VMCPU_FF_VMX_MTF \| VMCPU_FF_VMX_APIC_WRITE \
663	\| VMCPU_FF_VMX_INT_WINDOW \| VMCPU_FF_VMX_NMI_WINDOW )
664
665	/** All the forced VM flags. */
666	#define VM_FF_ALL_MASK (UINT32_MAX)
667	/** All the forced VMCPU flags. */
668	#define VMCPU_FF_ALL_MASK (UINT32_MAX)
669
670	/** All the forced VM flags except those related to raw-mode and hardware
671	* assisted execution. */
672	#define VM_FF_ALL_REM_MASK (~(VM_FF_HIGH_PRIORITY_PRE_RAW_MASK) \| VM_FF_PGM_NEED_HANDY_PAGES \| VM_FF_PGM_NO_MEMORY)
673	/** All the forced VMCPU flags except those related to raw-mode and hardware
674	* assisted execution. */
675	#define VMCPU_FF_ALL_REM_MASK (~(VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK \| VMCPU_FF_PDM_CRITSECT \| VMCPU_FF_TLB_FLUSH))
676	/** @} */
677
678	/** @def VM_FF_SET
679	* Sets a single force action flag.
680	*
681	* @param pVM The cross context VM structure.
682	* @param fFlag The flag to set.
683	*/
684	#define VM_FF_SET(pVM, fFlag) do { \
685	AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
686	AssertCompile((fFlag) == RT_BIT_32(fFlag##_BIT)); \
687	ASMAtomicOrU32(&(pVM)->fGlobalForcedActions, (fFlag)); \
688	} while (0)
689
690	/** @def VMCPU_FF_SET
691	* Sets a single force action flag for the given VCPU.
692	*
693	* @param pVCpu The cross context virtual CPU structure.
694	* @param fFlag The flag to set.
695	* @sa VMCPU_FF_SET_MASK
696	*/
697	#ifdef VMCPU_WITH_64_BIT_FFS
698	# define VMCPU_FF_SET(pVCpu, fFlag) do { \
699	AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
700	AssertCompile((fFlag) == RT_BIT_64(fFlag##_BIT)); \
701	ASMAtomicBitSet(&(pVCpu)->fLocalForcedActions, fFlag##_BIT); \
702	} while (0)
703	#else
704	# define VMCPU_FF_SET(pVCpu, fFlag) do { \
705	AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
706	AssertCompile((fFlag) == RT_BIT_32(fFlag##_BIT)); \
707	ASMAtomicOrU32(&(pVCpu)->fLocalForcedActions, (fFlag)); \
708	} while (0)
709	#endif
710
711	/** @def VMCPU_FF_SET_MASK
712	* Sets a two or more force action flag for the given VCPU.
713	*
714	* @param pVCpu The cross context virtual CPU structure.
715	* @param fFlags The flags to set.
716	* @sa VMCPU_FF_SET
717	*/
718	#ifdef VMCPU_WITH_64_BIT_FFS
719	# if ARCH_BITS > 32
720	# define VMCPU_FF_SET_MASK(pVCpu, fFlags) \
721	do { ASMAtomicOrU64(&pVCpu->fLocalForcedActions, (fFlags)); } while (0)
722	# else
723	# define VMCPU_FF_SET_MASK(pVCpu, fFlags) do { \
724	if (!((fFlags) >> 32)) ASMAtomicOrU32((uint32_t volatile *)&pVCpu->fLocalForcedActions, (uint32_t)(fFlags)); \
725	else ASMAtomicOrU64(&pVCpu->fLocalForcedActions, (fFlags)); \
726	} while (0)
727	# endif
728	#else
729	# define VMCPU_FF_SET_MASK(pVCpu, fFlags) \
730	do { ASMAtomicOrU32(&pVCpu->fLocalForcedActions, (fFlags)); } while (0)
731	#endif
732
733	/** @def VM_FF_CLEAR
734	* Clears a single force action flag.
735	*
736	* @param pVM The cross context VM structure.
737	* @param fFlag The flag to clear.
738	*/
739	#define VM_FF_CLEAR(pVM, fFlag) do { \
740	AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
741	AssertCompile((fFlag) == RT_BIT_32(fFlag##_BIT)); \
742	ASMAtomicAndU32(&(pVM)->fGlobalForcedActions, ~(fFlag)); \
743	} while (0)
744
745	/** @def VMCPU_FF_CLEAR
746	* Clears a single force action flag for the given VCPU.
747	*
748	* @param pVCpu The cross context virtual CPU structure.
749	* @param fFlag The flag to clear.
750	*/
751	#ifdef VMCPU_WITH_64_BIT_FFS
752	# define VMCPU_FF_CLEAR(pVCpu, fFlag) do { \
753	AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
754	AssertCompile((fFlag) == RT_BIT_64(fFlag##_BIT)); \
755	ASMAtomicBitClear(&(pVCpu)->fLocalForcedActions, fFlag##_BIT); \
756	} while (0)
757	#else
758	# define VMCPU_FF_CLEAR(pVCpu, fFlag) do { \
759	AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
760	AssertCompile((fFlag) == RT_BIT_32(fFlag##_BIT)); \
761	ASMAtomicAndU32(&(pVCpu)->fLocalForcedActions, ~(fFlag)); \
762	} while (0)
763	#endif
764
765	/** @def VMCPU_FF_CLEAR_MASK
766	* Clears two or more force action flags for the given VCPU.
767	*
768	* @param pVCpu The cross context virtual CPU structure.
769	* @param fFlags The flags to clear.
770	*/
771	#ifdef VMCPU_WITH_64_BIT_FFS
772	# if ARCH_BITS > 32
773	# define VMCPU_FF_CLEAR_MASK(pVCpu, fFlags) \
774	do { ASMAtomicAndU64(&(pVCpu)->fLocalForcedActions, ~(fFlags)); } while (0)
775	# else
776	# define VMCPU_FF_CLEAR_MASK(pVCpu, fFlags) do { \
777	if (!((fFlags) >> 32)) ASMAtomicAndU32((uint32_t volatile *)&(pVCpu)->fLocalForcedActions, ~(uint32_t)(fFlags)); \
778	else ASMAtomicAndU64(&(pVCpu)->fLocalForcedActions, ~(fFlags)); \
779	} while (0)
780	# endif
781	#else
782	# define VMCPU_FF_CLEAR_MASK(pVCpu, fFlags) \
783	do { ASMAtomicAndU32(&(pVCpu)->fLocalForcedActions, ~(fFlags)); } while (0)
784	#endif
785
786	/** @def VM_FF_IS_SET
787	* Checks if single a force action flag is set.
788	*
789	* @param pVM The cross context VM structure.
790	* @param fFlag The flag to check.
791	* @sa VM_FF_IS_ANY_SET
792	*/
793	#if !defined(VBOX_STRICT) \|\| !defined(RT_COMPILER_SUPPORTS_LAMBDA)
794	# define VM_FF_IS_SET(pVM, fFlag) RT_BOOL((pVM)->fGlobalForcedActions & (fFlag))
795	#else
796	# define VM_FF_IS_SET(pVM, fFlag) \
797	([](PVM a_pVM) -> bool \
798	{ \
799	AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
800	AssertCompile((fFlag) == RT_BIT_32(fFlag##_BIT)); \
801	return RT_BOOL(a_pVM->fGlobalForcedActions & (fFlag)); \
802	}(pVM))
803	#endif
804
805	/** @def VMCPU_FF_IS_SET
806	* Checks if a single force action flag is set for the given VCPU.
807	*
808	* @param pVCpu The cross context virtual CPU structure.
809	* @param fFlag The flag to check.
810	* @sa VMCPU_FF_IS_ANY_SET
811	*/
812	#if !defined(VBOX_STRICT) \|\| !defined(RT_COMPILER_SUPPORTS_LAMBDA)
813	# define VMCPU_FF_IS_SET(pVCpu, fFlag) RT_BOOL((pVCpu)->fLocalForcedActions & (fFlag))
814	#else
815	# define VMCPU_FF_IS_SET(pVCpu, fFlag) \
816	([](PCVMCPU a_pVCpu) -> bool \
817	{ \
818	AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \
819	AssertCompile((fFlag) == RT_BIT_64(fFlag##_BIT)); \
820	return RT_BOOL(a_pVCpu->fLocalForcedActions & (fFlag)); \
821	}(pVCpu))
822	#endif
823
824	/** @def VM_FF_IS_ANY_SET
825	* Checks if one or more force action in the specified set is pending.
826	*
827	* @param pVM The cross context VM structure.
828	* @param fFlags The flags to check for.
829	* @sa VM_FF_IS_SET
830	*/
831	#define VM_FF_IS_ANY_SET(pVM, fFlags) RT_BOOL((pVM)->fGlobalForcedActions & (fFlags))
832
833	/** @def VMCPU_FF_IS_ANY_SET
834	* Checks if two or more force action flags in the specified set is set for the given VCPU.
835	*
836	* @param pVCpu The cross context virtual CPU structure.
837	* @param fFlags The flags to check for.
838	* @sa VMCPU_FF_IS_SET
839	*/
840	#define VMCPU_FF_IS_ANY_SET(pVCpu, fFlags) RT_BOOL((pVCpu)->fLocalForcedActions & (fFlags))
841
842	/** @def VM_FF_TEST_AND_CLEAR
843	* Checks if one (!) force action in the specified set is pending and clears it atomically
844	*
845	* @returns true if the bit was set.
846	* @returns false if the bit was clear.
847	* @param pVM The cross context VM structure.
848	* @param fFlag Flag constant to check and clear (_BIT is appended).
849	*/
850	#define VM_FF_TEST_AND_CLEAR(pVM, fFlag) (ASMAtomicBitTestAndClear(&(pVM)->fGlobalForcedActions, fFlag##_BIT))
851
852	/** @def VMCPU_FF_TEST_AND_CLEAR
853	* Checks if one (!) force action in the specified set is pending and clears it atomically
854	*
855	* @returns true if the bit was set.
856	* @returns false if the bit was clear.
857	* @param pVCpu The cross context virtual CPU structure.
858	* @param fFlag Flag constant to check and clear (_BIT is appended).
859	*/
860	#define VMCPU_FF_TEST_AND_CLEAR(pVCpu, fFlag) (ASMAtomicBitTestAndClear(&(pVCpu)->fLocalForcedActions, fFlag##_BIT))
861
862	/** @def VM_FF_IS_PENDING_EXCEPT
863	* Checks if one or more force action in the specified set is pending while one
864	* or more other ones are not.
865	*
866	* @param pVM The cross context VM structure.
867	* @param fFlags The flags to check for.
868	* @param fExcpt The flags that should not be set.
869	*/
870	#define VM_FF_IS_PENDING_EXCEPT(pVM, fFlags, fExcpt) \
871	( ((pVM)->fGlobalForcedActions & (fFlags)) && !((pVM)->fGlobalForcedActions & (fExcpt)) )
872
873	/** @def VM_IS_EMT
874	* Checks if the current thread is the emulation thread (EMT).
875	*
876	* @remark The ring-0 variation will need attention if we expand the ring-0
877	* code to let threads other than EMT mess around with the VM.
878	*/
879	#ifdef IN_RC
880	# define VM_IS_EMT(pVM) true
881	#else
882	# define VM_IS_EMT(pVM) (VMMGetCpu(pVM) != NULL)
883	#endif
884
885	/** @def VMCPU_IS_EMT
886	* Checks if the current thread is the emulation thread (EMT) for the specified
887	* virtual CPU.
888	*/
889	#ifdef IN_RC
890	# define VMCPU_IS_EMT(pVCpu) true
891	#else
892	# define VMCPU_IS_EMT(pVCpu) ((pVCpu) && ((pVCpu) == VMMGetCpu((pVCpu)->CTX_SUFF(pVM))))
893	#endif
894
895	/** @def VM_ASSERT_EMT
896	* Asserts that the current thread IS the emulation thread (EMT).
897	*/
898	#ifdef IN_RC
899	# define VM_ASSERT_EMT(pVM) Assert(VM_IS_EMT(pVM))
900	#elif defined(IN_RING0)
901	# define VM_ASSERT_EMT(pVM) Assert(VM_IS_EMT(pVM))
902	#else
903	# define VM_ASSERT_EMT(pVM) \
904	AssertMsg(VM_IS_EMT(pVM), \
905	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd\n", RTThreadNativeSelf(), VMR3GetVMCPUNativeThread(pVM)))
906	#endif
907
908	/** @def VMCPU_ASSERT_EMT
909	* Asserts that the current thread IS the emulation thread (EMT) of the
910	* specified virtual CPU.
911	*/
912	#ifdef IN_RC
913	# define VMCPU_ASSERT_EMT(pVCpu) Assert(VMCPU_IS_EMT(pVCpu))
914	#elif defined(IN_RING0)
915	# define VMCPU_ASSERT_EMT(pVCpu) AssertMsg(VMCPU_IS_EMT(pVCpu), \
916	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd idCpu=%u\n", \
917	RTThreadNativeSelf(), (pVCpu) ? (pVCpu)->hNativeThreadR0 : 0, \
918	(pVCpu) ? (pVCpu)->idCpu : 0))
919	#else
920	# define VMCPU_ASSERT_EMT(pVCpu) AssertMsg(VMCPU_IS_EMT(pVCpu), \
921	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd idCpu=%#x\n", \
922	RTThreadNativeSelf(), (pVCpu)->hNativeThread, (pVCpu)->idCpu))
923	#endif
924
925	/** @def VM_ASSERT_EMT_RETURN
926	* Asserts that the current thread IS the emulation thread (EMT) and returns if it isn't.
927	*/
928	#ifdef IN_RC
929	# define VM_ASSERT_EMT_RETURN(pVM, rc) AssertReturn(VM_IS_EMT(pVM), (rc))
930	#elif defined(IN_RING0)
931	# define VM_ASSERT_EMT_RETURN(pVM, rc) AssertReturn(VM_IS_EMT(pVM), (rc))
932	#else
933	# define VM_ASSERT_EMT_RETURN(pVM, rc) \
934	AssertMsgReturn(VM_IS_EMT(pVM), \
935	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd\n", RTThreadNativeSelf(), VMR3GetVMCPUNativeThread(pVM)), \
936	(rc))
937	#endif
938
939	/** @def VMCPU_ASSERT_EMT_RETURN
940	* Asserts that the current thread IS the emulation thread (EMT) and returns if it isn't.
941	*/
942	#ifdef IN_RC
943	# define VMCPU_ASSERT_EMT_RETURN(pVCpu, rc) AssertReturn(VMCPU_IS_EMT(pVCpu), (rc))
944	#elif defined(IN_RING0)
945	# define VMCPU_ASSERT_EMT_RETURN(pVCpu, rc) AssertReturn(VMCPU_IS_EMT(pVCpu), (rc))
946	#else
947	# define VMCPU_ASSERT_EMT_RETURN(pVCpu, rc) \
948	AssertMsgReturn(VMCPU_IS_EMT(pVCpu), \
949	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd idCpu=%#x\n", \
950	RTThreadNativeSelf(), (pVCpu)->hNativeThread, (pVCpu)->idCpu), \
951	(rc))
952	#endif
953
954	/** @def VMCPU_ASSERT_EMT_OR_GURU
955	* Asserts that the current thread IS the emulation thread (EMT) of the
956	* specified virtual CPU.
957	*/
958	#if defined(IN_RC) \|\| defined(IN_RING0)
959	# define VMCPU_ASSERT_EMT_OR_GURU(pVCpu) Assert( VMCPU_IS_EMT(pVCpu) \
960	\|\| pVCpu->CTX_SUFF(pVM)->enmVMState == VMSTATE_GURU_MEDITATION \
961	\|\| pVCpu->CTX_SUFF(pVM)->enmVMState == VMSTATE_GURU_MEDITATION_LS )
962	#else
963	# define VMCPU_ASSERT_EMT_OR_GURU(pVCpu) \
964	AssertMsg( VMCPU_IS_EMT(pVCpu) \
965	\|\| pVCpu->CTX_SUFF(pVM)->enmVMState == VMSTATE_GURU_MEDITATION \
966	\|\| pVCpu->CTX_SUFF(pVM)->enmVMState == VMSTATE_GURU_MEDITATION_LS, \
967	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd idCpu=%#x\n", \
968	RTThreadNativeSelf(), (pVCpu)->hNativeThread, (pVCpu)->idCpu))
969	#endif
970
971	/** @def VMCPU_ASSERT_EMT_OR_NOT_RUNNING
972	* Asserts that the current thread IS the emulation thread (EMT) of the
973	* specified virtual CPU or the VM is not running.
974	*/
975	#if defined(IN_RC) \|\| defined(IN_RING0)
976	# define VMCPU_ASSERT_EMT_OR_NOT_RUNNING(pVCpu) \
977	Assert( VMCPU_IS_EMT(pVCpu) \
978	\|\| !VM_IS_RUNNING_FOR_ASSERTIONS_ONLY((pVCpu)->CTX_SUFF(pVM)) )
979	#else
980	# define VMCPU_ASSERT_EMT_OR_NOT_RUNNING(pVCpu) \
981	AssertMsg( VMCPU_IS_EMT(pVCpu) \
982	\|\| !VM_IS_RUNNING_FOR_ASSERTIONS_ONLY((pVCpu)->CTX_SUFF(pVM)), \
983	("Not emulation thread! Thread=%RTnthrd ThreadEMT=%RTnthrd idCpu=%#x\n", \
984	RTThreadNativeSelf(), (pVCpu)->hNativeThread, (pVCpu)->idCpu))
985	#endif
986
987	/** @def VMSTATE_IS_RUNNING
988	* Checks if the given state indicates a running VM.
989	*/
990	#define VMSTATE_IS_RUNNING(a_enmVMState) \
991	( (a_enmVMState) == VMSTATE_RUNNING \
992	\|\| (a_enmVMState) == VMSTATE_RUNNING_LS )
993
994	/** @def VM_IS_RUNNING_FOR_ASSERTIONS_ONLY
995	* Checks if the VM is running.
996	* @note This is only for pure debug assertions. No AssertReturn or similar!
997	* @sa VMSTATE_IS_RUNNING
998	*/
999	#define VM_IS_RUNNING_FOR_ASSERTIONS_ONLY(pVM) \
1000	( (pVM)->enmVMState == VMSTATE_RUNNING \
1001	\|\| (pVM)->enmVMState == VMSTATE_RUNNING_LS )
1002
1003
1004	/** @def VMSTATE_IS_POWERED_ON
1005	* Checks if the given state indicates the VM is powered on.
1006	*
1007	* @note Excludes all error states, so a powered on VM that hit a fatal error,
1008	* guru meditation, state load failure or similar will not be considered
1009	* powered on by this test.
1010	*/
1011	#define VMSTATE_IS_POWERED_ON(a_enmVMState) \
1012	( (a_enmVMState) >= VMSTATE_RESUMING && (a_enmVMState) < VMSTATE_POWERING_OFF )
1013
1014	/** @def VM_ASSERT_IS_NOT_RUNNING
1015	* Asserts that the VM is not running.
1016	*/
1017	#if defined(IN_RC) \|\| defined(IN_RING0)
1018	#define VM_ASSERT_IS_NOT_RUNNING(pVM) Assert(!VM_IS_RUNNING_FOR_ASSERTIONS_ONLY(pVM))
1019	#else
1020	#define VM_ASSERT_IS_NOT_RUNNING(pVM) AssertMsg(!VM_IS_RUNNING_FOR_ASSERTIONS_ONLY(pVM), \
1021	("VM is running. enmVMState=%d\n", (pVM)->enmVMState))
1022	#endif
1023
1024	/** @def VM_ASSERT_EMT0
1025	* Asserts that the current thread IS emulation thread \#0 (EMT0).
1026	*/
1027	#ifdef IN_RING3
1028	# define VM_ASSERT_EMT0(a_pVM) VMCPU_ASSERT_EMT((a_pVM)->apCpusR3[0])
1029	#else
1030	# define VM_ASSERT_EMT0(a_pVM) VMCPU_ASSERT_EMT(&(a_pVM)->aCpus[0])
1031	#endif
1032
1033	/** @def VM_ASSERT_EMT0_RETURN
1034	* Asserts that the current thread IS emulation thread \#0 (EMT0) and returns if
1035	* it isn't.
1036	*/
1037	#ifdef IN_RING3
1038	# define VM_ASSERT_EMT0_RETURN(pVM, rc) VMCPU_ASSERT_EMT_RETURN((pVM)->apCpusR3[0], (rc))
1039	#else
1040	# define VM_ASSERT_EMT0_RETURN(pVM, rc) VMCPU_ASSERT_EMT_RETURN(&(pVM)->aCpus[0], (rc))
1041	#endif
1042
1043
1044	/**
1045	* Asserts that the current thread is NOT the emulation thread.
1046	*/
1047	#define VM_ASSERT_OTHER_THREAD(pVM) \
1048	AssertMsg(!VM_IS_EMT(pVM), ("Not other thread!!\n"))
1049
1050
1051	/** @def VM_ASSERT_STATE
1052	* Asserts a certain VM state.
1053	*/
1054	#define VM_ASSERT_STATE(pVM, _enmState) \
1055	AssertMsg((pVM)->enmVMState == (_enmState), \
1056	("state %s, expected %s\n", VMGetStateName((pVM)->enmVMState), VMGetStateName(_enmState)))
1057
1058	/** @def VM_ASSERT_STATE_RETURN
1059	* Asserts a certain VM state and returns if it doesn't match.
1060	*/
1061	#define VM_ASSERT_STATE_RETURN(pVM, _enmState, rc) \
1062	AssertMsgReturn((pVM)->enmVMState == (_enmState), \
1063	("state %s, expected %s\n", VMGetStateName((pVM)->enmVMState), VMGetStateName(_enmState)), \
1064	(rc))
1065
1066	/** @def VM_IS_VALID_EXT
1067	* Asserts a the VM handle is valid for external access, i.e. not being destroy
1068	* or terminated. */
1069	#define VM_IS_VALID_EXT(pVM) \
1070	( RT_VALID_ALIGNED_PTR(pVM, PAGE_SIZE) \
1071	&& ( (unsigned)(pVM)->enmVMState < (unsigned)VMSTATE_DESTROYING \
1072	\|\| ( (unsigned)(pVM)->enmVMState == (unsigned)VMSTATE_DESTROYING \
1073	&& VM_IS_EMT(pVM))) )
1074
1075	/** @def VM_ASSERT_VALID_EXT_RETURN
1076	* Asserts a the VM handle is valid for external access, i.e. not being
1077	* destroy or terminated.
1078	*/
1079	#define VM_ASSERT_VALID_EXT_RETURN(pVM, rc) \
1080	AssertMsgReturn(VM_IS_VALID_EXT(pVM), \
1081	("pVM=%p state %s\n", (pVM), RT_VALID_ALIGNED_PTR(pVM, PAGE_SIZE) \
1082	? VMGetStateName(pVM->enmVMState) : ""), \
1083	(rc))
1084
1085	/** @def VMCPU_ASSERT_VALID_EXT_RETURN
1086	* Asserts a the VMCPU handle is valid for external access, i.e. not being
1087	* destroy or terminated.
1088	*/
1089	#define VMCPU_ASSERT_VALID_EXT_RETURN(pVCpu, rc) \
1090	AssertMsgReturn( RT_VALID_ALIGNED_PTR(pVCpu, 64) \
1091	&& RT_VALID_ALIGNED_PTR((pVCpu)->CTX_SUFF(pVM), PAGE_SIZE) \
1092	&& (unsigned)(pVCpu)->CTX_SUFF(pVM)->enmVMState < (unsigned)VMSTATE_DESTROYING, \
1093	("pVCpu=%p pVM=%p state %s\n", (pVCpu), RT_VALID_ALIGNED_PTR(pVCpu, 64) ? (pVCpu)->CTX_SUFF(pVM) : NULL, \
1094	RT_VALID_ALIGNED_PTR(pVCpu, 64) && RT_VALID_ALIGNED_PTR((pVCpu)->CTX_SUFF(pVM), PAGE_SIZE) \
1095	? VMGetStateName((pVCpu)->pVMR3->enmVMState) : ""), \
1096	(rc))
1097
1098	#endif /* !VBOX_FOR_DTRACE_LIB */
1099
1100
1101	/**
1102	* Helper that HM and NEM uses for safely modifying VM::bMainExecutionEngine.
1103	*
1104	* ONLY HM and NEM MAY USE THIS!
1105	*
1106	* @param a_pVM The cross context VM structure.
1107	* @param a_bValue The new value.
1108	* @internal
1109	*/
1110	#define VM_SET_MAIN_EXECUTION_ENGINE(a_pVM, a_bValue) \
1111	do { \
1112	const_cast<uint8_t >(&(a_pVM)->bMainExecutionEngine) = (a_bValue); \
1113	ASMCompilerBarrier(); /* just to be on the safe side */ \
1114	} while (0)
1115
1116	/**
1117	* Checks whether iem-executes-all-mode is used.
1118	*
1119	* @retval true if IEM is used.
1120	* @retval false if not.
1121	*
1122	* @param a_pVM The cross context VM structure.
1123	* @sa VM_IS_HM_OR_NEM_ENABLED, VM_IS_HM_ENABLED, VM_IS_NEM_ENABLED.
1124	* @internal
1125	*/
1126	#define VM_IS_EXEC_ENGINE_IEM(a_pVM) ((a_pVM)->bMainExecutionEngine == VM_EXEC_ENGINE_IEM)
1127
1128	/**
1129	* Checks whether HM (VT-x/AMD-V) or NEM is being used by this VM.
1130	*
1131	* @retval true if either is used.
1132	* @retval false if software virtualization (raw-mode) is used.
1133	*
1134	* @param a_pVM The cross context VM structure.
1135	* @sa VM_IS_EXEC_ENGINE_IEM, VM_IS_HM_ENABLED, VM_IS_NEM_ENABLED.
1136	* @internal
1137	*/
1138	#define VM_IS_HM_OR_NEM_ENABLED(a_pVM) ((a_pVM)->bMainExecutionEngine != VM_EXEC_ENGINE_IEM)
1139
1140	/**
1141	* Checks whether HM is being used by this VM.
1142	*
1143	* @retval true if HM (VT-x/AMD-v) is used.
1144	* @retval false if not.
1145	*
1146	* @param a_pVM The cross context VM structure.
1147	* @sa VM_IS_NEM_ENABLED, VM_IS_EXEC_ENGINE_IEM, VM_IS_HM_OR_NEM_ENABLED.
1148	* @internal
1149	*/
1150	#define VM_IS_HM_ENABLED(a_pVM) ((a_pVM)->bMainExecutionEngine == VM_EXEC_ENGINE_HW_VIRT)
1151
1152	/**
1153	* Checks whether NEM is being used by this VM.
1154	*
1155	* @retval true if a native hypervisor API is used.
1156	* @retval false if not.
1157	*
1158	* @param a_pVM The cross context VM structure.
1159	* @sa VM_IS_HM_ENABLED, VM_IS_EXEC_ENGINE_IEM, VM_IS_HM_OR_NEM_ENABLED.
1160	* @internal
1161	*/
1162	#define VM_IS_NEM_ENABLED(a_pVM) ((a_pVM)->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API)
1163
1164
1165	/**
1166	* The cross context VM structure.
1167	*
1168	* It contains all the VM data which have to be available in all contexts.
1169	* Even if it contains all the data the idea is to use APIs not to modify all
1170	* the members all around the place. Therefore we make use of unions to hide
1171	* everything which isn't local to the current source module. This means we'll
1172	* have to pay a little bit of attention when adding new members to structures
1173	* in the unions and make sure to keep the padding sizes up to date.
1174	*
1175	* Run 'kmk run-struct-tests' (from src/VBox/VMM if you like) after updating!
1176	*/
1177	typedef struct VM
1178	{
1179	/** The state of the VM.
1180	* This field is read only to everyone except the VM and EM. */
1181	VMSTATE volatile enmVMState;
1182	/** Forced action flags.
1183	* See the VM_FF_* \#defines. Updated atomically.
1184	*/
1185	volatile uint32_t fGlobalForcedActions;
1186	/** Pointer to the array of page descriptors for the VM structure allocation. */
1187	R3PTRTYPE(PSUPPAGE) paVMPagesR3;
1188	/** Session handle. For use when calling SUPR0 APIs. */
1189	#ifdef IN_RING0
1190	PSUPDRVSESSION pSessionUnsafe;
1191	#else
1192	PSUPDRVSESSION pSession;
1193	#endif
1194	/** Pointer to the ring-3 VM structure. */
1195	PUVM pUVM;
1196	/** Ring-3 Host Context VM Pointer. */
1197	#ifdef IN_RING0
1198	R3PTRTYPE(struct VM *) pVMR3Unsafe;
1199	#else
1200	R3PTRTYPE(struct VM *) pVMR3;
1201	#endif
1202	/** Ring-0 Host Context VM pointer for making ring-0 calls. */
1203	R0PTRTYPE(struct VM *) pVMR0ForCall;
1204	/** Raw-mode Context VM Pointer. */
1205	uint32_t pVMRC;
1206	/** Padding for new raw-mode (long mode). */
1207	uint32_t pVMRCPadding;
1208
1209	/** The GVM VM handle. Only the GVM should modify this field. */
1210	#ifdef IN_RING0
1211	uint32_t hSelfUnsafe;
1212	#else
1213	uint32_t hSelf;
1214	#endif
1215	/** Number of virtual CPUs. */
1216	#ifdef IN_RING0
1217	uint32_t cCpusUnsafe;
1218	#else
1219	uint32_t cCpus;
1220	#endif
1221	/** CPU excution cap (1-100) */
1222	uint32_t uCpuExecutionCap;
1223
1224	/** Size of the VM structure. */
1225	uint32_t cbSelf;
1226	/** Size of the VMCPU structure. */
1227	uint32_t cbVCpu;
1228	/** Structure version number (TBD). */
1229	uint32_t uStructVersion;
1230
1231	/** @name Various items that are frequently accessed.
1232	* @{ */
1233	/** The main execution engine, VM_EXEC_ENGINE_XXX.
1234	* This is set early during vmR3InitRing3 by HM or NEM. */
1235	uint8_t const bMainExecutionEngine;
1236
1237	/** Hardware VM support is available and enabled.
1238	* Determined very early during init.
1239	* This is placed here for performance reasons.
1240	* @todo obsoleted by bMainExecutionEngine, eliminate. */
1241	bool fHMEnabled;
1242	/** @} */
1243
1244	/** Alignment padding. */
1245	uint8_t uPadding1[6];
1246
1247	/** @name Debugging
1248	* @{ */
1249	/** Ring-3 Host Context VM Pointer. */
1250	R3PTRTYPE(RTTRACEBUF) hTraceBufR3;
1251	/** Ring-0 Host Context VM Pointer. */
1252	R0PTRTYPE(RTTRACEBUF) hTraceBufR0;
1253	/** @} */
1254
1255	/** Max EMT hash lookup collisions (in GVMM). */
1256	uint8_t cMaxEmtHashCollisions;
1257
1258	/** Padding - the unions must be aligned on a 64 bytes boundary. */
1259	uint8_t abAlignment3[HC_ARCH_BITS == 64 ? 23 : 51];
1260
1261	/** CPUM part. */
1262	union
1263	{
1264	#ifdef VMM_INCLUDED_SRC_include_CPUMInternal_h
1265	struct CPUM s;
1266	#endif
1267	#ifdef VBOX_INCLUDED_vmm_cpum_h
1268	/** Read only info exposed about the host and guest CPUs. */
1269	struct
1270	{
1271	/** Padding for hidden fields. */
1272	uint8_t abHidden0[64 + 48];
1273	/** Guest CPU feature information. */
1274	CPUMFEATURES GuestFeatures;
1275	} const ro;
1276	#endif
1277	/** @todo this is rather bloated because of static MSR range allocation.
1278	* Probably a good idea to move it to a separate R0 allocation... */
1279	uint8_t padding[8832 + 1288192 + 0x1d00]; / multiple of 64 */
1280	} cpum;
1281
1282	/** PGM part.
1283	* @note 16384 aligned for zero and mmio page storage. */
1284	union
1285	{
1286	#ifdef VMM_INCLUDED_SRC_include_PGMInternal_h
1287	struct PGM s;
1288	#endif
1289	uint8_t padding[53888]; /* multiple of 64 */
1290	} pgm;
1291
1292	/** VMM part. */
1293	union
1294	{
1295	#ifdef VMM_INCLUDED_SRC_include_VMMInternal_h
1296	struct VMM s;
1297	#endif
1298	uint8_t padding[1600]; /* multiple of 64 */
1299	} vmm;
1300
1301	/** HM part. */
1302	union
1303	{
1304	#ifdef VMM_INCLUDED_SRC_include_HMInternal_h
1305	struct HM s;
1306	#endif
1307	uint8_t padding[5504]; /* multiple of 64 */
1308	} hm;
1309
1310	/** TRPM part. */
1311	union
1312	{
1313	#ifdef VMM_INCLUDED_SRC_include_TRPMInternal_h
1314	struct TRPM s;
1315	#endif
1316	uint8_t padding[2048]; /* multiple of 64 */
1317	} trpm;
1318
1319	/** SELM part. */
1320	union
1321	{
1322	#ifdef VMM_INCLUDED_SRC_include_SELMInternal_h
1323	struct SELM s;
1324	#endif
1325	uint8_t padding[768]; /* multiple of 64 */
1326	} selm;
1327
1328	/** MM part. */
1329	union
1330	{
1331	#ifdef VMM_INCLUDED_SRC_include_MMInternal_h
1332	struct MM s;
1333	#endif
1334	uint8_t padding[192]; /* multiple of 64 */
1335	} mm;
1336
1337	/** PDM part. */
1338	union
1339	{
1340	#ifdef VMM_INCLUDED_SRC_include_PDMInternal_h
1341	struct PDM s;
1342	#endif
1343	uint8_t padding[22400]; /* multiple of 64 */
1344	} pdm;
1345
1346	/** IOM part. */
1347	union
1348	{
1349	#ifdef VMM_INCLUDED_SRC_include_IOMInternal_h
1350	struct IOM s;
1351	#endif
1352	uint8_t padding[1152]; /* multiple of 64 */
1353	} iom;
1354
1355	/** EM part. */
1356	union
1357	{
1358	#ifdef VMM_INCLUDED_SRC_include_EMInternal_h
1359	struct EM s;
1360	#endif
1361	uint8_t padding[256]; /* multiple of 64 */
1362	} em;
1363
1364	/** NEM part. */
1365	union
1366	{
1367	#ifdef VMM_INCLUDED_SRC_include_NEMInternal_h
1368	struct NEM s;
1369	#endif
1370	uint8_t padding[4608]; /* multiple of 64 */
1371	} nem;
1372
1373	/** TM part. */
1374	union
1375	{
1376	#ifdef VMM_INCLUDED_SRC_include_TMInternal_h
1377	struct TM s;
1378	#endif
1379	uint8_t padding[10112]; /* multiple of 64 */
1380	} tm;
1381
1382	/** DBGF part. */
1383	union
1384	{
1385	#ifdef VMM_INCLUDED_SRC_include_DBGFInternal_h
1386	struct DBGF s;
1387	#endif
1388	#ifdef VBOX_INCLUDED_vmm_dbgf_h
1389	/** Read only info exposed about interrupt breakpoints and selected events. */
1390	struct
1391	{
1392	/** Bitmap of enabled hardware interrupt breakpoints. */
1393	uint32_t bmHardIntBreakpoints[256 / 32];
1394	/** Bitmap of enabled software interrupt breakpoints. */
1395	uint32_t bmSoftIntBreakpoints[256 / 32];
1396	/** Bitmap of selected events.
1397	* This includes non-selectable events too for simplicity, we maintain the
1398	* state for some of these, as it may come in handy. */
1399	uint64_t bmSelectedEvents[(DBGFEVENT_END + 63) / 64];
1400	/** Enabled hardware interrupt breakpoints. */
1401	uint32_t cHardIntBreakpoints;
1402	/** Enabled software interrupt breakpoints. */
1403	uint32_t cSoftIntBreakpoints;
1404	/** The number of selected events. */
1405	uint32_t cSelectedEvents;
1406	/** The number of enabled hardware breakpoints. */
1407	uint8_t cEnabledHwBreakpoints;
1408	/** The number of enabled hardware I/O breakpoints. */
1409	uint8_t cEnabledHwIoBreakpoints;
1410	uint8_t au8Alignment1[2]; /*< Alignment padding. /
1411	/** The number of enabled INT3 breakpoints. */
1412	uint32_t volatile cEnabledInt3Breakpoints;
1413	} const ro;
1414	#endif
1415	uint8_t padding[2432]; /* multiple of 64 */
1416	} dbgf;
1417
1418	/** SSM part. */
1419	union
1420	{
1421	#ifdef VMM_INCLUDED_SRC_include_SSMInternal_h
1422	struct SSM s;
1423	#endif
1424	uint8_t padding[128]; /* multiple of 64 */
1425	} ssm;
1426
1427	union
1428	{
1429	#ifdef VMM_INCLUDED_SRC_include_GIMInternal_h
1430	struct GIM s;
1431	#endif
1432	uint8_t padding[448]; /* multiple of 64 */
1433	} gim;
1434
1435	union
1436	{
1437	#ifdef VMM_INCLUDED_SRC_include_APICInternal_h
1438	struct APIC s;
1439	#endif
1440	uint8_t padding[128]; /* multiple of 8 */
1441	} apic;
1442
1443	/* ---- begin small stuff ---- */
1444
1445	/** VM part. */
1446	union
1447	{
1448	#ifdef VMM_INCLUDED_SRC_include_VMInternal_h
1449	struct VMINT s;
1450	#endif
1451	uint8_t padding[32]; /* multiple of 8 */
1452	} vm;
1453
1454	/** CFGM part. */
1455	union
1456	{
1457	#ifdef VMM_INCLUDED_SRC_include_CFGMInternal_h
1458	struct CFGM s;
1459	#endif
1460	uint8_t padding[8]; /* multiple of 8 */
1461	} cfgm;
1462
1463	/** IEM part. */
1464	union
1465	{
1466	#ifdef VMM_INCLUDED_SRC_include_IEMInternal_h
1467	struct IEM s;
1468	#endif
1469	uint8_t padding[16]; /* multiple of 8 */
1470	} iem;
1471
1472	/** Statistics for ring-0 only components. */
1473	struct
1474	{
1475	/** GMMR0 stats. */
1476	struct
1477	{
1478	/** Chunk TLB hits. */
1479	uint64_t cChunkTlbHits;
1480	/** Chunk TLB misses. */
1481	uint64_t cChunkTlbMisses;
1482	} gmm;
1483	uint64_t au64Padding[6]; /* probably more comming here... */
1484	} R0Stats;
1485
1486	union
1487	{
1488	#ifdef VMM_INCLUDED_SRC_include_GCMInternal_h
1489	struct GCM s;
1490	#endif
1491	uint8_t padding[32]; /* multiple of 8 */
1492	} gcm;
1493
1494	/** Padding for aligning the structure size on a page boundrary. */
1495	uint8_t abAlignment2[8872 - sizeof(PVMCPUR3) * VMM_MAX_CPU_COUNT];
1496
1497	/* ---- end small stuff ---- */
1498
1499	/** Array of VMCPU ring-3 pointers. */
1500	PVMCPUR3 apCpusR3[VMM_MAX_CPU_COUNT];
1501
1502	/* This point is aligned on a 16384 boundrary (for arm64 purposes). */
1503	} VM;
1504	#ifndef VBOX_FOR_DTRACE_LIB
1505	//AssertCompileSizeAlignment(VM, 16384);
1506	#endif
1507
1508
1509	#ifdef IN_RC
1510	RT_C_DECLS_BEGIN
1511
1512	/** The VM structure.
1513	* This is imported from the VMMRCBuiltin module, i.e. it's a one of those magic
1514	* globals which we should avoid using.
1515	*/
1516	extern DECLIMPORT(VM) g_VM;
1517
1518	/** The VMCPU structure for virtual CPU \#0.
1519	* This is imported from the VMMRCBuiltin module, i.e. it's a one of those magic
1520	* globals which we should avoid using.
1521	*/
1522	extern DECLIMPORT(VMCPU) g_VCpu0;
1523
1524	RT_C_DECLS_END
1525	#endif
1526
1527	/** @} */
1528
1529	#endif /* !VBOX_INCLUDED_vmm_vm_h */
1530

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source: vbox/trunk/include/VBox/vmm/vm.h@ 98122

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