x86.h@ 18189

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1	/** @file
2	* X86 (and AMD64) Structures and Definitions.
3	*/
4
5	/*
6	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
7	*
8	* This file is part of VirtualBox Open Source Edition (OSE), as
9	* available from http://www.virtualbox.org. This file is free software;
10	* you can redistribute it and/or modify it under the terms of the GNU
11	* General Public License (GPL) as published by the Free Software
12	* Foundation, in version 2 as it comes in the "COPYING" file of the
13	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15	*
16	* The contents of this file may alternatively be used under the terms
17	* of the Common Development and Distribution License Version 1.0
18	* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19	* VirtualBox OSE distribution, in which case the provisions of the
20	* CDDL are applicable instead of those of the GPL.
21	*
22	* You may elect to license modified versions of this file under the
23	* terms and conditions of either the GPL or the CDDL or both.
24	*
25	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
26	* Clara, CA 95054 USA or visit http://www.sun.com if you need
27	* additional information or have any questions.
28	*/
29
30	/*
31	* x86.mac is generated from this file using:
32	* sed -e '/__VBox_x86_h__/d' -e '/#define/!d' -e 's/#define/%define/' include/VBox/x86.h
33	*/
34
35	#ifndef ___VBox_x86_h
36	#define ___VBox_x86_h
37
38	#include <VBox/types.h>
39	#include <iprt/assert.h>
40
41	/* Workaround for Solaris sys/regset.h defining CS, DS */
42	#if defined(RT_OS_SOLARIS)
43	# undef CS
44	# undef DS
45	#endif
46
47	/** @defgroup grp_x86 x86 Types and Definitions
48	* @{
49	*/
50
51	/**
52	* EFLAGS Bits.
53	*/
54	typedef struct X86EFLAGSBITS
55	{
56	/** Bit 0 - CF - Carry flag - Status flag. */
57	unsigned u1CF : 1;
58	/** Bit 1 - 1 - Reserved flag. */
59	unsigned u1Reserved0 : 1;
60	/** Bit 2 - PF - Parity flag - Status flag. */
61	unsigned u1PF : 1;
62	/** Bit 3 - 0 - Reserved flag. */
63	unsigned u1Reserved1 : 1;
64	/** Bit 4 - AF - Auxiliary carry flag - Status flag. */
65	unsigned u1AF : 1;
66	/** Bit 5 - 0 - Reserved flag. */
67	unsigned u1Reserved2 : 1;
68	/** Bit 6 - ZF - Zero flag - Status flag. */
69	unsigned u1ZF : 1;
70	/** Bit 7 - SF - Signed flag - Status flag. */
71	unsigned u1SF : 1;
72	/** Bit 8 - TF - Trap flag - System flag. */
73	unsigned u1TF : 1;
74	/** Bit 9 - IF - Interrupt flag - System flag. */
75	unsigned u1IF : 1;
76	/** Bit 10 - DF - Direction flag - Control flag. */
77	unsigned u1DF : 1;
78	/** Bit 11 - OF - Overflow flag - Status flag. */
79	unsigned u1OF : 1;
80	/** Bit 12-13 - IOPL - I/O prvilege level flag - System flag. */
81	unsigned u2IOPL : 2;
82	/** Bit 14 - NT - Nested task flag - System flag. */
83	unsigned u1NT : 1;
84	/** Bit 15 - 0 - Reserved flag. */
85	unsigned u1Reserved3 : 1;
86	/** Bit 16 - RF - Resume flag - System flag. */
87	unsigned u1RF : 1;
88	/** Bit 17 - VM - Virtual 8086 mode - System flag. */
89	unsigned u1VM : 1;
90	/** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
91	unsigned u1AC : 1;
92	/** Bit 19 - VIF - Virtual interupt flag - System flag. */
93	unsigned u1VIF : 1;
94	/** Bit 20 - VIP - Virtual interupt pending flag - System flag. */
95	unsigned u1VIP : 1;
96	/** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
97	unsigned u1ID : 1;
98	/** Bit 22-31 - 0 - Reserved flag. */
99	unsigned u10Reserved4 : 10;
100	} X86EFLAGSBITS;
101	/** Pointer to EFLAGS bits. */
102	typedef X86EFLAGSBITS *PX86EFLAGSBITS;
103	/** Pointer to const EFLAGS bits. */
104	typedef const X86EFLAGSBITS *PCX86EFLAGSBITS;
105
106	/**
107	* EFLAGS.
108	*/
109	typedef union X86EFLAGS
110	{
111	/** The plain unsigned view. */
112	uint32_t u;
113	/** The bitfield view. */
114	X86EFLAGSBITS Bits;
115	/** The 8-bit view. */
116	uint8_t au8[4];
117	/** The 16-bit view. */
118	uint16_t au16[2];
119	/** The 32-bit view. */
120	uint32_t au32[1];
121	/** The 32-bit view. */
122	uint32_t u32;
123	} X86EFLAGS;
124	/** Pointer to EFLAGS. */
125	typedef X86EFLAGS *PX86EFLAGS;
126	/** Pointer to const EFLAGS. */
127	typedef const X86EFLAGS *PCX86EFLAGS;
128
129	/**
130	* RFLAGS (32 upper bits are reserved).
131	*/
132	typedef union X86RFLAGS
133	{
134	/** The plain unsigned view. */
135	uint64_t u;
136	/** The bitfield view. */
137	X86EFLAGSBITS Bits;
138	/** The 8-bit view. */
139	uint8_t au8[8];
140	/** The 16-bit view. */
141	uint16_t au16[4];
142	/** The 32-bit view. */
143	uint32_t au32[2];
144	/** The 64-bit view. */
145	uint64_t au64[1];
146	/** The 64-bit view. */
147	uint64_t u64;
148	} X86RFLAGS;
149	/** Pointer to RFLAGS. */
150	typedef X86RFLAGS *PX86RFLAGS;
151	/** Pointer to const RFLAGS. */
152	typedef const X86RFLAGS *PCX86RFLAGS;
153
154
155	/** @name EFLAGS
156	* @{
157	*/
158	/** Bit 0 - CF - Carry flag - Status flag. */
159	#define X86_EFL_CF RT_BIT(0)
160	/** Bit 2 - PF - Parity flag - Status flag. */
161	#define X86_EFL_PF RT_BIT(2)
162	/** Bit 4 - AF - Auxiliary carry flag - Status flag. */
163	#define X86_EFL_AF RT_BIT(4)
164	/** Bit 6 - ZF - Zero flag - Status flag. */
165	#define X86_EFL_ZF RT_BIT(6)
166	/** Bit 7 - SF - Signed flag - Status flag. */
167	#define X86_EFL_SF RT_BIT(7)
168	/** Bit 8 - TF - Trap flag - System flag. */
169	#define X86_EFL_TF RT_BIT(8)
170	/** Bit 9 - IF - Interrupt flag - System flag. */
171	#define X86_EFL_IF RT_BIT(9)
172	/** Bit 10 - DF - Direction flag - Control flag. */
173	#define X86_EFL_DF RT_BIT(10)
174	/** Bit 11 - OF - Overflow flag - Status flag. */
175	#define X86_EFL_OF RT_BIT(11)
176	/** Bit 12-13 - IOPL - I/O prvilege level flag - System flag. */
177	#define X86_EFL_IOPL (RT_BIT(12) \| RT_BIT(13))
178	/** Bit 14 - NT - Nested task flag - System flag. */
179	#define X86_EFL_NT RT_BIT(14)
180	/** Bit 16 - RF - Resume flag - System flag. */
181	#define X86_EFL_RF RT_BIT(16)
182	/** Bit 17 - VM - Virtual 8086 mode - System flag. */
183	#define X86_EFL_VM RT_BIT(17)
184	/** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
185	#define X86_EFL_AC RT_BIT(18)
186	/** Bit 19 - VIF - Virtual interupt flag - System flag. */
187	#define X86_EFL_VIF RT_BIT(19)
188	/** Bit 20 - VIP - Virtual interupt pending flag - System flag. */
189	#define X86_EFL_VIP RT_BIT(20)
190	/** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
191	#define X86_EFL_ID RT_BIT(21)
192	/** IOPL shift. */
193	#define X86_EFL_IOPL_SHIFT 12
194	/** The the IOPL level from the flags. */
195	#define X86_EFL_GET_IOPL(efl) (((efl) >> X86_EFL_IOPL_SHIFT) & 3)
196	/** Bits restored by popf */
197	#define X86_EFL_POPF_BITS (X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_TF \| X86_EFL_IF \| X86_EFL_DF \| X86_EFL_OF \| X86_EFL_IOPL \| X86_EFL_NT \| X86_EFL_AC \| X86_EFL_ID)
198	/** @} */
199
200
201	/** CPUID Feature information - ECX.
202	* CPUID query with EAX=1.
203	*/
204	typedef struct X86CPUIDFEATECX
205	{
206	/** Bit 0 - SSE3 - Supports SSE3 or not. */
207	unsigned u1SSE3 : 1;
208	/** Reserved. */
209	unsigned u2Reserved1 : 2;
210	/** Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
211	unsigned u1Monitor : 1;
212	/** Bit 4 - CPL-DS - CPL Qualified Debug Store. */
213	unsigned u1CPLDS : 1;
214	/** Bit 5 - VMX - Virtual Machine Technology. */
215	unsigned u1VMX : 1;
216	/** Reserved. */
217	unsigned u1Reserved2 : 1;
218	/** Bit 7 - EST - Enh. SpeedStep Tech. */
219	unsigned u1EST : 1;
220	/** Bit 8 - TM2 - Terminal Monitor 2. */
221	unsigned u1TM2 : 1;
222	/** Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
223	unsigned u1SSSE3 : 1;
224	/** Bit 10 - CNTX-ID - L1 Context ID. */
225	unsigned u1CNTXID : 1;
226	/** Reserved. */
227	unsigned u2Reserved4 : 2;
228	/** Bit 13 - CX16 - CMPXCHG16B. */
229	unsigned u1CX16 : 1;
230	/** Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
231	unsigned u1TPRUpdate : 1;
232	/** Reserved. */
233	unsigned u17Reserved5 : 17;
234
235	} X86CPUIDFEATECX;
236	/** Pointer to CPUID Feature Information - ECX. */
237	typedef X86CPUIDFEATECX *PX86CPUIDFEATECX;
238	/** Pointer to const CPUID Feature Information - ECX. */
239	typedef const X86CPUIDFEATECX *PCX86CPUIDFEATECX;
240
241
242	/** CPUID Feature Information - EDX.
243	* CPUID query with EAX=1.
244	*/
245	typedef struct X86CPUIDFEATEDX
246	{
247	/** Bit 0 - FPU - x87 FPU on Chip. */
248	unsigned u1FPU : 1;
249	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
250	unsigned u1VME : 1;
251	/** Bit 2 - DE - Debugging extensions. */
252	unsigned u1DE : 1;
253	/** Bit 3 - PSE - Page Size Extension. */
254	unsigned u1PSE : 1;
255	/** Bit 4 - TSC - Time Stamp Counter. */
256	unsigned u1TSC : 1;
257	/** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
258	unsigned u1MSR : 1;
259	/** Bit 6 - PAE - Physical Address Extension. */
260	unsigned u1PAE : 1;
261	/** Bit 7 - MCE - Machine Check Exception. */
262	unsigned u1MCE : 1;
263	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
264	unsigned u1CX8 : 1;
265	/** Bit 9 - APIC - APIC On-Chip. */
266	unsigned u1APIC : 1;
267	/** Bit 10 - Reserved. */
268	unsigned u1Reserved1 : 1;
269	/** Bit 11 - SEP - SYSENTER and SYSEXIT. */
270	unsigned u1SEP : 1;
271	/** Bit 12 - MTRR - Memory Type Range Registers. */
272	unsigned u1MTRR : 1;
273	/** Bit 13 - PGE - PTE Global Bit. */
274	unsigned u1PGE : 1;
275	/** Bit 14 - MCA - Machine Check Architecture. */
276	unsigned u1MCA : 1;
277	/** Bit 15 - CMOV - Conditional Move Instructions. */
278	unsigned u1CMOV : 1;
279	/** Bit 16 - PAT - Page Attribute Table. */
280	unsigned u1PAT : 1;
281	/** Bit 17 - PSE-36 - 36-bit Page Size Extention. */
282	unsigned u1PSE36 : 1;
283	/** Bit 18 - PSN - Processor Serial Number. */
284	unsigned u1PSN : 1;
285	/** Bit 19 - CLFSH - CLFLUSH Instruction. */
286	unsigned u1CLFSH : 1;
287	/** Bit 20 - Reserved. */
288	unsigned u1Reserved2 : 1;
289	/** Bit 21 - DS - Debug Store. */
290	unsigned u1DS : 1;
291	/** Bit 22 - ACPI - Thermal Monitor and Software Controlled Clock Facilities. */
292	unsigned u1ACPI : 1;
293	/** Bit 23 - MMX - Intel MMX 'Technology'. */
294	unsigned u1MMX : 1;
295	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
296	unsigned u1FXSR : 1;
297	/** Bit 25 - SSE - SSE Support. */
298	unsigned u1SSE : 1;
299	/** Bit 26 - SSE2 - SSE2 Support. */
300	unsigned u1SSE2 : 1;
301	/** Bit 27 - SS - Self Snoop. */
302	unsigned u1SS : 1;
303	/** Bit 28 - HTT - Hyper-Threading Technology. */
304	unsigned u1HTT : 1;
305	/** Bit 29 - TM - Thermal Monitor. */
306	unsigned u1TM : 1;
307	/** Bit 30 - Reserved - . */
308	unsigned u1Reserved3 : 1;
309	/** Bit 31 - PBE - Pending Break Enabled. */
310	unsigned u1PBE : 1;
311	} X86CPUIDFEATEDX;
312	/** Pointer to CPUID Feature Information - EDX. */
313	typedef X86CPUIDFEATEDX *PX86CPUIDFEATEDX;
314	/** Pointer to const CPUID Feature Information - EDX. */
315	typedef const X86CPUIDFEATEDX *PCX86CPUIDFEATEDX;
316
317	/** @name CPUID Vendor information.
318	* CPUID query with EAX=0.
319	* @{
320	*/
321	#define X86_CPUID_VENDOR_INTEL_EBX 0x756e6547 /* Genu */
322	#define X86_CPUID_VENDOR_INTEL_ECX 0x6c65746e /* ntel */
323	#define X86_CPUID_VENDOR_INTEL_EDX 0x49656e69 /* ineI */
324
325	#define X86_CPUID_VENDOR_AMD_EBX 0x68747541 /* Auth */
326	#define X86_CPUID_VENDOR_AMD_ECX 0x444d4163 /* cAMD */
327	#define X86_CPUID_VENDOR_AMD_EDX 0x69746e65 /* enti */
328	/** @} */
329
330
331	/** @name CPUID Feature information.
332	* CPUID query with EAX=1.
333	* @{
334	*/
335	/** ECX Bit 0 - SSE3 - Supports SSE3 or not. */
336	#define X86_CPUID_FEATURE_ECX_SSE3 RT_BIT(0)
337	/** ECX Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
338	#define X86_CPUID_FEATURE_ECX_MONITOR RT_BIT(3)
339	/** ECX Bit 4 - CPL-DS - CPL Qualified Debug Store. */
340	#define X86_CPUID_FEATURE_ECX_CPLDS RT_BIT(4)
341	/** ECX Bit 5 - VMX - Virtual Machine Technology. */
342	#define X86_CPUID_FEATURE_ECX_VMX RT_BIT(5)
343	/** ECX Bit 7 - EST - Enh. SpeedStep Tech. */
344	#define X86_CPUID_FEATURE_ECX_EST RT_BIT(7)
345	/** ECX Bit 8 - TM2 - Terminal Monitor 2. */
346	#define X86_CPUID_FEATURE_ECX_TM2 RT_BIT(8)
347	/** ECX Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
348	#define X86_CPUID_FEATURE_ECX_SSSE3 RT_BIT(9)
349	/** ECX Bit 10 - CNTX-ID - L1 Context ID. */
350	#define X86_CPUID_FEATURE_ECX_CNTXID RT_BIT(10)
351	/** ECX Bit 13 - CX16 - CMPXCHG16B. */
352	#define X86_CPUID_FEATURE_ECX_CX16 RT_BIT(13)
353	/** ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
354	#define X86_CPUID_FEATURE_ECX_TPRUPDATE RT_BIT(14)
355	/** ECX Bit 21 - x2APIC support. */
356	#define X86_CPUID_FEATURE_ECX_X2APIC RT_BIT(21)
357	/** ECX Bit 23 - POPCOUNT instruction. */
358	#define X86_CPUID_FEATURE_ECX_POPCOUNT RT_BIT(23)
359
360
361	/** Bit 0 - FPU - x87 FPU on Chip. */
362	#define X86_CPUID_FEATURE_EDX_FPU RT_BIT(0)
363	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
364	#define X86_CPUID_FEATURE_EDX_VME RT_BIT(1)
365	/** Bit 2 - DE - Debugging extensions. */
366	#define X86_CPUID_FEATURE_EDX_DE RT_BIT(2)
367	/** Bit 3 - PSE - Page Size Extension. */
368	#define X86_CPUID_FEATURE_EDX_PSE RT_BIT(3)
369	/** Bit 4 - TSC - Time Stamp Counter. */
370	#define X86_CPUID_FEATURE_EDX_TSC RT_BIT(4)
371	/** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
372	#define X86_CPUID_FEATURE_EDX_MSR RT_BIT(5)
373	/** Bit 6 - PAE - Physical Address Extension. */
374	#define X86_CPUID_FEATURE_EDX_PAE RT_BIT(6)
375	/** Bit 7 - MCE - Machine Check Exception. */
376	#define X86_CPUID_FEATURE_EDX_MCE RT_BIT(7)
377	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
378	#define X86_CPUID_FEATURE_EDX_CX8 RT_BIT(8)
379	/** Bit 9 - APIC - APIC On-Chip. */
380	#define X86_CPUID_FEATURE_EDX_APIC RT_BIT(9)
381	/** Bit 11 - SEP - SYSENTER and SYSEXIT. */
382	#define X86_CPUID_FEATURE_EDX_SEP RT_BIT(11)
383	/** Bit 12 - MTRR - Memory Type Range Registers. */
384	#define X86_CPUID_FEATURE_EDX_MTRR RT_BIT(12)
385	/** Bit 13 - PGE - PTE Global Bit. */
386	#define X86_CPUID_FEATURE_EDX_PGE RT_BIT(13)
387	/** Bit 14 - MCA - Machine Check Architecture. */
388	#define X86_CPUID_FEATURE_EDX_MCA RT_BIT(14)
389	/** Bit 15 - CMOV - Conditional Move Instructions. */
390	#define X86_CPUID_FEATURE_EDX_CMOV RT_BIT(15)
391	/** Bit 16 - PAT - Page Attribute Table. */
392	#define X86_CPUID_FEATURE_EDX_PAT RT_BIT(16)
393	/** Bit 17 - PSE-36 - 36-bit Page Size Extention. */
394	#define X86_CPUID_FEATURE_EDX_PSE36 RT_BIT(17)
395	/** Bit 18 - PSN - Processor Serial Number. */
396	#define X86_CPUID_FEATURE_EDX_PSN RT_BIT(18)
397	/** Bit 19 - CLFSH - CLFLUSH Instruction. */
398	#define X86_CPUID_FEATURE_EDX_CLFSH RT_BIT(19)
399	/** Bit 21 - DS - Debug Store. */
400	#define X86_CPUID_FEATURE_EDX_DS RT_BIT(21)
401	/** Bit 22 - ACPI - Termal Monitor and Software Controlled Clock Facilities. */
402	#define X86_CPUID_FEATURE_EDX_ACPI RT_BIT(22)
403	/** Bit 23 - MMX - Intel MMX Technology. */
404	#define X86_CPUID_FEATURE_EDX_MMX RT_BIT(23)
405	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
406	#define X86_CPUID_FEATURE_EDX_FXSR RT_BIT(24)
407	/** Bit 25 - SSE - SSE Support. */
408	#define X86_CPUID_FEATURE_EDX_SSE RT_BIT(25)
409	/** Bit 26 - SSE2 - SSE2 Support. */
410	#define X86_CPUID_FEATURE_EDX_SSE2 RT_BIT(26)
411	/** Bit 27 - SS - Self Snoop. */
412	#define X86_CPUID_FEATURE_EDX_SS RT_BIT(27)
413	/** Bit 28 - HTT - Hyper-Threading Technology. */
414	#define X86_CPUID_FEATURE_EDX_HTT RT_BIT(28)
415	/** Bit 29 - TM - Therm. Monitor. */
416	#define X86_CPUID_FEATURE_EDX_TM RT_BIT(29)
417	/** Bit 31 - PBE - Pending Break Enabled. */
418	#define X86_CPUID_FEATURE_EDX_PBE RT_BIT(31)
419	/** @} */
420
421
422	/** @name CPUID AMD Feature information.
423	* CPUID query with EAX=0x80000001.
424	* @{
425	*/
426	/** Bit 0 - FPU - x87 FPU on Chip. */
427	#define X86_CPUID_AMD_FEATURE_EDX_FPU RT_BIT(0)
428	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
429	#define X86_CPUID_AMD_FEATURE_EDX_VME RT_BIT(1)
430	/** Bit 2 - DE - Debugging extensions. */
431	#define X86_CPUID_AMD_FEATURE_EDX_DE RT_BIT(2)
432	/** Bit 3 - PSE - Page Size Extension. */
433	#define X86_CPUID_AMD_FEATURE_EDX_PSE RT_BIT(3)
434	/** Bit 4 - TSC - Time Stamp Counter. */
435	#define X86_CPUID_AMD_FEATURE_EDX_TSC RT_BIT(4)
436	/** Bit 5 - MSR - K86 Model Specific Registers RDMSR and WRMSR Instructions. */
437	#define X86_CPUID_AMD_FEATURE_EDX_MSR RT_BIT(5)
438	/** Bit 6 - PAE - Physical Address Extension. */
439	#define X86_CPUID_AMD_FEATURE_EDX_PAE RT_BIT(6)
440	/** Bit 7 - MCE - Machine Check Exception. */
441	#define X86_CPUID_AMD_FEATURE_EDX_MCE RT_BIT(7)
442	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
443	#define X86_CPUID_AMD_FEATURE_EDX_CX8 RT_BIT(8)
444	/** Bit 9 - APIC - APIC On-Chip. */
445	#define X86_CPUID_AMD_FEATURE_EDX_APIC RT_BIT(9)
446	/** Bit 11 - SEP - AMD SYSCALL and SYSRET. */
447	#define X86_CPUID_AMD_FEATURE_EDX_SEP RT_BIT(11)
448	/** Bit 12 - MTRR - Memory Type Range Registers. */
449	#define X86_CPUID_AMD_FEATURE_EDX_MTRR RT_BIT(12)
450	/** Bit 13 - PGE - PTE Global Bit. */
451	#define X86_CPUID_AMD_FEATURE_EDX_PGE RT_BIT(13)
452	/** Bit 14 - MCA - Machine Check Architecture. */
453	#define X86_CPUID_AMD_FEATURE_EDX_MCA RT_BIT(14)
454	/** Bit 15 - CMOV - Conditional Move Instructions. */
455	#define X86_CPUID_AMD_FEATURE_EDX_CMOV RT_BIT(15)
456	/** Bit 16 - PAT - Page Attribute Table. */
457	#define X86_CPUID_AMD_FEATURE_EDX_PAT RT_BIT(16)
458	/** Bit 17 - PSE-36 - 36-bit Page Size Extention. */
459	#define X86_CPUID_AMD_FEATURE_EDX_PSE36 RT_BIT(17)
460	/** Bit 20 - NX - AMD No-Execute Page Protection. */
461	#define X86_CPUID_AMD_FEATURE_EDX_NX RT_BIT(20)
462	/** Bit 22 - AXMMX - AMD Extensions to MMX Instructions. */
463	#define X86_CPUID_AMD_FEATURE_EDX_AXMMX RT_BIT(22)
464	/** Bit 23 - MMX - Intel MMX Technology. */
465	#define X86_CPUID_AMD_FEATURE_EDX_MMX RT_BIT(23)
466	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
467	#define X86_CPUID_AMD_FEATURE_EDX_FXSR RT_BIT(24)
468	/** Bit 25 - FFXSR - AMD fast FXSAVE and FXRSTOR Instructions. */
469	#define X86_CPUID_AMD_FEATURE_EDX_FFXSR RT_BIT(25)
470	/** Bit 26 - PAGE1GB - AMD 1GB large page support. */
471	#define X86_CPUID_AMD_FEATURE_EDX_PAGE1GB RT_BIT(26)
472	/** Bit 27 - RDTSCP - AMD RDTSCP instruction. */
473	#define X86_CPUID_AMD_FEATURE_EDX_RDTSCP RT_BIT(27)
474	/** Bit 29 - LM - AMD Long Mode. */
475	#define X86_CPUID_AMD_FEATURE_EDX_LONG_MODE RT_BIT(29)
476	/** Bit 30 - 3DNOWEXT - AMD Extensions to 3DNow. */
477	#define X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX RT_BIT(30)
478	/** Bit 31 - 3DNOW - AMD 3DNow. */
479	#define X86_CPUID_AMD_FEATURE_EDX_3DNOW RT_BIT(31)
480
481	/** Bit 0 - LAHF/SAHF - AMD LAHF and SAHF in 64-bit mode. */
482	#define X86_CPUID_AMD_FEATURE_ECX_LAHF_SAHF RT_BIT(0)
483	/** Bit 1 - CMPL - Core multi-processing legacy mode. */
484	#define X86_CPUID_AMD_FEATURE_ECX_CMPL RT_BIT(1)
485	/** Bit 2 - SVM - AMD VM extensions. */
486	#define X86_CPUID_AMD_FEATURE_ECX_SVM RT_BIT(2)
487	/** Bit 3 - EXTAPIC - AMD extended APIC registers starting at 0x400. */
488	#define X86_CPUID_AMD_FEATURE_ECX_EXT_APIC RT_BIT(3)
489	/** Bit 4 - CR8L - AMD LOCK MOV CR0 means MOV CR8. */
490	#define X86_CPUID_AMD_FEATURE_ECX_CR8L RT_BIT(4)
491	/** Bit 5 - ABM - AMD Advanced bit manipulation. LZCNT instruction support. */
492	#define X86_CPUID_AMD_FEATURE_ECX_ABM RT_BIT(5)
493	/** Bit 6 - SSE4A - AMD EXTRQ, INSERTQ, MOVNTSS, and MOVNTSD instruction support. */
494	#define X86_CPUID_AMD_FEATURE_ECX_SSE4A RT_BIT(6)
495	/** Bit 7 - MISALIGNSSE - AMD Misaligned SSE mode. */
496	#define X86_CPUID_AMD_FEATURE_ECX_MISALNSSE RT_BIT(7)
497	/** Bit 8 - 3DNOWPRF - AMD PREFETCH and PREFETCHW instruction support. */
498	#define X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF RT_BIT(8)
499	/** Bit 9 - OSVW - AMD OS visible workaround. */
500	#define X86_CPUID_AMD_FEATURE_ECX_OSVW RT_BIT(9)
501	/** Bit 12 - SKINIT - AMD SKINIT: SKINIT, STGI, and DEV support. */
502	#define X86_CPUID_AMD_FEATURE_ECX_SKINIT RT_BIT(12)
503	/** Bit 13 - WDT - AMD Watchdog timer support. */
504	#define X86_CPUID_AMD_FEATURE_ECX_WDT RT_BIT(13)
505
506	/** @} */
507
508
509	/** @name CPUID AMD Feature information.
510	* CPUID query with EAX=0x80000007.
511	* @{
512	*/
513	/** Bit 0 - TS - Temperature Sensor. */
514	#define X86_CPUID_AMD_ADVPOWER_EDX_TS RT_BIT(0)
515	/** Bit 1 - FID - Frequency ID Control. */
516	#define X86_CPUID_AMD_ADVPOWER_EDX_FID RT_BIT(1)
517	/** Bit 2 - VID - Voltage ID Control. */
518	#define X86_CPUID_AMD_ADVPOWER_EDX_VID RT_BIT(2)
519	/** Bit 3 - TTP - THERMTRIP. */
520	#define X86_CPUID_AMD_ADVPOWER_EDX_TTP RT_BIT(3)
521	/** Bit 4 - TM - Hardware Thermal Control. */
522	#define X86_CPUID_AMD_ADVPOWER_EDX_TM RT_BIT(4)
523	/** Bit 5 - STC - Software Thermal Control. */
524	#define X86_CPUID_AMD_ADVPOWER_EDX_STC RT_BIT(5)
525	/** Bit 6 - MC - 100 Mhz Multiplier Control. */
526	#define X86_CPUID_AMD_ADVPOWER_EDX_MC RT_BIT(6)
527	/** Bit 7 - HWPSTATE - Hardware P-State Control. */
528	#define X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE RT_BIT(7)
529	/** Bit 8 - TSCINVAR - TSC Invariant. */
530	#define X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR RT_BIT(8)
531	/** @} */
532
533
534	/** @name CR0
535	* @{ */
536	/** Bit 0 - PE - Protection Enabled */
537	#define X86_CR0_PE RT_BIT(0)
538	#define X86_CR0_PROTECTION_ENABLE RT_BIT(0)
539	/** Bit 1 - MP - Monitor Coprocessor */
540	#define X86_CR0_MP RT_BIT(1)
541	#define X86_CR0_MONITOR_COPROCESSOR RT_BIT(1)
542	/** Bit 2 - EM - Emulation. */
543	#define X86_CR0_EM RT_BIT(2)
544	#define X86_CR0_EMULATE_FPU RT_BIT(2)
545	/** Bit 3 - TS - Task Switch. */
546	#define X86_CR0_TS RT_BIT(3)
547	#define X86_CR0_TASK_SWITCH RT_BIT(3)
548	/** Bit 4 - ET - Extension flag. ('hardcoded' to 1) */
549	#define X86_CR0_ET RT_BIT(4)
550	#define X86_CR0_EXTENSION_TYPE RT_BIT(4)
551	/** Bit 5 - NE - Numeric error. */
552	#define X86_CR0_NE RT_BIT(5)
553	#define X86_CR0_NUMERIC_ERROR RT_BIT(5)
554	/** Bit 16 - WP - Write Protect. */
555	#define X86_CR0_WP RT_BIT(16)
556	#define X86_CR0_WRITE_PROTECT RT_BIT(16)
557	/** Bit 18 - AM - Alignment Mask. */
558	#define X86_CR0_AM RT_BIT(18)
559	#define X86_CR0_ALIGMENT_MASK RT_BIT(18)
560	/** Bit 29 - NW - Not Write-though. */
561	#define X86_CR0_NW RT_BIT(29)
562	#define X86_CR0_NOT_WRITE_THROUGH RT_BIT(29)
563	/** Bit 30 - WP - Cache Disable. */
564	#define X86_CR0_CD RT_BIT(30)
565	#define X86_CR0_CACHE_DISABLE RT_BIT(30)
566	/** Bit 31 - PG - Paging. */
567	#define X86_CR0_PG RT_BIT(31)
568	#define X86_CR0_PAGING RT_BIT(31)
569	/** @} */
570
571
572	/** @name CR3
573	* @{ */
574	/** Bit 3 - PWT - Page-level Writes Transparent. */
575	#define X86_CR3_PWT RT_BIT(3)
576	/** Bit 4 - PCD - Page-level Cache Disable. */
577	#define X86_CR3_PCD RT_BIT(4)
578	/** Bits 12-31 - - Page directory page number. */
579	#define X86_CR3_PAGE_MASK (0xfffff000)
580	/** Bits 5-31 - - PAE Page directory page number. */
581	#define X86_CR3_PAE_PAGE_MASK (0xffffffe0)
582	/** Bits 12-51 - - AMD64 Page directory page number. */
583	#define X86_CR3_AMD64_PAGE_MASK UINT64_C(0x000ffffffffff000)
584	/** @} */
585
586
587	/** @name CR4
588	* @{ */
589	/** Bit 0 - VME - Virtual-8086 Mode Extensions. */
590	#define X86_CR4_VME RT_BIT(0)
591	/** Bit 1 - PVI - Protected-Mode Virtual Interrupts. */
592	#define X86_CR4_PVI RT_BIT(1)
593	/** Bit 2 - TSD - Time Stamp Disable. */
594	#define X86_CR4_TSD RT_BIT(2)
595	/** Bit 3 - DE - Debugging Extensions. */
596	#define X86_CR4_DE RT_BIT(3)
597	/** Bit 4 - PSE - Page Size Extension. */
598	#define X86_CR4_PSE RT_BIT(4)
599	/** Bit 5 - PAE - Physical Address Extension. */
600	#define X86_CR4_PAE RT_BIT(5)
601	/** Bit 6 - MCE - Machine-Check Enable. */
602	#define X86_CR4_MCE RT_BIT(6)
603	/** Bit 7 - PGE - Page Global Enable. */
604	#define X86_CR4_PGE RT_BIT(7)
605	/** Bit 8 - PCE - Performance-Monitoring Counter Enable. */
606	#define X86_CR4_PCE RT_BIT(8)
607	/** Bit 9 - OSFSXR - Operating System Support for FXSAVE and FXRSTORE instruction. */
608	#define X86_CR4_OSFSXR RT_BIT(9)
609	/** Bit 10 - OSXMMEEXCPT - Operating System Support for Unmasked SIMD Floating-Point Exceptions. */
610	#define X86_CR4_OSXMMEEXCPT RT_BIT(10)
611	/** Bit 13 - VMXE - VMX mode is enabled. */
612	#define X86_CR4_VMXE RT_BIT(13)
613	/** @} */
614
615
616	/** @name DR6
617	* @{ */
618	/** Bit 0 - B0 - Breakpoint 0 condition detected. */
619	#define X86_DR6_B0 RT_BIT(0)
620	/** Bit 1 - B1 - Breakpoint 1 condition detected. */
621	#define X86_DR6_B1 RT_BIT(1)
622	/** Bit 2 - B2 - Breakpoint 2 condition detected. */
623	#define X86_DR6_B2 RT_BIT(2)
624	/** Bit 3 - B3 - Breakpoint 3 condition detected. */
625	#define X86_DR6_B3 RT_BIT(3)
626	/** Bit 13 - BD - Debug register access detected. Corresponds to the X86_DR7_GD bit. */
627	#define X86_DR6_BD RT_BIT(13)
628	/** Bit 14 - BS - Single step */
629	#define X86_DR6_BS RT_BIT(14)
630	/** Bit 15 - BT - Task switch. (TSS T bit.) */
631	#define X86_DR6_BT RT_BIT(15)
632	/** Value of DR6 after powerup/reset. */
633	#define X86_DR6_INIT_VAL UINT64_C(0xFFFF0FF0)
634	/** @} */
635
636
637	/** @name DR7
638	* @{ */
639	/** Bit 0 - L0 - Local breakpoint enable. Cleared on task switch. */
640	#define X86_DR7_L0 RT_BIT(0)
641	/** Bit 1 - G0 - Global breakpoint enable. Not cleared on task switch. */
642	#define X86_DR7_G0 RT_BIT(1)
643	/** Bit 2 - L1 - Local breakpoint enable. Cleared on task switch. */
644	#define X86_DR7_L1 RT_BIT(2)
645	/** Bit 3 - G1 - Global breakpoint enable. Not cleared on task switch. */
646	#define X86_DR7_G1 RT_BIT(3)
647	/** Bit 4 - L2 - Local breakpoint enable. Cleared on task switch. */
648	#define X86_DR7_L2 RT_BIT(4)
649	/** Bit 5 - G2 - Global breakpoint enable. Not cleared on task switch. */
650	#define X86_DR7_G2 RT_BIT(5)
651	/** Bit 6 - L3 - Local breakpoint enable. Cleared on task switch. */
652	#define X86_DR7_L3 RT_BIT(6)
653	/** Bit 7 - G3 - Global breakpoint enable. Not cleared on task switch. */
654	#define X86_DR7_G3 RT_BIT(7)
655	/** Bit 8 - LE - Local breakpoint exact. (Not supported (read ignored) by P6 and later.) */
656	#define X86_DR7_LE RT_BIT(8)
657	/** Bit 9 - GE - Local breakpoint exact. (Not supported (read ignored) by P6 and later.) */
658	#define X86_DR7_GE RT_BIT(9)
659
660	/** Bit 13 - GD - General detect enable. Enables emulators to get exceptions when
661	* any DR register is accessed. */
662	#define X86_DR7_GD RT_BIT(13)
663	/** Bit 16 & 17 - R/W0 - Read write field 0. Values X86_DR7_RW_. /
664	#define X86_DR7_RW0_MASK (3 << 16)
665	/** Bit 18 & 19 - LEN0 - Length field 0. Values X86_DR7_LEN_. /
666	#define X86_DR7_LEN0_MASK (3 << 18)
667	/** Bit 20 & 21 - R/W1 - Read write field 0. Values X86_DR7_RW_. /
668	#define X86_DR7_RW1_MASK (3 << 20)
669	/** Bit 22 & 23 - LEN1 - Length field 0. Values X86_DR7_LEN_. /
670	#define X86_DR7_LEN1_MASK (3 << 22)
671	/** Bit 24 & 25 - R/W2 - Read write field 0. Values X86_DR7_RW_. /
672	#define X86_DR7_RW2_MASK (3 << 24)
673	/** Bit 26 & 27 - LEN2 - Length field 0. Values X86_DR7_LEN_. /
674	#define X86_DR7_LEN2_MASK (3 << 26)
675	/** Bit 28 & 29 - R/W3 - Read write field 0. Values X86_DR7_RW_. /
676	#define X86_DR7_RW3_MASK (3 << 28)
677	/** Bit 30 & 31 - LEN3 - Length field 0. Values X86_DR7_LEN_. /
678	#define X86_DR7_LEN3_MASK (3 << 30)
679
680	/** Bits which must be 1s. */
681	#define X86_DR7_MB1_MASK (RT_BIT(10))
682
683	/** Calcs the L bit of Nth breakpoint.
684	* @param iBp The breakpoint number [0..3].
685	*/
686	#define X86_DR7_L(iBp) ( UINT32_C(1) << (iBp * 2) )
687
688	/** Calcs the G bit of Nth breakpoint.
689	* @param iBp The breakpoint number [0..3].
690	*/
691	#define X86_DR7_G(iBp) ( UINT32_C(1) << (iBp * 2 + 1) )
692
693	/** @name Read/Write values.
694	* @{ */
695	/** Break on instruction fetch only. */
696	#define X86_DR7_RW_EO 0U
697	/** Break on write only. */
698	#define X86_DR7_RW_WO 1U
699	/** Break on I/O read/write. This is only defined if CR4.DE is set. */
700	#define X86_DR7_RW_IO 2U
701	/** Break on read or write (but not instruction fetches). */
702	#define X86_DR7_RW_RW 3U
703	/** @} */
704
705	/** Shifts a X86_DR7_RW_* value to its right place.
706	* @param iBp The breakpoint number [0..3].
707	* @param fRw One of the X86_DR7_RW_* value.
708	*/
709	#define X86_DR7_RW(iBp, fRw) ( (fRw) << ((iBp) * 4 + 16) )
710
711	/** @name Length values.
712	* @{ */
713	#define X86_DR7_LEN_BYTE 0U
714	#define X86_DR7_LEN_WORD 1U
715	#define X86_DR7_LEN_QWORD 2U /*< AMD64 long mode only. /
716	#define X86_DR7_LEN_DWORD 3U
717	/** @} */
718
719	/** Shifts a X86_DR7_LEN_* value to its right place.
720	* @param iBp The breakpoint number [0..3].
721	* @param cb One of the X86_DR7_LEN_* values.
722	*/
723	#define X86_DR7_LEN(iBp, cb) ( (cb) << ((iBp) * 4 + 18) )
724
725	/** Fetch the breakpoint length bits from the DR7 value.
726	* @param uDR7 DR7 value
727	* @param iBp The breakpoint number [0..3].
728	*/
729	#define X86_DR7_GET_LEN(uDR7, iBp) ( ( (uDR7) >> ((iBp) * 4 + 18) ) & 0x3U)
730
731	/** Mask used to check if any breakpoints are enabled. */
732	#define X86_DR7_ENABLED_MASK (RT_BIT(0) \| RT_BIT(1) \| RT_BIT(2) \| RT_BIT(3) \| RT_BIT(4) \| RT_BIT(5) \| RT_BIT(6) \| RT_BIT(7))
733
734	/** Mask used to check if any io breakpoints are set. */
735	#define X86_DR7_IO_ENABLED_MASK (X86_DR7_RW(0, X86_DR7_RW_IO) \| X86_DR7_RW(1, X86_DR7_RW_IO) \| X86_DR7_RW(2, X86_DR7_RW_IO) \| X86_DR7_RW(3, X86_DR7_RW_IO))
736
737	/** Value of DR7 after powerup/reset. */
738	#define X86_DR7_INIT_VAL 0x400
739	/** @} */
740
741
742	/** @name Machine Specific Registers
743	* @{
744	*/
745
746	/** Time Stamp Counter. */
747	#define MSR_IA32_TSC 0x10
748
749	#define MSR_IA32_PLATFORM_ID 0x17
750
751	#ifndef MSR_IA32_APICBASE /* qemu cpu.h klugde */
752	#define MSR_IA32_APICBASE 0x1b
753	#endif
754
755	/** CPU Feature control. */
756	#define MSR_IA32_FEATURE_CONTROL 0x3A
757	#define MSR_IA32_FEATURE_CONTROL_LOCK RT_BIT(0)
758	#define MSR_IA32_FEATURE_CONTROL_VMXON RT_BIT(2)
759
760	/** BIOS update trigger (microcode update). */
761	#define MSR_IA32_BIOS_UPDT_TRIG 0x79
762
763	/** BIOS update signature (microcode). */
764	#define MSR_IA32_BIOS_SIGN_ID 0x8B
765
766	/** MTRR Capabilities. */
767	#define MSR_IA32_MTRR_CAP 0xFE
768
769
770	#ifndef MSR_IA32_SYSENTER_CS /* qemu cpu.h klugde */
771	/** SYSENTER_CS - the R0 CS, indirectly giving R0 SS, R3 CS and R3 DS.
772	* R0 SS == CS + 8
773	* R3 CS == CS + 16
774	* R3 SS == CS + 24
775	*/
776	#define MSR_IA32_SYSENTER_CS 0x174
777	/** SYSENTER_ESP - the R0 ESP. */
778	#define MSR_IA32_SYSENTER_ESP 0x175
779	/** SYSENTER_EIP - the R0 EIP. */
780	#define MSR_IA32_SYSENTER_EIP 0x176
781	#endif
782
783	/** Machine Check Global Capabilities Register. */
784	#define MSR_IA32_MCP_CAP 0x179
785	/** Machine Check Global Status Register. */
786	#define MSR_IA32_MCP_STATUS 0x17A
787	/** Machine Check Global Control Register. */
788	#define MSR_IA32_MCP_CTRL 0x17B
789
790	/* Page Attribute Table. */
791	#define MSR_IA32_CR_PAT 0x277
792
793	/** MTRR Default Range. */
794	#define MSR_IA32_MTRR_DEF_TYPE 0x2FF
795
796	#define MSR_IA32_MC0_CTL 0x400
797	#define MSR_IA32_MC0_STATUS 0x401
798
799	/** Basic VMX information. */
800	#define MSR_IA32_VMX_BASIC_INFO 0x480
801	/** Allowed settings for pin-based VM execution controls */
802	#define MSR_IA32_VMX_PINBASED_CTLS 0x481
803	/** Allowed settings for proc-based VM execution controls */
804	#define MSR_IA32_VMX_PROCBASED_CTLS 0x482
805	/** Allowed settings for the VMX exit controls. */
806	#define MSR_IA32_VMX_EXIT_CTLS 0x483
807	/** Allowed settings for the VMX entry controls. */
808	#define MSR_IA32_VMX_ENTRY_CTLS 0x484
809	/** Misc VMX info. */
810	#define MSR_IA32_VMX_MISC 0x485
811	/** Fixed cleared bits in CR0. */
812	#define MSR_IA32_VMX_CR0_FIXED0 0x486
813	/** Fixed set bits in CR0. */
814	#define MSR_IA32_VMX_CR0_FIXED1 0x487
815	/** Fixed cleared bits in CR4. */
816	#define MSR_IA32_VMX_CR4_FIXED0 0x488
817	/** Fixed set bits in CR4. */
818	#define MSR_IA32_VMX_CR4_FIXED1 0x489
819	/** Information for enumerating fields in the VMCS. */
820	#define MSR_IA32_VMX_VMCS_ENUM 0x48A
821	/** Allowed settings for secondary proc-based VM execution controls */
822	#define MSR_IA32_VMX_PROCBASED_CTLS2 0x48B
823	/** EPT capabilities. */
824	#define MSR_IA32_VMX_EPT_CAPS 0x48C
825	/** X2APIC MSR ranges. */
826	#define MSR_IA32_APIC_START 0x800
827	#define MSR_IA32_APIC_END 0x900
828
829	/** K6 EFER - Extended Feature Enable Register. */
830	#define MSR_K6_EFER 0xc0000080
831	/** @todo document EFER */
832	/** Bit 0 - SCE - System call extensions (SYSCALL / SYSRET). (R/W) */
833	#define MSR_K6_EFER_SCE RT_BIT(0)
834	/** Bit 8 - LME - Long mode enabled. (R/W) */
835	#define MSR_K6_EFER_LME RT_BIT(8)
836	/** Bit 10 - LMA - Long mode active. (R) */
837	#define MSR_K6_EFER_LMA RT_BIT(10)
838	/** Bit 11 - NXE - No-Execute Page Protection Enabled. (R/W) */
839	#define MSR_K6_EFER_NXE RT_BIT(11)
840	/** Bit 12 - SVME - Secure VM Extension Enabled. (R/W) */
841	#define MSR_K6_EFER_SVME RT_BIT(12)
842	/** Bit 13 - LMSLE - Long Mode Segment Limit Enable. (R/W?) */
843	#define MSR_K6_EFER_LMSLE RT_BIT(13)
844	/** Bit 14 - FFXSR - Fast FXSAVE / FXRSTOR (skip XMM). (R/W) /
845	#define MSR_K6_EFER_FFXSR RT_BIT(14)
846	/** K6 STAR - SYSCALL/RET targets. */
847	#define MSR_K6_STAR 0xc0000081
848	/** Shift value for getting the SYSRET CS and SS value. */
849	#define MSR_K6_STAR_SYSRET_CS_SS_SHIFT 48
850	/** Shift value for getting the SYSCALL CS and SS value. */
851	#define MSR_K6_STAR_SYSCALL_CS_SS_SHIFT 32
852	/** Selector mask for use after shifting. */
853	#define MSR_K6_STAR_SEL_MASK 0xffff
854	/** The mask which give the SYSCALL EIP. */
855	#define MSR_K6_STAR_SYSCALL_EIP_MASK 0xffffffff
856	/** K6 WHCR - Write Handling Control Register. */
857	#define MSR_K6_WHCR 0xc0000082
858	/** K6 UWCCR - UC/WC Cacheability Control Register. */
859	#define MSR_K6_UWCCR 0xc0000085
860	/** K6 PSOR - Processor State Observability Register. */
861	#define MSR_K6_PSOR 0xc0000087
862	/** K6 PFIR - Page Flush/Invalidate Register. */
863	#define MSR_K6_PFIR 0xc0000088
864
865	#define MSR_K7_EVNTSEL0 0xc0010000
866	#define MSR_K7_EVNTSEL1 0xc0010001
867	#define MSR_K7_EVNTSEL2 0xc0010002
868	#define MSR_K7_EVNTSEL3 0xc0010003
869	#define MSR_K7_PERFCTR0 0xc0010004
870	#define MSR_K7_PERFCTR1 0xc0010005
871	#define MSR_K7_PERFCTR2 0xc0010006
872	#define MSR_K7_PERFCTR3 0xc0010007
873
874	/** K8 LSTAR - Long mode SYSCALL target (RIP). */
875	#define MSR_K8_LSTAR 0xc0000082
876	/** K8 CSTAR - Compatibility mode SYSCALL target (RIP). */
877	#define MSR_K8_CSTAR 0xc0000083
878	/** K8 SF_MASK - SYSCALL flag mask. (aka SFMASK) */
879	#define MSR_K8_SF_MASK 0xc0000084
880	/** K8 FS.base - The 64-bit base FS register. */
881	#define MSR_K8_FS_BASE 0xc0000100
882	/** K8 GS.base - The 64-bit base GS register. */
883	#define MSR_K8_GS_BASE 0xc0000101
884	/** K8 KernelGSbase - Used with SWAPGS. */
885	#define MSR_K8_KERNEL_GS_BASE 0xc0000102
886	#define MSR_K8_TSC_AUX 0xc0000103
887	#define MSR_K8_SYSCFG 0xc0010010
888	#define MSR_K8_HWCR 0xc0010015
889	#define MSR_K8_IORRBASE0 0xc0010016
890	#define MSR_K8_IORRMASK0 0xc0010017
891	#define MSR_K8_IORRBASE1 0xc0010018
892	#define MSR_K8_IORRMASK1 0xc0010019
893	#define MSR_K8_TOP_MEM1 0xc001001a
894	#define MSR_K8_TOP_MEM2 0xc001001d
895	#define MSR_K8_VM_CR 0xc0010114
896	#define MSR_K8_VM_CR_SVM_DISABLE RT_BIT(4)
897
898	#define MSR_K8_IGNNE 0xc0010115
899	#define MSR_K8_SMM_CTL 0xc0010116
900	/** SVM - VM_HSAVE_PA - Physical address for saving and restoring
901	* host state during world switch.
902	*/
903	#define MSR_K8_VM_HSAVE_PA 0xc0010117
904
905	/** @} */
906
907
908	/** @name Page Table / Directory / Directory Pointers / L4.
909	* @{
910	*/
911
912	/** Page table/directory entry as an unsigned integer. */
913	typedef uint32_t X86PGUINT;
914	/** Pointer to a page table/directory table entry as an unsigned integer. */
915	typedef X86PGUINT *PX86PGUINT;
916	/** Pointer to an const page table/directory table entry as an unsigned integer. */
917	typedef X86PGUINT const *PCX86PGUINT;
918
919	/** Number of entries in a 32-bit PT/PD. */
920	#define X86_PG_ENTRIES 1024
921
922
923	/** PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
924	typedef uint64_t X86PGPAEUINT;
925	/** Pointer to a PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
926	typedef X86PGPAEUINT *PX86PGPAEUINT;
927	/** Pointer to an const PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
928	typedef X86PGPAEUINT const *PCX86PGPAEUINT;
929
930	/** Number of entries in a PAE PT/PD. */
931	#define X86_PG_PAE_ENTRIES 512
932	/** Number of entries in a PAE PDPT. */
933	#define X86_PG_PAE_PDPE_ENTRIES 4
934
935	/** Number of entries in an AMD64 PT/PD/PDPT/L4/L5. */
936	#define X86_PG_AMD64_ENTRIES X86_PG_PAE_ENTRIES
937	/** Number of entries in an AMD64 PDPT.
938	* Just for complementing X86_PG_PAE_PDPE_ENTRIES, using X86_PG_AMD64_ENTRIES for this is fine too. */
939	#define X86_PG_AMD64_PDPE_ENTRIES X86_PG_AMD64_ENTRIES
940
941	/** The size of a 4KB page. */
942	#define X86_PAGE_4K_SIZE _4K
943	/** The page shift of a 4KB page. */
944	#define X86_PAGE_4K_SHIFT 12
945	/** The 4KB page offset mask. */
946	#define X86_PAGE_4K_OFFSET_MASK 0xfff
947	/** The 4KB page base mask for virtual addresses. */
948	#define X86_PAGE_4K_BASE_MASK 0xfffffffffffff000ULL
949	/** The 4KB page base mask for virtual addresses - 32bit version. */
950	#define X86_PAGE_4K_BASE_MASK_32 0xfffff000U
951
952	/** The size of a 2MB page. */
953	#define X86_PAGE_2M_SIZE _2M
954	/** The page shift of a 2MB page. */
955	#define X86_PAGE_2M_SHIFT 21
956	/** The 2MB page offset mask. */
957	#define X86_PAGE_2M_OFFSET_MASK 0x001fffff
958	/** The 2MB page base mask for virtual addresses. */
959	#define X86_PAGE_2M_BASE_MASK 0xffffffffffe00000ULL
960	/** The 2MB page base mask for virtual addresses - 32bit version. */
961	#define X86_PAGE_2M_BASE_MASK_32 0xffe00000U
962
963	/** The size of a 4MB page. */
964	#define X86_PAGE_4M_SIZE _4M
965	/** The page shift of a 4MB page. */
966	#define X86_PAGE_4M_SHIFT 22
967	/** The 4MB page offset mask. */
968	#define X86_PAGE_4M_OFFSET_MASK 0x003fffff
969	/** The 4MB page base mask for virtual addresses. */
970	#define X86_PAGE_4M_BASE_MASK 0xffffffffffc00000ULL
971	/** The 4MB page base mask for virtual addresses - 32bit version. */
972	#define X86_PAGE_4M_BASE_MASK_32 0xffc00000U
973
974
975
976	/** @name Page Table Entry
977	* @{
978	*/
979	/** Bit 0 - P - Present bit. */
980	#define X86_PTE_BIT_P 0
981	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
982	#define X86_PTE_BIT_RW 1
983	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
984	#define X86_PTE_BIT_US 2
985	/** Bit 3 - PWT - Page level write thru bit. */
986	#define X86_PTE_BIT_PWT 3
987	/** Bit 4 - PCD - Page level cache disable bit. */
988	#define X86_PTE_BIT_PCD 4
989	/** Bit 5 - A - Access bit. */
990	#define X86_PTE_BIT_A 5
991	/** Bit 6 - D - Dirty bit. */
992	#define X86_PTE_BIT_D 6
993	/** Bit 7 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
994	#define X86_PTE_BIT_PAT 7
995	/** Bit 8 - G - Global flag. */
996	#define X86_PTE_BIT_G 8
997
998	/** Bit 0 - P - Present bit mask. */
999	#define X86_PTE_P RT_BIT(0)
1000	/** Bit 1 - R/W - Read (clear) / Write (set) bit mask. */
1001	#define X86_PTE_RW RT_BIT(1)
1002	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit mask. */
1003	#define X86_PTE_US RT_BIT(2)
1004	/** Bit 3 - PWT - Page level write thru bit mask. */
1005	#define X86_PTE_PWT RT_BIT(3)
1006	/** Bit 4 - PCD - Page level cache disable bit mask. */
1007	#define X86_PTE_PCD RT_BIT(4)
1008	/** Bit 5 - A - Access bit mask. */
1009	#define X86_PTE_A RT_BIT(5)
1010	/** Bit 6 - D - Dirty bit mask. */
1011	#define X86_PTE_D RT_BIT(6)
1012	/** Bit 7 - PAT - Page Attribute Table index bit mask. Reserved and 0 if not supported. */
1013	#define X86_PTE_PAT RT_BIT(7)
1014	/** Bit 8 - G - Global bit mask. */
1015	#define X86_PTE_G RT_BIT(8)
1016
1017	/** Bits 9-11 - - Available for use to system software. */
1018	#define X86_PTE_AVL_MASK (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
1019	/** Bits 12-31 - - Physical Page number of the next level. */
1020	#define X86_PTE_PG_MASK ( 0xfffff000 )
1021
1022	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1023	#if 1 /* we're using this internally and have to mask of the top 16-bit. */
1024	#define X86_PTE_PAE_PG_MASK ( 0x0000fffffffff000ULL )
1025	/** @todo Get rid of the above hack; makes code unreadable. */
1026	#define X86_PTE_PAE_PG_MASK_FULL ( 0x000ffffffffff000ULL )
1027	#else
1028	#define X86_PTE_PAE_PG_MASK ( 0x000ffffffffff000ULL )
1029	#endif
1030	/** Bits 63 - NX - PAE - No execution flag. */
1031	#define X86_PTE_PAE_NX RT_BIT_64(63)
1032
1033	/**
1034	* Page table entry.
1035	*/
1036	typedef struct X86PTEBITS
1037	{
1038	/** Flags whether(=1) or not the page is present. */
1039	unsigned u1Present : 1;
1040	/** Read(=0) / Write(=1) flag. */
1041	unsigned u1Write : 1;
1042	/** User(=1) / Supervisor (=0) flag. */
1043	unsigned u1User : 1;
1044	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1045	unsigned u1WriteThru : 1;
1046	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1047	unsigned u1CacheDisable : 1;
1048	/** Accessed flag.
1049	* Indicates that the page have been read or written to. */
1050	unsigned u1Accessed : 1;
1051	/** Dirty flag.
1052	* Indicates that the page have been written to. */
1053	unsigned u1Dirty : 1;
1054	/** Reserved / If PAT enabled, bit 2 of the index. */
1055	unsigned u1PAT : 1;
1056	/** Global flag. (Ignored in all but final level.) */
1057	unsigned u1Global : 1;
1058	/** Available for use to system software. */
1059	unsigned u3Available : 3;
1060	/** Physical Page number of the next level. */
1061	unsigned u20PageNo : 20;
1062	} X86PTEBITS;
1063	/** Pointer to a page table entry. */
1064	typedef X86PTEBITS *PX86PTEBITS;
1065	/** Pointer to a const page table entry. */
1066	typedef const X86PTEBITS *PCX86PTEBITS;
1067
1068	/**
1069	* Page table entry.
1070	*/
1071	typedef union X86PTE
1072	{
1073	/** Unsigned integer view */
1074	X86PGUINT u;
1075	/** Bit field view. */
1076	X86PTEBITS n;
1077	/** 32-bit view. */
1078	uint32_t au32[1];
1079	/** 16-bit view. */
1080	uint16_t au16[2];
1081	/** 8-bit view. */
1082	uint8_t au8[4];
1083	} X86PTE;
1084	/** Pointer to a page table entry. */
1085	typedef X86PTE *PX86PTE;
1086	/** Pointer to a const page table entry. */
1087	typedef const X86PTE *PCX86PTE;
1088
1089
1090	/**
1091	* PAE page table entry.
1092	*/
1093	typedef struct X86PTEPAEBITS
1094	{
1095	/** Flags whether(=1) or not the page is present. */
1096	uint32_t u1Present : 1;
1097	/** Read(=0) / Write(=1) flag. */
1098	uint32_t u1Write : 1;
1099	/** User(=1) / Supervisor(=0) flag. */
1100	uint32_t u1User : 1;
1101	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1102	uint32_t u1WriteThru : 1;
1103	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1104	uint32_t u1CacheDisable : 1;
1105	/** Accessed flag.
1106	* Indicates that the page have been read or written to. */
1107	uint32_t u1Accessed : 1;
1108	/** Dirty flag.
1109	* Indicates that the page have been written to. */
1110	uint32_t u1Dirty : 1;
1111	/** Reserved / If PAT enabled, bit 2 of the index. */
1112	uint32_t u1PAT : 1;
1113	/** Global flag. (Ignored in all but final level.) */
1114	uint32_t u1Global : 1;
1115	/** Available for use to system software. */
1116	uint32_t u3Available : 3;
1117	/** Physical Page number of the next level - Low Part. Don't use this. */
1118	uint32_t u20PageNoLow : 20;
1119	/** Physical Page number of the next level - High Part. Don't use this. */
1120	uint32_t u20PageNoHigh : 20;
1121	/** MBZ bits */
1122	uint32_t u11Reserved : 11;
1123	/** No Execute flag. */
1124	uint32_t u1NoExecute : 1;
1125	} X86PTEPAEBITS;
1126	/** Pointer to a page table entry. */
1127	typedef X86PTEPAEBITS *PX86PTEPAEBITS;
1128	/** Pointer to a page table entry. */
1129	typedef const X86PTEPAEBITS *PCX86PTEPAEBITS;
1130
1131	/**
1132	* PAE Page table entry.
1133	*/
1134	typedef union X86PTEPAE
1135	{
1136	/** Unsigned integer view */
1137	X86PGPAEUINT u;
1138	/** Bit field view. */
1139	X86PTEPAEBITS n;
1140	/** 32-bit view. */
1141	uint32_t au32[2];
1142	/** 16-bit view. */
1143	uint16_t au16[4];
1144	/** 8-bit view. */
1145	uint8_t au8[8];
1146	} X86PTEPAE;
1147	/** Pointer to a PAE page table entry. */
1148	typedef X86PTEPAE *PX86PTEPAE;
1149	/** Pointer to a const PAE page table entry. */
1150	typedef const X86PTEPAE *PCX86PTEPAE;
1151	/** @} */
1152
1153	/**
1154	* Page table.
1155	*/
1156	typedef struct X86PT
1157	{
1158	/** PTE Array. */
1159	X86PTE a[X86_PG_ENTRIES];
1160	} X86PT;
1161	/** Pointer to a page table. */
1162	typedef X86PT *PX86PT;
1163	/** Pointer to a const page table. */
1164	typedef const X86PT *PCX86PT;
1165
1166	/** The page shift to get the PT index. */
1167	#define X86_PT_SHIFT 12
1168	/** The PT index mask (apply to a shifted page address). */
1169	#define X86_PT_MASK 0x3ff
1170
1171
1172	/**
1173	* Page directory.
1174	*/
1175	typedef struct X86PTPAE
1176	{
1177	/** PTE Array. */
1178	X86PTEPAE a[X86_PG_PAE_ENTRIES];
1179	} X86PTPAE;
1180	/** Pointer to a page table. */
1181	typedef X86PTPAE *PX86PTPAE;
1182	/** Pointer to a const page table. */
1183	typedef const X86PTPAE *PCX86PTPAE;
1184
1185	/** The page shift to get the PA PTE index. */
1186	#define X86_PT_PAE_SHIFT 12
1187	/** The PAE PT index mask (apply to a shifted page address). */
1188	#define X86_PT_PAE_MASK 0x1ff
1189
1190
1191	/** @name 4KB Page Directory Entry
1192	* @{
1193	*/
1194	/** Bit 0 - P - Present bit. */
1195	#define X86_PDE_P RT_BIT(0)
1196	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1197	#define X86_PDE_RW RT_BIT(1)
1198	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1199	#define X86_PDE_US RT_BIT(2)
1200	/** Bit 3 - PWT - Page level write thru bit. */
1201	#define X86_PDE_PWT RT_BIT(3)
1202	/** Bit 4 - PCD - Page level cache disable bit. */
1203	#define X86_PDE_PCD RT_BIT(4)
1204	/** Bit 5 - A - Access bit. */
1205	#define X86_PDE_A RT_BIT(5)
1206	/** Bit 7 - PS - Page size attribute.
1207	* Clear mean 4KB pages, set means large pages (2/4MB). */
1208	#define X86_PDE_PS RT_BIT(7)
1209	/** Bits 9-11 - - Available for use to system software. */
1210	#define X86_PDE_AVL_MASK (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
1211	/** Bits 12-31 - - Physical Page number of the next level. */
1212	#define X86_PDE_PG_MASK ( 0xfffff000 )
1213
1214	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1215	#if 1 /* we're using this internally and have to mask of the top 16-bit. */
1216	/* Note: This is kind of dangerous if the guest uses these bits (legally or illegally);
1217	* we partly or that part into shadow page table entries. Will be corrected
1218	* soon.
1219	*/
1220	#define X86_PDE_PAE_PG_MASK ( 0x0000fffffffff000ULL )
1221	#define X86_PDE_PAE_PG_MASK_FULL ( 0x000ffffffffff000ULL )
1222	#else
1223	#define X86_PDE_PAE_PG_MASK ( 0x000ffffffffff000ULL )
1224	#endif
1225	/** Bits 63 - NX - PAE - No execution flag. */
1226	#define X86_PDE_PAE_NX RT_BIT_64(63)
1227
1228	/**
1229	* Page directory entry.
1230	*/
1231	typedef struct X86PDEBITS
1232	{
1233	/** Flags whether(=1) or not the page is present. */
1234	unsigned u1Present : 1;
1235	/** Read(=0) / Write(=1) flag. */
1236	unsigned u1Write : 1;
1237	/** User(=1) / Supervisor (=0) flag. */
1238	unsigned u1User : 1;
1239	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1240	unsigned u1WriteThru : 1;
1241	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1242	unsigned u1CacheDisable : 1;
1243	/** Accessed flag.
1244	* Indicates that the page have been read or written to. */
1245	unsigned u1Accessed : 1;
1246	/** Reserved / Ignored (dirty bit). */
1247	unsigned u1Reserved0 : 1;
1248	/** Size bit if PSE is enabled - in any event it's 0. */
1249	unsigned u1Size : 1;
1250	/** Reserved / Ignored (global bit). */
1251	unsigned u1Reserved1 : 1;
1252	/** Available for use to system software. */
1253	unsigned u3Available : 3;
1254	/** Physical Page number of the next level. */
1255	unsigned u20PageNo : 20;
1256	} X86PDEBITS;
1257	/** Pointer to a page directory entry. */
1258	typedef X86PDEBITS *PX86PDEBITS;
1259	/** Pointer to a const page directory entry. */
1260	typedef const X86PDEBITS *PCX86PDEBITS;
1261
1262
1263	/**
1264	* PAE page directory entry.
1265	*/
1266	typedef struct X86PDEPAEBITS
1267	{
1268	/** Flags whether(=1) or not the page is present. */
1269	uint32_t u1Present : 1;
1270	/** Read(=0) / Write(=1) flag. */
1271	uint32_t u1Write : 1;
1272	/** User(=1) / Supervisor (=0) flag. */
1273	uint32_t u1User : 1;
1274	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1275	uint32_t u1WriteThru : 1;
1276	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1277	uint32_t u1CacheDisable : 1;
1278	/** Accessed flag.
1279	* Indicates that the page have been read or written to. */
1280	uint32_t u1Accessed : 1;
1281	/** Reserved / Ignored (dirty bit). */
1282	uint32_t u1Reserved0 : 1;
1283	/** Size bit if PSE is enabled - in any event it's 0. */
1284	uint32_t u1Size : 1;
1285	/** Reserved / Ignored (global bit). / */
1286	uint32_t u1Reserved1 : 1;
1287	/** Available for use to system software. */
1288	uint32_t u3Available : 3;
1289	/** Physical Page number of the next level - Low Part. Don't use! */
1290	uint32_t u20PageNoLow : 20;
1291	/** Physical Page number of the next level - High Part. Don't use! */
1292	uint32_t u20PageNoHigh : 20;
1293	/** MBZ bits */
1294	uint32_t u11Reserved : 11;
1295	/** No Execute flag. */
1296	uint32_t u1NoExecute : 1;
1297	} X86PDEPAEBITS;
1298	/** Pointer to a page directory entry. */
1299	typedef X86PDEPAEBITS *PX86PDEPAEBITS;
1300	/** Pointer to a const page directory entry. */
1301	typedef const X86PDEPAEBITS *PCX86PDEPAEBITS;
1302
1303	/** @} */
1304
1305
1306	/** @name 2/4MB Page Directory Entry
1307	* @{
1308	*/
1309	/** Bit 0 - P - Present bit. */
1310	#define X86_PDE4M_P RT_BIT(0)
1311	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1312	#define X86_PDE4M_RW RT_BIT(1)
1313	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1314	#define X86_PDE4M_US RT_BIT(2)
1315	/** Bit 3 - PWT - Page level write thru bit. */
1316	#define X86_PDE4M_PWT RT_BIT(3)
1317	/** Bit 4 - PCD - Page level cache disable bit. */
1318	#define X86_PDE4M_PCD RT_BIT(4)
1319	/** Bit 5 - A - Access bit. */
1320	#define X86_PDE4M_A RT_BIT(5)
1321	/** Bit 6 - D - Dirty bit. */
1322	#define X86_PDE4M_D RT_BIT(6)
1323	/** Bit 7 - PS - Page size attribute. Clear mean 4KB pages, set means large pages (2/4MB). */
1324	#define X86_PDE4M_PS RT_BIT(7)
1325	/** Bit 8 - G - Global flag. */
1326	#define X86_PDE4M_G RT_BIT(8)
1327	/** Bits 9-11 - AVL - Available for use to system software. */
1328	#define X86_PDE4M_AVL (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
1329	/** Bit 12 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
1330	#define X86_PDE4M_PAT RT_BIT(12)
1331	/** Shift to get from X86_PTE_PAT to X86_PDE4M_PAT. */
1332	#define X86_PDE4M_PAT_SHIFT (12 - 7)
1333	/** Bits 22-31 - - Physical Page number. */
1334	#define X86_PDE4M_PG_MASK ( 0xffc00000 )
1335	/** Bits 13-20 - - Physical Page number high part (32-39 bits). AMD64 hack. */
1336	#define X86_PDE4M_PG_HIGH_MASK ( 0x001fe000 )
1337	/** The number of bits to the high part of the page number. */
1338	#define X86_PDE4M_PG_HIGH_SHIFT 19
1339
1340	/** Bits 21-51 - - PAE & AMD64 - Physical Page number.
1341	* (Bits 40-51 (long mode) & bits 36-51 (pae legacy) are reserved according to the Intel docs; AMD allows for more.) */
1342	#define X86_PDE2M_PAE_PG_MASK ( 0x000fffffffe00000ULL )
1343	/** Bits 63 - NX - PAE & AMD64 - No execution flag. */
1344	#define X86_PDE2M_PAE_NX X86_PDE2M_PAE_NX
1345
1346	/**
1347	* 4MB page directory entry.
1348	*/
1349	typedef struct X86PDE4MBITS
1350	{
1351	/** Flags whether(=1) or not the page is present. */
1352	unsigned u1Present : 1;
1353	/** Read(=0) / Write(=1) flag. */
1354	unsigned u1Write : 1;
1355	/** User(=1) / Supervisor (=0) flag. */
1356	unsigned u1User : 1;
1357	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1358	unsigned u1WriteThru : 1;
1359	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1360	unsigned u1CacheDisable : 1;
1361	/** Accessed flag.
1362	* Indicates that the page have been read or written to. */
1363	unsigned u1Accessed : 1;
1364	/** Dirty flag.
1365	* Indicates that the page have been written to. */
1366	unsigned u1Dirty : 1;
1367	/** Page size flag - always 1 for 4MB entries. */
1368	unsigned u1Size : 1;
1369	/** Global flag. */
1370	unsigned u1Global : 1;
1371	/** Available for use to system software. */
1372	unsigned u3Available : 3;
1373	/** Reserved / If PAT enabled, bit 2 of the index. */
1374	unsigned u1PAT : 1;
1375	/** Bits 32-39 of the page number on AMD64.
1376	* This AMD64 hack allows accessing 40bits of physical memory without PAE. */
1377	unsigned u8PageNoHigh : 8;
1378	/** Reserved. */
1379	unsigned u1Reserved : 1;
1380	/** Physical Page number of the page. */
1381	unsigned u10PageNo : 10;
1382	} X86PDE4MBITS;
1383	/** Pointer to a page table entry. */
1384	typedef X86PDE4MBITS *PX86PDE4MBITS;
1385	/** Pointer to a const page table entry. */
1386	typedef const X86PDE4MBITS *PCX86PDE4MBITS;
1387
1388
1389	/**
1390	* 2MB PAE page directory entry.
1391	*/
1392	typedef struct X86PDE2MPAEBITS
1393	{
1394	/** Flags whether(=1) or not the page is present. */
1395	uint32_t u1Present : 1;
1396	/** Read(=0) / Write(=1) flag. */
1397	uint32_t u1Write : 1;
1398	/** User(=1) / Supervisor(=0) flag. */
1399	uint32_t u1User : 1;
1400	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1401	uint32_t u1WriteThru : 1;
1402	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1403	uint32_t u1CacheDisable : 1;
1404	/** Accessed flag.
1405	* Indicates that the page have been read or written to. */
1406	uint32_t u1Accessed : 1;
1407	/** Dirty flag.
1408	* Indicates that the page have been written to. */
1409	uint32_t u1Dirty : 1;
1410	/** Page size flag - always 1 for 2MB entries. */
1411	uint32_t u1Size : 1;
1412	/** Global flag. */
1413	uint32_t u1Global : 1;
1414	/** Available for use to system software. */
1415	uint32_t u3Available : 3;
1416	/** Reserved / If PAT enabled, bit 2 of the index. */
1417	uint32_t u1PAT : 1;
1418	/** Reserved. */
1419	uint32_t u9Reserved : 9;
1420	/** Physical Page number of the next level - Low part. Don't use! */
1421	uint32_t u10PageNoLow : 10;
1422	/** Physical Page number of the next level - High part. Don't use! */
1423	uint32_t u20PageNoHigh : 20;
1424	/** MBZ bits */
1425	uint32_t u11Reserved : 11;
1426	/** No Execute flag. */
1427	uint32_t u1NoExecute : 1;
1428	} X86PDE2MPAEBITS;
1429	/** Pointer to a 4MB PAE page table entry. */
1430	typedef X86PDE2MPAEBITS *PX86PDE2MPAEBITS;
1431	/** Pointer to a 4MB PAE page table entry. */
1432	typedef const X86PDE2MPAEBITS *PCX86PDE2MPAEBITS;
1433
1434	/** @} */
1435
1436	/**
1437	* Page directory entry.
1438	*/
1439	typedef union X86PDE
1440	{
1441	/** Unsigned integer view. */
1442	X86PGUINT u;
1443	/** Normal view. */
1444	X86PDEBITS n;
1445	/** 4MB view (big). */
1446	X86PDE4MBITS b;
1447	/** 8 bit unsigned integer view. */
1448	uint8_t au8[4];
1449	/** 16 bit unsigned integer view. */
1450	uint16_t au16[2];
1451	/** 32 bit unsigned integer view. */
1452	uint32_t au32[1];
1453	} X86PDE;
1454	/** Pointer to a page directory entry. */
1455	typedef X86PDE *PX86PDE;
1456	/** Pointer to a const page directory entry. */
1457	typedef const X86PDE *PCX86PDE;
1458
1459	/**
1460	* PAE page directory entry.
1461	*/
1462	typedef union X86PDEPAE
1463	{
1464	/** Unsigned integer view. */
1465	X86PGPAEUINT u;
1466	/** Normal view. */
1467	X86PDEPAEBITS n;
1468	/** 2MB page view (big). */
1469	X86PDE2MPAEBITS b;
1470	/** 8 bit unsigned integer view. */
1471	uint8_t au8[8];
1472	/** 16 bit unsigned integer view. */
1473	uint16_t au16[4];
1474	/** 32 bit unsigned integer view. */
1475	uint32_t au32[2];
1476	} X86PDEPAE;
1477	/** Pointer to a page directory entry. */
1478	typedef X86PDEPAE *PX86PDEPAE;
1479	/** Pointer to a const page directory entry. */
1480	typedef const X86PDEPAE *PCX86PDEPAE;
1481
1482	/**
1483	* Page directory.
1484	*/
1485	typedef struct X86PD
1486	{
1487	/** PDE Array. */
1488	X86PDE a[X86_PG_ENTRIES];
1489	} X86PD;
1490	/** Pointer to a page directory. */
1491	typedef X86PD *PX86PD;
1492	/** Pointer to a const page directory. */
1493	typedef const X86PD *PCX86PD;
1494
1495	/** The page shift to get the PD index. */
1496	#define X86_PD_SHIFT 22
1497	/** The PD index mask (apply to a shifted page address). */
1498	#define X86_PD_MASK 0x3ff
1499
1500
1501	/**
1502	* PAE page directory.
1503	*/
1504	typedef struct X86PDPAE
1505	{
1506	/** PDE Array. */
1507	X86PDEPAE a[X86_PG_PAE_ENTRIES];
1508	} X86PDPAE;
1509	/** Pointer to a PAE page directory. */
1510	typedef X86PDPAE *PX86PDPAE;
1511	/** Pointer to a const PAE page directory. */
1512	typedef const X86PDPAE *PCX86PDPAE;
1513
1514	/** The page shift to get the PAE PD index. */
1515	#define X86_PD_PAE_SHIFT 21
1516	/** The PAE PD index mask (apply to a shifted page address). */
1517	#define X86_PD_PAE_MASK 0x1ff
1518
1519
1520	/** @name Page Directory Pointer Table Entry (PAE)
1521	* @{
1522	*/
1523	/** Bit 0 - P - Present bit. */
1524	#define X86_PDPE_P RT_BIT(0)
1525	/** Bit 1 - R/W - Read (clear) / Write (set) bit. Long Mode only. */
1526	#define X86_PDPE_RW RT_BIT(1)
1527	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. Long Mode only. */
1528	#define X86_PDPE_US RT_BIT(2)
1529	/** Bit 3 - PWT - Page level write thru bit. */
1530	#define X86_PDPE_PWT RT_BIT(3)
1531	/** Bit 4 - PCD - Page level cache disable bit. */
1532	#define X86_PDPE_PCD RT_BIT(4)
1533	/** Bit 5 - A - Access bit. Long Mode only. */
1534	#define X86_PDPE_A RT_BIT(5)
1535	/** Bits 9-11 - - Available for use to system software. */
1536	#define X86_PDPE_AVL_MASK (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
1537	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1538	#if 1 /* we're using this internally and have to mask of the top 16-bit. */
1539	#define X86_PDPE_PG_MASK ( 0x0000fffffffff000ULL )
1540	/** @todo Get rid of the above hack; makes code unreadable. */
1541	#define X86_PDPE_PG_MASK_FULL ( 0x000ffffffffff000ULL )
1542	#else
1543	#define X86_PDPE_PG_MASK ( 0x000ffffffffff000ULL )
1544	#endif
1545	/** Bits 63 - NX - PAE - No execution flag. Long Mode only. */
1546	#define X86_PDPE_NX RT_BIT_64(63)
1547
1548	/**
1549	* Page directory pointer table entry.
1550	*/
1551	typedef struct X86PDPEBITS
1552	{
1553	/** Flags whether(=1) or not the page is present. */
1554	uint32_t u1Present : 1;
1555	/** Chunk of reserved bits. */
1556	uint32_t u2Reserved : 2;
1557	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1558	uint32_t u1WriteThru : 1;
1559	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1560	uint32_t u1CacheDisable : 1;
1561	/** Chunk of reserved bits. */
1562	uint32_t u4Reserved : 4;
1563	/** Available for use to system software. */
1564	uint32_t u3Available : 3;
1565	/** Physical Page number of the next level - Low Part. Don't use! */
1566	uint32_t u20PageNoLow : 20;
1567	/** Physical Page number of the next level - High Part. Don't use! */
1568	uint32_t u20PageNoHigh : 20;
1569	/** MBZ bits */
1570	uint32_t u12Reserved : 12;
1571	} X86PDPEBITS;
1572	/** Pointer to a page directory pointer table entry. */
1573	typedef X86PDPEBITS *PX86PTPEBITS;
1574	/** Pointer to a const page directory pointer table entry. */
1575	typedef const X86PDPEBITS *PCX86PTPEBITS;
1576
1577	/**
1578	* Page directory pointer table entry. AMD64 version
1579	*/
1580	typedef struct X86PDPEAMD64BITS
1581	{
1582	/** Flags whether(=1) or not the page is present. */
1583	uint32_t u1Present : 1;
1584	/** Read(=0) / Write(=1) flag. */
1585	uint32_t u1Write : 1;
1586	/** User(=1) / Supervisor (=0) flag. */
1587	uint32_t u1User : 1;
1588	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1589	uint32_t u1WriteThru : 1;
1590	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1591	uint32_t u1CacheDisable : 1;
1592	/** Accessed flag.
1593	* Indicates that the page have been read or written to. */
1594	uint32_t u1Accessed : 1;
1595	/** Chunk of reserved bits. */
1596	uint32_t u3Reserved : 3;
1597	/** Available for use to system software. */
1598	uint32_t u3Available : 3;
1599	/** Physical Page number of the next level - Low Part. Don't use! */
1600	uint32_t u20PageNoLow : 20;
1601	/** Physical Page number of the next level - High Part. Don't use! */
1602	uint32_t u20PageNoHigh : 20;
1603	/** MBZ bits */
1604	uint32_t u11Reserved : 11;
1605	/** No Execute flag. */
1606	uint32_t u1NoExecute : 1;
1607	} X86PDPEAMD64BITS;
1608	/** Pointer to a page directory pointer table entry. */
1609	typedef X86PDPEAMD64BITS *PX86PDPEAMD64BITS;
1610	/** Pointer to a const page directory pointer table entry. */
1611	typedef const X86PDPEBITS *PCX86PDPEAMD64BITS;
1612
1613	/**
1614	* Page directory pointer table entry.
1615	*/
1616	typedef union X86PDPE
1617	{
1618	/** Unsigned integer view. */
1619	X86PGPAEUINT u;
1620	/** Normal view. */
1621	X86PDPEBITS n;
1622	/** AMD64 view. */
1623	X86PDPEAMD64BITS lm;
1624	/** 8 bit unsigned integer view. */
1625	uint8_t au8[8];
1626	/** 16 bit unsigned integer view. */
1627	uint16_t au16[4];
1628	/** 32 bit unsigned integer view. */
1629	uint32_t au32[2];
1630	} X86PDPE;
1631	/** Pointer to a page directory pointer table entry. */
1632	typedef X86PDPE *PX86PDPE;
1633	/** Pointer to a const page directory pointer table entry. */
1634	typedef const X86PDPE *PCX86PDPE;
1635
1636
1637	/**
1638	* Page directory pointer table.
1639	*/
1640	typedef struct X86PDPT
1641	{
1642	/** PDE Array. */
1643	X86PDPE a[X86_PG_AMD64_PDPE_ENTRIES];
1644	} X86PDPT;
1645	/** Pointer to a page directory pointer table. */
1646	typedef X86PDPT *PX86PDPT;
1647	/** Pointer to a const page directory pointer table. */
1648	typedef const X86PDPT *PCX86PDPT;
1649
1650	/** The page shift to get the PDPT index. */
1651	#define X86_PDPT_SHIFT 30
1652	/** The PDPT index mask (apply to a shifted page address). (32 bits PAE) */
1653	#define X86_PDPT_MASK_PAE 0x3
1654	/** The PDPT index mask (apply to a shifted page address). (64 bits PAE)*/
1655	#define X86_PDPT_MASK_AMD64 0x1ff
1656
1657	/** @} */
1658
1659
1660	/** @name Page Map Level-4 Entry (Long Mode PAE)
1661	* @{
1662	*/
1663	/** Bit 0 - P - Present bit. */
1664	#define X86_PML4E_P RT_BIT(0)
1665	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1666	#define X86_PML4E_RW RT_BIT(1)
1667	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1668	#define X86_PML4E_US RT_BIT(2)
1669	/** Bit 3 - PWT - Page level write thru bit. */
1670	#define X86_PML4E_PWT RT_BIT(3)
1671	/** Bit 4 - PCD - Page level cache disable bit. */
1672	#define X86_PML4E_PCD RT_BIT(4)
1673	/** Bit 5 - A - Access bit. */
1674	#define X86_PML4E_A RT_BIT(5)
1675	/** Bits 9-11 - - Available for use to system software. */
1676	#define X86_PML4E_AVL_MASK (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
1677	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1678	#if 1 /* we're using this internally and have to mask of the top 16-bit. */
1679	#define X86_PML4E_PG_MASK ( 0x0000fffffffff000ULL )
1680	#define X86_PML4E_PG_MASK_FULL ( 0x000ffffffffff000ULL )
1681	#else
1682	#define X86_PML4E_PG_MASK ( 0x000ffffffffff000ULL )
1683	#endif
1684	/** Bits 63 - NX - PAE - No execution flag. */
1685	#define X86_PML4E_NX RT_BIT_64(63)
1686
1687	/**
1688	* Page Map Level-4 Entry
1689	*/
1690	typedef struct X86PML4EBITS
1691	{
1692	/** Flags whether(=1) or not the page is present. */
1693	uint32_t u1Present : 1;
1694	/** Read(=0) / Write(=1) flag. */
1695	uint32_t u1Write : 1;
1696	/** User(=1) / Supervisor (=0) flag. */
1697	uint32_t u1User : 1;
1698	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1699	uint32_t u1WriteThru : 1;
1700	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1701	uint32_t u1CacheDisable : 1;
1702	/** Accessed flag.
1703	* Indicates that the page have been read or written to. */
1704	uint32_t u1Accessed : 1;
1705	/** Chunk of reserved bits. */
1706	uint32_t u3Reserved : 3;
1707	/** Available for use to system software. */
1708	uint32_t u3Available : 3;
1709	/** Physical Page number of the next level - Low Part. Don't use! */
1710	uint32_t u20PageNoLow : 20;
1711	/** Physical Page number of the next level - High Part. Don't use! */
1712	uint32_t u20PageNoHigh : 20;
1713	/** MBZ bits */
1714	uint32_t u11Reserved : 11;
1715	/** No Execute flag. */
1716	uint32_t u1NoExecute : 1;
1717	} X86PML4EBITS;
1718	/** Pointer to a page map level-4 entry. */
1719	typedef X86PML4EBITS *PX86PML4EBITS;
1720	/** Pointer to a const page map level-4 entry. */
1721	typedef const X86PML4EBITS *PCX86PML4EBITS;
1722
1723	/**
1724	* Page Map Level-4 Entry.
1725	*/
1726	typedef union X86PML4E
1727	{
1728	/** Unsigned integer view. */
1729	X86PGPAEUINT u;
1730	/** Normal view. */
1731	X86PML4EBITS n;
1732	/** 8 bit unsigned integer view. */
1733	uint8_t au8[8];
1734	/** 16 bit unsigned integer view. */
1735	uint16_t au16[4];
1736	/** 32 bit unsigned integer view. */
1737	uint32_t au32[2];
1738	} X86PML4E;
1739	/** Pointer to a page map level-4 entry. */
1740	typedef X86PML4E *PX86PML4E;
1741	/** Pointer to a const page map level-4 entry. */
1742	typedef const X86PML4E *PCX86PML4E;
1743
1744
1745	/**
1746	* Page Map Level-4.
1747	*/
1748	typedef struct X86PML4
1749	{
1750	/** PDE Array. */
1751	X86PML4E a[X86_PG_PAE_ENTRIES];
1752	} X86PML4;
1753	/** Pointer to a page map level-4. */
1754	typedef X86PML4 *PX86PML4;
1755	/** Pointer to a const page map level-4. */
1756	typedef const X86PML4 *PCX86PML4;
1757
1758	/** The page shift to get the PML4 index. */
1759	#define X86_PML4_SHIFT 39
1760	/** The PML4 index mask (apply to a shifted page address). */
1761	#define X86_PML4_MASK 0x1ff
1762
1763	/** @} */
1764
1765	/** @} */
1766
1767
1768	/**
1769	* 80-bit MMX/FPU register type.
1770	*/
1771	typedef struct X86FPUMMX
1772	{
1773	uint8_t reg[10];
1774	} X86FPUMMX;
1775	/** Pointer to a 80-bit MMX/FPU register type. */
1776	typedef X86FPUMMX *PX86FPUMMX;
1777	/** Pointer to a const 80-bit MMX/FPU register type. */
1778	typedef const X86FPUMMX *PCX86FPUMMX;
1779
1780	/**
1781	* FPU state (aka FSAVE/FRSTOR Memory Region).
1782	*/
1783	#pragma pack(1)
1784	typedef struct X86FPUSTATE
1785	{
1786	/** Control word. */
1787	uint16_t FCW;
1788	/** Alignment word */
1789	uint16_t Dummy1;
1790	/** Status word. */
1791	uint16_t FSW;
1792	/** Alignment word */
1793	uint16_t Dummy2;
1794	/** Tag word */
1795	uint16_t FTW;
1796	/** Alignment word */
1797	uint16_t Dummy3;
1798
1799	/** Instruction pointer. */
1800	uint32_t FPUIP;
1801	/** Code selector. */
1802	uint16_t CS;
1803	/** Opcode. */
1804	uint16_t FOP;
1805	/** FOO. */
1806	uint32_t FPUOO;
1807	/** FOS. */
1808	uint32_t FPUOS;
1809	/** FPU view - todo. */
1810	X86FPUMMX regs[8];
1811	} X86FPUSTATE;
1812	#pragma pack()
1813	/** Pointer to a FPU state. */
1814	typedef X86FPUSTATE *PX86FPUSTATE;
1815	/** Pointer to a const FPU state. */
1816	typedef const X86FPUSTATE *PCX86FPUSTATE;
1817
1818	/**
1819	* FPU Extended state (aka FXSAVE/FXRSTORE Memory Region).
1820	*/
1821	#pragma pack(1)
1822	typedef struct X86FXSTATE
1823	{
1824	/** Control word. */
1825	uint16_t FCW;
1826	/** Status word. */
1827	uint16_t FSW;
1828	/** Tag word (it's a byte actually). */
1829	uint8_t FTW;
1830	uint8_t huh1;
1831	/** Opcode. */
1832	uint16_t FOP;
1833	/** Instruction pointer. */
1834	uint32_t FPUIP;
1835	/** Code selector. */
1836	uint16_t CS;
1837	uint16_t Rsvrd1;
1838	/* - offset 16 - */
1839	/** Data pointer. */
1840	uint32_t FPUDP;
1841	/** Data segment */
1842	uint16_t DS;
1843	uint16_t Rsrvd2;
1844	uint32_t MXCSR;
1845	uint32_t MXCSR_MASK;
1846	/* - offset 32 - */
1847	union
1848	{
1849	/** MMX view. */
1850	uint64_t mmx;
1851	/** FPU view - todo. */
1852	X86FPUMMX fpu;
1853	/** 8-bit view. */
1854	uint8_t au8[16];
1855	/** 16-bit view. */
1856	uint16_t au16[8];
1857	/** 32-bit view. */
1858	uint32_t au32[4];
1859	/** 64-bit view. */
1860	uint64_t au64[2];
1861	/** 128-bit view. (yeah, very helpful) */
1862	uint128_t au128[1];
1863	} aRegs[8];
1864	/* - offset 160 - */
1865	union
1866	{
1867	/** XMM Register view . /
1868	uint128_t xmm;
1869	/** 8-bit view. */
1870	uint8_t au8[16];
1871	/** 16-bit view. */
1872	uint16_t au16[8];
1873	/** 32-bit view. */
1874	uint32_t au32[4];
1875	/** 64-bit view. */
1876	uint64_t au64[2];
1877	/** 128-bit view. (yeah, very helpful) */
1878	uint128_t au128[1];
1879	} aXMM[16]; /* 8 registers in 32 bits mode; 16 in long mode */
1880	/* - offset 416 - */
1881	uint32_t au32RsrvdRest[(512 - 416) / sizeof(uint32_t)];
1882	} X86FXSTATE;
1883	#pragma pack()
1884	/** Pointer to a FPU Extended state. */
1885	typedef X86FXSTATE *PX86FXSTATE;
1886	/** Pointer to a const FPU Extended state. */
1887	typedef const X86FXSTATE *PCX86FXSTATE;
1888
1889
1890	/** @name Selector Descriptor
1891	* @{
1892	*/
1893
1894	/**
1895	* Generic descriptor table entry
1896	*/
1897	#pragma pack(1)
1898	typedef struct X86DESCGENERIC
1899	{
1900	/** Limit - Low word. */
1901	unsigned u16LimitLow : 16;
1902	/** Base address - lowe word.
1903	* Don't try set this to 24 because MSC is doing studing things then. */
1904	unsigned u16BaseLow : 16;
1905	/** Base address - first 8 bits of high word. */
1906	unsigned u8BaseHigh1 : 8;
1907	/** Segment Type. */
1908	unsigned u4Type : 4;
1909	/** Descriptor Type. System(=0) or code/data selector */
1910	unsigned u1DescType : 1;
1911	/** Descriptor Privelege level. */
1912	unsigned u2Dpl : 2;
1913	/** Flags selector present(=1) or not. */
1914	unsigned u1Present : 1;
1915	/** Segment limit 16-19. */
1916	unsigned u4LimitHigh : 4;
1917	/** Available for system software. */
1918	unsigned u1Available : 1;
1919	/** 32 bits mode: Reserved - 0, long mode: Long Attribute Bit. */
1920	unsigned u1Long : 1;
1921	/** This flags meaning depends on the segment type. Try make sense out
1922	* of the intel manual yourself. */
1923	unsigned u1DefBig : 1;
1924	/** Granularity of the limit. If set 4KB granularity is used, if
1925	* clear byte. */
1926	unsigned u1Granularity : 1;
1927	/** Base address - highest 8 bits. */
1928	unsigned u8BaseHigh2 : 8;
1929	} X86DESCGENERIC;
1930	#pragma pack()
1931	/** Pointer to a generic descriptor entry. */
1932	typedef X86DESCGENERIC *PX86DESCGENERIC;
1933	/** Pointer to a const generic descriptor entry. */
1934	typedef const X86DESCGENERIC *PCX86DESCGENERIC;
1935
1936
1937	/**
1938	* Descriptor attributes.
1939	*/
1940	typedef struct X86DESCATTRBITS
1941	{
1942	/** Segment Type. */
1943	unsigned u4Type : 4;
1944	/** Descriptor Type. System(=0) or code/data selector */
1945	unsigned u1DescType : 1;
1946	/** Descriptor Privelege level. */
1947	unsigned u2Dpl : 2;
1948	/** Flags selector present(=1) or not. */
1949	unsigned u1Present : 1;
1950	/** Segment limit 16-19. */
1951	unsigned u4LimitHigh : 4;
1952	/** Available for system software. */
1953	unsigned u1Available : 1;
1954	/** 32 bits mode: Reserved - 0, long mode: Long Attribute Bit. */
1955	unsigned u1Long : 1;
1956	/** This flags meaning depends on the segment type. Try make sense out
1957	* of the intel manual yourself. */
1958	unsigned u1DefBig : 1;
1959	/** Granularity of the limit. If set 4KB granularity is used, if
1960	* clear byte. */
1961	unsigned u1Granularity : 1;
1962	} X86DESCATTRBITS;
1963
1964
1965	#pragma pack(1)
1966	typedef union X86DESCATTR
1967	{
1968	/** Unsigned integer view. */
1969	uint32_t u;
1970	/** Normal view. */
1971	X86DESCATTRBITS n;
1972	} X86DESCATTR;
1973	#pragma pack()
1974
1975	/** Pointer to descriptor attributes. */
1976	typedef X86DESCATTR *PX86DESCATTR;
1977	/** Pointer to const descriptor attributes. */
1978	typedef const X86DESCATTR *PCX86DESCATTR;
1979
1980
1981	/**
1982	* Descriptor table entry.
1983	*/
1984	#pragma pack(1)
1985	typedef union X86DESC
1986	{
1987	/** Generic descriptor view. */
1988	X86DESCGENERIC Gen;
1989	#if 0
1990	/** IDT view. */
1991	VBOXIDTE Idt;
1992	#endif
1993
1994	/** 8 bit unsigned interger view. */
1995	uint8_t au8[8];
1996	/** 16 bit unsigned interger view. */
1997	uint16_t au16[4];
1998	/** 32 bit unsigned interger view. */
1999	uint32_t au32[2];
2000	} X86DESC;
2001	#pragma pack()
2002	/** Pointer to descriptor table entry. */
2003	typedef X86DESC *PX86DESC;
2004	/** Pointer to const descriptor table entry. */
2005	typedef const X86DESC *PCX86DESC;
2006
2007
2008	/** @def X86DESC_BASE
2009	* Return the base address of a descriptor.
2010	*/
2011	#define X86DESC_BASE(desc) \
2012	( ((uint32_t)((desc).Gen.u8BaseHigh2) << 24) \
2013	\| ( (desc).Gen.u8BaseHigh1 << 16) \
2014	\| ( (desc).Gen.u16BaseLow ) )
2015
2016	/** @def X86DESC_LIMIT
2017	* Return the limit of a descriptor.
2018	*/
2019	#define X86DESC_LIMIT(desc) \
2020	( ((uint32_t)((desc).Gen.u4LimitHigh) << 16) \
2021	\| ( (desc).Gen.u16LimitLow ) )
2022
2023	/**
2024	* 64 bits generic descriptor table entry
2025	* Note: most of these bits have no meaning in long mode.
2026	*/
2027	#pragma pack(1)
2028	typedef struct X86DESC64GENERIC
2029	{
2030	/** Limit - Low word - IGNORED. */
2031	unsigned u16LimitLow : 16;
2032	/** Base address - lowe word. - IGNORED
2033	* Don't try set this to 24 because MSC is doing studing things then. */
2034	unsigned u16BaseLow : 16;
2035	/** Base address - first 8 bits of high word. - IGNORED */
2036	unsigned u8BaseHigh1 : 8;
2037	/** Segment Type. */
2038	unsigned u4Type : 4;
2039	/** Descriptor Type. System(=0) or code/data selector */
2040	unsigned u1DescType : 1;
2041	/** Descriptor Privelege level. */
2042	unsigned u2Dpl : 2;
2043	/** Flags selector present(=1) or not. */
2044	unsigned u1Present : 1;
2045	/** Segment limit 16-19. - IGNORED */
2046	unsigned u4LimitHigh : 4;
2047	/** Available for system software. - IGNORED */
2048	unsigned u1Available : 1;
2049	/** Long mode flag. */
2050	unsigned u1Long : 1;
2051	/** This flags meaning depends on the segment type. Try make sense out
2052	* of the intel manual yourself. */
2053	unsigned u1DefBig : 1;
2054	/** Granularity of the limit. If set 4KB granularity is used, if
2055	* clear byte. - IGNORED */
2056	unsigned u1Granularity : 1;
2057	/** Base address - highest 8 bits. - IGNORED */
2058	unsigned u8BaseHigh2 : 8;
2059	/** Base address - bits 63-32. */
2060	unsigned u32BaseHigh3 : 32;
2061	unsigned u8Reserved : 8;
2062	unsigned u5Zeros : 5;
2063	unsigned u19Reserved : 19;
2064	} X86DESC64GENERIC;
2065	#pragma pack()
2066	/** Pointer to a generic descriptor entry. */
2067	typedef X86DESC64GENERIC *PX86DESC64GENERIC;
2068	/** Pointer to a const generic descriptor entry. */
2069	typedef const X86DESC64GENERIC *PCX86DESC64GENERIC;
2070
2071	/**
2072	* System descriptor table entry (64 bits)
2073	*/
2074	#pragma pack(1)
2075	typedef struct X86DESC64SYSTEM
2076	{
2077	/** Limit - Low word. */
2078	unsigned u16LimitLow : 16;
2079	/** Base address - lowe word.
2080	* Don't try set this to 24 because MSC is doing studing things then. */
2081	unsigned u16BaseLow : 16;
2082	/** Base address - first 8 bits of high word. */
2083	unsigned u8BaseHigh1 : 8;
2084	/** Segment Type. */
2085	unsigned u4Type : 4;
2086	/** Descriptor Type. System(=0) or code/data selector */
2087	unsigned u1DescType : 1;
2088	/** Descriptor Privelege level. */
2089	unsigned u2Dpl : 2;
2090	/** Flags selector present(=1) or not. */
2091	unsigned u1Present : 1;
2092	/** Segment limit 16-19. */
2093	unsigned u4LimitHigh : 4;
2094	/** Available for system software. */
2095	unsigned u1Available : 1;
2096	/** Reserved - 0. */
2097	unsigned u1Reserved : 1;
2098	/** This flags meaning depends on the segment type. Try make sense out
2099	* of the intel manual yourself. */
2100	unsigned u1DefBig : 1;
2101	/** Granularity of the limit. If set 4KB granularity is used, if
2102	* clear byte. */
2103	unsigned u1Granularity : 1;
2104	/** Base address - bits 31-24. */
2105	unsigned u8BaseHigh2 : 8;
2106	/** Base address - bits 63-32. */
2107	unsigned u32BaseHigh3 : 32;
2108	unsigned u8Reserved : 8;
2109	unsigned u5Zeros : 5;
2110	unsigned u19Reserved : 19;
2111	} X86DESC64SYSTEM;
2112	#pragma pack()
2113	/** Pointer to a generic descriptor entry. */
2114	typedef X86DESC64SYSTEM *PX86DESC64SYSTEM;
2115	/** Pointer to a const generic descriptor entry. */
2116	typedef const X86DESC64SYSTEM *PCX86DESC64SYSTEM;
2117
2118
2119	/**
2120	* Descriptor table entry.
2121	*/
2122	#pragma pack(1)
2123	typedef union X86DESC64
2124	{
2125	/** Generic descriptor view. */
2126	X86DESC64GENERIC Gen;
2127	/** System descriptor view. */
2128	X86DESC64SYSTEM System;
2129	#if 0
2130	X86DESC64GATE Gate;
2131	#endif
2132
2133	/** 8 bit unsigned interger view. */
2134	uint8_t au8[16];
2135	/** 16 bit unsigned interger view. */
2136	uint16_t au16[8];
2137	/** 32 bit unsigned interger view. */
2138	uint32_t au32[4];
2139	/** 64 bit unsigned interger view. */
2140	uint64_t au64[2];
2141	} X86DESC64;
2142	#pragma pack()
2143	/** Pointer to descriptor table entry. */
2144	typedef X86DESC64 *PX86DESC64;
2145	/** Pointer to const descriptor table entry. */
2146	typedef const X86DESC64 *PCX86DESC64;
2147
2148	#if HC_ARCH_BITS == 64
2149	typedef X86DESC64 X86DESCHC;
2150	typedef X86DESC64 *PX86DESCHC;
2151	#else
2152	typedef X86DESC X86DESCHC;
2153	typedef X86DESC *PX86DESCHC;
2154	#endif
2155
2156	/** @def X86DESC_LIMIT
2157	* Return the base of a 64-bit descriptor.
2158	*/
2159	#define X86DESC64_BASE(desc) \
2160	( ((uint64_t)((desc).Gen.u32BaseHigh3) << 32) \
2161	\| ((uint32_t)((desc).Gen.u8BaseHigh2) << 24) \
2162	\| ( (desc).Gen.u8BaseHigh1 << 16) \
2163	\| ( (desc).Gen.u16BaseLow ) )
2164
2165
2166	/** @name Selector Descriptor Types.
2167	* @{
2168	*/
2169
2170	/** @name Non-System Selector Types.
2171	* @{ */
2172	/** Code(=set)/Data(=clear) bit. */
2173	#define X86_SEL_TYPE_CODE 8
2174	/** Memory(=set)/System(=clear) bit. */
2175	#define X86_SEL_TYPE_MEMORY RT_BIT(4)
2176	/** Accessed bit. */
2177	#define X86_SEL_TYPE_ACCESSED 1
2178	/** Expand down bit (for data selectors only). */
2179	#define X86_SEL_TYPE_DOWN 4
2180	/** Conforming bit (for code selectors only). */
2181	#define X86_SEL_TYPE_CONF 4
2182	/** Write bit (for data selectors only). */
2183	#define X86_SEL_TYPE_WRITE 2
2184	/** Read bit (for code selectors only). */
2185	#define X86_SEL_TYPE_READ 2
2186
2187	/** Read only selector type. */
2188	#define X86_SEL_TYPE_RO 0
2189	/** Accessed read only selector type. */
2190	#define X86_SEL_TYPE_RO_ACC (0 \| X86_SEL_TYPE_ACCESSED)
2191	/** Read write selector type. */
2192	#define X86_SEL_TYPE_RW 2
2193	/** Accessed read write selector type. */
2194	#define X86_SEL_TYPE_RW_ACC (2 \| X86_SEL_TYPE_ACCESSED)
2195	/** Expand down read only selector type. */
2196	#define X86_SEL_TYPE_RO_DOWN 4
2197	/** Accessed expand down read only selector type. */
2198	#define X86_SEL_TYPE_RO_DOWN_ACC (4 \| X86_SEL_TYPE_ACCESSED)
2199	/** Expand down read write selector type. */
2200	#define X86_SEL_TYPE_RW_DOWN 6
2201	/** Accessed expand down read write selector type. */
2202	#define X86_SEL_TYPE_RW_DOWN_ACC (6 \| X86_SEL_TYPE_ACCESSED)
2203	/** Execute only selector type. */
2204	#define X86_SEL_TYPE_EO (0 \| X86_SEL_TYPE_CODE)
2205	/** Accessed execute only selector type. */
2206	#define X86_SEL_TYPE_EO_ACC (0 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
2207	/** Execute and read selector type. */
2208	#define X86_SEL_TYPE_ER (2 \| X86_SEL_TYPE_CODE)
2209	/** Accessed execute and read selector type. */
2210	#define X86_SEL_TYPE_ER_ACC (2 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
2211	/** Conforming execute only selector type. */
2212	#define X86_SEL_TYPE_EO_CONF (4 \| X86_SEL_TYPE_CODE)
2213	/** Accessed Conforming execute only selector type. */
2214	#define X86_SEL_TYPE_EO_CONF_ACC (4 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
2215	/** Conforming execute and write selector type. */
2216	#define X86_SEL_TYPE_ER_CONF (6 \| X86_SEL_TYPE_CODE)
2217	/** Accessed Conforming execute and write selector type. */
2218	#define X86_SEL_TYPE_ER_CONF_ACC (6 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
2219	/** @} */
2220
2221
2222	/** @name System Selector Types.
2223	* @{ */
2224	/** Undefined system selector type. */
2225	#define X86_SEL_TYPE_SYS_UNDEFINED 0
2226	/** 286 TSS selector. */
2227	#define X86_SEL_TYPE_SYS_286_TSS_AVAIL 1
2228	/** LDT selector. */
2229	#define X86_SEL_TYPE_SYS_LDT 2
2230	/** 286 TSS selector - Busy. */
2231	#define X86_SEL_TYPE_SYS_286_TSS_BUSY 3
2232	/** 286 Callgate selector. */
2233	#define X86_SEL_TYPE_SYS_286_CALL_GATE 4
2234	/** Taskgate selector. */
2235	#define X86_SEL_TYPE_SYS_TASK_GATE 5
2236	/** 286 Interrupt gate selector. */
2237	#define X86_SEL_TYPE_SYS_286_INT_GATE 6
2238	/** 286 Trapgate selector. */
2239	#define X86_SEL_TYPE_SYS_286_TRAP_GATE 7
2240	/** Undefined system selector. */
2241	#define X86_SEL_TYPE_SYS_UNDEFINED2 8
2242	/** 386 TSS selector. */
2243	#define X86_SEL_TYPE_SYS_386_TSS_AVAIL 9
2244	/** Undefined system selector. */
2245	#define X86_SEL_TYPE_SYS_UNDEFINED3 0xA
2246	/** 386 TSS selector - Busy. */
2247	#define X86_SEL_TYPE_SYS_386_TSS_BUSY 0xB
2248	/** 386 Callgate selector. */
2249	#define X86_SEL_TYPE_SYS_386_CALL_GATE 0xC
2250	/** Undefined system selector. */
2251	#define X86_SEL_TYPE_SYS_UNDEFINED4 0xD
2252	/** 386 Interruptgate selector. */
2253	#define X86_SEL_TYPE_SYS_386_INT_GATE 0xE
2254	/** 386 Trapgate selector. */
2255	#define X86_SEL_TYPE_SYS_386_TRAP_GATE 0xF
2256	/** @} */
2257
2258	/** @name AMD64 System Selector Types.
2259	* @{ */
2260	#define AMD64_SEL_TYPE_SYS_LDT 2
2261	/** 286 TSS selector - Busy. */
2262	#define AMD64_SEL_TYPE_SYS_TSS_AVAIL 9
2263	/** 386 TSS selector - Busy. */
2264	#define AMD64_SEL_TYPE_SYS_TSS_BUSY 0xB
2265	/** 386 Callgate selector. */
2266	#define AMD64_SEL_TYPE_SYS_CALL_GATE 0xC
2267	/** 386 Interruptgate selector. */
2268	#define AMD64_SEL_TYPE_SYS_INT_GATE 0xE
2269	/** 386 Trapgate selector. */
2270	#define AMD64_SEL_TYPE_SYS_TRAP_GATE 0xF
2271	/** @} */
2272
2273	/** @} */
2274
2275
2276	/** @name Descriptor Table Entry Flag Masks.
2277	* These are for the 2nd 32-bit word of a descriptor.
2278	* @{ */
2279	/** Bits 8-11 - TYPE - Descriptor type mask. */
2280	#define X86_DESC_TYPE_MASK (RT_BIT(8) \| RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
2281	/** Bit 12 - S - System (=0) or Code/Data (=1). */
2282	#define X86_DESC_S RT_BIT(12)
2283	/** Bits 13-14 - DPL - Descriptor Privilege Level. */
2284	#define X86_DESC_DPL (RT_BIT(13) \| RT_BIT(14))
2285	/** Bit 15 - P - Present. */
2286	#define X86_DESC_P RT_BIT(15)
2287	/** Bit 20 - AVL - Available for system software. */
2288	#define X86_DESC_AVL RT_BIT(20)
2289	/** Bit 22 - DB - Default operation size. 0 = 16 bit, 1 = 32 bit. */
2290	#define X86_DESC_DB RT_BIT(22)
2291	/** Bit 23 - G - Granularity of the limit. If set 4KB granularity is
2292	* used, if clear byte. */
2293	#define X86_DESC_G RT_BIT(23)
2294	/** @} */
2295
2296	/** @} */
2297
2298	/** @name Task segment.
2299	* @{
2300	*/
2301	#pragma pack(1)
2302	typedef struct X86TSS32
2303	{
2304	/** Back link to previous task. (static) */
2305	RTSEL selPrev;
2306	uint16_t padding1;
2307	/** Ring-0 stack pointer. (static) */
2308	uint32_t esp0;
2309	/** Ring-0 stack segment. (static) */
2310	RTSEL ss0;
2311	uint16_t padding_ss0;
2312	/** Ring-1 stack pointer. (static) */
2313	uint32_t esp1;
2314	/** Ring-1 stack segment. (static) */
2315	RTSEL ss1;
2316	uint16_t padding_ss1;
2317	/** Ring-2 stack pointer. (static) */
2318	uint32_t esp2;
2319	/** Ring-2 stack segment. (static) */
2320	RTSEL ss2;
2321	uint16_t padding_ss2;
2322	/** Page directory for the task. (static) */
2323	uint32_t cr3;
2324	/** EIP before task switch. */
2325	uint32_t eip;
2326	/** EFLAGS before task switch. */
2327	uint32_t eflags;
2328	/** EAX before task switch. */
2329	uint32_t eax;
2330	/** ECX before task switch. */
2331	uint32_t ecx;
2332	/** EDX before task switch. */
2333	uint32_t edx;
2334	/** EBX before task switch. */
2335	uint32_t ebx;
2336	/** ESP before task switch. */
2337	uint32_t esp;
2338	/** EBP before task switch. */
2339	uint32_t ebp;
2340	/** ESI before task switch. */
2341	uint32_t esi;
2342	/** EDI before task switch. */
2343	uint32_t edi;
2344	/** ES before task switch. */
2345	RTSEL es;
2346	uint16_t padding_es;
2347	/** CS before task switch. */
2348	RTSEL cs;
2349	uint16_t padding_cs;
2350	/** SS before task switch. */
2351	RTSEL ss;
2352	uint16_t padding_ss;
2353	/** DS before task switch. */
2354	RTSEL ds;
2355	uint16_t padding_ds;
2356	/** FS before task switch. */
2357	RTSEL fs;
2358	uint16_t padding_fs;
2359	/** GS before task switch. */
2360	RTSEL gs;
2361	uint16_t padding_gs;
2362	/** LDTR before task switch. */
2363	RTSEL selLdt;
2364	uint16_t padding_ldt;
2365	/** Debug trap flag */
2366	uint16_t fDebugTrap;
2367	/** Offset relative to the TSS of the start of the I/O Bitmap
2368	* and the end of the interrupt redirection bitmap. */
2369	uint16_t offIoBitmap;
2370	/** 32 bytes for the virtual interrupt redirection bitmap. (VME) */
2371	uint8_t IntRedirBitmap[32];
2372	} X86TSS32;
2373	#pragma pack()
2374	/** Pointer to task segment. */
2375	typedef X86TSS32 *PX86TSS32;
2376	/** Pointer to const task segment. */
2377	typedef const X86TSS32 *PCX86TSS32;
2378	/** @} */
2379
2380
2381	/** @name 64 bits Task segment.
2382	* @{
2383	*/
2384	#pragma pack(1)
2385	typedef struct X86TSS64
2386	{
2387	/** Reserved. */
2388	uint32_t u32Reserved;
2389	/** Ring-0 stack pointer. (static) */
2390	uint64_t rsp0;
2391	/** Ring-1 stack pointer. (static) */
2392	uint64_t rsp1;
2393	/** Ring-2 stack pointer. (static) */
2394	uint64_t rsp2;
2395	/** Reserved. */
2396	uint32_t u32Reserved2[2];
2397	/* IST */
2398	uint64_t ist1;
2399	uint64_t ist2;
2400	uint64_t ist3;
2401	uint64_t ist4;
2402	uint64_t ist5;
2403	uint64_t ist6;
2404	uint64_t ist7;
2405	/* Reserved. */
2406	uint16_t u16Reserved[5];
2407	/** Offset relative to the TSS of the start of the I/O Bitmap
2408	* and the end of the interrupt redirection bitmap. */
2409	uint16_t offIoBitmap;
2410	/** 32 bytes for the virtual interrupt redirection bitmap. (VME) */
2411	uint8_t IntRedirBitmap[32];
2412	} X86TSS64;
2413	#pragma pack()
2414	/** Pointer to task segment. */
2415	typedef X86TSS64 *PX86TSS64;
2416	/** Pointer to const task segment. */
2417	typedef const X86TSS64 *PCX86TSS64;
2418	AssertCompileSize(X86TSS64, 136);
2419
2420	/** @} */
2421
2422
2423	/** @name Selectors.
2424	* @{
2425	*/
2426
2427	/**
2428	* The shift used to convert a selector from and to index an index (C).
2429	*/
2430	#define X86_SEL_SHIFT 3
2431
2432	/**
2433	* The shift used to convert a selector from and to index an index (C).
2434	*/
2435	#define AMD64_SEL_SHIFT 4
2436
2437	/** @def X86_SEL_SHIFT_HC
2438	* This is for use with X86DESCHC. */
2439	#if HC_ARCH_BITS == 64
2440	#define X86_SEL_SHIFT_HC AMD64_SEL_SHIFT
2441	#else
2442	#define X86_SEL_SHIFT_HC X86_SEL_SHIFT
2443	#endif
2444
2445	/**
2446	* The mask used to mask off the table indicator and CPL of an selector.
2447	*/
2448	#define X86_SEL_MASK 0xfff8
2449
2450	/**
2451	* The bit indicating that a selector is in the LDT and not in the GDT.
2452	*/
2453	#define X86_SEL_LDT 0x0004
2454	/**
2455	* The bit mask for getting the RPL of a selector.
2456	*/
2457	#define X86_SEL_RPL 0x0003
2458
2459	/** @} */
2460
2461
2462	/**
2463	* x86 Exceptions/Faults/Traps.
2464	*/
2465	typedef enum X86XCPT
2466	{
2467	/** \#DE - Divide error. */
2468	X86_XCPT_DE = 0x00,
2469	/** \#DB - Debug event (single step, DRx, ..) */
2470	X86_XCPT_DB = 0x01,
2471	/** NMI - Non-Maskable Interrupt */
2472	X86_XCPT_NMI = 0x02,
2473	/** \#BP - Breakpoint (INT3). */
2474	X86_XCPT_BP = 0x03,
2475	/** \#OF - Overflow (INTO). */
2476	X86_XCPT_OF = 0x04,
2477	/** \#BR - Bound range exceeded (BOUND). */
2478	X86_XCPT_BR = 0x05,
2479	/** \#UD - Undefined opcode. */
2480	X86_XCPT_UD = 0x06,
2481	/** \#NM - Device not available (math coprocessor device). */
2482	X86_XCPT_NM = 0x07,
2483	/** \#DF - Double fault. */
2484	X86_XCPT_DF = 0x08,
2485	/** ??? - Coprocessor segment overrun (obsolete). */
2486	X86_XCPT_CO_SEG_OVERRUN = 0x09,
2487	/** \#TS - Taskswitch (TSS). */
2488	X86_XCPT_TS = 0x0a,
2489	/** \#NP - Segment no present. */
2490	X86_XCPT_NP = 0x0b,
2491	/** \#SS - Stack segment fault. */
2492	X86_XCPT_SS = 0x0c,
2493	/** \#GP - General protection fault. */
2494	X86_XCPT_GP = 0x0d,
2495	/** \#PF - Page fault. */
2496	X86_XCPT_PF = 0x0e,
2497	/* 0x0f is reserved. */
2498	/** \#MF - Math fault (FPU). */
2499	X86_XCPT_MF = 0x10,
2500	/** \#AC - Alignment check. */
2501	X86_XCPT_AC = 0x11,
2502	/** \#MC - Machine check. */
2503	X86_XCPT_MC = 0x12,
2504	/** \#XF - SIMD Floating-Pointer Exception. */
2505	X86_XCPT_XF = 0x13
2506	} X86XCPT;
2507	/** Pointer to a x86 exception code. */
2508	typedef X86XCPT *PX86XCPT;
2509	/** Pointer to a const x86 exception code. */
2510	typedef const X86XCPT *PCX86XCPT;
2511
2512
2513	/** @name Trap Error Codes
2514	* @{
2515	*/
2516	/** External indicator. */
2517	#define X86_TRAP_ERR_EXTERNAL 1
2518	/** IDT indicator. */
2519	#define X86_TRAP_ERR_IDT 2
2520	/** Descriptor table indicator - If set LDT, if clear GDT. */
2521	#define X86_TRAP_ERR_TI 4
2522	/** Mask for getting the selector. */
2523	#define X86_TRAP_ERR_SEL_MASK 0xfff8
2524	/** Shift for getting the selector table index (C type index). */
2525	#define X86_TRAP_ERR_SEL_SHIFT 3
2526	/** @} */
2527
2528
2529	/** @name \#PF Trap Error Codes
2530	* @{
2531	*/
2532	/** Bit 0 - P - Not present (clear) or page level protection (set) fault. */
2533	#define X86_TRAP_PF_P RT_BIT(0)
2534	/** Bit 1 - R/W - Read (clear) or write (set) access. */
2535	#define X86_TRAP_PF_RW RT_BIT(1)
2536	/** Bit 2 - U/S - CPU executing in user mode (set) or supervisor mode (clear). */
2537	#define X86_TRAP_PF_US RT_BIT(2)
2538	/** Bit 3 - RSVD- Reserved bit violation (set), i.e. reserved bit was set to 1. */
2539	#define X86_TRAP_PF_RSVD RT_BIT(3)
2540	/** Bit 4 - I/D - Instruction fetch (set) / Data access (clear) - PAE + NXE. */
2541	#define X86_TRAP_PF_ID RT_BIT(4)
2542	/** @} */
2543
2544	#pragma pack(1)
2545	/**
2546	* 32-bit IDTR/GDTR.
2547	*/
2548	typedef struct X86XDTR32
2549	{
2550	/** Size of the descriptor table. */
2551	uint16_t cb;
2552	/** Address of the descriptor table. */
2553	uint32_t uAddr;
2554	} X86XDTR32, *PX86XDTR32;
2555	#pragma pack()
2556
2557	#pragma pack(1)
2558	/**
2559	* 64-bit IDTR/GDTR.
2560	*/
2561	typedef struct X86XDTR64
2562	{
2563	/** Size of the descriptor table. */
2564	uint16_t cb;
2565	/** Address of the descriptor table. */
2566	uint64_t uAddr;
2567	} X86XDTR64, *PX86XDTR64;
2568	#pragma pack()
2569
2570	/** @} */
2571
2572	#endif
2573

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source: vbox/trunk/include/VBox/x86.h@ 18189

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