x86.h@ 27319

Last change on this file since 27319 was 27319, checked in by vboxsync, 15 years ago
Added MSR_IA32_MISC_ENABLE
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1	/** @file
2	* X86 (and AMD64) Structures and Definitions (VMM,++).
3	*
4	* x86.mac is generated from this file by running 'kmk incs' in the root.
5	*/
6
7	/*
8	* Copyright (C) 2006-2009 Sun Microsystems, Inc.
9	*
10	* This file is part of VirtualBox Open Source Edition (OSE), as
11	* available from http://www.virtualbox.org. This file is free software;
12	* you can redistribute it and/or modify it under the terms of the GNU
13	* General Public License (GPL) as published by the Free Software
14	* Foundation, in version 2 as it comes in the "COPYING" file of the
15	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
16	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
17	*
18	* The contents of this file may alternatively be used under the terms
19	* of the Common Development and Distribution License Version 1.0
20	* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
21	* VirtualBox OSE distribution, in which case the provisions of the
22	* CDDL are applicable instead of those of the GPL.
23	*
24	* You may elect to license modified versions of this file under the
25	* terms and conditions of either the GPL or the CDDL or both.
26	*
27	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
28	* Clara, CA 95054 USA or visit http://www.sun.com if you need
29	* additional information or have any questions.
30	*/
31
32	#ifndef ___VBox_x86_h
33	#define ___VBox_x86_h
34
35	#include <VBox/types.h>
36	#include <iprt/assert.h>
37
38	/* Workaround for Solaris sys/regset.h defining CS, DS */
39	#ifdef RT_OS_SOLARIS
40	# undef CS
41	# undef DS
42	#endif
43
44	/** @defgroup grp_x86 x86 Types and Definitions
45	* @{
46	*/
47
48	/**
49	* EFLAGS Bits.
50	*/
51	typedef struct X86EFLAGSBITS
52	{
53	/** Bit 0 - CF - Carry flag - Status flag. */
54	unsigned u1CF : 1;
55	/** Bit 1 - 1 - Reserved flag. */
56	unsigned u1Reserved0 : 1;
57	/** Bit 2 - PF - Parity flag - Status flag. */
58	unsigned u1PF : 1;
59	/** Bit 3 - 0 - Reserved flag. */
60	unsigned u1Reserved1 : 1;
61	/** Bit 4 - AF - Auxiliary carry flag - Status flag. */
62	unsigned u1AF : 1;
63	/** Bit 5 - 0 - Reserved flag. */
64	unsigned u1Reserved2 : 1;
65	/** Bit 6 - ZF - Zero flag - Status flag. */
66	unsigned u1ZF : 1;
67	/** Bit 7 - SF - Signed flag - Status flag. */
68	unsigned u1SF : 1;
69	/** Bit 8 - TF - Trap flag - System flag. */
70	unsigned u1TF : 1;
71	/** Bit 9 - IF - Interrupt flag - System flag. */
72	unsigned u1IF : 1;
73	/** Bit 10 - DF - Direction flag - Control flag. */
74	unsigned u1DF : 1;
75	/** Bit 11 - OF - Overflow flag - Status flag. */
76	unsigned u1OF : 1;
77	/** Bit 12-13 - IOPL - I/O prvilege level flag - System flag. */
78	unsigned u2IOPL : 2;
79	/** Bit 14 - NT - Nested task flag - System flag. */
80	unsigned u1NT : 1;
81	/** Bit 15 - 0 - Reserved flag. */
82	unsigned u1Reserved3 : 1;
83	/** Bit 16 - RF - Resume flag - System flag. */
84	unsigned u1RF : 1;
85	/** Bit 17 - VM - Virtual 8086 mode - System flag. */
86	unsigned u1VM : 1;
87	/** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
88	unsigned u1AC : 1;
89	/** Bit 19 - VIF - Virtual interupt flag - System flag. */
90	unsigned u1VIF : 1;
91	/** Bit 20 - VIP - Virtual interupt pending flag - System flag. */
92	unsigned u1VIP : 1;
93	/** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
94	unsigned u1ID : 1;
95	/** Bit 22-31 - 0 - Reserved flag. */
96	unsigned u10Reserved4 : 10;
97	} X86EFLAGSBITS;
98	/** Pointer to EFLAGS bits. */
99	typedef X86EFLAGSBITS *PX86EFLAGSBITS;
100	/** Pointer to const EFLAGS bits. */
101	typedef const X86EFLAGSBITS *PCX86EFLAGSBITS;
102
103	/**
104	* EFLAGS.
105	*/
106	typedef union X86EFLAGS
107	{
108	/** The plain unsigned view. */
109	uint32_t u;
110	/** The bitfield view. */
111	X86EFLAGSBITS Bits;
112	/** The 8-bit view. */
113	uint8_t au8[4];
114	/** The 16-bit view. */
115	uint16_t au16[2];
116	/** The 32-bit view. */
117	uint32_t au32[1];
118	/** The 32-bit view. */
119	uint32_t u32;
120	} X86EFLAGS;
121	/** Pointer to EFLAGS. */
122	typedef X86EFLAGS *PX86EFLAGS;
123	/** Pointer to const EFLAGS. */
124	typedef const X86EFLAGS *PCX86EFLAGS;
125
126	/**
127	* RFLAGS (32 upper bits are reserved).
128	*/
129	typedef union X86RFLAGS
130	{
131	/** The plain unsigned view. */
132	uint64_t u;
133	/** The bitfield view. */
134	X86EFLAGSBITS Bits;
135	/** The 8-bit view. */
136	uint8_t au8[8];
137	/** The 16-bit view. */
138	uint16_t au16[4];
139	/** The 32-bit view. */
140	uint32_t au32[2];
141	/** The 64-bit view. */
142	uint64_t au64[1];
143	/** The 64-bit view. */
144	uint64_t u64;
145	} X86RFLAGS;
146	/** Pointer to RFLAGS. */
147	typedef X86RFLAGS *PX86RFLAGS;
148	/** Pointer to const RFLAGS. */
149	typedef const X86RFLAGS *PCX86RFLAGS;
150
151
152	/** @name EFLAGS
153	* @{
154	*/
155	/** Bit 0 - CF - Carry flag - Status flag. */
156	#define X86_EFL_CF RT_BIT(0)
157	/** Bit 2 - PF - Parity flag - Status flag. */
158	#define X86_EFL_PF RT_BIT(2)
159	/** Bit 4 - AF - Auxiliary carry flag - Status flag. */
160	#define X86_EFL_AF RT_BIT(4)
161	/** Bit 6 - ZF - Zero flag - Status flag. */
162	#define X86_EFL_ZF RT_BIT(6)
163	/** Bit 7 - SF - Signed flag - Status flag. */
164	#define X86_EFL_SF RT_BIT(7)
165	/** Bit 8 - TF - Trap flag - System flag. */
166	#define X86_EFL_TF RT_BIT(8)
167	/** Bit 9 - IF - Interrupt flag - System flag. */
168	#define X86_EFL_IF RT_BIT(9)
169	/** Bit 10 - DF - Direction flag - Control flag. */
170	#define X86_EFL_DF RT_BIT(10)
171	/** Bit 11 - OF - Overflow flag - Status flag. */
172	#define X86_EFL_OF RT_BIT(11)
173	/** Bit 12-13 - IOPL - I/O prvilege level flag - System flag. */
174	#define X86_EFL_IOPL (RT_BIT(12) \| RT_BIT(13))
175	/** Bit 14 - NT - Nested task flag - System flag. */
176	#define X86_EFL_NT RT_BIT(14)
177	/** Bit 16 - RF - Resume flag - System flag. */
178	#define X86_EFL_RF RT_BIT(16)
179	/** Bit 17 - VM - Virtual 8086 mode - System flag. */
180	#define X86_EFL_VM RT_BIT(17)
181	/** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
182	#define X86_EFL_AC RT_BIT(18)
183	/** Bit 19 - VIF - Virtual interupt flag - System flag. */
184	#define X86_EFL_VIF RT_BIT(19)
185	/** Bit 20 - VIP - Virtual interupt pending flag - System flag. */
186	#define X86_EFL_VIP RT_BIT(20)
187	/** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
188	#define X86_EFL_ID RT_BIT(21)
189	/** IOPL shift. */
190	#define X86_EFL_IOPL_SHIFT 12
191	/** The the IOPL level from the flags. */
192	#define X86_EFL_GET_IOPL(efl) (((efl) >> X86_EFL_IOPL_SHIFT) & 3)
193	/** Bits restored by popf */
194	#define X86_EFL_POPF_BITS (X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_TF \| X86_EFL_IF \| X86_EFL_DF \| X86_EFL_OF \| X86_EFL_IOPL \| X86_EFL_NT \| X86_EFL_AC \| X86_EFL_ID)
195	/** @} */
196
197
198	/** CPUID Feature information - ECX.
199	* CPUID query with EAX=1.
200	*/
201	typedef struct X86CPUIDFEATECX
202	{
203	/** Bit 0 - SSE3 - Supports SSE3 or not. */
204	unsigned u1SSE3 : 1;
205	/** Reserved. */
206	unsigned u1Reserved1 : 1;
207	/** Bit 2 - DS Area 64-bit layout. */
208	unsigned u1DTE64 : 1;
209	/** Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
210	unsigned u1Monitor : 1;
211	/** Bit 4 - CPL-DS - CPL Qualified Debug Store. */
212	unsigned u1CPLDS : 1;
213	/** Bit 5 - VMX - Virtual Machine Technology. */
214	unsigned u1VMX : 1;
215	/** Bit 6 - SMX: Safer Mode Extensions. */
216	unsigned u1SMX : 1;
217	/** Bit 7 - EST - Enh. SpeedStep Tech. */
218	unsigned u1EST : 1;
219	/** Bit 8 - TM2 - Terminal Monitor 2. */
220	unsigned u1TM2 : 1;
221	/** Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
222	unsigned u1SSSE3 : 1;
223	/** Bit 10 - CNTX-ID - L1 Context ID. */
224	unsigned u1CNTXID : 1;
225	/** Bit 11 - FMA. */
226	unsigned u1FMA : 1;
227	/** Bit 12 - Reserved. */
228	unsigned u1Reserved2 : 1;
229	/** Bit 13 - CX16 - CMPXCHG16B. */
230	unsigned u1CX16 : 1;
231	/** Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
232	unsigned u1TPRUpdate : 1;
233	/** Bit 15 - PDCM - Perf/Debug Capability MSR. */
234	unsigned u1PDCM : 1;
235	/** Reserved. */
236	unsigned u2Reserved3 : 2;
237	/** Bit 18 - Direct Cache Access. */
238	unsigned u1DCA : 1;
239	/** Bit 19 - SSE4_1 - Supports SSE4_1 or not. */
240	unsigned u1SSE4_1 : 1;
241	/** Bit 20 - SSE4_2 - Supports SSE4_2 or not. */
242	unsigned u1SSE4_2 : 1;
243	/** Bit 21 - x2APIC. */
244	unsigned u1x2APIC : 1;
245	/** Bit 22 - MOVBE - Supports MOVBE. */
246	unsigned u1MOVBE : 1;
247	/** Bit 23 - POPCNT - Supports POPCNT. */
248	unsigned u1POPCNT : 1;
249	/** Bit 24 - Reserved. */
250	unsigned u1Reserved4 : 1;
251	/** Bit 25 - AES. */
252	unsigned u1AES : 1;
253	/** Bit 26 - XSAVE - Supports XSAVE. */
254	unsigned u1XSAVE : 1;
255	/** Bit 27 - OSXSAVE - Supports OSXSAVE. */
256	unsigned u1OSXSAVE : 1;
257	/** Reserved. */
258	unsigned u4Reserved5 : 4;
259	} X86CPUIDFEATECX;
260	/** Pointer to CPUID Feature Information - ECX. */
261	typedef X86CPUIDFEATECX *PX86CPUIDFEATECX;
262	/** Pointer to const CPUID Feature Information - ECX. */
263	typedef const X86CPUIDFEATECX *PCX86CPUIDFEATECX;
264
265
266	/** CPUID Feature Information - EDX.
267	* CPUID query with EAX=1.
268	*/
269	typedef struct X86CPUIDFEATEDX
270	{
271	/** Bit 0 - FPU - x87 FPU on Chip. */
272	unsigned u1FPU : 1;
273	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
274	unsigned u1VME : 1;
275	/** Bit 2 - DE - Debugging extensions. */
276	unsigned u1DE : 1;
277	/** Bit 3 - PSE - Page Size Extension. */
278	unsigned u1PSE : 1;
279	/** Bit 4 - TSC - Time Stamp Counter. */
280	unsigned u1TSC : 1;
281	/** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
282	unsigned u1MSR : 1;
283	/** Bit 6 - PAE - Physical Address Extension. */
284	unsigned u1PAE : 1;
285	/** Bit 7 - MCE - Machine Check Exception. */
286	unsigned u1MCE : 1;
287	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
288	unsigned u1CX8 : 1;
289	/** Bit 9 - APIC - APIC On-Chip. */
290	unsigned u1APIC : 1;
291	/** Bit 10 - Reserved. */
292	unsigned u1Reserved1 : 1;
293	/** Bit 11 - SEP - SYSENTER and SYSEXIT. */
294	unsigned u1SEP : 1;
295	/** Bit 12 - MTRR - Memory Type Range Registers. */
296	unsigned u1MTRR : 1;
297	/** Bit 13 - PGE - PTE Global Bit. */
298	unsigned u1PGE : 1;
299	/** Bit 14 - MCA - Machine Check Architecture. */
300	unsigned u1MCA : 1;
301	/** Bit 15 - CMOV - Conditional Move Instructions. */
302	unsigned u1CMOV : 1;
303	/** Bit 16 - PAT - Page Attribute Table. */
304	unsigned u1PAT : 1;
305	/** Bit 17 - PSE-36 - 36-bit Page Size Extention. */
306	unsigned u1PSE36 : 1;
307	/** Bit 18 - PSN - Processor Serial Number. */
308	unsigned u1PSN : 1;
309	/** Bit 19 - CLFSH - CLFLUSH Instruction. */
310	unsigned u1CLFSH : 1;
311	/** Bit 20 - Reserved. */
312	unsigned u1Reserved2 : 1;
313	/** Bit 21 - DS - Debug Store. */
314	unsigned u1DS : 1;
315	/** Bit 22 - ACPI - Thermal Monitor and Software Controlled Clock Facilities. */
316	unsigned u1ACPI : 1;
317	/** Bit 23 - MMX - Intel MMX 'Technology'. */
318	unsigned u1MMX : 1;
319	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
320	unsigned u1FXSR : 1;
321	/** Bit 25 - SSE - SSE Support. */
322	unsigned u1SSE : 1;
323	/** Bit 26 - SSE2 - SSE2 Support. */
324	unsigned u1SSE2 : 1;
325	/** Bit 27 - SS - Self Snoop. */
326	unsigned u1SS : 1;
327	/** Bit 28 - HTT - Hyper-Threading Technology. */
328	unsigned u1HTT : 1;
329	/** Bit 29 - TM - Thermal Monitor. */
330	unsigned u1TM : 1;
331	/** Bit 30 - Reserved - . */
332	unsigned u1Reserved3 : 1;
333	/** Bit 31 - PBE - Pending Break Enabled. */
334	unsigned u1PBE : 1;
335	} X86CPUIDFEATEDX;
336	/** Pointer to CPUID Feature Information - EDX. */
337	typedef X86CPUIDFEATEDX *PX86CPUIDFEATEDX;
338	/** Pointer to const CPUID Feature Information - EDX. */
339	typedef const X86CPUIDFEATEDX *PCX86CPUIDFEATEDX;
340
341	/** @name CPUID Vendor information.
342	* CPUID query with EAX=0.
343	* @{
344	*/
345	#define X86_CPUID_VENDOR_INTEL_EBX 0x756e6547 /* Genu */
346	#define X86_CPUID_VENDOR_INTEL_ECX 0x6c65746e /* ntel */
347	#define X86_CPUID_VENDOR_INTEL_EDX 0x49656e69 /* ineI */
348
349	#define X86_CPUID_VENDOR_AMD_EBX 0x68747541 /* Auth */
350	#define X86_CPUID_VENDOR_AMD_ECX 0x444d4163 /* cAMD */
351	#define X86_CPUID_VENDOR_AMD_EDX 0x69746e65 /* enti */
352	/** @} */
353
354
355	/** @name CPUID Feature information.
356	* CPUID query with EAX=1.
357	* @{
358	*/
359	/** ECX Bit 0 - SSE3 - Supports SSE3 or not. */
360	#define X86_CPUID_FEATURE_ECX_SSE3 RT_BIT(0)
361	/** ECX Bit 1 - PCLMUL - PCLMULQDQ support (for AES-GCM). */
362	#define X86_CPUID_FEATURE_ECX_PCLMUL RT_BIT(1)
363	/** ECX Bit 2 - DTES64 - DS Area 64-bit Layout. */
364	#define X86_CPUID_FEATURE_ECX_DTES64 RT_BIT(2)
365	/** ECX Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
366	#define X86_CPUID_FEATURE_ECX_MONITOR RT_BIT(3)
367	/** ECX Bit 4 - CPL-DS - CPL Qualified Debug Store. */
368	#define X86_CPUID_FEATURE_ECX_CPLDS RT_BIT(4)
369	/** ECX Bit 5 - VMX - Virtual Machine Technology. */
370	#define X86_CPUID_FEATURE_ECX_VMX RT_BIT(5)
371	/** ECX Bit 6 - SMX - Safer Mode Extensions. */
372	#define X86_CPUID_FEATURE_ECX_SMX RT_BIT(6)
373	/** ECX Bit 7 - EST - Enh. SpeedStep Tech. */
374	#define X86_CPUID_FEATURE_ECX_EST RT_BIT(7)
375	/** ECX Bit 8 - TM2 - Terminal Monitor 2. */
376	#define X86_CPUID_FEATURE_ECX_TM2 RT_BIT(8)
377	/** ECX Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
378	#define X86_CPUID_FEATURE_ECX_SSSE3 RT_BIT(9)
379	/** ECX Bit 10 - CNTX-ID - L1 Context ID. */
380	#define X86_CPUID_FEATURE_ECX_CNTXID RT_BIT(10)
381	/** ECX Bit 12 - FMA. */
382	#define X86_CPUID_FEATURE_ECX_FMA RT_BIT(12)
383	/** ECX Bit 13 - CX16 - CMPXCHG16B. */
384	#define X86_CPUID_FEATURE_ECX_CX16 RT_BIT(13)
385	/** ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
386	#define X86_CPUID_FEATURE_ECX_TPRUPDATE RT_BIT(14)
387	/** ECX Bit 15 - PDCM - Perf/Debug Capability MSR. */
388	#define X86_CPUID_FEATURE_ECX_PDCM RT_BIT(15)
389	/** ECX Bit 18 - DCA - Direct Cache Access. */
390	#define X86_CPUID_FEATURE_ECX_DCA RT_BIT(18)
391	/** ECX Bit 19 - SSE4_1 - Supports SSE4_1 or not. */
392	#define X86_CPUID_FEATURE_ECX_SSE4_1 RT_BIT(19)
393	/** ECX Bit 20 - SSE4_2 - Supports SSE4_2 or not. */
394	#define X86_CPUID_FEATURE_ECX_SSE4_2 RT_BIT(20)
395	/** ECX Bit 21 - x2APIC support. */
396	#define X86_CPUID_FEATURE_ECX_X2APIC RT_BIT(21)
397	/** ECX Bit 22 - MOVBE instruction. */
398	#define X86_CPUID_FEATURE_ECX_MOVBE RT_BIT(22)
399	/** ECX Bit 23 - POPCNT instruction. */
400	#define X86_CPUID_FEATURE_ECX_POPCNT RT_BIT(23)
401	/** ECX Bit 25 - AES instructions. */
402	#define X86_CPUID_FEATURE_ECX_AES RT_BIT(25)
403	/** ECX Bit 26 - XSAVE instruction. */
404	#define X86_CPUID_FEATURE_ECX_XSAVE RT_BIT(26)
405	/** ECX Bit 27 - OSXSAVE instruction. */
406	#define X86_CPUID_FEATURE_ECX_OSXSAVE RT_BIT(27)
407	/** ECX Bit 28 - AVX. */
408	#define X86_CPUID_FEATURE_ECX_AVX RT_BIT(28)
409
410
411	/** Bit 0 - FPU - x87 FPU on Chip. */
412	#define X86_CPUID_FEATURE_EDX_FPU RT_BIT(0)
413	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
414	#define X86_CPUID_FEATURE_EDX_VME RT_BIT(1)
415	/** Bit 2 - DE - Debugging extensions. */
416	#define X86_CPUID_FEATURE_EDX_DE RT_BIT(2)
417	/** Bit 3 - PSE - Page Size Extension. */
418	#define X86_CPUID_FEATURE_EDX_PSE RT_BIT(3)
419	/** Bit 4 - TSC - Time Stamp Counter. */
420	#define X86_CPUID_FEATURE_EDX_TSC RT_BIT(4)
421	/** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
422	#define X86_CPUID_FEATURE_EDX_MSR RT_BIT(5)
423	/** Bit 6 - PAE - Physical Address Extension. */
424	#define X86_CPUID_FEATURE_EDX_PAE RT_BIT(6)
425	/** Bit 7 - MCE - Machine Check Exception. */
426	#define X86_CPUID_FEATURE_EDX_MCE RT_BIT(7)
427	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
428	#define X86_CPUID_FEATURE_EDX_CX8 RT_BIT(8)
429	/** Bit 9 - APIC - APIC On-Chip. */
430	#define X86_CPUID_FEATURE_EDX_APIC RT_BIT(9)
431	/** Bit 11 - SEP - SYSENTER and SYSEXIT. */
432	#define X86_CPUID_FEATURE_EDX_SEP RT_BIT(11)
433	/** Bit 12 - MTRR - Memory Type Range Registers. */
434	#define X86_CPUID_FEATURE_EDX_MTRR RT_BIT(12)
435	/** Bit 13 - PGE - PTE Global Bit. */
436	#define X86_CPUID_FEATURE_EDX_PGE RT_BIT(13)
437	/** Bit 14 - MCA - Machine Check Architecture. */
438	#define X86_CPUID_FEATURE_EDX_MCA RT_BIT(14)
439	/** Bit 15 - CMOV - Conditional Move Instructions. */
440	#define X86_CPUID_FEATURE_EDX_CMOV RT_BIT(15)
441	/** Bit 16 - PAT - Page Attribute Table. */
442	#define X86_CPUID_FEATURE_EDX_PAT RT_BIT(16)
443	/** Bit 17 - PSE-36 - 36-bit Page Size Extention. */
444	#define X86_CPUID_FEATURE_EDX_PSE36 RT_BIT(17)
445	/** Bit 18 - PSN - Processor Serial Number. */
446	#define X86_CPUID_FEATURE_EDX_PSN RT_BIT(18)
447	/** Bit 19 - CLFSH - CLFLUSH Instruction. */
448	#define X86_CPUID_FEATURE_EDX_CLFSH RT_BIT(19)
449	/** Bit 21 - DS - Debug Store. */
450	#define X86_CPUID_FEATURE_EDX_DS RT_BIT(21)
451	/** Bit 22 - ACPI - Termal Monitor and Software Controlled Clock Facilities. */
452	#define X86_CPUID_FEATURE_EDX_ACPI RT_BIT(22)
453	/** Bit 23 - MMX - Intel MMX Technology. */
454	#define X86_CPUID_FEATURE_EDX_MMX RT_BIT(23)
455	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
456	#define X86_CPUID_FEATURE_EDX_FXSR RT_BIT(24)
457	/** Bit 25 - SSE - SSE Support. */
458	#define X86_CPUID_FEATURE_EDX_SSE RT_BIT(25)
459	/** Bit 26 - SSE2 - SSE2 Support. */
460	#define X86_CPUID_FEATURE_EDX_SSE2 RT_BIT(26)
461	/** Bit 27 - SS - Self Snoop. */
462	#define X86_CPUID_FEATURE_EDX_SS RT_BIT(27)
463	/** Bit 28 - HTT - Hyper-Threading Technology. */
464	#define X86_CPUID_FEATURE_EDX_HTT RT_BIT(28)
465	/** Bit 29 - TM - Therm. Monitor. */
466	#define X86_CPUID_FEATURE_EDX_TM RT_BIT(29)
467	/** Bit 31 - PBE - Pending Break Enabled. */
468	#define X86_CPUID_FEATURE_EDX_PBE RT_BIT(31)
469	/** @} */
470
471	/** @name CPUID mwait/monitor information.
472	* CPUID query with EAX=5.
473	* @{
474	*/
475	/** ECX Bit 0 - MWAITEXT - Supports mwait/monitor extensions or not. */
476	#define X86_CPUID_MWAIT_ECX_EXT RT_BIT(0)
477	/** ECX Bit 1 - MWAITBREAK - Break mwait for external interrupt even if EFLAGS.IF=0. */
478	#define X86_CPUID_MWAIT_ECX_BREAKIRQIF0 RT_BIT(1)
479	/** @} */
480
481
482	/** @name CPUID AMD Feature information.
483	* CPUID query with EAX=0x80000001.
484	* @{
485	*/
486	/** Bit 0 - FPU - x87 FPU on Chip. */
487	#define X86_CPUID_AMD_FEATURE_EDX_FPU RT_BIT(0)
488	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
489	#define X86_CPUID_AMD_FEATURE_EDX_VME RT_BIT(1)
490	/** Bit 2 - DE - Debugging extensions. */
491	#define X86_CPUID_AMD_FEATURE_EDX_DE RT_BIT(2)
492	/** Bit 3 - PSE - Page Size Extension. */
493	#define X86_CPUID_AMD_FEATURE_EDX_PSE RT_BIT(3)
494	/** Bit 4 - TSC - Time Stamp Counter. */
495	#define X86_CPUID_AMD_FEATURE_EDX_TSC RT_BIT(4)
496	/** Bit 5 - MSR - K86 Model Specific Registers RDMSR and WRMSR Instructions. */
497	#define X86_CPUID_AMD_FEATURE_EDX_MSR RT_BIT(5)
498	/** Bit 6 - PAE - Physical Address Extension. */
499	#define X86_CPUID_AMD_FEATURE_EDX_PAE RT_BIT(6)
500	/** Bit 7 - MCE - Machine Check Exception. */
501	#define X86_CPUID_AMD_FEATURE_EDX_MCE RT_BIT(7)
502	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
503	#define X86_CPUID_AMD_FEATURE_EDX_CX8 RT_BIT(8)
504	/** Bit 9 - APIC - APIC On-Chip. */
505	#define X86_CPUID_AMD_FEATURE_EDX_APIC RT_BIT(9)
506	/** Bit 11 - SEP - AMD SYSCALL and SYSRET. */
507	#define X86_CPUID_AMD_FEATURE_EDX_SEP RT_BIT(11)
508	/** Bit 12 - MTRR - Memory Type Range Registers. */
509	#define X86_CPUID_AMD_FEATURE_EDX_MTRR RT_BIT(12)
510	/** Bit 13 - PGE - PTE Global Bit. */
511	#define X86_CPUID_AMD_FEATURE_EDX_PGE RT_BIT(13)
512	/** Bit 14 - MCA - Machine Check Architecture. */
513	#define X86_CPUID_AMD_FEATURE_EDX_MCA RT_BIT(14)
514	/** Bit 15 - CMOV - Conditional Move Instructions. */
515	#define X86_CPUID_AMD_FEATURE_EDX_CMOV RT_BIT(15)
516	/** Bit 16 - PAT - Page Attribute Table. */
517	#define X86_CPUID_AMD_FEATURE_EDX_PAT RT_BIT(16)
518	/** Bit 17 - PSE-36 - 36-bit Page Size Extention. */
519	#define X86_CPUID_AMD_FEATURE_EDX_PSE36 RT_BIT(17)
520	/** Bit 20 - NX - AMD No-Execute Page Protection. */
521	#define X86_CPUID_AMD_FEATURE_EDX_NX RT_BIT(20)
522	/** Bit 22 - AXMMX - AMD Extensions to MMX Instructions. */
523	#define X86_CPUID_AMD_FEATURE_EDX_AXMMX RT_BIT(22)
524	/** Bit 23 - MMX - Intel MMX Technology. */
525	#define X86_CPUID_AMD_FEATURE_EDX_MMX RT_BIT(23)
526	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
527	#define X86_CPUID_AMD_FEATURE_EDX_FXSR RT_BIT(24)
528	/** Bit 25 - FFXSR - AMD fast FXSAVE and FXRSTOR Instructions. */
529	#define X86_CPUID_AMD_FEATURE_EDX_FFXSR RT_BIT(25)
530	/** Bit 26 - PAGE1GB - AMD 1GB large page support. */
531	#define X86_CPUID_AMD_FEATURE_EDX_PAGE1GB RT_BIT(26)
532	/** Bit 27 - RDTSCP - AMD RDTSCP instruction. */
533	#define X86_CPUID_AMD_FEATURE_EDX_RDTSCP RT_BIT(27)
534	/** Bit 29 - LM - AMD Long Mode. */
535	#define X86_CPUID_AMD_FEATURE_EDX_LONG_MODE RT_BIT(29)
536	/** Bit 30 - 3DNOWEXT - AMD Extensions to 3DNow. */
537	#define X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX RT_BIT(30)
538	/** Bit 31 - 3DNOW - AMD 3DNow. */
539	#define X86_CPUID_AMD_FEATURE_EDX_3DNOW RT_BIT(31)
540
541	/** Bit 0 - LAHF/SAHF - AMD LAHF and SAHF in 64-bit mode. */
542	#define X86_CPUID_AMD_FEATURE_ECX_LAHF_SAHF RT_BIT(0)
543	/** Bit 1 - CMPL - Core multi-processing legacy mode. */
544	#define X86_CPUID_AMD_FEATURE_ECX_CMPL RT_BIT(1)
545	/** Bit 2 - SVM - AMD VM extensions. */
546	#define X86_CPUID_AMD_FEATURE_ECX_SVM RT_BIT(2)
547	/** Bit 3 - EXTAPIC - AMD extended APIC registers starting at 0x400. */
548	#define X86_CPUID_AMD_FEATURE_ECX_EXT_APIC RT_BIT(3)
549	/** Bit 4 - CR8L - AMD LOCK MOV CR0 means MOV CR8. */
550	#define X86_CPUID_AMD_FEATURE_ECX_CR8L RT_BIT(4)
551	/** Bit 5 - ABM - AMD Advanced bit manipulation. LZCNT instruction support. */
552	#define X86_CPUID_AMD_FEATURE_ECX_ABM RT_BIT(5)
553	/** Bit 6 - SSE4A - AMD EXTRQ, INSERTQ, MOVNTSS, and MOVNTSD instruction support. */
554	#define X86_CPUID_AMD_FEATURE_ECX_SSE4A RT_BIT(6)
555	/** Bit 7 - MISALIGNSSE - AMD Misaligned SSE mode. */
556	#define X86_CPUID_AMD_FEATURE_ECX_MISALNSSE RT_BIT(7)
557	/** Bit 8 - 3DNOWPRF - AMD PREFETCH and PREFETCHW instruction support. */
558	#define X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF RT_BIT(8)
559	/** Bit 9 - OSVW - AMD OS visible workaround. */
560	#define X86_CPUID_AMD_FEATURE_ECX_OSVW RT_BIT(9)
561	/** Bit 10 - IBS - Instruct based sampling. */
562	#define X86_CPUID_AMD_FEATURE_ECX_IBS RT_BIT(10)
563	/** Bit 11 - SSE5 - SSE5 instruction support. */
564	#define X86_CPUID_AMD_FEATURE_ECX_SSE5 RT_BIT(11)
565	/** Bit 12 - SKINIT - AMD SKINIT: SKINIT, STGI, and DEV support. */
566	#define X86_CPUID_AMD_FEATURE_ECX_SKINIT RT_BIT(12)
567	/** Bit 13 - WDT - AMD Watchdog timer support. */
568	#define X86_CPUID_AMD_FEATURE_ECX_WDT RT_BIT(13)
569
570	/** @} */
571
572
573	/** @name CPUID AMD Feature information.
574	* CPUID query with EAX=0x80000007.
575	* @{
576	*/
577	/** Bit 0 - TS - Temperature Sensor. */
578	#define X86_CPUID_AMD_ADVPOWER_EDX_TS RT_BIT(0)
579	/** Bit 1 - FID - Frequency ID Control. */
580	#define X86_CPUID_AMD_ADVPOWER_EDX_FID RT_BIT(1)
581	/** Bit 2 - VID - Voltage ID Control. */
582	#define X86_CPUID_AMD_ADVPOWER_EDX_VID RT_BIT(2)
583	/** Bit 3 - TTP - THERMTRIP. */
584	#define X86_CPUID_AMD_ADVPOWER_EDX_TTP RT_BIT(3)
585	/** Bit 4 - TM - Hardware Thermal Control. */
586	#define X86_CPUID_AMD_ADVPOWER_EDX_TM RT_BIT(4)
587	/** Bit 5 - STC - Software Thermal Control. */
588	#define X86_CPUID_AMD_ADVPOWER_EDX_STC RT_BIT(5)
589	/** Bit 6 - MC - 100 Mhz Multiplier Control. */
590	#define X86_CPUID_AMD_ADVPOWER_EDX_MC RT_BIT(6)
591	/** Bit 7 - HWPSTATE - Hardware P-State Control. */
592	#define X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE RT_BIT(7)
593	/** Bit 8 - TSCINVAR - TSC Invariant. */
594	#define X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR RT_BIT(8)
595	/** @} */
596
597
598	/** @name CR0
599	* @{ */
600	/** Bit 0 - PE - Protection Enabled */
601	#define X86_CR0_PE RT_BIT(0)
602	#define X86_CR0_PROTECTION_ENABLE RT_BIT(0)
603	/** Bit 1 - MP - Monitor Coprocessor */
604	#define X86_CR0_MP RT_BIT(1)
605	#define X86_CR0_MONITOR_COPROCESSOR RT_BIT(1)
606	/** Bit 2 - EM - Emulation. */
607	#define X86_CR0_EM RT_BIT(2)
608	#define X86_CR0_EMULATE_FPU RT_BIT(2)
609	/** Bit 3 - TS - Task Switch. */
610	#define X86_CR0_TS RT_BIT(3)
611	#define X86_CR0_TASK_SWITCH RT_BIT(3)
612	/** Bit 4 - ET - Extension flag. ('hardcoded' to 1) */
613	#define X86_CR0_ET RT_BIT(4)
614	#define X86_CR0_EXTENSION_TYPE RT_BIT(4)
615	/** Bit 5 - NE - Numeric error. */
616	#define X86_CR0_NE RT_BIT(5)
617	#define X86_CR0_NUMERIC_ERROR RT_BIT(5)
618	/** Bit 16 - WP - Write Protect. */
619	#define X86_CR0_WP RT_BIT(16)
620	#define X86_CR0_WRITE_PROTECT RT_BIT(16)
621	/** Bit 18 - AM - Alignment Mask. */
622	#define X86_CR0_AM RT_BIT(18)
623	#define X86_CR0_ALIGMENT_MASK RT_BIT(18)
624	/** Bit 29 - NW - Not Write-though. */
625	#define X86_CR0_NW RT_BIT(29)
626	#define X86_CR0_NOT_WRITE_THROUGH RT_BIT(29)
627	/** Bit 30 - WP - Cache Disable. */
628	#define X86_CR0_CD RT_BIT(30)
629	#define X86_CR0_CACHE_DISABLE RT_BIT(30)
630	/** Bit 31 - PG - Paging. */
631	#define X86_CR0_PG RT_BIT(31)
632	#define X86_CR0_PAGING RT_BIT(31)
633	/** @} */
634
635
636	/** @name CR3
637	* @{ */
638	/** Bit 3 - PWT - Page-level Writes Transparent. */
639	#define X86_CR3_PWT RT_BIT(3)
640	/** Bit 4 - PCD - Page-level Cache Disable. */
641	#define X86_CR3_PCD RT_BIT(4)
642	/** Bits 12-31 - - Page directory page number. */
643	#define X86_CR3_PAGE_MASK (0xfffff000)
644	/** Bits 5-31 - - PAE Page directory page number. */
645	#define X86_CR3_PAE_PAGE_MASK (0xffffffe0)
646	/** Bits 12-51 - - AMD64 Page directory page number. */
647	#define X86_CR3_AMD64_PAGE_MASK UINT64_C(0x000ffffffffff000)
648	/** @} */
649
650
651	/** @name CR4
652	* @{ */
653	/** Bit 0 - VME - Virtual-8086 Mode Extensions. */
654	#define X86_CR4_VME RT_BIT(0)
655	/** Bit 1 - PVI - Protected-Mode Virtual Interrupts. */
656	#define X86_CR4_PVI RT_BIT(1)
657	/** Bit 2 - TSD - Time Stamp Disable. */
658	#define X86_CR4_TSD RT_BIT(2)
659	/** Bit 3 - DE - Debugging Extensions. */
660	#define X86_CR4_DE RT_BIT(3)
661	/** Bit 4 - PSE - Page Size Extension. */
662	#define X86_CR4_PSE RT_BIT(4)
663	/** Bit 5 - PAE - Physical Address Extension. */
664	#define X86_CR4_PAE RT_BIT(5)
665	/** Bit 6 - MCE - Machine-Check Enable. */
666	#define X86_CR4_MCE RT_BIT(6)
667	/** Bit 7 - PGE - Page Global Enable. */
668	#define X86_CR4_PGE RT_BIT(7)
669	/** Bit 8 - PCE - Performance-Monitoring Counter Enable. */
670	#define X86_CR4_PCE RT_BIT(8)
671	/** Bit 9 - OSFSXR - Operating System Support for FXSAVE and FXRSTORE instruction. */
672	#define X86_CR4_OSFSXR RT_BIT(9)
673	/** Bit 10 - OSXMMEEXCPT - Operating System Support for Unmasked SIMD Floating-Point Exceptions. */
674	#define X86_CR4_OSXMMEEXCPT RT_BIT(10)
675	/** Bit 13 - VMXE - VMX mode is enabled. */
676	#define X86_CR4_VMXE RT_BIT(13)
677	/** @} */
678
679
680	/** @name DR6
681	* @{ */
682	/** Bit 0 - B0 - Breakpoint 0 condition detected. */
683	#define X86_DR6_B0 RT_BIT(0)
684	/** Bit 1 - B1 - Breakpoint 1 condition detected. */
685	#define X86_DR6_B1 RT_BIT(1)
686	/** Bit 2 - B2 - Breakpoint 2 condition detected. */
687	#define X86_DR6_B2 RT_BIT(2)
688	/** Bit 3 - B3 - Breakpoint 3 condition detected. */
689	#define X86_DR6_B3 RT_BIT(3)
690	/** Bit 13 - BD - Debug register access detected. Corresponds to the X86_DR7_GD bit. */
691	#define X86_DR6_BD RT_BIT(13)
692	/** Bit 14 - BS - Single step */
693	#define X86_DR6_BS RT_BIT(14)
694	/** Bit 15 - BT - Task switch. (TSS T bit.) */
695	#define X86_DR6_BT RT_BIT(15)
696	/** Value of DR6 after powerup/reset. */
697	#define X86_DR6_INIT_VAL UINT64_C(0xFFFF0FF0)
698	/** @} */
699
700
701	/** @name DR7
702	* @{ */
703	/** Bit 0 - L0 - Local breakpoint enable. Cleared on task switch. */
704	#define X86_DR7_L0 RT_BIT(0)
705	/** Bit 1 - G0 - Global breakpoint enable. Not cleared on task switch. */
706	#define X86_DR7_G0 RT_BIT(1)
707	/** Bit 2 - L1 - Local breakpoint enable. Cleared on task switch. */
708	#define X86_DR7_L1 RT_BIT(2)
709	/** Bit 3 - G1 - Global breakpoint enable. Not cleared on task switch. */
710	#define X86_DR7_G1 RT_BIT(3)
711	/** Bit 4 - L2 - Local breakpoint enable. Cleared on task switch. */
712	#define X86_DR7_L2 RT_BIT(4)
713	/** Bit 5 - G2 - Global breakpoint enable. Not cleared on task switch. */
714	#define X86_DR7_G2 RT_BIT(5)
715	/** Bit 6 - L3 - Local breakpoint enable. Cleared on task switch. */
716	#define X86_DR7_L3 RT_BIT(6)
717	/** Bit 7 - G3 - Global breakpoint enable. Not cleared on task switch. */
718	#define X86_DR7_G3 RT_BIT(7)
719	/** Bit 8 - LE - Local breakpoint exact. (Not supported (read ignored) by P6 and later.) */
720	#define X86_DR7_LE RT_BIT(8)
721	/** Bit 9 - GE - Local breakpoint exact. (Not supported (read ignored) by P6 and later.) */
722	#define X86_DR7_GE RT_BIT(9)
723
724	/** Bit 13 - GD - General detect enable. Enables emulators to get exceptions when
725	* any DR register is accessed. */
726	#define X86_DR7_GD RT_BIT(13)
727	/** Bit 16 & 17 - R/W0 - Read write field 0. Values X86_DR7_RW_. /
728	#define X86_DR7_RW0_MASK (3 << 16)
729	/** Bit 18 & 19 - LEN0 - Length field 0. Values X86_DR7_LEN_. /
730	#define X86_DR7_LEN0_MASK (3 << 18)
731	/** Bit 20 & 21 - R/W1 - Read write field 0. Values X86_DR7_RW_. /
732	#define X86_DR7_RW1_MASK (3 << 20)
733	/** Bit 22 & 23 - LEN1 - Length field 0. Values X86_DR7_LEN_. /
734	#define X86_DR7_LEN1_MASK (3 << 22)
735	/** Bit 24 & 25 - R/W2 - Read write field 0. Values X86_DR7_RW_. /
736	#define X86_DR7_RW2_MASK (3 << 24)
737	/** Bit 26 & 27 - LEN2 - Length field 0. Values X86_DR7_LEN_. /
738	#define X86_DR7_LEN2_MASK (3 << 26)
739	/** Bit 28 & 29 - R/W3 - Read write field 0. Values X86_DR7_RW_. /
740	#define X86_DR7_RW3_MASK (3 << 28)
741	/** Bit 30 & 31 - LEN3 - Length field 0. Values X86_DR7_LEN_. /
742	#define X86_DR7_LEN3_MASK (3 << 30)
743
744	/** Bits which must be 1s. */
745	#define X86_DR7_MB1_MASK (RT_BIT(10))
746
747	/** Calcs the L bit of Nth breakpoint.
748	* @param iBp The breakpoint number [0..3].
749	*/
750	#define X86_DR7_L(iBp) ( UINT32_C(1) << (iBp * 2) )
751
752	/** Calcs the G bit of Nth breakpoint.
753	* @param iBp The breakpoint number [0..3].
754	*/
755	#define X86_DR7_G(iBp) ( UINT32_C(1) << (iBp * 2 + 1) )
756
757	/** @name Read/Write values.
758	* @{ */
759	/** Break on instruction fetch only. */
760	#define X86_DR7_RW_EO 0U
761	/** Break on write only. */
762	#define X86_DR7_RW_WO 1U
763	/** Break on I/O read/write. This is only defined if CR4.DE is set. */
764	#define X86_DR7_RW_IO 2U
765	/** Break on read or write (but not instruction fetches). */
766	#define X86_DR7_RW_RW 3U
767	/** @} */
768
769	/** Shifts a X86_DR7_RW_* value to its right place.
770	* @param iBp The breakpoint number [0..3].
771	* @param fRw One of the X86_DR7_RW_* value.
772	*/
773	#define X86_DR7_RW(iBp, fRw) ( (fRw) << ((iBp) * 4 + 16) )
774
775	/** @name Length values.
776	* @{ */
777	#define X86_DR7_LEN_BYTE 0U
778	#define X86_DR7_LEN_WORD 1U
779	#define X86_DR7_LEN_QWORD 2U /*< AMD64 long mode only. /
780	#define X86_DR7_LEN_DWORD 3U
781	/** @} */
782
783	/** Shifts a X86_DR7_LEN_* value to its right place.
784	* @param iBp The breakpoint number [0..3].
785	* @param cb One of the X86_DR7_LEN_* values.
786	*/
787	#define X86_DR7_LEN(iBp, cb) ( (cb) << ((iBp) * 4 + 18) )
788
789	/** Fetch the breakpoint length bits from the DR7 value.
790	* @param uDR7 DR7 value
791	* @param iBp The breakpoint number [0..3].
792	*/
793	#define X86_DR7_GET_LEN(uDR7, iBp) ( ( (uDR7) >> ((iBp) * 4 + 18) ) & 0x3U)
794
795	/** Mask used to check if any breakpoints are enabled. */
796	#define X86_DR7_ENABLED_MASK (RT_BIT(0) \| RT_BIT(1) \| RT_BIT(2) \| RT_BIT(3) \| RT_BIT(4) \| RT_BIT(5) \| RT_BIT(6) \| RT_BIT(7))
797
798	/** Mask used to check if any io breakpoints are set. */
799	#define X86_DR7_IO_ENABLED_MASK (X86_DR7_RW(0, X86_DR7_RW_IO) \| X86_DR7_RW(1, X86_DR7_RW_IO) \| X86_DR7_RW(2, X86_DR7_RW_IO) \| X86_DR7_RW(3, X86_DR7_RW_IO))
800
801	/** Value of DR7 after powerup/reset. */
802	#define X86_DR7_INIT_VAL 0x400
803	/** @} */
804
805
806	/** @name Machine Specific Registers
807	* @{
808	*/
809
810	/** Time Stamp Counter. */
811	#define MSR_IA32_TSC 0x10
812
813	#define MSR_IA32_PLATFORM_ID 0x17
814
815	#ifndef MSR_IA32_APICBASE /* qemu cpu.h klugde */
816	#define MSR_IA32_APICBASE 0x1b
817	#endif
818
819	/** CPU Feature control. */
820	#define MSR_IA32_FEATURE_CONTROL 0x3A
821	#define MSR_IA32_FEATURE_CONTROL_LOCK RT_BIT(0)
822	#define MSR_IA32_FEATURE_CONTROL_VMXON RT_BIT(2)
823
824	/** BIOS update trigger (microcode update). */
825	#define MSR_IA32_BIOS_UPDT_TRIG 0x79
826
827	/** BIOS update signature (microcode). */
828	#define MSR_IA32_BIOS_SIGN_ID 0x8B
829
830	/** Nehalem power control. */
831	#define MSR_IA32_PLATFORM_INFO 0xCE
832
833	/** MTRR Capabilities. */
834	#define MSR_IA32_MTRR_CAP 0xFE
835
836
837	#ifndef MSR_IA32_SYSENTER_CS /* qemu cpu.h klugde */
838	/** SYSENTER_CS - the R0 CS, indirectly giving R0 SS, R3 CS and R3 DS.
839	* R0 SS == CS + 8
840	* R3 CS == CS + 16
841	* R3 SS == CS + 24
842	*/
843	#define MSR_IA32_SYSENTER_CS 0x174
844	/** SYSENTER_ESP - the R0 ESP. */
845	#define MSR_IA32_SYSENTER_ESP 0x175
846	/** SYSENTER_EIP - the R0 EIP. */
847	#define MSR_IA32_SYSENTER_EIP 0x176
848	#endif
849
850	/** Machine Check Global Capabilities Register. */
851	#define MSR_IA32_MCP_CAP 0x179
852	/** Machine Check Global Status Register. */
853	#define MSR_IA32_MCP_STATUS 0x17A
854	/** Machine Check Global Control Register. */
855	#define MSR_IA32_MCP_CTRL 0x17B
856
857	/** Trace/Profile Resource Control (R/W) */
858	#define MSR_IA32_DEBUGCTL 0x1D9
859
860	/* Page Attribute Table. */
861	#define MSR_IA32_CR_PAT 0x277
862
863	/** Performance counter MSRs. (Intel only) */
864	#define MSR_IA32_PERFEVTSEL0 0x186
865	#define MSR_IA32_PERFEVTSEL1 0x187
866	#define MSR_IA32_FLEX_RATIO 0x194
867	#define MSR_IA32_PERF_STATUS 0x198
868	#define MSR_IA32_PERF_CTL 0x199
869
870	/** Enable misc. processor features (R/W). */
871	#define MSR_IA32_MISC_ENABLE 0x1A0
872
873	/** MTRR Default Range. */
874	#define MSR_IA32_MTRR_DEF_TYPE 0x2FF
875
876	#define MSR_IA32_MC0_CTL 0x400
877	#define MSR_IA32_MC0_STATUS 0x401
878
879	/** Basic VMX information. */
880	#define MSR_IA32_VMX_BASIC_INFO 0x480
881	/** Allowed settings for pin-based VM execution controls */
882	#define MSR_IA32_VMX_PINBASED_CTLS 0x481
883	/** Allowed settings for proc-based VM execution controls */
884	#define MSR_IA32_VMX_PROCBASED_CTLS 0x482
885	/** Allowed settings for the VMX exit controls. */
886	#define MSR_IA32_VMX_EXIT_CTLS 0x483
887	/** Allowed settings for the VMX entry controls. */
888	#define MSR_IA32_VMX_ENTRY_CTLS 0x484
889	/** Misc VMX info. */
890	#define MSR_IA32_VMX_MISC 0x485
891	/** Fixed cleared bits in CR0. */
892	#define MSR_IA32_VMX_CR0_FIXED0 0x486
893	/** Fixed set bits in CR0. */
894	#define MSR_IA32_VMX_CR0_FIXED1 0x487
895	/** Fixed cleared bits in CR4. */
896	#define MSR_IA32_VMX_CR4_FIXED0 0x488
897	/** Fixed set bits in CR4. */
898	#define MSR_IA32_VMX_CR4_FIXED1 0x489
899	/** Information for enumerating fields in the VMCS. */
900	#define MSR_IA32_VMX_VMCS_ENUM 0x48A
901	/** Allowed settings for secondary proc-based VM execution controls */
902	#define MSR_IA32_VMX_PROCBASED_CTLS2 0x48B
903	/** EPT capabilities. */
904	#define MSR_IA32_VMX_EPT_CAPS 0x48C
905	/** DS Save Area (R/W). */
906	#define MSR_IA32_DS_AREA 0x600
907	/** X2APIC MSR ranges. */
908	#define MSR_IA32_APIC_START 0x800
909	#define MSR_IA32_APIC_END 0x900
910
911	/** K6 EFER - Extended Feature Enable Register. */
912	#define MSR_K6_EFER 0xc0000080
913	/** @todo document EFER */
914	/** Bit 0 - SCE - System call extensions (SYSCALL / SYSRET). (R/W) */
915	#define MSR_K6_EFER_SCE RT_BIT(0)
916	/** Bit 8 - LME - Long mode enabled. (R/W) */
917	#define MSR_K6_EFER_LME RT_BIT(8)
918	/** Bit 10 - LMA - Long mode active. (R) */
919	#define MSR_K6_EFER_LMA RT_BIT(10)
920	/** Bit 11 - NXE - No-Execute Page Protection Enabled. (R/W) */
921	#define MSR_K6_EFER_NXE RT_BIT(11)
922	/** Bit 12 - SVME - Secure VM Extension Enabled. (R/W) */
923	#define MSR_K6_EFER_SVME RT_BIT(12)
924	/** Bit 13 - LMSLE - Long Mode Segment Limit Enable. (R/W?) */
925	#define MSR_K6_EFER_LMSLE RT_BIT(13)
926	/** Bit 14 - FFXSR - Fast FXSAVE / FXRSTOR (skip XMM). (R/W) /
927	#define MSR_K6_EFER_FFXSR RT_BIT(14)
928	/** K6 STAR - SYSCALL/RET targets. */
929	#define MSR_K6_STAR 0xc0000081
930	/** Shift value for getting the SYSRET CS and SS value. */
931	#define MSR_K6_STAR_SYSRET_CS_SS_SHIFT 48
932	/** Shift value for getting the SYSCALL CS and SS value. */
933	#define MSR_K6_STAR_SYSCALL_CS_SS_SHIFT 32
934	/** Selector mask for use after shifting. */
935	#define MSR_K6_STAR_SEL_MASK 0xffff
936	/** The mask which give the SYSCALL EIP. */
937	#define MSR_K6_STAR_SYSCALL_EIP_MASK 0xffffffff
938	/** K6 WHCR - Write Handling Control Register. */
939	#define MSR_K6_WHCR 0xc0000082
940	/** K6 UWCCR - UC/WC Cacheability Control Register. */
941	#define MSR_K6_UWCCR 0xc0000085
942	/** K6 PSOR - Processor State Observability Register. */
943	#define MSR_K6_PSOR 0xc0000087
944	/** K6 PFIR - Page Flush/Invalidate Register. */
945	#define MSR_K6_PFIR 0xc0000088
946
947	/** Performance counter MSRs. (AMD only) */
948	#define MSR_K7_EVNTSEL0 0xc0010000
949	#define MSR_K7_EVNTSEL1 0xc0010001
950	#define MSR_K7_EVNTSEL2 0xc0010002
951	#define MSR_K7_EVNTSEL3 0xc0010003
952	#define MSR_K7_PERFCTR0 0xc0010004
953	#define MSR_K7_PERFCTR1 0xc0010005
954	#define MSR_K7_PERFCTR2 0xc0010006
955	#define MSR_K7_PERFCTR3 0xc0010007
956
957	#define MSR_K8_HWCR 0xc0010015
958
959	/** K8 LSTAR - Long mode SYSCALL target (RIP). */
960	#define MSR_K8_LSTAR 0xc0000082
961	/** K8 CSTAR - Compatibility mode SYSCALL target (RIP). */
962	#define MSR_K8_CSTAR 0xc0000083
963	/** K8 SF_MASK - SYSCALL flag mask. (aka SFMASK) */
964	#define MSR_K8_SF_MASK 0xc0000084
965	/** K8 FS.base - The 64-bit base FS register. */
966	#define MSR_K8_FS_BASE 0xc0000100
967	/** K8 GS.base - The 64-bit base GS register. */
968	#define MSR_K8_GS_BASE 0xc0000101
969	/** K8 KernelGSbase - Used with SWAPGS. */
970	#define MSR_K8_KERNEL_GS_BASE 0xc0000102
971	#define MSR_K8_TSC_AUX 0xc0000103
972	#define MSR_K8_SYSCFG 0xc0010010
973	#define MSR_K8_HWCR 0xc0010015
974	#define MSR_K8_IORRBASE0 0xc0010016
975	#define MSR_K8_IORRMASK0 0xc0010017
976	#define MSR_K8_IORRBASE1 0xc0010018
977	#define MSR_K8_IORRMASK1 0xc0010019
978	#define MSR_K8_TOP_MEM1 0xc001001a
979	#define MSR_K8_TOP_MEM2 0xc001001d
980	#define MSR_K8_VM_CR 0xc0010114
981	#define MSR_K8_VM_CR_SVM_DISABLE RT_BIT(4)
982
983	#define MSR_K8_IGNNE 0xc0010115
984	#define MSR_K8_SMM_CTL 0xc0010116
985	/** SVM - VM_HSAVE_PA - Physical address for saving and restoring
986	* host state during world switch.
987	*/
988	#define MSR_K8_VM_HSAVE_PA 0xc0010117
989
990	/** @} */
991
992
993	/** @name Page Table / Directory / Directory Pointers / L4.
994	* @{
995	*/
996
997	/** Page table/directory entry as an unsigned integer. */
998	typedef uint32_t X86PGUINT;
999	/** Pointer to a page table/directory table entry as an unsigned integer. */
1000	typedef X86PGUINT *PX86PGUINT;
1001	/** Pointer to an const page table/directory table entry as an unsigned integer. */
1002	typedef X86PGUINT const *PCX86PGUINT;
1003
1004	/** Number of entries in a 32-bit PT/PD. */
1005	#define X86_PG_ENTRIES 1024
1006
1007
1008	/** PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
1009	typedef uint64_t X86PGPAEUINT;
1010	/** Pointer to a PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
1011	typedef X86PGPAEUINT *PX86PGPAEUINT;
1012	/** Pointer to an const PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
1013	typedef X86PGPAEUINT const *PCX86PGPAEUINT;
1014
1015	/** Number of entries in a PAE PT/PD. */
1016	#define X86_PG_PAE_ENTRIES 512
1017	/** Number of entries in a PAE PDPT. */
1018	#define X86_PG_PAE_PDPE_ENTRIES 4
1019
1020	/** Number of entries in an AMD64 PT/PD/PDPT/L4/L5. */
1021	#define X86_PG_AMD64_ENTRIES X86_PG_PAE_ENTRIES
1022	/** Number of entries in an AMD64 PDPT.
1023	* Just for complementing X86_PG_PAE_PDPE_ENTRIES, using X86_PG_AMD64_ENTRIES for this is fine too. */
1024	#define X86_PG_AMD64_PDPE_ENTRIES X86_PG_AMD64_ENTRIES
1025
1026	/** The size of a 4KB page. */
1027	#define X86_PAGE_4K_SIZE _4K
1028	/** The page shift of a 4KB page. */
1029	#define X86_PAGE_4K_SHIFT 12
1030	/** The 4KB page offset mask. */
1031	#define X86_PAGE_4K_OFFSET_MASK 0xfff
1032	/** The 4KB page base mask for virtual addresses. */
1033	#define X86_PAGE_4K_BASE_MASK 0xfffffffffffff000ULL
1034	/** The 4KB page base mask for virtual addresses - 32bit version. */
1035	#define X86_PAGE_4K_BASE_MASK_32 0xfffff000U
1036
1037	/** The size of a 2MB page. */
1038	#define X86_PAGE_2M_SIZE _2M
1039	/** The page shift of a 2MB page. */
1040	#define X86_PAGE_2M_SHIFT 21
1041	/** The 2MB page offset mask. */
1042	#define X86_PAGE_2M_OFFSET_MASK 0x001fffff
1043	/** The 2MB page base mask for virtual addresses. */
1044	#define X86_PAGE_2M_BASE_MASK 0xffffffffffe00000ULL
1045	/** The 2MB page base mask for virtual addresses - 32bit version. */
1046	#define X86_PAGE_2M_BASE_MASK_32 0xffe00000U
1047
1048	/** The size of a 4MB page. */
1049	#define X86_PAGE_4M_SIZE _4M
1050	/** The page shift of a 4MB page. */
1051	#define X86_PAGE_4M_SHIFT 22
1052	/** The 4MB page offset mask. */
1053	#define X86_PAGE_4M_OFFSET_MASK 0x003fffff
1054	/** The 4MB page base mask for virtual addresses. */
1055	#define X86_PAGE_4M_BASE_MASK 0xffffffffffc00000ULL
1056	/** The 4MB page base mask for virtual addresses - 32bit version. */
1057	#define X86_PAGE_4M_BASE_MASK_32 0xffc00000U
1058
1059
1060
1061	/** @name Page Table Entry
1062	* @{
1063	*/
1064	/** Bit 0 - P - Present bit. */
1065	#define X86_PTE_BIT_P 0
1066	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1067	#define X86_PTE_BIT_RW 1
1068	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1069	#define X86_PTE_BIT_US 2
1070	/** Bit 3 - PWT - Page level write thru bit. */
1071	#define X86_PTE_BIT_PWT 3
1072	/** Bit 4 - PCD - Page level cache disable bit. */
1073	#define X86_PTE_BIT_PCD 4
1074	/** Bit 5 - A - Access bit. */
1075	#define X86_PTE_BIT_A 5
1076	/** Bit 6 - D - Dirty bit. */
1077	#define X86_PTE_BIT_D 6
1078	/** Bit 7 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
1079	#define X86_PTE_BIT_PAT 7
1080	/** Bit 8 - G - Global flag. */
1081	#define X86_PTE_BIT_G 8
1082
1083	/** Bit 0 - P - Present bit mask. */
1084	#define X86_PTE_P RT_BIT(0)
1085	/** Bit 1 - R/W - Read (clear) / Write (set) bit mask. */
1086	#define X86_PTE_RW RT_BIT(1)
1087	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit mask. */
1088	#define X86_PTE_US RT_BIT(2)
1089	/** Bit 3 - PWT - Page level write thru bit mask. */
1090	#define X86_PTE_PWT RT_BIT(3)
1091	/** Bit 4 - PCD - Page level cache disable bit mask. */
1092	#define X86_PTE_PCD RT_BIT(4)
1093	/** Bit 5 - A - Access bit mask. */
1094	#define X86_PTE_A RT_BIT(5)
1095	/** Bit 6 - D - Dirty bit mask. */
1096	#define X86_PTE_D RT_BIT(6)
1097	/** Bit 7 - PAT - Page Attribute Table index bit mask. Reserved and 0 if not supported. */
1098	#define X86_PTE_PAT RT_BIT(7)
1099	/** Bit 8 - G - Global bit mask. */
1100	#define X86_PTE_G RT_BIT(8)
1101
1102	/** Bits 9-11 - - Available for use to system software. */
1103	#define X86_PTE_AVL_MASK (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
1104	/** Bits 12-31 - - Physical Page number of the next level. */
1105	#define X86_PTE_PG_MASK ( 0xfffff000 )
1106
1107	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1108	#if 1 /* we're using this internally and have to mask of the top 16-bit. */
1109	#define X86_PTE_PAE_PG_MASK ( 0x0000fffffffff000ULL )
1110	/** @todo Get rid of the above hack; makes code unreadable. */
1111	#define X86_PTE_PAE_PG_MASK_FULL ( 0x000ffffffffff000ULL )
1112	#else
1113	#define X86_PTE_PAE_PG_MASK ( 0x000ffffffffff000ULL )
1114	#endif
1115	/** Bits 63 - NX - PAE - No execution flag. */
1116	#define X86_PTE_PAE_NX RT_BIT_64(63)
1117
1118	/**
1119	* Page table entry.
1120	*/
1121	typedef struct X86PTEBITS
1122	{
1123	/** Flags whether(=1) or not the page is present. */
1124	unsigned u1Present : 1;
1125	/** Read(=0) / Write(=1) flag. */
1126	unsigned u1Write : 1;
1127	/** User(=1) / Supervisor (=0) flag. */
1128	unsigned u1User : 1;
1129	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1130	unsigned u1WriteThru : 1;
1131	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1132	unsigned u1CacheDisable : 1;
1133	/** Accessed flag.
1134	* Indicates that the page have been read or written to. */
1135	unsigned u1Accessed : 1;
1136	/** Dirty flag.
1137	* Indicates that the page has been written to. */
1138	unsigned u1Dirty : 1;
1139	/** Reserved / If PAT enabled, bit 2 of the index. */
1140	unsigned u1PAT : 1;
1141	/** Global flag. (Ignored in all but final level.) */
1142	unsigned u1Global : 1;
1143	/** Available for use to system software. */
1144	unsigned u3Available : 3;
1145	/** Physical Page number of the next level. */
1146	unsigned u20PageNo : 20;
1147	} X86PTEBITS;
1148	/** Pointer to a page table entry. */
1149	typedef X86PTEBITS *PX86PTEBITS;
1150	/** Pointer to a const page table entry. */
1151	typedef const X86PTEBITS *PCX86PTEBITS;
1152
1153	/**
1154	* Page table entry.
1155	*/
1156	typedef union X86PTE
1157	{
1158	/** Unsigned integer view */
1159	X86PGUINT u;
1160	/** Bit field view. */
1161	X86PTEBITS n;
1162	/** 32-bit view. */
1163	uint32_t au32[1];
1164	/** 16-bit view. */
1165	uint16_t au16[2];
1166	/** 8-bit view. */
1167	uint8_t au8[4];
1168	} X86PTE;
1169	/** Pointer to a page table entry. */
1170	typedef X86PTE *PX86PTE;
1171	/** Pointer to a const page table entry. */
1172	typedef const X86PTE *PCX86PTE;
1173
1174
1175	/**
1176	* PAE page table entry.
1177	*/
1178	typedef struct X86PTEPAEBITS
1179	{
1180	/** Flags whether(=1) or not the page is present. */
1181	uint32_t u1Present : 1;
1182	/** Read(=0) / Write(=1) flag. */
1183	uint32_t u1Write : 1;
1184	/** User(=1) / Supervisor(=0) flag. */
1185	uint32_t u1User : 1;
1186	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1187	uint32_t u1WriteThru : 1;
1188	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1189	uint32_t u1CacheDisable : 1;
1190	/** Accessed flag.
1191	* Indicates that the page have been read or written to. */
1192	uint32_t u1Accessed : 1;
1193	/** Dirty flag.
1194	* Indicates that the page has been written to. */
1195	uint32_t u1Dirty : 1;
1196	/** Reserved / If PAT enabled, bit 2 of the index. */
1197	uint32_t u1PAT : 1;
1198	/** Global flag. (Ignored in all but final level.) */
1199	uint32_t u1Global : 1;
1200	/** Available for use to system software. */
1201	uint32_t u3Available : 3;
1202	/** Physical Page number of the next level - Low Part. Don't use this. */
1203	uint32_t u20PageNoLow : 20;
1204	/** Physical Page number of the next level - High Part. Don't use this. */
1205	uint32_t u20PageNoHigh : 20;
1206	/** MBZ bits */
1207	uint32_t u11Reserved : 11;
1208	/** No Execute flag. */
1209	uint32_t u1NoExecute : 1;
1210	} X86PTEPAEBITS;
1211	/** Pointer to a page table entry. */
1212	typedef X86PTEPAEBITS *PX86PTEPAEBITS;
1213	/** Pointer to a page table entry. */
1214	typedef const X86PTEPAEBITS *PCX86PTEPAEBITS;
1215
1216	/**
1217	* PAE Page table entry.
1218	*/
1219	typedef union X86PTEPAE
1220	{
1221	/** Unsigned integer view */
1222	X86PGPAEUINT u;
1223	/** Bit field view. */
1224	X86PTEPAEBITS n;
1225	/** 32-bit view. */
1226	uint32_t au32[2];
1227	/** 16-bit view. */
1228	uint16_t au16[4];
1229	/** 8-bit view. */
1230	uint8_t au8[8];
1231	} X86PTEPAE;
1232	/** Pointer to a PAE page table entry. */
1233	typedef X86PTEPAE *PX86PTEPAE;
1234	/** Pointer to a const PAE page table entry. */
1235	typedef const X86PTEPAE *PCX86PTEPAE;
1236	/** @} */
1237
1238	/**
1239	* Page table.
1240	*/
1241	typedef struct X86PT
1242	{
1243	/** PTE Array. */
1244	X86PTE a[X86_PG_ENTRIES];
1245	} X86PT;
1246	/** Pointer to a page table. */
1247	typedef X86PT *PX86PT;
1248	/** Pointer to a const page table. */
1249	typedef const X86PT *PCX86PT;
1250
1251	/** The page shift to get the PT index. */
1252	#define X86_PT_SHIFT 12
1253	/** The PT index mask (apply to a shifted page address). */
1254	#define X86_PT_MASK 0x3ff
1255
1256
1257	/**
1258	* Page directory.
1259	*/
1260	typedef struct X86PTPAE
1261	{
1262	/** PTE Array. */
1263	X86PTEPAE a[X86_PG_PAE_ENTRIES];
1264	} X86PTPAE;
1265	/** Pointer to a page table. */
1266	typedef X86PTPAE *PX86PTPAE;
1267	/** Pointer to a const page table. */
1268	typedef const X86PTPAE *PCX86PTPAE;
1269
1270	/** The page shift to get the PA PTE index. */
1271	#define X86_PT_PAE_SHIFT 12
1272	/** The PAE PT index mask (apply to a shifted page address). */
1273	#define X86_PT_PAE_MASK 0x1ff
1274
1275
1276	/** @name 4KB Page Directory Entry
1277	* @{
1278	*/
1279	/** Bit 0 - P - Present bit. */
1280	#define X86_PDE_P RT_BIT(0)
1281	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1282	#define X86_PDE_RW RT_BIT(1)
1283	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1284	#define X86_PDE_US RT_BIT(2)
1285	/** Bit 3 - PWT - Page level write thru bit. */
1286	#define X86_PDE_PWT RT_BIT(3)
1287	/** Bit 4 - PCD - Page level cache disable bit. */
1288	#define X86_PDE_PCD RT_BIT(4)
1289	/** Bit 5 - A - Access bit. */
1290	#define X86_PDE_A RT_BIT(5)
1291	/** Bit 7 - PS - Page size attribute.
1292	* Clear mean 4KB pages, set means large pages (2/4MB). */
1293	#define X86_PDE_PS RT_BIT(7)
1294	/** Bits 9-11 - - Available for use to system software. */
1295	#define X86_PDE_AVL_MASK (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
1296	/** Bits 12-31 - - Physical Page number of the next level. */
1297	#define X86_PDE_PG_MASK ( 0xfffff000 )
1298
1299	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1300	#if 1 /* we're using this internally and have to mask of the top 16-bit. */
1301	/* Note: This is kind of dangerous if the guest uses these bits (legally or illegally);
1302	* we partly or that part into shadow page table entries. Will be corrected
1303	* soon.
1304	*/
1305	#define X86_PDE_PAE_PG_MASK ( 0x0000fffffffff000ULL )
1306	#define X86_PDE_PAE_PG_MASK_FULL ( 0x000ffffffffff000ULL )
1307	#else
1308	#define X86_PDE_PAE_PG_MASK ( 0x000ffffffffff000ULL )
1309	#endif
1310	/** Bits 63 - NX - PAE - No execution flag. */
1311	#define X86_PDE_PAE_NX RT_BIT_64(63)
1312
1313	/**
1314	* Page directory entry.
1315	*/
1316	typedef struct X86PDEBITS
1317	{
1318	/** Flags whether(=1) or not the page is present. */
1319	unsigned u1Present : 1;
1320	/** Read(=0) / Write(=1) flag. */
1321	unsigned u1Write : 1;
1322	/** User(=1) / Supervisor (=0) flag. */
1323	unsigned u1User : 1;
1324	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1325	unsigned u1WriteThru : 1;
1326	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1327	unsigned u1CacheDisable : 1;
1328	/** Accessed flag.
1329	* Indicates that the page has been read or written to. */
1330	unsigned u1Accessed : 1;
1331	/** Reserved / Ignored (dirty bit). */
1332	unsigned u1Reserved0 : 1;
1333	/** Size bit if PSE is enabled - in any event it's 0. */
1334	unsigned u1Size : 1;
1335	/** Reserved / Ignored (global bit). */
1336	unsigned u1Reserved1 : 1;
1337	/** Available for use to system software. */
1338	unsigned u3Available : 3;
1339	/** Physical Page number of the next level. */
1340	unsigned u20PageNo : 20;
1341	} X86PDEBITS;
1342	/** Pointer to a page directory entry. */
1343	typedef X86PDEBITS *PX86PDEBITS;
1344	/** Pointer to a const page directory entry. */
1345	typedef const X86PDEBITS *PCX86PDEBITS;
1346
1347
1348	/**
1349	* PAE page directory entry.
1350	*/
1351	typedef struct X86PDEPAEBITS
1352	{
1353	/** Flags whether(=1) or not the page is present. */
1354	uint32_t u1Present : 1;
1355	/** Read(=0) / Write(=1) flag. */
1356	uint32_t u1Write : 1;
1357	/** User(=1) / Supervisor (=0) flag. */
1358	uint32_t u1User : 1;
1359	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1360	uint32_t u1WriteThru : 1;
1361	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1362	uint32_t u1CacheDisable : 1;
1363	/** Accessed flag.
1364	* Indicates that the page has been read or written to. */
1365	uint32_t u1Accessed : 1;
1366	/** Reserved / Ignored (dirty bit). */
1367	uint32_t u1Reserved0 : 1;
1368	/** Size bit if PSE is enabled - in any event it's 0. */
1369	uint32_t u1Size : 1;
1370	/** Reserved / Ignored (global bit). / */
1371	uint32_t u1Reserved1 : 1;
1372	/** Available for use to system software. */
1373	uint32_t u3Available : 3;
1374	/** Physical Page number of the next level - Low Part. Don't use! */
1375	uint32_t u20PageNoLow : 20;
1376	/** Physical Page number of the next level - High Part. Don't use! */
1377	uint32_t u20PageNoHigh : 20;
1378	/** MBZ bits */
1379	uint32_t u11Reserved : 11;
1380	/** No Execute flag. */
1381	uint32_t u1NoExecute : 1;
1382	} X86PDEPAEBITS;
1383	/** Pointer to a page directory entry. */
1384	typedef X86PDEPAEBITS *PX86PDEPAEBITS;
1385	/** Pointer to a const page directory entry. */
1386	typedef const X86PDEPAEBITS *PCX86PDEPAEBITS;
1387
1388	/** @} */
1389
1390
1391	/** @name 2/4MB Page Directory Entry
1392	* @{
1393	*/
1394	/** Bit 0 - P - Present bit. */
1395	#define X86_PDE4M_P RT_BIT(0)
1396	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1397	#define X86_PDE4M_RW RT_BIT(1)
1398	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1399	#define X86_PDE4M_US RT_BIT(2)
1400	/** Bit 3 - PWT - Page level write thru bit. */
1401	#define X86_PDE4M_PWT RT_BIT(3)
1402	/** Bit 4 - PCD - Page level cache disable bit. */
1403	#define X86_PDE4M_PCD RT_BIT(4)
1404	/** Bit 5 - A - Access bit. */
1405	#define X86_PDE4M_A RT_BIT(5)
1406	/** Bit 6 - D - Dirty bit. */
1407	#define X86_PDE4M_D RT_BIT(6)
1408	/** Bit 7 - PS - Page size attribute. Clear mean 4KB pages, set means large pages (2/4MB). */
1409	#define X86_PDE4M_PS RT_BIT(7)
1410	/** Bit 8 - G - Global flag. */
1411	#define X86_PDE4M_G RT_BIT(8)
1412	/** Bits 9-11 - AVL - Available for use to system software. */
1413	#define X86_PDE4M_AVL (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
1414	/** Bit 12 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
1415	#define X86_PDE4M_PAT RT_BIT(12)
1416	/** Shift to get from X86_PTE_PAT to X86_PDE4M_PAT. */
1417	#define X86_PDE4M_PAT_SHIFT (12 - 7)
1418	/** Bits 22-31 - - Physical Page number. */
1419	#define X86_PDE4M_PG_MASK ( 0xffc00000 )
1420	/** Bits 13-20 - - Physical Page number high part (32-39 bits). AMD64 hack. */
1421	#define X86_PDE4M_PG_HIGH_MASK ( 0x001fe000 )
1422	/** The number of bits to the high part of the page number. */
1423	#define X86_PDE4M_PG_HIGH_SHIFT 19
1424
1425	/** Bits 21-51 - - PAE & AMD64 - Physical Page number.
1426	* (Bits 40-51 (long mode) & bits 36-51 (pae legacy) are reserved according to the Intel docs; AMD allows for more.) */
1427	#define X86_PDE2M_PAE_PG_MASK ( 0x000fffffffe00000ULL )
1428	/** Bits 63 - NX - PAE & AMD64 - No execution flag. */
1429	#define X86_PDE2M_PAE_NX X86_PDE2M_PAE_NX
1430
1431	/**
1432	* 4MB page directory entry.
1433	*/
1434	typedef struct X86PDE4MBITS
1435	{
1436	/** Flags whether(=1) or not the page is present. */
1437	unsigned u1Present : 1;
1438	/** Read(=0) / Write(=1) flag. */
1439	unsigned u1Write : 1;
1440	/** User(=1) / Supervisor (=0) flag. */
1441	unsigned u1User : 1;
1442	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1443	unsigned u1WriteThru : 1;
1444	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1445	unsigned u1CacheDisable : 1;
1446	/** Accessed flag.
1447	* Indicates that the page have been read or written to. */
1448	unsigned u1Accessed : 1;
1449	/** Dirty flag.
1450	* Indicates that the page has been written to. */
1451	unsigned u1Dirty : 1;
1452	/** Page size flag - always 1 for 4MB entries. */
1453	unsigned u1Size : 1;
1454	/** Global flag. */
1455	unsigned u1Global : 1;
1456	/** Available for use to system software. */
1457	unsigned u3Available : 3;
1458	/** Reserved / If PAT enabled, bit 2 of the index. */
1459	unsigned u1PAT : 1;
1460	/** Bits 32-39 of the page number on AMD64.
1461	* This AMD64 hack allows accessing 40bits of physical memory without PAE. */
1462	unsigned u8PageNoHigh : 8;
1463	/** Reserved. */
1464	unsigned u1Reserved : 1;
1465	/** Physical Page number of the page. */
1466	unsigned u10PageNo : 10;
1467	} X86PDE4MBITS;
1468	/** Pointer to a page table entry. */
1469	typedef X86PDE4MBITS *PX86PDE4MBITS;
1470	/** Pointer to a const page table entry. */
1471	typedef const X86PDE4MBITS *PCX86PDE4MBITS;
1472
1473
1474	/**
1475	* 2MB PAE page directory entry.
1476	*/
1477	typedef struct X86PDE2MPAEBITS
1478	{
1479	/** Flags whether(=1) or not the page is present. */
1480	uint32_t u1Present : 1;
1481	/** Read(=0) / Write(=1) flag. */
1482	uint32_t u1Write : 1;
1483	/** User(=1) / Supervisor(=0) flag. */
1484	uint32_t u1User : 1;
1485	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1486	uint32_t u1WriteThru : 1;
1487	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1488	uint32_t u1CacheDisable : 1;
1489	/** Accessed flag.
1490	* Indicates that the page have been read or written to. */
1491	uint32_t u1Accessed : 1;
1492	/** Dirty flag.
1493	* Indicates that the page has been written to. */
1494	uint32_t u1Dirty : 1;
1495	/** Page size flag - always 1 for 2MB entries. */
1496	uint32_t u1Size : 1;
1497	/** Global flag. */
1498	uint32_t u1Global : 1;
1499	/** Available for use to system software. */
1500	uint32_t u3Available : 3;
1501	/** Reserved / If PAT enabled, bit 2 of the index. */
1502	uint32_t u1PAT : 1;
1503	/** Reserved. */
1504	uint32_t u9Reserved : 9;
1505	/** Physical Page number of the next level - Low part. Don't use! */
1506	uint32_t u10PageNoLow : 10;
1507	/** Physical Page number of the next level - High part. Don't use! */
1508	uint32_t u20PageNoHigh : 20;
1509	/** MBZ bits */
1510	uint32_t u11Reserved : 11;
1511	/** No Execute flag. */
1512	uint32_t u1NoExecute : 1;
1513	} X86PDE2MPAEBITS;
1514	/** Pointer to a 2MB PAE page table entry. */
1515	typedef X86PDE2MPAEBITS *PX86PDE2MPAEBITS;
1516	/** Pointer to a 2MB PAE page table entry. */
1517	typedef const X86PDE2MPAEBITS *PCX86PDE2MPAEBITS;
1518
1519	/** @} */
1520
1521	/**
1522	* Page directory entry.
1523	*/
1524	typedef union X86PDE
1525	{
1526	/** Unsigned integer view. */
1527	X86PGUINT u;
1528	/** Normal view. */
1529	X86PDEBITS n;
1530	/** 4MB view (big). */
1531	X86PDE4MBITS b;
1532	/** 8 bit unsigned integer view. */
1533	uint8_t au8[4];
1534	/** 16 bit unsigned integer view. */
1535	uint16_t au16[2];
1536	/** 32 bit unsigned integer view. */
1537	uint32_t au32[1];
1538	} X86PDE;
1539	/** Pointer to a page directory entry. */
1540	typedef X86PDE *PX86PDE;
1541	/** Pointer to a const page directory entry. */
1542	typedef const X86PDE *PCX86PDE;
1543
1544	/**
1545	* PAE page directory entry.
1546	*/
1547	typedef union X86PDEPAE
1548	{
1549	/** Unsigned integer view. */
1550	X86PGPAEUINT u;
1551	/** Normal view. */
1552	X86PDEPAEBITS n;
1553	/** 2MB page view (big). */
1554	X86PDE2MPAEBITS b;
1555	/** 8 bit unsigned integer view. */
1556	uint8_t au8[8];
1557	/** 16 bit unsigned integer view. */
1558	uint16_t au16[4];
1559	/** 32 bit unsigned integer view. */
1560	uint32_t au32[2];
1561	} X86PDEPAE;
1562	/** Pointer to a page directory entry. */
1563	typedef X86PDEPAE *PX86PDEPAE;
1564	/** Pointer to a const page directory entry. */
1565	typedef const X86PDEPAE *PCX86PDEPAE;
1566
1567	/**
1568	* Page directory.
1569	*/
1570	typedef struct X86PD
1571	{
1572	/** PDE Array. */
1573	X86PDE a[X86_PG_ENTRIES];
1574	} X86PD;
1575	/** Pointer to a page directory. */
1576	typedef X86PD *PX86PD;
1577	/** Pointer to a const page directory. */
1578	typedef const X86PD *PCX86PD;
1579
1580	/** The page shift to get the PD index. */
1581	#define X86_PD_SHIFT 22
1582	/** The PD index mask (apply to a shifted page address). */
1583	#define X86_PD_MASK 0x3ff
1584
1585
1586	/**
1587	* PAE page directory.
1588	*/
1589	typedef struct X86PDPAE
1590	{
1591	/** PDE Array. */
1592	X86PDEPAE a[X86_PG_PAE_ENTRIES];
1593	} X86PDPAE;
1594	/** Pointer to a PAE page directory. */
1595	typedef X86PDPAE *PX86PDPAE;
1596	/** Pointer to a const PAE page directory. */
1597	typedef const X86PDPAE *PCX86PDPAE;
1598
1599	/** The page shift to get the PAE PD index. */
1600	#define X86_PD_PAE_SHIFT 21
1601	/** The PAE PD index mask (apply to a shifted page address). */
1602	#define X86_PD_PAE_MASK 0x1ff
1603
1604
1605	/** @name Page Directory Pointer Table Entry (PAE)
1606	* @{
1607	*/
1608	/** Bit 0 - P - Present bit. */
1609	#define X86_PDPE_P RT_BIT(0)
1610	/** Bit 1 - R/W - Read (clear) / Write (set) bit. Long Mode only. */
1611	#define X86_PDPE_RW RT_BIT(1)
1612	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. Long Mode only. */
1613	#define X86_PDPE_US RT_BIT(2)
1614	/** Bit 3 - PWT - Page level write thru bit. */
1615	#define X86_PDPE_PWT RT_BIT(3)
1616	/** Bit 4 - PCD - Page level cache disable bit. */
1617	#define X86_PDPE_PCD RT_BIT(4)
1618	/** Bit 5 - A - Access bit. Long Mode only. */
1619	#define X86_PDPE_A RT_BIT(5)
1620	/** Bits 9-11 - - Available for use to system software. */
1621	#define X86_PDPE_AVL_MASK (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
1622	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1623	#if 1 /* we're using this internally and have to mask of the top 16-bit. */
1624	#define X86_PDPE_PG_MASK ( 0x0000fffffffff000ULL )
1625	/** @todo Get rid of the above hack; makes code unreadable. */
1626	#define X86_PDPE_PG_MASK_FULL ( 0x000ffffffffff000ULL )
1627	#else
1628	#define X86_PDPE_PG_MASK ( 0x000ffffffffff000ULL )
1629	#endif
1630	/** Bits 63 - NX - PAE - No execution flag. Long Mode only. */
1631	#define X86_PDPE_NX RT_BIT_64(63)
1632
1633	/**
1634	* Page directory pointer table entry.
1635	*/
1636	typedef struct X86PDPEBITS
1637	{
1638	/** Flags whether(=1) or not the page is present. */
1639	uint32_t u1Present : 1;
1640	/** Chunk of reserved bits. */
1641	uint32_t u2Reserved : 2;
1642	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1643	uint32_t u1WriteThru : 1;
1644	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1645	uint32_t u1CacheDisable : 1;
1646	/** Chunk of reserved bits. */
1647	uint32_t u4Reserved : 4;
1648	/** Available for use to system software. */
1649	uint32_t u3Available : 3;
1650	/** Physical Page number of the next level - Low Part. Don't use! */
1651	uint32_t u20PageNoLow : 20;
1652	/** Physical Page number of the next level - High Part. Don't use! */
1653	uint32_t u20PageNoHigh : 20;
1654	/** MBZ bits */
1655	uint32_t u12Reserved : 12;
1656	} X86PDPEBITS;
1657	/** Pointer to a page directory pointer table entry. */
1658	typedef X86PDPEBITS *PX86PTPEBITS;
1659	/** Pointer to a const page directory pointer table entry. */
1660	typedef const X86PDPEBITS *PCX86PTPEBITS;
1661
1662	/**
1663	* Page directory pointer table entry. AMD64 version
1664	*/
1665	typedef struct X86PDPEAMD64BITS
1666	{
1667	/** Flags whether(=1) or not the page is present. */
1668	uint32_t u1Present : 1;
1669	/** Read(=0) / Write(=1) flag. */
1670	uint32_t u1Write : 1;
1671	/** User(=1) / Supervisor (=0) flag. */
1672	uint32_t u1User : 1;
1673	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1674	uint32_t u1WriteThru : 1;
1675	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1676	uint32_t u1CacheDisable : 1;
1677	/** Accessed flag.
1678	* Indicates that the page have been read or written to. */
1679	uint32_t u1Accessed : 1;
1680	/** Chunk of reserved bits. */
1681	uint32_t u3Reserved : 3;
1682	/** Available for use to system software. */
1683	uint32_t u3Available : 3;
1684	/** Physical Page number of the next level - Low Part. Don't use! */
1685	uint32_t u20PageNoLow : 20;
1686	/** Physical Page number of the next level - High Part. Don't use! */
1687	uint32_t u20PageNoHigh : 20;
1688	/** MBZ bits */
1689	uint32_t u11Reserved : 11;
1690	/** No Execute flag. */
1691	uint32_t u1NoExecute : 1;
1692	} X86PDPEAMD64BITS;
1693	/** Pointer to a page directory pointer table entry. */
1694	typedef X86PDPEAMD64BITS *PX86PDPEAMD64BITS;
1695	/** Pointer to a const page directory pointer table entry. */
1696	typedef const X86PDPEBITS *PCX86PDPEAMD64BITS;
1697
1698	/**
1699	* Page directory pointer table entry.
1700	*/
1701	typedef union X86PDPE
1702	{
1703	/** Unsigned integer view. */
1704	X86PGPAEUINT u;
1705	/** Normal view. */
1706	X86PDPEBITS n;
1707	/** AMD64 view. */
1708	X86PDPEAMD64BITS lm;
1709	/** 8 bit unsigned integer view. */
1710	uint8_t au8[8];
1711	/** 16 bit unsigned integer view. */
1712	uint16_t au16[4];
1713	/** 32 bit unsigned integer view. */
1714	uint32_t au32[2];
1715	} X86PDPE;
1716	/** Pointer to a page directory pointer table entry. */
1717	typedef X86PDPE *PX86PDPE;
1718	/** Pointer to a const page directory pointer table entry. */
1719	typedef const X86PDPE *PCX86PDPE;
1720
1721
1722	/**
1723	* Page directory pointer table.
1724	*/
1725	typedef struct X86PDPT
1726	{
1727	/** PDE Array. */
1728	X86PDPE a[X86_PG_AMD64_PDPE_ENTRIES];
1729	} X86PDPT;
1730	/** Pointer to a page directory pointer table. */
1731	typedef X86PDPT *PX86PDPT;
1732	/** Pointer to a const page directory pointer table. */
1733	typedef const X86PDPT *PCX86PDPT;
1734
1735	/** The page shift to get the PDPT index. */
1736	#define X86_PDPT_SHIFT 30
1737	/** The PDPT index mask (apply to a shifted page address). (32 bits PAE) */
1738	#define X86_PDPT_MASK_PAE 0x3
1739	/** The PDPT index mask (apply to a shifted page address). (64 bits PAE)*/
1740	#define X86_PDPT_MASK_AMD64 0x1ff
1741
1742	/** @} */
1743
1744
1745	/** @name Page Map Level-4 Entry (Long Mode PAE)
1746	* @{
1747	*/
1748	/** Bit 0 - P - Present bit. */
1749	#define X86_PML4E_P RT_BIT(0)
1750	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1751	#define X86_PML4E_RW RT_BIT(1)
1752	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1753	#define X86_PML4E_US RT_BIT(2)
1754	/** Bit 3 - PWT - Page level write thru bit. */
1755	#define X86_PML4E_PWT RT_BIT(3)
1756	/** Bit 4 - PCD - Page level cache disable bit. */
1757	#define X86_PML4E_PCD RT_BIT(4)
1758	/** Bit 5 - A - Access bit. */
1759	#define X86_PML4E_A RT_BIT(5)
1760	/** Bits 9-11 - - Available for use to system software. */
1761	#define X86_PML4E_AVL_MASK (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
1762	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1763	#if 1 /* we're using this internally and have to mask of the top 16-bit. */
1764	#define X86_PML4E_PG_MASK ( 0x0000fffffffff000ULL )
1765	#define X86_PML4E_PG_MASK_FULL ( 0x000ffffffffff000ULL )
1766	#else
1767	#define X86_PML4E_PG_MASK ( 0x000ffffffffff000ULL )
1768	#endif
1769	/** Bits 63 - NX - PAE - No execution flag. */
1770	#define X86_PML4E_NX RT_BIT_64(63)
1771
1772	/**
1773	* Page Map Level-4 Entry
1774	*/
1775	typedef struct X86PML4EBITS
1776	{
1777	/** Flags whether(=1) or not the page is present. */
1778	uint32_t u1Present : 1;
1779	/** Read(=0) / Write(=1) flag. */
1780	uint32_t u1Write : 1;
1781	/** User(=1) / Supervisor (=0) flag. */
1782	uint32_t u1User : 1;
1783	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1784	uint32_t u1WriteThru : 1;
1785	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1786	uint32_t u1CacheDisable : 1;
1787	/** Accessed flag.
1788	* Indicates that the page have been read or written to. */
1789	uint32_t u1Accessed : 1;
1790	/** Chunk of reserved bits. */
1791	uint32_t u3Reserved : 3;
1792	/** Available for use to system software. */
1793	uint32_t u3Available : 3;
1794	/** Physical Page number of the next level - Low Part. Don't use! */
1795	uint32_t u20PageNoLow : 20;
1796	/** Physical Page number of the next level - High Part. Don't use! */
1797	uint32_t u20PageNoHigh : 20;
1798	/** MBZ bits */
1799	uint32_t u11Reserved : 11;
1800	/** No Execute flag. */
1801	uint32_t u1NoExecute : 1;
1802	} X86PML4EBITS;
1803	/** Pointer to a page map level-4 entry. */
1804	typedef X86PML4EBITS *PX86PML4EBITS;
1805	/** Pointer to a const page map level-4 entry. */
1806	typedef const X86PML4EBITS *PCX86PML4EBITS;
1807
1808	/**
1809	* Page Map Level-4 Entry.
1810	*/
1811	typedef union X86PML4E
1812	{
1813	/** Unsigned integer view. */
1814	X86PGPAEUINT u;
1815	/** Normal view. */
1816	X86PML4EBITS n;
1817	/** 8 bit unsigned integer view. */
1818	uint8_t au8[8];
1819	/** 16 bit unsigned integer view. */
1820	uint16_t au16[4];
1821	/** 32 bit unsigned integer view. */
1822	uint32_t au32[2];
1823	} X86PML4E;
1824	/** Pointer to a page map level-4 entry. */
1825	typedef X86PML4E *PX86PML4E;
1826	/** Pointer to a const page map level-4 entry. */
1827	typedef const X86PML4E *PCX86PML4E;
1828
1829
1830	/**
1831	* Page Map Level-4.
1832	*/
1833	typedef struct X86PML4
1834	{
1835	/** PDE Array. */
1836	X86PML4E a[X86_PG_PAE_ENTRIES];
1837	} X86PML4;
1838	/** Pointer to a page map level-4. */
1839	typedef X86PML4 *PX86PML4;
1840	/** Pointer to a const page map level-4. */
1841	typedef const X86PML4 *PCX86PML4;
1842
1843	/** The page shift to get the PML4 index. */
1844	#define X86_PML4_SHIFT 39
1845	/** The PML4 index mask (apply to a shifted page address). */
1846	#define X86_PML4_MASK 0x1ff
1847
1848	/** @} */
1849
1850	/** @} */
1851
1852
1853	/**
1854	* 80-bit MMX/FPU register type.
1855	*/
1856	typedef struct X86FPUMMX
1857	{
1858	uint8_t reg[10];
1859	} X86FPUMMX;
1860	/** Pointer to a 80-bit MMX/FPU register type. */
1861	typedef X86FPUMMX *PX86FPUMMX;
1862	/** Pointer to a const 80-bit MMX/FPU register type. */
1863	typedef const X86FPUMMX *PCX86FPUMMX;
1864
1865	/**
1866	* FPU state (aka FSAVE/FRSTOR Memory Region).
1867	*/
1868	#pragma pack(1)
1869	typedef struct X86FPUSTATE
1870	{
1871	/** Control word. */
1872	uint16_t FCW;
1873	/** Alignment word */
1874	uint16_t Dummy1;
1875	/** Status word. */
1876	uint16_t FSW;
1877	/** Alignment word */
1878	uint16_t Dummy2;
1879	/** Tag word */
1880	uint16_t FTW;
1881	/** Alignment word */
1882	uint16_t Dummy3;
1883
1884	/** Instruction pointer. */
1885	uint32_t FPUIP;
1886	/** Code selector. */
1887	uint16_t CS;
1888	/** Opcode. */
1889	uint16_t FOP;
1890	/** FOO. */
1891	uint32_t FPUOO;
1892	/** FOS. */
1893	uint32_t FPUOS;
1894	/** FPU view - todo. */
1895	X86FPUMMX regs[8];
1896	} X86FPUSTATE;
1897	#pragma pack()
1898	/** Pointer to a FPU state. */
1899	typedef X86FPUSTATE *PX86FPUSTATE;
1900	/** Pointer to a const FPU state. */
1901	typedef const X86FPUSTATE *PCX86FPUSTATE;
1902
1903	/**
1904	* FPU Extended state (aka FXSAVE/FXRSTORE Memory Region).
1905	*/
1906	#pragma pack(1)
1907	typedef struct X86FXSTATE
1908	{
1909	/** Control word. */
1910	uint16_t FCW;
1911	/** Status word. */
1912	uint16_t FSW;
1913	/** Tag word. (The upper byte is always zero.) */
1914	uint16_t FTW;
1915	/** Opcode. */
1916	uint16_t FOP;
1917	/** Instruction pointer. */
1918	uint32_t FPUIP;
1919	/** Code selector. */
1920	uint16_t CS;
1921	uint16_t Rsvrd1;
1922	/* - offset 16 - */
1923	/** Data pointer. */
1924	uint32_t FPUDP;
1925	/** Data segment */
1926	uint16_t DS;
1927	uint16_t Rsrvd2;
1928	uint32_t MXCSR;
1929	uint32_t MXCSR_MASK;
1930	/* - offset 32 - */
1931	union
1932	{
1933	/** MMX view. */
1934	uint64_t mmx;
1935	/** FPU view - todo. */
1936	X86FPUMMX fpu;
1937	/** 8-bit view. */
1938	uint8_t au8[16];
1939	/** 16-bit view. */
1940	uint16_t au16[8];
1941	/** 32-bit view. */
1942	uint32_t au32[4];
1943	/** 64-bit view. */
1944	uint64_t au64[2];
1945	/** 128-bit view. (yeah, very helpful) */
1946	uint128_t au128[1];
1947	} aRegs[8];
1948	/* - offset 160 - */
1949	union
1950	{
1951	/** XMM Register view . /
1952	uint128_t xmm;
1953	/** 8-bit view. */
1954	uint8_t au8[16];
1955	/** 16-bit view. */
1956	uint16_t au16[8];
1957	/** 32-bit view. */
1958	uint32_t au32[4];
1959	/** 64-bit view. */
1960	uint64_t au64[2];
1961	/** 128-bit view. (yeah, very helpful) */
1962	uint128_t au128[1];
1963	} aXMM[16]; /* 8 registers in 32 bits mode; 16 in long mode */
1964	/* - offset 416 - */
1965	uint32_t au32RsrvdRest[(512 - 416) / sizeof(uint32_t)];
1966	} X86FXSTATE;
1967	#pragma pack()
1968	/** Pointer to a FPU Extended state. */
1969	typedef X86FXSTATE *PX86FXSTATE;
1970	/** Pointer to a const FPU Extended state. */
1971	typedef const X86FXSTATE *PCX86FXSTATE;
1972
1973
1974	/** @name Selector Descriptor
1975	* @{
1976	*/
1977
1978	/**
1979	* Descriptor attributes.
1980	*/
1981	typedef struct X86DESCATTRBITS
1982	{
1983	/** 00 - Segment Type. */
1984	unsigned u4Type : 4;
1985	/** 04 - Descriptor Type. System(=0) or code/data selector */
1986	unsigned u1DescType : 1;
1987	/** 05 - Descriptor Privelege level. */
1988	unsigned u2Dpl : 2;
1989	/** 07 - Flags selector present(=1) or not. */
1990	unsigned u1Present : 1;
1991	/** 08 - Segment limit 16-19. */
1992	unsigned u4LimitHigh : 4;
1993	/** 0c - Available for system software. */
1994	unsigned u1Available : 1;
1995	/** 0d - 32 bits mode: Reserved - 0, long mode: Long Attribute Bit. */
1996	unsigned u1Long : 1;
1997	/** 0e - This flags meaning depends on the segment type. Try make sense out
1998	* of the intel manual yourself. */
1999	unsigned u1DefBig : 1;
2000	/** 0f - Granularity of the limit. If set 4KB granularity is used, if
2001	* clear byte. */
2002	unsigned u1Granularity : 1;
2003	} X86DESCATTRBITS;
2004
2005
2006	#pragma pack(1)
2007	typedef union X86DESCATTR
2008	{
2009	/** Unsigned integer view. */
2010	uint32_t u;
2011	/** Normal view. */
2012	X86DESCATTRBITS n;
2013	} X86DESCATTR;
2014	#pragma pack()
2015	/** Pointer to descriptor attributes. */
2016	typedef X86DESCATTR *PX86DESCATTR;
2017	/** Pointer to const descriptor attributes. */
2018	typedef const X86DESCATTR *PCX86DESCATTR;
2019
2020
2021	/**
2022	* Generic descriptor table entry
2023	*/
2024	#pragma pack(1)
2025	typedef struct X86DESCGENERIC
2026	{
2027	/** Limit - Low word. */
2028	unsigned u16LimitLow : 16;
2029	/** Base address - lowe word.
2030	* Don't try set this to 24 because MSC is doing stupid things then. */
2031	unsigned u16BaseLow : 16;
2032	/** Base address - first 8 bits of high word. */
2033	unsigned u8BaseHigh1 : 8;
2034	/** Segment Type. */
2035	unsigned u4Type : 4;
2036	/** Descriptor Type. System(=0) or code/data selector */
2037	unsigned u1DescType : 1;
2038	/** Descriptor Privelege level. */
2039	unsigned u2Dpl : 2;
2040	/** Flags selector present(=1) or not. */
2041	unsigned u1Present : 1;
2042	/** Segment limit 16-19. */
2043	unsigned u4LimitHigh : 4;
2044	/** Available for system software. */
2045	unsigned u1Available : 1;
2046	/** 32 bits mode: Reserved - 0, long mode: Long Attribute Bit. */
2047	unsigned u1Long : 1;
2048	/** This flags meaning depends on the segment type. Try make sense out
2049	* of the intel manual yourself. */
2050	unsigned u1DefBig : 1;
2051	/** Granularity of the limit. If set 4KB granularity is used, if
2052	* clear byte. */
2053	unsigned u1Granularity : 1;
2054	/** Base address - highest 8 bits. */
2055	unsigned u8BaseHigh2 : 8;
2056	} X86DESCGENERIC;
2057	#pragma pack()
2058	/** Pointer to a generic descriptor entry. */
2059	typedef X86DESCGENERIC *PX86DESCGENERIC;
2060	/** Pointer to a const generic descriptor entry. */
2061	typedef const X86DESCGENERIC *PCX86DESCGENERIC;
2062
2063	/**
2064	* Call-, Interrupt-, Trap- or Task-gate descriptor (legacy).
2065	*/
2066	typedef struct X86DESCGATE
2067	{
2068	/** Target code segment offset - Low word.
2069	* Ignored if task-gate. */
2070	unsigned u16OffsetLow : 16;
2071	/** Target code segment selector for call-, interrupt- and trap-gates,
2072	* TSS selector if task-gate. */
2073	unsigned u16Sel : 16;
2074	/** Number of parameters for a call-gate.
2075	* Ignored if interrupt-, trap- or task-gate. */
2076	unsigned u4ParmCount : 4;
2077	/** Reserved / ignored. */
2078	unsigned u4Reserved : 4;
2079	/** Segment Type. */
2080	unsigned u4Type : 4;
2081	/** Descriptor Type (0 = system). */
2082	unsigned u1DescType : 1;
2083	/** Descriptor Privelege level. */
2084	unsigned u2Dpl : 2;
2085	/** Flags selector present(=1) or not. */
2086	unsigned u1Present : 1;
2087	/** Target code segment offset - High word.
2088	* Ignored if task-gate. */
2089	unsigned u16OffsetHigh : 16;
2090	} X86DESCGATE;
2091	AssertCompileSize(X86DESCGATE, 8);
2092	/** Pointer to a Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
2093	typedef X86DESCGATE *PX86DESCGATE;
2094	/** Pointer to a const Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
2095	typedef const X86DESCGATE *PCX86DESCGATE;
2096
2097	/**
2098	* Descriptor table entry.
2099	*/
2100	#pragma pack(1)
2101	typedef union X86DESC
2102	{
2103	/** Generic descriptor view. */
2104	X86DESCGENERIC Gen;
2105	/** Gate descriptor view. */
2106	X86DESCGATE Gate;
2107
2108	/** 8 bit unsigned interger view. */
2109	uint8_t au8[8];
2110	/** 16 bit unsigned interger view. */
2111	uint16_t au16[4];
2112	/** 32 bit unsigned interger view. */
2113	uint32_t au32[2];
2114	} X86DESC;
2115	AssertCompileSize(X86DESC, 8);
2116	#pragma pack()
2117	/** Pointer to descriptor table entry. */
2118	typedef X86DESC *PX86DESC;
2119	/** Pointer to const descriptor table entry. */
2120	typedef const X86DESC *PCX86DESC;
2121
2122	/** @def X86DESC_BASE
2123	* Return the base address of a descriptor.
2124	*/
2125	#define X86DESC_BASE(desc) /ASM-NOINC/ \
2126	( ((uint32_t)((desc).Gen.u8BaseHigh2) << 24) \
2127	\| ( (desc).Gen.u8BaseHigh1 << 16) \
2128	\| ( (desc).Gen.u16BaseLow ) )
2129
2130	/** @def X86DESC_LIMIT
2131	* Return the limit of a descriptor.
2132	*/
2133	#define X86DESC_LIMIT(desc) /ASM-NOINC/ \
2134	( ((uint32_t)((desc).Gen.u4LimitHigh) << 16) \
2135	\| ( (desc).Gen.u16LimitLow ) )
2136
2137	/**
2138	* 64 bits generic descriptor table entry
2139	* Note: most of these bits have no meaning in long mode.
2140	*/
2141	#pragma pack(1)
2142	typedef struct X86DESC64GENERIC
2143	{
2144	/** Limit - Low word - IGNORED. */
2145	unsigned u16LimitLow : 16;
2146	/** Base address - lowe word. - IGNORED
2147	* Don't try set this to 24 because MSC is doing stupid things then. */
2148	unsigned u16BaseLow : 16;
2149	/** Base address - first 8 bits of high word. - IGNORED */
2150	unsigned u8BaseHigh1 : 8;
2151	/** Segment Type. */
2152	unsigned u4Type : 4;
2153	/** Descriptor Type. System(=0) or code/data selector */
2154	unsigned u1DescType : 1;
2155	/** Descriptor Privelege level. */
2156	unsigned u2Dpl : 2;
2157	/** Flags selector present(=1) or not. */
2158	unsigned u1Present : 1;
2159	/** Segment limit 16-19. - IGNORED */
2160	unsigned u4LimitHigh : 4;
2161	/** Available for system software. - IGNORED */
2162	unsigned u1Available : 1;
2163	/** Long mode flag. */
2164	unsigned u1Long : 1;
2165	/** This flags meaning depends on the segment type. Try make sense out
2166	* of the intel manual yourself. */
2167	unsigned u1DefBig : 1;
2168	/** Granularity of the limit. If set 4KB granularity is used, if
2169	* clear byte. - IGNORED */
2170	unsigned u1Granularity : 1;
2171	/** Base address - highest 8 bits. - IGNORED */
2172	unsigned u8BaseHigh2 : 8;
2173	/** Base address - bits 63-32. */
2174	unsigned u32BaseHigh3 : 32;
2175	unsigned u8Reserved : 8;
2176	unsigned u5Zeros : 5;
2177	unsigned u19Reserved : 19;
2178	} X86DESC64GENERIC;
2179	#pragma pack()
2180	/** Pointer to a generic descriptor entry. */
2181	typedef X86DESC64GENERIC *PX86DESC64GENERIC;
2182	/** Pointer to a const generic descriptor entry. */
2183	typedef const X86DESC64GENERIC *PCX86DESC64GENERIC;
2184
2185	/**
2186	* System descriptor table entry (64 bits)
2187	*
2188	* @remarks This is, save a couple of comments, identical to X86DESC64GENERIC...
2189	*/
2190	#pragma pack(1)
2191	typedef struct X86DESC64SYSTEM
2192	{
2193	/** Limit - Low word. */
2194	unsigned u16LimitLow : 16;
2195	/** Base address - lowe word.
2196	* Don't try set this to 24 because MSC is doing stupid things then. */
2197	unsigned u16BaseLow : 16;
2198	/** Base address - first 8 bits of high word. */
2199	unsigned u8BaseHigh1 : 8;
2200	/** Segment Type. */
2201	unsigned u4Type : 4;
2202	/** Descriptor Type. System(=0) or code/data selector */
2203	unsigned u1DescType : 1;
2204	/** Descriptor Privelege level. */
2205	unsigned u2Dpl : 2;
2206	/** Flags selector present(=1) or not. */
2207	unsigned u1Present : 1;
2208	/** Segment limit 16-19. */
2209	unsigned u4LimitHigh : 4;
2210	/** Available for system software. */
2211	unsigned u1Available : 1;
2212	/** Reserved - 0. */
2213	unsigned u1Reserved : 1;
2214	/** This flags meaning depends on the segment type. Try make sense out
2215	* of the intel manual yourself. */
2216	unsigned u1DefBig : 1;
2217	/** Granularity of the limit. If set 4KB granularity is used, if
2218	* clear byte. */
2219	unsigned u1Granularity : 1;
2220	/** Base address - bits 31-24. */
2221	unsigned u8BaseHigh2 : 8;
2222	/** Base address - bits 63-32. */
2223	unsigned u32BaseHigh3 : 32;
2224	unsigned u8Reserved : 8;
2225	unsigned u5Zeros : 5;
2226	unsigned u19Reserved : 19;
2227	} X86DESC64SYSTEM;
2228	#pragma pack()
2229	/** Pointer to a system descriptor entry. */
2230	typedef X86DESC64SYSTEM *PX86DESC64SYSTEM;
2231	/** Pointer to a const system descriptor entry. */
2232	typedef const X86DESC64SYSTEM *PCX86DESC64SYSTEM;
2233
2234	/**
2235	* Call-, Interrupt-, Trap- or Task-gate descriptor (64-bit).
2236	*/
2237	typedef struct X86DESC64GATE
2238	{
2239	/** Target code segment offset - Low word. */
2240	unsigned u16OffsetLow : 16;
2241	/** Target code segment selector. */
2242	unsigned u16Sel : 16;
2243	/** Interrupt stack table for interrupt- and trap-gates.
2244	* Ignored by call-gates. */
2245	unsigned u3IST : 3;
2246	/** Reserved / ignored. */
2247	unsigned u5Reserved : 5;
2248	/** Segment Type. */
2249	unsigned u4Type : 4;
2250	/** Descriptor Type (0 = system). */
2251	unsigned u1DescType : 1;
2252	/** Descriptor Privelege level. */
2253	unsigned u2Dpl : 2;
2254	/** Flags selector present(=1) or not. */
2255	unsigned u1Present : 1;
2256	/** Target code segment offset - High word.
2257	* Ignored if task-gate. */
2258	unsigned u16OffsetHigh : 16;
2259	/** Target code segment offset - Top dword.
2260	* Ignored if task-gate. */
2261	unsigned u32OffsetTop : 32;
2262	/** Reserved / ignored / must be zero.
2263	* For call-gates bits 8 thru 12 must be zero, the other gates ignores this. */
2264	unsigned u32Reserved : 32;
2265	} X86DESC64GATE;
2266	AssertCompileSize(X86DESC64GATE, 16);
2267	/** Pointer to a Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
2268	typedef X86DESC64GATE *PX86DESC64GATE;
2269	/** Pointer to a const Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
2270	typedef const X86DESC64GATE *PCX86DESC64GATE;
2271
2272
2273	/**
2274	* Descriptor table entry.
2275	*/
2276	#pragma pack(1)
2277	typedef union X86DESC64
2278	{
2279	/** Generic descriptor view. */
2280	X86DESC64GENERIC Gen;
2281	/** System descriptor view. */
2282	X86DESC64SYSTEM System;
2283	/** Gate descriptor view. */
2284	X86DESC64GATE Gate;
2285
2286	/** 8 bit unsigned interger view. */
2287	uint8_t au8[16];
2288	/** 16 bit unsigned interger view. */
2289	uint16_t au16[8];
2290	/** 32 bit unsigned interger view. */
2291	uint32_t au32[4];
2292	/** 64 bit unsigned interger view. */
2293	uint64_t au64[2];
2294	} X86DESC64;
2295	AssertCompileSize(X86DESC64, 16);
2296	#pragma pack()
2297	/** Pointer to descriptor table entry. */
2298	typedef X86DESC64 *PX86DESC64;
2299	/** Pointer to const descriptor table entry. */
2300	typedef const X86DESC64 *PCX86DESC64;
2301
2302	/** @def X86DESC64_BASE
2303	* Return the base of a 64-bit descriptor.
2304	*/
2305	#define X86DESC64_BASE(desc) /ASM-NOINC/ \
2306	( ((uint64_t)((desc).Gen.u32BaseHigh3) << 32) \
2307	\| ((uint32_t)((desc).Gen.u8BaseHigh2) << 24) \
2308	\| ( (desc).Gen.u8BaseHigh1 << 16) \
2309	\| ( (desc).Gen.u16BaseLow ) )
2310
2311
2312
2313	/** @name Host system descriptor table entry - Use with care!
2314	* @{ */
2315	/** Host system descriptor table entry. */
2316	#if HC_ARCH_BITS == 64
2317	typedef X86DESC64 X86DESCHC;
2318	#else
2319	typedef X86DESC X86DESCHC;
2320	#endif
2321	/** Pointer to a host system descriptor table entry. */
2322	#if HC_ARCH_BITS == 64
2323	typedef PX86DESC64 PX86DESCHC;
2324	#else
2325	typedef PX86DESC PX86DESCHC;
2326	#endif
2327	/** Pointer to a const host system descriptor table entry. */
2328	#if HC_ARCH_BITS == 64
2329	typedef PCX86DESC64 PCX86DESCHC;
2330	#else
2331	typedef PCX86DESC PCX86DESCHC;
2332	#endif
2333	/** @} */
2334
2335
2336	/** @name Selector Descriptor Types.
2337	* @{
2338	*/
2339
2340	/** @name Non-System Selector Types.
2341	* @{ */
2342	/** Code(=set)/Data(=clear) bit. */
2343	#define X86_SEL_TYPE_CODE 8
2344	/** Memory(=set)/System(=clear) bit. */
2345	#define X86_SEL_TYPE_MEMORY RT_BIT(4)
2346	/** Accessed bit. */
2347	#define X86_SEL_TYPE_ACCESSED 1
2348	/** Expand down bit (for data selectors only). */
2349	#define X86_SEL_TYPE_DOWN 4
2350	/** Conforming bit (for code selectors only). */
2351	#define X86_SEL_TYPE_CONF 4
2352	/** Write bit (for data selectors only). */
2353	#define X86_SEL_TYPE_WRITE 2
2354	/** Read bit (for code selectors only). */
2355	#define X86_SEL_TYPE_READ 2
2356
2357	/** Read only selector type. */
2358	#define X86_SEL_TYPE_RO 0
2359	/** Accessed read only selector type. */
2360	#define X86_SEL_TYPE_RO_ACC (0 \| X86_SEL_TYPE_ACCESSED)
2361	/** Read write selector type. */
2362	#define X86_SEL_TYPE_RW 2
2363	/** Accessed read write selector type. */
2364	#define X86_SEL_TYPE_RW_ACC (2 \| X86_SEL_TYPE_ACCESSED)
2365	/** Expand down read only selector type. */
2366	#define X86_SEL_TYPE_RO_DOWN 4
2367	/** Accessed expand down read only selector type. */
2368	#define X86_SEL_TYPE_RO_DOWN_ACC (4 \| X86_SEL_TYPE_ACCESSED)
2369	/** Expand down read write selector type. */
2370	#define X86_SEL_TYPE_RW_DOWN 6
2371	/** Accessed expand down read write selector type. */
2372	#define X86_SEL_TYPE_RW_DOWN_ACC (6 \| X86_SEL_TYPE_ACCESSED)
2373	/** Execute only selector type. */
2374	#define X86_SEL_TYPE_EO (0 \| X86_SEL_TYPE_CODE)
2375	/** Accessed execute only selector type. */
2376	#define X86_SEL_TYPE_EO_ACC (0 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
2377	/** Execute and read selector type. */
2378	#define X86_SEL_TYPE_ER (2 \| X86_SEL_TYPE_CODE)
2379	/** Accessed execute and read selector type. */
2380	#define X86_SEL_TYPE_ER_ACC (2 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
2381	/** Conforming execute only selector type. */
2382	#define X86_SEL_TYPE_EO_CONF (4 \| X86_SEL_TYPE_CODE)
2383	/** Accessed Conforming execute only selector type. */
2384	#define X86_SEL_TYPE_EO_CONF_ACC (4 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
2385	/** Conforming execute and write selector type. */
2386	#define X86_SEL_TYPE_ER_CONF (6 \| X86_SEL_TYPE_CODE)
2387	/** Accessed Conforming execute and write selector type. */
2388	#define X86_SEL_TYPE_ER_CONF_ACC (6 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
2389	/** @} */
2390
2391
2392	/** @name System Selector Types.
2393	* @{ */
2394	/** Undefined system selector type. */
2395	#define X86_SEL_TYPE_SYS_UNDEFINED 0
2396	/** 286 TSS selector. */
2397	#define X86_SEL_TYPE_SYS_286_TSS_AVAIL 1
2398	/** LDT selector. */
2399	#define X86_SEL_TYPE_SYS_LDT 2
2400	/** 286 TSS selector - Busy. */
2401	#define X86_SEL_TYPE_SYS_286_TSS_BUSY 3
2402	/** 286 Callgate selector. */
2403	#define X86_SEL_TYPE_SYS_286_CALL_GATE 4
2404	/** Taskgate selector. */
2405	#define X86_SEL_TYPE_SYS_TASK_GATE 5
2406	/** 286 Interrupt gate selector. */
2407	#define X86_SEL_TYPE_SYS_286_INT_GATE 6
2408	/** 286 Trapgate selector. */
2409	#define X86_SEL_TYPE_SYS_286_TRAP_GATE 7
2410	/** Undefined system selector. */
2411	#define X86_SEL_TYPE_SYS_UNDEFINED2 8
2412	/** 386 TSS selector. */
2413	#define X86_SEL_TYPE_SYS_386_TSS_AVAIL 9
2414	/** Undefined system selector. */
2415	#define X86_SEL_TYPE_SYS_UNDEFINED3 0xA
2416	/** 386 TSS selector - Busy. */
2417	#define X86_SEL_TYPE_SYS_386_TSS_BUSY 0xB
2418	/** 386 Callgate selector. */
2419	#define X86_SEL_TYPE_SYS_386_CALL_GATE 0xC
2420	/** Undefined system selector. */
2421	#define X86_SEL_TYPE_SYS_UNDEFINED4 0xD
2422	/** 386 Interruptgate selector. */
2423	#define X86_SEL_TYPE_SYS_386_INT_GATE 0xE
2424	/** 386 Trapgate selector. */
2425	#define X86_SEL_TYPE_SYS_386_TRAP_GATE 0xF
2426	/** @} */
2427
2428	/** @name AMD64 System Selector Types.
2429	* @{ */
2430	#define AMD64_SEL_TYPE_SYS_LDT 2
2431	/** 286 TSS selector - Busy. */
2432	#define AMD64_SEL_TYPE_SYS_TSS_AVAIL 9
2433	/** 386 TSS selector - Busy. */
2434	#define AMD64_SEL_TYPE_SYS_TSS_BUSY 0xB
2435	/** 386 Callgate selector. */
2436	#define AMD64_SEL_TYPE_SYS_CALL_GATE 0xC
2437	/** 386 Interruptgate selector. */
2438	#define AMD64_SEL_TYPE_SYS_INT_GATE 0xE
2439	/** 386 Trapgate selector. */
2440	#define AMD64_SEL_TYPE_SYS_TRAP_GATE 0xF
2441	/** @} */
2442
2443	/** @} */
2444
2445
2446	/** @name Descriptor Table Entry Flag Masks.
2447	* These are for the 2nd 32-bit word of a descriptor.
2448	* @{ */
2449	/** Bits 8-11 - TYPE - Descriptor type mask. */
2450	#define X86_DESC_TYPE_MASK (RT_BIT(8) \| RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
2451	/** Bit 12 - S - System (=0) or Code/Data (=1). */
2452	#define X86_DESC_S RT_BIT(12)
2453	/** Bits 13-14 - DPL - Descriptor Privilege Level. */
2454	#define X86_DESC_DPL (RT_BIT(13) \| RT_BIT(14))
2455	/** Bit 15 - P - Present. */
2456	#define X86_DESC_P RT_BIT(15)
2457	/** Bit 20 - AVL - Available for system software. */
2458	#define X86_DESC_AVL RT_BIT(20)
2459	/** Bit 22 - DB - Default operation size. 0 = 16 bit, 1 = 32 bit. */
2460	#define X86_DESC_DB RT_BIT(22)
2461	/** Bit 23 - G - Granularity of the limit. If set 4KB granularity is
2462	* used, if clear byte. */
2463	#define X86_DESC_G RT_BIT(23)
2464	/** @} */
2465
2466	/** @} */
2467
2468	/** @name Task segment.
2469	* @{
2470	*/
2471	#pragma pack(1)
2472	typedef struct X86TSS32
2473	{
2474	/** Back link to previous task. (static) */
2475	RTSEL selPrev;
2476	uint16_t padding1;
2477	/** Ring-0 stack pointer. (static) */
2478	uint32_t esp0;
2479	/** Ring-0 stack segment. (static) */
2480	RTSEL ss0;
2481	uint16_t padding_ss0;
2482	/** Ring-1 stack pointer. (static) */
2483	uint32_t esp1;
2484	/** Ring-1 stack segment. (static) */
2485	RTSEL ss1;
2486	uint16_t padding_ss1;
2487	/** Ring-2 stack pointer. (static) */
2488	uint32_t esp2;
2489	/** Ring-2 stack segment. (static) */
2490	RTSEL ss2;
2491	uint16_t padding_ss2;
2492	/** Page directory for the task. (static) */
2493	uint32_t cr3;
2494	/** EIP before task switch. */
2495	uint32_t eip;
2496	/** EFLAGS before task switch. */
2497	uint32_t eflags;
2498	/** EAX before task switch. */
2499	uint32_t eax;
2500	/** ECX before task switch. */
2501	uint32_t ecx;
2502	/** EDX before task switch. */
2503	uint32_t edx;
2504	/** EBX before task switch. */
2505	uint32_t ebx;
2506	/** ESP before task switch. */
2507	uint32_t esp;
2508	/** EBP before task switch. */
2509	uint32_t ebp;
2510	/** ESI before task switch. */
2511	uint32_t esi;
2512	/** EDI before task switch. */
2513	uint32_t edi;
2514	/** ES before task switch. */
2515	RTSEL es;
2516	uint16_t padding_es;
2517	/** CS before task switch. */
2518	RTSEL cs;
2519	uint16_t padding_cs;
2520	/** SS before task switch. */
2521	RTSEL ss;
2522	uint16_t padding_ss;
2523	/** DS before task switch. */
2524	RTSEL ds;
2525	uint16_t padding_ds;
2526	/** FS before task switch. */
2527	RTSEL fs;
2528	uint16_t padding_fs;
2529	/** GS before task switch. */
2530	RTSEL gs;
2531	uint16_t padding_gs;
2532	/** LDTR before task switch. */
2533	RTSEL selLdt;
2534	uint16_t padding_ldt;
2535	/** Debug trap flag */
2536	uint16_t fDebugTrap;
2537	/** Offset relative to the TSS of the start of the I/O Bitmap
2538	* and the end of the interrupt redirection bitmap. */
2539	uint16_t offIoBitmap;
2540	/** 32 bytes for the virtual interrupt redirection bitmap. (VME) */
2541	uint8_t IntRedirBitmap[32];
2542	} X86TSS32;
2543	#pragma pack()
2544	/** Pointer to task segment. */
2545	typedef X86TSS32 *PX86TSS32;
2546	/** Pointer to const task segment. */
2547	typedef const X86TSS32 *PCX86TSS32;
2548	/** @} */
2549
2550
2551	/** @name 64 bits Task segment.
2552	* @{
2553	*/
2554	#pragma pack(1)
2555	typedef struct X86TSS64
2556	{
2557	/** Reserved. */
2558	uint32_t u32Reserved;
2559	/** Ring-0 stack pointer. (static) */
2560	uint64_t rsp0;
2561	/** Ring-1 stack pointer. (static) */
2562	uint64_t rsp1;
2563	/** Ring-2 stack pointer. (static) */
2564	uint64_t rsp2;
2565	/** Reserved. */
2566	uint32_t u32Reserved2[2];
2567	/* IST */
2568	uint64_t ist1;
2569	uint64_t ist2;
2570	uint64_t ist3;
2571	uint64_t ist4;
2572	uint64_t ist5;
2573	uint64_t ist6;
2574	uint64_t ist7;
2575	/* Reserved. */
2576	uint16_t u16Reserved[5];
2577	/** Offset relative to the TSS of the start of the I/O Bitmap
2578	* and the end of the interrupt redirection bitmap. */
2579	uint16_t offIoBitmap;
2580	/** 32 bytes for the virtual interrupt redirection bitmap. (VME) */
2581	uint8_t IntRedirBitmap[32];
2582	} X86TSS64;
2583	#pragma pack()
2584	/** Pointer to task segment. */
2585	typedef X86TSS64 *PX86TSS64;
2586	/** Pointer to const task segment. */
2587	typedef const X86TSS64 *PCX86TSS64;
2588	AssertCompileSize(X86TSS64, 136);
2589
2590	/** @} */
2591
2592
2593	/** @name Selectors.
2594	* @{
2595	*/
2596
2597	/**
2598	* The shift used to convert a selector from and to index an index (C).
2599	*/
2600	#define X86_SEL_SHIFT 3
2601
2602	/**
2603	* The mask used to mask off the table indicator and CPL of an selector.
2604	*/
2605	#define X86_SEL_MASK 0xfff8
2606
2607	/**
2608	* The bit indicating that a selector is in the LDT and not in the GDT.
2609	*/
2610	#define X86_SEL_LDT 0x0004
2611	/**
2612	* The bit mask for getting the RPL of a selector.
2613	*/
2614	#define X86_SEL_RPL 0x0003
2615
2616	/** @} */
2617
2618
2619	/**
2620	* x86 Exceptions/Faults/Traps.
2621	*/
2622	typedef enum X86XCPT
2623	{
2624	/** \#DE - Divide error. */
2625	X86_XCPT_DE = 0x00,
2626	/** \#DB - Debug event (single step, DRx, ..) */
2627	X86_XCPT_DB = 0x01,
2628	/** NMI - Non-Maskable Interrupt */
2629	X86_XCPT_NMI = 0x02,
2630	/** \#BP - Breakpoint (INT3). */
2631	X86_XCPT_BP = 0x03,
2632	/** \#OF - Overflow (INTO). */
2633	X86_XCPT_OF = 0x04,
2634	/** \#BR - Bound range exceeded (BOUND). */
2635	X86_XCPT_BR = 0x05,
2636	/** \#UD - Undefined opcode. */
2637	X86_XCPT_UD = 0x06,
2638	/** \#NM - Device not available (math coprocessor device). */
2639	X86_XCPT_NM = 0x07,
2640	/** \#DF - Double fault. */
2641	X86_XCPT_DF = 0x08,
2642	/** ??? - Coprocessor segment overrun (obsolete). */
2643	X86_XCPT_CO_SEG_OVERRUN = 0x09,
2644	/** \#TS - Taskswitch (TSS). */
2645	X86_XCPT_TS = 0x0a,
2646	/** \#NP - Segment no present. */
2647	X86_XCPT_NP = 0x0b,
2648	/** \#SS - Stack segment fault. */
2649	X86_XCPT_SS = 0x0c,
2650	/** \#GP - General protection fault. */
2651	X86_XCPT_GP = 0x0d,
2652	/** \#PF - Page fault. */
2653	X86_XCPT_PF = 0x0e,
2654	/* 0x0f is reserved. */
2655	/** \#MF - Math fault (FPU). */
2656	X86_XCPT_MF = 0x10,
2657	/** \#AC - Alignment check. */
2658	X86_XCPT_AC = 0x11,
2659	/** \#MC - Machine check. */
2660	X86_XCPT_MC = 0x12,
2661	/** \#XF - SIMD Floating-Pointer Exception. */
2662	X86_XCPT_XF = 0x13
2663	} X86XCPT;
2664	/** Pointer to a x86 exception code. */
2665	typedef X86XCPT *PX86XCPT;
2666	/** Pointer to a const x86 exception code. */
2667	typedef const X86XCPT *PCX86XCPT;
2668
2669
2670	/** @name Trap Error Codes
2671	* @{
2672	*/
2673	/** External indicator. */
2674	#define X86_TRAP_ERR_EXTERNAL 1
2675	/** IDT indicator. */
2676	#define X86_TRAP_ERR_IDT 2
2677	/** Descriptor table indicator - If set LDT, if clear GDT. */
2678	#define X86_TRAP_ERR_TI 4
2679	/** Mask for getting the selector. */
2680	#define X86_TRAP_ERR_SEL_MASK 0xfff8
2681	/** Shift for getting the selector table index (C type index). */
2682	#define X86_TRAP_ERR_SEL_SHIFT 3
2683	/** @} */
2684
2685
2686	/** @name \#PF Trap Error Codes
2687	* @{
2688	*/
2689	/** Bit 0 - P - Not present (clear) or page level protection (set) fault. */
2690	#define X86_TRAP_PF_P RT_BIT(0)
2691	/** Bit 1 - R/W - Read (clear) or write (set) access. */
2692	#define X86_TRAP_PF_RW RT_BIT(1)
2693	/** Bit 2 - U/S - CPU executing in user mode (set) or supervisor mode (clear). */
2694	#define X86_TRAP_PF_US RT_BIT(2)
2695	/** Bit 3 - RSVD- Reserved bit violation (set), i.e. reserved bit was set to 1. */
2696	#define X86_TRAP_PF_RSVD RT_BIT(3)
2697	/** Bit 4 - I/D - Instruction fetch (set) / Data access (clear) - PAE + NXE. */
2698	#define X86_TRAP_PF_ID RT_BIT(4)
2699	/** @} */
2700
2701	#pragma pack(1)
2702	/**
2703	* 32-bit IDTR/GDTR.
2704	*/
2705	typedef struct X86XDTR32
2706	{
2707	/** Size of the descriptor table. */
2708	uint16_t cb;
2709	/** Address of the descriptor table. */
2710	uint32_t uAddr;
2711	} X86XDTR32, *PX86XDTR32;
2712	#pragma pack()
2713
2714	#pragma pack(1)
2715	/**
2716	* 64-bit IDTR/GDTR.
2717	*/
2718	typedef struct X86XDTR64
2719	{
2720	/** Size of the descriptor table. */
2721	uint16_t cb;
2722	/** Address of the descriptor table. */
2723	uint64_t uAddr;
2724	} X86XDTR64, *PX86XDTR64;
2725	#pragma pack()
2726
2727	/** @} */
2728
2729	#endif
2730

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source: vbox/trunk/include/VBox/x86.h@ 27319

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