x86.h@ 4011

Last change on this file since 4011 was 3942, checked in by vboxsync, 17 years ago
fixed detecting the CPU vendor (in DevAPIC) by introducing symbolic constants
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 75.0 KB

Line
1	/** @file
2	* X86 (and AMD64) Structures and Definitions.
3	*/
4
5	/*
6	* Copyright (C) 2006-2007 innotek GmbH
7	*
8	* This file is part of VirtualBox Open Source Edition (OSE), as
9	* available from http://www.virtualbox.org. This file is free software;
10	* you can redistribute it and/or modify it under the terms of the GNU
11	* General Public License as published by the Free Software Foundation,
12	* in version 2 as it comes in the "COPYING" file of the VirtualBox OSE
13	* distribution. VirtualBox OSE is distributed in the hope that it will
14	* be useful, but WITHOUT ANY WARRANTY of any kind.
15	*
16	* If you received this file as part of a commercial VirtualBox
17	* distribution, then only the terms of your commercial VirtualBox
18	* license agreement apply instead of the previous paragraph.
19	*/
20
21	/*
22	* x86.mac is generated from this file using:
23	* sed -e '/__VBox_x86_h__/d' -e '/#define/!d' -e 's/#define/%define/' include/VBox/x86.h
24	*/
25
26	#ifndef ___VBox_x86_h
27	#define ___VBox_x86_h
28
29	#include <VBox/types.h>
30
31	/* Workaround for Solaris sys/regset.h defining CS, DS */
32	#if defined(RT_OS_SOLARIS)
33	# undef CS
34	# undef DS
35	#endif
36
37	/** @defgroup grp_x86 x86 Types and Definitions
38	* @{
39	*/
40
41	/**
42	* EFLAGS Bits.
43	*/
44	typedef struct X86EFLAGSBITS
45	{
46	/** Bit 0 - CF - Carry flag - Status flag. */
47	unsigned u1CF : 1;
48	/** Bit 1 - 1 - Reserved flag. */
49	unsigned u1Reserved0 : 1;
50	/** Bit 2 - PF - Parity flag - Status flag. */
51	unsigned u1PF : 1;
52	/** Bit 3 - 0 - Reserved flag. */
53	unsigned u1Reserved1 : 1;
54	/** Bit 4 - AF - Auxiliary carry flag - Status flag. */
55	unsigned u1AF : 1;
56	/** Bit 5 - 0 - Reserved flag. */
57	unsigned u1Reserved2 : 1;
58	/** Bit 6 - ZF - Zero flag - Status flag. */
59	unsigned u1ZF : 1;
60	/** Bit 7 - SF - Signed flag - Status flag. */
61	unsigned u1SF : 1;
62	/** Bit 8 - TF - Trap flag - System flag. */
63	unsigned u1TF : 1;
64	/** Bit 9 - IF - Interrupt flag - System flag. */
65	unsigned u1IF : 1;
66	/** Bit 10 - DF - Direction flag - Control flag. */
67	unsigned u1DF : 1;
68	/** Bit 11 - OF - Overflow flag - Status flag. */
69	unsigned u1OF : 1;
70	/** Bit 12-13 - IOPL - I/O prvilege level flag - System flag. */
71	unsigned u2IOPL : 2;
72	/** Bit 14 - NT - Nested task flag - System flag. */
73	unsigned u1NT : 1;
74	/** Bit 15 - 0 - Reserved flag. */
75	unsigned u1Reserved3 : 1;
76	/** Bit 16 - RF - Resume flag - System flag. */
77	unsigned u1RF : 1;
78	/** Bit 17 - VM - Virtual 8086 mode - System flag. */
79	unsigned u1VM : 1;
80	/** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
81	unsigned u1AC : 1;
82	/** Bit 19 - VIF - Virtual interupt flag - System flag. */
83	unsigned u1VIF : 1;
84	/** Bit 20 - VIP - Virtual interupt pending flag - System flag. */
85	unsigned u1VIP : 1;
86	/** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
87	unsigned u1ID : 1;
88	/** Bit 22-31 - 0 - Reserved flag. */
89	unsigned u10Reserved4 : 10;
90	} X86EFLAGSBITS;
91	/** Pointer to EFLAGS bits. */
92	typedef X86EFLAGSBITS *PX86EFLAGSBITS;
93	/** Pointer to const EFLAGS bits. */
94	typedef const X86EFLAGSBITS *PCX86EFLAGSBITS;
95
96	/**
97	* EFLAGS.
98	*/
99	typedef union X86EFLAGS
100	{
101	/** The bitfield view. */
102	X86EFLAGSBITS Bits;
103	/** The 8-bit view. */
104	uint8_t au8[4];
105	/** The 16-bit view. */
106	uint16_t au16[2];
107	/** The 32-bit view. */
108	uint32_t au32[1];
109	/** The 32-bit view. */
110	uint32_t u32;
111	} X86EFLAGS;
112	/** Pointer to EFLAGS. */
113	typedef X86EFLAGS *PX86EFLAGS;
114	/** Pointer to const EFLAGS. */
115	typedef const X86EFLAGS *PCX86EFLAGS;
116
117
118	/** @name EFLAGS
119	* @{
120	*/
121	/** Bit 0 - CF - Carry flag - Status flag. */
122	#define X86_EFL_CF BIT(0)
123	/** Bit 2 - PF - Parity flag - Status flag. */
124	#define X86_EFL_PF BIT(2)
125	/** Bit 4 - AF - Auxiliary carry flag - Status flag. */
126	#define X86_EFL_AF BIT(4)
127	/** Bit 6 - ZF - Zero flag - Status flag. */
128	#define X86_EFL_ZF BIT(6)
129	/** Bit 7 - SF - Signed flag - Status flag. */
130	#define X86_EFL_SF BIT(7)
131	/** Bit 8 - TF - Trap flag - System flag. */
132	#define X86_EFL_TF BIT(8)
133	/** Bit 9 - IF - Interrupt flag - System flag. */
134	#define X86_EFL_IF BIT(9)
135	/** Bit 10 - DF - Direction flag - Control flag. */
136	#define X86_EFL_DF BIT(10)
137	/** Bit 11 - OF - Overflow flag - Status flag. */
138	#define X86_EFL_OF BIT(11)
139	/** Bit 12-13 - IOPL - I/O prvilege level flag - System flag. */
140	#define X86_EFL_IOPL (BIT(12) \| BIT(13))
141	/** Bit 14 - NT - Nested task flag - System flag. */
142	#define X86_EFL_NT BIT(14)
143	/** Bit 16 - RF - Resume flag - System flag. */
144	#define X86_EFL_RF BIT(16)
145	/** Bit 17 - VM - Virtual 8086 mode - System flag. */
146	#define X86_EFL_VM BIT(17)
147	/** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
148	#define X86_EFL_AC BIT(18)
149	/** Bit 19 - VIF - Virtual interupt flag - System flag. */
150	#define X86_EFL_VIF BIT(19)
151	/** Bit 20 - VIP - Virtual interupt pending flag - System flag. */
152	#define X86_EFL_VIP BIT(20)
153	/** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
154	#define X86_EFL_ID BIT(21)
155	/** IOPL shift. */
156	#define X86_EFL_IOPL_SHIFT 12
157	/** The the IOPL level from the flags. */
158	#define X86_EFL_GET_IOPL(efl) (((efl) >> X86_EFL_IOPL_SHIFT) & 3)
159	/** @} */
160
161
162	/** CPUID Feature information - ECX.
163	* CPUID query with EAX=1.
164	*/
165	typedef struct X86CPUIDFEATECX
166	{
167	/** Bit 0 - SSE3 - Supports SSE3 or not. */
168	unsigned u1SSE3 : 1;
169	/** Reserved. */
170	unsigned u2Reserved1 : 2;
171	/** Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
172	unsigned u1Monitor : 1;
173	/** Bit 4 - CPL-DS - CPL Qualified Debug Store. */
174	unsigned u1CPLDS : 1;
175	/** Bit 5 - VMX - Virtual Machine Technology. */
176	unsigned u1VMX : 1;
177	/** Reserved. */
178	unsigned u1Reserved2 : 1;
179	/** Bit 7 - EST - Enh. SpeedStep Tech. */
180	unsigned u1EST : 1;
181	/** Bit 8 - TM2 - Terminal Monitor 2. */
182	unsigned u1TM2 : 1;
183	/** Reserved. */
184	unsigned u1Reserved3 : 1;
185	/** Bit 10 - CNTX-ID - L1 Context ID. */
186	unsigned u1CNTXID : 1;
187	/** Reserved. */
188	unsigned u2Reserved4 : 2;
189	/** Bit 13 - CX16 - CMPXCHG16B. */
190	unsigned u1CX16 : 1;
191	/** Reserved. */
192	unsigned u18Reserved5 : 18;
193
194	} X86CPUIDFEATECX;
195	/** Pointer to CPUID Feature Information - ECX. */
196	typedef X86CPUIDFEATECX *PX86CPUIDFEATECX;
197	/** Pointer to const CPUID Feature Information - ECX. */
198	typedef const X86CPUIDFEATECX *PCX86CPUIDFEATECX;
199
200
201	/** CPUID Feature Information - EDX.
202	* CPUID query with EAX=1.
203	*/
204	typedef struct X86CPUIDFEATEDX
205	{
206	/** Bit 0 - FPU - x87 FPU on Chip. */
207	unsigned u1FPU : 1;
208	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
209	unsigned u1VME : 1;
210	/** Bit 2 - DE - Debugging extensions. */
211	unsigned u1DE : 1;
212	/** Bit 3 - PSE - Page Size Extension. */
213	unsigned u1PSE : 1;
214	/** Bit 4 - TSC - Tiem Stamp Counter. */
215	unsigned u1TSC : 1;
216	/** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
217	unsigned u1MSR : 1;
218	/** Bit 6 - PAE - Physical Address Extension. */
219	unsigned u1PAE : 1;
220	/** Bit 7 - MCE - Machine Check Exception. */
221	unsigned u1MCE : 1;
222	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
223	unsigned u1CX8 : 1;
224	/** Bit 9 - APIC - APIC On-Chick. */
225	unsigned u1APIC : 1;
226	/** Bit 10 - Reserved. */
227	unsigned u1Reserved1 : 1;
228	/** Bit 11 - SEP - SYSENTER and SYSEXIT. */
229	unsigned u1SEP : 1;
230	/** Bit 12 - MTRR - Memory Type Range Registers. */
231	unsigned u1MTRR : 1;
232	/** Bit 13 - PGE - PTE Global Bit. */
233	unsigned u1PGE : 1;
234	/** Bit 14 - MCA - Machine Check Architecture. */
235	unsigned u1MCA : 1;
236	/** Bit 15 - CMOV - Conditional Move Instructions. */
237	unsigned u1CMOV : 1;
238	/** Bit 16 - PAT - Page Attribute Table. */
239	unsigned u1PAT : 1;
240	/** Bit 17 - PSE-36 - 36-bit Page Size Extention. */
241	unsigned u1PSE36 : 1;
242	/** Bit 18 - PSN - Processor Serial Number. */
243	unsigned u1PSN : 1;
244	/** Bit 19 - CLFSH - CLFLUSH Instruction. */
245	unsigned u1CLFSH : 1;
246	/** Bit 20 - Reserved. */
247	unsigned u1Reserved2 : 1;
248	/** Bit 21 - DS - Debug Store. */
249	unsigned u1DS : 1;
250	/** Bit 22 - ACPI - Thermal Monitor and Software Controlled Clock Facilities. */
251	unsigned u1ACPI : 1;
252	/** Bit 23 - MMX - Intel MMX 'Technology'. */
253	unsigned u1MMX : 1;
254	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
255	unsigned u1FXSR : 1;
256	/** Bit 25 - SSE - SSE Support. */
257	unsigned u1SSE : 1;
258	/** Bit 26 - SSE2 - SSE2 Support. */
259	unsigned u1SSE2 : 1;
260	/** Bit 27 - SS - Self Snoop. */
261	unsigned u1SS : 1;
262	/** Bit 28 - HTT - Hyper-Threading Technology. */
263	unsigned u1HTT : 1;
264	/** Bit 29 - TM - Thermal Monitor. */
265	unsigned u1TM : 1;
266	/** Bit 30 - Reserved - . */
267	unsigned u1Reserved3 : 1;
268	/** Bit 31 - PBE - Pending Break Enabled. */
269	unsigned u1PBE : 1;
270	} X86CPUIDFEATEDX;
271	/** Pointer to CPUID Feature Information - EDX. */
272	typedef X86CPUIDFEATEDX *PX86CPUIDFEATEDX;
273	/** Pointer to const CPUID Feature Information - EDX. */
274	typedef const X86CPUIDFEATEDX *PCX86CPUIDFEATEDX;
275
276	/** @name CPUID Vendor information.
277	* CPUID query with EAX=0.
278	* @{
279	*/
280	#define X86_CPUID_VENDOR_INTEL_EBX 0x756e6547 /* Genu */
281	#define X86_CPUID_VENDOR_INTEL_ECX 0x6c65746e /* ntel */
282	#define X86_CPUID_VENDOR_INTEL_EDX 0x49656e69 /* ineI */
283
284	#define X86_CPUID_VENDOR_AMD_EBX 0x68747541 /* Auth */
285	#define X86_CPUID_VENDOR_AMD_ECX 0x444d4163 /* cAMD */
286	#define X86_CPUID_VENDOR_AMD_EDX 0x69746e65 /* enti */
287	/** @} */
288
289
290	/** @name CPUID Feature information.
291	* CPUID query with EAX=1.
292	* @{
293	*/
294	/** ECX Bit 0 - SSE3 - Supports SSE3 or not. */
295	#define X86_CPUID_FEATURE_ECX_SSE3 BIT(0)
296	/** ECX Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
297	#define X86_CPUID_FEATURE_ECX_MONITOR BIT(3)
298	/** ECX Bit 4 - CPL-DS - CPL Qualified Debug Store. */
299	#define X86_CPUID_FEATURE_ECX_CPLDS BIT(4)
300	/** ECX Bit 5 - VMX - Virtual Machine Technology. */
301	#define X86_CPUID_FEATURE_ECX_VMX BIT(5)
302	/** ECX Bit 7 - EST - Enh. SpeedStep Tech. */
303	#define X86_CPUID_FEATURE_ECX_EST BIT(7)
304	/** ECX Bit 8 - TM2 - Terminal Monitor 2. */
305	#define X86_CPUID_FEATURE_ECX_TM2 BIT(8)
306	/** ECX Bit 10 - CNTX-ID - L1 Context ID. */
307	#define X86_CPUID_FEATURE_ECX_CNTXID BIT(10)
308	/** ECX Bit 13 - CX16 - L1 Context ID. */
309	#define X86_CPUID_FEATURE_ECX_CX16 BIT(13)
310
311
312	/** Bit 0 - FPU - x87 FPU on Chip. */
313	#define X86_CPUID_FEATURE_EDX_FPU BIT(0)
314	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
315	#define X86_CPUID_FEATURE_EDX_VME BIT(1)
316	/** Bit 2 - DE - Debugging extensions. */
317	#define X86_CPUID_FEATURE_EDX_DE BIT(2)
318	/** Bit 3 - PSE - Page Size Extension. */
319	#define X86_CPUID_FEATURE_EDX_PSE BIT(3)
320	/** Bit 4 - TSC - Time Stamp Counter. */
321	#define X86_CPUID_FEATURE_EDX_TSC BIT(4)
322	/** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
323	#define X86_CPUID_FEATURE_EDX_MSR BIT(5)
324	/** Bit 6 - PAE - Physical Address Extension. */
325	#define X86_CPUID_FEATURE_EDX_PAE BIT(6)
326	/** Bit 7 - MCE - Machine Check Exception. */
327	#define X86_CPUID_FEATURE_EDX_MCE BIT(7)
328	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
329	#define X86_CPUID_FEATURE_EDX_CX8 BIT(8)
330	/** Bit 9 - APIC - APIC On-Chip. */
331	#define X86_CPUID_FEATURE_EDX_APIC BIT(9)
332	/** Bit 11 - SEP - SYSENTER and SYSEXIT. */
333	#define X86_CPUID_FEATURE_EDX_SEP BIT(11)
334	/** Bit 12 - MTRR - Memory Type Range Registers. */
335	#define X86_CPUID_FEATURE_EDX_MTRR BIT(12)
336	/** Bit 13 - PGE - PTE Global Bit. */
337	#define X86_CPUID_FEATURE_EDX_PGE BIT(13)
338	/** Bit 14 - MCA - Machine Check Architecture. */
339	#define X86_CPUID_FEATURE_EDX_MCA BIT(14)
340	/** Bit 15 - CMOV - Conditional Move Instructions. */
341	#define X86_CPUID_FEATURE_EDX_CMOV BIT(15)
342	/** Bit 16 - PAT - Page Attribute Table. */
343	#define X86_CPUID_FEATURE_EDX_PAT BIT(16)
344	/** Bit 17 - PSE-36 - 36-bit Page Size Extention. */
345	#define X86_CPUID_FEATURE_EDX_PSE36 BIT(17)
346	/** Bit 18 - PSN - Processor Serial Number. */
347	#define X86_CPUID_FEATURE_EDX_PSN BIT(18)
348	/** Bit 19 - CLFSH - CLFLUSH Instruction. */
349	#define X86_CPUID_FEATURE_EDX_CLFSH BIT(19)
350	/** Bit 21 - DS - Debug Store. */
351	#define X86_CPUID_FEATURE_EDX_DS BIT(21)
352	/** Bit 22 - ACPI - Termal Monitor and Software Controlled Clock Facilities. */
353	#define X86_CPUID_FEATURE_EDX_ACPI BIT(22)
354	/** Bit 23 - MMX - Intel MMX Technology. */
355	#define X86_CPUID_FEATURE_EDX_MMX BIT(23)
356	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
357	#define X86_CPUID_FEATURE_EDX_FXSR BIT(24)
358	/** Bit 25 - SSE - SSE Support. */
359	#define X86_CPUID_FEATURE_EDX_SSE BIT(25)
360	/** Bit 26 - SSE2 - SSE2 Support. */
361	#define X86_CPUID_FEATURE_EDX_SSE2 BIT(26)
362	/** Bit 27 - SS - Self Snoop. */
363	#define X86_CPUID_FEATURE_EDX_SS BIT(27)
364	/** Bit 28 - HTT - Hyper-Threading Technology. */
365	#define X86_CPUID_FEATURE_EDX_HTT BIT(28)
366	/** Bit 29 - TM - Therm. Monitor. */
367	#define X86_CPUID_FEATURE_EDX_TM BIT(29)
368	/** Bit 31 - PBE - Pending Break Enabled. */
369	#define X86_CPUID_FEATURE_EDX_PBE BIT(31)
370	/** @} */
371
372
373	/** @name CPUID AMD Feature information.
374	* CPUID query with EAX=0x80000001.
375	* @{
376	*/
377	/** Bit 0 - FPU - x87 FPU on Chip. */
378	#define X86_CPUID_AMD_FEATURE_EDX_FPU BIT(0)
379	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
380	#define X86_CPUID_AMD_FEATURE_EDX_VME BIT(1)
381	/** Bit 2 - DE - Debugging extensions. */
382	#define X86_CPUID_AMD_FEATURE_EDX_DE BIT(2)
383	/** Bit 3 - PSE - Page Size Extension. */
384	#define X86_CPUID_AMD_FEATURE_EDX_PSE BIT(3)
385	/** Bit 4 - TSC - Time Stamp Counter. */
386	#define X86_CPUID_AMD_FEATURE_EDX_TSC BIT(4)
387	/** Bit 5 - MSR - K86 Model Specific Registers RDMSR and WRMSR Instructions. */
388	#define X86_CPUID_AMD_FEATURE_EDX_MSR BIT(5)
389	/** Bit 6 - PAE - Physical Address Extension. */
390	#define X86_CPUID_AMD_FEATURE_EDX_PAE BIT(6)
391	/** Bit 7 - MCE - Machine Check Exception. */
392	#define X86_CPUID_AMD_FEATURE_EDX_MCE BIT(7)
393	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
394	#define X86_CPUID_AMD_FEATURE_EDX_CX8 BIT(8)
395	/** Bit 9 - APIC - APIC On-Chip. */
396	#define X86_CPUID_AMD_FEATURE_EDX_APIC BIT(9)
397	/** Bit 11 - SEP - AMD SYSCALL and SYSRET. */
398	#define X86_CPUID_AMD_FEATURE_EDX_SEP BIT(11)
399	/** Bit 12 - MTRR - Memory Type Range Registers. */
400	#define X86_CPUID_AMD_FEATURE_EDX_MTRR BIT(12)
401	/** Bit 13 - PGE - PTE Global Bit. */
402	#define X86_CPUID_AMD_FEATURE_EDX_PGE BIT(13)
403	/** Bit 14 - MCA - Machine Check Architecture. */
404	#define X86_CPUID_AMD_FEATURE_EDX_MCA BIT(14)
405	/** Bit 15 - CMOV - Conditional Move Instructions. */
406	#define X86_CPUID_AMD_FEATURE_EDX_CMOV BIT(15)
407	/** Bit 16 - PAT - Page Attribute Table. */
408	#define X86_CPUID_AMD_FEATURE_EDX_PAT BIT(16)
409	/** Bit 17 - PSE-36 - 36-bit Page Size Extention. */
410	#define X86_CPUID_AMD_FEATURE_EDX_PSE36 BIT(17)
411	/** Bit 20 - NX - AMD No-Execute Page Protection. */
412	#define X86_CPUID_AMD_FEATURE_EDX_NX BIT(20)
413	/** Bit 22 - AXMMX - AMD Extensions to MMX Instructions. */
414	#define X86_CPUID_AMD_FEATURE_EDX_AXMMX BIT(22)
415	/** Bit 23 - MMX - Intel MMX Technology. */
416	#define X86_CPUID_AMD_FEATURE_EDX_MMX BIT(23)
417	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
418	#define X86_CPUID_AMD_FEATURE_EDX_FXSR BIT(24)
419	/** Bit 25 - ???? - AMD fast FXSAVE and FXRSTOR Instructions. */
420	#define X86_CPUID_AMD_FEATURE_EDX_FFXSR BIT(25)
421	/** Bit 29 - ???? - AMD Long Mode. */
422	#define X86_CPUID_AMD_FEATURE_EDX_LONG_MODE BIT(29)
423	/** Bit 30 - ???? - AMD Extensions to 3DNow. */
424	#define X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX BIT(30)
425	/** Bit 31 - ???? - AMD 3DNow. */
426	#define X86_CPUID_AMD_FEATURE_EDX_3DNOW BIT(31)
427
428	/** Bit 1 - LAHF/SAHF - ???. */
429	/define X86_CPUID_AMD_FEATURE_ECX_TODO BIT(0)/
430	/** Bit 1 - CMPL - ???. */
431	#define X86_CPUID_AMD_FEATURE_ECX_CMPL BIT(1)
432	/** Bit 2 - SVM - AMD VM extensions. */
433	#define X86_CPUID_AMD_FEATURE_ECX_SVM BIT(2)
434	/** Bit 4 - CR8L - ???. */
435	#define X86_CPUID_AMD_FEATURE_ECX_CR8L BIT(4)
436
437	/** @} */
438
439
440	/** @name CR0
441	* @{ */
442	/** Bit 0 - PE - Protection Enabled */
443	#define X86_CR0_PE BIT(0)
444	#define X86_CR0_PROTECTION_ENABLE BIT(0)
445	/** Bit 1 - MP - Monitor Coprocessor */
446	#define X86_CR0_MP BIT(1)
447	#define X86_CR0_MONITOR_COPROCESSOR BIT(1)
448	/** Bit 2 - EM - Emulation. */
449	#define X86_CR0_EM BIT(2)
450	#define X86_CR0_EMULATE_FPU BIT(2)
451	/** Bit 3 - TS - Task Switch. */
452	#define X86_CR0_TS BIT(3)
453	#define X86_CR0_TASK_SWITCH BIT(3)
454	/** Bit 4 - ET - Extension flag. ('hardcoded' to 1) */
455	#define X86_CR0_ET BIT(4)
456	#define X86_CR0_EXTENSION_TYPE BIT(4)
457	/** Bit 5 - NE - Numeric error. */
458	#define X86_CR0_NE BIT(5)
459	#define X86_CR0_NUMERIC_ERROR BIT(5)
460	/** Bit 16 - WP - Write Protect. */
461	#define X86_CR0_WP BIT(16)
462	#define X86_CR0_WRITE_PROTECT BIT(16)
463	/** Bit 18 - AM - Alignment Mask. */
464	#define X86_CR0_AM BIT(18)
465	#define X86_CR0_ALIGMENT_MASK BIT(18)
466	/** Bit 29 - NW - Not Write-though. */
467	#define X86_CR0_NW BIT(29)
468	#define X86_CR0_NOT_WRITE_THROUGH BIT(29)
469	/** Bit 30 - WP - Cache Disable. */
470	#define X86_CR0_CD BIT(30)
471	#define X86_CR0_CACHE_DISABLE BIT(30)
472	/** Bit 31 - PG - Paging. */
473	#define X86_CR0_PG BIT(31)
474	#define X86_CR0_PAGING BIT(31)
475	/** @} */
476
477
478	/** @name CR3
479	* @{ */
480	/** Bit 3 - PWT - Page-level Writes Transparent. */
481	#define X86_CR3_PWT BIT(3)
482	/** Bit 4 - PCD - Page-level Cache Disable. */
483	#define X86_CR3_PCD BIT(4)
484	/** Bits 12-31 - - Page directory page number. */
485	#define X86_CR3_PAGE_MASK (0xfffff000)
486	/** Bits 5-31 - - PAE Page directory page number. */
487	#define X86_CR3_PAE_PAGE_MASK (0xffffffe0)
488	/** @} */
489
490
491	/** @name CR4
492	* @{ */
493	/** Bit 0 - VME - Virtual-8086 Mode Extensions. */
494	#define X86_CR4_VME BIT(0)
495	/** Bit 1 - PVI - Protected-Mode Virtual Interrupts. */
496	#define X86_CR4_PVI BIT(1)
497	/** Bit 2 - TSD - Time Stamp Disable. */
498	#define X86_CR4_TSD BIT(2)
499	/** Bit 3 - DE - Debugging Extensions. */
500	#define X86_CR4_DE BIT(3)
501	/** Bit 4 - PSE - Page Size Extension. */
502	#define X86_CR4_PSE BIT(4)
503	/** Bit 5 - PAE - Physical Address Extension. */
504	#define X86_CR4_PAE BIT(5)
505	/** Bit 6 - MCE - Machine-Check Enable. */
506	#define X86_CR4_MCE BIT(6)
507	/** Bit 7 - PGE - Page Global Enable. */
508	#define X86_CR4_PGE BIT(7)
509	/** Bit 8 - PCE - Performance-Monitoring Counter Enable. */
510	#define X86_CR4_PCE BIT(8)
511	/** Bit 9 - OSFSXR - Operating System Support for FXSAVE and FXRSTORE instruction. */
512	#define X86_CR4_OSFSXR BIT(9)
513	/** Bit 10 - OSXMMEEXCPT - Operating System Support for Unmasked SIMD Floating-Point Exceptions. */
514	#define X86_CR4_OSXMMEEXCPT BIT(10)
515	/** Bit 13 - VMXE - VMX mode is enabled. */
516	#define X86_CR4_VMXE BIT(13)
517	/** @} */
518
519
520	/** @name DR6
521	* @{ */
522	/** Bit 0 - B0 - Breakpoint 0 condition detected. */
523	#define X86_DR6_B0 BIT(0)
524	/** Bit 1 - B1 - Breakpoint 1 condition detected. */
525	#define X86_DR6_B1 BIT(1)
526	/** Bit 2 - B2 - Breakpoint 2 condition detected. */
527	#define X86_DR6_B2 BIT(2)
528	/** Bit 3 - B3 - Breakpoint 3 condition detected. */
529	#define X86_DR6_B3 BIT(3)
530	/** Bit 13 - BD - Debug register access detected. Corresponds to the X86_DR7_GD bit. */
531	#define X86_DR6_BD BIT(13)
532	/** Bit 14 - BS - Single step */
533	#define X86_DR6_BS BIT(14)
534	/** Bit 15 - BT - Task switch. (TSS T bit.) */
535	#define X86_DR6_BT BIT(15)
536	/** @} */
537
538
539	/** @name DR7
540	* @{ */
541	/** Bit 0 - L0 - Local breakpoint enable. Cleared on task switch. */
542	#define X86_DR7_L0 BIT(0)
543	/** Bit 1 - G0 - Global breakpoint enable. Not cleared on task switch. */
544	#define X86_DR7_G0 BIT(1)
545	/** Bit 2 - L1 - Local breakpoint enable. Cleared on task switch. */
546	#define X86_DR7_L1 BIT(2)
547	/** Bit 3 - G1 - Global breakpoint enable. Not cleared on task switch. */
548	#define X86_DR7_G1 BIT(3)
549	/** Bit 4 - L2 - Local breakpoint enable. Cleared on task switch. */
550	#define X86_DR7_L2 BIT(4)
551	/** Bit 5 - G2 - Global breakpoint enable. Not cleared on task switch. */
552	#define X86_DR7_G2 BIT(5)
553	/** Bit 6 - L3 - Local breakpoint enable. Cleared on task switch. */
554	#define X86_DR7_L3 BIT(6)
555	/** Bit 7 - G3 - Global breakpoint enable. Not cleared on task switch. */
556	#define X86_DR7_G3 BIT(7)
557	/** Bit 8 - LE - Local breakpoint exact. (Not supported (read ignored) by P6 and later.) */
558	#define X86_DR7_LE BIT(8)
559	/** Bit 9 - GE - Local breakpoint exact. (Not supported (read ignored) by P6 and later.) */
560	#define X86_DR7_GE BIT(9)
561
562	/** Bit 13 - GD - General detect enable. Enables emulators to get exceptions when
563	* any DR register is accessed. */
564	#define X86_DR7_GD BIT(13)
565	/** Bit 16 & 17 - R/W0 - Read write field 0. Values X86_DR7_RW_. /
566	#define X86_DR7_RW0_MASK (3 << 16)
567	/** Bit 18 & 19 - LEN0 - Length field 0. Values X86_DR7_LEN_. /
568	#define X86_DR7_LEN0_MASK (3 << 18)
569	/** Bit 20 & 21 - R/W1 - Read write field 0. Values X86_DR7_RW_. /
570	#define X86_DR7_RW1_MASK (3 << 20)
571	/** Bit 22 & 23 - LEN1 - Length field 0. Values X86_DR7_LEN_. /
572	#define X86_DR7_LEN1_MASK (3 << 22)
573	/** Bit 24 & 25 - R/W2 - Read write field 0. Values X86_DR7_RW_. /
574	#define X86_DR7_RW2_MASK (3 << 24)
575	/** Bit 26 & 27 - LEN2 - Length field 0. Values X86_DR7_LEN_. /
576	#define X86_DR7_LEN2_MASK (3 << 26)
577	/** Bit 28 & 29 - R/W3 - Read write field 0. Values X86_DR7_RW_. /
578	#define X86_DR7_RW3_MASK (3 << 28)
579	/** Bit 30 & 31 - LEN3 - Length field 0. Values X86_DR7_LEN_. /
580	#define X86_DR7_LEN3_MASK (3 << 30)
581
582	/** Bits which must be 1s. */
583	#define X86_DR7_MB1_MASK (BIT(10))
584
585	/** Calcs the L bit of Nth breakpoint.
586	* @param iBp The breakpoint number [0..3].
587	*/
588	#define X86_DR7_L(iBp) ( 1 << (iBp * 2) )
589
590	/** Calcs the G bit of Nth breakpoint.
591	* @param iBp The breakpoint number [0..3].
592	*/
593	#define X86_DR7_G(iBp) ( 1 << (iBp * 2 + 1) )
594
595	/** @name Read/Write values.
596	* @{ */
597	/** Break on instruction fetch only. */
598	#define X86_DR7_RW_EO 0
599	/** Break on write only. */
600	#define X86_DR7_RW_WO 1
601	/** Break on I/O read/write. This is only defined if CR4.DE is set. */
602	#define X86_DR7_RW_IO 2
603	/** Break on read or write (but not instruction fetches). */
604	#define X86_DR7_RW_RW 3
605	/** @} */
606
607	/** Shifts a X86_DR7_RW_* value to its right place.
608	* @param iBp The breakpoint number [0..3].
609	* @param fRw One of the X86_DR7_RW_* value.
610	*/
611	#define X86_DR7_RW(iBp, fRw) ( (fRw) << ((iBp) * 4 + 16) )
612
613	/** @name Length values.
614	* @{ */
615	#define X86_DR7_LEN_BYTE 0
616	#define X86_DR7_LEN_WORD 1
617	#define X86_DR7_LEN_QWORD 2 /*< AMD64 long mode only. /
618	#define X86_DR7_LEN_DWORD 3
619	/** @} */
620
621	/** Shifts a X86_DR7_LEN_* value to its right place.
622	* @param iBp The breakpoint number [0..3].
623	* @param cb One of the X86_DR7_LEN_* values.
624	*/
625	#define X86_DR7_LEN(iBp, cb) ( (cb) << ((iBp) * 4 + 18) )
626
627	/** Mask used to check if any breakpoints are enabled. */
628	#define X86_DR7_ENABLED_MASK (BIT(0) \| BIT(1) \| BIT(2) \| BIT(3) \| BIT(4) \| BIT(6) \| BIT(7))
629
630	/** @} */
631
632
633	/** @name Machine Specific Registers
634	* @{
635	*/
636	/** CPU Feature control. */
637	#define MSR_IA32_FEATURE_CONTROL 0x3A
638	#define MSR_IA32_FEATURE_CONTROL_LOCK BIT(0)
639	#define MSR_IA32_FEATURE_CONTROL_VMXON BIT(2)
640
641
642	#ifndef MSR_IA32_SYSENTER_CS /* qemu cpu.h klugde */
643	/** SYSENTER_CS - the R0 CS, indirectly giving R0 SS, R3 CS and R3 DS.
644	* R0 SS == CS + 8
645	* R3 CS == CS + 16
646	* R3 SS == CS + 24
647	*/
648	#define MSR_IA32_SYSENTER_CS 0x174
649	/** SYSENTER_ESP - the R0 ESP. */
650	#define MSR_IA32_SYSENTER_ESP 0x175
651	/** SYSENTER_EIP - the R0 EIP. */
652	#define MSR_IA32_SYSENTER_EIP 0x176
653	#endif
654
655	/** Basic VMX information. */
656	#define MSR_IA32_VMX_BASIC_INFO 0x480
657	/** Allowed settings for pin-based VM execution controls */
658	#define MSR_IA32_VMX_PINBASED_CTLS 0x481
659	/** Allowed settings for proc-based VM execution controls */
660	#define MSR_IA32_VMX_PROCBASED_CTLS 0x482
661	/** Allowed settings for the VMX exit controls. */
662	#define MSR_IA32_VMX_EXIT_CTLS 0x483
663	/** Allowed settings for the VMX entry controls. */
664	#define MSR_IA32_VMX_ENTRY_CTLS 0x484
665	/** Misc VMX info. */
666	#define MSR_IA32_VMX_MISC 0x485
667	/** Fixed cleared bits in CR0. */
668	#define MSR_IA32_VMX_CR0_FIXED0 0x486
669	/** Fixed set bits in CR0. */
670	#define MSR_IA32_VMX_CR0_FIXED1 0x487
671	/** Fixed cleared bits in CR4. */
672	#define MSR_IA32_VMX_CR4_FIXED0 0x488
673	/** Fixed set bits in CR4. */
674	#define MSR_IA32_VMX_CR4_FIXED1 0x489
675	/** Information for enumerating fields in the VMCS. */
676	#define MSR_IA32_VMX_VMCS_ENUM 0x48A
677
678
679	/** K6 EFER - Extended Feature Enable Register. */
680	#define MSR_K6_EFER 0xc0000080
681	/** @todo document EFER */
682	/** Bit 0 - SCE - System call extensions (SYSCALL / SYSRET). (R/W) */
683	#define MSR_K6_EFER_SCE BIT(0)
684	/** Bit 8 - LME - Long mode enabled. (R/W) */
685	#define MSR_K6_EFER_LME BIT(8)
686	/** Bit 10 - LMA - Long mode active. (R) */
687	#define MSR_K6_EFER_LMA BIT(10)
688	/** Bit 11 - NXE - No-Execute Page Protection Enabled. (R/W) */
689	#define MSR_K6_EFER_NXE BIT(11)
690	/** Bit 12 - SVME - Secure VM Extension Enabled. (R/W) */
691	#define MSR_K6_EFER_SVME BIT(12)
692	/** Bit 13 - LMSLE - Long Mode Segment Limit Enable. (R/W?) */
693	#define MSR_K6_EFER_LMSLE BIT(13)
694	/** Bit 14 - FFXSR - Fast FXSAVE / FXRSTOR (skip XMM). (R/W) /
695	#define MSR_K6_EFER_FFXSR BIT(14)
696	/** K6 STAR - SYSCALL/RET targets. */
697	#define MSR_K6_STAR 0xc0000081
698	/** Shift value for getting the SYSRET CS and SS value. */
699	#define MSR_K6_STAR_SYSRET_CS_SS_SHIFT 48
700	/** Shift value for getting the SYSCALL CS and SS value. */
701	#define MSR_K6_STAR_SYSCALL_CS_SS_SHIFT 32
702	/** Selector mask for use after shifting. */
703	#define MSR_K6_STAR_SEL_MASK 0xffff
704	/** The mask which give the SYSCALL EIP. */
705	#define MSR_K6_STAR_SYSCALL_EIP_MASK 0xffffffff
706	/** K6 WHCR - Write Handling Control Register. */
707	#define MSR_K6_WHCR 0xc0000082
708	/** K6 UWCCR - UC/WC Cacheability Control Register. */
709	#define MSR_K6_UWCCR 0xc0000085
710	/** K6 PSOR - Processor State Observability Register. */
711	#define MSR_K6_PSOR 0xc0000087
712	/** K6 PFIR - Page Flush/Invalidate Register. */
713	#define MSR_K6_PFIR 0xc0000088
714
715	#define MSR_K7_EVNTSEL0 0xc0010000
716	#define MSR_K7_EVNTSEL1 0xc0010001
717	#define MSR_K7_EVNTSEL2 0xc0010002
718	#define MSR_K7_EVNTSEL3 0xc0010003
719	#define MSR_K7_PERFCTR0 0xc0010004
720	#define MSR_K7_PERFCTR1 0xc0010005
721	#define MSR_K7_PERFCTR2 0xc0010006
722	#define MSR_K7_PERFCTR3 0xc0010007
723
724	/** K8 LSTAR - Long mode SYSCALL target (RIP). */
725	#define MSR_K8_LSTAR 0xc0000082
726	/** K8 CSTAR - Compatibility mode SYSCALL target (RIP). */
727	#define MSR_K8_CSTAR 0xc0000083
728	/** K8 SF_MASK - SYSCALL flag mask. (aka SFMASK) */
729	#define MSR_K8_SF_MASK 0xc0000084
730	/** K8 FS.base - The 64-bit base FS register. */
731	#define MSR_K8_FS_BASE 0xc0000100
732	/** K8 GS.base - The 64-bit base GS register. */
733	#define MSR_K8_GS_BASE 0xc0000101
734	/** K8 KernelGSbase - Used with SWAPGS. */
735	#define MSR_K8_KERNEL_GS_BASE 0xc0000102
736	#define MSR_K8_TSC_AUX 0xc0000103
737	#define MSR_K8_SYSCFG 0xc0010010
738	#define MSR_K8_HWCR 0xc0010015
739	#define MSR_K8_IORRBASE0 0xc0010016
740	#define MSR_K8_IORRMASK0 0xc0010017
741	#define MSR_K8_IORRBASE1 0xc0010018
742	#define MSR_K8_IORRMASK1 0xc0010019
743	#define MSR_K8_TOP_MEM1 0xc001001a
744	#define MSR_K8_TOP_MEM2 0xc001001d
745	#define MSR_K8_VM_CR 0xc0010114
746	#define MSR_K8_VM_CR_SVM_DISABLE BIT(4)
747
748	#define MSR_K8_IGNNE 0xc0010115
749	#define MSR_K8_SMM_CTL 0xc0010116
750	/** SVM - VM_HSAVE_PA - Physical address for saving and restoring
751	* host state during world switch.
752	*/
753	#define MSR_K8_VM_HSAVE_PA 0xc0010117
754
755	/** @} */
756
757
758	/** @name Page Table / Directory / Directory Pointers / L4.
759	* @{
760	*/
761
762	/** Page table/directory entry as an unsigned integer. */
763	typedef uint32_t X86PGUINT;
764	/** Pointer to a page table/directory table entry as an unsigned integer. */
765	typedef X86PGUINT *PX86PGUINT;
766
767	/** Number of entries in a 32-bit PT/PD. */
768	#define X86_PG_ENTRIES 1024
769
770
771	/** PAE page table/page directory/pdptr/l4/l5 entry as an unsigned integer. */
772	typedef uint64_t X86PGPAEUINT;
773	/** Pointer to a PAE page table/page directory/pdptr/l4/l5 entry as an unsigned integer. */
774	typedef X86PGPAEUINT *PX86PGPAEUINT;
775
776	/** Number of entries in a PAE PT/PD/PDPTR/L4/L5. */
777	#define X86_PG_PAE_ENTRIES 512
778
779
780	/** The size of a 4KB page. */
781	#define X86_PAGE_4K_SIZE _4K
782	/** The page shift of a 4KB page. */
783	#define X86_PAGE_4K_SHIFT 12
784	/** The 4KB page offset mask. */
785	#define X86_PAGE_4K_OFFSET_MASK 0xfff
786	/** The 4KB page base mask for virtual addresses. */
787	#define X86_PAGE_4K_BASE_MASK 0xfffffffffffff000ULL
788	/** The 4KB page base mask for virtual addresses - 32bit version. */
789	#define X86_PAGE_4K_BASE_MASK_32 0xfffff000U
790
791	/** The size of a 2MB page. */
792	#define X86_PAGE_2M_SIZE _2M
793	/** The page shift of a 2MB page. */
794	#define X86_PAGE_2M_SHIFT 21
795	/** The 2MB page offset mask. */
796	#define X86_PAGE_2M_OFFSET_MASK 0x001fffff
797	/** The 2MB page base mask for virtual addresses. */
798	#define X86_PAGE_2M_BASE_MASK 0xffffffffffe00000ULL
799	/** The 2MB page base mask for virtual addresses - 32bit version. */
800	#define X86_PAGE_2M_BASE_MASK_32 0xffe00000U
801
802	/** The size of a 4MB page. */
803	#define X86_PAGE_4M_SIZE _4M
804	/** The page shift of a 4MB page. */
805	#define X86_PAGE_4M_SHIFT 22
806	/** The 4MB page offset mask. */
807	#define X86_PAGE_4M_OFFSET_MASK 0x003fffff
808	/** The 4MB page base mask for virtual addresses. */
809	#define X86_PAGE_4M_BASE_MASK 0xffffffffffc00000ULL
810	/** The 4MB page base mask for virtual addresses - 32bit version. */
811	#define X86_PAGE_4M_BASE_MASK_32 0xffc00000U
812
813
814
815	/** @name Page Table Entry
816	* @{
817	*/
818	/** Bit 0 - P - Present bit. */
819	#define X86_PTE_P BIT(0)
820	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
821	#define X86_PTE_RW BIT(1)
822	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
823	#define X86_PTE_US BIT(2)
824	/** Bit 3 - PWT - Page level write thru bit. */
825	#define X86_PTE_PWT BIT(3)
826	/** Bit 4 - PCD - Page level cache disable bit. */
827	#define X86_PTE_PCD BIT(4)
828	/** Bit 5 - A - Access bit. */
829	#define X86_PTE_A BIT(5)
830	/** Bit 6 - D - Dirty bit. */
831	#define X86_PTE_D BIT(6)
832	/** Bit 7 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
833	#define X86_PTE_PAT BIT(7)
834	/** Bit 8 - G - Global flag. */
835	#define X86_PTE_G BIT(8)
836	/** Bits 9-11 - - Available for use to system software. */
837	#define X86_PTE_AVL_MASK (BIT(9) \| BIT(10) \| BIT(11))
838	/** Bits 12-31 - - Physical Page number of the next level. */
839	#define X86_PTE_PG_MASK ( 0xfffff000 )
840
841	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
842	#if 1 /* we're using this internally and have to mask of the top 16-bit. */
843	#define X86_PTE_PAE_PG_MASK ( 0x0000fffffffff000ULL )
844	#else
845	#define X86_PTE_PAE_PG_MASK ( 0x000ffffffffff000ULL )
846	#endif
847	/** Bits 63 - NX - PAE - No execution flag. */
848	#define X86_PTE_PAE_NX BIT64(63)
849
850	/**
851	* Page table entry.
852	*/
853	typedef struct X86PTEBITS
854	{
855	/** Flags whether(=1) or not the page is present. */
856	unsigned u1Present : 1;
857	/** Read(=0) / Write(=1) flag. */
858	unsigned u1Write : 1;
859	/** User(=1) / Supervisor (=0) flag. */
860	unsigned u1User : 1;
861	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
862	unsigned u1WriteThru : 1;
863	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
864	unsigned u1CacheDisable : 1;
865	/** Accessed flag.
866	* Indicates that the page have been read or written to. */
867	unsigned u1Accessed : 1;
868	/** Dirty flag.
869	* Indicates that the page have been written to. */
870	unsigned u1Dirty : 1;
871	/** Reserved / If PAT enabled, bit 2 of the index. */
872	unsigned u1PAT : 1;
873	/** Global flag. (Ignored in all but final level.) */
874	unsigned u1Global : 1;
875	/** Available for use to system software. */
876	unsigned u3Available : 3;
877	/** Physical Page number of the next level. */
878	unsigned u20PageNo : 20;
879	} X86PTEBITS;
880	/** Pointer to a page table entry. */
881	typedef X86PTEBITS *PX86PTEBITS;
882	/** Pointer to a const page table entry. */
883	typedef const X86PTEBITS *PCX86PTEBITS;
884
885	/**
886	* Page table entry.
887	*/
888	typedef union X86PTE
889	{
890	/** Bit field view. */
891	X86PTEBITS n;
892	/** Unsigned integer view */
893	X86PGUINT u;
894	/** 32-bit view. */
895	uint32_t au32[1];
896	/** 16-bit view. */
897	uint16_t au16[2];
898	/** 8-bit view. */
899	uint8_t au8[4];
900	} X86PTE;
901	/** Pointer to a page table entry. */
902	typedef X86PTE *PX86PTE;
903	/** Pointer to a const page table entry. */
904	typedef const X86PTE *PCX86PTE;
905
906
907	/**
908	* PAE page table entry.
909	*/
910	typedef struct X86PTEPAEBITS
911	{
912	/** Flags whether(=1) or not the page is present. */
913	uint32_t u1Present : 1;
914	/** Read(=0) / Write(=1) flag. */
915	uint32_t u1Write : 1;
916	/** User(=1) / Supervisor(=0) flag. */
917	uint32_t u1User : 1;
918	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
919	uint32_t u1WriteThru : 1;
920	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
921	uint32_t u1CacheDisable : 1;
922	/** Accessed flag.
923	* Indicates that the page have been read or written to. */
924	uint32_t u1Accessed : 1;
925	/** Dirty flag.
926	* Indicates that the page have been written to. */
927	uint32_t u1Dirty : 1;
928	/** Reserved / If PAT enabled, bit 2 of the index. */
929	uint32_t u1PAT : 1;
930	/** Global flag. (Ignored in all but final level.) */
931	uint32_t u1Global : 1;
932	/** Available for use to system software. */
933	uint32_t u3Available : 3;
934	/** Physical Page number of the next level - Low Part. Don't use this. */
935	uint32_t u20PageNoLow : 20;
936	/** Physical Page number of the next level - High Part. Don't use this. */
937	uint32_t u20PageNoHigh : 20;
938	/** MBZ bits */
939	uint32_t u11Reserved : 11;
940	/** No Execute flag. */
941	uint32_t u1NoExecute : 1;
942	} X86PTEPAEBITS;
943	/** Pointer to a page table entry. */
944	typedef X86PTEPAEBITS *PX86PTEPAEBITS;
945	/** Pointer to a page table entry. */
946	typedef const X86PTEPAEBITS *PCX86PTEPAEBITS;
947
948	/**
949	* PAE Page table entry.
950	*/
951	typedef union X86PTEPAE
952	{
953	/** Bit field view. */
954	X86PTEPAEBITS n;
955	/** Unsigned integer view */
956	X86PGPAEUINT u;
957	/** 32-bit view. */
958	uint32_t au32[2];
959	/** 16-bit view. */
960	uint16_t au16[4];
961	/** 8-bit view. */
962	uint8_t au8[8];
963	} X86PTEPAE;
964	/** Pointer to a PAE page table entry. */
965	typedef X86PTEPAE *PX86PTEPAE;
966	/** Pointer to a const PAE page table entry. */
967	typedef const X86PTEPAE *PCX86PTEPAE;
968	/** @} */
969
970	/**
971	* Page table.
972	*/
973	typedef struct X86PT
974	{
975	/** PTE Array. */
976	X86PTE a[X86_PG_ENTRIES];
977	} X86PT;
978	/** Pointer to a page table. */
979	typedef X86PT *PX86PT;
980	/** Pointer to a const page table. */
981	typedef const X86PT *PCX86PT;
982
983	/** The page shift to get the PT index. */
984	#define X86_PT_SHIFT 12
985	/** The PT index mask (apply to a shifted page address). */
986	#define X86_PT_MASK 0x3ff
987
988
989	/**
990	* Page directory.
991	*/
992	typedef struct X86PTPAE
993	{
994	/** PTE Array. */
995	X86PTEPAE a[X86_PG_PAE_ENTRIES];
996	} X86PTPAE;
997	/** Pointer to a page table. */
998	typedef X86PTPAE *PX86PTPAE;
999	/** Pointer to a const page table. */
1000	typedef const X86PTPAE *PCX86PTPAE;
1001
1002	/** The page shift to get the PA PTE index. */
1003	#define X86_PT_PAE_SHIFT 12
1004	/** The PAE PT index mask (apply to a shifted page address). */
1005	#define X86_PT_PAE_MASK 0x1ff
1006
1007
1008	/** @name 4KB Page Directory Entry
1009	* @{
1010	*/
1011	/** Bit 0 - P - Present bit. */
1012	#define X86_PDE_P BIT(0)
1013	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1014	#define X86_PDE_RW BIT(1)
1015	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1016	#define X86_PDE_US BIT(2)
1017	/** Bit 3 - PWT - Page level write thru bit. */
1018	#define X86_PDE_PWT BIT(3)
1019	/** Bit 4 - PCD - Page level cache disable bit. */
1020	#define X86_PDE_PCD BIT(4)
1021	/** Bit 5 - A - Access bit. */
1022	#define X86_PDE_A BIT(5)
1023	/** Bit 7 - PS - Page size attribute.
1024	* Clear mean 4KB pages, set means large pages (2/4MB). */
1025	#define X86_PDE_PS BIT(7)
1026	/** Bits 9-11 - - Available for use to system software. */
1027	#define X86_PDE_AVL_MASK (BIT(9) \| BIT(10) \| BIT(11))
1028	/** Bits 12-31 - - Physical Page number of the next level. */
1029	#define X86_PDE_PG_MASK ( 0xfffff000 )
1030
1031	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1032	#if 1 /* we're using this internally and have to mask of the top 16-bit. */
1033	#define X86_PDE_PAE_PG_MASK ( 0x0000fffffffff000ULL )
1034	#else
1035	#define X86_PDE_PAE_PG_MASK ( 0x000ffffffffff000ULL )
1036	#endif
1037	/** Bits 63 - NX - PAE - No execution flag. */
1038	#define X86_PDE_PAE_NX BIT64(63)
1039
1040	/**
1041	* Page directory entry.
1042	*/
1043	typedef struct X86PDEBITS
1044	{
1045	/** Flags whether(=1) or not the page is present. */
1046	unsigned u1Present : 1;
1047	/** Read(=0) / Write(=1) flag. */
1048	unsigned u1Write : 1;
1049	/** User(=1) / Supervisor (=0) flag. */
1050	unsigned u1User : 1;
1051	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1052	unsigned u1WriteThru : 1;
1053	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1054	unsigned u1CacheDisable : 1;
1055	/** Accessed flag.
1056	* Indicates that the page have been read or written to. */
1057	unsigned u1Accessed : 1;
1058	/** Reserved / Ignored (dirty bit). */
1059	unsigned u1Reserved0 : 1;
1060	/** Size bit if PSE is enabled - in any event it's 0. */
1061	unsigned u1Size : 1;
1062	/** Reserved / Ignored (global bit). */
1063	unsigned u1Reserved1 : 1;
1064	/** Available for use to system software. */
1065	unsigned u3Available : 3;
1066	/** Physical Page number of the next level. */
1067	unsigned u20PageNo : 20;
1068	} X86PDEBITS;
1069	/** Pointer to a page directory entry. */
1070	typedef X86PDEBITS *PX86PDEBITS;
1071	/** Pointer to a const page directory entry. */
1072	typedef const X86PDEBITS *PCX86PDEBITS;
1073
1074
1075	/**
1076	* PAE page directory entry.
1077	*/
1078	typedef struct X86PDEPAEBITS
1079	{
1080	/** Flags whether(=1) or not the page is present. */
1081	uint32_t u1Present : 1;
1082	/** Read(=0) / Write(=1) flag. */
1083	uint32_t u1Write : 1;
1084	/** User(=1) / Supervisor (=0) flag. */
1085	uint32_t u1User : 1;
1086	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1087	uint32_t u1WriteThru : 1;
1088	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1089	uint32_t u1CacheDisable : 1;
1090	/** Accessed flag.
1091	* Indicates that the page have been read or written to. */
1092	uint32_t u1Accessed : 1;
1093	/** Reserved / Ignored (dirty bit). */
1094	uint32_t u1Reserved0 : 1;
1095	/** Size bit if PSE is enabled - in any event it's 0. */
1096	uint32_t u1Size : 1;
1097	/** Reserved / Ignored (global bit). / */
1098	uint32_t u1Reserved1 : 1;
1099	/** Available for use to system software. */
1100	uint32_t u3Available : 3;
1101	/** Physical Page number of the next level - Low Part. Don't use! */
1102	uint32_t u20PageNoLow : 20;
1103	/** Physical Page number of the next level - High Part. Don't use! */
1104	uint32_t u20PageNoHigh : 20;
1105	/** MBZ bits */
1106	uint32_t u11Reserved : 11;
1107	/** No Execute flag. */
1108	uint32_t u1NoExecute : 1;
1109	} X86PDEPAEBITS;
1110	/** Pointer to a page directory entry. */
1111	typedef X86PDEPAEBITS *PX86PDEPAEBITS;
1112	/** Pointer to a const page directory entry. */
1113	typedef const X86PDEPAEBITS *PCX86PDEPAEBITS;
1114
1115	/** @} */
1116
1117
1118	/** @name 2/4MB Page Directory Entry
1119	* @{
1120	*/
1121	/** Bit 0 - P - Present bit. */
1122	#define X86_PDE4M_P BIT(0)
1123	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1124	#define X86_PDE4M_RW BIT(1)
1125	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1126	#define X86_PDE4M_US BIT(2)
1127	/** Bit 3 - PWT - Page level write thru bit. */
1128	#define X86_PDE4M_PWT BIT(3)
1129	/** Bit 4 - PCD - Page level cache disable bit. */
1130	#define X86_PDE4M_PCD BIT(4)
1131	/** Bit 5 - A - Access bit. */
1132	#define X86_PDE4M_A BIT(5)
1133	/** Bit 6 - D - Dirty bit. */
1134	#define X86_PDE4M_D BIT(6)
1135	/** Bit 7 - PS - Page size attribute. Clear mean 4KB pages, set means large pages (2/4MB). */
1136	#define X86_PDE4M_PS BIT(7)
1137	/** Bit 8 - G - Global flag. */
1138	#define X86_PDE4M_G BIT(8)
1139	/** Bits 9-11 - AVL - Available for use to system software. */
1140	#define X86_PDE4M_AVL (BIT(9) \| BIT(10) \| BIT(11))
1141	/** Bit 12 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
1142	#define X86_PDE4M_PAT BIT(12)
1143	/** Shift to get from X86_PTE_PAT to X86_PDE4M_PAT. */
1144	#define X86_PDE4M_PAT_SHIFT (12 - 7)
1145	/** Bits 22-31 - - Physical Page number. */
1146	#define X86_PDE4M_PG_MASK ( 0xffc00000 )
1147	/** Bits 13-20 - - Physical Page number high part (32-39 bits). AMD64 hack. */
1148	#define X86_PDE4M_PG_HIGH_MASK ( 0x001fe000 )
1149	/** The number of bits to the high part of the page number. */
1150	#define X86_PDE4M_PG_HIGH_SHIFT 19
1151
1152	/** Bits 12-51 - - PAE - Physical Page number. */
1153	#define X86_PDE4M_PAE_PG_MASK ( 0x000fffffffc00000ULL )
1154	/** Bits 63 - NX - PAE - No execution flag. */
1155	#define X86_PDE4M_PAE_NX BIT64(63)
1156
1157	/**
1158	* 4MB page directory entry.
1159	*/
1160	typedef struct X86PDE4MBITS
1161	{
1162	/** Flags whether(=1) or not the page is present. */
1163	unsigned u1Present : 1;
1164	/** Read(=0) / Write(=1) flag. */
1165	unsigned u1Write : 1;
1166	/** User(=1) / Supervisor (=0) flag. */
1167	unsigned u1User : 1;
1168	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1169	unsigned u1WriteThru : 1;
1170	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1171	unsigned u1CacheDisable : 1;
1172	/** Accessed flag.
1173	* Indicates that the page have been read or written to. */
1174	unsigned u1Accessed : 1;
1175	/** Dirty flag.
1176	* Indicates that the page have been written to. */
1177	unsigned u1Dirty : 1;
1178	/** Page size flag - always 1 for 4MB entries. */
1179	unsigned u1Size : 1;
1180	/** Global flag. */
1181	unsigned u1Global : 1;
1182	/** Available for use to system software. */
1183	unsigned u3Available : 3;
1184	/** Reserved / If PAT enabled, bit 2 of the index. */
1185	unsigned u1PAT : 1;
1186	/** Bits 32-39 of the page number on AMD64.
1187	* This AMD64 hack allows accessing 40bits of physical memory without PAE. */
1188	unsigned u8PageNoHigh : 8;
1189	/** Reserved. */
1190	unsigned u1Reserved : 1;
1191	/** Physical Page number of the page. */
1192	unsigned u10PageNo : 10;
1193	} X86PDE4MBITS;
1194	/** Pointer to a page table entry. */
1195	typedef X86PDE4MBITS *PX86PDE4MBITS;
1196	/** Pointer to a const page table entry. */
1197	typedef const X86PDE4MBITS *PCX86PDE4MBITS;
1198
1199
1200	/**
1201	* 2MB PAE page directory entry.
1202	*/
1203	typedef struct X86PDE2MPAEBITS
1204	{
1205	/** Flags whether(=1) or not the page is present. */
1206	uint32_t u1Present : 1;
1207	/** Read(=0) / Write(=1) flag. */
1208	uint32_t u1Write : 1;
1209	/** User(=1) / Supervisor(=0) flag. */
1210	uint32_t u1User : 1;
1211	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1212	uint32_t u1WriteThru : 1;
1213	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1214	uint32_t u1CacheDisable : 1;
1215	/** Accessed flag.
1216	* Indicates that the page have been read or written to. */
1217	uint32_t u1Accessed : 1;
1218	/** Dirty flag.
1219	* Indicates that the page have been written to. */
1220	uint32_t u1Dirty : 1;
1221	/** Page size flag - always 1 for 2MB entries. */
1222	uint32_t u1Size : 1;
1223	/** Global flag. */
1224	uint32_t u1Global : 1;
1225	/** Available for use to system software. */
1226	uint32_t u3Available : 3;
1227	/** Reserved / If PAT enabled, bit 2 of the index. */
1228	uint32_t u1PAT : 1;
1229	/** Reserved. */
1230	uint32_t u9Reserved : 9;
1231	/** Physical Page number of the next level - Low part. Don't use! */
1232	uint32_t u10PageNoLow : 10;
1233	/** Physical Page number of the next level - High part. Don't use! */
1234	uint32_t u20PageNoHigh : 20;
1235	/** MBZ bits */
1236	uint32_t u11Reserved : 11;
1237	/** No Execute flag. */
1238	uint32_t u1NoExecute : 1;
1239	} X86PDE2MPAEBITS;
1240	/** Pointer to a 4MB PAE page table entry. */
1241	typedef X86PDE2MPAEBITS *PX86PDE2MPAEBITS;
1242	/** Pointer to a 4MB PAE page table entry. */
1243	typedef const X86PDE2MPAEBITS *PCX86PDE2MPAEBITS;
1244
1245	/** @} */
1246
1247	/**
1248	* Page directory entry.
1249	*/
1250	typedef union X86PDE
1251	{
1252	/** Normal view. */
1253	X86PDEBITS n;
1254	/** 4MB view (big). */
1255	X86PDE4MBITS b;
1256	/** Unsigned integer view. */
1257	X86PGUINT u;
1258	/** 8 bit unsigned integer view. */
1259	uint8_t au8[4];
1260	/** 16 bit unsigned integer view. */
1261	uint16_t au16[2];
1262	/** 32 bit unsigned integer view. */
1263	uint32_t au32[1];
1264	} X86PDE;
1265	/** Pointer to a page directory entry. */
1266	typedef X86PDE *PX86PDE;
1267	/** Pointer to a const page directory entry. */
1268	typedef const X86PDE *PCX86PDE;
1269
1270	/**
1271	* PAE page directory entry.
1272	*/
1273	typedef union X86PDEPAE
1274	{
1275	/** Normal view. */
1276	X86PDEPAEBITS n;
1277	/** 2MB page view (big). */
1278	X86PDE2MPAEBITS b;
1279	/** Unsigned integer view. */
1280	X86PGPAEUINT u;
1281	/** 8 bit unsigned integer view. */
1282	uint8_t au8[8];
1283	/** 16 bit unsigned integer view. */
1284	uint16_t au16[4];
1285	/** 32 bit unsigned integer view. */
1286	uint32_t au32[2];
1287	} X86PDEPAE;
1288	/** Pointer to a page directory entry. */
1289	typedef X86PDEPAE *PX86PDEPAE;
1290	/** Pointer to a const page directory entry. */
1291	typedef const X86PDEPAE *PCX86PDEPAE;
1292
1293	/**
1294	* Page directory.
1295	*/
1296	typedef struct X86PD
1297	{
1298	/** PDE Array. */
1299	X86PDE a[X86_PG_ENTRIES];
1300	} X86PD;
1301	/** Pointer to a page directory. */
1302	typedef X86PD *PX86PD;
1303	/** Pointer to a const page directory. */
1304	typedef const X86PD *PCX86PD;
1305
1306	/** The page shift to get the PD index. */
1307	#define X86_PD_SHIFT 22
1308	/** The PD index mask (apply to a shifted page address). */
1309	#define X86_PD_MASK 0x3ff
1310
1311
1312	/**
1313	* PAE page directory.
1314	*/
1315	typedef struct X86PDPAE
1316	{
1317	/** PDE Array. */
1318	X86PDEPAE a[X86_PG_PAE_ENTRIES];
1319	} X86PDPAE;
1320	/** Pointer to a PAE page directory. */
1321	typedef X86PDPAE *PX86PDPAE;
1322	/** Pointer to a const PAE page directory. */
1323	typedef const X86PDPAE *PCX86PDPAE;
1324
1325	/** The page shift to get the PAE PD index. */
1326	#define X86_PD_PAE_SHIFT 21
1327	/** The PAE PD index mask (apply to a shifted page address). */
1328	#define X86_PD_PAE_MASK 0x1ff
1329
1330
1331	/** @name Page Directory Pointer Table Entry (PAE)
1332	* @{
1333	*/
1334	/** Bit 0 - P - Present bit. */
1335	#define X86_PDPE_P BIT(0)
1336	/** Bit 1 - R/W - Read (clear) / Write (set) bit. Long Mode only. */
1337	#define X86_PDPE_RW BIT(1)
1338	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. Long Mode only. */
1339	#define X86_PDPE_US BIT(2)
1340	/** Bit 3 - PWT - Page level write thru bit. */
1341	#define X86_PDPE_PWT BIT(3)
1342	/** Bit 4 - PCD - Page level cache disable bit. */
1343	#define X86_PDPE_PCD BIT(4)
1344	/** Bit 5 - A - Access bit. Long Mode only. */
1345	#define X86_PDPE_A BIT(5)
1346	/** Bits 9-11 - - Available for use to system software. */
1347	#define X86_PDPE_AVL_MASK (BIT(9) \| BIT(10) \| BIT(11))
1348	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1349	#if 1 /* we're using this internally and have to mask of the top 16-bit. */
1350	#define X86_PDPE_PG_MASK ( 0x0000fffffffff000ULL )
1351	#else
1352	#define X86_PDPE_PG_MASK ( 0x000ffffffffff000ULL )
1353	#endif
1354	/** Bits 63 - NX - PAE - No execution flag. */
1355	#define X86_PDPE_NX BIT64(63)
1356
1357	/**
1358	* Page directory pointer table entry.
1359	*/
1360	typedef struct X86PDPEBITS
1361	{
1362	/** Flags whether(=1) or not the page is present. */
1363	uint32_t u1Present : 1;
1364	/** Read(=0) / Write(=1) flag. */
1365	uint32_t u1Write : 1;
1366	/** User(=1) / Supervisor (=0) flag. */
1367	uint32_t u1User : 1;
1368	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1369	uint32_t u1WriteThru : 1;
1370	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1371	uint32_t u1CacheDisable : 1;
1372	/** Accessed flag.
1373	* Indicates that the page have been read or written to. */
1374	uint32_t u1Accessed : 1;
1375	/** Chunk of reserved bits. */
1376	uint32_t u3Reserved : 3;
1377	/** Available for use to system software. */
1378	uint32_t u3Available : 3;
1379	/** Physical Page number of the next level - Low Part. Don't use! */
1380	uint32_t u20PageNoLow : 20;
1381	/** Physical Page number of the next level - High Part. Don't use! */
1382	uint32_t u20PageNoHigh : 20;
1383	/** MBZ bits */
1384	uint32_t u11Reserved : 11;
1385	/** No Execute flag. */
1386	uint32_t u1NoExecute : 1;
1387	} X86PDPEBITS;
1388	/** Pointer to a page directory pointer table entry. */
1389	typedef X86PDPEBITS *PX86PTPEBITS;
1390	/** Pointer to a const page directory pointer table entry. */
1391	typedef const X86PDPEBITS *PCX86PTPEBITS;
1392
1393	/**
1394	* Page directory pointer table entry.
1395	*/
1396	typedef union X86PDPE
1397	{
1398	/** Normal view. */
1399	X86PDPEBITS n;
1400	/** Unsigned integer view. */
1401	X86PGPAEUINT u;
1402	/** 8 bit unsigned integer view. */
1403	uint8_t au8[8];
1404	/** 16 bit unsigned integer view. */
1405	uint16_t au16[4];
1406	/** 32 bit unsigned integer view. */
1407	uint32_t au32[2];
1408	} X86PDPE;
1409	/** Pointer to a page directory pointer table entry. */
1410	typedef X86PDPE *PX86PDPE;
1411	/** Pointer to a const page directory pointer table entry. */
1412	typedef const X86PDPE *PCX86PDPE;
1413
1414
1415	/**
1416	* Page directory pointer table.
1417	*/
1418	typedef struct X86PDPTR
1419	{
1420	/** PDE Array. */
1421	X86PDPE a[X86_PG_PAE_ENTRIES];
1422	} X86PDPTR;
1423	/** Pointer to a page directory pointer table. */
1424	typedef X86PDPTR *PX86PDPTR;
1425	/** Pointer to a const page directory pointer table. */
1426	typedef const X86PDPTR *PCX86PDPTR;
1427
1428	/** The page shift to get the PDPTR index. */
1429	#define X86_PDPTR_SHIFT 30
1430	/** The PDPTR index mask (apply to a shifted page address). (32 bits PAE) */
1431	#define X86_PDPTR_MASK_32 0x3
1432	/** The PDPTR index mask (apply to a shifted page address). (64 bits PAE)*/
1433	#define X86_PDPTR_MASK 0x1ff
1434
1435	/** @} */
1436
1437
1438	/** @name Page Map Level-4 Entry (Long Mode PAE)
1439	* @{
1440	*/
1441	/** Bit 0 - P - Present bit. */
1442	#define X86_PML4E_P BIT(0)
1443	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1444	#define X86_PML4E_RW BIT(1)
1445	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1446	#define X86_PML4E_US BIT(2)
1447	/** Bit 3 - PWT - Page level write thru bit. */
1448	#define X86_PML4E_PWT BIT(3)
1449	/** Bit 4 - PCD - Page level cache disable bit. */
1450	#define X86_PML4E_PCD BIT(4)
1451	/** Bit 5 - A - Access bit. */
1452	#define X86_PML4E_A BIT(5)
1453	/** Bits 9-11 - - Available for use to system software. */
1454	#define X86_PML4E_AVL_MASK (BIT(9) \| BIT(10) \| BIT(11))
1455	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1456	#if 1 /* we're using this internally and have to mask of the top 16-bit. */
1457	#define X86_PML4E_PG_MASK ( 0x0000fffffffff000ULL )
1458	#else
1459	#define X86_PML4E_PG_MASK ( 0x000ffffffffff000ULL )
1460	#endif
1461	/** Bits 63 - NX - PAE - No execution flag. */
1462	#define X86_PML4E_NX BIT64(63)
1463
1464	/**
1465	* Page Map Level-4 Entry
1466	*/
1467	typedef struct X86PML4EBITS
1468	{
1469	/** Flags whether(=1) or not the page is present. */
1470	uint32_t u1Present : 1;
1471	/** Read(=0) / Write(=1) flag. */
1472	uint32_t u1Write : 1;
1473	/** User(=1) / Supervisor (=0) flag. */
1474	uint32_t u1User : 1;
1475	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1476	uint32_t u1WriteThru : 1;
1477	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1478	uint32_t u1CacheDisable : 1;
1479	/** Accessed flag.
1480	* Indicates that the page have been read or written to. */
1481	uint32_t u1Accessed : 1;
1482	/** Chunk of reserved bits. */
1483	uint32_t u3Reserved : 3;
1484	/** Available for use to system software. */
1485	uint32_t u3Available : 3;
1486	/** Physical Page number of the next level - Low Part. Don't use! */
1487	uint32_t u20PageNoLow : 20;
1488	/** Physical Page number of the next level - High Part. Don't use! */
1489	uint32_t u20PageNoHigh : 20;
1490	/** MBZ bits */
1491	uint32_t u11Reserved : 11;
1492	/** No Execute flag. */
1493	uint32_t u1NoExecute : 1;
1494	} X86PML4EBITS;
1495	/** Pointer to a page map level-4 entry. */
1496	typedef X86PML4EBITS *PX86PML4EBITS;
1497	/** Pointer to a const page map level-4 entry. */
1498	typedef const X86PML4EBITS *PCX86PML4EBITS;
1499
1500	/**
1501	* Page Map Level-4 Entry.
1502	*/
1503	typedef union X86PML4E
1504	{
1505	/** Normal view. */
1506	X86PML4EBITS n;
1507	/** Unsigned integer view. */
1508	X86PGPAEUINT u;
1509	/** 8 bit unsigned integer view. */
1510	uint8_t au8[8];
1511	/** 16 bit unsigned integer view. */
1512	uint16_t au16[4];
1513	/** 32 bit unsigned integer view. */
1514	uint32_t au32[2];
1515	} X86PML4E;
1516	/** Pointer to a page map level-4 entry. */
1517	typedef X86PML4E *PX86PML4E;
1518	/** Pointer to a const page map level-4 entry. */
1519	typedef const X86PML4E *PCX86PML4E;
1520
1521
1522	/**
1523	* Page Map Level-4.
1524	*/
1525	typedef struct X86PML4
1526	{
1527	/** PDE Array. */
1528	X86PML4E a[X86_PG_PAE_ENTRIES];
1529	} X86PML4;
1530	/** Pointer to a page map level-4. */
1531	typedef X86PML4 *PX86PML4;
1532	/** Pointer to a const page map level-4. */
1533	typedef const X86PML4 *PCX86PML4;
1534
1535	/** The page shift to get the PML4 index. */
1536	#define X86_PML4_SHIFT 39
1537	/** The PML4 index mask (apply to a shifted page address). */
1538	#define X86_PML4_MASK 0x1ff
1539
1540	/** @} */
1541
1542	/** @} */
1543
1544
1545	/**
1546	* 80-bit MMX/FPU register type.
1547	*/
1548	typedef struct X86FPUMMX
1549	{
1550	uint8_t reg[10];
1551	} X86FPUMMX;
1552	/** Pointer to a 80-bit MMX/FPU register type. */
1553	typedef X86FPUMMX *PX86FPUMMX;
1554	/** Pointer to a const 80-bit MMX/FPU register type. */
1555	typedef const X86FPUMMX *PCX86FPUMMX;
1556
1557	/**
1558	* FPU state (aka FSAVE/FRSTOR Memory Region).
1559	*/
1560	#pragma pack(1)
1561	typedef struct X86FPUSTATE
1562	{
1563	/** Control word. */
1564	uint16_t FCW;
1565	/** Alignment word */
1566	uint16_t Dummy1;
1567	/** Status word. */
1568	uint16_t FSW;
1569	/** Alignment word */
1570	uint16_t Dummy2;
1571	/** Tag word */
1572	uint16_t FTW;
1573	/** Alignment word */
1574	uint16_t Dummy3;
1575
1576	/** Instruction pointer. */
1577	uint32_t FPUIP;
1578	/** Code selector. */
1579	uint16_t CS;
1580	/** Opcode. */
1581	uint16_t FOP;
1582	/** FOO. */
1583	uint32_t FPUOO;
1584	/** FOS. */
1585	uint32_t FPUOS;
1586	/** FPU view - todo. */
1587	X86FPUMMX regs[8];
1588	} X86FPUSTATE;
1589	#pragma pack()
1590	/** Pointer to a FPU state. */
1591	typedef X86FPUSTATE *PX86FPUSTATE;
1592	/** Pointer to a const FPU state. */
1593	typedef const X86FPUSTATE *PCX86FPUSTATE;
1594
1595	/**
1596	* FPU Extended state (aka FXSAVE/FXRSTORE Memory Region).
1597	*/
1598	#pragma pack(1)
1599	typedef struct X86FXSTATE
1600	{
1601	/** Control word. */
1602	uint16_t FCW;
1603	/** Status word. */
1604	uint16_t FSW;
1605	/** Tag word (it's a byte actually). */
1606	uint8_t FTW;
1607	uint8_t huh1;
1608	/** Opcode. */
1609	uint16_t FOP;
1610	/** Instruction pointer. */
1611	uint32_t FPUIP;
1612	/** Code selector. */
1613	uint16_t CS;
1614	uint16_t Rsvrd1;
1615	/* - offset 16 - */
1616	/** Data pointer. */
1617	uint32_t FPUDP;
1618	/** Data segment */
1619	uint16_t DS;
1620	uint16_t Rsrvd2;
1621	uint32_t MXCSR;
1622	uint32_t MXCSR_MASK;
1623	/* - offset 32 - */
1624	union
1625	{
1626	/** MMX view. */
1627	uint64_t mmx;
1628	/** FPU view - todo. */
1629	X86FPUMMX fpu;
1630	/** 8-bit view. */
1631	uint8_t au8[16];
1632	/** 16-bit view. */
1633	uint16_t au16[8];
1634	/** 32-bit view. */
1635	uint32_t au32[4];
1636	/** 64-bit view. */
1637	uint64_t au64[2];
1638	/** 128-bit view. (yeah, very helpful) */
1639	uint128_t au128[1];
1640	} aRegs[8];
1641	/* - offset 160 - */
1642	union
1643	{
1644	/** XMM Register view . /
1645	uint128_t xmm;
1646	/** 8-bit view. */
1647	uint8_t au8[16];
1648	/** 16-bit view. */
1649	uint16_t au16[8];
1650	/** 32-bit view. */
1651	uint32_t au32[4];
1652	/** 64-bit view. */
1653	uint64_t au64[2];
1654	/** 128-bit view. (yeah, very helpful) */
1655	uint128_t au128[1];
1656	} aXMM[8];
1657	/* - offset 288 - */
1658	uint32_t au32RsrvdRest[(512 - 288) / sizeof(uint32_t)];
1659	} X86FXSTATE;
1660	#pragma pack()
1661	/** Pointer to a FPU Extended state. */
1662	typedef X86FXSTATE *PX86FXSTATE;
1663	/** Pointer to a const FPU Extended state. */
1664	typedef const X86FXSTATE *PCX86FXSTATE;
1665
1666
1667	/** @name Selector Descriptor
1668	* @{
1669	*/
1670
1671	/**
1672	* Generic descriptor table entry
1673	*/
1674	#pragma pack(1)
1675	typedef struct X86DESCGENERIC
1676	{
1677	/** Limit - Low word. */
1678	unsigned u16LimitLow : 16;
1679	/** Base address - lowe word.
1680	* Don't try set this to 24 because MSC is doing studing things then. */
1681	unsigned u16BaseLow : 16;
1682	/** Base address - first 8 bits of high word. */
1683	unsigned u8BaseHigh1 : 8;
1684	/** Segment Type. */
1685	unsigned u4Type : 4;
1686	/** Descriptor Type. System(=0) or code/data selector */
1687	unsigned u1DescType : 1;
1688	/** Descriptor Privelege level. */
1689	unsigned u2Dpl : 2;
1690	/** Flags selector present(=1) or not. */
1691	unsigned u1Present : 1;
1692	/** Segment limit 16-19. */
1693	unsigned u4LimitHigh : 4;
1694	/** Available for system software. */
1695	unsigned u1Available : 1;
1696	/** Reserved - 0. */
1697	unsigned u1Reserved : 1;
1698	/** This flags meaning depends on the segment type. Try make sense out
1699	* of the intel manual yourself. */
1700	unsigned u1DefBig : 1;
1701	/** Granularity of the limit. If set 4KB granularity is used, if
1702	* clear byte. */
1703	unsigned u1Granularity : 1;
1704	/** Base address - highest 8 bits. */
1705	unsigned u8BaseHigh2 : 8;
1706	} X86DESCGENERIC;
1707	#pragma pack()
1708	/** Pointer to a generic descriptor entry. */
1709	typedef X86DESCGENERIC *PX86DESCGENERIC;
1710	/** Pointer to a const generic descriptor entry. */
1711	typedef const X86DESCGENERIC *PCX86DESCGENERIC;
1712
1713
1714	/**
1715	* Descriptor attributes.
1716	*/
1717	typedef struct X86DESCATTRBITS
1718	{
1719	/** Segment Type. */
1720	unsigned u4Type : 4;
1721	/** Descriptor Type. System(=0) or code/data selector */
1722	unsigned u1DescType : 1;
1723	/** Descriptor Privelege level. */
1724	unsigned u2Dpl : 2;
1725	/** Flags selector present(=1) or not. */
1726	unsigned u1Present : 1;
1727	/** Segment limit 16-19. */
1728	unsigned u4LimitHigh : 4;
1729	/** Available for system software. */
1730	unsigned u1Available : 1;
1731	/** Reserved - 0. */
1732	unsigned u1Reserved : 1;
1733	/** This flags meaning depends on the segment type. Try make sense out
1734	* of the intel manual yourself. */
1735	unsigned u1DefBig : 1;
1736	/** Granularity of the limit. If set 4KB granularity is used, if
1737	* clear byte. */
1738	unsigned u1Granularity : 1;
1739	} X86DESCATTRBITS;
1740
1741
1742	#pragma pack(1)
1743	typedef union X86DESCATTR
1744	{
1745	/** Normal view. */
1746	X86DESCATTRBITS n;
1747	/** Unsigned integer view. */
1748	uint32_t u;
1749	} X86DESCATTR;
1750	#pragma pack()
1751
1752	/** Pointer to descriptor attributes. */
1753	typedef X86DESCATTR *PX86DESCATTR;
1754	/** Pointer to const descriptor attributes. */
1755	typedef const X86DESCATTR *PCX86DESCATTR;
1756
1757
1758	/**
1759	* Descriptor table entry.
1760	*/
1761	#pragma pack(1)
1762	typedef union X86DESC
1763	{
1764	/** Generic descriptor view. */
1765	X86DESCGENERIC Gen;
1766	#if 0
1767	/** IDT view. */
1768	VBOXIDTE Idt;
1769	#endif
1770
1771	/** 8 bit unsigned interger view. */
1772	uint8_t au8[8];
1773	/** 16 bit unsigned interger view. */
1774	uint16_t au16[4];
1775	/** 32 bit unsigned interger view. */
1776	uint32_t au32[2];
1777	} X86DESC;
1778	#pragma pack()
1779	/** Pointer to descriptor table entry. */
1780	typedef X86DESC *PX86DESC;
1781	/** Pointer to const descriptor table entry. */
1782	typedef const X86DESC *PCX86DESC;
1783
1784
1785	/**
1786	* 64 bits generic descriptor table entry
1787	* Note: most of these bits have no meaning in long mode.
1788	*/
1789	#pragma pack(1)
1790	typedef struct X86DESC64GENERIC
1791	{
1792	/** Limit - Low word - IGNORED. */
1793	unsigned u16LimitLow : 16;
1794	/** Base address - lowe word. - IGNORED
1795	* Don't try set this to 24 because MSC is doing studing things then. */
1796	unsigned u16BaseLow : 16;
1797	/** Base address - first 8 bits of high word. - IGNORED */
1798	unsigned u8BaseHigh1 : 8;
1799	/** Segment Type. */
1800	unsigned u4Type : 4;
1801	/** Descriptor Type. System(=0) or code/data selector */
1802	unsigned u1DescType : 1;
1803	/** Descriptor Privelege level. */
1804	unsigned u2Dpl : 2;
1805	/** Flags selector present(=1) or not. */
1806	unsigned u1Present : 1;
1807	/** Segment limit 16-19. - IGNORED */
1808	unsigned u4LimitHigh : 4;
1809	/** Available for system software. - IGNORED */
1810	unsigned u1Available : 1;
1811	/** Long mode flag. */
1812	unsigned u1Long : 1;
1813	/** This flags meaning depends on the segment type. Try make sense out
1814	* of the intel manual yourself. */
1815	unsigned u1DefBig : 1;
1816	/** Granularity of the limit. If set 4KB granularity is used, if
1817	* clear byte. - IGNORED */
1818	unsigned u1Granularity : 1;
1819	/** Base address - highest 8 bits. - IGNORED */
1820	unsigned u8BaseHigh2 : 8;
1821	/** Base address - bits 63-32. */
1822	unsigned u32BaseHigh3 : 32;
1823	unsigned u8Reserved : 8;
1824	unsigned u5Zeros : 5;
1825	unsigned u19Reserved : 19;
1826	} X86DESC64GENERIC;
1827	#pragma pack()
1828	/** Pointer to a generic descriptor entry. */
1829	typedef X86DESC64GENERIC *PX86DESC64GENERIC;
1830	/** Pointer to a const generic descriptor entry. */
1831	typedef const X86DESC64GENERIC *PCX86DESC64GENERIC;
1832
1833	/**
1834	* System descriptor table entry (64 bits)
1835	*/
1836	#pragma pack(1)
1837	typedef struct X86DESC64SYSTEM
1838	{
1839	/** Limit - Low word. */
1840	unsigned u16LimitLow : 16;
1841	/** Base address - lowe word.
1842	* Don't try set this to 24 because MSC is doing studing things then. */
1843	unsigned u16BaseLow : 16;
1844	/** Base address - first 8 bits of high word. */
1845	unsigned u8BaseHigh1 : 8;
1846	/** Segment Type. */
1847	unsigned u4Type : 4;
1848	/** Descriptor Type. System(=0) or code/data selector */
1849	unsigned u1DescType : 1;
1850	/** Descriptor Privelege level. */
1851	unsigned u2Dpl : 2;
1852	/** Flags selector present(=1) or not. */
1853	unsigned u1Present : 1;
1854	/** Segment limit 16-19. */
1855	unsigned u4LimitHigh : 4;
1856	/** Available for system software. */
1857	unsigned u1Available : 1;
1858	/** Reserved - 0. */
1859	unsigned u1Reserved : 1;
1860	/** This flags meaning depends on the segment type. Try make sense out
1861	* of the intel manual yourself. */
1862	unsigned u1DefBig : 1;
1863	/** Granularity of the limit. If set 4KB granularity is used, if
1864	* clear byte. */
1865	unsigned u1Granularity : 1;
1866	/** Base address - bits 31-24. */
1867	unsigned u8BaseHigh2 : 8;
1868	/** Base address - bits 63-32. */
1869	unsigned u32BaseHigh3 : 32;
1870	unsigned u8Reserved : 8;
1871	unsigned u5Zeros : 5;
1872	unsigned u19Reserved : 19;
1873	} X86DESC64SYSTEM;
1874	#pragma pack()
1875	/** Pointer to a generic descriptor entry. */
1876	typedef X86DESC64SYSTEM *PX86DESC64SYSTEM;
1877	/** Pointer to a const generic descriptor entry. */
1878	typedef const X86DESC64SYSTEM *PCX86DESC64SYSTEM;
1879
1880
1881	/**
1882	* Descriptor table entry.
1883	*/
1884	#pragma pack(1)
1885	typedef union X86DESC64
1886	{
1887	/** Generic descriptor view. */
1888	X86DESC64GENERIC Gen;
1889	/** System descriptor view. */
1890	X86DESC64SYSTEM System;
1891	#if 0
1892	X86DESC64GATE Gate;
1893	#endif
1894
1895	/** 8 bit unsigned interger view. */
1896	uint8_t au8[16];
1897	/** 16 bit unsigned interger view. */
1898	uint16_t au16[8];
1899	/** 32 bit unsigned interger view. */
1900	uint32_t au32[4];
1901	/** 64 bit unsigned interger view. */
1902	uint64_t au64[2];
1903	} X86DESC64;
1904	#pragma pack()
1905	/** Pointer to descriptor table entry. */
1906	typedef X86DESC64 *PX86DESC64;
1907	/** Pointer to const descriptor table entry. */
1908	typedef const X86DESC64 *PCX86DESC64;
1909
1910	#if HC_ARCH_BITS == 64
1911	typedef X86DESC64 X86DESCHC;
1912	typedef X86DESC64 *PX86DESCHC;
1913	#else
1914	typedef X86DESC X86DESCHC;
1915	typedef X86DESC *PX86DESCHC;
1916	#endif
1917
1918	/** @name Selector Descriptor Types.
1919	* @{
1920	*/
1921
1922	/** @name Non-System Selector Types.
1923	* @{ */
1924	/** Code(=set)/Data(=clear) bit. */
1925	#define X86_SEL_TYPE_CODE 8
1926	/** Memory(=set)/System(=clear) bit. */
1927	#define X86_SEL_TYPE_MEMORY BIT(4)
1928	/** Accessed bit. */
1929	#define X86_SEL_TYPE_ACCESSED 1
1930	/** Expand down bit (for data selectors only). */
1931	#define X86_SEL_TYPE_DOWN 4
1932	/** Conforming bit (for code selectors only). */
1933	#define X86_SEL_TYPE_CONF 4
1934	/** Write bit (for data selectors only). */
1935	#define X86_SEL_TYPE_WRITE 2
1936	/** Read bit (for code selectors only). */
1937	#define X86_SEL_TYPE_READ 2
1938
1939	/** Read only selector type. */
1940	#define X86_SEL_TYPE_RO 0
1941	/** Accessed read only selector type. */
1942	#define X86_SEL_TYPE_RO_ACC (0 \| X86_SEL_TYPE_ACCESSED)
1943	/** Read write selector type. */
1944	#define X86_SEL_TYPE_RW 2
1945	/** Accessed read write selector type. */
1946	#define X86_SEL_TYPE_RW_ACC (2 \| X86_SEL_TYPE_ACCESSED)
1947	/** Expand down read only selector type. */
1948	#define X86_SEL_TYPE_RO_DOWN 4
1949	/** Accessed expand down read only selector type. */
1950	#define X86_SEL_TYPE_RO_DOWN_ACC (4 \| X86_SEL_TYPE_ACCESSED)
1951	/** Expand down read write selector type. */
1952	#define X86_SEL_TYPE_RW_DOWN 6
1953	/** Accessed expand down read write selector type. */
1954	#define X86_SEL_TYPE_RW_DOWN_ACC (6 \| X86_SEL_TYPE_ACCESSED)
1955	/** Execute only selector type. */
1956	#define X86_SEL_TYPE_EO (0 \| X86_SEL_TYPE_CODE)
1957	/** Accessed execute only selector type. */
1958	#define X86_SEL_TYPE_EO_ACC (0 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
1959	/** Execute and read selector type. */
1960	#define X86_SEL_TYPE_ER (2 \| X86_SEL_TYPE_CODE)
1961	/** Accessed execute and read selector type. */
1962	#define X86_SEL_TYPE_ER_ACC (2 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
1963	/** Conforming execute only selector type. */
1964	#define X86_SEL_TYPE_EO_CONF (4 \| X86_SEL_TYPE_CODE)
1965	/** Accessed Conforming execute only selector type. */
1966	#define X86_SEL_TYPE_EO_CONF_ACC (4 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
1967	/** Conforming execute and write selector type. */
1968	#define X86_SEL_TYPE_ER_CONF (6 \| X86_SEL_TYPE_CODE)
1969	/** Accessed Conforming execute and write selector type. */
1970	#define X86_SEL_TYPE_ER_CONF_ACC (6 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
1971	/** @} */
1972
1973
1974	/** @name System Selector Types.
1975	* @{ */
1976	/** Undefined system selector type. */
1977	#define X86_SEL_TYPE_SYS_UNDEFINED 0
1978	/** 286 TSS selector. */
1979	#define X86_SEL_TYPE_SYS_286_TSS_AVAIL 1
1980	/** LDT selector. */
1981	#define X86_SEL_TYPE_SYS_LDT 2
1982	/** 286 TSS selector - Busy. */
1983	#define X86_SEL_TYPE_SYS_286_TSS_BUSY 3
1984	/** 286 Callgate selector. */
1985	#define X86_SEL_TYPE_SYS_286_CALL_GATE 4
1986	/** Taskgate selector. */
1987	#define X86_SEL_TYPE_SYS_TASK_GATE 5
1988	/** 286 Interrupt gate selector. */
1989	#define X86_SEL_TYPE_SYS_286_INT_GATE 6
1990	/** 286 Trapgate selector. */
1991	#define X86_SEL_TYPE_SYS_286_TRAP_GATE 7
1992	/** Undefined system selector. */
1993	#define X86_SEL_TYPE_SYS_UNDEFINED2 8
1994	/** 386 TSS selector. */
1995	#define X86_SEL_TYPE_SYS_386_TSS_AVAIL 9
1996	/** Undefined system selector. */
1997	#define X86_SEL_TYPE_SYS_UNDEFINED3 0xA
1998	/** 386 TSS selector - Busy. */
1999	#define X86_SEL_TYPE_SYS_386_TSS_BUSY 0xB
2000	/** 386 Callgate selector. */
2001	#define X86_SEL_TYPE_SYS_386_CALL_GATE 0xC
2002	/** Undefined system selector. */
2003	#define X86_SEL_TYPE_SYS_UNDEFINED4 0xD
2004	/** 386 Interruptgate selector. */
2005	#define X86_SEL_TYPE_SYS_386_INT_GATE 0xE
2006	/** 386 Trapgate selector. */
2007	#define X86_SEL_TYPE_SYS_386_TRAP_GATE 0xF
2008	/** @} */
2009
2010	/** @name AMD64 System Selector Types.
2011	* @{ */
2012	#define AMD64_SEL_TYPE_SYS_LDT 2
2013	/** 286 TSS selector - Busy. */
2014	#define AMD64_SEL_TYPE_SYS_TSS_AVAIL 9
2015	/** 386 TSS selector - Busy. */
2016	#define AMD64_SEL_TYPE_SYS_TSS_BUSY 0xB
2017	/** 386 Callgate selector. */
2018	#define AMD64_SEL_TYPE_SYS_CALL_GATE 0xC
2019	/** 386 Interruptgate selector. */
2020	#define AMD64_SEL_TYPE_SYS_INT_GATE 0xE
2021	/** 386 Trapgate selector. */
2022	#define AMD64_SEL_TYPE_SYS_TRAP_GATE 0xF
2023	/** @} */
2024
2025	/** @} */
2026
2027
2028	/** @name Descriptor Table Entry Flag Masks.
2029	* These are for the 2nd 32-bit word of a descriptor.
2030	* @{ */
2031	/** Bits 8-11 - TYPE - Descriptor type mask. */
2032	#define X86_DESC_TYPE_MASK (BIT(8) \| BIT(9) \| BIT(10) \| BIT(11))
2033	/** Bit 12 - S - System (=0) or Code/Data (=1). */
2034	#define X86_DESC_S BIT(12)
2035	/** Bits 13-14 - DPL - Descriptor Privilege Level. */
2036	#define X86_DESC_DPL (BIT(13) \| BIT(14))
2037	/** Bit 15 - P - Present. */
2038	#define X86_DESC_P BIT(15)
2039	/** Bit 20 - AVL - Available for system software. */
2040	#define X86_DESC_AVL BIT(20)
2041	/** Bit 22 - DB - Default operation size. 0 = 16 bit, 1 = 32 bit. */
2042	#define X86_DESC_DB BIT(22)
2043	/** Bit 23 - G - Granularity of the limit. If set 4KB granularity is
2044	* used, if clear byte. */
2045	#define X86_DESC_G BIT(23)
2046	/** @} */
2047
2048	/** @} */
2049
2050
2051	/** @name Selectors.
2052	* @{
2053	*/
2054
2055	/**
2056	* The shift used to convert a selector from and to index an index (C).
2057	*/
2058	#define X86_SEL_SHIFT 3
2059
2060	/**
2061	* The shift used to convert a selector from and to index an index (C).
2062	*/
2063	#define AMD64_SEL_SHIFT 4
2064
2065	#if HC_ARCH_BITS == 64
2066	#define X86_SEL_SHIFT_HC AMD64_SEL_SHIFT
2067	#else
2068	#define X86_SEL_SHIFT_HC X86_SEL_SHIFT
2069	#endif
2070
2071	/**
2072	* The mask used to mask off the table indicator and CPL of an selector.
2073	*/
2074	#define X86_SEL_MASK 0xfff8
2075
2076	/**
2077	* The bit indicating that a selector is in the LDT and not in the GDT.
2078	*/
2079	#define X86_SEL_LDT 0x0004
2080	/**
2081	* The bit mask for getting the RPL of a selector.
2082	*/
2083	#define X86_SEL_RPL 0x0003
2084
2085	/** @} */
2086
2087
2088	/**
2089	* x86 Exceptions/Faults/Traps.
2090	*/
2091	typedef enum X86XCPT
2092	{
2093	/** \#DE - Divide error. */
2094	X86_XCPT_DE = 0x00,
2095	/** \#DB - Debug event (single step, DRx, ..) */
2096	X86_XCPT_DB = 0x01,
2097	/** NMI - Non-Maskable Interrupt */
2098	X86_XCPT_NMI = 0x02,
2099	/** \#BP - Breakpoint (INT3). */
2100	X86_XCPT_BP = 0x03,
2101	/** \#OF - Overflow (INTO). */
2102	X86_XCPT_OF = 0x04,
2103	/** \#BR - Bound range exceeded (BOUND). */
2104	X86_XCPT_BR = 0x05,
2105	/** \#UD - Undefined opcode. */
2106	X86_XCPT_UD = 0x06,
2107	/** \#NM - Device not available (math coprocessor device). */
2108	X86_XCPT_NM = 0x07,
2109	/** \#DF - Double fault. */
2110	X86_XCPT_DF = 0x08,
2111	/** ??? - Coprocessor segment overrun (obsolete). */
2112	X86_XCPT_CO_SEG_OVERRUN = 0x09,
2113	/** \#TS - Taskswitch (TSS). */
2114	X86_XCPT_TS = 0x0a,
2115	/** \#NP - Segment no present. */
2116	X86_XCPT_NP = 0x0b,
2117	/** \#SS - Stack segment fault. */
2118	X86_XCPT_SS = 0x0c,
2119	/** \#GP - General protection fault. */
2120	X86_XCPT_GP = 0x0d,
2121	/** \#PF - Page fault. */
2122	X86_XCPT_PF = 0x0e,
2123	/* 0x0f is reserved. */
2124	/** \#MF - Math fault (FPU). */
2125	X86_XCPT_MF = 0x10,
2126	/** \#AC - Alignment check. */
2127	X86_XCPT_AC = 0x11,
2128	/** \#MC - Machine check. */
2129	X86_XCPT_MC = 0x12,
2130	/** \#XF - SIMD Floating-Pointer Exception. */
2131	X86_XCPT_XF = 0x13
2132	} X86XCPT;
2133	/** Pointer to a x86 exception code. */
2134	typedef X86XCPT *PX86XCPT;
2135	/** Pointer to a const x86 exception code. */
2136	typedef const X86XCPT *PCX86XCPT;
2137
2138
2139	/** @name Trap Error Codes
2140	* @{
2141	*/
2142	/** External indicator. */
2143	#define X86_TRAP_ERR_EXTERNAL 1
2144	/** IDT indicator. */
2145	#define X86_TRAP_ERR_IDT 2
2146	/** Descriptor table indicator - If set LDT, if clear GDT. */
2147	#define X86_TRAP_ERR_TI 4
2148	/** Mask for getting the selector. */
2149	#define X86_TRAP_ERR_SEL_MASK 0xfff8
2150	/** Shift for getting the selector table index (C type index). */
2151	#define X86_TRAP_ERR_SEL_SHIFT 3
2152	/** @} */
2153
2154
2155	/** @name \#PF Trap Error Codes
2156	* @{
2157	*/
2158	/** Bit 0 - P - Not present (clear) or page level protection (set) fault. */
2159	#define X86_TRAP_PF_P BIT(0)
2160	/** Bit 1 - R/W - Read (clear) or write (set) access. */
2161	#define X86_TRAP_PF_RW BIT(1)
2162	/** Bit 2 - U/S - CPU executing in user mode (set) or supervisor mode (clear). */
2163	#define X86_TRAP_PF_US BIT(2)
2164	/** Bit 3 - RSVD- Reserved bit violation (set), i.e. reserved bit was set to 1. */
2165	#define X86_TRAP_PF_RSVD BIT(3)
2166	/** Bit 4 - I/D - Instruction fetch (set) / Data access (clear) - PAE + NXE. */
2167	#define X86_TRAP_PF_ID BIT(4)
2168	/** @} */
2169
2170	#pragma pack(1)
2171	/**
2172	* 32-bit IDTR/GDTR.
2173	*/
2174	typedef struct X86XDTR32
2175	{
2176	/** Size of the descriptor table. */
2177	uint16_t cb;
2178	/** Address of the descriptor table. */
2179	uint32_t uAddr;
2180	} X86XDTR32, *PX86XDTR32;
2181	#pragma pack()
2182
2183	#pragma pack(1)
2184	/**
2185	* 64-bit IDTR/GDTR.
2186	*/
2187	typedef struct X86XDTR64
2188	{
2189	/** Size of the descriptor table. */
2190	uint16_t cb;
2191	/** Address of the descriptor table. */
2192	uint64_t uAddr;
2193	} X86XDTR64, *PX86XDTR64;
2194	#pragma pack()
2195
2196	/** @} */
2197
2198	#endif
2199

Note: See TracBrowser for help on using the repository browser.

source: vbox/trunk/include/VBox/x86.h@ 4011

Download in other formats: