x86.h@ 4337

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1	/** @file
2	* X86 (and AMD64) Structures and Definitions.
3	*/
4
5	/*
6	* Copyright (C) 2006-2007 innotek GmbH
7	*
8	* This file is part of VirtualBox Open Source Edition (OSE), as
9	* available from http://www.virtualbox.org. This file is free software;
10	* you can redistribute it and/or modify it under the terms of the GNU
11	* General Public License as published by the Free Software Foundation,
12	* in version 2 as it comes in the "COPYING" file of the VirtualBox OSE
13	* distribution. VirtualBox OSE is distributed in the hope that it will
14	* be useful, but WITHOUT ANY WARRANTY of any kind.
15	*/
16
17	/*
18	* x86.mac is generated from this file using:
19	* sed -e '/__VBox_x86_h__/d' -e '/#define/!d' -e 's/#define/%define/' include/VBox/x86.h
20	*/
21
22	#ifndef ___VBox_x86_h
23	#define ___VBox_x86_h
24
25	#include <VBox/types.h>
26
27	/* Workaround for Solaris sys/regset.h defining CS, DS */
28	#if defined(RT_OS_SOLARIS)
29	# undef CS
30	# undef DS
31	#endif
32
33	/** @defgroup grp_x86 x86 Types and Definitions
34	* @{
35	*/
36
37	/**
38	* EFLAGS Bits.
39	*/
40	typedef struct X86EFLAGSBITS
41	{
42	/** Bit 0 - CF - Carry flag - Status flag. */
43	unsigned u1CF : 1;
44	/** Bit 1 - 1 - Reserved flag. */
45	unsigned u1Reserved0 : 1;
46	/** Bit 2 - PF - Parity flag - Status flag. */
47	unsigned u1PF : 1;
48	/** Bit 3 - 0 - Reserved flag. */
49	unsigned u1Reserved1 : 1;
50	/** Bit 4 - AF - Auxiliary carry flag - Status flag. */
51	unsigned u1AF : 1;
52	/** Bit 5 - 0 - Reserved flag. */
53	unsigned u1Reserved2 : 1;
54	/** Bit 6 - ZF - Zero flag - Status flag. */
55	unsigned u1ZF : 1;
56	/** Bit 7 - SF - Signed flag - Status flag. */
57	unsigned u1SF : 1;
58	/** Bit 8 - TF - Trap flag - System flag. */
59	unsigned u1TF : 1;
60	/** Bit 9 - IF - Interrupt flag - System flag. */
61	unsigned u1IF : 1;
62	/** Bit 10 - DF - Direction flag - Control flag. */
63	unsigned u1DF : 1;
64	/** Bit 11 - OF - Overflow flag - Status flag. */
65	unsigned u1OF : 1;
66	/** Bit 12-13 - IOPL - I/O prvilege level flag - System flag. */
67	unsigned u2IOPL : 2;
68	/** Bit 14 - NT - Nested task flag - System flag. */
69	unsigned u1NT : 1;
70	/** Bit 15 - 0 - Reserved flag. */
71	unsigned u1Reserved3 : 1;
72	/** Bit 16 - RF - Resume flag - System flag. */
73	unsigned u1RF : 1;
74	/** Bit 17 - VM - Virtual 8086 mode - System flag. */
75	unsigned u1VM : 1;
76	/** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
77	unsigned u1AC : 1;
78	/** Bit 19 - VIF - Virtual interupt flag - System flag. */
79	unsigned u1VIF : 1;
80	/** Bit 20 - VIP - Virtual interupt pending flag - System flag. */
81	unsigned u1VIP : 1;
82	/** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
83	unsigned u1ID : 1;
84	/** Bit 22-31 - 0 - Reserved flag. */
85	unsigned u10Reserved4 : 10;
86	} X86EFLAGSBITS;
87	/** Pointer to EFLAGS bits. */
88	typedef X86EFLAGSBITS *PX86EFLAGSBITS;
89	/** Pointer to const EFLAGS bits. */
90	typedef const X86EFLAGSBITS *PCX86EFLAGSBITS;
91
92	/**
93	* EFLAGS.
94	*/
95	typedef union X86EFLAGS
96	{
97	/** The bitfield view. */
98	X86EFLAGSBITS Bits;
99	/** The 8-bit view. */
100	uint8_t au8[4];
101	/** The 16-bit view. */
102	uint16_t au16[2];
103	/** The 32-bit view. */
104	uint32_t au32[1];
105	/** The 32-bit view. */
106	uint32_t u32;
107	} X86EFLAGS;
108	/** Pointer to EFLAGS. */
109	typedef X86EFLAGS *PX86EFLAGS;
110	/** Pointer to const EFLAGS. */
111	typedef const X86EFLAGS *PCX86EFLAGS;
112
113
114	/** @name EFLAGS
115	* @{
116	*/
117	/** Bit 0 - CF - Carry flag - Status flag. */
118	#define X86_EFL_CF BIT(0)
119	/** Bit 2 - PF - Parity flag - Status flag. */
120	#define X86_EFL_PF BIT(2)
121	/** Bit 4 - AF - Auxiliary carry flag - Status flag. */
122	#define X86_EFL_AF BIT(4)
123	/** Bit 6 - ZF - Zero flag - Status flag. */
124	#define X86_EFL_ZF BIT(6)
125	/** Bit 7 - SF - Signed flag - Status flag. */
126	#define X86_EFL_SF BIT(7)
127	/** Bit 8 - TF - Trap flag - System flag. */
128	#define X86_EFL_TF BIT(8)
129	/** Bit 9 - IF - Interrupt flag - System flag. */
130	#define X86_EFL_IF BIT(9)
131	/** Bit 10 - DF - Direction flag - Control flag. */
132	#define X86_EFL_DF BIT(10)
133	/** Bit 11 - OF - Overflow flag - Status flag. */
134	#define X86_EFL_OF BIT(11)
135	/** Bit 12-13 - IOPL - I/O prvilege level flag - System flag. */
136	#define X86_EFL_IOPL (BIT(12) \| BIT(13))
137	/** Bit 14 - NT - Nested task flag - System flag. */
138	#define X86_EFL_NT BIT(14)
139	/** Bit 16 - RF - Resume flag - System flag. */
140	#define X86_EFL_RF BIT(16)
141	/** Bit 17 - VM - Virtual 8086 mode - System flag. */
142	#define X86_EFL_VM BIT(17)
143	/** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
144	#define X86_EFL_AC BIT(18)
145	/** Bit 19 - VIF - Virtual interupt flag - System flag. */
146	#define X86_EFL_VIF BIT(19)
147	/** Bit 20 - VIP - Virtual interupt pending flag - System flag. */
148	#define X86_EFL_VIP BIT(20)
149	/** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
150	#define X86_EFL_ID BIT(21)
151	/** IOPL shift. */
152	#define X86_EFL_IOPL_SHIFT 12
153	/** The the IOPL level from the flags. */
154	#define X86_EFL_GET_IOPL(efl) (((efl) >> X86_EFL_IOPL_SHIFT) & 3)
155	/** @} */
156
157
158	/** CPUID Feature information - ECX.
159	* CPUID query with EAX=1.
160	*/
161	typedef struct X86CPUIDFEATECX
162	{
163	/** Bit 0 - SSE3 - Supports SSE3 or not. */
164	unsigned u1SSE3 : 1;
165	/** Reserved. */
166	unsigned u2Reserved1 : 2;
167	/** Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
168	unsigned u1Monitor : 1;
169	/** Bit 4 - CPL-DS - CPL Qualified Debug Store. */
170	unsigned u1CPLDS : 1;
171	/** Bit 5 - VMX - Virtual Machine Technology. */
172	unsigned u1VMX : 1;
173	/** Reserved. */
174	unsigned u1Reserved2 : 1;
175	/** Bit 7 - EST - Enh. SpeedStep Tech. */
176	unsigned u1EST : 1;
177	/** Bit 8 - TM2 - Terminal Monitor 2. */
178	unsigned u1TM2 : 1;
179	/** Reserved. */
180	unsigned u1Reserved3 : 1;
181	/** Bit 10 - CNTX-ID - L1 Context ID. */
182	unsigned u1CNTXID : 1;
183	/** Reserved. */
184	unsigned u2Reserved4 : 2;
185	/** Bit 13 - CX16 - CMPXCHG16B. */
186	unsigned u1CX16 : 1;
187	/** Reserved. */
188	unsigned u18Reserved5 : 18;
189
190	} X86CPUIDFEATECX;
191	/** Pointer to CPUID Feature Information - ECX. */
192	typedef X86CPUIDFEATECX *PX86CPUIDFEATECX;
193	/** Pointer to const CPUID Feature Information - ECX. */
194	typedef const X86CPUIDFEATECX *PCX86CPUIDFEATECX;
195
196
197	/** CPUID Feature Information - EDX.
198	* CPUID query with EAX=1.
199	*/
200	typedef struct X86CPUIDFEATEDX
201	{
202	/** Bit 0 - FPU - x87 FPU on Chip. */
203	unsigned u1FPU : 1;
204	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
205	unsigned u1VME : 1;
206	/** Bit 2 - DE - Debugging extensions. */
207	unsigned u1DE : 1;
208	/** Bit 3 - PSE - Page Size Extension. */
209	unsigned u1PSE : 1;
210	/** Bit 4 - TSC - Tiem Stamp Counter. */
211	unsigned u1TSC : 1;
212	/** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
213	unsigned u1MSR : 1;
214	/** Bit 6 - PAE - Physical Address Extension. */
215	unsigned u1PAE : 1;
216	/** Bit 7 - MCE - Machine Check Exception. */
217	unsigned u1MCE : 1;
218	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
219	unsigned u1CX8 : 1;
220	/** Bit 9 - APIC - APIC On-Chick. */
221	unsigned u1APIC : 1;
222	/** Bit 10 - Reserved. */
223	unsigned u1Reserved1 : 1;
224	/** Bit 11 - SEP - SYSENTER and SYSEXIT. */
225	unsigned u1SEP : 1;
226	/** Bit 12 - MTRR - Memory Type Range Registers. */
227	unsigned u1MTRR : 1;
228	/** Bit 13 - PGE - PTE Global Bit. */
229	unsigned u1PGE : 1;
230	/** Bit 14 - MCA - Machine Check Architecture. */
231	unsigned u1MCA : 1;
232	/** Bit 15 - CMOV - Conditional Move Instructions. */
233	unsigned u1CMOV : 1;
234	/** Bit 16 - PAT - Page Attribute Table. */
235	unsigned u1PAT : 1;
236	/** Bit 17 - PSE-36 - 36-bit Page Size Extention. */
237	unsigned u1PSE36 : 1;
238	/** Bit 18 - PSN - Processor Serial Number. */
239	unsigned u1PSN : 1;
240	/** Bit 19 - CLFSH - CLFLUSH Instruction. */
241	unsigned u1CLFSH : 1;
242	/** Bit 20 - Reserved. */
243	unsigned u1Reserved2 : 1;
244	/** Bit 21 - DS - Debug Store. */
245	unsigned u1DS : 1;
246	/** Bit 22 - ACPI - Thermal Monitor and Software Controlled Clock Facilities. */
247	unsigned u1ACPI : 1;
248	/** Bit 23 - MMX - Intel MMX 'Technology'. */
249	unsigned u1MMX : 1;
250	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
251	unsigned u1FXSR : 1;
252	/** Bit 25 - SSE - SSE Support. */
253	unsigned u1SSE : 1;
254	/** Bit 26 - SSE2 - SSE2 Support. */
255	unsigned u1SSE2 : 1;
256	/** Bit 27 - SS - Self Snoop. */
257	unsigned u1SS : 1;
258	/** Bit 28 - HTT - Hyper-Threading Technology. */
259	unsigned u1HTT : 1;
260	/** Bit 29 - TM - Thermal Monitor. */
261	unsigned u1TM : 1;
262	/** Bit 30 - Reserved - . */
263	unsigned u1Reserved3 : 1;
264	/** Bit 31 - PBE - Pending Break Enabled. */
265	unsigned u1PBE : 1;
266	} X86CPUIDFEATEDX;
267	/** Pointer to CPUID Feature Information - EDX. */
268	typedef X86CPUIDFEATEDX *PX86CPUIDFEATEDX;
269	/** Pointer to const CPUID Feature Information - EDX. */
270	typedef const X86CPUIDFEATEDX *PCX86CPUIDFEATEDX;
271
272	/** @name CPUID Vendor information.
273	* CPUID query with EAX=0.
274	* @{
275	*/
276	#define X86_CPUID_VENDOR_INTEL_EBX 0x756e6547 /* Genu */
277	#define X86_CPUID_VENDOR_INTEL_ECX 0x6c65746e /* ntel */
278	#define X86_CPUID_VENDOR_INTEL_EDX 0x49656e69 /* ineI */
279
280	#define X86_CPUID_VENDOR_AMD_EBX 0x68747541 /* Auth */
281	#define X86_CPUID_VENDOR_AMD_ECX 0x444d4163 /* cAMD */
282	#define X86_CPUID_VENDOR_AMD_EDX 0x69746e65 /* enti */
283	/** @} */
284
285
286	/** @name CPUID Feature information.
287	* CPUID query with EAX=1.
288	* @{
289	*/
290	/** ECX Bit 0 - SSE3 - Supports SSE3 or not. */
291	#define X86_CPUID_FEATURE_ECX_SSE3 BIT(0)
292	/** ECX Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
293	#define X86_CPUID_FEATURE_ECX_MONITOR BIT(3)
294	/** ECX Bit 4 - CPL-DS - CPL Qualified Debug Store. */
295	#define X86_CPUID_FEATURE_ECX_CPLDS BIT(4)
296	/** ECX Bit 5 - VMX - Virtual Machine Technology. */
297	#define X86_CPUID_FEATURE_ECX_VMX BIT(5)
298	/** ECX Bit 7 - EST - Enh. SpeedStep Tech. */
299	#define X86_CPUID_FEATURE_ECX_EST BIT(7)
300	/** ECX Bit 8 - TM2 - Terminal Monitor 2. */
301	#define X86_CPUID_FEATURE_ECX_TM2 BIT(8)
302	/** ECX Bit 10 - CNTX-ID - L1 Context ID. */
303	#define X86_CPUID_FEATURE_ECX_CNTXID BIT(10)
304	/** ECX Bit 13 - CX16 - L1 Context ID. */
305	#define X86_CPUID_FEATURE_ECX_CX16 BIT(13)
306
307
308	/** Bit 0 - FPU - x87 FPU on Chip. */
309	#define X86_CPUID_FEATURE_EDX_FPU BIT(0)
310	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
311	#define X86_CPUID_FEATURE_EDX_VME BIT(1)
312	/** Bit 2 - DE - Debugging extensions. */
313	#define X86_CPUID_FEATURE_EDX_DE BIT(2)
314	/** Bit 3 - PSE - Page Size Extension. */
315	#define X86_CPUID_FEATURE_EDX_PSE BIT(3)
316	/** Bit 4 - TSC - Time Stamp Counter. */
317	#define X86_CPUID_FEATURE_EDX_TSC BIT(4)
318	/** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
319	#define X86_CPUID_FEATURE_EDX_MSR BIT(5)
320	/** Bit 6 - PAE - Physical Address Extension. */
321	#define X86_CPUID_FEATURE_EDX_PAE BIT(6)
322	/** Bit 7 - MCE - Machine Check Exception. */
323	#define X86_CPUID_FEATURE_EDX_MCE BIT(7)
324	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
325	#define X86_CPUID_FEATURE_EDX_CX8 BIT(8)
326	/** Bit 9 - APIC - APIC On-Chip. */
327	#define X86_CPUID_FEATURE_EDX_APIC BIT(9)
328	/** Bit 11 - SEP - SYSENTER and SYSEXIT. */
329	#define X86_CPUID_FEATURE_EDX_SEP BIT(11)
330	/** Bit 12 - MTRR - Memory Type Range Registers. */
331	#define X86_CPUID_FEATURE_EDX_MTRR BIT(12)
332	/** Bit 13 - PGE - PTE Global Bit. */
333	#define X86_CPUID_FEATURE_EDX_PGE BIT(13)
334	/** Bit 14 - MCA - Machine Check Architecture. */
335	#define X86_CPUID_FEATURE_EDX_MCA BIT(14)
336	/** Bit 15 - CMOV - Conditional Move Instructions. */
337	#define X86_CPUID_FEATURE_EDX_CMOV BIT(15)
338	/** Bit 16 - PAT - Page Attribute Table. */
339	#define X86_CPUID_FEATURE_EDX_PAT BIT(16)
340	/** Bit 17 - PSE-36 - 36-bit Page Size Extention. */
341	#define X86_CPUID_FEATURE_EDX_PSE36 BIT(17)
342	/** Bit 18 - PSN - Processor Serial Number. */
343	#define X86_CPUID_FEATURE_EDX_PSN BIT(18)
344	/** Bit 19 - CLFSH - CLFLUSH Instruction. */
345	#define X86_CPUID_FEATURE_EDX_CLFSH BIT(19)
346	/** Bit 21 - DS - Debug Store. */
347	#define X86_CPUID_FEATURE_EDX_DS BIT(21)
348	/** Bit 22 - ACPI - Termal Monitor and Software Controlled Clock Facilities. */
349	#define X86_CPUID_FEATURE_EDX_ACPI BIT(22)
350	/** Bit 23 - MMX - Intel MMX Technology. */
351	#define X86_CPUID_FEATURE_EDX_MMX BIT(23)
352	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
353	#define X86_CPUID_FEATURE_EDX_FXSR BIT(24)
354	/** Bit 25 - SSE - SSE Support. */
355	#define X86_CPUID_FEATURE_EDX_SSE BIT(25)
356	/** Bit 26 - SSE2 - SSE2 Support. */
357	#define X86_CPUID_FEATURE_EDX_SSE2 BIT(26)
358	/** Bit 27 - SS - Self Snoop. */
359	#define X86_CPUID_FEATURE_EDX_SS BIT(27)
360	/** Bit 28 - HTT - Hyper-Threading Technology. */
361	#define X86_CPUID_FEATURE_EDX_HTT BIT(28)
362	/** Bit 29 - TM - Therm. Monitor. */
363	#define X86_CPUID_FEATURE_EDX_TM BIT(29)
364	/** Bit 31 - PBE - Pending Break Enabled. */
365	#define X86_CPUID_FEATURE_EDX_PBE BIT(31)
366	/** @} */
367
368
369	/** @name CPUID AMD Feature information.
370	* CPUID query with EAX=0x80000001.
371	* @{
372	*/
373	/** Bit 0 - FPU - x87 FPU on Chip. */
374	#define X86_CPUID_AMD_FEATURE_EDX_FPU BIT(0)
375	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
376	#define X86_CPUID_AMD_FEATURE_EDX_VME BIT(1)
377	/** Bit 2 - DE - Debugging extensions. */
378	#define X86_CPUID_AMD_FEATURE_EDX_DE BIT(2)
379	/** Bit 3 - PSE - Page Size Extension. */
380	#define X86_CPUID_AMD_FEATURE_EDX_PSE BIT(3)
381	/** Bit 4 - TSC - Time Stamp Counter. */
382	#define X86_CPUID_AMD_FEATURE_EDX_TSC BIT(4)
383	/** Bit 5 - MSR - K86 Model Specific Registers RDMSR and WRMSR Instructions. */
384	#define X86_CPUID_AMD_FEATURE_EDX_MSR BIT(5)
385	/** Bit 6 - PAE - Physical Address Extension. */
386	#define X86_CPUID_AMD_FEATURE_EDX_PAE BIT(6)
387	/** Bit 7 - MCE - Machine Check Exception. */
388	#define X86_CPUID_AMD_FEATURE_EDX_MCE BIT(7)
389	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
390	#define X86_CPUID_AMD_FEATURE_EDX_CX8 BIT(8)
391	/** Bit 9 - APIC - APIC On-Chip. */
392	#define X86_CPUID_AMD_FEATURE_EDX_APIC BIT(9)
393	/** Bit 11 - SEP - AMD SYSCALL and SYSRET. */
394	#define X86_CPUID_AMD_FEATURE_EDX_SEP BIT(11)
395	/** Bit 12 - MTRR - Memory Type Range Registers. */
396	#define X86_CPUID_AMD_FEATURE_EDX_MTRR BIT(12)
397	/** Bit 13 - PGE - PTE Global Bit. */
398	#define X86_CPUID_AMD_FEATURE_EDX_PGE BIT(13)
399	/** Bit 14 - MCA - Machine Check Architecture. */
400	#define X86_CPUID_AMD_FEATURE_EDX_MCA BIT(14)
401	/** Bit 15 - CMOV - Conditional Move Instructions. */
402	#define X86_CPUID_AMD_FEATURE_EDX_CMOV BIT(15)
403	/** Bit 16 - PAT - Page Attribute Table. */
404	#define X86_CPUID_AMD_FEATURE_EDX_PAT BIT(16)
405	/** Bit 17 - PSE-36 - 36-bit Page Size Extention. */
406	#define X86_CPUID_AMD_FEATURE_EDX_PSE36 BIT(17)
407	/** Bit 20 - NX - AMD No-Execute Page Protection. */
408	#define X86_CPUID_AMD_FEATURE_EDX_NX BIT(20)
409	/** Bit 22 - AXMMX - AMD Extensions to MMX Instructions. */
410	#define X86_CPUID_AMD_FEATURE_EDX_AXMMX BIT(22)
411	/** Bit 23 - MMX - Intel MMX Technology. */
412	#define X86_CPUID_AMD_FEATURE_EDX_MMX BIT(23)
413	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
414	#define X86_CPUID_AMD_FEATURE_EDX_FXSR BIT(24)
415	/** Bit 25 - ???? - AMD fast FXSAVE and FXRSTOR Instructions. */
416	#define X86_CPUID_AMD_FEATURE_EDX_FFXSR BIT(25)
417	/** Bit 29 - ???? - AMD Long Mode. */
418	#define X86_CPUID_AMD_FEATURE_EDX_LONG_MODE BIT(29)
419	/** Bit 30 - ???? - AMD Extensions to 3DNow. */
420	#define X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX BIT(30)
421	/** Bit 31 - ???? - AMD 3DNow. */
422	#define X86_CPUID_AMD_FEATURE_EDX_3DNOW BIT(31)
423
424	/** Bit 1 - LAHF/SAHF - ???. */
425	/define X86_CPUID_AMD_FEATURE_ECX_TODO BIT(0)/
426	/** Bit 1 - CMPL - ???. */
427	#define X86_CPUID_AMD_FEATURE_ECX_CMPL BIT(1)
428	/** Bit 2 - SVM - AMD VM extensions. */
429	#define X86_CPUID_AMD_FEATURE_ECX_SVM BIT(2)
430	/** Bit 4 - CR8L - ???. */
431	#define X86_CPUID_AMD_FEATURE_ECX_CR8L BIT(4)
432
433	/** @} */
434
435
436	/** @name CR0
437	* @{ */
438	/** Bit 0 - PE - Protection Enabled */
439	#define X86_CR0_PE BIT(0)
440	#define X86_CR0_PROTECTION_ENABLE BIT(0)
441	/** Bit 1 - MP - Monitor Coprocessor */
442	#define X86_CR0_MP BIT(1)
443	#define X86_CR0_MONITOR_COPROCESSOR BIT(1)
444	/** Bit 2 - EM - Emulation. */
445	#define X86_CR0_EM BIT(2)
446	#define X86_CR0_EMULATE_FPU BIT(2)
447	/** Bit 3 - TS - Task Switch. */
448	#define X86_CR0_TS BIT(3)
449	#define X86_CR0_TASK_SWITCH BIT(3)
450	/** Bit 4 - ET - Extension flag. ('hardcoded' to 1) */
451	#define X86_CR0_ET BIT(4)
452	#define X86_CR0_EXTENSION_TYPE BIT(4)
453	/** Bit 5 - NE - Numeric error. */
454	#define X86_CR0_NE BIT(5)
455	#define X86_CR0_NUMERIC_ERROR BIT(5)
456	/** Bit 16 - WP - Write Protect. */
457	#define X86_CR0_WP BIT(16)
458	#define X86_CR0_WRITE_PROTECT BIT(16)
459	/** Bit 18 - AM - Alignment Mask. */
460	#define X86_CR0_AM BIT(18)
461	#define X86_CR0_ALIGMENT_MASK BIT(18)
462	/** Bit 29 - NW - Not Write-though. */
463	#define X86_CR0_NW BIT(29)
464	#define X86_CR0_NOT_WRITE_THROUGH BIT(29)
465	/** Bit 30 - WP - Cache Disable. */
466	#define X86_CR0_CD BIT(30)
467	#define X86_CR0_CACHE_DISABLE BIT(30)
468	/** Bit 31 - PG - Paging. */
469	#define X86_CR0_PG BIT(31)
470	#define X86_CR0_PAGING BIT(31)
471	/** @} */
472
473
474	/** @name CR3
475	* @{ */
476	/** Bit 3 - PWT - Page-level Writes Transparent. */
477	#define X86_CR3_PWT BIT(3)
478	/** Bit 4 - PCD - Page-level Cache Disable. */
479	#define X86_CR3_PCD BIT(4)
480	/** Bits 12-31 - - Page directory page number. */
481	#define X86_CR3_PAGE_MASK (0xfffff000)
482	/** Bits 5-31 - - PAE Page directory page number. */
483	#define X86_CR3_PAE_PAGE_MASK (0xffffffe0)
484	/** @} */
485
486
487	/** @name CR4
488	* @{ */
489	/** Bit 0 - VME - Virtual-8086 Mode Extensions. */
490	#define X86_CR4_VME BIT(0)
491	/** Bit 1 - PVI - Protected-Mode Virtual Interrupts. */
492	#define X86_CR4_PVI BIT(1)
493	/** Bit 2 - TSD - Time Stamp Disable. */
494	#define X86_CR4_TSD BIT(2)
495	/** Bit 3 - DE - Debugging Extensions. */
496	#define X86_CR4_DE BIT(3)
497	/** Bit 4 - PSE - Page Size Extension. */
498	#define X86_CR4_PSE BIT(4)
499	/** Bit 5 - PAE - Physical Address Extension. */
500	#define X86_CR4_PAE BIT(5)
501	/** Bit 6 - MCE - Machine-Check Enable. */
502	#define X86_CR4_MCE BIT(6)
503	/** Bit 7 - PGE - Page Global Enable. */
504	#define X86_CR4_PGE BIT(7)
505	/** Bit 8 - PCE - Performance-Monitoring Counter Enable. */
506	#define X86_CR4_PCE BIT(8)
507	/** Bit 9 - OSFSXR - Operating System Support for FXSAVE and FXRSTORE instruction. */
508	#define X86_CR4_OSFSXR BIT(9)
509	/** Bit 10 - OSXMMEEXCPT - Operating System Support for Unmasked SIMD Floating-Point Exceptions. */
510	#define X86_CR4_OSXMMEEXCPT BIT(10)
511	/** Bit 13 - VMXE - VMX mode is enabled. */
512	#define X86_CR4_VMXE BIT(13)
513	/** @} */
514
515
516	/** @name DR6
517	* @{ */
518	/** Bit 0 - B0 - Breakpoint 0 condition detected. */
519	#define X86_DR6_B0 BIT(0)
520	/** Bit 1 - B1 - Breakpoint 1 condition detected. */
521	#define X86_DR6_B1 BIT(1)
522	/** Bit 2 - B2 - Breakpoint 2 condition detected. */
523	#define X86_DR6_B2 BIT(2)
524	/** Bit 3 - B3 - Breakpoint 3 condition detected. */
525	#define X86_DR6_B3 BIT(3)
526	/** Bit 13 - BD - Debug register access detected. Corresponds to the X86_DR7_GD bit. */
527	#define X86_DR6_BD BIT(13)
528	/** Bit 14 - BS - Single step */
529	#define X86_DR6_BS BIT(14)
530	/** Bit 15 - BT - Task switch. (TSS T bit.) */
531	#define X86_DR6_BT BIT(15)
532	/** @} */
533
534
535	/** @name DR7
536	* @{ */
537	/** Bit 0 - L0 - Local breakpoint enable. Cleared on task switch. */
538	#define X86_DR7_L0 BIT(0)
539	/** Bit 1 - G0 - Global breakpoint enable. Not cleared on task switch. */
540	#define X86_DR7_G0 BIT(1)
541	/** Bit 2 - L1 - Local breakpoint enable. Cleared on task switch. */
542	#define X86_DR7_L1 BIT(2)
543	/** Bit 3 - G1 - Global breakpoint enable. Not cleared on task switch. */
544	#define X86_DR7_G1 BIT(3)
545	/** Bit 4 - L2 - Local breakpoint enable. Cleared on task switch. */
546	#define X86_DR7_L2 BIT(4)
547	/** Bit 5 - G2 - Global breakpoint enable. Not cleared on task switch. */
548	#define X86_DR7_G2 BIT(5)
549	/** Bit 6 - L3 - Local breakpoint enable. Cleared on task switch. */
550	#define X86_DR7_L3 BIT(6)
551	/** Bit 7 - G3 - Global breakpoint enable. Not cleared on task switch. */
552	#define X86_DR7_G3 BIT(7)
553	/** Bit 8 - LE - Local breakpoint exact. (Not supported (read ignored) by P6 and later.) */
554	#define X86_DR7_LE BIT(8)
555	/** Bit 9 - GE - Local breakpoint exact. (Not supported (read ignored) by P6 and later.) */
556	#define X86_DR7_GE BIT(9)
557
558	/** Bit 13 - GD - General detect enable. Enables emulators to get exceptions when
559	* any DR register is accessed. */
560	#define X86_DR7_GD BIT(13)
561	/** Bit 16 & 17 - R/W0 - Read write field 0. Values X86_DR7_RW_. /
562	#define X86_DR7_RW0_MASK (3 << 16)
563	/** Bit 18 & 19 - LEN0 - Length field 0. Values X86_DR7_LEN_. /
564	#define X86_DR7_LEN0_MASK (3 << 18)
565	/** Bit 20 & 21 - R/W1 - Read write field 0. Values X86_DR7_RW_. /
566	#define X86_DR7_RW1_MASK (3 << 20)
567	/** Bit 22 & 23 - LEN1 - Length field 0. Values X86_DR7_LEN_. /
568	#define X86_DR7_LEN1_MASK (3 << 22)
569	/** Bit 24 & 25 - R/W2 - Read write field 0. Values X86_DR7_RW_. /
570	#define X86_DR7_RW2_MASK (3 << 24)
571	/** Bit 26 & 27 - LEN2 - Length field 0. Values X86_DR7_LEN_. /
572	#define X86_DR7_LEN2_MASK (3 << 26)
573	/** Bit 28 & 29 - R/W3 - Read write field 0. Values X86_DR7_RW_. /
574	#define X86_DR7_RW3_MASK (3 << 28)
575	/** Bit 30 & 31 - LEN3 - Length field 0. Values X86_DR7_LEN_. /
576	#define X86_DR7_LEN3_MASK (3 << 30)
577
578	/** Bits which must be 1s. */
579	#define X86_DR7_MB1_MASK (BIT(10))
580
581	/** Calcs the L bit of Nth breakpoint.
582	* @param iBp The breakpoint number [0..3].
583	*/
584	#define X86_DR7_L(iBp) ( 1 << (iBp * 2) )
585
586	/** Calcs the G bit of Nth breakpoint.
587	* @param iBp The breakpoint number [0..3].
588	*/
589	#define X86_DR7_G(iBp) ( 1 << (iBp * 2 + 1) )
590
591	/** @name Read/Write values.
592	* @{ */
593	/** Break on instruction fetch only. */
594	#define X86_DR7_RW_EO 0
595	/** Break on write only. */
596	#define X86_DR7_RW_WO 1
597	/** Break on I/O read/write. This is only defined if CR4.DE is set. */
598	#define X86_DR7_RW_IO 2
599	/** Break on read or write (but not instruction fetches). */
600	#define X86_DR7_RW_RW 3
601	/** @} */
602
603	/** Shifts a X86_DR7_RW_* value to its right place.
604	* @param iBp The breakpoint number [0..3].
605	* @param fRw One of the X86_DR7_RW_* value.
606	*/
607	#define X86_DR7_RW(iBp, fRw) ( (fRw) << ((iBp) * 4 + 16) )
608
609	/** @name Length values.
610	* @{ */
611	#define X86_DR7_LEN_BYTE 0
612	#define X86_DR7_LEN_WORD 1
613	#define X86_DR7_LEN_QWORD 2 /*< AMD64 long mode only. /
614	#define X86_DR7_LEN_DWORD 3
615	/** @} */
616
617	/** Shifts a X86_DR7_LEN_* value to its right place.
618	* @param iBp The breakpoint number [0..3].
619	* @param cb One of the X86_DR7_LEN_* values.
620	*/
621	#define X86_DR7_LEN(iBp, cb) ( (cb) << ((iBp) * 4 + 18) )
622
623	/** Mask used to check if any breakpoints are enabled. */
624	#define X86_DR7_ENABLED_MASK (BIT(0) \| BIT(1) \| BIT(2) \| BIT(3) \| BIT(4) \| BIT(6) \| BIT(7))
625
626	/** @} */
627
628
629	/** @name Machine Specific Registers
630	* @{
631	*/
632	/** CPU Feature control. */
633	#define MSR_IA32_FEATURE_CONTROL 0x3A
634	#define MSR_IA32_FEATURE_CONTROL_LOCK BIT(0)
635	#define MSR_IA32_FEATURE_CONTROL_VMXON BIT(2)
636
637
638	#ifndef MSR_IA32_SYSENTER_CS /* qemu cpu.h klugde */
639	/** SYSENTER_CS - the R0 CS, indirectly giving R0 SS, R3 CS and R3 DS.
640	* R0 SS == CS + 8
641	* R3 CS == CS + 16
642	* R3 SS == CS + 24
643	*/
644	#define MSR_IA32_SYSENTER_CS 0x174
645	/** SYSENTER_ESP - the R0 ESP. */
646	#define MSR_IA32_SYSENTER_ESP 0x175
647	/** SYSENTER_EIP - the R0 EIP. */
648	#define MSR_IA32_SYSENTER_EIP 0x176
649	#endif
650
651	/** Basic VMX information. */
652	#define MSR_IA32_VMX_BASIC_INFO 0x480
653	/** Allowed settings for pin-based VM execution controls */
654	#define MSR_IA32_VMX_PINBASED_CTLS 0x481
655	/** Allowed settings for proc-based VM execution controls */
656	#define MSR_IA32_VMX_PROCBASED_CTLS 0x482
657	/** Allowed settings for the VMX exit controls. */
658	#define MSR_IA32_VMX_EXIT_CTLS 0x483
659	/** Allowed settings for the VMX entry controls. */
660	#define MSR_IA32_VMX_ENTRY_CTLS 0x484
661	/** Misc VMX info. */
662	#define MSR_IA32_VMX_MISC 0x485
663	/** Fixed cleared bits in CR0. */
664	#define MSR_IA32_VMX_CR0_FIXED0 0x486
665	/** Fixed set bits in CR0. */
666	#define MSR_IA32_VMX_CR0_FIXED1 0x487
667	/** Fixed cleared bits in CR4. */
668	#define MSR_IA32_VMX_CR4_FIXED0 0x488
669	/** Fixed set bits in CR4. */
670	#define MSR_IA32_VMX_CR4_FIXED1 0x489
671	/** Information for enumerating fields in the VMCS. */
672	#define MSR_IA32_VMX_VMCS_ENUM 0x48A
673
674
675	/** K6 EFER - Extended Feature Enable Register. */
676	#define MSR_K6_EFER 0xc0000080
677	/** @todo document EFER */
678	/** Bit 0 - SCE - System call extensions (SYSCALL / SYSRET). (R/W) */
679	#define MSR_K6_EFER_SCE BIT(0)
680	/** Bit 8 - LME - Long mode enabled. (R/W) */
681	#define MSR_K6_EFER_LME BIT(8)
682	/** Bit 10 - LMA - Long mode active. (R) */
683	#define MSR_K6_EFER_LMA BIT(10)
684	/** Bit 11 - NXE - No-Execute Page Protection Enabled. (R/W) */
685	#define MSR_K6_EFER_NXE BIT(11)
686	/** Bit 12 - SVME - Secure VM Extension Enabled. (R/W) */
687	#define MSR_K6_EFER_SVME BIT(12)
688	/** Bit 13 - LMSLE - Long Mode Segment Limit Enable. (R/W?) */
689	#define MSR_K6_EFER_LMSLE BIT(13)
690	/** Bit 14 - FFXSR - Fast FXSAVE / FXRSTOR (skip XMM). (R/W) /
691	#define MSR_K6_EFER_FFXSR BIT(14)
692	/** K6 STAR - SYSCALL/RET targets. */
693	#define MSR_K6_STAR 0xc0000081
694	/** Shift value for getting the SYSRET CS and SS value. */
695	#define MSR_K6_STAR_SYSRET_CS_SS_SHIFT 48
696	/** Shift value for getting the SYSCALL CS and SS value. */
697	#define MSR_K6_STAR_SYSCALL_CS_SS_SHIFT 32
698	/** Selector mask for use after shifting. */
699	#define MSR_K6_STAR_SEL_MASK 0xffff
700	/** The mask which give the SYSCALL EIP. */
701	#define MSR_K6_STAR_SYSCALL_EIP_MASK 0xffffffff
702	/** K6 WHCR - Write Handling Control Register. */
703	#define MSR_K6_WHCR 0xc0000082
704	/** K6 UWCCR - UC/WC Cacheability Control Register. */
705	#define MSR_K6_UWCCR 0xc0000085
706	/** K6 PSOR - Processor State Observability Register. */
707	#define MSR_K6_PSOR 0xc0000087
708	/** K6 PFIR - Page Flush/Invalidate Register. */
709	#define MSR_K6_PFIR 0xc0000088
710
711	#define MSR_K7_EVNTSEL0 0xc0010000
712	#define MSR_K7_EVNTSEL1 0xc0010001
713	#define MSR_K7_EVNTSEL2 0xc0010002
714	#define MSR_K7_EVNTSEL3 0xc0010003
715	#define MSR_K7_PERFCTR0 0xc0010004
716	#define MSR_K7_PERFCTR1 0xc0010005
717	#define MSR_K7_PERFCTR2 0xc0010006
718	#define MSR_K7_PERFCTR3 0xc0010007
719
720	/** K8 LSTAR - Long mode SYSCALL target (RIP). */
721	#define MSR_K8_LSTAR 0xc0000082
722	/** K8 CSTAR - Compatibility mode SYSCALL target (RIP). */
723	#define MSR_K8_CSTAR 0xc0000083
724	/** K8 SF_MASK - SYSCALL flag mask. (aka SFMASK) */
725	#define MSR_K8_SF_MASK 0xc0000084
726	/** K8 FS.base - The 64-bit base FS register. */
727	#define MSR_K8_FS_BASE 0xc0000100
728	/** K8 GS.base - The 64-bit base GS register. */
729	#define MSR_K8_GS_BASE 0xc0000101
730	/** K8 KernelGSbase - Used with SWAPGS. */
731	#define MSR_K8_KERNEL_GS_BASE 0xc0000102
732	#define MSR_K8_TSC_AUX 0xc0000103
733	#define MSR_K8_SYSCFG 0xc0010010
734	#define MSR_K8_HWCR 0xc0010015
735	#define MSR_K8_IORRBASE0 0xc0010016
736	#define MSR_K8_IORRMASK0 0xc0010017
737	#define MSR_K8_IORRBASE1 0xc0010018
738	#define MSR_K8_IORRMASK1 0xc0010019
739	#define MSR_K8_TOP_MEM1 0xc001001a
740	#define MSR_K8_TOP_MEM2 0xc001001d
741	#define MSR_K8_VM_CR 0xc0010114
742	#define MSR_K8_VM_CR_SVM_DISABLE BIT(4)
743
744	#define MSR_K8_IGNNE 0xc0010115
745	#define MSR_K8_SMM_CTL 0xc0010116
746	/** SVM - VM_HSAVE_PA - Physical address for saving and restoring
747	* host state during world switch.
748	*/
749	#define MSR_K8_VM_HSAVE_PA 0xc0010117
750
751	/** @} */
752
753
754	/** @name Page Table / Directory / Directory Pointers / L4.
755	* @{
756	*/
757
758	/** Page table/directory entry as an unsigned integer. */
759	typedef uint32_t X86PGUINT;
760	/** Pointer to a page table/directory table entry as an unsigned integer. */
761	typedef X86PGUINT *PX86PGUINT;
762
763	/** Number of entries in a 32-bit PT/PD. */
764	#define X86_PG_ENTRIES 1024
765
766
767	/** PAE page table/page directory/pdptr/l4/l5 entry as an unsigned integer. */
768	typedef uint64_t X86PGPAEUINT;
769	/** Pointer to a PAE page table/page directory/pdptr/l4/l5 entry as an unsigned integer. */
770	typedef X86PGPAEUINT *PX86PGPAEUINT;
771
772	/** Number of entries in a PAE PT/PD/PDPTR/L4/L5. */
773	#define X86_PG_PAE_ENTRIES 512
774
775
776	/** The size of a 4KB page. */
777	#define X86_PAGE_4K_SIZE _4K
778	/** The page shift of a 4KB page. */
779	#define X86_PAGE_4K_SHIFT 12
780	/** The 4KB page offset mask. */
781	#define X86_PAGE_4K_OFFSET_MASK 0xfff
782	/** The 4KB page base mask for virtual addresses. */
783	#define X86_PAGE_4K_BASE_MASK 0xfffffffffffff000ULL
784	/** The 4KB page base mask for virtual addresses - 32bit version. */
785	#define X86_PAGE_4K_BASE_MASK_32 0xfffff000U
786
787	/** The size of a 2MB page. */
788	#define X86_PAGE_2M_SIZE _2M
789	/** The page shift of a 2MB page. */
790	#define X86_PAGE_2M_SHIFT 21
791	/** The 2MB page offset mask. */
792	#define X86_PAGE_2M_OFFSET_MASK 0x001fffff
793	/** The 2MB page base mask for virtual addresses. */
794	#define X86_PAGE_2M_BASE_MASK 0xffffffffffe00000ULL
795	/** The 2MB page base mask for virtual addresses - 32bit version. */
796	#define X86_PAGE_2M_BASE_MASK_32 0xffe00000U
797
798	/** The size of a 4MB page. */
799	#define X86_PAGE_4M_SIZE _4M
800	/** The page shift of a 4MB page. */
801	#define X86_PAGE_4M_SHIFT 22
802	/** The 4MB page offset mask. */
803	#define X86_PAGE_4M_OFFSET_MASK 0x003fffff
804	/** The 4MB page base mask for virtual addresses. */
805	#define X86_PAGE_4M_BASE_MASK 0xffffffffffc00000ULL
806	/** The 4MB page base mask for virtual addresses - 32bit version. */
807	#define X86_PAGE_4M_BASE_MASK_32 0xffc00000U
808
809
810
811	/** @name Page Table Entry
812	* @{
813	*/
814	/** Bit 0 - P - Present bit. */
815	#define X86_PTE_P BIT(0)
816	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
817	#define X86_PTE_RW BIT(1)
818	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
819	#define X86_PTE_US BIT(2)
820	/** Bit 3 - PWT - Page level write thru bit. */
821	#define X86_PTE_PWT BIT(3)
822	/** Bit 4 - PCD - Page level cache disable bit. */
823	#define X86_PTE_PCD BIT(4)
824	/** Bit 5 - A - Access bit. */
825	#define X86_PTE_A BIT(5)
826	/** Bit 6 - D - Dirty bit. */
827	#define X86_PTE_D BIT(6)
828	/** Bit 7 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
829	#define X86_PTE_PAT BIT(7)
830	/** Bit 8 - G - Global flag. */
831	#define X86_PTE_G BIT(8)
832	/** Bits 9-11 - - Available for use to system software. */
833	#define X86_PTE_AVL_MASK (BIT(9) \| BIT(10) \| BIT(11))
834	/** Bits 12-31 - - Physical Page number of the next level. */
835	#define X86_PTE_PG_MASK ( 0xfffff000 )
836
837	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
838	#if 1 /* we're using this internally and have to mask of the top 16-bit. */
839	#define X86_PTE_PAE_PG_MASK ( 0x0000fffffffff000ULL )
840	#else
841	#define X86_PTE_PAE_PG_MASK ( 0x000ffffffffff000ULL )
842	#endif
843	/** Bits 63 - NX - PAE - No execution flag. */
844	#define X86_PTE_PAE_NX BIT64(63)
845
846	/**
847	* Page table entry.
848	*/
849	typedef struct X86PTEBITS
850	{
851	/** Flags whether(=1) or not the page is present. */
852	unsigned u1Present : 1;
853	/** Read(=0) / Write(=1) flag. */
854	unsigned u1Write : 1;
855	/** User(=1) / Supervisor (=0) flag. */
856	unsigned u1User : 1;
857	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
858	unsigned u1WriteThru : 1;
859	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
860	unsigned u1CacheDisable : 1;
861	/** Accessed flag.
862	* Indicates that the page have been read or written to. */
863	unsigned u1Accessed : 1;
864	/** Dirty flag.
865	* Indicates that the page have been written to. */
866	unsigned u1Dirty : 1;
867	/** Reserved / If PAT enabled, bit 2 of the index. */
868	unsigned u1PAT : 1;
869	/** Global flag. (Ignored in all but final level.) */
870	unsigned u1Global : 1;
871	/** Available for use to system software. */
872	unsigned u3Available : 3;
873	/** Physical Page number of the next level. */
874	unsigned u20PageNo : 20;
875	} X86PTEBITS;
876	/** Pointer to a page table entry. */
877	typedef X86PTEBITS *PX86PTEBITS;
878	/** Pointer to a const page table entry. */
879	typedef const X86PTEBITS *PCX86PTEBITS;
880
881	/**
882	* Page table entry.
883	*/
884	typedef union X86PTE
885	{
886	/** Bit field view. */
887	X86PTEBITS n;
888	/** Unsigned integer view */
889	X86PGUINT u;
890	/** 32-bit view. */
891	uint32_t au32[1];
892	/** 16-bit view. */
893	uint16_t au16[2];
894	/** 8-bit view. */
895	uint8_t au8[4];
896	} X86PTE;
897	/** Pointer to a page table entry. */
898	typedef X86PTE *PX86PTE;
899	/** Pointer to a const page table entry. */
900	typedef const X86PTE *PCX86PTE;
901
902
903	/**
904	* PAE page table entry.
905	*/
906	typedef struct X86PTEPAEBITS
907	{
908	/** Flags whether(=1) or not the page is present. */
909	uint32_t u1Present : 1;
910	/** Read(=0) / Write(=1) flag. */
911	uint32_t u1Write : 1;
912	/** User(=1) / Supervisor(=0) flag. */
913	uint32_t u1User : 1;
914	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
915	uint32_t u1WriteThru : 1;
916	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
917	uint32_t u1CacheDisable : 1;
918	/** Accessed flag.
919	* Indicates that the page have been read or written to. */
920	uint32_t u1Accessed : 1;
921	/** Dirty flag.
922	* Indicates that the page have been written to. */
923	uint32_t u1Dirty : 1;
924	/** Reserved / If PAT enabled, bit 2 of the index. */
925	uint32_t u1PAT : 1;
926	/** Global flag. (Ignored in all but final level.) */
927	uint32_t u1Global : 1;
928	/** Available for use to system software. */
929	uint32_t u3Available : 3;
930	/** Physical Page number of the next level - Low Part. Don't use this. */
931	uint32_t u20PageNoLow : 20;
932	/** Physical Page number of the next level - High Part. Don't use this. */
933	uint32_t u20PageNoHigh : 20;
934	/** MBZ bits */
935	uint32_t u11Reserved : 11;
936	/** No Execute flag. */
937	uint32_t u1NoExecute : 1;
938	} X86PTEPAEBITS;
939	/** Pointer to a page table entry. */
940	typedef X86PTEPAEBITS *PX86PTEPAEBITS;
941	/** Pointer to a page table entry. */
942	typedef const X86PTEPAEBITS *PCX86PTEPAEBITS;
943
944	/**
945	* PAE Page table entry.
946	*/
947	typedef union X86PTEPAE
948	{
949	/** Bit field view. */
950	X86PTEPAEBITS n;
951	/** Unsigned integer view */
952	X86PGPAEUINT u;
953	/** 32-bit view. */
954	uint32_t au32[2];
955	/** 16-bit view. */
956	uint16_t au16[4];
957	/** 8-bit view. */
958	uint8_t au8[8];
959	} X86PTEPAE;
960	/** Pointer to a PAE page table entry. */
961	typedef X86PTEPAE *PX86PTEPAE;
962	/** Pointer to a const PAE page table entry. */
963	typedef const X86PTEPAE *PCX86PTEPAE;
964	/** @} */
965
966	/**
967	* Page table.
968	*/
969	typedef struct X86PT
970	{
971	/** PTE Array. */
972	X86PTE a[X86_PG_ENTRIES];
973	} X86PT;
974	/** Pointer to a page table. */
975	typedef X86PT *PX86PT;
976	/** Pointer to a const page table. */
977	typedef const X86PT *PCX86PT;
978
979	/** The page shift to get the PT index. */
980	#define X86_PT_SHIFT 12
981	/** The PT index mask (apply to a shifted page address). */
982	#define X86_PT_MASK 0x3ff
983
984
985	/**
986	* Page directory.
987	*/
988	typedef struct X86PTPAE
989	{
990	/** PTE Array. */
991	X86PTEPAE a[X86_PG_PAE_ENTRIES];
992	} X86PTPAE;
993	/** Pointer to a page table. */
994	typedef X86PTPAE *PX86PTPAE;
995	/** Pointer to a const page table. */
996	typedef const X86PTPAE *PCX86PTPAE;
997
998	/** The page shift to get the PA PTE index. */
999	#define X86_PT_PAE_SHIFT 12
1000	/** The PAE PT index mask (apply to a shifted page address). */
1001	#define X86_PT_PAE_MASK 0x1ff
1002
1003
1004	/** @name 4KB Page Directory Entry
1005	* @{
1006	*/
1007	/** Bit 0 - P - Present bit. */
1008	#define X86_PDE_P BIT(0)
1009	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1010	#define X86_PDE_RW BIT(1)
1011	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1012	#define X86_PDE_US BIT(2)
1013	/** Bit 3 - PWT - Page level write thru bit. */
1014	#define X86_PDE_PWT BIT(3)
1015	/** Bit 4 - PCD - Page level cache disable bit. */
1016	#define X86_PDE_PCD BIT(4)
1017	/** Bit 5 - A - Access bit. */
1018	#define X86_PDE_A BIT(5)
1019	/** Bit 7 - PS - Page size attribute.
1020	* Clear mean 4KB pages, set means large pages (2/4MB). */
1021	#define X86_PDE_PS BIT(7)
1022	/** Bits 9-11 - - Available for use to system software. */
1023	#define X86_PDE_AVL_MASK (BIT(9) \| BIT(10) \| BIT(11))
1024	/** Bits 12-31 - - Physical Page number of the next level. */
1025	#define X86_PDE_PG_MASK ( 0xfffff000 )
1026
1027	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1028	#if 1 /* we're using this internally and have to mask of the top 16-bit. */
1029	#define X86_PDE_PAE_PG_MASK ( 0x0000fffffffff000ULL )
1030	#else
1031	#define X86_PDE_PAE_PG_MASK ( 0x000ffffffffff000ULL )
1032	#endif
1033	/** Bits 63 - NX - PAE - No execution flag. */
1034	#define X86_PDE_PAE_NX BIT64(63)
1035
1036	/**
1037	* Page directory entry.
1038	*/
1039	typedef struct X86PDEBITS
1040	{
1041	/** Flags whether(=1) or not the page is present. */
1042	unsigned u1Present : 1;
1043	/** Read(=0) / Write(=1) flag. */
1044	unsigned u1Write : 1;
1045	/** User(=1) / Supervisor (=0) flag. */
1046	unsigned u1User : 1;
1047	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1048	unsigned u1WriteThru : 1;
1049	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1050	unsigned u1CacheDisable : 1;
1051	/** Accessed flag.
1052	* Indicates that the page have been read or written to. */
1053	unsigned u1Accessed : 1;
1054	/** Reserved / Ignored (dirty bit). */
1055	unsigned u1Reserved0 : 1;
1056	/** Size bit if PSE is enabled - in any event it's 0. */
1057	unsigned u1Size : 1;
1058	/** Reserved / Ignored (global bit). */
1059	unsigned u1Reserved1 : 1;
1060	/** Available for use to system software. */
1061	unsigned u3Available : 3;
1062	/** Physical Page number of the next level. */
1063	unsigned u20PageNo : 20;
1064	} X86PDEBITS;
1065	/** Pointer to a page directory entry. */
1066	typedef X86PDEBITS *PX86PDEBITS;
1067	/** Pointer to a const page directory entry. */
1068	typedef const X86PDEBITS *PCX86PDEBITS;
1069
1070
1071	/**
1072	* PAE page directory entry.
1073	*/
1074	typedef struct X86PDEPAEBITS
1075	{
1076	/** Flags whether(=1) or not the page is present. */
1077	uint32_t u1Present : 1;
1078	/** Read(=0) / Write(=1) flag. */
1079	uint32_t u1Write : 1;
1080	/** User(=1) / Supervisor (=0) flag. */
1081	uint32_t u1User : 1;
1082	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1083	uint32_t u1WriteThru : 1;
1084	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1085	uint32_t u1CacheDisable : 1;
1086	/** Accessed flag.
1087	* Indicates that the page have been read or written to. */
1088	uint32_t u1Accessed : 1;
1089	/** Reserved / Ignored (dirty bit). */
1090	uint32_t u1Reserved0 : 1;
1091	/** Size bit if PSE is enabled - in any event it's 0. */
1092	uint32_t u1Size : 1;
1093	/** Reserved / Ignored (global bit). / */
1094	uint32_t u1Reserved1 : 1;
1095	/** Available for use to system software. */
1096	uint32_t u3Available : 3;
1097	/** Physical Page number of the next level - Low Part. Don't use! */
1098	uint32_t u20PageNoLow : 20;
1099	/** Physical Page number of the next level - High Part. Don't use! */
1100	uint32_t u20PageNoHigh : 20;
1101	/** MBZ bits */
1102	uint32_t u11Reserved : 11;
1103	/** No Execute flag. */
1104	uint32_t u1NoExecute : 1;
1105	} X86PDEPAEBITS;
1106	/** Pointer to a page directory entry. */
1107	typedef X86PDEPAEBITS *PX86PDEPAEBITS;
1108	/** Pointer to a const page directory entry. */
1109	typedef const X86PDEPAEBITS *PCX86PDEPAEBITS;
1110
1111	/** @} */
1112
1113
1114	/** @name 2/4MB Page Directory Entry
1115	* @{
1116	*/
1117	/** Bit 0 - P - Present bit. */
1118	#define X86_PDE4M_P BIT(0)
1119	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1120	#define X86_PDE4M_RW BIT(1)
1121	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1122	#define X86_PDE4M_US BIT(2)
1123	/** Bit 3 - PWT - Page level write thru bit. */
1124	#define X86_PDE4M_PWT BIT(3)
1125	/** Bit 4 - PCD - Page level cache disable bit. */
1126	#define X86_PDE4M_PCD BIT(4)
1127	/** Bit 5 - A - Access bit. */
1128	#define X86_PDE4M_A BIT(5)
1129	/** Bit 6 - D - Dirty bit. */
1130	#define X86_PDE4M_D BIT(6)
1131	/** Bit 7 - PS - Page size attribute. Clear mean 4KB pages, set means large pages (2/4MB). */
1132	#define X86_PDE4M_PS BIT(7)
1133	/** Bit 8 - G - Global flag. */
1134	#define X86_PDE4M_G BIT(8)
1135	/** Bits 9-11 - AVL - Available for use to system software. */
1136	#define X86_PDE4M_AVL (BIT(9) \| BIT(10) \| BIT(11))
1137	/** Bit 12 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
1138	#define X86_PDE4M_PAT BIT(12)
1139	/** Shift to get from X86_PTE_PAT to X86_PDE4M_PAT. */
1140	#define X86_PDE4M_PAT_SHIFT (12 - 7)
1141	/** Bits 22-31 - - Physical Page number. */
1142	#define X86_PDE4M_PG_MASK ( 0xffc00000 )
1143	/** Bits 13-20 - - Physical Page number high part (32-39 bits). AMD64 hack. */
1144	#define X86_PDE4M_PG_HIGH_MASK ( 0x001fe000 )
1145	/** The number of bits to the high part of the page number. */
1146	#define X86_PDE4M_PG_HIGH_SHIFT 19
1147
1148	/** Bits 12-51 - - PAE - Physical Page number. */
1149	#define X86_PDE4M_PAE_PG_MASK ( 0x000fffffffc00000ULL )
1150	/** Bits 63 - NX - PAE - No execution flag. */
1151	#define X86_PDE4M_PAE_NX BIT64(63)
1152
1153	/**
1154	* 4MB page directory entry.
1155	*/
1156	typedef struct X86PDE4MBITS
1157	{
1158	/** Flags whether(=1) or not the page is present. */
1159	unsigned u1Present : 1;
1160	/** Read(=0) / Write(=1) flag. */
1161	unsigned u1Write : 1;
1162	/** User(=1) / Supervisor (=0) flag. */
1163	unsigned u1User : 1;
1164	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1165	unsigned u1WriteThru : 1;
1166	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1167	unsigned u1CacheDisable : 1;
1168	/** Accessed flag.
1169	* Indicates that the page have been read or written to. */
1170	unsigned u1Accessed : 1;
1171	/** Dirty flag.
1172	* Indicates that the page have been written to. */
1173	unsigned u1Dirty : 1;
1174	/** Page size flag - always 1 for 4MB entries. */
1175	unsigned u1Size : 1;
1176	/** Global flag. */
1177	unsigned u1Global : 1;
1178	/** Available for use to system software. */
1179	unsigned u3Available : 3;
1180	/** Reserved / If PAT enabled, bit 2 of the index. */
1181	unsigned u1PAT : 1;
1182	/** Bits 32-39 of the page number on AMD64.
1183	* This AMD64 hack allows accessing 40bits of physical memory without PAE. */
1184	unsigned u8PageNoHigh : 8;
1185	/** Reserved. */
1186	unsigned u1Reserved : 1;
1187	/** Physical Page number of the page. */
1188	unsigned u10PageNo : 10;
1189	} X86PDE4MBITS;
1190	/** Pointer to a page table entry. */
1191	typedef X86PDE4MBITS *PX86PDE4MBITS;
1192	/** Pointer to a const page table entry. */
1193	typedef const X86PDE4MBITS *PCX86PDE4MBITS;
1194
1195
1196	/**
1197	* 2MB PAE page directory entry.
1198	*/
1199	typedef struct X86PDE2MPAEBITS
1200	{
1201	/** Flags whether(=1) or not the page is present. */
1202	uint32_t u1Present : 1;
1203	/** Read(=0) / Write(=1) flag. */
1204	uint32_t u1Write : 1;
1205	/** User(=1) / Supervisor(=0) flag. */
1206	uint32_t u1User : 1;
1207	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1208	uint32_t u1WriteThru : 1;
1209	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1210	uint32_t u1CacheDisable : 1;
1211	/** Accessed flag.
1212	* Indicates that the page have been read or written to. */
1213	uint32_t u1Accessed : 1;
1214	/** Dirty flag.
1215	* Indicates that the page have been written to. */
1216	uint32_t u1Dirty : 1;
1217	/** Page size flag - always 1 for 2MB entries. */
1218	uint32_t u1Size : 1;
1219	/** Global flag. */
1220	uint32_t u1Global : 1;
1221	/** Available for use to system software. */
1222	uint32_t u3Available : 3;
1223	/** Reserved / If PAT enabled, bit 2 of the index. */
1224	uint32_t u1PAT : 1;
1225	/** Reserved. */
1226	uint32_t u9Reserved : 9;
1227	/** Physical Page number of the next level - Low part. Don't use! */
1228	uint32_t u10PageNoLow : 10;
1229	/** Physical Page number of the next level - High part. Don't use! */
1230	uint32_t u20PageNoHigh : 20;
1231	/** MBZ bits */
1232	uint32_t u11Reserved : 11;
1233	/** No Execute flag. */
1234	uint32_t u1NoExecute : 1;
1235	} X86PDE2MPAEBITS;
1236	/** Pointer to a 4MB PAE page table entry. */
1237	typedef X86PDE2MPAEBITS *PX86PDE2MPAEBITS;
1238	/** Pointer to a 4MB PAE page table entry. */
1239	typedef const X86PDE2MPAEBITS *PCX86PDE2MPAEBITS;
1240
1241	/** @} */
1242
1243	/**
1244	* Page directory entry.
1245	*/
1246	typedef union X86PDE
1247	{
1248	/** Normal view. */
1249	X86PDEBITS n;
1250	/** 4MB view (big). */
1251	X86PDE4MBITS b;
1252	/** Unsigned integer view. */
1253	X86PGUINT u;
1254	/** 8 bit unsigned integer view. */
1255	uint8_t au8[4];
1256	/** 16 bit unsigned integer view. */
1257	uint16_t au16[2];
1258	/** 32 bit unsigned integer view. */
1259	uint32_t au32[1];
1260	} X86PDE;
1261	/** Pointer to a page directory entry. */
1262	typedef X86PDE *PX86PDE;
1263	/** Pointer to a const page directory entry. */
1264	typedef const X86PDE *PCX86PDE;
1265
1266	/**
1267	* PAE page directory entry.
1268	*/
1269	typedef union X86PDEPAE
1270	{
1271	/** Normal view. */
1272	X86PDEPAEBITS n;
1273	/** 2MB page view (big). */
1274	X86PDE2MPAEBITS b;
1275	/** Unsigned integer view. */
1276	X86PGPAEUINT u;
1277	/** 8 bit unsigned integer view. */
1278	uint8_t au8[8];
1279	/** 16 bit unsigned integer view. */
1280	uint16_t au16[4];
1281	/** 32 bit unsigned integer view. */
1282	uint32_t au32[2];
1283	} X86PDEPAE;
1284	/** Pointer to a page directory entry. */
1285	typedef X86PDEPAE *PX86PDEPAE;
1286	/** Pointer to a const page directory entry. */
1287	typedef const X86PDEPAE *PCX86PDEPAE;
1288
1289	/**
1290	* Page directory.
1291	*/
1292	typedef struct X86PD
1293	{
1294	/** PDE Array. */
1295	X86PDE a[X86_PG_ENTRIES];
1296	} X86PD;
1297	/** Pointer to a page directory. */
1298	typedef X86PD *PX86PD;
1299	/** Pointer to a const page directory. */
1300	typedef const X86PD *PCX86PD;
1301
1302	/** The page shift to get the PD index. */
1303	#define X86_PD_SHIFT 22
1304	/** The PD index mask (apply to a shifted page address). */
1305	#define X86_PD_MASK 0x3ff
1306
1307
1308	/**
1309	* PAE page directory.
1310	*/
1311	typedef struct X86PDPAE
1312	{
1313	/** PDE Array. */
1314	X86PDEPAE a[X86_PG_PAE_ENTRIES];
1315	} X86PDPAE;
1316	/** Pointer to a PAE page directory. */
1317	typedef X86PDPAE *PX86PDPAE;
1318	/** Pointer to a const PAE page directory. */
1319	typedef const X86PDPAE *PCX86PDPAE;
1320
1321	/** The page shift to get the PAE PD index. */
1322	#define X86_PD_PAE_SHIFT 21
1323	/** The PAE PD index mask (apply to a shifted page address). */
1324	#define X86_PD_PAE_MASK 0x1ff
1325
1326
1327	/** @name Page Directory Pointer Table Entry (PAE)
1328	* @{
1329	*/
1330	/** Bit 0 - P - Present bit. */
1331	#define X86_PDPE_P BIT(0)
1332	/** Bit 1 - R/W - Read (clear) / Write (set) bit. Long Mode only. */
1333	#define X86_PDPE_RW BIT(1)
1334	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. Long Mode only. */
1335	#define X86_PDPE_US BIT(2)
1336	/** Bit 3 - PWT - Page level write thru bit. */
1337	#define X86_PDPE_PWT BIT(3)
1338	/** Bit 4 - PCD - Page level cache disable bit. */
1339	#define X86_PDPE_PCD BIT(4)
1340	/** Bit 5 - A - Access bit. Long Mode only. */
1341	#define X86_PDPE_A BIT(5)
1342	/** Bits 9-11 - - Available for use to system software. */
1343	#define X86_PDPE_AVL_MASK (BIT(9) \| BIT(10) \| BIT(11))
1344	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1345	#if 1 /* we're using this internally and have to mask of the top 16-bit. */
1346	#define X86_PDPE_PG_MASK ( 0x0000fffffffff000ULL )
1347	#else
1348	#define X86_PDPE_PG_MASK ( 0x000ffffffffff000ULL )
1349	#endif
1350	/** Bits 63 - NX - PAE - No execution flag. */
1351	#define X86_PDPE_NX BIT64(63)
1352
1353	/**
1354	* Page directory pointer table entry.
1355	*/
1356	typedef struct X86PDPEBITS
1357	{
1358	/** Flags whether(=1) or not the page is present. */
1359	uint32_t u1Present : 1;
1360	/** Read(=0) / Write(=1) flag. */
1361	uint32_t u1Write : 1;
1362	/** User(=1) / Supervisor (=0) flag. */
1363	uint32_t u1User : 1;
1364	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1365	uint32_t u1WriteThru : 1;
1366	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1367	uint32_t u1CacheDisable : 1;
1368	/** Accessed flag.
1369	* Indicates that the page have been read or written to. */
1370	uint32_t u1Accessed : 1;
1371	/** Chunk of reserved bits. */
1372	uint32_t u3Reserved : 3;
1373	/** Available for use to system software. */
1374	uint32_t u3Available : 3;
1375	/** Physical Page number of the next level - Low Part. Don't use! */
1376	uint32_t u20PageNoLow : 20;
1377	/** Physical Page number of the next level - High Part. Don't use! */
1378	uint32_t u20PageNoHigh : 20;
1379	/** MBZ bits */
1380	uint32_t u11Reserved : 11;
1381	/** No Execute flag. */
1382	uint32_t u1NoExecute : 1;
1383	} X86PDPEBITS;
1384	/** Pointer to a page directory pointer table entry. */
1385	typedef X86PDPEBITS *PX86PTPEBITS;
1386	/** Pointer to a const page directory pointer table entry. */
1387	typedef const X86PDPEBITS *PCX86PTPEBITS;
1388
1389	/**
1390	* Page directory pointer table entry.
1391	*/
1392	typedef union X86PDPE
1393	{
1394	/** Normal view. */
1395	X86PDPEBITS n;
1396	/** Unsigned integer view. */
1397	X86PGPAEUINT u;
1398	/** 8 bit unsigned integer view. */
1399	uint8_t au8[8];
1400	/** 16 bit unsigned integer view. */
1401	uint16_t au16[4];
1402	/** 32 bit unsigned integer view. */
1403	uint32_t au32[2];
1404	} X86PDPE;
1405	/** Pointer to a page directory pointer table entry. */
1406	typedef X86PDPE *PX86PDPE;
1407	/** Pointer to a const page directory pointer table entry. */
1408	typedef const X86PDPE *PCX86PDPE;
1409
1410
1411	/**
1412	* Page directory pointer table.
1413	*/
1414	typedef struct X86PDPTR
1415	{
1416	/** PDE Array. */
1417	X86PDPE a[X86_PG_PAE_ENTRIES];
1418	} X86PDPTR;
1419	/** Pointer to a page directory pointer table. */
1420	typedef X86PDPTR *PX86PDPTR;
1421	/** Pointer to a const page directory pointer table. */
1422	typedef const X86PDPTR *PCX86PDPTR;
1423
1424	/** The page shift to get the PDPTR index. */
1425	#define X86_PDPTR_SHIFT 30
1426	/** The PDPTR index mask (apply to a shifted page address). (32 bits PAE) */
1427	#define X86_PDPTR_MASK_32 0x3
1428	/** The PDPTR index mask (apply to a shifted page address). (64 bits PAE)*/
1429	#define X86_PDPTR_MASK 0x1ff
1430
1431	/** @} */
1432
1433
1434	/** @name Page Map Level-4 Entry (Long Mode PAE)
1435	* @{
1436	*/
1437	/** Bit 0 - P - Present bit. */
1438	#define X86_PML4E_P BIT(0)
1439	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1440	#define X86_PML4E_RW BIT(1)
1441	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1442	#define X86_PML4E_US BIT(2)
1443	/** Bit 3 - PWT - Page level write thru bit. */
1444	#define X86_PML4E_PWT BIT(3)
1445	/** Bit 4 - PCD - Page level cache disable bit. */
1446	#define X86_PML4E_PCD BIT(4)
1447	/** Bit 5 - A - Access bit. */
1448	#define X86_PML4E_A BIT(5)
1449	/** Bits 9-11 - - Available for use to system software. */
1450	#define X86_PML4E_AVL_MASK (BIT(9) \| BIT(10) \| BIT(11))
1451	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1452	#if 1 /* we're using this internally and have to mask of the top 16-bit. */
1453	#define X86_PML4E_PG_MASK ( 0x0000fffffffff000ULL )
1454	#else
1455	#define X86_PML4E_PG_MASK ( 0x000ffffffffff000ULL )
1456	#endif
1457	/** Bits 63 - NX - PAE - No execution flag. */
1458	#define X86_PML4E_NX BIT64(63)
1459
1460	/**
1461	* Page Map Level-4 Entry
1462	*/
1463	typedef struct X86PML4EBITS
1464	{
1465	/** Flags whether(=1) or not the page is present. */
1466	uint32_t u1Present : 1;
1467	/** Read(=0) / Write(=1) flag. */
1468	uint32_t u1Write : 1;
1469	/** User(=1) / Supervisor (=0) flag. */
1470	uint32_t u1User : 1;
1471	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1472	uint32_t u1WriteThru : 1;
1473	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1474	uint32_t u1CacheDisable : 1;
1475	/** Accessed flag.
1476	* Indicates that the page have been read or written to. */
1477	uint32_t u1Accessed : 1;
1478	/** Chunk of reserved bits. */
1479	uint32_t u3Reserved : 3;
1480	/** Available for use to system software. */
1481	uint32_t u3Available : 3;
1482	/** Physical Page number of the next level - Low Part. Don't use! */
1483	uint32_t u20PageNoLow : 20;
1484	/** Physical Page number of the next level - High Part. Don't use! */
1485	uint32_t u20PageNoHigh : 20;
1486	/** MBZ bits */
1487	uint32_t u11Reserved : 11;
1488	/** No Execute flag. */
1489	uint32_t u1NoExecute : 1;
1490	} X86PML4EBITS;
1491	/** Pointer to a page map level-4 entry. */
1492	typedef X86PML4EBITS *PX86PML4EBITS;
1493	/** Pointer to a const page map level-4 entry. */
1494	typedef const X86PML4EBITS *PCX86PML4EBITS;
1495
1496	/**
1497	* Page Map Level-4 Entry.
1498	*/
1499	typedef union X86PML4E
1500	{
1501	/** Normal view. */
1502	X86PML4EBITS n;
1503	/** Unsigned integer view. */
1504	X86PGPAEUINT u;
1505	/** 8 bit unsigned integer view. */
1506	uint8_t au8[8];
1507	/** 16 bit unsigned integer view. */
1508	uint16_t au16[4];
1509	/** 32 bit unsigned integer view. */
1510	uint32_t au32[2];
1511	} X86PML4E;
1512	/** Pointer to a page map level-4 entry. */
1513	typedef X86PML4E *PX86PML4E;
1514	/** Pointer to a const page map level-4 entry. */
1515	typedef const X86PML4E *PCX86PML4E;
1516
1517
1518	/**
1519	* Page Map Level-4.
1520	*/
1521	typedef struct X86PML4
1522	{
1523	/** PDE Array. */
1524	X86PML4E a[X86_PG_PAE_ENTRIES];
1525	} X86PML4;
1526	/** Pointer to a page map level-4. */
1527	typedef X86PML4 *PX86PML4;
1528	/** Pointer to a const page map level-4. */
1529	typedef const X86PML4 *PCX86PML4;
1530
1531	/** The page shift to get the PML4 index. */
1532	#define X86_PML4_SHIFT 39
1533	/** The PML4 index mask (apply to a shifted page address). */
1534	#define X86_PML4_MASK 0x1ff
1535
1536	/** @} */
1537
1538	/** @} */
1539
1540
1541	/**
1542	* 80-bit MMX/FPU register type.
1543	*/
1544	typedef struct X86FPUMMX
1545	{
1546	uint8_t reg[10];
1547	} X86FPUMMX;
1548	/** Pointer to a 80-bit MMX/FPU register type. */
1549	typedef X86FPUMMX *PX86FPUMMX;
1550	/** Pointer to a const 80-bit MMX/FPU register type. */
1551	typedef const X86FPUMMX *PCX86FPUMMX;
1552
1553	/**
1554	* FPU state (aka FSAVE/FRSTOR Memory Region).
1555	*/
1556	#pragma pack(1)
1557	typedef struct X86FPUSTATE
1558	{
1559	/** Control word. */
1560	uint16_t FCW;
1561	/** Alignment word */
1562	uint16_t Dummy1;
1563	/** Status word. */
1564	uint16_t FSW;
1565	/** Alignment word */
1566	uint16_t Dummy2;
1567	/** Tag word */
1568	uint16_t FTW;
1569	/** Alignment word */
1570	uint16_t Dummy3;
1571
1572	/** Instruction pointer. */
1573	uint32_t FPUIP;
1574	/** Code selector. */
1575	uint16_t CS;
1576	/** Opcode. */
1577	uint16_t FOP;
1578	/** FOO. */
1579	uint32_t FPUOO;
1580	/** FOS. */
1581	uint32_t FPUOS;
1582	/** FPU view - todo. */
1583	X86FPUMMX regs[8];
1584	} X86FPUSTATE;
1585	#pragma pack()
1586	/** Pointer to a FPU state. */
1587	typedef X86FPUSTATE *PX86FPUSTATE;
1588	/** Pointer to a const FPU state. */
1589	typedef const X86FPUSTATE *PCX86FPUSTATE;
1590
1591	/**
1592	* FPU Extended state (aka FXSAVE/FXRSTORE Memory Region).
1593	*/
1594	#pragma pack(1)
1595	typedef struct X86FXSTATE
1596	{
1597	/** Control word. */
1598	uint16_t FCW;
1599	/** Status word. */
1600	uint16_t FSW;
1601	/** Tag word (it's a byte actually). */
1602	uint8_t FTW;
1603	uint8_t huh1;
1604	/** Opcode. */
1605	uint16_t FOP;
1606	/** Instruction pointer. */
1607	uint32_t FPUIP;
1608	/** Code selector. */
1609	uint16_t CS;
1610	uint16_t Rsvrd1;
1611	/* - offset 16 - */
1612	/** Data pointer. */
1613	uint32_t FPUDP;
1614	/** Data segment */
1615	uint16_t DS;
1616	uint16_t Rsrvd2;
1617	uint32_t MXCSR;
1618	uint32_t MXCSR_MASK;
1619	/* - offset 32 - */
1620	union
1621	{
1622	/** MMX view. */
1623	uint64_t mmx;
1624	/** FPU view - todo. */
1625	X86FPUMMX fpu;
1626	/** 8-bit view. */
1627	uint8_t au8[16];
1628	/** 16-bit view. */
1629	uint16_t au16[8];
1630	/** 32-bit view. */
1631	uint32_t au32[4];
1632	/** 64-bit view. */
1633	uint64_t au64[2];
1634	/** 128-bit view. (yeah, very helpful) */
1635	uint128_t au128[1];
1636	} aRegs[8];
1637	/* - offset 160 - */
1638	union
1639	{
1640	/** XMM Register view . /
1641	uint128_t xmm;
1642	/** 8-bit view. */
1643	uint8_t au8[16];
1644	/** 16-bit view. */
1645	uint16_t au16[8];
1646	/** 32-bit view. */
1647	uint32_t au32[4];
1648	/** 64-bit view. */
1649	uint64_t au64[2];
1650	/** 128-bit view. (yeah, very helpful) */
1651	uint128_t au128[1];
1652	} aXMM[8];
1653	/* - offset 288 - */
1654	uint32_t au32RsrvdRest[(512 - 288) / sizeof(uint32_t)];
1655	} X86FXSTATE;
1656	#pragma pack()
1657	/** Pointer to a FPU Extended state. */
1658	typedef X86FXSTATE *PX86FXSTATE;
1659	/** Pointer to a const FPU Extended state. */
1660	typedef const X86FXSTATE *PCX86FXSTATE;
1661
1662
1663	/** @name Selector Descriptor
1664	* @{
1665	*/
1666
1667	/**
1668	* Generic descriptor table entry
1669	*/
1670	#pragma pack(1)
1671	typedef struct X86DESCGENERIC
1672	{
1673	/** Limit - Low word. */
1674	unsigned u16LimitLow : 16;
1675	/** Base address - lowe word.
1676	* Don't try set this to 24 because MSC is doing studing things then. */
1677	unsigned u16BaseLow : 16;
1678	/** Base address - first 8 bits of high word. */
1679	unsigned u8BaseHigh1 : 8;
1680	/** Segment Type. */
1681	unsigned u4Type : 4;
1682	/** Descriptor Type. System(=0) or code/data selector */
1683	unsigned u1DescType : 1;
1684	/** Descriptor Privelege level. */
1685	unsigned u2Dpl : 2;
1686	/** Flags selector present(=1) or not. */
1687	unsigned u1Present : 1;
1688	/** Segment limit 16-19. */
1689	unsigned u4LimitHigh : 4;
1690	/** Available for system software. */
1691	unsigned u1Available : 1;
1692	/** Reserved - 0. */
1693	unsigned u1Reserved : 1;
1694	/** This flags meaning depends on the segment type. Try make sense out
1695	* of the intel manual yourself. */
1696	unsigned u1DefBig : 1;
1697	/** Granularity of the limit. If set 4KB granularity is used, if
1698	* clear byte. */
1699	unsigned u1Granularity : 1;
1700	/** Base address - highest 8 bits. */
1701	unsigned u8BaseHigh2 : 8;
1702	} X86DESCGENERIC;
1703	#pragma pack()
1704	/** Pointer to a generic descriptor entry. */
1705	typedef X86DESCGENERIC *PX86DESCGENERIC;
1706	/** Pointer to a const generic descriptor entry. */
1707	typedef const X86DESCGENERIC *PCX86DESCGENERIC;
1708
1709
1710	/**
1711	* Descriptor attributes.
1712	*/
1713	typedef struct X86DESCATTRBITS
1714	{
1715	/** Segment Type. */
1716	unsigned u4Type : 4;
1717	/** Descriptor Type. System(=0) or code/data selector */
1718	unsigned u1DescType : 1;
1719	/** Descriptor Privelege level. */
1720	unsigned u2Dpl : 2;
1721	/** Flags selector present(=1) or not. */
1722	unsigned u1Present : 1;
1723	/** Segment limit 16-19. */
1724	unsigned u4LimitHigh : 4;
1725	/** Available for system software. */
1726	unsigned u1Available : 1;
1727	/** Reserved - 0. */
1728	unsigned u1Reserved : 1;
1729	/** This flags meaning depends on the segment type. Try make sense out
1730	* of the intel manual yourself. */
1731	unsigned u1DefBig : 1;
1732	/** Granularity of the limit. If set 4KB granularity is used, if
1733	* clear byte. */
1734	unsigned u1Granularity : 1;
1735	} X86DESCATTRBITS;
1736
1737
1738	#pragma pack(1)
1739	typedef union X86DESCATTR
1740	{
1741	/** Normal view. */
1742	X86DESCATTRBITS n;
1743	/** Unsigned integer view. */
1744	uint32_t u;
1745	} X86DESCATTR;
1746	#pragma pack()
1747
1748	/** Pointer to descriptor attributes. */
1749	typedef X86DESCATTR *PX86DESCATTR;
1750	/** Pointer to const descriptor attributes. */
1751	typedef const X86DESCATTR *PCX86DESCATTR;
1752
1753
1754	/**
1755	* Descriptor table entry.
1756	*/
1757	#pragma pack(1)
1758	typedef union X86DESC
1759	{
1760	/** Generic descriptor view. */
1761	X86DESCGENERIC Gen;
1762	#if 0
1763	/** IDT view. */
1764	VBOXIDTE Idt;
1765	#endif
1766
1767	/** 8 bit unsigned interger view. */
1768	uint8_t au8[8];
1769	/** 16 bit unsigned interger view. */
1770	uint16_t au16[4];
1771	/** 32 bit unsigned interger view. */
1772	uint32_t au32[2];
1773	} X86DESC;
1774	#pragma pack()
1775	/** Pointer to descriptor table entry. */
1776	typedef X86DESC *PX86DESC;
1777	/** Pointer to const descriptor table entry. */
1778	typedef const X86DESC *PCX86DESC;
1779
1780
1781	/**
1782	* 64 bits generic descriptor table entry
1783	* Note: most of these bits have no meaning in long mode.
1784	*/
1785	#pragma pack(1)
1786	typedef struct X86DESC64GENERIC
1787	{
1788	/** Limit - Low word - IGNORED. */
1789	unsigned u16LimitLow : 16;
1790	/** Base address - lowe word. - IGNORED
1791	* Don't try set this to 24 because MSC is doing studing things then. */
1792	unsigned u16BaseLow : 16;
1793	/** Base address - first 8 bits of high word. - IGNORED */
1794	unsigned u8BaseHigh1 : 8;
1795	/** Segment Type. */
1796	unsigned u4Type : 4;
1797	/** Descriptor Type. System(=0) or code/data selector */
1798	unsigned u1DescType : 1;
1799	/** Descriptor Privelege level. */
1800	unsigned u2Dpl : 2;
1801	/** Flags selector present(=1) or not. */
1802	unsigned u1Present : 1;
1803	/** Segment limit 16-19. - IGNORED */
1804	unsigned u4LimitHigh : 4;
1805	/** Available for system software. - IGNORED */
1806	unsigned u1Available : 1;
1807	/** Long mode flag. */
1808	unsigned u1Long : 1;
1809	/** This flags meaning depends on the segment type. Try make sense out
1810	* of the intel manual yourself. */
1811	unsigned u1DefBig : 1;
1812	/** Granularity of the limit. If set 4KB granularity is used, if
1813	* clear byte. - IGNORED */
1814	unsigned u1Granularity : 1;
1815	/** Base address - highest 8 bits. - IGNORED */
1816	unsigned u8BaseHigh2 : 8;
1817	/** Base address - bits 63-32. */
1818	unsigned u32BaseHigh3 : 32;
1819	unsigned u8Reserved : 8;
1820	unsigned u5Zeros : 5;
1821	unsigned u19Reserved : 19;
1822	} X86DESC64GENERIC;
1823	#pragma pack()
1824	/** Pointer to a generic descriptor entry. */
1825	typedef X86DESC64GENERIC *PX86DESC64GENERIC;
1826	/** Pointer to a const generic descriptor entry. */
1827	typedef const X86DESC64GENERIC *PCX86DESC64GENERIC;
1828
1829	/**
1830	* System descriptor table entry (64 bits)
1831	*/
1832	#pragma pack(1)
1833	typedef struct X86DESC64SYSTEM
1834	{
1835	/** Limit - Low word. */
1836	unsigned u16LimitLow : 16;
1837	/** Base address - lowe word.
1838	* Don't try set this to 24 because MSC is doing studing things then. */
1839	unsigned u16BaseLow : 16;
1840	/** Base address - first 8 bits of high word. */
1841	unsigned u8BaseHigh1 : 8;
1842	/** Segment Type. */
1843	unsigned u4Type : 4;
1844	/** Descriptor Type. System(=0) or code/data selector */
1845	unsigned u1DescType : 1;
1846	/** Descriptor Privelege level. */
1847	unsigned u2Dpl : 2;
1848	/** Flags selector present(=1) or not. */
1849	unsigned u1Present : 1;
1850	/** Segment limit 16-19. */
1851	unsigned u4LimitHigh : 4;
1852	/** Available for system software. */
1853	unsigned u1Available : 1;
1854	/** Reserved - 0. */
1855	unsigned u1Reserved : 1;
1856	/** This flags meaning depends on the segment type. Try make sense out
1857	* of the intel manual yourself. */
1858	unsigned u1DefBig : 1;
1859	/** Granularity of the limit. If set 4KB granularity is used, if
1860	* clear byte. */
1861	unsigned u1Granularity : 1;
1862	/** Base address - bits 31-24. */
1863	unsigned u8BaseHigh2 : 8;
1864	/** Base address - bits 63-32. */
1865	unsigned u32BaseHigh3 : 32;
1866	unsigned u8Reserved : 8;
1867	unsigned u5Zeros : 5;
1868	unsigned u19Reserved : 19;
1869	} X86DESC64SYSTEM;
1870	#pragma pack()
1871	/** Pointer to a generic descriptor entry. */
1872	typedef X86DESC64SYSTEM *PX86DESC64SYSTEM;
1873	/** Pointer to a const generic descriptor entry. */
1874	typedef const X86DESC64SYSTEM *PCX86DESC64SYSTEM;
1875
1876
1877	/**
1878	* Descriptor table entry.
1879	*/
1880	#pragma pack(1)
1881	typedef union X86DESC64
1882	{
1883	/** Generic descriptor view. */
1884	X86DESC64GENERIC Gen;
1885	/** System descriptor view. */
1886	X86DESC64SYSTEM System;
1887	#if 0
1888	X86DESC64GATE Gate;
1889	#endif
1890
1891	/** 8 bit unsigned interger view. */
1892	uint8_t au8[16];
1893	/** 16 bit unsigned interger view. */
1894	uint16_t au16[8];
1895	/** 32 bit unsigned interger view. */
1896	uint32_t au32[4];
1897	/** 64 bit unsigned interger view. */
1898	uint64_t au64[2];
1899	} X86DESC64;
1900	#pragma pack()
1901	/** Pointer to descriptor table entry. */
1902	typedef X86DESC64 *PX86DESC64;
1903	/** Pointer to const descriptor table entry. */
1904	typedef const X86DESC64 *PCX86DESC64;
1905
1906	#if HC_ARCH_BITS == 64
1907	typedef X86DESC64 X86DESCHC;
1908	typedef X86DESC64 *PX86DESCHC;
1909	#else
1910	typedef X86DESC X86DESCHC;
1911	typedef X86DESC *PX86DESCHC;
1912	#endif
1913
1914	/** @name Selector Descriptor Types.
1915	* @{
1916	*/
1917
1918	/** @name Non-System Selector Types.
1919	* @{ */
1920	/** Code(=set)/Data(=clear) bit. */
1921	#define X86_SEL_TYPE_CODE 8
1922	/** Memory(=set)/System(=clear) bit. */
1923	#define X86_SEL_TYPE_MEMORY BIT(4)
1924	/** Accessed bit. */
1925	#define X86_SEL_TYPE_ACCESSED 1
1926	/** Expand down bit (for data selectors only). */
1927	#define X86_SEL_TYPE_DOWN 4
1928	/** Conforming bit (for code selectors only). */
1929	#define X86_SEL_TYPE_CONF 4
1930	/** Write bit (for data selectors only). */
1931	#define X86_SEL_TYPE_WRITE 2
1932	/** Read bit (for code selectors only). */
1933	#define X86_SEL_TYPE_READ 2
1934
1935	/** Read only selector type. */
1936	#define X86_SEL_TYPE_RO 0
1937	/** Accessed read only selector type. */
1938	#define X86_SEL_TYPE_RO_ACC (0 \| X86_SEL_TYPE_ACCESSED)
1939	/** Read write selector type. */
1940	#define X86_SEL_TYPE_RW 2
1941	/** Accessed read write selector type. */
1942	#define X86_SEL_TYPE_RW_ACC (2 \| X86_SEL_TYPE_ACCESSED)
1943	/** Expand down read only selector type. */
1944	#define X86_SEL_TYPE_RO_DOWN 4
1945	/** Accessed expand down read only selector type. */
1946	#define X86_SEL_TYPE_RO_DOWN_ACC (4 \| X86_SEL_TYPE_ACCESSED)
1947	/** Expand down read write selector type. */
1948	#define X86_SEL_TYPE_RW_DOWN 6
1949	/** Accessed expand down read write selector type. */
1950	#define X86_SEL_TYPE_RW_DOWN_ACC (6 \| X86_SEL_TYPE_ACCESSED)
1951	/** Execute only selector type. */
1952	#define X86_SEL_TYPE_EO (0 \| X86_SEL_TYPE_CODE)
1953	/** Accessed execute only selector type. */
1954	#define X86_SEL_TYPE_EO_ACC (0 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
1955	/** Execute and read selector type. */
1956	#define X86_SEL_TYPE_ER (2 \| X86_SEL_TYPE_CODE)
1957	/** Accessed execute and read selector type. */
1958	#define X86_SEL_TYPE_ER_ACC (2 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
1959	/** Conforming execute only selector type. */
1960	#define X86_SEL_TYPE_EO_CONF (4 \| X86_SEL_TYPE_CODE)
1961	/** Accessed Conforming execute only selector type. */
1962	#define X86_SEL_TYPE_EO_CONF_ACC (4 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
1963	/** Conforming execute and write selector type. */
1964	#define X86_SEL_TYPE_ER_CONF (6 \| X86_SEL_TYPE_CODE)
1965	/** Accessed Conforming execute and write selector type. */
1966	#define X86_SEL_TYPE_ER_CONF_ACC (6 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
1967	/** @} */
1968
1969
1970	/** @name System Selector Types.
1971	* @{ */
1972	/** Undefined system selector type. */
1973	#define X86_SEL_TYPE_SYS_UNDEFINED 0
1974	/** 286 TSS selector. */
1975	#define X86_SEL_TYPE_SYS_286_TSS_AVAIL 1
1976	/** LDT selector. */
1977	#define X86_SEL_TYPE_SYS_LDT 2
1978	/** 286 TSS selector - Busy. */
1979	#define X86_SEL_TYPE_SYS_286_TSS_BUSY 3
1980	/** 286 Callgate selector. */
1981	#define X86_SEL_TYPE_SYS_286_CALL_GATE 4
1982	/** Taskgate selector. */
1983	#define X86_SEL_TYPE_SYS_TASK_GATE 5
1984	/** 286 Interrupt gate selector. */
1985	#define X86_SEL_TYPE_SYS_286_INT_GATE 6
1986	/** 286 Trapgate selector. */
1987	#define X86_SEL_TYPE_SYS_286_TRAP_GATE 7
1988	/** Undefined system selector. */
1989	#define X86_SEL_TYPE_SYS_UNDEFINED2 8
1990	/** 386 TSS selector. */
1991	#define X86_SEL_TYPE_SYS_386_TSS_AVAIL 9
1992	/** Undefined system selector. */
1993	#define X86_SEL_TYPE_SYS_UNDEFINED3 0xA
1994	/** 386 TSS selector - Busy. */
1995	#define X86_SEL_TYPE_SYS_386_TSS_BUSY 0xB
1996	/** 386 Callgate selector. */
1997	#define X86_SEL_TYPE_SYS_386_CALL_GATE 0xC
1998	/** Undefined system selector. */
1999	#define X86_SEL_TYPE_SYS_UNDEFINED4 0xD
2000	/** 386 Interruptgate selector. */
2001	#define X86_SEL_TYPE_SYS_386_INT_GATE 0xE
2002	/** 386 Trapgate selector. */
2003	#define X86_SEL_TYPE_SYS_386_TRAP_GATE 0xF
2004	/** @} */
2005
2006	/** @name AMD64 System Selector Types.
2007	* @{ */
2008	#define AMD64_SEL_TYPE_SYS_LDT 2
2009	/** 286 TSS selector - Busy. */
2010	#define AMD64_SEL_TYPE_SYS_TSS_AVAIL 9
2011	/** 386 TSS selector - Busy. */
2012	#define AMD64_SEL_TYPE_SYS_TSS_BUSY 0xB
2013	/** 386 Callgate selector. */
2014	#define AMD64_SEL_TYPE_SYS_CALL_GATE 0xC
2015	/** 386 Interruptgate selector. */
2016	#define AMD64_SEL_TYPE_SYS_INT_GATE 0xE
2017	/** 386 Trapgate selector. */
2018	#define AMD64_SEL_TYPE_SYS_TRAP_GATE 0xF
2019	/** @} */
2020
2021	/** @} */
2022
2023
2024	/** @name Descriptor Table Entry Flag Masks.
2025	* These are for the 2nd 32-bit word of a descriptor.
2026	* @{ */
2027	/** Bits 8-11 - TYPE - Descriptor type mask. */
2028	#define X86_DESC_TYPE_MASK (BIT(8) \| BIT(9) \| BIT(10) \| BIT(11))
2029	/** Bit 12 - S - System (=0) or Code/Data (=1). */
2030	#define X86_DESC_S BIT(12)
2031	/** Bits 13-14 - DPL - Descriptor Privilege Level. */
2032	#define X86_DESC_DPL (BIT(13) \| BIT(14))
2033	/** Bit 15 - P - Present. */
2034	#define X86_DESC_P BIT(15)
2035	/** Bit 20 - AVL - Available for system software. */
2036	#define X86_DESC_AVL BIT(20)
2037	/** Bit 22 - DB - Default operation size. 0 = 16 bit, 1 = 32 bit. */
2038	#define X86_DESC_DB BIT(22)
2039	/** Bit 23 - G - Granularity of the limit. If set 4KB granularity is
2040	* used, if clear byte. */
2041	#define X86_DESC_G BIT(23)
2042	/** @} */
2043
2044	/** @} */
2045
2046
2047	/** @name Selectors.
2048	* @{
2049	*/
2050
2051	/**
2052	* The shift used to convert a selector from and to index an index (C).
2053	*/
2054	#define X86_SEL_SHIFT 3
2055
2056	/**
2057	* The shift used to convert a selector from and to index an index (C).
2058	*/
2059	#define AMD64_SEL_SHIFT 4
2060
2061	#if HC_ARCH_BITS == 64
2062	#define X86_SEL_SHIFT_HC AMD64_SEL_SHIFT
2063	#else
2064	#define X86_SEL_SHIFT_HC X86_SEL_SHIFT
2065	#endif
2066
2067	/**
2068	* The mask used to mask off the table indicator and CPL of an selector.
2069	*/
2070	#define X86_SEL_MASK 0xfff8
2071
2072	/**
2073	* The bit indicating that a selector is in the LDT and not in the GDT.
2074	*/
2075	#define X86_SEL_LDT 0x0004
2076	/**
2077	* The bit mask for getting the RPL of a selector.
2078	*/
2079	#define X86_SEL_RPL 0x0003
2080
2081	/** @} */
2082
2083
2084	/**
2085	* x86 Exceptions/Faults/Traps.
2086	*/
2087	typedef enum X86XCPT
2088	{
2089	/** \#DE - Divide error. */
2090	X86_XCPT_DE = 0x00,
2091	/** \#DB - Debug event (single step, DRx, ..) */
2092	X86_XCPT_DB = 0x01,
2093	/** NMI - Non-Maskable Interrupt */
2094	X86_XCPT_NMI = 0x02,
2095	/** \#BP - Breakpoint (INT3). */
2096	X86_XCPT_BP = 0x03,
2097	/** \#OF - Overflow (INTO). */
2098	X86_XCPT_OF = 0x04,
2099	/** \#BR - Bound range exceeded (BOUND). */
2100	X86_XCPT_BR = 0x05,
2101	/** \#UD - Undefined opcode. */
2102	X86_XCPT_UD = 0x06,
2103	/** \#NM - Device not available (math coprocessor device). */
2104	X86_XCPT_NM = 0x07,
2105	/** \#DF - Double fault. */
2106	X86_XCPT_DF = 0x08,
2107	/** ??? - Coprocessor segment overrun (obsolete). */
2108	X86_XCPT_CO_SEG_OVERRUN = 0x09,
2109	/** \#TS - Taskswitch (TSS). */
2110	X86_XCPT_TS = 0x0a,
2111	/** \#NP - Segment no present. */
2112	X86_XCPT_NP = 0x0b,
2113	/** \#SS - Stack segment fault. */
2114	X86_XCPT_SS = 0x0c,
2115	/** \#GP - General protection fault. */
2116	X86_XCPT_GP = 0x0d,
2117	/** \#PF - Page fault. */
2118	X86_XCPT_PF = 0x0e,
2119	/* 0x0f is reserved. */
2120	/** \#MF - Math fault (FPU). */
2121	X86_XCPT_MF = 0x10,
2122	/** \#AC - Alignment check. */
2123	X86_XCPT_AC = 0x11,
2124	/** \#MC - Machine check. */
2125	X86_XCPT_MC = 0x12,
2126	/** \#XF - SIMD Floating-Pointer Exception. */
2127	X86_XCPT_XF = 0x13
2128	} X86XCPT;
2129	/** Pointer to a x86 exception code. */
2130	typedef X86XCPT *PX86XCPT;
2131	/** Pointer to a const x86 exception code. */
2132	typedef const X86XCPT *PCX86XCPT;
2133
2134
2135	/** @name Trap Error Codes
2136	* @{
2137	*/
2138	/** External indicator. */
2139	#define X86_TRAP_ERR_EXTERNAL 1
2140	/** IDT indicator. */
2141	#define X86_TRAP_ERR_IDT 2
2142	/** Descriptor table indicator - If set LDT, if clear GDT. */
2143	#define X86_TRAP_ERR_TI 4
2144	/** Mask for getting the selector. */
2145	#define X86_TRAP_ERR_SEL_MASK 0xfff8
2146	/** Shift for getting the selector table index (C type index). */
2147	#define X86_TRAP_ERR_SEL_SHIFT 3
2148	/** @} */
2149
2150
2151	/** @name \#PF Trap Error Codes
2152	* @{
2153	*/
2154	/** Bit 0 - P - Not present (clear) or page level protection (set) fault. */
2155	#define X86_TRAP_PF_P BIT(0)
2156	/** Bit 1 - R/W - Read (clear) or write (set) access. */
2157	#define X86_TRAP_PF_RW BIT(1)
2158	/** Bit 2 - U/S - CPU executing in user mode (set) or supervisor mode (clear). */
2159	#define X86_TRAP_PF_US BIT(2)
2160	/** Bit 3 - RSVD- Reserved bit violation (set), i.e. reserved bit was set to 1. */
2161	#define X86_TRAP_PF_RSVD BIT(3)
2162	/** Bit 4 - I/D - Instruction fetch (set) / Data access (clear) - PAE + NXE. */
2163	#define X86_TRAP_PF_ID BIT(4)
2164	/** @} */
2165
2166	#pragma pack(1)
2167	/**
2168	* 32-bit IDTR/GDTR.
2169	*/
2170	typedef struct X86XDTR32
2171	{
2172	/** Size of the descriptor table. */
2173	uint16_t cb;
2174	/** Address of the descriptor table. */
2175	uint32_t uAddr;
2176	} X86XDTR32, *PX86XDTR32;
2177	#pragma pack()
2178
2179	#pragma pack(1)
2180	/**
2181	* 64-bit IDTR/GDTR.
2182	*/
2183	typedef struct X86XDTR64
2184	{
2185	/** Size of the descriptor table. */
2186	uint16_t cb;
2187	/** Address of the descriptor table. */
2188	uint64_t uAddr;
2189	} X86XDTR64, *PX86XDTR64;
2190	#pragma pack()
2191
2192	/** @} */
2193
2194	#endif
2195

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source: vbox/trunk/include/VBox/x86.h@ 4337

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