x86.h@ 7581

Last change on this file since 7581 was 7121, checked in by vboxsync, 17 years ago
Added a plain unsigned view to keep things shorter.
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1	/** @file
2	* X86 (and AMD64) Structures and Definitions.
3	*/
4
5	/*
6	* Copyright (C) 2006-2007 innotek GmbH
7	*
8	* This file is part of VirtualBox Open Source Edition (OSE), as
9	* available from http://www.virtualbox.org. This file is free software;
10	* you can redistribute it and/or modify it under the terms of the GNU
11	* General Public License (GPL) as published by the Free Software
12	* Foundation, in version 2 as it comes in the "COPYING" file of the
13	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15	*
16	* The contents of this file may alternatively be used under the terms
17	* of the Common Development and Distribution License Version 1.0
18	* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19	* VirtualBox OSE distribution, in which case the provisions of the
20	* CDDL are applicable instead of those of the GPL.
21	*
22	* You may elect to license modified versions of this file under the
23	* terms and conditions of either the GPL or the CDDL or both.
24	*/
25
26	/*
27	* x86.mac is generated from this file using:
28	* sed -e '/__VBox_x86_h__/d' -e '/#define/!d' -e 's/#define/%define/' include/VBox/x86.h
29	*/
30
31	#ifndef ___VBox_x86_h
32	#define ___VBox_x86_h
33
34	#include <VBox/types.h>
35
36	/* Workaround for Solaris sys/regset.h defining CS, DS */
37	#if defined(RT_OS_SOLARIS)
38	# undef CS
39	# undef DS
40	#endif
41
42	/** @defgroup grp_x86 x86 Types and Definitions
43	* @{
44	*/
45
46	/**
47	* EFLAGS Bits.
48	*/
49	typedef struct X86EFLAGSBITS
50	{
51	/** Bit 0 - CF - Carry flag - Status flag. */
52	unsigned u1CF : 1;
53	/** Bit 1 - 1 - Reserved flag. */
54	unsigned u1Reserved0 : 1;
55	/** Bit 2 - PF - Parity flag - Status flag. */
56	unsigned u1PF : 1;
57	/** Bit 3 - 0 - Reserved flag. */
58	unsigned u1Reserved1 : 1;
59	/** Bit 4 - AF - Auxiliary carry flag - Status flag. */
60	unsigned u1AF : 1;
61	/** Bit 5 - 0 - Reserved flag. */
62	unsigned u1Reserved2 : 1;
63	/** Bit 6 - ZF - Zero flag - Status flag. */
64	unsigned u1ZF : 1;
65	/** Bit 7 - SF - Signed flag - Status flag. */
66	unsigned u1SF : 1;
67	/** Bit 8 - TF - Trap flag - System flag. */
68	unsigned u1TF : 1;
69	/** Bit 9 - IF - Interrupt flag - System flag. */
70	unsigned u1IF : 1;
71	/** Bit 10 - DF - Direction flag - Control flag. */
72	unsigned u1DF : 1;
73	/** Bit 11 - OF - Overflow flag - Status flag. */
74	unsigned u1OF : 1;
75	/** Bit 12-13 - IOPL - I/O prvilege level flag - System flag. */
76	unsigned u2IOPL : 2;
77	/** Bit 14 - NT - Nested task flag - System flag. */
78	unsigned u1NT : 1;
79	/** Bit 15 - 0 - Reserved flag. */
80	unsigned u1Reserved3 : 1;
81	/** Bit 16 - RF - Resume flag - System flag. */
82	unsigned u1RF : 1;
83	/** Bit 17 - VM - Virtual 8086 mode - System flag. */
84	unsigned u1VM : 1;
85	/** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
86	unsigned u1AC : 1;
87	/** Bit 19 - VIF - Virtual interupt flag - System flag. */
88	unsigned u1VIF : 1;
89	/** Bit 20 - VIP - Virtual interupt pending flag - System flag. */
90	unsigned u1VIP : 1;
91	/** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
92	unsigned u1ID : 1;
93	/** Bit 22-31 - 0 - Reserved flag. */
94	unsigned u10Reserved4 : 10;
95	} X86EFLAGSBITS;
96	/** Pointer to EFLAGS bits. */
97	typedef X86EFLAGSBITS *PX86EFLAGSBITS;
98	/** Pointer to const EFLAGS bits. */
99	typedef const X86EFLAGSBITS *PCX86EFLAGSBITS;
100
101	/**
102	* EFLAGS.
103	*/
104	typedef union X86EFLAGS
105	{
106	/** The bitfield view. */
107	X86EFLAGSBITS Bits;
108	/** The 8-bit view. */
109	uint8_t au8[4];
110	/** The 16-bit view. */
111	uint16_t au16[2];
112	/** The 32-bit view. */
113	uint32_t au32[1];
114	/** The 32-bit view. */
115	uint32_t u32;
116	/** The plain unsigned view. */
117	uint32_t u;
118	} X86EFLAGS;
119	/** Pointer to EFLAGS. */
120	typedef X86EFLAGS *PX86EFLAGS;
121	/** Pointer to const EFLAGS. */
122	typedef const X86EFLAGS *PCX86EFLAGS;
123
124	/**
125	* RFLAGS (32 upper bits are reserved).
126	*/
127	typedef union X86RFLAGS
128	{
129	/** The bitfield view. */
130	X86EFLAGSBITS Bits;
131	/** The 8-bit view. */
132	uint8_t au8[8];
133	/** The 16-bit view. */
134	uint16_t au16[4];
135	/** The 32-bit view. */
136	uint32_t au32[2];
137	/** The 64-bit view. */
138	uint64_t au64[1];
139	/** The 64-bit view. */
140	uint64_t u64;
141	/** The plain unsigned view. */
142	uint64_t u;
143	} X86RFLAGS;
144	/** Pointer to RFLAGS. */
145	typedef X86RFLAGS *PX86RFLAGS;
146	/** Pointer to const RFLAGS. */
147	typedef const X86RFLAGS *PCX86RFLAGS;
148
149
150	/** @name EFLAGS
151	* @{
152	*/
153	/** Bit 0 - CF - Carry flag - Status flag. */
154	#define X86_EFL_CF RT_BIT(0)
155	/** Bit 2 - PF - Parity flag - Status flag. */
156	#define X86_EFL_PF RT_BIT(2)
157	/** Bit 4 - AF - Auxiliary carry flag - Status flag. */
158	#define X86_EFL_AF RT_BIT(4)
159	/** Bit 6 - ZF - Zero flag - Status flag. */
160	#define X86_EFL_ZF RT_BIT(6)
161	/** Bit 7 - SF - Signed flag - Status flag. */
162	#define X86_EFL_SF RT_BIT(7)
163	/** Bit 8 - TF - Trap flag - System flag. */
164	#define X86_EFL_TF RT_BIT(8)
165	/** Bit 9 - IF - Interrupt flag - System flag. */
166	#define X86_EFL_IF RT_BIT(9)
167	/** Bit 10 - DF - Direction flag - Control flag. */
168	#define X86_EFL_DF RT_BIT(10)
169	/** Bit 11 - OF - Overflow flag - Status flag. */
170	#define X86_EFL_OF RT_BIT(11)
171	/** Bit 12-13 - IOPL - I/O prvilege level flag - System flag. */
172	#define X86_EFL_IOPL (RT_BIT(12) \| RT_BIT(13))
173	/** Bit 14 - NT - Nested task flag - System flag. */
174	#define X86_EFL_NT RT_BIT(14)
175	/** Bit 16 - RF - Resume flag - System flag. */
176	#define X86_EFL_RF RT_BIT(16)
177	/** Bit 17 - VM - Virtual 8086 mode - System flag. */
178	#define X86_EFL_VM RT_BIT(17)
179	/** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
180	#define X86_EFL_AC RT_BIT(18)
181	/** Bit 19 - VIF - Virtual interupt flag - System flag. */
182	#define X86_EFL_VIF RT_BIT(19)
183	/** Bit 20 - VIP - Virtual interupt pending flag - System flag. */
184	#define X86_EFL_VIP RT_BIT(20)
185	/** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
186	#define X86_EFL_ID RT_BIT(21)
187	/** IOPL shift. */
188	#define X86_EFL_IOPL_SHIFT 12
189	/** The the IOPL level from the flags. */
190	#define X86_EFL_GET_IOPL(efl) (((efl) >> X86_EFL_IOPL_SHIFT) & 3)
191	/** @} */
192
193
194	/** CPUID Feature information - ECX.
195	* CPUID query with EAX=1.
196	*/
197	typedef struct X86CPUIDFEATECX
198	{
199	/** Bit 0 - SSE3 - Supports SSE3 or not. */
200	unsigned u1SSE3 : 1;
201	/** Reserved. */
202	unsigned u2Reserved1 : 2;
203	/** Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
204	unsigned u1Monitor : 1;
205	/** Bit 4 - CPL-DS - CPL Qualified Debug Store. */
206	unsigned u1CPLDS : 1;
207	/** Bit 5 - VMX - Virtual Machine Technology. */
208	unsigned u1VMX : 1;
209	/** Reserved. */
210	unsigned u1Reserved2 : 1;
211	/** Bit 7 - EST - Enh. SpeedStep Tech. */
212	unsigned u1EST : 1;
213	/** Bit 8 - TM2 - Terminal Monitor 2. */
214	unsigned u1TM2 : 1;
215	/** Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
216	unsigned u1SSSE3 : 1;
217	/** Bit 10 - CNTX-ID - L1 Context ID. */
218	unsigned u1CNTXID : 1;
219	/** Reserved. */
220	unsigned u2Reserved4 : 2;
221	/** Bit 13 - CX16 - CMPXCHG16B. */
222	unsigned u1CX16 : 1;
223	/** Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
224	unsigned u1TPRUpdate : 1;
225	/** Reserved. */
226	unsigned u17Reserved5 : 17;
227
228	} X86CPUIDFEATECX;
229	/** Pointer to CPUID Feature Information - ECX. */
230	typedef X86CPUIDFEATECX *PX86CPUIDFEATECX;
231	/** Pointer to const CPUID Feature Information - ECX. */
232	typedef const X86CPUIDFEATECX *PCX86CPUIDFEATECX;
233
234
235	/** CPUID Feature Information - EDX.
236	* CPUID query with EAX=1.
237	*/
238	typedef struct X86CPUIDFEATEDX
239	{
240	/** Bit 0 - FPU - x87 FPU on Chip. */
241	unsigned u1FPU : 1;
242	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
243	unsigned u1VME : 1;
244	/** Bit 2 - DE - Debugging extensions. */
245	unsigned u1DE : 1;
246	/** Bit 3 - PSE - Page Size Extension. */
247	unsigned u1PSE : 1;
248	/** Bit 4 - TSC - Time Stamp Counter. */
249	unsigned u1TSC : 1;
250	/** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
251	unsigned u1MSR : 1;
252	/** Bit 6 - PAE - Physical Address Extension. */
253	unsigned u1PAE : 1;
254	/** Bit 7 - MCE - Machine Check Exception. */
255	unsigned u1MCE : 1;
256	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
257	unsigned u1CX8 : 1;
258	/** Bit 9 - APIC - APIC On-Chick. */
259	unsigned u1APIC : 1;
260	/** Bit 10 - Reserved. */
261	unsigned u1Reserved1 : 1;
262	/** Bit 11 - SEP - SYSENTER and SYSEXIT. */
263	unsigned u1SEP : 1;
264	/** Bit 12 - MTRR - Memory Type Range Registers. */
265	unsigned u1MTRR : 1;
266	/** Bit 13 - PGE - PTE Global Bit. */
267	unsigned u1PGE : 1;
268	/** Bit 14 - MCA - Machine Check Architecture. */
269	unsigned u1MCA : 1;
270	/** Bit 15 - CMOV - Conditional Move Instructions. */
271	unsigned u1CMOV : 1;
272	/** Bit 16 - PAT - Page Attribute Table. */
273	unsigned u1PAT : 1;
274	/** Bit 17 - PSE-36 - 36-bit Page Size Extention. */
275	unsigned u1PSE36 : 1;
276	/** Bit 18 - PSN - Processor Serial Number. */
277	unsigned u1PSN : 1;
278	/** Bit 19 - CLFSH - CLFLUSH Instruction. */
279	unsigned u1CLFSH : 1;
280	/** Bit 20 - Reserved. */
281	unsigned u1Reserved2 : 1;
282	/** Bit 21 - DS - Debug Store. */
283	unsigned u1DS : 1;
284	/** Bit 22 - ACPI - Thermal Monitor and Software Controlled Clock Facilities. */
285	unsigned u1ACPI : 1;
286	/** Bit 23 - MMX - Intel MMX 'Technology'. */
287	unsigned u1MMX : 1;
288	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
289	unsigned u1FXSR : 1;
290	/** Bit 25 - SSE - SSE Support. */
291	unsigned u1SSE : 1;
292	/** Bit 26 - SSE2 - SSE2 Support. */
293	unsigned u1SSE2 : 1;
294	/** Bit 27 - SS - Self Snoop. */
295	unsigned u1SS : 1;
296	/** Bit 28 - HTT - Hyper-Threading Technology. */
297	unsigned u1HTT : 1;
298	/** Bit 29 - TM - Thermal Monitor. */
299	unsigned u1TM : 1;
300	/** Bit 30 - Reserved - . */
301	unsigned u1Reserved3 : 1;
302	/** Bit 31 - PBE - Pending Break Enabled. */
303	unsigned u1PBE : 1;
304	} X86CPUIDFEATEDX;
305	/** Pointer to CPUID Feature Information - EDX. */
306	typedef X86CPUIDFEATEDX *PX86CPUIDFEATEDX;
307	/** Pointer to const CPUID Feature Information - EDX. */
308	typedef const X86CPUIDFEATEDX *PCX86CPUIDFEATEDX;
309
310	/** @name CPUID Vendor information.
311	* CPUID query with EAX=0.
312	* @{
313	*/
314	#define X86_CPUID_VENDOR_INTEL_EBX 0x756e6547 /* Genu */
315	#define X86_CPUID_VENDOR_INTEL_ECX 0x6c65746e /* ntel */
316	#define X86_CPUID_VENDOR_INTEL_EDX 0x49656e69 /* ineI */
317
318	#define X86_CPUID_VENDOR_AMD_EBX 0x68747541 /* Auth */
319	#define X86_CPUID_VENDOR_AMD_ECX 0x444d4163 /* cAMD */
320	#define X86_CPUID_VENDOR_AMD_EDX 0x69746e65 /* enti */
321	/** @} */
322
323
324	/** @name CPUID Feature information.
325	* CPUID query with EAX=1.
326	* @{
327	*/
328	/** ECX Bit 0 - SSE3 - Supports SSE3 or not. */
329	#define X86_CPUID_FEATURE_ECX_SSE3 RT_BIT(0)
330	/** ECX Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
331	#define X86_CPUID_FEATURE_ECX_MONITOR RT_BIT(3)
332	/** ECX Bit 4 - CPL-DS - CPL Qualified Debug Store. */
333	#define X86_CPUID_FEATURE_ECX_CPLDS RT_BIT(4)
334	/** ECX Bit 5 - VMX - Virtual Machine Technology. */
335	#define X86_CPUID_FEATURE_ECX_VMX RT_BIT(5)
336	/** ECX Bit 7 - EST - Enh. SpeedStep Tech. */
337	#define X86_CPUID_FEATURE_ECX_EST RT_BIT(7)
338	/** ECX Bit 8 - TM2 - Terminal Monitor 2. */
339	#define X86_CPUID_FEATURE_ECX_TM2 RT_BIT(8)
340	/** ECX Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
341	#define X86_CPUID_FEATURE_ECX_SSSE3 RT_BIT(9)
342	/** ECX Bit 10 - CNTX-ID - L1 Context ID. */
343	#define X86_CPUID_FEATURE_ECX_CNTXID RT_BIT(10)
344	/** ECX Bit 13 - CX16 - CMPXCHG16B. */
345	#define X86_CPUID_FEATURE_ECX_CX16 RT_BIT(13)
346	/** ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
347	#define X86_CPUID_FEATURE_ECX_TPRUPDATE RT_BIT(14)
348	/** ECX Bit 23 - POPCOUNT instruction. */
349	#define X86_CPUID_FEATURE_ECX_POPCOUNT RT_BIT(23)
350
351
352	/** Bit 0 - FPU - x87 FPU on Chip. */
353	#define X86_CPUID_FEATURE_EDX_FPU RT_BIT(0)
354	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
355	#define X86_CPUID_FEATURE_EDX_VME RT_BIT(1)
356	/** Bit 2 - DE - Debugging extensions. */
357	#define X86_CPUID_FEATURE_EDX_DE RT_BIT(2)
358	/** Bit 3 - PSE - Page Size Extension. */
359	#define X86_CPUID_FEATURE_EDX_PSE RT_BIT(3)
360	/** Bit 4 - TSC - Time Stamp Counter. */
361	#define X86_CPUID_FEATURE_EDX_TSC RT_BIT(4)
362	/** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
363	#define X86_CPUID_FEATURE_EDX_MSR RT_BIT(5)
364	/** Bit 6 - PAE - Physical Address Extension. */
365	#define X86_CPUID_FEATURE_EDX_PAE RT_BIT(6)
366	/** Bit 7 - MCE - Machine Check Exception. */
367	#define X86_CPUID_FEATURE_EDX_MCE RT_BIT(7)
368	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
369	#define X86_CPUID_FEATURE_EDX_CX8 RT_BIT(8)
370	/** Bit 9 - APIC - APIC On-Chip. */
371	#define X86_CPUID_FEATURE_EDX_APIC RT_BIT(9)
372	/** Bit 11 - SEP - SYSENTER and SYSEXIT. */
373	#define X86_CPUID_FEATURE_EDX_SEP RT_BIT(11)
374	/** Bit 12 - MTRR - Memory Type Range Registers. */
375	#define X86_CPUID_FEATURE_EDX_MTRR RT_BIT(12)
376	/** Bit 13 - PGE - PTE Global Bit. */
377	#define X86_CPUID_FEATURE_EDX_PGE RT_BIT(13)
378	/** Bit 14 - MCA - Machine Check Architecture. */
379	#define X86_CPUID_FEATURE_EDX_MCA RT_BIT(14)
380	/** Bit 15 - CMOV - Conditional Move Instructions. */
381	#define X86_CPUID_FEATURE_EDX_CMOV RT_BIT(15)
382	/** Bit 16 - PAT - Page Attribute Table. */
383	#define X86_CPUID_FEATURE_EDX_PAT RT_BIT(16)
384	/** Bit 17 - PSE-36 - 36-bit Page Size Extention. */
385	#define X86_CPUID_FEATURE_EDX_PSE36 RT_BIT(17)
386	/** Bit 18 - PSN - Processor Serial Number. */
387	#define X86_CPUID_FEATURE_EDX_PSN RT_BIT(18)
388	/** Bit 19 - CLFSH - CLFLUSH Instruction. */
389	#define X86_CPUID_FEATURE_EDX_CLFSH RT_BIT(19)
390	/** Bit 21 - DS - Debug Store. */
391	#define X86_CPUID_FEATURE_EDX_DS RT_BIT(21)
392	/** Bit 22 - ACPI - Termal Monitor and Software Controlled Clock Facilities. */
393	#define X86_CPUID_FEATURE_EDX_ACPI RT_BIT(22)
394	/** Bit 23 - MMX - Intel MMX Technology. */
395	#define X86_CPUID_FEATURE_EDX_MMX RT_BIT(23)
396	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
397	#define X86_CPUID_FEATURE_EDX_FXSR RT_BIT(24)
398	/** Bit 25 - SSE - SSE Support. */
399	#define X86_CPUID_FEATURE_EDX_SSE RT_BIT(25)
400	/** Bit 26 - SSE2 - SSE2 Support. */
401	#define X86_CPUID_FEATURE_EDX_SSE2 RT_BIT(26)
402	/** Bit 27 - SS - Self Snoop. */
403	#define X86_CPUID_FEATURE_EDX_SS RT_BIT(27)
404	/** Bit 28 - HTT - Hyper-Threading Technology. */
405	#define X86_CPUID_FEATURE_EDX_HTT RT_BIT(28)
406	/** Bit 29 - TM - Therm. Monitor. */
407	#define X86_CPUID_FEATURE_EDX_TM RT_BIT(29)
408	/** Bit 31 - PBE - Pending Break Enabled. */
409	#define X86_CPUID_FEATURE_EDX_PBE RT_BIT(31)
410	/** @} */
411
412
413	/** @name CPUID AMD Feature information.
414	* CPUID query with EAX=0x80000001.
415	* @{
416	*/
417	/** Bit 0 - FPU - x87 FPU on Chip. */
418	#define X86_CPUID_AMD_FEATURE_EDX_FPU RT_BIT(0)
419	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
420	#define X86_CPUID_AMD_FEATURE_EDX_VME RT_BIT(1)
421	/** Bit 2 - DE - Debugging extensions. */
422	#define X86_CPUID_AMD_FEATURE_EDX_DE RT_BIT(2)
423	/** Bit 3 - PSE - Page Size Extension. */
424	#define X86_CPUID_AMD_FEATURE_EDX_PSE RT_BIT(3)
425	/** Bit 4 - TSC - Time Stamp Counter. */
426	#define X86_CPUID_AMD_FEATURE_EDX_TSC RT_BIT(4)
427	/** Bit 5 - MSR - K86 Model Specific Registers RDMSR and WRMSR Instructions. */
428	#define X86_CPUID_AMD_FEATURE_EDX_MSR RT_BIT(5)
429	/** Bit 6 - PAE - Physical Address Extension. */
430	#define X86_CPUID_AMD_FEATURE_EDX_PAE RT_BIT(6)
431	/** Bit 7 - MCE - Machine Check Exception. */
432	#define X86_CPUID_AMD_FEATURE_EDX_MCE RT_BIT(7)
433	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
434	#define X86_CPUID_AMD_FEATURE_EDX_CX8 RT_BIT(8)
435	/** Bit 9 - APIC - APIC On-Chip. */
436	#define X86_CPUID_AMD_FEATURE_EDX_APIC RT_BIT(9)
437	/** Bit 11 - SEP - AMD SYSCALL and SYSRET. */
438	#define X86_CPUID_AMD_FEATURE_EDX_SEP RT_BIT(11)
439	/** Bit 12 - MTRR - Memory Type Range Registers. */
440	#define X86_CPUID_AMD_FEATURE_EDX_MTRR RT_BIT(12)
441	/** Bit 13 - PGE - PTE Global Bit. */
442	#define X86_CPUID_AMD_FEATURE_EDX_PGE RT_BIT(13)
443	/** Bit 14 - MCA - Machine Check Architecture. */
444	#define X86_CPUID_AMD_FEATURE_EDX_MCA RT_BIT(14)
445	/** Bit 15 - CMOV - Conditional Move Instructions. */
446	#define X86_CPUID_AMD_FEATURE_EDX_CMOV RT_BIT(15)
447	/** Bit 16 - PAT - Page Attribute Table. */
448	#define X86_CPUID_AMD_FEATURE_EDX_PAT RT_BIT(16)
449	/** Bit 17 - PSE-36 - 36-bit Page Size Extention. */
450	#define X86_CPUID_AMD_FEATURE_EDX_PSE36 RT_BIT(17)
451	/** Bit 20 - NX - AMD No-Execute Page Protection. */
452	#define X86_CPUID_AMD_FEATURE_EDX_NX RT_BIT(20)
453	/** Bit 22 - AXMMX - AMD Extensions to MMX Instructions. */
454	#define X86_CPUID_AMD_FEATURE_EDX_AXMMX RT_BIT(22)
455	/** Bit 23 - MMX - Intel MMX Technology. */
456	#define X86_CPUID_AMD_FEATURE_EDX_MMX RT_BIT(23)
457	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
458	#define X86_CPUID_AMD_FEATURE_EDX_FXSR RT_BIT(24)
459	/** Bit 25 - FFXSR - AMD fast FXSAVE and FXRSTOR Instructions. */
460	#define X86_CPUID_AMD_FEATURE_EDX_FFXSR RT_BIT(25)
461	/** Bit 26 - PAGE1GB - AMD 1GB large page support. */
462	#define X86_CPUID_AMD_FEATURE_EDX_PAGE1GB RT_BIT(26)
463	/** Bit 27 - RDTSCP - AMD RDTSCP instruction. */
464	#define X86_CPUID_AMD_FEATURE_EDX_RDTSCP RT_BIT(27)
465	/** Bit 29 - LM - AMD Long Mode. */
466	#define X86_CPUID_AMD_FEATURE_EDX_LONG_MODE RT_BIT(29)
467	/** Bit 30 - 3DNOWEXT - AMD Extensions to 3DNow. */
468	#define X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX RT_BIT(30)
469	/** Bit 31 - 3DNOW - AMD 3DNow. */
470	#define X86_CPUID_AMD_FEATURE_EDX_3DNOW RT_BIT(31)
471
472	/** Bit 0 - LAHF/SAHF - AMD LAHF and SAHF in 64-bit mode. */
473	#define X86_CPUID_AMD_FEATURE_ECX_LAHF_SAHF RT_BIT(0)
474	/** Bit 1 - CMPL - Core multi-processing legacy mode. */
475	#define X86_CPUID_AMD_FEATURE_ECX_CMPL RT_BIT(1)
476	/** Bit 2 - SVM - AMD VM extensions. */
477	#define X86_CPUID_AMD_FEATURE_ECX_SVM RT_BIT(2)
478	/** Bit 3 - EXTAPIC - AMD extended APIC registers starting at 0x400. */
479	#define X86_CPUID_AMD_FEATURE_ECX_EXT_APIC RT_BIT(3)
480	/** Bit 4 - CR8L - AMD LOCK MOV CR0 means MOV CR8. */
481	#define X86_CPUID_AMD_FEATURE_ECX_CR8L RT_BIT(4)
482	/** Bit 5 - ABM - AMD Advanced bit manipulation. LZCNT instruction support. */
483	#define X86_CPUID_AMD_FEATURE_ECX_ABM RT_BIT(5)
484	/** Bit 6 - SSE4A - AMD EXTRQ, INSERTQ, MOVNTSS, and MOVNTSD instruction support. */
485	#define X86_CPUID_AMD_FEATURE_ECX_SSE4A RT_BIT(6)
486	/** Bit 7 - MISALIGNSSE - AMD Misaligned SSE mode. */
487	#define X86_CPUID_AMD_FEATURE_ECX_MISALNSSE RT_BIT(7)
488	/** Bit 8 - 3DNOWPRF - AMD PREFETCH and PREFETCHW instruction support. */
489	#define X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF RT_BIT(8)
490	/** Bit 9 - OSVW - AMD OS visible workaround. */
491	#define X86_CPUID_AMD_FEATURE_ECX_OSVW RT_BIT(9)
492	/** Bit 12 - SKINIT - AMD SKINIT: SKINIT, STGI, and DEV support. */
493	#define X86_CPUID_AMD_FEATURE_ECX_SKINIT RT_BIT(12)
494	/** Bit 13 - WDT - AMD Watchdog timer support. */
495	#define X86_CPUID_AMD_FEATURE_ECX_WDT RT_BIT(13)
496
497	/** @} */
498
499
500	/** @name CR0
501	* @{ */
502	/** Bit 0 - PE - Protection Enabled */
503	#define X86_CR0_PE RT_BIT(0)
504	#define X86_CR0_PROTECTION_ENABLE RT_BIT(0)
505	/** Bit 1 - MP - Monitor Coprocessor */
506	#define X86_CR0_MP RT_BIT(1)
507	#define X86_CR0_MONITOR_COPROCESSOR RT_BIT(1)
508	/** Bit 2 - EM - Emulation. */
509	#define X86_CR0_EM RT_BIT(2)
510	#define X86_CR0_EMULATE_FPU RT_BIT(2)
511	/** Bit 3 - TS - Task Switch. */
512	#define X86_CR0_TS RT_BIT(3)
513	#define X86_CR0_TASK_SWITCH RT_BIT(3)
514	/** Bit 4 - ET - Extension flag. ('hardcoded' to 1) */
515	#define X86_CR0_ET RT_BIT(4)
516	#define X86_CR0_EXTENSION_TYPE RT_BIT(4)
517	/** Bit 5 - NE - Numeric error. */
518	#define X86_CR0_NE RT_BIT(5)
519	#define X86_CR0_NUMERIC_ERROR RT_BIT(5)
520	/** Bit 16 - WP - Write Protect. */
521	#define X86_CR0_WP RT_BIT(16)
522	#define X86_CR0_WRITE_PROTECT RT_BIT(16)
523	/** Bit 18 - AM - Alignment Mask. */
524	#define X86_CR0_AM RT_BIT(18)
525	#define X86_CR0_ALIGMENT_MASK RT_BIT(18)
526	/** Bit 29 - NW - Not Write-though. */
527	#define X86_CR0_NW RT_BIT(29)
528	#define X86_CR0_NOT_WRITE_THROUGH RT_BIT(29)
529	/** Bit 30 - WP - Cache Disable. */
530	#define X86_CR0_CD RT_BIT(30)
531	#define X86_CR0_CACHE_DISABLE RT_BIT(30)
532	/** Bit 31 - PG - Paging. */
533	#define X86_CR0_PG RT_BIT(31)
534	#define X86_CR0_PAGING RT_BIT(31)
535	/** @} */
536
537
538	/** @name CR3
539	* @{ */
540	/** Bit 3 - PWT - Page-level Writes Transparent. */
541	#define X86_CR3_PWT RT_BIT(3)
542	/** Bit 4 - PCD - Page-level Cache Disable. */
543	#define X86_CR3_PCD RT_BIT(4)
544	/** Bits 12-31 - - Page directory page number. */
545	#define X86_CR3_PAGE_MASK (0xfffff000)
546	/** Bits 5-31 - - PAE Page directory page number. */
547	#define X86_CR3_PAE_PAGE_MASK (0xffffffe0)
548	/** @} */
549
550
551	/** @name CR4
552	* @{ */
553	/** Bit 0 - VME - Virtual-8086 Mode Extensions. */
554	#define X86_CR4_VME RT_BIT(0)
555	/** Bit 1 - PVI - Protected-Mode Virtual Interrupts. */
556	#define X86_CR4_PVI RT_BIT(1)
557	/** Bit 2 - TSD - Time Stamp Disable. */
558	#define X86_CR4_TSD RT_BIT(2)
559	/** Bit 3 - DE - Debugging Extensions. */
560	#define X86_CR4_DE RT_BIT(3)
561	/** Bit 4 - PSE - Page Size Extension. */
562	#define X86_CR4_PSE RT_BIT(4)
563	/** Bit 5 - PAE - Physical Address Extension. */
564	#define X86_CR4_PAE RT_BIT(5)
565	/** Bit 6 - MCE - Machine-Check Enable. */
566	#define X86_CR4_MCE RT_BIT(6)
567	/** Bit 7 - PGE - Page Global Enable. */
568	#define X86_CR4_PGE RT_BIT(7)
569	/** Bit 8 - PCE - Performance-Monitoring Counter Enable. */
570	#define X86_CR4_PCE RT_BIT(8)
571	/** Bit 9 - OSFSXR - Operating System Support for FXSAVE and FXRSTORE instruction. */
572	#define X86_CR4_OSFSXR RT_BIT(9)
573	/** Bit 10 - OSXMMEEXCPT - Operating System Support for Unmasked SIMD Floating-Point Exceptions. */
574	#define X86_CR4_OSXMMEEXCPT RT_BIT(10)
575	/** Bit 13 - VMXE - VMX mode is enabled. */
576	#define X86_CR4_VMXE RT_BIT(13)
577	/** @} */
578
579
580	/** @name DR6
581	* @{ */
582	/** Bit 0 - B0 - Breakpoint 0 condition detected. */
583	#define X86_DR6_B0 RT_BIT(0)
584	/** Bit 1 - B1 - Breakpoint 1 condition detected. */
585	#define X86_DR6_B1 RT_BIT(1)
586	/** Bit 2 - B2 - Breakpoint 2 condition detected. */
587	#define X86_DR6_B2 RT_BIT(2)
588	/** Bit 3 - B3 - Breakpoint 3 condition detected. */
589	#define X86_DR6_B3 RT_BIT(3)
590	/** Bit 13 - BD - Debug register access detected. Corresponds to the X86_DR7_GD bit. */
591	#define X86_DR6_BD RT_BIT(13)
592	/** Bit 14 - BS - Single step */
593	#define X86_DR6_BS RT_BIT(14)
594	/** Bit 15 - BT - Task switch. (TSS T bit.) */
595	#define X86_DR6_BT RT_BIT(15)
596	/** @} */
597
598
599	/** @name DR7
600	* @{ */
601	/** Bit 0 - L0 - Local breakpoint enable. Cleared on task switch. */
602	#define X86_DR7_L0 RT_BIT(0)
603	/** Bit 1 - G0 - Global breakpoint enable. Not cleared on task switch. */
604	#define X86_DR7_G0 RT_BIT(1)
605	/** Bit 2 - L1 - Local breakpoint enable. Cleared on task switch. */
606	#define X86_DR7_L1 RT_BIT(2)
607	/** Bit 3 - G1 - Global breakpoint enable. Not cleared on task switch. */
608	#define X86_DR7_G1 RT_BIT(3)
609	/** Bit 4 - L2 - Local breakpoint enable. Cleared on task switch. */
610	#define X86_DR7_L2 RT_BIT(4)
611	/** Bit 5 - G2 - Global breakpoint enable. Not cleared on task switch. */
612	#define X86_DR7_G2 RT_BIT(5)
613	/** Bit 6 - L3 - Local breakpoint enable. Cleared on task switch. */
614	#define X86_DR7_L3 RT_BIT(6)
615	/** Bit 7 - G3 - Global breakpoint enable. Not cleared on task switch. */
616	#define X86_DR7_G3 RT_BIT(7)
617	/** Bit 8 - LE - Local breakpoint exact. (Not supported (read ignored) by P6 and later.) */
618	#define X86_DR7_LE RT_BIT(8)
619	/** Bit 9 - GE - Local breakpoint exact. (Not supported (read ignored) by P6 and later.) */
620	#define X86_DR7_GE RT_BIT(9)
621
622	/** Bit 13 - GD - General detect enable. Enables emulators to get exceptions when
623	* any DR register is accessed. */
624	#define X86_DR7_GD RT_BIT(13)
625	/** Bit 16 & 17 - R/W0 - Read write field 0. Values X86_DR7_RW_. /
626	#define X86_DR7_RW0_MASK (3 << 16)
627	/** Bit 18 & 19 - LEN0 - Length field 0. Values X86_DR7_LEN_. /
628	#define X86_DR7_LEN0_MASK (3 << 18)
629	/** Bit 20 & 21 - R/W1 - Read write field 0. Values X86_DR7_RW_. /
630	#define X86_DR7_RW1_MASK (3 << 20)
631	/** Bit 22 & 23 - LEN1 - Length field 0. Values X86_DR7_LEN_. /
632	#define X86_DR7_LEN1_MASK (3 << 22)
633	/** Bit 24 & 25 - R/W2 - Read write field 0. Values X86_DR7_RW_. /
634	#define X86_DR7_RW2_MASK (3 << 24)
635	/** Bit 26 & 27 - LEN2 - Length field 0. Values X86_DR7_LEN_. /
636	#define X86_DR7_LEN2_MASK (3 << 26)
637	/** Bit 28 & 29 - R/W3 - Read write field 0. Values X86_DR7_RW_. /
638	#define X86_DR7_RW3_MASK (3 << 28)
639	/** Bit 30 & 31 - LEN3 - Length field 0. Values X86_DR7_LEN_. /
640	#define X86_DR7_LEN3_MASK (3 << 30)
641
642	/** Bits which must be 1s. */
643	#define X86_DR7_MB1_MASK (RT_BIT(10))
644
645	/** Calcs the L bit of Nth breakpoint.
646	* @param iBp The breakpoint number [0..3].
647	*/
648	#define X86_DR7_L(iBp) ( 1 << (iBp * 2) )
649
650	/** Calcs the G bit of Nth breakpoint.
651	* @param iBp The breakpoint number [0..3].
652	*/
653	#define X86_DR7_G(iBp) ( 1 << (iBp * 2 + 1) )
654
655	/** @name Read/Write values.
656	* @{ */
657	/** Break on instruction fetch only. */
658	#define X86_DR7_RW_EO 0
659	/** Break on write only. */
660	#define X86_DR7_RW_WO 1
661	/** Break on I/O read/write. This is only defined if CR4.DE is set. */
662	#define X86_DR7_RW_IO 2
663	/** Break on read or write (but not instruction fetches). */
664	#define X86_DR7_RW_RW 3
665	/** @} */
666
667	/** Shifts a X86_DR7_RW_* value to its right place.
668	* @param iBp The breakpoint number [0..3].
669	* @param fRw One of the X86_DR7_RW_* value.
670	*/
671	#define X86_DR7_RW(iBp, fRw) ( (fRw) << ((iBp) * 4 + 16) )
672
673	/** @name Length values.
674	* @{ */
675	#define X86_DR7_LEN_BYTE 0
676	#define X86_DR7_LEN_WORD 1
677	#define X86_DR7_LEN_QWORD 2 /*< AMD64 long mode only. /
678	#define X86_DR7_LEN_DWORD 3
679	/** @} */
680
681	/** Shifts a X86_DR7_LEN_* value to its right place.
682	* @param iBp The breakpoint number [0..3].
683	* @param cb One of the X86_DR7_LEN_* values.
684	*/
685	#define X86_DR7_LEN(iBp, cb) ( (cb) << ((iBp) * 4 + 18) )
686
687	/** Mask used to check if any breakpoints are enabled. */
688	#define X86_DR7_ENABLED_MASK (RT_BIT(0) \| RT_BIT(1) \| RT_BIT(2) \| RT_BIT(3) \| RT_BIT(4) \| RT_BIT(6) \| RT_BIT(7))
689
690	/** @} */
691
692
693	/** @name Machine Specific Registers
694	* @{
695	*/
696	/** CPU Feature control. */
697	#define MSR_IA32_FEATURE_CONTROL 0x3A
698	#define MSR_IA32_FEATURE_CONTROL_LOCK RT_BIT(0)
699	#define MSR_IA32_FEATURE_CONTROL_VMXON RT_BIT(2)
700
701
702	#ifndef MSR_IA32_SYSENTER_CS /* qemu cpu.h klugde */
703	/** SYSENTER_CS - the R0 CS, indirectly giving R0 SS, R3 CS and R3 DS.
704	* R0 SS == CS + 8
705	* R3 CS == CS + 16
706	* R3 SS == CS + 24
707	*/
708	#define MSR_IA32_SYSENTER_CS 0x174
709	/** SYSENTER_ESP - the R0 ESP. */
710	#define MSR_IA32_SYSENTER_ESP 0x175
711	/** SYSENTER_EIP - the R0 EIP. */
712	#define MSR_IA32_SYSENTER_EIP 0x176
713	#endif
714
715	/** Basic VMX information. */
716	#define MSR_IA32_VMX_BASIC_INFO 0x480
717	/** Allowed settings for pin-based VM execution controls */
718	#define MSR_IA32_VMX_PINBASED_CTLS 0x481
719	/** Allowed settings for proc-based VM execution controls */
720	#define MSR_IA32_VMX_PROCBASED_CTLS 0x482
721	/** Allowed settings for the VMX exit controls. */
722	#define MSR_IA32_VMX_EXIT_CTLS 0x483
723	/** Allowed settings for the VMX entry controls. */
724	#define MSR_IA32_VMX_ENTRY_CTLS 0x484
725	/** Misc VMX info. */
726	#define MSR_IA32_VMX_MISC 0x485
727	/** Fixed cleared bits in CR0. */
728	#define MSR_IA32_VMX_CR0_FIXED0 0x486
729	/** Fixed set bits in CR0. */
730	#define MSR_IA32_VMX_CR0_FIXED1 0x487
731	/** Fixed cleared bits in CR4. */
732	#define MSR_IA32_VMX_CR4_FIXED0 0x488
733	/** Fixed set bits in CR4. */
734	#define MSR_IA32_VMX_CR4_FIXED1 0x489
735	/** Information for enumerating fields in the VMCS. */
736	#define MSR_IA32_VMX_VMCS_ENUM 0x48A
737
738
739	/** K6 EFER - Extended Feature Enable Register. */
740	#define MSR_K6_EFER 0xc0000080
741	/** @todo document EFER */
742	/** Bit 0 - SCE - System call extensions (SYSCALL / SYSRET). (R/W) */
743	#define MSR_K6_EFER_SCE RT_BIT(0)
744	/** Bit 8 - LME - Long mode enabled. (R/W) */
745	#define MSR_K6_EFER_LME RT_BIT(8)
746	/** Bit 10 - LMA - Long mode active. (R) */
747	#define MSR_K6_EFER_LMA RT_BIT(10)
748	/** Bit 11 - NXE - No-Execute Page Protection Enabled. (R/W) */
749	#define MSR_K6_EFER_NXE RT_BIT(11)
750	/** Bit 12 - SVME - Secure VM Extension Enabled. (R/W) */
751	#define MSR_K6_EFER_SVME RT_BIT(12)
752	/** Bit 13 - LMSLE - Long Mode Segment Limit Enable. (R/W?) */
753	#define MSR_K6_EFER_LMSLE RT_BIT(13)
754	/** Bit 14 - FFXSR - Fast FXSAVE / FXRSTOR (skip XMM). (R/W) /
755	#define MSR_K6_EFER_FFXSR RT_BIT(14)
756	/** K6 STAR - SYSCALL/RET targets. */
757	#define MSR_K6_STAR 0xc0000081
758	/** Shift value for getting the SYSRET CS and SS value. */
759	#define MSR_K6_STAR_SYSRET_CS_SS_SHIFT 48
760	/** Shift value for getting the SYSCALL CS and SS value. */
761	#define MSR_K6_STAR_SYSCALL_CS_SS_SHIFT 32
762	/** Selector mask for use after shifting. */
763	#define MSR_K6_STAR_SEL_MASK 0xffff
764	/** The mask which give the SYSCALL EIP. */
765	#define MSR_K6_STAR_SYSCALL_EIP_MASK 0xffffffff
766	/** K6 WHCR - Write Handling Control Register. */
767	#define MSR_K6_WHCR 0xc0000082
768	/** K6 UWCCR - UC/WC Cacheability Control Register. */
769	#define MSR_K6_UWCCR 0xc0000085
770	/** K6 PSOR - Processor State Observability Register. */
771	#define MSR_K6_PSOR 0xc0000087
772	/** K6 PFIR - Page Flush/Invalidate Register. */
773	#define MSR_K6_PFIR 0xc0000088
774
775	#define MSR_K7_EVNTSEL0 0xc0010000
776	#define MSR_K7_EVNTSEL1 0xc0010001
777	#define MSR_K7_EVNTSEL2 0xc0010002
778	#define MSR_K7_EVNTSEL3 0xc0010003
779	#define MSR_K7_PERFCTR0 0xc0010004
780	#define MSR_K7_PERFCTR1 0xc0010005
781	#define MSR_K7_PERFCTR2 0xc0010006
782	#define MSR_K7_PERFCTR3 0xc0010007
783
784	/** K8 LSTAR - Long mode SYSCALL target (RIP). */
785	#define MSR_K8_LSTAR 0xc0000082
786	/** K8 CSTAR - Compatibility mode SYSCALL target (RIP). */
787	#define MSR_K8_CSTAR 0xc0000083
788	/** K8 SF_MASK - SYSCALL flag mask. (aka SFMASK) */
789	#define MSR_K8_SF_MASK 0xc0000084
790	/** K8 FS.base - The 64-bit base FS register. */
791	#define MSR_K8_FS_BASE 0xc0000100
792	/** K8 GS.base - The 64-bit base GS register. */
793	#define MSR_K8_GS_BASE 0xc0000101
794	/** K8 KernelGSbase - Used with SWAPGS. */
795	#define MSR_K8_KERNEL_GS_BASE 0xc0000102
796	#define MSR_K8_TSC_AUX 0xc0000103
797	#define MSR_K8_SYSCFG 0xc0010010
798	#define MSR_K8_HWCR 0xc0010015
799	#define MSR_K8_IORRBASE0 0xc0010016
800	#define MSR_K8_IORRMASK0 0xc0010017
801	#define MSR_K8_IORRBASE1 0xc0010018
802	#define MSR_K8_IORRMASK1 0xc0010019
803	#define MSR_K8_TOP_MEM1 0xc001001a
804	#define MSR_K8_TOP_MEM2 0xc001001d
805	#define MSR_K8_VM_CR 0xc0010114
806	#define MSR_K8_VM_CR_SVM_DISABLE RT_BIT(4)
807
808	#define MSR_K8_IGNNE 0xc0010115
809	#define MSR_K8_SMM_CTL 0xc0010116
810	/** SVM - VM_HSAVE_PA - Physical address for saving and restoring
811	* host state during world switch.
812	*/
813	#define MSR_K8_VM_HSAVE_PA 0xc0010117
814
815	/** @} */
816
817
818	/** @name Page Table / Directory / Directory Pointers / L4.
819	* @{
820	*/
821
822	/** Page table/directory entry as an unsigned integer. */
823	typedef uint32_t X86PGUINT;
824	/** Pointer to a page table/directory table entry as an unsigned integer. */
825	typedef X86PGUINT *PX86PGUINT;
826
827	/** Number of entries in a 32-bit PT/PD. */
828	#define X86_PG_ENTRIES 1024
829
830
831	/** PAE page table/page directory/pdptr/l4/l5 entry as an unsigned integer. */
832	typedef uint64_t X86PGPAEUINT;
833	/** Pointer to a PAE page table/page directory/pdptr/l4/l5 entry as an unsigned integer. */
834	typedef X86PGPAEUINT *PX86PGPAEUINT;
835
836	/** Number of entries in a PAE PT/PD/PDPTR/L4/L5. */
837	#define X86_PG_PAE_ENTRIES 512
838
839
840	/** The size of a 4KB page. */
841	#define X86_PAGE_4K_SIZE _4K
842	/** The page shift of a 4KB page. */
843	#define X86_PAGE_4K_SHIFT 12
844	/** The 4KB page offset mask. */
845	#define X86_PAGE_4K_OFFSET_MASK 0xfff
846	/** The 4KB page base mask for virtual addresses. */
847	#define X86_PAGE_4K_BASE_MASK 0xfffffffffffff000ULL
848	/** The 4KB page base mask for virtual addresses - 32bit version. */
849	#define X86_PAGE_4K_BASE_MASK_32 0xfffff000U
850
851	/** The size of a 2MB page. */
852	#define X86_PAGE_2M_SIZE _2M
853	/** The page shift of a 2MB page. */
854	#define X86_PAGE_2M_SHIFT 21
855	/** The 2MB page offset mask. */
856	#define X86_PAGE_2M_OFFSET_MASK 0x001fffff
857	/** The 2MB page base mask for virtual addresses. */
858	#define X86_PAGE_2M_BASE_MASK 0xffffffffffe00000ULL
859	/** The 2MB page base mask for virtual addresses - 32bit version. */
860	#define X86_PAGE_2M_BASE_MASK_32 0xffe00000U
861
862	/** The size of a 4MB page. */
863	#define X86_PAGE_4M_SIZE _4M
864	/** The page shift of a 4MB page. */
865	#define X86_PAGE_4M_SHIFT 22
866	/** The 4MB page offset mask. */
867	#define X86_PAGE_4M_OFFSET_MASK 0x003fffff
868	/** The 4MB page base mask for virtual addresses. */
869	#define X86_PAGE_4M_BASE_MASK 0xffffffffffc00000ULL
870	/** The 4MB page base mask for virtual addresses - 32bit version. */
871	#define X86_PAGE_4M_BASE_MASK_32 0xffc00000U
872
873
874
875	/** @name Page Table Entry
876	* @{
877	*/
878	/** Bit 0 - P - Present bit. */
879	#define X86_PTE_P RT_BIT(0)
880	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
881	#define X86_PTE_RW RT_BIT(1)
882	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
883	#define X86_PTE_US RT_BIT(2)
884	/** Bit 3 - PWT - Page level write thru bit. */
885	#define X86_PTE_PWT RT_BIT(3)
886	/** Bit 4 - PCD - Page level cache disable bit. */
887	#define X86_PTE_PCD RT_BIT(4)
888	/** Bit 5 - A - Access bit. */
889	#define X86_PTE_A RT_BIT(5)
890	/** Bit 6 - D - Dirty bit. */
891	#define X86_PTE_D RT_BIT(6)
892	/** Bit 7 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
893	#define X86_PTE_PAT RT_BIT(7)
894	/** Bit 8 - G - Global flag. */
895	#define X86_PTE_G RT_BIT(8)
896	/** Bits 9-11 - - Available for use to system software. */
897	#define X86_PTE_AVL_MASK (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
898	/** Bits 12-31 - - Physical Page number of the next level. */
899	#define X86_PTE_PG_MASK ( 0xfffff000 )
900
901	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
902	#if 1 /* we're using this internally and have to mask of the top 16-bit. */
903	#define X86_PTE_PAE_PG_MASK ( 0x0000fffffffff000ULL )
904	#else
905	#define X86_PTE_PAE_PG_MASK ( 0x000ffffffffff000ULL )
906	#endif
907	/** Bits 63 - NX - PAE - No execution flag. */
908	#define X86_PTE_PAE_NX RT_BIT_64(63)
909
910	/**
911	* Page table entry.
912	*/
913	typedef struct X86PTEBITS
914	{
915	/** Flags whether(=1) or not the page is present. */
916	unsigned u1Present : 1;
917	/** Read(=0) / Write(=1) flag. */
918	unsigned u1Write : 1;
919	/** User(=1) / Supervisor (=0) flag. */
920	unsigned u1User : 1;
921	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
922	unsigned u1WriteThru : 1;
923	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
924	unsigned u1CacheDisable : 1;
925	/** Accessed flag.
926	* Indicates that the page have been read or written to. */
927	unsigned u1Accessed : 1;
928	/** Dirty flag.
929	* Indicates that the page have been written to. */
930	unsigned u1Dirty : 1;
931	/** Reserved / If PAT enabled, bit 2 of the index. */
932	unsigned u1PAT : 1;
933	/** Global flag. (Ignored in all but final level.) */
934	unsigned u1Global : 1;
935	/** Available for use to system software. */
936	unsigned u3Available : 3;
937	/** Physical Page number of the next level. */
938	unsigned u20PageNo : 20;
939	} X86PTEBITS;
940	/** Pointer to a page table entry. */
941	typedef X86PTEBITS *PX86PTEBITS;
942	/** Pointer to a const page table entry. */
943	typedef const X86PTEBITS *PCX86PTEBITS;
944
945	/**
946	* Page table entry.
947	*/
948	typedef union X86PTE
949	{
950	/** Bit field view. */
951	X86PTEBITS n;
952	/** Unsigned integer view */
953	X86PGUINT u;
954	/** 32-bit view. */
955	uint32_t au32[1];
956	/** 16-bit view. */
957	uint16_t au16[2];
958	/** 8-bit view. */
959	uint8_t au8[4];
960	} X86PTE;
961	/** Pointer to a page table entry. */
962	typedef X86PTE *PX86PTE;
963	/** Pointer to a const page table entry. */
964	typedef const X86PTE *PCX86PTE;
965
966
967	/**
968	* PAE page table entry.
969	*/
970	typedef struct X86PTEPAEBITS
971	{
972	/** Flags whether(=1) or not the page is present. */
973	uint32_t u1Present : 1;
974	/** Read(=0) / Write(=1) flag. */
975	uint32_t u1Write : 1;
976	/** User(=1) / Supervisor(=0) flag. */
977	uint32_t u1User : 1;
978	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
979	uint32_t u1WriteThru : 1;
980	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
981	uint32_t u1CacheDisable : 1;
982	/** Accessed flag.
983	* Indicates that the page have been read or written to. */
984	uint32_t u1Accessed : 1;
985	/** Dirty flag.
986	* Indicates that the page have been written to. */
987	uint32_t u1Dirty : 1;
988	/** Reserved / If PAT enabled, bit 2 of the index. */
989	uint32_t u1PAT : 1;
990	/** Global flag. (Ignored in all but final level.) */
991	uint32_t u1Global : 1;
992	/** Available for use to system software. */
993	uint32_t u3Available : 3;
994	/** Physical Page number of the next level - Low Part. Don't use this. */
995	uint32_t u20PageNoLow : 20;
996	/** Physical Page number of the next level - High Part. Don't use this. */
997	uint32_t u20PageNoHigh : 20;
998	/** MBZ bits */
999	uint32_t u11Reserved : 11;
1000	/** No Execute flag. */
1001	uint32_t u1NoExecute : 1;
1002	} X86PTEPAEBITS;
1003	/** Pointer to a page table entry. */
1004	typedef X86PTEPAEBITS *PX86PTEPAEBITS;
1005	/** Pointer to a page table entry. */
1006	typedef const X86PTEPAEBITS *PCX86PTEPAEBITS;
1007
1008	/**
1009	* PAE Page table entry.
1010	*/
1011	typedef union X86PTEPAE
1012	{
1013	/** Bit field view. */
1014	X86PTEPAEBITS n;
1015	/** Unsigned integer view */
1016	X86PGPAEUINT u;
1017	/** 32-bit view. */
1018	uint32_t au32[2];
1019	/** 16-bit view. */
1020	uint16_t au16[4];
1021	/** 8-bit view. */
1022	uint8_t au8[8];
1023	} X86PTEPAE;
1024	/** Pointer to a PAE page table entry. */
1025	typedef X86PTEPAE *PX86PTEPAE;
1026	/** Pointer to a const PAE page table entry. */
1027	typedef const X86PTEPAE *PCX86PTEPAE;
1028	/** @} */
1029
1030	/**
1031	* Page table.
1032	*/
1033	typedef struct X86PT
1034	{
1035	/** PTE Array. */
1036	X86PTE a[X86_PG_ENTRIES];
1037	} X86PT;
1038	/** Pointer to a page table. */
1039	typedef X86PT *PX86PT;
1040	/** Pointer to a const page table. */
1041	typedef const X86PT *PCX86PT;
1042
1043	/** The page shift to get the PT index. */
1044	#define X86_PT_SHIFT 12
1045	/** The PT index mask (apply to a shifted page address). */
1046	#define X86_PT_MASK 0x3ff
1047
1048
1049	/**
1050	* Page directory.
1051	*/
1052	typedef struct X86PTPAE
1053	{
1054	/** PTE Array. */
1055	X86PTEPAE a[X86_PG_PAE_ENTRIES];
1056	} X86PTPAE;
1057	/** Pointer to a page table. */
1058	typedef X86PTPAE *PX86PTPAE;
1059	/** Pointer to a const page table. */
1060	typedef const X86PTPAE *PCX86PTPAE;
1061
1062	/** The page shift to get the PA PTE index. */
1063	#define X86_PT_PAE_SHIFT 12
1064	/** The PAE PT index mask (apply to a shifted page address). */
1065	#define X86_PT_PAE_MASK 0x1ff
1066
1067
1068	/** @name 4KB Page Directory Entry
1069	* @{
1070	*/
1071	/** Bit 0 - P - Present bit. */
1072	#define X86_PDE_P RT_BIT(0)
1073	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1074	#define X86_PDE_RW RT_BIT(1)
1075	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1076	#define X86_PDE_US RT_BIT(2)
1077	/** Bit 3 - PWT - Page level write thru bit. */
1078	#define X86_PDE_PWT RT_BIT(3)
1079	/** Bit 4 - PCD - Page level cache disable bit. */
1080	#define X86_PDE_PCD RT_BIT(4)
1081	/** Bit 5 - A - Access bit. */
1082	#define X86_PDE_A RT_BIT(5)
1083	/** Bit 7 - PS - Page size attribute.
1084	* Clear mean 4KB pages, set means large pages (2/4MB). */
1085	#define X86_PDE_PS RT_BIT(7)
1086	/** Bits 9-11 - - Available for use to system software. */
1087	#define X86_PDE_AVL_MASK (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
1088	/** Bits 12-31 - - Physical Page number of the next level. */
1089	#define X86_PDE_PG_MASK ( 0xfffff000 )
1090
1091	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1092	#if 1 /* we're using this internally and have to mask of the top 16-bit. */
1093	#define X86_PDE_PAE_PG_MASK ( 0x0000fffffffff000ULL )
1094	#else
1095	#define X86_PDE_PAE_PG_MASK ( 0x000ffffffffff000ULL )
1096	#endif
1097	/** Bits 63 - NX - PAE - No execution flag. */
1098	#define X86_PDE_PAE_NX RT_BIT_64(63)
1099
1100	/**
1101	* Page directory entry.
1102	*/
1103	typedef struct X86PDEBITS
1104	{
1105	/** Flags whether(=1) or not the page is present. */
1106	unsigned u1Present : 1;
1107	/** Read(=0) / Write(=1) flag. */
1108	unsigned u1Write : 1;
1109	/** User(=1) / Supervisor (=0) flag. */
1110	unsigned u1User : 1;
1111	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1112	unsigned u1WriteThru : 1;
1113	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1114	unsigned u1CacheDisable : 1;
1115	/** Accessed flag.
1116	* Indicates that the page have been read or written to. */
1117	unsigned u1Accessed : 1;
1118	/** Reserved / Ignored (dirty bit). */
1119	unsigned u1Reserved0 : 1;
1120	/** Size bit if PSE is enabled - in any event it's 0. */
1121	unsigned u1Size : 1;
1122	/** Reserved / Ignored (global bit). */
1123	unsigned u1Reserved1 : 1;
1124	/** Available for use to system software. */
1125	unsigned u3Available : 3;
1126	/** Physical Page number of the next level. */
1127	unsigned u20PageNo : 20;
1128	} X86PDEBITS;
1129	/** Pointer to a page directory entry. */
1130	typedef X86PDEBITS *PX86PDEBITS;
1131	/** Pointer to a const page directory entry. */
1132	typedef const X86PDEBITS *PCX86PDEBITS;
1133
1134
1135	/**
1136	* PAE page directory entry.
1137	*/
1138	typedef struct X86PDEPAEBITS
1139	{
1140	/** Flags whether(=1) or not the page is present. */
1141	uint32_t u1Present : 1;
1142	/** Read(=0) / Write(=1) flag. */
1143	uint32_t u1Write : 1;
1144	/** User(=1) / Supervisor (=0) flag. */
1145	uint32_t u1User : 1;
1146	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1147	uint32_t u1WriteThru : 1;
1148	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1149	uint32_t u1CacheDisable : 1;
1150	/** Accessed flag.
1151	* Indicates that the page have been read or written to. */
1152	uint32_t u1Accessed : 1;
1153	/** Reserved / Ignored (dirty bit). */
1154	uint32_t u1Reserved0 : 1;
1155	/** Size bit if PSE is enabled - in any event it's 0. */
1156	uint32_t u1Size : 1;
1157	/** Reserved / Ignored (global bit). / */
1158	uint32_t u1Reserved1 : 1;
1159	/** Available for use to system software. */
1160	uint32_t u3Available : 3;
1161	/** Physical Page number of the next level - Low Part. Don't use! */
1162	uint32_t u20PageNoLow : 20;
1163	/** Physical Page number of the next level - High Part. Don't use! */
1164	uint32_t u20PageNoHigh : 20;
1165	/** MBZ bits */
1166	uint32_t u11Reserved : 11;
1167	/** No Execute flag. */
1168	uint32_t u1NoExecute : 1;
1169	} X86PDEPAEBITS;
1170	/** Pointer to a page directory entry. */
1171	typedef X86PDEPAEBITS *PX86PDEPAEBITS;
1172	/** Pointer to a const page directory entry. */
1173	typedef const X86PDEPAEBITS *PCX86PDEPAEBITS;
1174
1175	/** @} */
1176
1177
1178	/** @name 2/4MB Page Directory Entry
1179	* @{
1180	*/
1181	/** Bit 0 - P - Present bit. */
1182	#define X86_PDE4M_P RT_BIT(0)
1183	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1184	#define X86_PDE4M_RW RT_BIT(1)
1185	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1186	#define X86_PDE4M_US RT_BIT(2)
1187	/** Bit 3 - PWT - Page level write thru bit. */
1188	#define X86_PDE4M_PWT RT_BIT(3)
1189	/** Bit 4 - PCD - Page level cache disable bit. */
1190	#define X86_PDE4M_PCD RT_BIT(4)
1191	/** Bit 5 - A - Access bit. */
1192	#define X86_PDE4M_A RT_BIT(5)
1193	/** Bit 6 - D - Dirty bit. */
1194	#define X86_PDE4M_D RT_BIT(6)
1195	/** Bit 7 - PS - Page size attribute. Clear mean 4KB pages, set means large pages (2/4MB). */
1196	#define X86_PDE4M_PS RT_BIT(7)
1197	/** Bit 8 - G - Global flag. */
1198	#define X86_PDE4M_G RT_BIT(8)
1199	/** Bits 9-11 - AVL - Available for use to system software. */
1200	#define X86_PDE4M_AVL (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
1201	/** Bit 12 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
1202	#define X86_PDE4M_PAT RT_BIT(12)
1203	/** Shift to get from X86_PTE_PAT to X86_PDE4M_PAT. */
1204	#define X86_PDE4M_PAT_SHIFT (12 - 7)
1205	/** Bits 22-31 - - Physical Page number. */
1206	#define X86_PDE4M_PG_MASK ( 0xffc00000 )
1207	/** Bits 13-20 - - Physical Page number high part (32-39 bits). AMD64 hack. */
1208	#define X86_PDE4M_PG_HIGH_MASK ( 0x001fe000 )
1209	/** The number of bits to the high part of the page number. */
1210	#define X86_PDE4M_PG_HIGH_SHIFT 19
1211
1212	/** Bits 12-51 - - PAE - Physical Page number. */
1213	#define X86_PDE4M_PAE_PG_MASK ( 0x000fffffffc00000ULL )
1214	/** Bits 63 - NX - PAE - No execution flag. */
1215	#define X86_PDE4M_PAE_NX RT_BIT_64(63)
1216
1217	/**
1218	* 4MB page directory entry.
1219	*/
1220	typedef struct X86PDE4MBITS
1221	{
1222	/** Flags whether(=1) or not the page is present. */
1223	unsigned u1Present : 1;
1224	/** Read(=0) / Write(=1) flag. */
1225	unsigned u1Write : 1;
1226	/** User(=1) / Supervisor (=0) flag. */
1227	unsigned u1User : 1;
1228	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1229	unsigned u1WriteThru : 1;
1230	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1231	unsigned u1CacheDisable : 1;
1232	/** Accessed flag.
1233	* Indicates that the page have been read or written to. */
1234	unsigned u1Accessed : 1;
1235	/** Dirty flag.
1236	* Indicates that the page have been written to. */
1237	unsigned u1Dirty : 1;
1238	/** Page size flag - always 1 for 4MB entries. */
1239	unsigned u1Size : 1;
1240	/** Global flag. */
1241	unsigned u1Global : 1;
1242	/** Available for use to system software. */
1243	unsigned u3Available : 3;
1244	/** Reserved / If PAT enabled, bit 2 of the index. */
1245	unsigned u1PAT : 1;
1246	/** Bits 32-39 of the page number on AMD64.
1247	* This AMD64 hack allows accessing 40bits of physical memory without PAE. */
1248	unsigned u8PageNoHigh : 8;
1249	/** Reserved. */
1250	unsigned u1Reserved : 1;
1251	/** Physical Page number of the page. */
1252	unsigned u10PageNo : 10;
1253	} X86PDE4MBITS;
1254	/** Pointer to a page table entry. */
1255	typedef X86PDE4MBITS *PX86PDE4MBITS;
1256	/** Pointer to a const page table entry. */
1257	typedef const X86PDE4MBITS *PCX86PDE4MBITS;
1258
1259
1260	/**
1261	* 2MB PAE page directory entry.
1262	*/
1263	typedef struct X86PDE2MPAEBITS
1264	{
1265	/** Flags whether(=1) or not the page is present. */
1266	uint32_t u1Present : 1;
1267	/** Read(=0) / Write(=1) flag. */
1268	uint32_t u1Write : 1;
1269	/** User(=1) / Supervisor(=0) flag. */
1270	uint32_t u1User : 1;
1271	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1272	uint32_t u1WriteThru : 1;
1273	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1274	uint32_t u1CacheDisable : 1;
1275	/** Accessed flag.
1276	* Indicates that the page have been read or written to. */
1277	uint32_t u1Accessed : 1;
1278	/** Dirty flag.
1279	* Indicates that the page have been written to. */
1280	uint32_t u1Dirty : 1;
1281	/** Page size flag - always 1 for 2MB entries. */
1282	uint32_t u1Size : 1;
1283	/** Global flag. */
1284	uint32_t u1Global : 1;
1285	/** Available for use to system software. */
1286	uint32_t u3Available : 3;
1287	/** Reserved / If PAT enabled, bit 2 of the index. */
1288	uint32_t u1PAT : 1;
1289	/** Reserved. */
1290	uint32_t u9Reserved : 9;
1291	/** Physical Page number of the next level - Low part. Don't use! */
1292	uint32_t u10PageNoLow : 10;
1293	/** Physical Page number of the next level - High part. Don't use! */
1294	uint32_t u20PageNoHigh : 20;
1295	/** MBZ bits */
1296	uint32_t u11Reserved : 11;
1297	/** No Execute flag. */
1298	uint32_t u1NoExecute : 1;
1299	} X86PDE2MPAEBITS;
1300	/** Pointer to a 4MB PAE page table entry. */
1301	typedef X86PDE2MPAEBITS *PX86PDE2MPAEBITS;
1302	/** Pointer to a 4MB PAE page table entry. */
1303	typedef const X86PDE2MPAEBITS *PCX86PDE2MPAEBITS;
1304
1305	/** @} */
1306
1307	/**
1308	* Page directory entry.
1309	*/
1310	typedef union X86PDE
1311	{
1312	/** Normal view. */
1313	X86PDEBITS n;
1314	/** 4MB view (big). */
1315	X86PDE4MBITS b;
1316	/** Unsigned integer view. */
1317	X86PGUINT u;
1318	/** 8 bit unsigned integer view. */
1319	uint8_t au8[4];
1320	/** 16 bit unsigned integer view. */
1321	uint16_t au16[2];
1322	/** 32 bit unsigned integer view. */
1323	uint32_t au32[1];
1324	} X86PDE;
1325	/** Pointer to a page directory entry. */
1326	typedef X86PDE *PX86PDE;
1327	/** Pointer to a const page directory entry. */
1328	typedef const X86PDE *PCX86PDE;
1329
1330	/**
1331	* PAE page directory entry.
1332	*/
1333	typedef union X86PDEPAE
1334	{
1335	/** Normal view. */
1336	X86PDEPAEBITS n;
1337	/** 2MB page view (big). */
1338	X86PDE2MPAEBITS b;
1339	/** Unsigned integer view. */
1340	X86PGPAEUINT u;
1341	/** 8 bit unsigned integer view. */
1342	uint8_t au8[8];
1343	/** 16 bit unsigned integer view. */
1344	uint16_t au16[4];
1345	/** 32 bit unsigned integer view. */
1346	uint32_t au32[2];
1347	} X86PDEPAE;
1348	/** Pointer to a page directory entry. */
1349	typedef X86PDEPAE *PX86PDEPAE;
1350	/** Pointer to a const page directory entry. */
1351	typedef const X86PDEPAE *PCX86PDEPAE;
1352
1353	/**
1354	* Page directory.
1355	*/
1356	typedef struct X86PD
1357	{
1358	/** PDE Array. */
1359	X86PDE a[X86_PG_ENTRIES];
1360	} X86PD;
1361	/** Pointer to a page directory. */
1362	typedef X86PD *PX86PD;
1363	/** Pointer to a const page directory. */
1364	typedef const X86PD *PCX86PD;
1365
1366	/** The page shift to get the PD index. */
1367	#define X86_PD_SHIFT 22
1368	/** The PD index mask (apply to a shifted page address). */
1369	#define X86_PD_MASK 0x3ff
1370
1371
1372	/**
1373	* PAE page directory.
1374	*/
1375	typedef struct X86PDPAE
1376	{
1377	/** PDE Array. */
1378	X86PDEPAE a[X86_PG_PAE_ENTRIES];
1379	} X86PDPAE;
1380	/** Pointer to a PAE page directory. */
1381	typedef X86PDPAE *PX86PDPAE;
1382	/** Pointer to a const PAE page directory. */
1383	typedef const X86PDPAE *PCX86PDPAE;
1384
1385	/** The page shift to get the PAE PD index. */
1386	#define X86_PD_PAE_SHIFT 21
1387	/** The PAE PD index mask (apply to a shifted page address). */
1388	#define X86_PD_PAE_MASK 0x1ff
1389
1390
1391	/** @name Page Directory Pointer Table Entry (PAE)
1392	* @{
1393	*/
1394	/** Bit 0 - P - Present bit. */
1395	#define X86_PDPE_P RT_BIT(0)
1396	/** Bit 1 - R/W - Read (clear) / Write (set) bit. Long Mode only. */
1397	#define X86_PDPE_RW RT_BIT(1)
1398	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. Long Mode only. */
1399	#define X86_PDPE_US RT_BIT(2)
1400	/** Bit 3 - PWT - Page level write thru bit. */
1401	#define X86_PDPE_PWT RT_BIT(3)
1402	/** Bit 4 - PCD - Page level cache disable bit. */
1403	#define X86_PDPE_PCD RT_BIT(4)
1404	/** Bit 5 - A - Access bit. Long Mode only. */
1405	#define X86_PDPE_A RT_BIT(5)
1406	/** Bits 9-11 - - Available for use to system software. */
1407	#define X86_PDPE_AVL_MASK (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
1408	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1409	#if 1 /* we're using this internally and have to mask of the top 16-bit. */
1410	#define X86_PDPE_PG_MASK ( 0x0000fffffffff000ULL )
1411	#else
1412	#define X86_PDPE_PG_MASK ( 0x000ffffffffff000ULL )
1413	#endif
1414	/** Bits 63 - NX - PAE - No execution flag. */
1415	#define X86_PDPE_NX RT_BIT_64(63)
1416
1417	/**
1418	* Page directory pointer table entry.
1419	*/
1420	typedef struct X86PDPEBITS
1421	{
1422	/** Flags whether(=1) or not the page is present. */
1423	uint32_t u1Present : 1;
1424	/** Read(=0) / Write(=1) flag. */
1425	uint32_t u1Write : 1;
1426	/** User(=1) / Supervisor (=0) flag. */
1427	uint32_t u1User : 1;
1428	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1429	uint32_t u1WriteThru : 1;
1430	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1431	uint32_t u1CacheDisable : 1;
1432	/** Accessed flag.
1433	* Indicates that the page have been read or written to. */
1434	uint32_t u1Accessed : 1;
1435	/** Chunk of reserved bits. */
1436	uint32_t u3Reserved : 3;
1437	/** Available for use to system software. */
1438	uint32_t u3Available : 3;
1439	/** Physical Page number of the next level - Low Part. Don't use! */
1440	uint32_t u20PageNoLow : 20;
1441	/** Physical Page number of the next level - High Part. Don't use! */
1442	uint32_t u20PageNoHigh : 20;
1443	/** MBZ bits */
1444	uint32_t u11Reserved : 11;
1445	/** No Execute flag. */
1446	uint32_t u1NoExecute : 1;
1447	} X86PDPEBITS;
1448	/** Pointer to a page directory pointer table entry. */
1449	typedef X86PDPEBITS *PX86PTPEBITS;
1450	/** Pointer to a const page directory pointer table entry. */
1451	typedef const X86PDPEBITS *PCX86PTPEBITS;
1452
1453	/**
1454	* Page directory pointer table entry.
1455	*/
1456	typedef union X86PDPE
1457	{
1458	/** Normal view. */
1459	X86PDPEBITS n;
1460	/** Unsigned integer view. */
1461	X86PGPAEUINT u;
1462	/** 8 bit unsigned integer view. */
1463	uint8_t au8[8];
1464	/** 16 bit unsigned integer view. */
1465	uint16_t au16[4];
1466	/** 32 bit unsigned integer view. */
1467	uint32_t au32[2];
1468	} X86PDPE;
1469	/** Pointer to a page directory pointer table entry. */
1470	typedef X86PDPE *PX86PDPE;
1471	/** Pointer to a const page directory pointer table entry. */
1472	typedef const X86PDPE *PCX86PDPE;
1473
1474
1475	/**
1476	* Page directory pointer table.
1477	*/
1478	typedef struct X86PDPTR
1479	{
1480	/** PDE Array. */
1481	X86PDPE a[X86_PG_PAE_ENTRIES];
1482	} X86PDPTR;
1483	/** Pointer to a page directory pointer table. */
1484	typedef X86PDPTR *PX86PDPTR;
1485	/** Pointer to a const page directory pointer table. */
1486	typedef const X86PDPTR *PCX86PDPTR;
1487
1488	/** The page shift to get the PDPTR index. */
1489	#define X86_PDPTR_SHIFT 30
1490	/** The PDPTR index mask (apply to a shifted page address). (32 bits PAE) */
1491	#define X86_PDPTR_MASK_32 0x3
1492	/** The PDPTR index mask (apply to a shifted page address). (64 bits PAE)*/
1493	#define X86_PDPTR_MASK 0x1ff
1494
1495	/** @} */
1496
1497
1498	/** @name Page Map Level-4 Entry (Long Mode PAE)
1499	* @{
1500	*/
1501	/** Bit 0 - P - Present bit. */
1502	#define X86_PML4E_P RT_BIT(0)
1503	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1504	#define X86_PML4E_RW RT_BIT(1)
1505	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1506	#define X86_PML4E_US RT_BIT(2)
1507	/** Bit 3 - PWT - Page level write thru bit. */
1508	#define X86_PML4E_PWT RT_BIT(3)
1509	/** Bit 4 - PCD - Page level cache disable bit. */
1510	#define X86_PML4E_PCD RT_BIT(4)
1511	/** Bit 5 - A - Access bit. */
1512	#define X86_PML4E_A RT_BIT(5)
1513	/** Bits 9-11 - - Available for use to system software. */
1514	#define X86_PML4E_AVL_MASK (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
1515	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1516	#if 1 /* we're using this internally and have to mask of the top 16-bit. */
1517	#define X86_PML4E_PG_MASK ( 0x0000fffffffff000ULL )
1518	#else
1519	#define X86_PML4E_PG_MASK ( 0x000ffffffffff000ULL )
1520	#endif
1521	/** Bits 63 - NX - PAE - No execution flag. */
1522	#define X86_PML4E_NX RT_BIT_64(63)
1523
1524	/**
1525	* Page Map Level-4 Entry
1526	*/
1527	typedef struct X86PML4EBITS
1528	{
1529	/** Flags whether(=1) or not the page is present. */
1530	uint32_t u1Present : 1;
1531	/** Read(=0) / Write(=1) flag. */
1532	uint32_t u1Write : 1;
1533	/** User(=1) / Supervisor (=0) flag. */
1534	uint32_t u1User : 1;
1535	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1536	uint32_t u1WriteThru : 1;
1537	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1538	uint32_t u1CacheDisable : 1;
1539	/** Accessed flag.
1540	* Indicates that the page have been read or written to. */
1541	uint32_t u1Accessed : 1;
1542	/** Chunk of reserved bits. */
1543	uint32_t u3Reserved : 3;
1544	/** Available for use to system software. */
1545	uint32_t u3Available : 3;
1546	/** Physical Page number of the next level - Low Part. Don't use! */
1547	uint32_t u20PageNoLow : 20;
1548	/** Physical Page number of the next level - High Part. Don't use! */
1549	uint32_t u20PageNoHigh : 20;
1550	/** MBZ bits */
1551	uint32_t u11Reserved : 11;
1552	/** No Execute flag. */
1553	uint32_t u1NoExecute : 1;
1554	} X86PML4EBITS;
1555	/** Pointer to a page map level-4 entry. */
1556	typedef X86PML4EBITS *PX86PML4EBITS;
1557	/** Pointer to a const page map level-4 entry. */
1558	typedef const X86PML4EBITS *PCX86PML4EBITS;
1559
1560	/**
1561	* Page Map Level-4 Entry.
1562	*/
1563	typedef union X86PML4E
1564	{
1565	/** Normal view. */
1566	X86PML4EBITS n;
1567	/** Unsigned integer view. */
1568	X86PGPAEUINT u;
1569	/** 8 bit unsigned integer view. */
1570	uint8_t au8[8];
1571	/** 16 bit unsigned integer view. */
1572	uint16_t au16[4];
1573	/** 32 bit unsigned integer view. */
1574	uint32_t au32[2];
1575	} X86PML4E;
1576	/** Pointer to a page map level-4 entry. */
1577	typedef X86PML4E *PX86PML4E;
1578	/** Pointer to a const page map level-4 entry. */
1579	typedef const X86PML4E *PCX86PML4E;
1580
1581
1582	/**
1583	* Page Map Level-4.
1584	*/
1585	typedef struct X86PML4
1586	{
1587	/** PDE Array. */
1588	X86PML4E a[X86_PG_PAE_ENTRIES];
1589	} X86PML4;
1590	/** Pointer to a page map level-4. */
1591	typedef X86PML4 *PX86PML4;
1592	/** Pointer to a const page map level-4. */
1593	typedef const X86PML4 *PCX86PML4;
1594
1595	/** The page shift to get the PML4 index. */
1596	#define X86_PML4_SHIFT 39
1597	/** The PML4 index mask (apply to a shifted page address). */
1598	#define X86_PML4_MASK 0x1ff
1599
1600	/** @} */
1601
1602	/** @} */
1603
1604
1605	/**
1606	* 80-bit MMX/FPU register type.
1607	*/
1608	typedef struct X86FPUMMX
1609	{
1610	uint8_t reg[10];
1611	} X86FPUMMX;
1612	/** Pointer to a 80-bit MMX/FPU register type. */
1613	typedef X86FPUMMX *PX86FPUMMX;
1614	/** Pointer to a const 80-bit MMX/FPU register type. */
1615	typedef const X86FPUMMX *PCX86FPUMMX;
1616
1617	/**
1618	* FPU state (aka FSAVE/FRSTOR Memory Region).
1619	*/
1620	#pragma pack(1)
1621	typedef struct X86FPUSTATE
1622	{
1623	/** Control word. */
1624	uint16_t FCW;
1625	/** Alignment word */
1626	uint16_t Dummy1;
1627	/** Status word. */
1628	uint16_t FSW;
1629	/** Alignment word */
1630	uint16_t Dummy2;
1631	/** Tag word */
1632	uint16_t FTW;
1633	/** Alignment word */
1634	uint16_t Dummy3;
1635
1636	/** Instruction pointer. */
1637	uint32_t FPUIP;
1638	/** Code selector. */
1639	uint16_t CS;
1640	/** Opcode. */
1641	uint16_t FOP;
1642	/** FOO. */
1643	uint32_t FPUOO;
1644	/** FOS. */
1645	uint32_t FPUOS;
1646	/** FPU view - todo. */
1647	X86FPUMMX regs[8];
1648	} X86FPUSTATE;
1649	#pragma pack()
1650	/** Pointer to a FPU state. */
1651	typedef X86FPUSTATE *PX86FPUSTATE;
1652	/** Pointer to a const FPU state. */
1653	typedef const X86FPUSTATE *PCX86FPUSTATE;
1654
1655	/**
1656	* FPU Extended state (aka FXSAVE/FXRSTORE Memory Region).
1657	*/
1658	#pragma pack(1)
1659	typedef struct X86FXSTATE
1660	{
1661	/** Control word. */
1662	uint16_t FCW;
1663	/** Status word. */
1664	uint16_t FSW;
1665	/** Tag word (it's a byte actually). */
1666	uint8_t FTW;
1667	uint8_t huh1;
1668	/** Opcode. */
1669	uint16_t FOP;
1670	/** Instruction pointer. */
1671	uint32_t FPUIP;
1672	/** Code selector. */
1673	uint16_t CS;
1674	uint16_t Rsvrd1;
1675	/* - offset 16 - */
1676	/** Data pointer. */
1677	uint32_t FPUDP;
1678	/** Data segment */
1679	uint16_t DS;
1680	uint16_t Rsrvd2;
1681	uint32_t MXCSR;
1682	uint32_t MXCSR_MASK;
1683	/* - offset 32 - */
1684	union
1685	{
1686	/** MMX view. */
1687	uint64_t mmx;
1688	/** FPU view - todo. */
1689	X86FPUMMX fpu;
1690	/** 8-bit view. */
1691	uint8_t au8[16];
1692	/** 16-bit view. */
1693	uint16_t au16[8];
1694	/** 32-bit view. */
1695	uint32_t au32[4];
1696	/** 64-bit view. */
1697	uint64_t au64[2];
1698	/** 128-bit view. (yeah, very helpful) */
1699	uint128_t au128[1];
1700	} aRegs[8];
1701	/* - offset 160 - */
1702	union
1703	{
1704	/** XMM Register view . /
1705	uint128_t xmm;
1706	/** 8-bit view. */
1707	uint8_t au8[16];
1708	/** 16-bit view. */
1709	uint16_t au16[8];
1710	/** 32-bit view. */
1711	uint32_t au32[4];
1712	/** 64-bit view. */
1713	uint64_t au64[2];
1714	/** 128-bit view. (yeah, very helpful) */
1715	uint128_t au128[1];
1716	} aXMM[16]; /* 8 registers in 32 bits mode; 16 in long mode */
1717	/* - offset 416 - */
1718	uint32_t au32RsrvdRest[(512 - 416) / sizeof(uint32_t)];
1719	} X86FXSTATE;
1720	#pragma pack()
1721	/** Pointer to a FPU Extended state. */
1722	typedef X86FXSTATE *PX86FXSTATE;
1723	/** Pointer to a const FPU Extended state. */
1724	typedef const X86FXSTATE *PCX86FXSTATE;
1725
1726
1727	/** @name Selector Descriptor
1728	* @{
1729	*/
1730
1731	/**
1732	* Generic descriptor table entry
1733	*/
1734	#pragma pack(1)
1735	typedef struct X86DESCGENERIC
1736	{
1737	/** Limit - Low word. */
1738	unsigned u16LimitLow : 16;
1739	/** Base address - lowe word.
1740	* Don't try set this to 24 because MSC is doing studing things then. */
1741	unsigned u16BaseLow : 16;
1742	/** Base address - first 8 bits of high word. */
1743	unsigned u8BaseHigh1 : 8;
1744	/** Segment Type. */
1745	unsigned u4Type : 4;
1746	/** Descriptor Type. System(=0) or code/data selector */
1747	unsigned u1DescType : 1;
1748	/** Descriptor Privelege level. */
1749	unsigned u2Dpl : 2;
1750	/** Flags selector present(=1) or not. */
1751	unsigned u1Present : 1;
1752	/** Segment limit 16-19. */
1753	unsigned u4LimitHigh : 4;
1754	/** Available for system software. */
1755	unsigned u1Available : 1;
1756	/** Reserved - 0. */
1757	unsigned u1Reserved : 1;
1758	/** This flags meaning depends on the segment type. Try make sense out
1759	* of the intel manual yourself. */
1760	unsigned u1DefBig : 1;
1761	/** Granularity of the limit. If set 4KB granularity is used, if
1762	* clear byte. */
1763	unsigned u1Granularity : 1;
1764	/** Base address - highest 8 bits. */
1765	unsigned u8BaseHigh2 : 8;
1766	} X86DESCGENERIC;
1767	#pragma pack()
1768	/** Pointer to a generic descriptor entry. */
1769	typedef X86DESCGENERIC *PX86DESCGENERIC;
1770	/** Pointer to a const generic descriptor entry. */
1771	typedef const X86DESCGENERIC *PCX86DESCGENERIC;
1772
1773
1774	/**
1775	* Descriptor attributes.
1776	*/
1777	typedef struct X86DESCATTRBITS
1778	{
1779	/** Segment Type. */
1780	unsigned u4Type : 4;
1781	/** Descriptor Type. System(=0) or code/data selector */
1782	unsigned u1DescType : 1;
1783	/** Descriptor Privelege level. */
1784	unsigned u2Dpl : 2;
1785	/** Flags selector present(=1) or not. */
1786	unsigned u1Present : 1;
1787	/** Segment limit 16-19. */
1788	unsigned u4LimitHigh : 4;
1789	/** Available for system software. */
1790	unsigned u1Available : 1;
1791	/** Reserved - 0. */
1792	unsigned u1Reserved : 1;
1793	/** This flags meaning depends on the segment type. Try make sense out
1794	* of the intel manual yourself. */
1795	unsigned u1DefBig : 1;
1796	/** Granularity of the limit. If set 4KB granularity is used, if
1797	* clear byte. */
1798	unsigned u1Granularity : 1;
1799	} X86DESCATTRBITS;
1800
1801
1802	#pragma pack(1)
1803	typedef union X86DESCATTR
1804	{
1805	/** Normal view. */
1806	X86DESCATTRBITS n;
1807	/** Unsigned integer view. */
1808	uint32_t u;
1809	} X86DESCATTR;
1810	#pragma pack()
1811
1812	/** Pointer to descriptor attributes. */
1813	typedef X86DESCATTR *PX86DESCATTR;
1814	/** Pointer to const descriptor attributes. */
1815	typedef const X86DESCATTR *PCX86DESCATTR;
1816
1817
1818	/**
1819	* Descriptor table entry.
1820	*/
1821	#pragma pack(1)
1822	typedef union X86DESC
1823	{
1824	/** Generic descriptor view. */
1825	X86DESCGENERIC Gen;
1826	#if 0
1827	/** IDT view. */
1828	VBOXIDTE Idt;
1829	#endif
1830
1831	/** 8 bit unsigned interger view. */
1832	uint8_t au8[8];
1833	/** 16 bit unsigned interger view. */
1834	uint16_t au16[4];
1835	/** 32 bit unsigned interger view. */
1836	uint32_t au32[2];
1837	} X86DESC;
1838	#pragma pack()
1839	/** Pointer to descriptor table entry. */
1840	typedef X86DESC *PX86DESC;
1841	/** Pointer to const descriptor table entry. */
1842	typedef const X86DESC *PCX86DESC;
1843
1844
1845	/**
1846	* 64 bits generic descriptor table entry
1847	* Note: most of these bits have no meaning in long mode.
1848	*/
1849	#pragma pack(1)
1850	typedef struct X86DESC64GENERIC
1851	{
1852	/** Limit - Low word - IGNORED. */
1853	unsigned u16LimitLow : 16;
1854	/** Base address - lowe word. - IGNORED
1855	* Don't try set this to 24 because MSC is doing studing things then. */
1856	unsigned u16BaseLow : 16;
1857	/** Base address - first 8 bits of high word. - IGNORED */
1858	unsigned u8BaseHigh1 : 8;
1859	/** Segment Type. */
1860	unsigned u4Type : 4;
1861	/** Descriptor Type. System(=0) or code/data selector */
1862	unsigned u1DescType : 1;
1863	/** Descriptor Privelege level. */
1864	unsigned u2Dpl : 2;
1865	/** Flags selector present(=1) or not. */
1866	unsigned u1Present : 1;
1867	/** Segment limit 16-19. - IGNORED */
1868	unsigned u4LimitHigh : 4;
1869	/** Available for system software. - IGNORED */
1870	unsigned u1Available : 1;
1871	/** Long mode flag. */
1872	unsigned u1Long : 1;
1873	/** This flags meaning depends on the segment type. Try make sense out
1874	* of the intel manual yourself. */
1875	unsigned u1DefBig : 1;
1876	/** Granularity of the limit. If set 4KB granularity is used, if
1877	* clear byte. - IGNORED */
1878	unsigned u1Granularity : 1;
1879	/** Base address - highest 8 bits. - IGNORED */
1880	unsigned u8BaseHigh2 : 8;
1881	/** Base address - bits 63-32. */
1882	unsigned u32BaseHigh3 : 32;
1883	unsigned u8Reserved : 8;
1884	unsigned u5Zeros : 5;
1885	unsigned u19Reserved : 19;
1886	} X86DESC64GENERIC;
1887	#pragma pack()
1888	/** Pointer to a generic descriptor entry. */
1889	typedef X86DESC64GENERIC *PX86DESC64GENERIC;
1890	/** Pointer to a const generic descriptor entry. */
1891	typedef const X86DESC64GENERIC *PCX86DESC64GENERIC;
1892
1893	/**
1894	* System descriptor table entry (64 bits)
1895	*/
1896	#pragma pack(1)
1897	typedef struct X86DESC64SYSTEM
1898	{
1899	/** Limit - Low word. */
1900	unsigned u16LimitLow : 16;
1901	/** Base address - lowe word.
1902	* Don't try set this to 24 because MSC is doing studing things then. */
1903	unsigned u16BaseLow : 16;
1904	/** Base address - first 8 bits of high word. */
1905	unsigned u8BaseHigh1 : 8;
1906	/** Segment Type. */
1907	unsigned u4Type : 4;
1908	/** Descriptor Type. System(=0) or code/data selector */
1909	unsigned u1DescType : 1;
1910	/** Descriptor Privelege level. */
1911	unsigned u2Dpl : 2;
1912	/** Flags selector present(=1) or not. */
1913	unsigned u1Present : 1;
1914	/** Segment limit 16-19. */
1915	unsigned u4LimitHigh : 4;
1916	/** Available for system software. */
1917	unsigned u1Available : 1;
1918	/** Reserved - 0. */
1919	unsigned u1Reserved : 1;
1920	/** This flags meaning depends on the segment type. Try make sense out
1921	* of the intel manual yourself. */
1922	unsigned u1DefBig : 1;
1923	/** Granularity of the limit. If set 4KB granularity is used, if
1924	* clear byte. */
1925	unsigned u1Granularity : 1;
1926	/** Base address - bits 31-24. */
1927	unsigned u8BaseHigh2 : 8;
1928	/** Base address - bits 63-32. */
1929	unsigned u32BaseHigh3 : 32;
1930	unsigned u8Reserved : 8;
1931	unsigned u5Zeros : 5;
1932	unsigned u19Reserved : 19;
1933	} X86DESC64SYSTEM;
1934	#pragma pack()
1935	/** Pointer to a generic descriptor entry. */
1936	typedef X86DESC64SYSTEM *PX86DESC64SYSTEM;
1937	/** Pointer to a const generic descriptor entry. */
1938	typedef const X86DESC64SYSTEM *PCX86DESC64SYSTEM;
1939
1940
1941	/**
1942	* Descriptor table entry.
1943	*/
1944	#pragma pack(1)
1945	typedef union X86DESC64
1946	{
1947	/** Generic descriptor view. */
1948	X86DESC64GENERIC Gen;
1949	/** System descriptor view. */
1950	X86DESC64SYSTEM System;
1951	#if 0
1952	X86DESC64GATE Gate;
1953	#endif
1954
1955	/** 8 bit unsigned interger view. */
1956	uint8_t au8[16];
1957	/** 16 bit unsigned interger view. */
1958	uint16_t au16[8];
1959	/** 32 bit unsigned interger view. */
1960	uint32_t au32[4];
1961	/** 64 bit unsigned interger view. */
1962	uint64_t au64[2];
1963	} X86DESC64;
1964	#pragma pack()
1965	/** Pointer to descriptor table entry. */
1966	typedef X86DESC64 *PX86DESC64;
1967	/** Pointer to const descriptor table entry. */
1968	typedef const X86DESC64 *PCX86DESC64;
1969
1970	#if HC_ARCH_BITS == 64
1971	typedef X86DESC64 X86DESCHC;
1972	typedef X86DESC64 *PX86DESCHC;
1973	#else
1974	typedef X86DESC X86DESCHC;
1975	typedef X86DESC *PX86DESCHC;
1976	#endif
1977
1978	/** @name Selector Descriptor Types.
1979	* @{
1980	*/
1981
1982	/** @name Non-System Selector Types.
1983	* @{ */
1984	/** Code(=set)/Data(=clear) bit. */
1985	#define X86_SEL_TYPE_CODE 8
1986	/** Memory(=set)/System(=clear) bit. */
1987	#define X86_SEL_TYPE_MEMORY RT_BIT(4)
1988	/** Accessed bit. */
1989	#define X86_SEL_TYPE_ACCESSED 1
1990	/** Expand down bit (for data selectors only). */
1991	#define X86_SEL_TYPE_DOWN 4
1992	/** Conforming bit (for code selectors only). */
1993	#define X86_SEL_TYPE_CONF 4
1994	/** Write bit (for data selectors only). */
1995	#define X86_SEL_TYPE_WRITE 2
1996	/** Read bit (for code selectors only). */
1997	#define X86_SEL_TYPE_READ 2
1998
1999	/** Read only selector type. */
2000	#define X86_SEL_TYPE_RO 0
2001	/** Accessed read only selector type. */
2002	#define X86_SEL_TYPE_RO_ACC (0 \| X86_SEL_TYPE_ACCESSED)
2003	/** Read write selector type. */
2004	#define X86_SEL_TYPE_RW 2
2005	/** Accessed read write selector type. */
2006	#define X86_SEL_TYPE_RW_ACC (2 \| X86_SEL_TYPE_ACCESSED)
2007	/** Expand down read only selector type. */
2008	#define X86_SEL_TYPE_RO_DOWN 4
2009	/** Accessed expand down read only selector type. */
2010	#define X86_SEL_TYPE_RO_DOWN_ACC (4 \| X86_SEL_TYPE_ACCESSED)
2011	/** Expand down read write selector type. */
2012	#define X86_SEL_TYPE_RW_DOWN 6
2013	/** Accessed expand down read write selector type. */
2014	#define X86_SEL_TYPE_RW_DOWN_ACC (6 \| X86_SEL_TYPE_ACCESSED)
2015	/** Execute only selector type. */
2016	#define X86_SEL_TYPE_EO (0 \| X86_SEL_TYPE_CODE)
2017	/** Accessed execute only selector type. */
2018	#define X86_SEL_TYPE_EO_ACC (0 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
2019	/** Execute and read selector type. */
2020	#define X86_SEL_TYPE_ER (2 \| X86_SEL_TYPE_CODE)
2021	/** Accessed execute and read selector type. */
2022	#define X86_SEL_TYPE_ER_ACC (2 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
2023	/** Conforming execute only selector type. */
2024	#define X86_SEL_TYPE_EO_CONF (4 \| X86_SEL_TYPE_CODE)
2025	/** Accessed Conforming execute only selector type. */
2026	#define X86_SEL_TYPE_EO_CONF_ACC (4 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
2027	/** Conforming execute and write selector type. */
2028	#define X86_SEL_TYPE_ER_CONF (6 \| X86_SEL_TYPE_CODE)
2029	/** Accessed Conforming execute and write selector type. */
2030	#define X86_SEL_TYPE_ER_CONF_ACC (6 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
2031	/** @} */
2032
2033
2034	/** @name System Selector Types.
2035	* @{ */
2036	/** Undefined system selector type. */
2037	#define X86_SEL_TYPE_SYS_UNDEFINED 0
2038	/** 286 TSS selector. */
2039	#define X86_SEL_TYPE_SYS_286_TSS_AVAIL 1
2040	/** LDT selector. */
2041	#define X86_SEL_TYPE_SYS_LDT 2
2042	/** 286 TSS selector - Busy. */
2043	#define X86_SEL_TYPE_SYS_286_TSS_BUSY 3
2044	/** 286 Callgate selector. */
2045	#define X86_SEL_TYPE_SYS_286_CALL_GATE 4
2046	/** Taskgate selector. */
2047	#define X86_SEL_TYPE_SYS_TASK_GATE 5
2048	/** 286 Interrupt gate selector. */
2049	#define X86_SEL_TYPE_SYS_286_INT_GATE 6
2050	/** 286 Trapgate selector. */
2051	#define X86_SEL_TYPE_SYS_286_TRAP_GATE 7
2052	/** Undefined system selector. */
2053	#define X86_SEL_TYPE_SYS_UNDEFINED2 8
2054	/** 386 TSS selector. */
2055	#define X86_SEL_TYPE_SYS_386_TSS_AVAIL 9
2056	/** Undefined system selector. */
2057	#define X86_SEL_TYPE_SYS_UNDEFINED3 0xA
2058	/** 386 TSS selector - Busy. */
2059	#define X86_SEL_TYPE_SYS_386_TSS_BUSY 0xB
2060	/** 386 Callgate selector. */
2061	#define X86_SEL_TYPE_SYS_386_CALL_GATE 0xC
2062	/** Undefined system selector. */
2063	#define X86_SEL_TYPE_SYS_UNDEFINED4 0xD
2064	/** 386 Interruptgate selector. */
2065	#define X86_SEL_TYPE_SYS_386_INT_GATE 0xE
2066	/** 386 Trapgate selector. */
2067	#define X86_SEL_TYPE_SYS_386_TRAP_GATE 0xF
2068	/** @} */
2069
2070	/** @name AMD64 System Selector Types.
2071	* @{ */
2072	#define AMD64_SEL_TYPE_SYS_LDT 2
2073	/** 286 TSS selector - Busy. */
2074	#define AMD64_SEL_TYPE_SYS_TSS_AVAIL 9
2075	/** 386 TSS selector - Busy. */
2076	#define AMD64_SEL_TYPE_SYS_TSS_BUSY 0xB
2077	/** 386 Callgate selector. */
2078	#define AMD64_SEL_TYPE_SYS_CALL_GATE 0xC
2079	/** 386 Interruptgate selector. */
2080	#define AMD64_SEL_TYPE_SYS_INT_GATE 0xE
2081	/** 386 Trapgate selector. */
2082	#define AMD64_SEL_TYPE_SYS_TRAP_GATE 0xF
2083	/** @} */
2084
2085	/** @} */
2086
2087
2088	/** @name Descriptor Table Entry Flag Masks.
2089	* These are for the 2nd 32-bit word of a descriptor.
2090	* @{ */
2091	/** Bits 8-11 - TYPE - Descriptor type mask. */
2092	#define X86_DESC_TYPE_MASK (RT_BIT(8) \| RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
2093	/** Bit 12 - S - System (=0) or Code/Data (=1). */
2094	#define X86_DESC_S RT_BIT(12)
2095	/** Bits 13-14 - DPL - Descriptor Privilege Level. */
2096	#define X86_DESC_DPL (RT_BIT(13) \| RT_BIT(14))
2097	/** Bit 15 - P - Present. */
2098	#define X86_DESC_P RT_BIT(15)
2099	/** Bit 20 - AVL - Available for system software. */
2100	#define X86_DESC_AVL RT_BIT(20)
2101	/** Bit 22 - DB - Default operation size. 0 = 16 bit, 1 = 32 bit. */
2102	#define X86_DESC_DB RT_BIT(22)
2103	/** Bit 23 - G - Granularity of the limit. If set 4KB granularity is
2104	* used, if clear byte. */
2105	#define X86_DESC_G RT_BIT(23)
2106	/** @} */
2107
2108	/** @} */
2109
2110
2111	/** @name Selectors.
2112	* @{
2113	*/
2114
2115	/**
2116	* The shift used to convert a selector from and to index an index (C).
2117	*/
2118	#define X86_SEL_SHIFT 3
2119
2120	/**
2121	* The shift used to convert a selector from and to index an index (C).
2122	*/
2123	#define AMD64_SEL_SHIFT 4
2124
2125	#if HC_ARCH_BITS == 64
2126	#define X86_SEL_SHIFT_HC AMD64_SEL_SHIFT
2127	#else
2128	#define X86_SEL_SHIFT_HC X86_SEL_SHIFT
2129	#endif
2130
2131	/**
2132	* The mask used to mask off the table indicator and CPL of an selector.
2133	*/
2134	#define X86_SEL_MASK 0xfff8
2135
2136	/**
2137	* The bit indicating that a selector is in the LDT and not in the GDT.
2138	*/
2139	#define X86_SEL_LDT 0x0004
2140	/**
2141	* The bit mask for getting the RPL of a selector.
2142	*/
2143	#define X86_SEL_RPL 0x0003
2144
2145	/** @} */
2146
2147
2148	/**
2149	* x86 Exceptions/Faults/Traps.
2150	*/
2151	typedef enum X86XCPT
2152	{
2153	/** \#DE - Divide error. */
2154	X86_XCPT_DE = 0x00,
2155	/** \#DB - Debug event (single step, DRx, ..) */
2156	X86_XCPT_DB = 0x01,
2157	/** NMI - Non-Maskable Interrupt */
2158	X86_XCPT_NMI = 0x02,
2159	/** \#BP - Breakpoint (INT3). */
2160	X86_XCPT_BP = 0x03,
2161	/** \#OF - Overflow (INTO). */
2162	X86_XCPT_OF = 0x04,
2163	/** \#BR - Bound range exceeded (BOUND). */
2164	X86_XCPT_BR = 0x05,
2165	/** \#UD - Undefined opcode. */
2166	X86_XCPT_UD = 0x06,
2167	/** \#NM - Device not available (math coprocessor device). */
2168	X86_XCPT_NM = 0x07,
2169	/** \#DF - Double fault. */
2170	X86_XCPT_DF = 0x08,
2171	/** ??? - Coprocessor segment overrun (obsolete). */
2172	X86_XCPT_CO_SEG_OVERRUN = 0x09,
2173	/** \#TS - Taskswitch (TSS). */
2174	X86_XCPT_TS = 0x0a,
2175	/** \#NP - Segment no present. */
2176	X86_XCPT_NP = 0x0b,
2177	/** \#SS - Stack segment fault. */
2178	X86_XCPT_SS = 0x0c,
2179	/** \#GP - General protection fault. */
2180	X86_XCPT_GP = 0x0d,
2181	/** \#PF - Page fault. */
2182	X86_XCPT_PF = 0x0e,
2183	/* 0x0f is reserved. */
2184	/** \#MF - Math fault (FPU). */
2185	X86_XCPT_MF = 0x10,
2186	/** \#AC - Alignment check. */
2187	X86_XCPT_AC = 0x11,
2188	/** \#MC - Machine check. */
2189	X86_XCPT_MC = 0x12,
2190	/** \#XF - SIMD Floating-Pointer Exception. */
2191	X86_XCPT_XF = 0x13
2192	} X86XCPT;
2193	/** Pointer to a x86 exception code. */
2194	typedef X86XCPT *PX86XCPT;
2195	/** Pointer to a const x86 exception code. */
2196	typedef const X86XCPT *PCX86XCPT;
2197
2198
2199	/** @name Trap Error Codes
2200	* @{
2201	*/
2202	/** External indicator. */
2203	#define X86_TRAP_ERR_EXTERNAL 1
2204	/** IDT indicator. */
2205	#define X86_TRAP_ERR_IDT 2
2206	/** Descriptor table indicator - If set LDT, if clear GDT. */
2207	#define X86_TRAP_ERR_TI 4
2208	/** Mask for getting the selector. */
2209	#define X86_TRAP_ERR_SEL_MASK 0xfff8
2210	/** Shift for getting the selector table index (C type index). */
2211	#define X86_TRAP_ERR_SEL_SHIFT 3
2212	/** @} */
2213
2214
2215	/** @name \#PF Trap Error Codes
2216	* @{
2217	*/
2218	/** Bit 0 - P - Not present (clear) or page level protection (set) fault. */
2219	#define X86_TRAP_PF_P RT_BIT(0)
2220	/** Bit 1 - R/W - Read (clear) or write (set) access. */
2221	#define X86_TRAP_PF_RW RT_BIT(1)
2222	/** Bit 2 - U/S - CPU executing in user mode (set) or supervisor mode (clear). */
2223	#define X86_TRAP_PF_US RT_BIT(2)
2224	/** Bit 3 - RSVD- Reserved bit violation (set), i.e. reserved bit was set to 1. */
2225	#define X86_TRAP_PF_RSVD RT_BIT(3)
2226	/** Bit 4 - I/D - Instruction fetch (set) / Data access (clear) - PAE + NXE. */
2227	#define X86_TRAP_PF_ID RT_BIT(4)
2228	/** @} */
2229
2230	#pragma pack(1)
2231	/**
2232	* 32-bit IDTR/GDTR.
2233	*/
2234	typedef struct X86XDTR32
2235	{
2236	/** Size of the descriptor table. */
2237	uint16_t cb;
2238	/** Address of the descriptor table. */
2239	uint32_t uAddr;
2240	} X86XDTR32, *PX86XDTR32;
2241	#pragma pack()
2242
2243	#pragma pack(1)
2244	/**
2245	* 64-bit IDTR/GDTR.
2246	*/
2247	typedef struct X86XDTR64
2248	{
2249	/** Size of the descriptor table. */
2250	uint16_t cb;
2251	/** Address of the descriptor table. */
2252	uint64_t uAddr;
2253	} X86XDTR64, *PX86XDTR64;
2254	#pragma pack()
2255
2256	/** @} */
2257
2258	#endif
2259

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source: vbox/trunk/include/VBox/x86.h@ 7581

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