x86.h@ 9965

Last change on this file since 9965 was 9887, checked in by vboxsync, 17 years ago
Added X86_CR3_AMD64_PAGE_MASK
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 82.0 KB

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1	/** @file
2	* X86 (and AMD64) Structures and Definitions.
3	*/
4
5	/*
6	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
7	*
8	* This file is part of VirtualBox Open Source Edition (OSE), as
9	* available from http://www.virtualbox.org. This file is free software;
10	* you can redistribute it and/or modify it under the terms of the GNU
11	* General Public License (GPL) as published by the Free Software
12	* Foundation, in version 2 as it comes in the "COPYING" file of the
13	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15	*
16	* The contents of this file may alternatively be used under the terms
17	* of the Common Development and Distribution License Version 1.0
18	* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19	* VirtualBox OSE distribution, in which case the provisions of the
20	* CDDL are applicable instead of those of the GPL.
21	*
22	* You may elect to license modified versions of this file under the
23	* terms and conditions of either the GPL or the CDDL or both.
24	*
25	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
26	* Clara, CA 95054 USA or visit http://www.sun.com if you need
27	* additional information or have any questions.
28	*/
29
30	/*
31	* x86.mac is generated from this file using:
32	* sed -e '/__VBox_x86_h__/d' -e '/#define/!d' -e 's/#define/%define/' include/VBox/x86.h
33	*/
34
35	#ifndef ___VBox_x86_h
36	#define ___VBox_x86_h
37
38	#include <VBox/types.h>
39
40	/* Workaround for Solaris sys/regset.h defining CS, DS */
41	#if defined(RT_OS_SOLARIS)
42	# undef CS
43	# undef DS
44	#endif
45
46	/** @defgroup grp_x86 x86 Types and Definitions
47	* @{
48	*/
49
50	/**
51	* EFLAGS Bits.
52	*/
53	typedef struct X86EFLAGSBITS
54	{
55	/** Bit 0 - CF - Carry flag - Status flag. */
56	unsigned u1CF : 1;
57	/** Bit 1 - 1 - Reserved flag. */
58	unsigned u1Reserved0 : 1;
59	/** Bit 2 - PF - Parity flag - Status flag. */
60	unsigned u1PF : 1;
61	/** Bit 3 - 0 - Reserved flag. */
62	unsigned u1Reserved1 : 1;
63	/** Bit 4 - AF - Auxiliary carry flag - Status flag. */
64	unsigned u1AF : 1;
65	/** Bit 5 - 0 - Reserved flag. */
66	unsigned u1Reserved2 : 1;
67	/** Bit 6 - ZF - Zero flag - Status flag. */
68	unsigned u1ZF : 1;
69	/** Bit 7 - SF - Signed flag - Status flag. */
70	unsigned u1SF : 1;
71	/** Bit 8 - TF - Trap flag - System flag. */
72	unsigned u1TF : 1;
73	/** Bit 9 - IF - Interrupt flag - System flag. */
74	unsigned u1IF : 1;
75	/** Bit 10 - DF - Direction flag - Control flag. */
76	unsigned u1DF : 1;
77	/** Bit 11 - OF - Overflow flag - Status flag. */
78	unsigned u1OF : 1;
79	/** Bit 12-13 - IOPL - I/O prvilege level flag - System flag. */
80	unsigned u2IOPL : 2;
81	/** Bit 14 - NT - Nested task flag - System flag. */
82	unsigned u1NT : 1;
83	/** Bit 15 - 0 - Reserved flag. */
84	unsigned u1Reserved3 : 1;
85	/** Bit 16 - RF - Resume flag - System flag. */
86	unsigned u1RF : 1;
87	/** Bit 17 - VM - Virtual 8086 mode - System flag. */
88	unsigned u1VM : 1;
89	/** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
90	unsigned u1AC : 1;
91	/** Bit 19 - VIF - Virtual interupt flag - System flag. */
92	unsigned u1VIF : 1;
93	/** Bit 20 - VIP - Virtual interupt pending flag - System flag. */
94	unsigned u1VIP : 1;
95	/** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
96	unsigned u1ID : 1;
97	/** Bit 22-31 - 0 - Reserved flag. */
98	unsigned u10Reserved4 : 10;
99	} X86EFLAGSBITS;
100	/** Pointer to EFLAGS bits. */
101	typedef X86EFLAGSBITS *PX86EFLAGSBITS;
102	/** Pointer to const EFLAGS bits. */
103	typedef const X86EFLAGSBITS *PCX86EFLAGSBITS;
104
105	/**
106	* EFLAGS.
107	*/
108	typedef union X86EFLAGS
109	{
110	/** The bitfield view. */
111	X86EFLAGSBITS Bits;
112	/** The 8-bit view. */
113	uint8_t au8[4];
114	/** The 16-bit view. */
115	uint16_t au16[2];
116	/** The 32-bit view. */
117	uint32_t au32[1];
118	/** The 32-bit view. */
119	uint32_t u32;
120	/** The plain unsigned view. */
121	uint32_t u;
122	} X86EFLAGS;
123	/** Pointer to EFLAGS. */
124	typedef X86EFLAGS *PX86EFLAGS;
125	/** Pointer to const EFLAGS. */
126	typedef const X86EFLAGS *PCX86EFLAGS;
127
128	/**
129	* RFLAGS (32 upper bits are reserved).
130	*/
131	typedef union X86RFLAGS
132	{
133	/** The bitfield view. */
134	X86EFLAGSBITS Bits;
135	/** The 8-bit view. */
136	uint8_t au8[8];
137	/** The 16-bit view. */
138	uint16_t au16[4];
139	/** The 32-bit view. */
140	uint32_t au32[2];
141	/** The 64-bit view. */
142	uint64_t au64[1];
143	/** The 64-bit view. */
144	uint64_t u64;
145	/** The plain unsigned view. */
146	uint64_t u;
147	} X86RFLAGS;
148	/** Pointer to RFLAGS. */
149	typedef X86RFLAGS *PX86RFLAGS;
150	/** Pointer to const RFLAGS. */
151	typedef const X86RFLAGS *PCX86RFLAGS;
152
153
154	/** @name EFLAGS
155	* @{
156	*/
157	/** Bit 0 - CF - Carry flag - Status flag. */
158	#define X86_EFL_CF RT_BIT(0)
159	/** Bit 2 - PF - Parity flag - Status flag. */
160	#define X86_EFL_PF RT_BIT(2)
161	/** Bit 4 - AF - Auxiliary carry flag - Status flag. */
162	#define X86_EFL_AF RT_BIT(4)
163	/** Bit 6 - ZF - Zero flag - Status flag. */
164	#define X86_EFL_ZF RT_BIT(6)
165	/** Bit 7 - SF - Signed flag - Status flag. */
166	#define X86_EFL_SF RT_BIT(7)
167	/** Bit 8 - TF - Trap flag - System flag. */
168	#define X86_EFL_TF RT_BIT(8)
169	/** Bit 9 - IF - Interrupt flag - System flag. */
170	#define X86_EFL_IF RT_BIT(9)
171	/** Bit 10 - DF - Direction flag - Control flag. */
172	#define X86_EFL_DF RT_BIT(10)
173	/** Bit 11 - OF - Overflow flag - Status flag. */
174	#define X86_EFL_OF RT_BIT(11)
175	/** Bit 12-13 - IOPL - I/O prvilege level flag - System flag. */
176	#define X86_EFL_IOPL (RT_BIT(12) \| RT_BIT(13))
177	/** Bit 14 - NT - Nested task flag - System flag. */
178	#define X86_EFL_NT RT_BIT(14)
179	/** Bit 16 - RF - Resume flag - System flag. */
180	#define X86_EFL_RF RT_BIT(16)
181	/** Bit 17 - VM - Virtual 8086 mode - System flag. */
182	#define X86_EFL_VM RT_BIT(17)
183	/** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
184	#define X86_EFL_AC RT_BIT(18)
185	/** Bit 19 - VIF - Virtual interupt flag - System flag. */
186	#define X86_EFL_VIF RT_BIT(19)
187	/** Bit 20 - VIP - Virtual interupt pending flag - System flag. */
188	#define X86_EFL_VIP RT_BIT(20)
189	/** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
190	#define X86_EFL_ID RT_BIT(21)
191	/** IOPL shift. */
192	#define X86_EFL_IOPL_SHIFT 12
193	/** The the IOPL level from the flags. */
194	#define X86_EFL_GET_IOPL(efl) (((efl) >> X86_EFL_IOPL_SHIFT) & 3)
195	/** @} */
196
197
198	/** CPUID Feature information - ECX.
199	* CPUID query with EAX=1.
200	*/
201	typedef struct X86CPUIDFEATECX
202	{
203	/** Bit 0 - SSE3 - Supports SSE3 or not. */
204	unsigned u1SSE3 : 1;
205	/** Reserved. */
206	unsigned u2Reserved1 : 2;
207	/** Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
208	unsigned u1Monitor : 1;
209	/** Bit 4 - CPL-DS - CPL Qualified Debug Store. */
210	unsigned u1CPLDS : 1;
211	/** Bit 5 - VMX - Virtual Machine Technology. */
212	unsigned u1VMX : 1;
213	/** Reserved. */
214	unsigned u1Reserved2 : 1;
215	/** Bit 7 - EST - Enh. SpeedStep Tech. */
216	unsigned u1EST : 1;
217	/** Bit 8 - TM2 - Terminal Monitor 2. */
218	unsigned u1TM2 : 1;
219	/** Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
220	unsigned u1SSSE3 : 1;
221	/** Bit 10 - CNTX-ID - L1 Context ID. */
222	unsigned u1CNTXID : 1;
223	/** Reserved. */
224	unsigned u2Reserved4 : 2;
225	/** Bit 13 - CX16 - CMPXCHG16B. */
226	unsigned u1CX16 : 1;
227	/** Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
228	unsigned u1TPRUpdate : 1;
229	/** Reserved. */
230	unsigned u17Reserved5 : 17;
231
232	} X86CPUIDFEATECX;
233	/** Pointer to CPUID Feature Information - ECX. */
234	typedef X86CPUIDFEATECX *PX86CPUIDFEATECX;
235	/** Pointer to const CPUID Feature Information - ECX. */
236	typedef const X86CPUIDFEATECX *PCX86CPUIDFEATECX;
237
238
239	/** CPUID Feature Information - EDX.
240	* CPUID query with EAX=1.
241	*/
242	typedef struct X86CPUIDFEATEDX
243	{
244	/** Bit 0 - FPU - x87 FPU on Chip. */
245	unsigned u1FPU : 1;
246	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
247	unsigned u1VME : 1;
248	/** Bit 2 - DE - Debugging extensions. */
249	unsigned u1DE : 1;
250	/** Bit 3 - PSE - Page Size Extension. */
251	unsigned u1PSE : 1;
252	/** Bit 4 - TSC - Time Stamp Counter. */
253	unsigned u1TSC : 1;
254	/** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
255	unsigned u1MSR : 1;
256	/** Bit 6 - PAE - Physical Address Extension. */
257	unsigned u1PAE : 1;
258	/** Bit 7 - MCE - Machine Check Exception. */
259	unsigned u1MCE : 1;
260	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
261	unsigned u1CX8 : 1;
262	/** Bit 9 - APIC - APIC On-Chip. */
263	unsigned u1APIC : 1;
264	/** Bit 10 - Reserved. */
265	unsigned u1Reserved1 : 1;
266	/** Bit 11 - SEP - SYSENTER and SYSEXIT. */
267	unsigned u1SEP : 1;
268	/** Bit 12 - MTRR - Memory Type Range Registers. */
269	unsigned u1MTRR : 1;
270	/** Bit 13 - PGE - PTE Global Bit. */
271	unsigned u1PGE : 1;
272	/** Bit 14 - MCA - Machine Check Architecture. */
273	unsigned u1MCA : 1;
274	/** Bit 15 - CMOV - Conditional Move Instructions. */
275	unsigned u1CMOV : 1;
276	/** Bit 16 - PAT - Page Attribute Table. */
277	unsigned u1PAT : 1;
278	/** Bit 17 - PSE-36 - 36-bit Page Size Extention. */
279	unsigned u1PSE36 : 1;
280	/** Bit 18 - PSN - Processor Serial Number. */
281	unsigned u1PSN : 1;
282	/** Bit 19 - CLFSH - CLFLUSH Instruction. */
283	unsigned u1CLFSH : 1;
284	/** Bit 20 - Reserved. */
285	unsigned u1Reserved2 : 1;
286	/** Bit 21 - DS - Debug Store. */
287	unsigned u1DS : 1;
288	/** Bit 22 - ACPI - Thermal Monitor and Software Controlled Clock Facilities. */
289	unsigned u1ACPI : 1;
290	/** Bit 23 - MMX - Intel MMX 'Technology'. */
291	unsigned u1MMX : 1;
292	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
293	unsigned u1FXSR : 1;
294	/** Bit 25 - SSE - SSE Support. */
295	unsigned u1SSE : 1;
296	/** Bit 26 - SSE2 - SSE2 Support. */
297	unsigned u1SSE2 : 1;
298	/** Bit 27 - SS - Self Snoop. */
299	unsigned u1SS : 1;
300	/** Bit 28 - HTT - Hyper-Threading Technology. */
301	unsigned u1HTT : 1;
302	/** Bit 29 - TM - Thermal Monitor. */
303	unsigned u1TM : 1;
304	/** Bit 30 - Reserved - . */
305	unsigned u1Reserved3 : 1;
306	/** Bit 31 - PBE - Pending Break Enabled. */
307	unsigned u1PBE : 1;
308	} X86CPUIDFEATEDX;
309	/** Pointer to CPUID Feature Information - EDX. */
310	typedef X86CPUIDFEATEDX *PX86CPUIDFEATEDX;
311	/** Pointer to const CPUID Feature Information - EDX. */
312	typedef const X86CPUIDFEATEDX *PCX86CPUIDFEATEDX;
313
314	/** @name CPUID Vendor information.
315	* CPUID query with EAX=0.
316	* @{
317	*/
318	#define X86_CPUID_VENDOR_INTEL_EBX 0x756e6547 /* Genu */
319	#define X86_CPUID_VENDOR_INTEL_ECX 0x6c65746e /* ntel */
320	#define X86_CPUID_VENDOR_INTEL_EDX 0x49656e69 /* ineI */
321
322	#define X86_CPUID_VENDOR_AMD_EBX 0x68747541 /* Auth */
323	#define X86_CPUID_VENDOR_AMD_ECX 0x444d4163 /* cAMD */
324	#define X86_CPUID_VENDOR_AMD_EDX 0x69746e65 /* enti */
325	/** @} */
326
327
328	/** @name CPUID Feature information.
329	* CPUID query with EAX=1.
330	* @{
331	*/
332	/** ECX Bit 0 - SSE3 - Supports SSE3 or not. */
333	#define X86_CPUID_FEATURE_ECX_SSE3 RT_BIT(0)
334	/** ECX Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
335	#define X86_CPUID_FEATURE_ECX_MONITOR RT_BIT(3)
336	/** ECX Bit 4 - CPL-DS - CPL Qualified Debug Store. */
337	#define X86_CPUID_FEATURE_ECX_CPLDS RT_BIT(4)
338	/** ECX Bit 5 - VMX - Virtual Machine Technology. */
339	#define X86_CPUID_FEATURE_ECX_VMX RT_BIT(5)
340	/** ECX Bit 7 - EST - Enh. SpeedStep Tech. */
341	#define X86_CPUID_FEATURE_ECX_EST RT_BIT(7)
342	/** ECX Bit 8 - TM2 - Terminal Monitor 2. */
343	#define X86_CPUID_FEATURE_ECX_TM2 RT_BIT(8)
344	/** ECX Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
345	#define X86_CPUID_FEATURE_ECX_SSSE3 RT_BIT(9)
346	/** ECX Bit 10 - CNTX-ID - L1 Context ID. */
347	#define X86_CPUID_FEATURE_ECX_CNTXID RT_BIT(10)
348	/** ECX Bit 13 - CX16 - CMPXCHG16B. */
349	#define X86_CPUID_FEATURE_ECX_CX16 RT_BIT(13)
350	/** ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
351	#define X86_CPUID_FEATURE_ECX_TPRUPDATE RT_BIT(14)
352	/** ECX Bit 23 - POPCOUNT instruction. */
353	#define X86_CPUID_FEATURE_ECX_POPCOUNT RT_BIT(23)
354
355
356	/** Bit 0 - FPU - x87 FPU on Chip. */
357	#define X86_CPUID_FEATURE_EDX_FPU RT_BIT(0)
358	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
359	#define X86_CPUID_FEATURE_EDX_VME RT_BIT(1)
360	/** Bit 2 - DE - Debugging extensions. */
361	#define X86_CPUID_FEATURE_EDX_DE RT_BIT(2)
362	/** Bit 3 - PSE - Page Size Extension. */
363	#define X86_CPUID_FEATURE_EDX_PSE RT_BIT(3)
364	/** Bit 4 - TSC - Time Stamp Counter. */
365	#define X86_CPUID_FEATURE_EDX_TSC RT_BIT(4)
366	/** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
367	#define X86_CPUID_FEATURE_EDX_MSR RT_BIT(5)
368	/** Bit 6 - PAE - Physical Address Extension. */
369	#define X86_CPUID_FEATURE_EDX_PAE RT_BIT(6)
370	/** Bit 7 - MCE - Machine Check Exception. */
371	#define X86_CPUID_FEATURE_EDX_MCE RT_BIT(7)
372	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
373	#define X86_CPUID_FEATURE_EDX_CX8 RT_BIT(8)
374	/** Bit 9 - APIC - APIC On-Chip. */
375	#define X86_CPUID_FEATURE_EDX_APIC RT_BIT(9)
376	/** Bit 11 - SEP - SYSENTER and SYSEXIT. */
377	#define X86_CPUID_FEATURE_EDX_SEP RT_BIT(11)
378	/** Bit 12 - MTRR - Memory Type Range Registers. */
379	#define X86_CPUID_FEATURE_EDX_MTRR RT_BIT(12)
380	/** Bit 13 - PGE - PTE Global Bit. */
381	#define X86_CPUID_FEATURE_EDX_PGE RT_BIT(13)
382	/** Bit 14 - MCA - Machine Check Architecture. */
383	#define X86_CPUID_FEATURE_EDX_MCA RT_BIT(14)
384	/** Bit 15 - CMOV - Conditional Move Instructions. */
385	#define X86_CPUID_FEATURE_EDX_CMOV RT_BIT(15)
386	/** Bit 16 - PAT - Page Attribute Table. */
387	#define X86_CPUID_FEATURE_EDX_PAT RT_BIT(16)
388	/** Bit 17 - PSE-36 - 36-bit Page Size Extention. */
389	#define X86_CPUID_FEATURE_EDX_PSE36 RT_BIT(17)
390	/** Bit 18 - PSN - Processor Serial Number. */
391	#define X86_CPUID_FEATURE_EDX_PSN RT_BIT(18)
392	/** Bit 19 - CLFSH - CLFLUSH Instruction. */
393	#define X86_CPUID_FEATURE_EDX_CLFSH RT_BIT(19)
394	/** Bit 21 - DS - Debug Store. */
395	#define X86_CPUID_FEATURE_EDX_DS RT_BIT(21)
396	/** Bit 22 - ACPI - Termal Monitor and Software Controlled Clock Facilities. */
397	#define X86_CPUID_FEATURE_EDX_ACPI RT_BIT(22)
398	/** Bit 23 - MMX - Intel MMX Technology. */
399	#define X86_CPUID_FEATURE_EDX_MMX RT_BIT(23)
400	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
401	#define X86_CPUID_FEATURE_EDX_FXSR RT_BIT(24)
402	/** Bit 25 - SSE - SSE Support. */
403	#define X86_CPUID_FEATURE_EDX_SSE RT_BIT(25)
404	/** Bit 26 - SSE2 - SSE2 Support. */
405	#define X86_CPUID_FEATURE_EDX_SSE2 RT_BIT(26)
406	/** Bit 27 - SS - Self Snoop. */
407	#define X86_CPUID_FEATURE_EDX_SS RT_BIT(27)
408	/** Bit 28 - HTT - Hyper-Threading Technology. */
409	#define X86_CPUID_FEATURE_EDX_HTT RT_BIT(28)
410	/** Bit 29 - TM - Therm. Monitor. */
411	#define X86_CPUID_FEATURE_EDX_TM RT_BIT(29)
412	/** Bit 31 - PBE - Pending Break Enabled. */
413	#define X86_CPUID_FEATURE_EDX_PBE RT_BIT(31)
414	/** @} */
415
416
417	/** @name CPUID AMD Feature information.
418	* CPUID query with EAX=0x80000001.
419	* @{
420	*/
421	/** Bit 0 - FPU - x87 FPU on Chip. */
422	#define X86_CPUID_AMD_FEATURE_EDX_FPU RT_BIT(0)
423	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
424	#define X86_CPUID_AMD_FEATURE_EDX_VME RT_BIT(1)
425	/** Bit 2 - DE - Debugging extensions. */
426	#define X86_CPUID_AMD_FEATURE_EDX_DE RT_BIT(2)
427	/** Bit 3 - PSE - Page Size Extension. */
428	#define X86_CPUID_AMD_FEATURE_EDX_PSE RT_BIT(3)
429	/** Bit 4 - TSC - Time Stamp Counter. */
430	#define X86_CPUID_AMD_FEATURE_EDX_TSC RT_BIT(4)
431	/** Bit 5 - MSR - K86 Model Specific Registers RDMSR and WRMSR Instructions. */
432	#define X86_CPUID_AMD_FEATURE_EDX_MSR RT_BIT(5)
433	/** Bit 6 - PAE - Physical Address Extension. */
434	#define X86_CPUID_AMD_FEATURE_EDX_PAE RT_BIT(6)
435	/** Bit 7 - MCE - Machine Check Exception. */
436	#define X86_CPUID_AMD_FEATURE_EDX_MCE RT_BIT(7)
437	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
438	#define X86_CPUID_AMD_FEATURE_EDX_CX8 RT_BIT(8)
439	/** Bit 9 - APIC - APIC On-Chip. */
440	#define X86_CPUID_AMD_FEATURE_EDX_APIC RT_BIT(9)
441	/** Bit 11 - SEP - AMD SYSCALL and SYSRET. */
442	#define X86_CPUID_AMD_FEATURE_EDX_SEP RT_BIT(11)
443	/** Bit 12 - MTRR - Memory Type Range Registers. */
444	#define X86_CPUID_AMD_FEATURE_EDX_MTRR RT_BIT(12)
445	/** Bit 13 - PGE - PTE Global Bit. */
446	#define X86_CPUID_AMD_FEATURE_EDX_PGE RT_BIT(13)
447	/** Bit 14 - MCA - Machine Check Architecture. */
448	#define X86_CPUID_AMD_FEATURE_EDX_MCA RT_BIT(14)
449	/** Bit 15 - CMOV - Conditional Move Instructions. */
450	#define X86_CPUID_AMD_FEATURE_EDX_CMOV RT_BIT(15)
451	/** Bit 16 - PAT - Page Attribute Table. */
452	#define X86_CPUID_AMD_FEATURE_EDX_PAT RT_BIT(16)
453	/** Bit 17 - PSE-36 - 36-bit Page Size Extention. */
454	#define X86_CPUID_AMD_FEATURE_EDX_PSE36 RT_BIT(17)
455	/** Bit 20 - NX - AMD No-Execute Page Protection. */
456	#define X86_CPUID_AMD_FEATURE_EDX_NX RT_BIT(20)
457	/** Bit 22 - AXMMX - AMD Extensions to MMX Instructions. */
458	#define X86_CPUID_AMD_FEATURE_EDX_AXMMX RT_BIT(22)
459	/** Bit 23 - MMX - Intel MMX Technology. */
460	#define X86_CPUID_AMD_FEATURE_EDX_MMX RT_BIT(23)
461	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
462	#define X86_CPUID_AMD_FEATURE_EDX_FXSR RT_BIT(24)
463	/** Bit 25 - FFXSR - AMD fast FXSAVE and FXRSTOR Instructions. */
464	#define X86_CPUID_AMD_FEATURE_EDX_FFXSR RT_BIT(25)
465	/** Bit 26 - PAGE1GB - AMD 1GB large page support. */
466	#define X86_CPUID_AMD_FEATURE_EDX_PAGE1GB RT_BIT(26)
467	/** Bit 27 - RDTSCP - AMD RDTSCP instruction. */
468	#define X86_CPUID_AMD_FEATURE_EDX_RDTSCP RT_BIT(27)
469	/** Bit 29 - LM - AMD Long Mode. */
470	#define X86_CPUID_AMD_FEATURE_EDX_LONG_MODE RT_BIT(29)
471	/** Bit 30 - 3DNOWEXT - AMD Extensions to 3DNow. */
472	#define X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX RT_BIT(30)
473	/** Bit 31 - 3DNOW - AMD 3DNow. */
474	#define X86_CPUID_AMD_FEATURE_EDX_3DNOW RT_BIT(31)
475
476	/** Bit 0 - LAHF/SAHF - AMD LAHF and SAHF in 64-bit mode. */
477	#define X86_CPUID_AMD_FEATURE_ECX_LAHF_SAHF RT_BIT(0)
478	/** Bit 1 - CMPL - Core multi-processing legacy mode. */
479	#define X86_CPUID_AMD_FEATURE_ECX_CMPL RT_BIT(1)
480	/** Bit 2 - SVM - AMD VM extensions. */
481	#define X86_CPUID_AMD_FEATURE_ECX_SVM RT_BIT(2)
482	/** Bit 3 - EXTAPIC - AMD extended APIC registers starting at 0x400. */
483	#define X86_CPUID_AMD_FEATURE_ECX_EXT_APIC RT_BIT(3)
484	/** Bit 4 - CR8L - AMD LOCK MOV CR0 means MOV CR8. */
485	#define X86_CPUID_AMD_FEATURE_ECX_CR8L RT_BIT(4)
486	/** Bit 5 - ABM - AMD Advanced bit manipulation. LZCNT instruction support. */
487	#define X86_CPUID_AMD_FEATURE_ECX_ABM RT_BIT(5)
488	/** Bit 6 - SSE4A - AMD EXTRQ, INSERTQ, MOVNTSS, and MOVNTSD instruction support. */
489	#define X86_CPUID_AMD_FEATURE_ECX_SSE4A RT_BIT(6)
490	/** Bit 7 - MISALIGNSSE - AMD Misaligned SSE mode. */
491	#define X86_CPUID_AMD_FEATURE_ECX_MISALNSSE RT_BIT(7)
492	/** Bit 8 - 3DNOWPRF - AMD PREFETCH and PREFETCHW instruction support. */
493	#define X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF RT_BIT(8)
494	/** Bit 9 - OSVW - AMD OS visible workaround. */
495	#define X86_CPUID_AMD_FEATURE_ECX_OSVW RT_BIT(9)
496	/** Bit 12 - SKINIT - AMD SKINIT: SKINIT, STGI, and DEV support. */
497	#define X86_CPUID_AMD_FEATURE_ECX_SKINIT RT_BIT(12)
498	/** Bit 13 - WDT - AMD Watchdog timer support. */
499	#define X86_CPUID_AMD_FEATURE_ECX_WDT RT_BIT(13)
500
501	/** @} */
502
503
504	/** @name CR0
505	* @{ */
506	/** Bit 0 - PE - Protection Enabled */
507	#define X86_CR0_PE RT_BIT(0)
508	#define X86_CR0_PROTECTION_ENABLE RT_BIT(0)
509	/** Bit 1 - MP - Monitor Coprocessor */
510	#define X86_CR0_MP RT_BIT(1)
511	#define X86_CR0_MONITOR_COPROCESSOR RT_BIT(1)
512	/** Bit 2 - EM - Emulation. */
513	#define X86_CR0_EM RT_BIT(2)
514	#define X86_CR0_EMULATE_FPU RT_BIT(2)
515	/** Bit 3 - TS - Task Switch. */
516	#define X86_CR0_TS RT_BIT(3)
517	#define X86_CR0_TASK_SWITCH RT_BIT(3)
518	/** Bit 4 - ET - Extension flag. ('hardcoded' to 1) */
519	#define X86_CR0_ET RT_BIT(4)
520	#define X86_CR0_EXTENSION_TYPE RT_BIT(4)
521	/** Bit 5 - NE - Numeric error. */
522	#define X86_CR0_NE RT_BIT(5)
523	#define X86_CR0_NUMERIC_ERROR RT_BIT(5)
524	/** Bit 16 - WP - Write Protect. */
525	#define X86_CR0_WP RT_BIT(16)
526	#define X86_CR0_WRITE_PROTECT RT_BIT(16)
527	/** Bit 18 - AM - Alignment Mask. */
528	#define X86_CR0_AM RT_BIT(18)
529	#define X86_CR0_ALIGMENT_MASK RT_BIT(18)
530	/** Bit 29 - NW - Not Write-though. */
531	#define X86_CR0_NW RT_BIT(29)
532	#define X86_CR0_NOT_WRITE_THROUGH RT_BIT(29)
533	/** Bit 30 - WP - Cache Disable. */
534	#define X86_CR0_CD RT_BIT(30)
535	#define X86_CR0_CACHE_DISABLE RT_BIT(30)
536	/** Bit 31 - PG - Paging. */
537	#define X86_CR0_PG RT_BIT(31)
538	#define X86_CR0_PAGING RT_BIT(31)
539	/** @} */
540
541
542	/** @name CR3
543	* @{ */
544	/** Bit 3 - PWT - Page-level Writes Transparent. */
545	#define X86_CR3_PWT RT_BIT(3)
546	/** Bit 4 - PCD - Page-level Cache Disable. */
547	#define X86_CR3_PCD RT_BIT(4)
548	/** Bits 12-31 - - Page directory page number. */
549	#define X86_CR3_PAGE_MASK (0xfffff000)
550	/** Bits 5-31 - - PAE Page directory page number. */
551	#define X86_CR3_PAE_PAGE_MASK (0xffffffe0)
552	/** Bits 12-51 - - AMD64 Page directory page number. */
553	#define X86_CR3_AMD64_PAGE_MASK UINT64_C(0x000ffffffffff000)
554	/** @} */
555
556
557	/** @name CR4
558	* @{ */
559	/** Bit 0 - VME - Virtual-8086 Mode Extensions. */
560	#define X86_CR4_VME RT_BIT(0)
561	/** Bit 1 - PVI - Protected-Mode Virtual Interrupts. */
562	#define X86_CR4_PVI RT_BIT(1)
563	/** Bit 2 - TSD - Time Stamp Disable. */
564	#define X86_CR4_TSD RT_BIT(2)
565	/** Bit 3 - DE - Debugging Extensions. */
566	#define X86_CR4_DE RT_BIT(3)
567	/** Bit 4 - PSE - Page Size Extension. */
568	#define X86_CR4_PSE RT_BIT(4)
569	/** Bit 5 - PAE - Physical Address Extension. */
570	#define X86_CR4_PAE RT_BIT(5)
571	/** Bit 6 - MCE - Machine-Check Enable. */
572	#define X86_CR4_MCE RT_BIT(6)
573	/** Bit 7 - PGE - Page Global Enable. */
574	#define X86_CR4_PGE RT_BIT(7)
575	/** Bit 8 - PCE - Performance-Monitoring Counter Enable. */
576	#define X86_CR4_PCE RT_BIT(8)
577	/** Bit 9 - OSFSXR - Operating System Support for FXSAVE and FXRSTORE instruction. */
578	#define X86_CR4_OSFSXR RT_BIT(9)
579	/** Bit 10 - OSXMMEEXCPT - Operating System Support for Unmasked SIMD Floating-Point Exceptions. */
580	#define X86_CR4_OSXMMEEXCPT RT_BIT(10)
581	/** Bit 13 - VMXE - VMX mode is enabled. */
582	#define X86_CR4_VMXE RT_BIT(13)
583	/** @} */
584
585
586	/** @name DR6
587	* @{ */
588	/** Bit 0 - B0 - Breakpoint 0 condition detected. */
589	#define X86_DR6_B0 RT_BIT(0)
590	/** Bit 1 - B1 - Breakpoint 1 condition detected. */
591	#define X86_DR6_B1 RT_BIT(1)
592	/** Bit 2 - B2 - Breakpoint 2 condition detected. */
593	#define X86_DR6_B2 RT_BIT(2)
594	/** Bit 3 - B3 - Breakpoint 3 condition detected. */
595	#define X86_DR6_B3 RT_BIT(3)
596	/** Bit 13 - BD - Debug register access detected. Corresponds to the X86_DR7_GD bit. */
597	#define X86_DR6_BD RT_BIT(13)
598	/** Bit 14 - BS - Single step */
599	#define X86_DR6_BS RT_BIT(14)
600	/** Bit 15 - BT - Task switch. (TSS T bit.) */
601	#define X86_DR6_BT RT_BIT(15)
602	/** @} */
603
604
605	/** @name DR7
606	* @{ */
607	/** Bit 0 - L0 - Local breakpoint enable. Cleared on task switch. */
608	#define X86_DR7_L0 RT_BIT(0)
609	/** Bit 1 - G0 - Global breakpoint enable. Not cleared on task switch. */
610	#define X86_DR7_G0 RT_BIT(1)
611	/** Bit 2 - L1 - Local breakpoint enable. Cleared on task switch. */
612	#define X86_DR7_L1 RT_BIT(2)
613	/** Bit 3 - G1 - Global breakpoint enable. Not cleared on task switch. */
614	#define X86_DR7_G1 RT_BIT(3)
615	/** Bit 4 - L2 - Local breakpoint enable. Cleared on task switch. */
616	#define X86_DR7_L2 RT_BIT(4)
617	/** Bit 5 - G2 - Global breakpoint enable. Not cleared on task switch. */
618	#define X86_DR7_G2 RT_BIT(5)
619	/** Bit 6 - L3 - Local breakpoint enable. Cleared on task switch. */
620	#define X86_DR7_L3 RT_BIT(6)
621	/** Bit 7 - G3 - Global breakpoint enable. Not cleared on task switch. */
622	#define X86_DR7_G3 RT_BIT(7)
623	/** Bit 8 - LE - Local breakpoint exact. (Not supported (read ignored) by P6 and later.) */
624	#define X86_DR7_LE RT_BIT(8)
625	/** Bit 9 - GE - Local breakpoint exact. (Not supported (read ignored) by P6 and later.) */
626	#define X86_DR7_GE RT_BIT(9)
627
628	/** Bit 13 - GD - General detect enable. Enables emulators to get exceptions when
629	* any DR register is accessed. */
630	#define X86_DR7_GD RT_BIT(13)
631	/** Bit 16 & 17 - R/W0 - Read write field 0. Values X86_DR7_RW_. /
632	#define X86_DR7_RW0_MASK (3 << 16)
633	/** Bit 18 & 19 - LEN0 - Length field 0. Values X86_DR7_LEN_. /
634	#define X86_DR7_LEN0_MASK (3 << 18)
635	/** Bit 20 & 21 - R/W1 - Read write field 0. Values X86_DR7_RW_. /
636	#define X86_DR7_RW1_MASK (3 << 20)
637	/** Bit 22 & 23 - LEN1 - Length field 0. Values X86_DR7_LEN_. /
638	#define X86_DR7_LEN1_MASK (3 << 22)
639	/** Bit 24 & 25 - R/W2 - Read write field 0. Values X86_DR7_RW_. /
640	#define X86_DR7_RW2_MASK (3 << 24)
641	/** Bit 26 & 27 - LEN2 - Length field 0. Values X86_DR7_LEN_. /
642	#define X86_DR7_LEN2_MASK (3 << 26)
643	/** Bit 28 & 29 - R/W3 - Read write field 0. Values X86_DR7_RW_. /
644	#define X86_DR7_RW3_MASK (3 << 28)
645	/** Bit 30 & 31 - LEN3 - Length field 0. Values X86_DR7_LEN_. /
646	#define X86_DR7_LEN3_MASK (3 << 30)
647
648	/** Bits which must be 1s. */
649	#define X86_DR7_MB1_MASK (RT_BIT(10))
650
651	/** Calcs the L bit of Nth breakpoint.
652	* @param iBp The breakpoint number [0..3].
653	*/
654	#define X86_DR7_L(iBp) ( 1 << (iBp * 2) )
655
656	/** Calcs the G bit of Nth breakpoint.
657	* @param iBp The breakpoint number [0..3].
658	*/
659	#define X86_DR7_G(iBp) ( 1 << (iBp * 2 + 1) )
660
661	/** @name Read/Write values.
662	* @{ */
663	/** Break on instruction fetch only. */
664	#define X86_DR7_RW_EO 0
665	/** Break on write only. */
666	#define X86_DR7_RW_WO 1
667	/** Break on I/O read/write. This is only defined if CR4.DE is set. */
668	#define X86_DR7_RW_IO 2
669	/** Break on read or write (but not instruction fetches). */
670	#define X86_DR7_RW_RW 3
671	/** @} */
672
673	/** Shifts a X86_DR7_RW_* value to its right place.
674	* @param iBp The breakpoint number [0..3].
675	* @param fRw One of the X86_DR7_RW_* value.
676	*/
677	#define X86_DR7_RW(iBp, fRw) ( (fRw) << ((iBp) * 4 + 16) )
678
679	/** @name Length values.
680	* @{ */
681	#define X86_DR7_LEN_BYTE 0
682	#define X86_DR7_LEN_WORD 1
683	#define X86_DR7_LEN_QWORD 2 /*< AMD64 long mode only. /
684	#define X86_DR7_LEN_DWORD 3
685	/** @} */
686
687	/** Shifts a X86_DR7_LEN_* value to its right place.
688	* @param iBp The breakpoint number [0..3].
689	* @param cb One of the X86_DR7_LEN_* values.
690	*/
691	#define X86_DR7_LEN(iBp, cb) ( (cb) << ((iBp) * 4 + 18) )
692
693	/** Mask used to check if any breakpoints are enabled. */
694	#define X86_DR7_ENABLED_MASK (RT_BIT(0) \| RT_BIT(1) \| RT_BIT(2) \| RT_BIT(3) \| RT_BIT(4) \| RT_BIT(6) \| RT_BIT(7))
695
696	/** @} */
697
698
699	/** @name Machine Specific Registers
700	* @{
701	*/
702	#ifndef MSR_IA32_APICBASE /* qemu cpu.h klugde */
703	#define MSR_IA32_APICBASE 0x1b
704	#endif
705
706	/** CPU Feature control. */
707	#define MSR_IA32_FEATURE_CONTROL 0x3A
708	#define MSR_IA32_FEATURE_CONTROL_LOCK RT_BIT(0)
709	#define MSR_IA32_FEATURE_CONTROL_VMXON RT_BIT(2)
710
711
712	#ifndef MSR_IA32_SYSENTER_CS /* qemu cpu.h klugde */
713	/** SYSENTER_CS - the R0 CS, indirectly giving R0 SS, R3 CS and R3 DS.
714	* R0 SS == CS + 8
715	* R3 CS == CS + 16
716	* R3 SS == CS + 24
717	*/
718	#define MSR_IA32_SYSENTER_CS 0x174
719	/** SYSENTER_ESP - the R0 ESP. */
720	#define MSR_IA32_SYSENTER_ESP 0x175
721	/** SYSENTER_EIP - the R0 EIP. */
722	#define MSR_IA32_SYSENTER_EIP 0x176
723	#endif
724
725	/* Page Attribute Table. */
726	#define MSR_IA32_CR_PAT 0x277
727
728	/** Basic VMX information. */
729	#define MSR_IA32_VMX_BASIC_INFO 0x480
730	/** Allowed settings for pin-based VM execution controls */
731	#define MSR_IA32_VMX_PINBASED_CTLS 0x481
732	/** Allowed settings for proc-based VM execution controls */
733	#define MSR_IA32_VMX_PROCBASED_CTLS 0x482
734	/** Allowed settings for the VMX exit controls. */
735	#define MSR_IA32_VMX_EXIT_CTLS 0x483
736	/** Allowed settings for the VMX entry controls. */
737	#define MSR_IA32_VMX_ENTRY_CTLS 0x484
738	/** Misc VMX info. */
739	#define MSR_IA32_VMX_MISC 0x485
740	/** Fixed cleared bits in CR0. */
741	#define MSR_IA32_VMX_CR0_FIXED0 0x486
742	/** Fixed set bits in CR0. */
743	#define MSR_IA32_VMX_CR0_FIXED1 0x487
744	/** Fixed cleared bits in CR4. */
745	#define MSR_IA32_VMX_CR4_FIXED0 0x488
746	/** Fixed set bits in CR4. */
747	#define MSR_IA32_VMX_CR4_FIXED1 0x489
748	/** Information for enumerating fields in the VMCS. */
749	#define MSR_IA32_VMX_VMCS_ENUM 0x48A
750
751
752	/** K6 EFER - Extended Feature Enable Register. */
753	#define MSR_K6_EFER 0xc0000080
754	/** @todo document EFER */
755	/** Bit 0 - SCE - System call extensions (SYSCALL / SYSRET). (R/W) */
756	#define MSR_K6_EFER_SCE RT_BIT(0)
757	/** Bit 8 - LME - Long mode enabled. (R/W) */
758	#define MSR_K6_EFER_LME RT_BIT(8)
759	/** Bit 10 - LMA - Long mode active. (R) */
760	#define MSR_K6_EFER_LMA RT_BIT(10)
761	/** Bit 11 - NXE - No-Execute Page Protection Enabled. (R/W) */
762	#define MSR_K6_EFER_NXE RT_BIT(11)
763	/** Bit 12 - SVME - Secure VM Extension Enabled. (R/W) */
764	#define MSR_K6_EFER_SVME RT_BIT(12)
765	/** Bit 13 - LMSLE - Long Mode Segment Limit Enable. (R/W?) */
766	#define MSR_K6_EFER_LMSLE RT_BIT(13)
767	/** Bit 14 - FFXSR - Fast FXSAVE / FXRSTOR (skip XMM). (R/W) /
768	#define MSR_K6_EFER_FFXSR RT_BIT(14)
769	/** K6 STAR - SYSCALL/RET targets. */
770	#define MSR_K6_STAR 0xc0000081
771	/** Shift value for getting the SYSRET CS and SS value. */
772	#define MSR_K6_STAR_SYSRET_CS_SS_SHIFT 48
773	/** Shift value for getting the SYSCALL CS and SS value. */
774	#define MSR_K6_STAR_SYSCALL_CS_SS_SHIFT 32
775	/** Selector mask for use after shifting. */
776	#define MSR_K6_STAR_SEL_MASK 0xffff
777	/** The mask which give the SYSCALL EIP. */
778	#define MSR_K6_STAR_SYSCALL_EIP_MASK 0xffffffff
779	/** K6 WHCR - Write Handling Control Register. */
780	#define MSR_K6_WHCR 0xc0000082
781	/** K6 UWCCR - UC/WC Cacheability Control Register. */
782	#define MSR_K6_UWCCR 0xc0000085
783	/** K6 PSOR - Processor State Observability Register. */
784	#define MSR_K6_PSOR 0xc0000087
785	/** K6 PFIR - Page Flush/Invalidate Register. */
786	#define MSR_K6_PFIR 0xc0000088
787
788	#define MSR_K7_EVNTSEL0 0xc0010000
789	#define MSR_K7_EVNTSEL1 0xc0010001
790	#define MSR_K7_EVNTSEL2 0xc0010002
791	#define MSR_K7_EVNTSEL3 0xc0010003
792	#define MSR_K7_PERFCTR0 0xc0010004
793	#define MSR_K7_PERFCTR1 0xc0010005
794	#define MSR_K7_PERFCTR2 0xc0010006
795	#define MSR_K7_PERFCTR3 0xc0010007
796
797	/** K8 LSTAR - Long mode SYSCALL target (RIP). */
798	#define MSR_K8_LSTAR 0xc0000082
799	/** K8 CSTAR - Compatibility mode SYSCALL target (RIP). */
800	#define MSR_K8_CSTAR 0xc0000083
801	/** K8 SF_MASK - SYSCALL flag mask. (aka SFMASK) */
802	#define MSR_K8_SF_MASK 0xc0000084
803	/** K8 FS.base - The 64-bit base FS register. */
804	#define MSR_K8_FS_BASE 0xc0000100
805	/** K8 GS.base - The 64-bit base GS register. */
806	#define MSR_K8_GS_BASE 0xc0000101
807	/** K8 KernelGSbase - Used with SWAPGS. */
808	#define MSR_K8_KERNEL_GS_BASE 0xc0000102
809	#define MSR_K8_TSC_AUX 0xc0000103
810	#define MSR_K8_SYSCFG 0xc0010010
811	#define MSR_K8_HWCR 0xc0010015
812	#define MSR_K8_IORRBASE0 0xc0010016
813	#define MSR_K8_IORRMASK0 0xc0010017
814	#define MSR_K8_IORRBASE1 0xc0010018
815	#define MSR_K8_IORRMASK1 0xc0010019
816	#define MSR_K8_TOP_MEM1 0xc001001a
817	#define MSR_K8_TOP_MEM2 0xc001001d
818	#define MSR_K8_VM_CR 0xc0010114
819	#define MSR_K8_VM_CR_SVM_DISABLE RT_BIT(4)
820
821	#define MSR_K8_IGNNE 0xc0010115
822	#define MSR_K8_SMM_CTL 0xc0010116
823	/** SVM - VM_HSAVE_PA - Physical address for saving and restoring
824	* host state during world switch.
825	*/
826	#define MSR_K8_VM_HSAVE_PA 0xc0010117
827
828	/** @} */
829
830
831	/** @name Page Table / Directory / Directory Pointers / L4.
832	* @{
833	*/
834
835	/** Page table/directory entry as an unsigned integer. */
836	typedef uint32_t X86PGUINT;
837	/** Pointer to a page table/directory table entry as an unsigned integer. */
838	typedef X86PGUINT *PX86PGUINT;
839
840	/** Number of entries in a 32-bit PT/PD. */
841	#define X86_PG_ENTRIES 1024
842
843
844	/** PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
845	typedef uint64_t X86PGPAEUINT;
846	/** Pointer to a PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
847	typedef X86PGPAEUINT *PX86PGPAEUINT;
848
849	/** Number of entries in a PAE PT/PD. */
850	#define X86_PG_PAE_ENTRIES 512
851	/** Number of entries in a PAE PDPT. */
852	#define X86_PG_PAE_PDPE_ENTRIES 4
853
854	/** Number of entries in an AMD64 PT/PD/PDPT/L4/L5. */
855	#define X86_PG_AMD64_ENTRIES X86_PG_PAE_ENTRIES
856	/** Number of entries in an AMD64 PDPT.
857	* Just for complementing X86_PG_PAE_PDPE_ENTRIES, using X86_PG_AMD64_ENTRIES for this is fine too. */
858	#define X86_PG_AMD64_PDPE_ENTRIES X86_PG_AMD64_ENTRIES
859
860	/** The size of a 4KB page. */
861	#define X86_PAGE_4K_SIZE _4K
862	/** The page shift of a 4KB page. */
863	#define X86_PAGE_4K_SHIFT 12
864	/** The 4KB page offset mask. */
865	#define X86_PAGE_4K_OFFSET_MASK 0xfff
866	/** The 4KB page base mask for virtual addresses. */
867	#define X86_PAGE_4K_BASE_MASK 0xfffffffffffff000ULL
868	/** The 4KB page base mask for virtual addresses - 32bit version. */
869	#define X86_PAGE_4K_BASE_MASK_32 0xfffff000U
870
871	/** The size of a 2MB page. */
872	#define X86_PAGE_2M_SIZE _2M
873	/** The page shift of a 2MB page. */
874	#define X86_PAGE_2M_SHIFT 21
875	/** The 2MB page offset mask. */
876	#define X86_PAGE_2M_OFFSET_MASK 0x001fffff
877	/** The 2MB page base mask for virtual addresses. */
878	#define X86_PAGE_2M_BASE_MASK 0xffffffffffe00000ULL
879	/** The 2MB page base mask for virtual addresses - 32bit version. */
880	#define X86_PAGE_2M_BASE_MASK_32 0xffe00000U
881
882	/** The size of a 4MB page. */
883	#define X86_PAGE_4M_SIZE _4M
884	/** The page shift of a 4MB page. */
885	#define X86_PAGE_4M_SHIFT 22
886	/** The 4MB page offset mask. */
887	#define X86_PAGE_4M_OFFSET_MASK 0x003fffff
888	/** The 4MB page base mask for virtual addresses. */
889	#define X86_PAGE_4M_BASE_MASK 0xffffffffffc00000ULL
890	/** The 4MB page base mask for virtual addresses - 32bit version. */
891	#define X86_PAGE_4M_BASE_MASK_32 0xffc00000U
892
893
894
895	/** @name Page Table Entry
896	* @{
897	*/
898	/** Bit 0 - P - Present bit. */
899	#define X86_PTE_P RT_BIT(0)
900	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
901	#define X86_PTE_RW RT_BIT(1)
902	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
903	#define X86_PTE_US RT_BIT(2)
904	/** Bit 3 - PWT - Page level write thru bit. */
905	#define X86_PTE_PWT RT_BIT(3)
906	/** Bit 4 - PCD - Page level cache disable bit. */
907	#define X86_PTE_PCD RT_BIT(4)
908	/** Bit 5 - A - Access bit. */
909	#define X86_PTE_A RT_BIT(5)
910	/** Bit 6 - D - Dirty bit. */
911	#define X86_PTE_D RT_BIT(6)
912	/** Bit 7 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
913	#define X86_PTE_PAT RT_BIT(7)
914	/** Bit 8 - G - Global flag. */
915	#define X86_PTE_G RT_BIT(8)
916	/** Bits 9-11 - - Available for use to system software. */
917	#define X86_PTE_AVL_MASK (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
918	/** Bits 12-31 - - Physical Page number of the next level. */
919	#define X86_PTE_PG_MASK ( 0xfffff000 )
920
921	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
922	#if 1 /* we're using this internally and have to mask of the top 16-bit. */
923	#define X86_PTE_PAE_PG_MASK ( 0x0000fffffffff000ULL )
924	/** @todo Get rid of the above hack; makes code unreadable. */
925	#define X86_PTE_PAE_PG_MASK_FULL ( 0x000ffffffffff000ULL )
926	#else
927	#define X86_PTE_PAE_PG_MASK ( 0x000ffffffffff000ULL )
928	#endif
929	/** Bits 63 - NX - PAE - No execution flag. */
930	#define X86_PTE_PAE_NX RT_BIT_64(63)
931
932	/**
933	* Page table entry.
934	*/
935	typedef struct X86PTEBITS
936	{
937	/** Flags whether(=1) or not the page is present. */
938	unsigned u1Present : 1;
939	/** Read(=0) / Write(=1) flag. */
940	unsigned u1Write : 1;
941	/** User(=1) / Supervisor (=0) flag. */
942	unsigned u1User : 1;
943	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
944	unsigned u1WriteThru : 1;
945	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
946	unsigned u1CacheDisable : 1;
947	/** Accessed flag.
948	* Indicates that the page have been read or written to. */
949	unsigned u1Accessed : 1;
950	/** Dirty flag.
951	* Indicates that the page have been written to. */
952	unsigned u1Dirty : 1;
953	/** Reserved / If PAT enabled, bit 2 of the index. */
954	unsigned u1PAT : 1;
955	/** Global flag. (Ignored in all but final level.) */
956	unsigned u1Global : 1;
957	/** Available for use to system software. */
958	unsigned u3Available : 3;
959	/** Physical Page number of the next level. */
960	unsigned u20PageNo : 20;
961	} X86PTEBITS;
962	/** Pointer to a page table entry. */
963	typedef X86PTEBITS *PX86PTEBITS;
964	/** Pointer to a const page table entry. */
965	typedef const X86PTEBITS *PCX86PTEBITS;
966
967	/**
968	* Page table entry.
969	*/
970	typedef union X86PTE
971	{
972	/** Bit field view. */
973	X86PTEBITS n;
974	/** Unsigned integer view */
975	X86PGUINT u;
976	/** 32-bit view. */
977	uint32_t au32[1];
978	/** 16-bit view. */
979	uint16_t au16[2];
980	/** 8-bit view. */
981	uint8_t au8[4];
982	} X86PTE;
983	/** Pointer to a page table entry. */
984	typedef X86PTE *PX86PTE;
985	/** Pointer to a const page table entry. */
986	typedef const X86PTE *PCX86PTE;
987
988
989	/**
990	* PAE page table entry.
991	*/
992	typedef struct X86PTEPAEBITS
993	{
994	/** Flags whether(=1) or not the page is present. */
995	uint32_t u1Present : 1;
996	/** Read(=0) / Write(=1) flag. */
997	uint32_t u1Write : 1;
998	/** User(=1) / Supervisor(=0) flag. */
999	uint32_t u1User : 1;
1000	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1001	uint32_t u1WriteThru : 1;
1002	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1003	uint32_t u1CacheDisable : 1;
1004	/** Accessed flag.
1005	* Indicates that the page have been read or written to. */
1006	uint32_t u1Accessed : 1;
1007	/** Dirty flag.
1008	* Indicates that the page have been written to. */
1009	uint32_t u1Dirty : 1;
1010	/** Reserved / If PAT enabled, bit 2 of the index. */
1011	uint32_t u1PAT : 1;
1012	/** Global flag. (Ignored in all but final level.) */
1013	uint32_t u1Global : 1;
1014	/** Available for use to system software. */
1015	uint32_t u3Available : 3;
1016	/** Physical Page number of the next level - Low Part. Don't use this. */
1017	uint32_t u20PageNoLow : 20;
1018	/** Physical Page number of the next level - High Part. Don't use this. */
1019	uint32_t u20PageNoHigh : 20;
1020	/** MBZ bits */
1021	uint32_t u11Reserved : 11;
1022	/** No Execute flag. */
1023	uint32_t u1NoExecute : 1;
1024	} X86PTEPAEBITS;
1025	/** Pointer to a page table entry. */
1026	typedef X86PTEPAEBITS *PX86PTEPAEBITS;
1027	/** Pointer to a page table entry. */
1028	typedef const X86PTEPAEBITS *PCX86PTEPAEBITS;
1029
1030	/**
1031	* PAE Page table entry.
1032	*/
1033	typedef union X86PTEPAE
1034	{
1035	/** Bit field view. */
1036	X86PTEPAEBITS n;
1037	/** Unsigned integer view */
1038	X86PGPAEUINT u;
1039	/** 32-bit view. */
1040	uint32_t au32[2];
1041	/** 16-bit view. */
1042	uint16_t au16[4];
1043	/** 8-bit view. */
1044	uint8_t au8[8];
1045	} X86PTEPAE;
1046	/** Pointer to a PAE page table entry. */
1047	typedef X86PTEPAE *PX86PTEPAE;
1048	/** Pointer to a const PAE page table entry. */
1049	typedef const X86PTEPAE *PCX86PTEPAE;
1050	/** @} */
1051
1052	/**
1053	* Page table.
1054	*/
1055	typedef struct X86PT
1056	{
1057	/** PTE Array. */
1058	X86PTE a[X86_PG_ENTRIES];
1059	} X86PT;
1060	/** Pointer to a page table. */
1061	typedef X86PT *PX86PT;
1062	/** Pointer to a const page table. */
1063	typedef const X86PT *PCX86PT;
1064
1065	/** The page shift to get the PT index. */
1066	#define X86_PT_SHIFT 12
1067	/** The PT index mask (apply to a shifted page address). */
1068	#define X86_PT_MASK 0x3ff
1069
1070
1071	/**
1072	* Page directory.
1073	*/
1074	typedef struct X86PTPAE
1075	{
1076	/** PTE Array. */
1077	X86PTEPAE a[X86_PG_PAE_ENTRIES];
1078	} X86PTPAE;
1079	/** Pointer to a page table. */
1080	typedef X86PTPAE *PX86PTPAE;
1081	/** Pointer to a const page table. */
1082	typedef const X86PTPAE *PCX86PTPAE;
1083
1084	/** The page shift to get the PA PTE index. */
1085	#define X86_PT_PAE_SHIFT 12
1086	/** The PAE PT index mask (apply to a shifted page address). */
1087	#define X86_PT_PAE_MASK 0x1ff
1088
1089
1090	/** @name 4KB Page Directory Entry
1091	* @{
1092	*/
1093	/** Bit 0 - P - Present bit. */
1094	#define X86_PDE_P RT_BIT(0)
1095	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1096	#define X86_PDE_RW RT_BIT(1)
1097	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1098	#define X86_PDE_US RT_BIT(2)
1099	/** Bit 3 - PWT - Page level write thru bit. */
1100	#define X86_PDE_PWT RT_BIT(3)
1101	/** Bit 4 - PCD - Page level cache disable bit. */
1102	#define X86_PDE_PCD RT_BIT(4)
1103	/** Bit 5 - A - Access bit. */
1104	#define X86_PDE_A RT_BIT(5)
1105	/** Bit 7 - PS - Page size attribute.
1106	* Clear mean 4KB pages, set means large pages (2/4MB). */
1107	#define X86_PDE_PS RT_BIT(7)
1108	/** Bits 9-11 - - Available for use to system software. */
1109	#define X86_PDE_AVL_MASK (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
1110	/** Bits 12-31 - - Physical Page number of the next level. */
1111	#define X86_PDE_PG_MASK ( 0xfffff000 )
1112
1113	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1114	#if 1 /* we're using this internally and have to mask of the top 16-bit. */
1115	/* Note: This is kind of dangerous if the guest uses these bits (legally or illegally);
1116	* we partly or that part into shadow page table entries. Will be corrected
1117	* soon.
1118	*/
1119	#define X86_PDE_PAE_PG_MASK ( 0x0000fffffffff000ULL )
1120	#define X86_PDE_PAE_PG_MASK_FULL ( 0x000ffffffffff000ULL )
1121	#else
1122	#define X86_PDE_PAE_PG_MASK ( 0x000ffffffffff000ULL )
1123	#endif
1124	/** Bits 63 - NX - PAE - No execution flag. */
1125	#define X86_PDE_PAE_NX RT_BIT_64(63)
1126
1127	/**
1128	* Page directory entry.
1129	*/
1130	typedef struct X86PDEBITS
1131	{
1132	/** Flags whether(=1) or not the page is present. */
1133	unsigned u1Present : 1;
1134	/** Read(=0) / Write(=1) flag. */
1135	unsigned u1Write : 1;
1136	/** User(=1) / Supervisor (=0) flag. */
1137	unsigned u1User : 1;
1138	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1139	unsigned u1WriteThru : 1;
1140	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1141	unsigned u1CacheDisable : 1;
1142	/** Accessed flag.
1143	* Indicates that the page have been read or written to. */
1144	unsigned u1Accessed : 1;
1145	/** Reserved / Ignored (dirty bit). */
1146	unsigned u1Reserved0 : 1;
1147	/** Size bit if PSE is enabled - in any event it's 0. */
1148	unsigned u1Size : 1;
1149	/** Reserved / Ignored (global bit). */
1150	unsigned u1Reserved1 : 1;
1151	/** Available for use to system software. */
1152	unsigned u3Available : 3;
1153	/** Physical Page number of the next level. */
1154	unsigned u20PageNo : 20;
1155	} X86PDEBITS;
1156	/** Pointer to a page directory entry. */
1157	typedef X86PDEBITS *PX86PDEBITS;
1158	/** Pointer to a const page directory entry. */
1159	typedef const X86PDEBITS *PCX86PDEBITS;
1160
1161
1162	/**
1163	* PAE page directory entry.
1164	*/
1165	typedef struct X86PDEPAEBITS
1166	{
1167	/** Flags whether(=1) or not the page is present. */
1168	uint32_t u1Present : 1;
1169	/** Read(=0) / Write(=1) flag. */
1170	uint32_t u1Write : 1;
1171	/** User(=1) / Supervisor (=0) flag. */
1172	uint32_t u1User : 1;
1173	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1174	uint32_t u1WriteThru : 1;
1175	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1176	uint32_t u1CacheDisable : 1;
1177	/** Accessed flag.
1178	* Indicates that the page have been read or written to. */
1179	uint32_t u1Accessed : 1;
1180	/** Reserved / Ignored (dirty bit). */
1181	uint32_t u1Reserved0 : 1;
1182	/** Size bit if PSE is enabled - in any event it's 0. */
1183	uint32_t u1Size : 1;
1184	/** Reserved / Ignored (global bit). / */
1185	uint32_t u1Reserved1 : 1;
1186	/** Available for use to system software. */
1187	uint32_t u3Available : 3;
1188	/** Physical Page number of the next level - Low Part. Don't use! */
1189	uint32_t u20PageNoLow : 20;
1190	/** Physical Page number of the next level - High Part. Don't use! */
1191	uint32_t u20PageNoHigh : 20;
1192	/** MBZ bits */
1193	uint32_t u11Reserved : 11;
1194	/** No Execute flag. */
1195	uint32_t u1NoExecute : 1;
1196	} X86PDEPAEBITS;
1197	/** Pointer to a page directory entry. */
1198	typedef X86PDEPAEBITS *PX86PDEPAEBITS;
1199	/** Pointer to a const page directory entry. */
1200	typedef const X86PDEPAEBITS *PCX86PDEPAEBITS;
1201
1202	/** @} */
1203
1204
1205	/** @name 2/4MB Page Directory Entry
1206	* @{
1207	*/
1208	/** Bit 0 - P - Present bit. */
1209	#define X86_PDE4M_P RT_BIT(0)
1210	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1211	#define X86_PDE4M_RW RT_BIT(1)
1212	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1213	#define X86_PDE4M_US RT_BIT(2)
1214	/** Bit 3 - PWT - Page level write thru bit. */
1215	#define X86_PDE4M_PWT RT_BIT(3)
1216	/** Bit 4 - PCD - Page level cache disable bit. */
1217	#define X86_PDE4M_PCD RT_BIT(4)
1218	/** Bit 5 - A - Access bit. */
1219	#define X86_PDE4M_A RT_BIT(5)
1220	/** Bit 6 - D - Dirty bit. */
1221	#define X86_PDE4M_D RT_BIT(6)
1222	/** Bit 7 - PS - Page size attribute. Clear mean 4KB pages, set means large pages (2/4MB). */
1223	#define X86_PDE4M_PS RT_BIT(7)
1224	/** Bit 8 - G - Global flag. */
1225	#define X86_PDE4M_G RT_BIT(8)
1226	/** Bits 9-11 - AVL - Available for use to system software. */
1227	#define X86_PDE4M_AVL (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
1228	/** Bit 12 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
1229	#define X86_PDE4M_PAT RT_BIT(12)
1230	/** Shift to get from X86_PTE_PAT to X86_PDE4M_PAT. */
1231	#define X86_PDE4M_PAT_SHIFT (12 - 7)
1232	/** Bits 22-31 - - Physical Page number. */
1233	#define X86_PDE4M_PG_MASK ( 0xffc00000 )
1234	/** Bits 13-20 - - Physical Page number high part (32-39 bits). AMD64 hack. */
1235	#define X86_PDE4M_PG_HIGH_MASK ( 0x001fe000 )
1236	/** The number of bits to the high part of the page number. */
1237	#define X86_PDE4M_PG_HIGH_SHIFT 19
1238
1239	/** Bits 21-51 - - PAE & AMD64 - Physical Page number.
1240	* (Bits 40-51 (long mode) & bits 36-51 (pae legacy) are reserved according to the Intel docs; AMD allows for more.) */
1241	#define X86_PDE2M_PAE_PG_MASK ( 0x000fffffffe00000ULL )
1242	/** Bits 63 - NX - PAE & AMD64 - No execution flag. */
1243	#define X86_PDE2M_PAE_NX X86_PDE2M_PAE_NX
1244
1245	/**
1246	* 4MB page directory entry.
1247	*/
1248	typedef struct X86PDE4MBITS
1249	{
1250	/** Flags whether(=1) or not the page is present. */
1251	unsigned u1Present : 1;
1252	/** Read(=0) / Write(=1) flag. */
1253	unsigned u1Write : 1;
1254	/** User(=1) / Supervisor (=0) flag. */
1255	unsigned u1User : 1;
1256	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1257	unsigned u1WriteThru : 1;
1258	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1259	unsigned u1CacheDisable : 1;
1260	/** Accessed flag.
1261	* Indicates that the page have been read or written to. */
1262	unsigned u1Accessed : 1;
1263	/** Dirty flag.
1264	* Indicates that the page have been written to. */
1265	unsigned u1Dirty : 1;
1266	/** Page size flag - always 1 for 4MB entries. */
1267	unsigned u1Size : 1;
1268	/** Global flag. */
1269	unsigned u1Global : 1;
1270	/** Available for use to system software. */
1271	unsigned u3Available : 3;
1272	/** Reserved / If PAT enabled, bit 2 of the index. */
1273	unsigned u1PAT : 1;
1274	/** Bits 32-39 of the page number on AMD64.
1275	* This AMD64 hack allows accessing 40bits of physical memory without PAE. */
1276	unsigned u8PageNoHigh : 8;
1277	/** Reserved. */
1278	unsigned u1Reserved : 1;
1279	/** Physical Page number of the page. */
1280	unsigned u10PageNo : 10;
1281	} X86PDE4MBITS;
1282	/** Pointer to a page table entry. */
1283	typedef X86PDE4MBITS *PX86PDE4MBITS;
1284	/** Pointer to a const page table entry. */
1285	typedef const X86PDE4MBITS *PCX86PDE4MBITS;
1286
1287
1288	/**
1289	* 2MB PAE page directory entry.
1290	*/
1291	typedef struct X86PDE2MPAEBITS
1292	{
1293	/** Flags whether(=1) or not the page is present. */
1294	uint32_t u1Present : 1;
1295	/** Read(=0) / Write(=1) flag. */
1296	uint32_t u1Write : 1;
1297	/** User(=1) / Supervisor(=0) flag. */
1298	uint32_t u1User : 1;
1299	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1300	uint32_t u1WriteThru : 1;
1301	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1302	uint32_t u1CacheDisable : 1;
1303	/** Accessed flag.
1304	* Indicates that the page have been read or written to. */
1305	uint32_t u1Accessed : 1;
1306	/** Dirty flag.
1307	* Indicates that the page have been written to. */
1308	uint32_t u1Dirty : 1;
1309	/** Page size flag - always 1 for 2MB entries. */
1310	uint32_t u1Size : 1;
1311	/** Global flag. */
1312	uint32_t u1Global : 1;
1313	/** Available for use to system software. */
1314	uint32_t u3Available : 3;
1315	/** Reserved / If PAT enabled, bit 2 of the index. */
1316	uint32_t u1PAT : 1;
1317	/** Reserved. */
1318	uint32_t u9Reserved : 9;
1319	/** Physical Page number of the next level - Low part. Don't use! */
1320	uint32_t u10PageNoLow : 10;
1321	/** Physical Page number of the next level - High part. Don't use! */
1322	uint32_t u20PageNoHigh : 20;
1323	/** MBZ bits */
1324	uint32_t u11Reserved : 11;
1325	/** No Execute flag. */
1326	uint32_t u1NoExecute : 1;
1327	} X86PDE2MPAEBITS;
1328	/** Pointer to a 4MB PAE page table entry. */
1329	typedef X86PDE2MPAEBITS *PX86PDE2MPAEBITS;
1330	/** Pointer to a 4MB PAE page table entry. */
1331	typedef const X86PDE2MPAEBITS *PCX86PDE2MPAEBITS;
1332
1333	/** @} */
1334
1335	/**
1336	* Page directory entry.
1337	*/
1338	typedef union X86PDE
1339	{
1340	/** Normal view. */
1341	X86PDEBITS n;
1342	/** 4MB view (big). */
1343	X86PDE4MBITS b;
1344	/** Unsigned integer view. */
1345	X86PGUINT u;
1346	/** 8 bit unsigned integer view. */
1347	uint8_t au8[4];
1348	/** 16 bit unsigned integer view. */
1349	uint16_t au16[2];
1350	/** 32 bit unsigned integer view. */
1351	uint32_t au32[1];
1352	} X86PDE;
1353	/** Pointer to a page directory entry. */
1354	typedef X86PDE *PX86PDE;
1355	/** Pointer to a const page directory entry. */
1356	typedef const X86PDE *PCX86PDE;
1357
1358	/**
1359	* PAE page directory entry.
1360	*/
1361	typedef union X86PDEPAE
1362	{
1363	/** Normal view. */
1364	X86PDEPAEBITS n;
1365	/** 2MB page view (big). */
1366	X86PDE2MPAEBITS b;
1367	/** Unsigned integer view. */
1368	X86PGPAEUINT u;
1369	/** 8 bit unsigned integer view. */
1370	uint8_t au8[8];
1371	/** 16 bit unsigned integer view. */
1372	uint16_t au16[4];
1373	/** 32 bit unsigned integer view. */
1374	uint32_t au32[2];
1375	} X86PDEPAE;
1376	/** Pointer to a page directory entry. */
1377	typedef X86PDEPAE *PX86PDEPAE;
1378	/** Pointer to a const page directory entry. */
1379	typedef const X86PDEPAE *PCX86PDEPAE;
1380
1381	/**
1382	* Page directory.
1383	*/
1384	typedef struct X86PD
1385	{
1386	/** PDE Array. */
1387	X86PDE a[X86_PG_ENTRIES];
1388	} X86PD;
1389	/** Pointer to a page directory. */
1390	typedef X86PD *PX86PD;
1391	/** Pointer to a const page directory. */
1392	typedef const X86PD *PCX86PD;
1393
1394	/** The page shift to get the PD index. */
1395	#define X86_PD_SHIFT 22
1396	/** The PD index mask (apply to a shifted page address). */
1397	#define X86_PD_MASK 0x3ff
1398
1399
1400	/**
1401	* PAE page directory.
1402	*/
1403	typedef struct X86PDPAE
1404	{
1405	/** PDE Array. */
1406	X86PDEPAE a[X86_PG_PAE_ENTRIES];
1407	} X86PDPAE;
1408	/** Pointer to a PAE page directory. */
1409	typedef X86PDPAE *PX86PDPAE;
1410	/** Pointer to a const PAE page directory. */
1411	typedef const X86PDPAE *PCX86PDPAE;
1412
1413	/** The page shift to get the PAE PD index. */
1414	#define X86_PD_PAE_SHIFT 21
1415	/** The PAE PD index mask (apply to a shifted page address). */
1416	#define X86_PD_PAE_MASK 0x1ff
1417
1418
1419	/** @name Page Directory Pointer Table Entry (PAE)
1420	* @{
1421	*/
1422	/** Bit 0 - P - Present bit. */
1423	#define X86_PDPE_P RT_BIT(0)
1424	/** Bit 1 - R/W - Read (clear) / Write (set) bit. Long Mode only. */
1425	#define X86_PDPE_RW RT_BIT(1)
1426	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. Long Mode only. */
1427	#define X86_PDPE_US RT_BIT(2)
1428	/** Bit 3 - PWT - Page level write thru bit. */
1429	#define X86_PDPE_PWT RT_BIT(3)
1430	/** Bit 4 - PCD - Page level cache disable bit. */
1431	#define X86_PDPE_PCD RT_BIT(4)
1432	/** Bit 5 - A - Access bit. Long Mode only. */
1433	#define X86_PDPE_A RT_BIT(5)
1434	/** Bits 9-11 - - Available for use to system software. */
1435	#define X86_PDPE_AVL_MASK (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
1436	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1437	#if 1 /* we're using this internally and have to mask of the top 16-bit. */
1438	#define X86_PDPE_PG_MASK ( 0x0000fffffffff000ULL )
1439	/** @todo Get rid of the above hack; makes code unreadable. */
1440	#define X86_PDPE_PG_MASK_FULL ( 0x000ffffffffff000ULL )
1441	#else
1442	#define X86_PDPE_PG_MASK ( 0x000ffffffffff000ULL )
1443	#endif
1444	/** Bits 63 - NX - PAE - No execution flag. Long Mode only. */
1445	#define X86_PDPE_NX RT_BIT_64(63)
1446
1447	/**
1448	* Page directory pointer table entry.
1449	*/
1450	typedef struct X86PDPEBITS
1451	{
1452	/** Flags whether(=1) or not the page is present. */
1453	uint32_t u1Present : 1;
1454	/** Chunk of reserved bits. */
1455	uint32_t u2Reserved : 2;
1456	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1457	uint32_t u1WriteThru : 1;
1458	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1459	uint32_t u1CacheDisable : 1;
1460	/** Chunk of reserved bits. */
1461	uint32_t u4Reserved : 4;
1462	/** Available for use to system software. */
1463	uint32_t u3Available : 3;
1464	/** Physical Page number of the next level - Low Part. Don't use! */
1465	uint32_t u20PageNoLow : 20;
1466	/** Physical Page number of the next level - High Part. Don't use! */
1467	uint32_t u20PageNoHigh : 20;
1468	/** MBZ bits */
1469	uint32_t u12Reserved : 12;
1470	} X86PDPEBITS;
1471	/** Pointer to a page directory pointer table entry. */
1472	typedef X86PDPEBITS *PX86PTPEBITS;
1473	/** Pointer to a const page directory pointer table entry. */
1474	typedef const X86PDPEBITS *PCX86PTPEBITS;
1475
1476	/**
1477	* Page directory pointer table entry. AMD64 version
1478	*/
1479	typedef struct X86PDPEAMD64BITS
1480	{
1481	/** Flags whether(=1) or not the page is present. */
1482	uint32_t u1Present : 1;
1483	/** Read(=0) / Write(=1) flag. */
1484	uint32_t u1Write : 1;
1485	/** User(=1) / Supervisor (=0) flag. */
1486	uint32_t u1User : 1;
1487	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1488	uint32_t u1WriteThru : 1;
1489	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1490	uint32_t u1CacheDisable : 1;
1491	/** Accessed flag.
1492	* Indicates that the page have been read or written to. */
1493	uint32_t u1Accessed : 1;
1494	/** Chunk of reserved bits. */
1495	uint32_t u3Reserved : 3;
1496	/** Available for use to system software. */
1497	uint32_t u3Available : 3;
1498	/** Physical Page number of the next level - Low Part. Don't use! */
1499	uint32_t u20PageNoLow : 20;
1500	/** Physical Page number of the next level - High Part. Don't use! */
1501	uint32_t u20PageNoHigh : 20;
1502	/** MBZ bits */
1503	uint32_t u11Reserved : 11;
1504	/** No Execute flag. */
1505	uint32_t u1NoExecute : 1;
1506	} X86PDPEAMD64BITS;
1507	/** Pointer to a page directory pointer table entry. */
1508	typedef X86PDPEAMD64BITS *PX86PDPEAMD64BITS;
1509	/** Pointer to a const page directory pointer table entry. */
1510	typedef const X86PDPEBITS *PCX86PDPEAMD64BITS;
1511
1512	/**
1513	* Page directory pointer table entry.
1514	*/
1515	typedef union X86PDPE
1516	{
1517	/** Normal view. */
1518	X86PDPEBITS n;
1519	/** AMD64 view. */
1520	X86PDPEAMD64BITS lm;
1521	/** Unsigned integer view. */
1522	X86PGPAEUINT u;
1523	/** 8 bit unsigned integer view. */
1524	uint8_t au8[8];
1525	/** 16 bit unsigned integer view. */
1526	uint16_t au16[4];
1527	/** 32 bit unsigned integer view. */
1528	uint32_t au32[2];
1529	} X86PDPE;
1530	/** Pointer to a page directory pointer table entry. */
1531	typedef X86PDPE *PX86PDPE;
1532	/** Pointer to a const page directory pointer table entry. */
1533	typedef const X86PDPE *PCX86PDPE;
1534
1535
1536	/**
1537	* Page directory pointer table.
1538	*/
1539	typedef struct X86PDPT
1540	{
1541	/** PDE Array. */
1542	X86PDPE a[X86_PG_AMD64_PDPE_ENTRIES];
1543	} X86PDPT;
1544	/** Pointer to a page directory pointer table. */
1545	typedef X86PDPT *PX86PDPT;
1546	/** Pointer to a const page directory pointer table. */
1547	typedef const X86PDPT *PCX86PDPT;
1548
1549	/** The page shift to get the PDPT index. */
1550	#define X86_PDPT_SHIFT 30
1551	/** The PDPT index mask (apply to a shifted page address). (32 bits PAE) */
1552	#define X86_PDPT_MASK_PAE 0x3
1553	/** The PDPT index mask (apply to a shifted page address). (64 bits PAE)*/
1554	#define X86_PDPT_MASK_AMD64 0x1ff
1555
1556	/** @} */
1557
1558
1559	/** @name Page Map Level-4 Entry (Long Mode PAE)
1560	* @{
1561	*/
1562	/** Bit 0 - P - Present bit. */
1563	#define X86_PML4E_P RT_BIT(0)
1564	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1565	#define X86_PML4E_RW RT_BIT(1)
1566	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1567	#define X86_PML4E_US RT_BIT(2)
1568	/** Bit 3 - PWT - Page level write thru bit. */
1569	#define X86_PML4E_PWT RT_BIT(3)
1570	/** Bit 4 - PCD - Page level cache disable bit. */
1571	#define X86_PML4E_PCD RT_BIT(4)
1572	/** Bit 5 - A - Access bit. */
1573	#define X86_PML4E_A RT_BIT(5)
1574	/** Bits 9-11 - - Available for use to system software. */
1575	#define X86_PML4E_AVL_MASK (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
1576	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1577	#if 1 /* we're using this internally and have to mask of the top 16-bit. */
1578	#define X86_PML4E_PG_MASK ( 0x0000fffffffff000ULL )
1579	#define X86_PML4E_PG_MASK_FULL ( 0x000ffffffffff000ULL )
1580	#else
1581	#define X86_PML4E_PG_MASK ( 0x000ffffffffff000ULL )
1582	#endif
1583	/** Bits 63 - NX - PAE - No execution flag. */
1584	#define X86_PML4E_NX RT_BIT_64(63)
1585
1586	/**
1587	* Page Map Level-4 Entry
1588	*/
1589	typedef struct X86PML4EBITS
1590	{
1591	/** Flags whether(=1) or not the page is present. */
1592	uint32_t u1Present : 1;
1593	/** Read(=0) / Write(=1) flag. */
1594	uint32_t u1Write : 1;
1595	/** User(=1) / Supervisor (=0) flag. */
1596	uint32_t u1User : 1;
1597	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1598	uint32_t u1WriteThru : 1;
1599	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1600	uint32_t u1CacheDisable : 1;
1601	/** Accessed flag.
1602	* Indicates that the page have been read or written to. */
1603	uint32_t u1Accessed : 1;
1604	/** Chunk of reserved bits. */
1605	uint32_t u3Reserved : 3;
1606	/** Available for use to system software. */
1607	uint32_t u3Available : 3;
1608	/** Physical Page number of the next level - Low Part. Don't use! */
1609	uint32_t u20PageNoLow : 20;
1610	/** Physical Page number of the next level - High Part. Don't use! */
1611	uint32_t u20PageNoHigh : 20;
1612	/** MBZ bits */
1613	uint32_t u11Reserved : 11;
1614	/** No Execute flag. */
1615	uint32_t u1NoExecute : 1;
1616	} X86PML4EBITS;
1617	/** Pointer to a page map level-4 entry. */
1618	typedef X86PML4EBITS *PX86PML4EBITS;
1619	/** Pointer to a const page map level-4 entry. */
1620	typedef const X86PML4EBITS *PCX86PML4EBITS;
1621
1622	/**
1623	* Page Map Level-4 Entry.
1624	*/
1625	typedef union X86PML4E
1626	{
1627	/** Normal view. */
1628	X86PML4EBITS n;
1629	/** Unsigned integer view. */
1630	X86PGPAEUINT u;
1631	/** 8 bit unsigned integer view. */
1632	uint8_t au8[8];
1633	/** 16 bit unsigned integer view. */
1634	uint16_t au16[4];
1635	/** 32 bit unsigned integer view. */
1636	uint32_t au32[2];
1637	} X86PML4E;
1638	/** Pointer to a page map level-4 entry. */
1639	typedef X86PML4E *PX86PML4E;
1640	/** Pointer to a const page map level-4 entry. */
1641	typedef const X86PML4E *PCX86PML4E;
1642
1643
1644	/**
1645	* Page Map Level-4.
1646	*/
1647	typedef struct X86PML4
1648	{
1649	/** PDE Array. */
1650	X86PML4E a[X86_PG_PAE_ENTRIES];
1651	} X86PML4;
1652	/** Pointer to a page map level-4. */
1653	typedef X86PML4 *PX86PML4;
1654	/** Pointer to a const page map level-4. */
1655	typedef const X86PML4 *PCX86PML4;
1656
1657	/** The page shift to get the PML4 index. */
1658	#define X86_PML4_SHIFT 39
1659	/** The PML4 index mask (apply to a shifted page address). */
1660	#define X86_PML4_MASK 0x1ff
1661
1662	/** @} */
1663
1664	/** @} */
1665
1666
1667	/**
1668	* 80-bit MMX/FPU register type.
1669	*/
1670	typedef struct X86FPUMMX
1671	{
1672	uint8_t reg[10];
1673	} X86FPUMMX;
1674	/** Pointer to a 80-bit MMX/FPU register type. */
1675	typedef X86FPUMMX *PX86FPUMMX;
1676	/** Pointer to a const 80-bit MMX/FPU register type. */
1677	typedef const X86FPUMMX *PCX86FPUMMX;
1678
1679	/**
1680	* FPU state (aka FSAVE/FRSTOR Memory Region).
1681	*/
1682	#pragma pack(1)
1683	typedef struct X86FPUSTATE
1684	{
1685	/** Control word. */
1686	uint16_t FCW;
1687	/** Alignment word */
1688	uint16_t Dummy1;
1689	/** Status word. */
1690	uint16_t FSW;
1691	/** Alignment word */
1692	uint16_t Dummy2;
1693	/** Tag word */
1694	uint16_t FTW;
1695	/** Alignment word */
1696	uint16_t Dummy3;
1697
1698	/** Instruction pointer. */
1699	uint32_t FPUIP;
1700	/** Code selector. */
1701	uint16_t CS;
1702	/** Opcode. */
1703	uint16_t FOP;
1704	/** FOO. */
1705	uint32_t FPUOO;
1706	/** FOS. */
1707	uint32_t FPUOS;
1708	/** FPU view - todo. */
1709	X86FPUMMX regs[8];
1710	} X86FPUSTATE;
1711	#pragma pack()
1712	/** Pointer to a FPU state. */
1713	typedef X86FPUSTATE *PX86FPUSTATE;
1714	/** Pointer to a const FPU state. */
1715	typedef const X86FPUSTATE *PCX86FPUSTATE;
1716
1717	/**
1718	* FPU Extended state (aka FXSAVE/FXRSTORE Memory Region).
1719	*/
1720	#pragma pack(1)
1721	typedef struct X86FXSTATE
1722	{
1723	/** Control word. */
1724	uint16_t FCW;
1725	/** Status word. */
1726	uint16_t FSW;
1727	/** Tag word (it's a byte actually). */
1728	uint8_t FTW;
1729	uint8_t huh1;
1730	/** Opcode. */
1731	uint16_t FOP;
1732	/** Instruction pointer. */
1733	uint32_t FPUIP;
1734	/** Code selector. */
1735	uint16_t CS;
1736	uint16_t Rsvrd1;
1737	/* - offset 16 - */
1738	/** Data pointer. */
1739	uint32_t FPUDP;
1740	/** Data segment */
1741	uint16_t DS;
1742	uint16_t Rsrvd2;
1743	uint32_t MXCSR;
1744	uint32_t MXCSR_MASK;
1745	/* - offset 32 - */
1746	union
1747	{
1748	/** MMX view. */
1749	uint64_t mmx;
1750	/** FPU view - todo. */
1751	X86FPUMMX fpu;
1752	/** 8-bit view. */
1753	uint8_t au8[16];
1754	/** 16-bit view. */
1755	uint16_t au16[8];
1756	/** 32-bit view. */
1757	uint32_t au32[4];
1758	/** 64-bit view. */
1759	uint64_t au64[2];
1760	/** 128-bit view. (yeah, very helpful) */
1761	uint128_t au128[1];
1762	} aRegs[8];
1763	/* - offset 160 - */
1764	union
1765	{
1766	/** XMM Register view . /
1767	uint128_t xmm;
1768	/** 8-bit view. */
1769	uint8_t au8[16];
1770	/** 16-bit view. */
1771	uint16_t au16[8];
1772	/** 32-bit view. */
1773	uint32_t au32[4];
1774	/** 64-bit view. */
1775	uint64_t au64[2];
1776	/** 128-bit view. (yeah, very helpful) */
1777	uint128_t au128[1];
1778	} aXMM[16]; /* 8 registers in 32 bits mode; 16 in long mode */
1779	/* - offset 416 - */
1780	uint32_t au32RsrvdRest[(512 - 416) / sizeof(uint32_t)];
1781	} X86FXSTATE;
1782	#pragma pack()
1783	/** Pointer to a FPU Extended state. */
1784	typedef X86FXSTATE *PX86FXSTATE;
1785	/** Pointer to a const FPU Extended state. */
1786	typedef const X86FXSTATE *PCX86FXSTATE;
1787
1788
1789	/** @name Selector Descriptor
1790	* @{
1791	*/
1792
1793	/**
1794	* Generic descriptor table entry
1795	*/
1796	#pragma pack(1)
1797	typedef struct X86DESCGENERIC
1798	{
1799	/** Limit - Low word. */
1800	unsigned u16LimitLow : 16;
1801	/** Base address - lowe word.
1802	* Don't try set this to 24 because MSC is doing studing things then. */
1803	unsigned u16BaseLow : 16;
1804	/** Base address - first 8 bits of high word. */
1805	unsigned u8BaseHigh1 : 8;
1806	/** Segment Type. */
1807	unsigned u4Type : 4;
1808	/** Descriptor Type. System(=0) or code/data selector */
1809	unsigned u1DescType : 1;
1810	/** Descriptor Privelege level. */
1811	unsigned u2Dpl : 2;
1812	/** Flags selector present(=1) or not. */
1813	unsigned u1Present : 1;
1814	/** Segment limit 16-19. */
1815	unsigned u4LimitHigh : 4;
1816	/** Available for system software. */
1817	unsigned u1Available : 1;
1818	/** 32 bits mode: Reserved - 0, long mode: Long Attribute Bit. */
1819	unsigned u1Long : 1;
1820	/** This flags meaning depends on the segment type. Try make sense out
1821	* of the intel manual yourself. */
1822	unsigned u1DefBig : 1;
1823	/** Granularity of the limit. If set 4KB granularity is used, if
1824	* clear byte. */
1825	unsigned u1Granularity : 1;
1826	/** Base address - highest 8 bits. */
1827	unsigned u8BaseHigh2 : 8;
1828	} X86DESCGENERIC;
1829	#pragma pack()
1830	/** Pointer to a generic descriptor entry. */
1831	typedef X86DESCGENERIC *PX86DESCGENERIC;
1832	/** Pointer to a const generic descriptor entry. */
1833	typedef const X86DESCGENERIC *PCX86DESCGENERIC;
1834
1835
1836	/**
1837	* Descriptor attributes.
1838	*/
1839	typedef struct X86DESCATTRBITS
1840	{
1841	/** Segment Type. */
1842	unsigned u4Type : 4;
1843	/** Descriptor Type. System(=0) or code/data selector */
1844	unsigned u1DescType : 1;
1845	/** Descriptor Privelege level. */
1846	unsigned u2Dpl : 2;
1847	/** Flags selector present(=1) or not. */
1848	unsigned u1Present : 1;
1849	/** Segment limit 16-19. */
1850	unsigned u4LimitHigh : 4;
1851	/** Available for system software. */
1852	unsigned u1Available : 1;
1853	/** 32 bits mode: Reserved - 0, long mode: Long Attribute Bit. */
1854	unsigned u1Long : 1;
1855	/** This flags meaning depends on the segment type. Try make sense out
1856	* of the intel manual yourself. */
1857	unsigned u1DefBig : 1;
1858	/** Granularity of the limit. If set 4KB granularity is used, if
1859	* clear byte. */
1860	unsigned u1Granularity : 1;
1861	} X86DESCATTRBITS;
1862
1863
1864	#pragma pack(1)
1865	typedef union X86DESCATTR
1866	{
1867	/** Normal view. */
1868	X86DESCATTRBITS n;
1869	/** Unsigned integer view. */
1870	uint32_t u;
1871	} X86DESCATTR;
1872	#pragma pack()
1873
1874	/** Pointer to descriptor attributes. */
1875	typedef X86DESCATTR *PX86DESCATTR;
1876	/** Pointer to const descriptor attributes. */
1877	typedef const X86DESCATTR *PCX86DESCATTR;
1878
1879
1880	/**
1881	* Descriptor table entry.
1882	*/
1883	#pragma pack(1)
1884	typedef union X86DESC
1885	{
1886	/** Generic descriptor view. */
1887	X86DESCGENERIC Gen;
1888	#if 0
1889	/** IDT view. */
1890	VBOXIDTE Idt;
1891	#endif
1892
1893	/** 8 bit unsigned interger view. */
1894	uint8_t au8[8];
1895	/** 16 bit unsigned interger view. */
1896	uint16_t au16[4];
1897	/** 32 bit unsigned interger view. */
1898	uint32_t au32[2];
1899	} X86DESC;
1900	#pragma pack()
1901	/** Pointer to descriptor table entry. */
1902	typedef X86DESC *PX86DESC;
1903	/** Pointer to const descriptor table entry. */
1904	typedef const X86DESC *PCX86DESC;
1905
1906
1907	/** @def X86DESC_BASE
1908	* Return the base address of a descriptor.
1909	*/
1910	#define X86DESC_BASE(desc) \
1911	( ((uint32_t)((desc).Gen.u8BaseHigh2) << 24) \
1912	\| ( (desc).Gen.u8BaseHigh1 << 16) \
1913	\| ( (desc).Gen.u16BaseLow ) )
1914
1915	/** @def X86DESC_LIMIT
1916	* Return the limit of a descriptor.
1917	*/
1918	#define X86DESC_LIMIT(desc) \
1919	( ((uint32_t)((desc).Gen.u4LimitHigh) << 16) \
1920	\| ( (desc).Gen.u16LimitLow ) )
1921
1922	/**
1923	* 64 bits generic descriptor table entry
1924	* Note: most of these bits have no meaning in long mode.
1925	*/
1926	#pragma pack(1)
1927	typedef struct X86DESC64GENERIC
1928	{
1929	/** Limit - Low word - IGNORED. */
1930	unsigned u16LimitLow : 16;
1931	/** Base address - lowe word. - IGNORED
1932	* Don't try set this to 24 because MSC is doing studing things then. */
1933	unsigned u16BaseLow : 16;
1934	/** Base address - first 8 bits of high word. - IGNORED */
1935	unsigned u8BaseHigh1 : 8;
1936	/** Segment Type. */
1937	unsigned u4Type : 4;
1938	/** Descriptor Type. System(=0) or code/data selector */
1939	unsigned u1DescType : 1;
1940	/** Descriptor Privelege level. */
1941	unsigned u2Dpl : 2;
1942	/** Flags selector present(=1) or not. */
1943	unsigned u1Present : 1;
1944	/** Segment limit 16-19. - IGNORED */
1945	unsigned u4LimitHigh : 4;
1946	/** Available for system software. - IGNORED */
1947	unsigned u1Available : 1;
1948	/** Long mode flag. */
1949	unsigned u1Long : 1;
1950	/** This flags meaning depends on the segment type. Try make sense out
1951	* of the intel manual yourself. */
1952	unsigned u1DefBig : 1;
1953	/** Granularity of the limit. If set 4KB granularity is used, if
1954	* clear byte. - IGNORED */
1955	unsigned u1Granularity : 1;
1956	/** Base address - highest 8 bits. - IGNORED */
1957	unsigned u8BaseHigh2 : 8;
1958	/** Base address - bits 63-32. */
1959	unsigned u32BaseHigh3 : 32;
1960	unsigned u8Reserved : 8;
1961	unsigned u5Zeros : 5;
1962	unsigned u19Reserved : 19;
1963	} X86DESC64GENERIC;
1964	#pragma pack()
1965	/** Pointer to a generic descriptor entry. */
1966	typedef X86DESC64GENERIC *PX86DESC64GENERIC;
1967	/** Pointer to a const generic descriptor entry. */
1968	typedef const X86DESC64GENERIC *PCX86DESC64GENERIC;
1969
1970	/**
1971	* System descriptor table entry (64 bits)
1972	*/
1973	#pragma pack(1)
1974	typedef struct X86DESC64SYSTEM
1975	{
1976	/** Limit - Low word. */
1977	unsigned u16LimitLow : 16;
1978	/** Base address - lowe word.
1979	* Don't try set this to 24 because MSC is doing studing things then. */
1980	unsigned u16BaseLow : 16;
1981	/** Base address - first 8 bits of high word. */
1982	unsigned u8BaseHigh1 : 8;
1983	/** Segment Type. */
1984	unsigned u4Type : 4;
1985	/** Descriptor Type. System(=0) or code/data selector */
1986	unsigned u1DescType : 1;
1987	/** Descriptor Privelege level. */
1988	unsigned u2Dpl : 2;
1989	/** Flags selector present(=1) or not. */
1990	unsigned u1Present : 1;
1991	/** Segment limit 16-19. */
1992	unsigned u4LimitHigh : 4;
1993	/** Available for system software. */
1994	unsigned u1Available : 1;
1995	/** Reserved - 0. */
1996	unsigned u1Reserved : 1;
1997	/** This flags meaning depends on the segment type. Try make sense out
1998	* of the intel manual yourself. */
1999	unsigned u1DefBig : 1;
2000	/** Granularity of the limit. If set 4KB granularity is used, if
2001	* clear byte. */
2002	unsigned u1Granularity : 1;
2003	/** Base address - bits 31-24. */
2004	unsigned u8BaseHigh2 : 8;
2005	/** Base address - bits 63-32. */
2006	unsigned u32BaseHigh3 : 32;
2007	unsigned u8Reserved : 8;
2008	unsigned u5Zeros : 5;
2009	unsigned u19Reserved : 19;
2010	} X86DESC64SYSTEM;
2011	#pragma pack()
2012	/** Pointer to a generic descriptor entry. */
2013	typedef X86DESC64SYSTEM *PX86DESC64SYSTEM;
2014	/** Pointer to a const generic descriptor entry. */
2015	typedef const X86DESC64SYSTEM *PCX86DESC64SYSTEM;
2016
2017
2018	/**
2019	* Descriptor table entry.
2020	*/
2021	#pragma pack(1)
2022	typedef union X86DESC64
2023	{
2024	/** Generic descriptor view. */
2025	X86DESC64GENERIC Gen;
2026	/** System descriptor view. */
2027	X86DESC64SYSTEM System;
2028	#if 0
2029	X86DESC64GATE Gate;
2030	#endif
2031
2032	/** 8 bit unsigned interger view. */
2033	uint8_t au8[16];
2034	/** 16 bit unsigned interger view. */
2035	uint16_t au16[8];
2036	/** 32 bit unsigned interger view. */
2037	uint32_t au32[4];
2038	/** 64 bit unsigned interger view. */
2039	uint64_t au64[2];
2040	} X86DESC64;
2041	#pragma pack()
2042	/** Pointer to descriptor table entry. */
2043	typedef X86DESC64 *PX86DESC64;
2044	/** Pointer to const descriptor table entry. */
2045	typedef const X86DESC64 *PCX86DESC64;
2046
2047	#if HC_ARCH_BITS == 64
2048	typedef X86DESC64 X86DESCHC;
2049	typedef X86DESC64 *PX86DESCHC;
2050	#else
2051	typedef X86DESC X86DESCHC;
2052	typedef X86DESC *PX86DESCHC;
2053	#endif
2054
2055	/** @def X86DESC_LIMIT
2056	* Return the base of a 64-bit descriptor.
2057	*/
2058	#define X86DESC64_BASE(desc) \
2059	( ((uint64_t)((desc).Gen.u32BaseHigh3) << 32) \
2060	\| ((uint32_t)((desc).Gen.u8BaseHigh2) << 24) \
2061	\| ( (desc).Gen.u8BaseHigh1 << 16) \
2062	\| ( (desc).Gen.u16BaseLow ) )
2063
2064
2065	/** @name Selector Descriptor Types.
2066	* @{
2067	*/
2068
2069	/** @name Non-System Selector Types.
2070	* @{ */
2071	/** Code(=set)/Data(=clear) bit. */
2072	#define X86_SEL_TYPE_CODE 8
2073	/** Memory(=set)/System(=clear) bit. */
2074	#define X86_SEL_TYPE_MEMORY RT_BIT(4)
2075	/** Accessed bit. */
2076	#define X86_SEL_TYPE_ACCESSED 1
2077	/** Expand down bit (for data selectors only). */
2078	#define X86_SEL_TYPE_DOWN 4
2079	/** Conforming bit (for code selectors only). */
2080	#define X86_SEL_TYPE_CONF 4
2081	/** Write bit (for data selectors only). */
2082	#define X86_SEL_TYPE_WRITE 2
2083	/** Read bit (for code selectors only). */
2084	#define X86_SEL_TYPE_READ 2
2085
2086	/** Read only selector type. */
2087	#define X86_SEL_TYPE_RO 0
2088	/** Accessed read only selector type. */
2089	#define X86_SEL_TYPE_RO_ACC (0 \| X86_SEL_TYPE_ACCESSED)
2090	/** Read write selector type. */
2091	#define X86_SEL_TYPE_RW 2
2092	/** Accessed read write selector type. */
2093	#define X86_SEL_TYPE_RW_ACC (2 \| X86_SEL_TYPE_ACCESSED)
2094	/** Expand down read only selector type. */
2095	#define X86_SEL_TYPE_RO_DOWN 4
2096	/** Accessed expand down read only selector type. */
2097	#define X86_SEL_TYPE_RO_DOWN_ACC (4 \| X86_SEL_TYPE_ACCESSED)
2098	/** Expand down read write selector type. */
2099	#define X86_SEL_TYPE_RW_DOWN 6
2100	/** Accessed expand down read write selector type. */
2101	#define X86_SEL_TYPE_RW_DOWN_ACC (6 \| X86_SEL_TYPE_ACCESSED)
2102	/** Execute only selector type. */
2103	#define X86_SEL_TYPE_EO (0 \| X86_SEL_TYPE_CODE)
2104	/** Accessed execute only selector type. */
2105	#define X86_SEL_TYPE_EO_ACC (0 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
2106	/** Execute and read selector type. */
2107	#define X86_SEL_TYPE_ER (2 \| X86_SEL_TYPE_CODE)
2108	/** Accessed execute and read selector type. */
2109	#define X86_SEL_TYPE_ER_ACC (2 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
2110	/** Conforming execute only selector type. */
2111	#define X86_SEL_TYPE_EO_CONF (4 \| X86_SEL_TYPE_CODE)
2112	/** Accessed Conforming execute only selector type. */
2113	#define X86_SEL_TYPE_EO_CONF_ACC (4 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
2114	/** Conforming execute and write selector type. */
2115	#define X86_SEL_TYPE_ER_CONF (6 \| X86_SEL_TYPE_CODE)
2116	/** Accessed Conforming execute and write selector type. */
2117	#define X86_SEL_TYPE_ER_CONF_ACC (6 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
2118	/** @} */
2119
2120
2121	/** @name System Selector Types.
2122	* @{ */
2123	/** Undefined system selector type. */
2124	#define X86_SEL_TYPE_SYS_UNDEFINED 0
2125	/** 286 TSS selector. */
2126	#define X86_SEL_TYPE_SYS_286_TSS_AVAIL 1
2127	/** LDT selector. */
2128	#define X86_SEL_TYPE_SYS_LDT 2
2129	/** 286 TSS selector - Busy. */
2130	#define X86_SEL_TYPE_SYS_286_TSS_BUSY 3
2131	/** 286 Callgate selector. */
2132	#define X86_SEL_TYPE_SYS_286_CALL_GATE 4
2133	/** Taskgate selector. */
2134	#define X86_SEL_TYPE_SYS_TASK_GATE 5
2135	/** 286 Interrupt gate selector. */
2136	#define X86_SEL_TYPE_SYS_286_INT_GATE 6
2137	/** 286 Trapgate selector. */
2138	#define X86_SEL_TYPE_SYS_286_TRAP_GATE 7
2139	/** Undefined system selector. */
2140	#define X86_SEL_TYPE_SYS_UNDEFINED2 8
2141	/** 386 TSS selector. */
2142	#define X86_SEL_TYPE_SYS_386_TSS_AVAIL 9
2143	/** Undefined system selector. */
2144	#define X86_SEL_TYPE_SYS_UNDEFINED3 0xA
2145	/** 386 TSS selector - Busy. */
2146	#define X86_SEL_TYPE_SYS_386_TSS_BUSY 0xB
2147	/** 386 Callgate selector. */
2148	#define X86_SEL_TYPE_SYS_386_CALL_GATE 0xC
2149	/** Undefined system selector. */
2150	#define X86_SEL_TYPE_SYS_UNDEFINED4 0xD
2151	/** 386 Interruptgate selector. */
2152	#define X86_SEL_TYPE_SYS_386_INT_GATE 0xE
2153	/** 386 Trapgate selector. */
2154	#define X86_SEL_TYPE_SYS_386_TRAP_GATE 0xF
2155	/** @} */
2156
2157	/** @name AMD64 System Selector Types.
2158	* @{ */
2159	#define AMD64_SEL_TYPE_SYS_LDT 2
2160	/** 286 TSS selector - Busy. */
2161	#define AMD64_SEL_TYPE_SYS_TSS_AVAIL 9
2162	/** 386 TSS selector - Busy. */
2163	#define AMD64_SEL_TYPE_SYS_TSS_BUSY 0xB
2164	/** 386 Callgate selector. */
2165	#define AMD64_SEL_TYPE_SYS_CALL_GATE 0xC
2166	/** 386 Interruptgate selector. */
2167	#define AMD64_SEL_TYPE_SYS_INT_GATE 0xE
2168	/** 386 Trapgate selector. */
2169	#define AMD64_SEL_TYPE_SYS_TRAP_GATE 0xF
2170	/** @} */
2171
2172	/** @} */
2173
2174
2175	/** @name Descriptor Table Entry Flag Masks.
2176	* These are for the 2nd 32-bit word of a descriptor.
2177	* @{ */
2178	/** Bits 8-11 - TYPE - Descriptor type mask. */
2179	#define X86_DESC_TYPE_MASK (RT_BIT(8) \| RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
2180	/** Bit 12 - S - System (=0) or Code/Data (=1). */
2181	#define X86_DESC_S RT_BIT(12)
2182	/** Bits 13-14 - DPL - Descriptor Privilege Level. */
2183	#define X86_DESC_DPL (RT_BIT(13) \| RT_BIT(14))
2184	/** Bit 15 - P - Present. */
2185	#define X86_DESC_P RT_BIT(15)
2186	/** Bit 20 - AVL - Available for system software. */
2187	#define X86_DESC_AVL RT_BIT(20)
2188	/** Bit 22 - DB - Default operation size. 0 = 16 bit, 1 = 32 bit. */
2189	#define X86_DESC_DB RT_BIT(22)
2190	/** Bit 23 - G - Granularity of the limit. If set 4KB granularity is
2191	* used, if clear byte. */
2192	#define X86_DESC_G RT_BIT(23)
2193	/** @} */
2194
2195	/** @} */
2196
2197
2198	/** @name Selectors.
2199	* @{
2200	*/
2201
2202	/**
2203	* The shift used to convert a selector from and to index an index (C).
2204	*/
2205	#define X86_SEL_SHIFT 3
2206
2207	/**
2208	* The shift used to convert a selector from and to index an index (C).
2209	*/
2210	#define AMD64_SEL_SHIFT 4
2211
2212	#if HC_ARCH_BITS == 64
2213	#define X86_SEL_SHIFT_HC AMD64_SEL_SHIFT
2214	#else
2215	#define X86_SEL_SHIFT_HC X86_SEL_SHIFT
2216	#endif
2217
2218	/**
2219	* The mask used to mask off the table indicator and CPL of an selector.
2220	*/
2221	#define X86_SEL_MASK 0xfff8
2222
2223	/**
2224	* The bit indicating that a selector is in the LDT and not in the GDT.
2225	*/
2226	#define X86_SEL_LDT 0x0004
2227	/**
2228	* The bit mask for getting the RPL of a selector.
2229	*/
2230	#define X86_SEL_RPL 0x0003
2231
2232	/** @} */
2233
2234
2235	/**
2236	* x86 Exceptions/Faults/Traps.
2237	*/
2238	typedef enum X86XCPT
2239	{
2240	/** \#DE - Divide error. */
2241	X86_XCPT_DE = 0x00,
2242	/** \#DB - Debug event (single step, DRx, ..) */
2243	X86_XCPT_DB = 0x01,
2244	/** NMI - Non-Maskable Interrupt */
2245	X86_XCPT_NMI = 0x02,
2246	/** \#BP - Breakpoint (INT3). */
2247	X86_XCPT_BP = 0x03,
2248	/** \#OF - Overflow (INTO). */
2249	X86_XCPT_OF = 0x04,
2250	/** \#BR - Bound range exceeded (BOUND). */
2251	X86_XCPT_BR = 0x05,
2252	/** \#UD - Undefined opcode. */
2253	X86_XCPT_UD = 0x06,
2254	/** \#NM - Device not available (math coprocessor device). */
2255	X86_XCPT_NM = 0x07,
2256	/** \#DF - Double fault. */
2257	X86_XCPT_DF = 0x08,
2258	/** ??? - Coprocessor segment overrun (obsolete). */
2259	X86_XCPT_CO_SEG_OVERRUN = 0x09,
2260	/** \#TS - Taskswitch (TSS). */
2261	X86_XCPT_TS = 0x0a,
2262	/** \#NP - Segment no present. */
2263	X86_XCPT_NP = 0x0b,
2264	/** \#SS - Stack segment fault. */
2265	X86_XCPT_SS = 0x0c,
2266	/** \#GP - General protection fault. */
2267	X86_XCPT_GP = 0x0d,
2268	/** \#PF - Page fault. */
2269	X86_XCPT_PF = 0x0e,
2270	/* 0x0f is reserved. */
2271	/** \#MF - Math fault (FPU). */
2272	X86_XCPT_MF = 0x10,
2273	/** \#AC - Alignment check. */
2274	X86_XCPT_AC = 0x11,
2275	/** \#MC - Machine check. */
2276	X86_XCPT_MC = 0x12,
2277	/** \#XF - SIMD Floating-Pointer Exception. */
2278	X86_XCPT_XF = 0x13
2279	} X86XCPT;
2280	/** Pointer to a x86 exception code. */
2281	typedef X86XCPT *PX86XCPT;
2282	/** Pointer to a const x86 exception code. */
2283	typedef const X86XCPT *PCX86XCPT;
2284
2285
2286	/** @name Trap Error Codes
2287	* @{
2288	*/
2289	/** External indicator. */
2290	#define X86_TRAP_ERR_EXTERNAL 1
2291	/** IDT indicator. */
2292	#define X86_TRAP_ERR_IDT 2
2293	/** Descriptor table indicator - If set LDT, if clear GDT. */
2294	#define X86_TRAP_ERR_TI 4
2295	/** Mask for getting the selector. */
2296	#define X86_TRAP_ERR_SEL_MASK 0xfff8
2297	/** Shift for getting the selector table index (C type index). */
2298	#define X86_TRAP_ERR_SEL_SHIFT 3
2299	/** @} */
2300
2301
2302	/** @name \#PF Trap Error Codes
2303	* @{
2304	*/
2305	/** Bit 0 - P - Not present (clear) or page level protection (set) fault. */
2306	#define X86_TRAP_PF_P RT_BIT(0)
2307	/** Bit 1 - R/W - Read (clear) or write (set) access. */
2308	#define X86_TRAP_PF_RW RT_BIT(1)
2309	/** Bit 2 - U/S - CPU executing in user mode (set) or supervisor mode (clear). */
2310	#define X86_TRAP_PF_US RT_BIT(2)
2311	/** Bit 3 - RSVD- Reserved bit violation (set), i.e. reserved bit was set to 1. */
2312	#define X86_TRAP_PF_RSVD RT_BIT(3)
2313	/** Bit 4 - I/D - Instruction fetch (set) / Data access (clear) - PAE + NXE. */
2314	#define X86_TRAP_PF_ID RT_BIT(4)
2315	/** @} */
2316
2317	#pragma pack(1)
2318	/**
2319	* 32-bit IDTR/GDTR.
2320	*/
2321	typedef struct X86XDTR32
2322	{
2323	/** Size of the descriptor table. */
2324	uint16_t cb;
2325	/** Address of the descriptor table. */
2326	uint32_t uAddr;
2327	} X86XDTR32, *PX86XDTR32;
2328	#pragma pack()
2329
2330	#pragma pack(1)
2331	/**
2332	* 64-bit IDTR/GDTR.
2333	*/
2334	typedef struct X86XDTR64
2335	{
2336	/** Size of the descriptor table. */
2337	uint16_t cb;
2338	/** Address of the descriptor table. */
2339	uint64_t uAddr;
2340	} X86XDTR64, *PX86XDTR64;
2341	#pragma pack()
2342
2343	/** @} */
2344
2345	#endif
2346

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source: vbox/trunk/include/VBox/x86.h@ 9965

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