x86.h@ 10518

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1	/** @file
2	* X86 (and AMD64) Structures and Definitions.
3	*/
4
5	/*
6	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
7	*
8	* This file is part of VirtualBox Open Source Edition (OSE), as
9	* available from http://www.virtualbox.org. This file is free software;
10	* you can redistribute it and/or modify it under the terms of the GNU
11	* General Public License (GPL) as published by the Free Software
12	* Foundation, in version 2 as it comes in the "COPYING" file of the
13	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15	*
16	* The contents of this file may alternatively be used under the terms
17	* of the Common Development and Distribution License Version 1.0
18	* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19	* VirtualBox OSE distribution, in which case the provisions of the
20	* CDDL are applicable instead of those of the GPL.
21	*
22	* You may elect to license modified versions of this file under the
23	* terms and conditions of either the GPL or the CDDL or both.
24	*
25	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
26	* Clara, CA 95054 USA or visit http://www.sun.com if you need
27	* additional information or have any questions.
28	*/
29
30	/*
31	* x86.mac is generated from this file using:
32	* sed -e '/__VBox_x86_h__/d' -e '/#define/!d' -e 's/#define/%define/' include/VBox/x86.h
33	*/
34
35	#ifndef ___VBox_x86_h
36	#define ___VBox_x86_h
37
38	#include <VBox/types.h>
39
40	/* Workaround for Solaris sys/regset.h defining CS, DS */
41	#if defined(RT_OS_SOLARIS)
42	# undef CS
43	# undef DS
44	#endif
45
46	/** @defgroup grp_x86 x86 Types and Definitions
47	* @{
48	*/
49
50	/**
51	* EFLAGS Bits.
52	*/
53	typedef struct X86EFLAGSBITS
54	{
55	/** Bit 0 - CF - Carry flag - Status flag. */
56	unsigned u1CF : 1;
57	/** Bit 1 - 1 - Reserved flag. */
58	unsigned u1Reserved0 : 1;
59	/** Bit 2 - PF - Parity flag - Status flag. */
60	unsigned u1PF : 1;
61	/** Bit 3 - 0 - Reserved flag. */
62	unsigned u1Reserved1 : 1;
63	/** Bit 4 - AF - Auxiliary carry flag - Status flag. */
64	unsigned u1AF : 1;
65	/** Bit 5 - 0 - Reserved flag. */
66	unsigned u1Reserved2 : 1;
67	/** Bit 6 - ZF - Zero flag - Status flag. */
68	unsigned u1ZF : 1;
69	/** Bit 7 - SF - Signed flag - Status flag. */
70	unsigned u1SF : 1;
71	/** Bit 8 - TF - Trap flag - System flag. */
72	unsigned u1TF : 1;
73	/** Bit 9 - IF - Interrupt flag - System flag. */
74	unsigned u1IF : 1;
75	/** Bit 10 - DF - Direction flag - Control flag. */
76	unsigned u1DF : 1;
77	/** Bit 11 - OF - Overflow flag - Status flag. */
78	unsigned u1OF : 1;
79	/** Bit 12-13 - IOPL - I/O prvilege level flag - System flag. */
80	unsigned u2IOPL : 2;
81	/** Bit 14 - NT - Nested task flag - System flag. */
82	unsigned u1NT : 1;
83	/** Bit 15 - 0 - Reserved flag. */
84	unsigned u1Reserved3 : 1;
85	/** Bit 16 - RF - Resume flag - System flag. */
86	unsigned u1RF : 1;
87	/** Bit 17 - VM - Virtual 8086 mode - System flag. */
88	unsigned u1VM : 1;
89	/** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
90	unsigned u1AC : 1;
91	/** Bit 19 - VIF - Virtual interupt flag - System flag. */
92	unsigned u1VIF : 1;
93	/** Bit 20 - VIP - Virtual interupt pending flag - System flag. */
94	unsigned u1VIP : 1;
95	/** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
96	unsigned u1ID : 1;
97	/** Bit 22-31 - 0 - Reserved flag. */
98	unsigned u10Reserved4 : 10;
99	} X86EFLAGSBITS;
100	/** Pointer to EFLAGS bits. */
101	typedef X86EFLAGSBITS *PX86EFLAGSBITS;
102	/** Pointer to const EFLAGS bits. */
103	typedef const X86EFLAGSBITS *PCX86EFLAGSBITS;
104
105	/**
106	* EFLAGS.
107	*/
108	typedef union X86EFLAGS
109	{
110	/** The bitfield view. */
111	X86EFLAGSBITS Bits;
112	/** The 8-bit view. */
113	uint8_t au8[4];
114	/** The 16-bit view. */
115	uint16_t au16[2];
116	/** The 32-bit view. */
117	uint32_t au32[1];
118	/** The 32-bit view. */
119	uint32_t u32;
120	/** The plain unsigned view. */
121	uint32_t u;
122	} X86EFLAGS;
123	/** Pointer to EFLAGS. */
124	typedef X86EFLAGS *PX86EFLAGS;
125	/** Pointer to const EFLAGS. */
126	typedef const X86EFLAGS *PCX86EFLAGS;
127
128	/**
129	* RFLAGS (32 upper bits are reserved).
130	*/
131	typedef union X86RFLAGS
132	{
133	/** The bitfield view. */
134	X86EFLAGSBITS Bits;
135	/** The 8-bit view. */
136	uint8_t au8[8];
137	/** The 16-bit view. */
138	uint16_t au16[4];
139	/** The 32-bit view. */
140	uint32_t au32[2];
141	/** The 64-bit view. */
142	uint64_t au64[1];
143	/** The 64-bit view. */
144	uint64_t u64;
145	/** The plain unsigned view. */
146	uint64_t u;
147	} X86RFLAGS;
148	/** Pointer to RFLAGS. */
149	typedef X86RFLAGS *PX86RFLAGS;
150	/** Pointer to const RFLAGS. */
151	typedef const X86RFLAGS *PCX86RFLAGS;
152
153
154	/** @name EFLAGS
155	* @{
156	*/
157	/** Bit 0 - CF - Carry flag - Status flag. */
158	#define X86_EFL_CF RT_BIT(0)
159	/** Bit 2 - PF - Parity flag - Status flag. */
160	#define X86_EFL_PF RT_BIT(2)
161	/** Bit 4 - AF - Auxiliary carry flag - Status flag. */
162	#define X86_EFL_AF RT_BIT(4)
163	/** Bit 6 - ZF - Zero flag - Status flag. */
164	#define X86_EFL_ZF RT_BIT(6)
165	/** Bit 7 - SF - Signed flag - Status flag. */
166	#define X86_EFL_SF RT_BIT(7)
167	/** Bit 8 - TF - Trap flag - System flag. */
168	#define X86_EFL_TF RT_BIT(8)
169	/** Bit 9 - IF - Interrupt flag - System flag. */
170	#define X86_EFL_IF RT_BIT(9)
171	/** Bit 10 - DF - Direction flag - Control flag. */
172	#define X86_EFL_DF RT_BIT(10)
173	/** Bit 11 - OF - Overflow flag - Status flag. */
174	#define X86_EFL_OF RT_BIT(11)
175	/** Bit 12-13 - IOPL - I/O prvilege level flag - System flag. */
176	#define X86_EFL_IOPL (RT_BIT(12) \| RT_BIT(13))
177	/** Bit 14 - NT - Nested task flag - System flag. */
178	#define X86_EFL_NT RT_BIT(14)
179	/** Bit 16 - RF - Resume flag - System flag. */
180	#define X86_EFL_RF RT_BIT(16)
181	/** Bit 17 - VM - Virtual 8086 mode - System flag. */
182	#define X86_EFL_VM RT_BIT(17)
183	/** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
184	#define X86_EFL_AC RT_BIT(18)
185	/** Bit 19 - VIF - Virtual interupt flag - System flag. */
186	#define X86_EFL_VIF RT_BIT(19)
187	/** Bit 20 - VIP - Virtual interupt pending flag - System flag. */
188	#define X86_EFL_VIP RT_BIT(20)
189	/** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
190	#define X86_EFL_ID RT_BIT(21)
191	/** IOPL shift. */
192	#define X86_EFL_IOPL_SHIFT 12
193	/** The the IOPL level from the flags. */
194	#define X86_EFL_GET_IOPL(efl) (((efl) >> X86_EFL_IOPL_SHIFT) & 3)
195	/** @} */
196
197
198	/** CPUID Feature information - ECX.
199	* CPUID query with EAX=1.
200	*/
201	typedef struct X86CPUIDFEATECX
202	{
203	/** Bit 0 - SSE3 - Supports SSE3 or not. */
204	unsigned u1SSE3 : 1;
205	/** Reserved. */
206	unsigned u2Reserved1 : 2;
207	/** Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
208	unsigned u1Monitor : 1;
209	/** Bit 4 - CPL-DS - CPL Qualified Debug Store. */
210	unsigned u1CPLDS : 1;
211	/** Bit 5 - VMX - Virtual Machine Technology. */
212	unsigned u1VMX : 1;
213	/** Reserved. */
214	unsigned u1Reserved2 : 1;
215	/** Bit 7 - EST - Enh. SpeedStep Tech. */
216	unsigned u1EST : 1;
217	/** Bit 8 - TM2 - Terminal Monitor 2. */
218	unsigned u1TM2 : 1;
219	/** Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
220	unsigned u1SSSE3 : 1;
221	/** Bit 10 - CNTX-ID - L1 Context ID. */
222	unsigned u1CNTXID : 1;
223	/** Reserved. */
224	unsigned u2Reserved4 : 2;
225	/** Bit 13 - CX16 - CMPXCHG16B. */
226	unsigned u1CX16 : 1;
227	/** Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
228	unsigned u1TPRUpdate : 1;
229	/** Reserved. */
230	unsigned u17Reserved5 : 17;
231
232	} X86CPUIDFEATECX;
233	/** Pointer to CPUID Feature Information - ECX. */
234	typedef X86CPUIDFEATECX *PX86CPUIDFEATECX;
235	/** Pointer to const CPUID Feature Information - ECX. */
236	typedef const X86CPUIDFEATECX *PCX86CPUIDFEATECX;
237
238
239	/** CPUID Feature Information - EDX.
240	* CPUID query with EAX=1.
241	*/
242	typedef struct X86CPUIDFEATEDX
243	{
244	/** Bit 0 - FPU - x87 FPU on Chip. */
245	unsigned u1FPU : 1;
246	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
247	unsigned u1VME : 1;
248	/** Bit 2 - DE - Debugging extensions. */
249	unsigned u1DE : 1;
250	/** Bit 3 - PSE - Page Size Extension. */
251	unsigned u1PSE : 1;
252	/** Bit 4 - TSC - Time Stamp Counter. */
253	unsigned u1TSC : 1;
254	/** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
255	unsigned u1MSR : 1;
256	/** Bit 6 - PAE - Physical Address Extension. */
257	unsigned u1PAE : 1;
258	/** Bit 7 - MCE - Machine Check Exception. */
259	unsigned u1MCE : 1;
260	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
261	unsigned u1CX8 : 1;
262	/** Bit 9 - APIC - APIC On-Chip. */
263	unsigned u1APIC : 1;
264	/** Bit 10 - Reserved. */
265	unsigned u1Reserved1 : 1;
266	/** Bit 11 - SEP - SYSENTER and SYSEXIT. */
267	unsigned u1SEP : 1;
268	/** Bit 12 - MTRR - Memory Type Range Registers. */
269	unsigned u1MTRR : 1;
270	/** Bit 13 - PGE - PTE Global Bit. */
271	unsigned u1PGE : 1;
272	/** Bit 14 - MCA - Machine Check Architecture. */
273	unsigned u1MCA : 1;
274	/** Bit 15 - CMOV - Conditional Move Instructions. */
275	unsigned u1CMOV : 1;
276	/** Bit 16 - PAT - Page Attribute Table. */
277	unsigned u1PAT : 1;
278	/** Bit 17 - PSE-36 - 36-bit Page Size Extention. */
279	unsigned u1PSE36 : 1;
280	/** Bit 18 - PSN - Processor Serial Number. */
281	unsigned u1PSN : 1;
282	/** Bit 19 - CLFSH - CLFLUSH Instruction. */
283	unsigned u1CLFSH : 1;
284	/** Bit 20 - Reserved. */
285	unsigned u1Reserved2 : 1;
286	/** Bit 21 - DS - Debug Store. */
287	unsigned u1DS : 1;
288	/** Bit 22 - ACPI - Thermal Monitor and Software Controlled Clock Facilities. */
289	unsigned u1ACPI : 1;
290	/** Bit 23 - MMX - Intel MMX 'Technology'. */
291	unsigned u1MMX : 1;
292	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
293	unsigned u1FXSR : 1;
294	/** Bit 25 - SSE - SSE Support. */
295	unsigned u1SSE : 1;
296	/** Bit 26 - SSE2 - SSE2 Support. */
297	unsigned u1SSE2 : 1;
298	/** Bit 27 - SS - Self Snoop. */
299	unsigned u1SS : 1;
300	/** Bit 28 - HTT - Hyper-Threading Technology. */
301	unsigned u1HTT : 1;
302	/** Bit 29 - TM - Thermal Monitor. */
303	unsigned u1TM : 1;
304	/** Bit 30 - Reserved - . */
305	unsigned u1Reserved3 : 1;
306	/** Bit 31 - PBE - Pending Break Enabled. */
307	unsigned u1PBE : 1;
308	} X86CPUIDFEATEDX;
309	/** Pointer to CPUID Feature Information - EDX. */
310	typedef X86CPUIDFEATEDX *PX86CPUIDFEATEDX;
311	/** Pointer to const CPUID Feature Information - EDX. */
312	typedef const X86CPUIDFEATEDX *PCX86CPUIDFEATEDX;
313
314	/** @name CPUID Vendor information.
315	* CPUID query with EAX=0.
316	* @{
317	*/
318	#define X86_CPUID_VENDOR_INTEL_EBX 0x756e6547 /* Genu */
319	#define X86_CPUID_VENDOR_INTEL_ECX 0x6c65746e /* ntel */
320	#define X86_CPUID_VENDOR_INTEL_EDX 0x49656e69 /* ineI */
321
322	#define X86_CPUID_VENDOR_AMD_EBX 0x68747541 /* Auth */
323	#define X86_CPUID_VENDOR_AMD_ECX 0x444d4163 /* cAMD */
324	#define X86_CPUID_VENDOR_AMD_EDX 0x69746e65 /* enti */
325	/** @} */
326
327
328	/** @name CPUID Feature information.
329	* CPUID query with EAX=1.
330	* @{
331	*/
332	/** ECX Bit 0 - SSE3 - Supports SSE3 or not. */
333	#define X86_CPUID_FEATURE_ECX_SSE3 RT_BIT(0)
334	/** ECX Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
335	#define X86_CPUID_FEATURE_ECX_MONITOR RT_BIT(3)
336	/** ECX Bit 4 - CPL-DS - CPL Qualified Debug Store. */
337	#define X86_CPUID_FEATURE_ECX_CPLDS RT_BIT(4)
338	/** ECX Bit 5 - VMX - Virtual Machine Technology. */
339	#define X86_CPUID_FEATURE_ECX_VMX RT_BIT(5)
340	/** ECX Bit 7 - EST - Enh. SpeedStep Tech. */
341	#define X86_CPUID_FEATURE_ECX_EST RT_BIT(7)
342	/** ECX Bit 8 - TM2 - Terminal Monitor 2. */
343	#define X86_CPUID_FEATURE_ECX_TM2 RT_BIT(8)
344	/** ECX Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
345	#define X86_CPUID_FEATURE_ECX_SSSE3 RT_BIT(9)
346	/** ECX Bit 10 - CNTX-ID - L1 Context ID. */
347	#define X86_CPUID_FEATURE_ECX_CNTXID RT_BIT(10)
348	/** ECX Bit 13 - CX16 - CMPXCHG16B. */
349	#define X86_CPUID_FEATURE_ECX_CX16 RT_BIT(13)
350	/** ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
351	#define X86_CPUID_FEATURE_ECX_TPRUPDATE RT_BIT(14)
352	/** ECX Bit 23 - POPCOUNT instruction. */
353	#define X86_CPUID_FEATURE_ECX_POPCOUNT RT_BIT(23)
354
355
356	/** Bit 0 - FPU - x87 FPU on Chip. */
357	#define X86_CPUID_FEATURE_EDX_FPU RT_BIT(0)
358	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
359	#define X86_CPUID_FEATURE_EDX_VME RT_BIT(1)
360	/** Bit 2 - DE - Debugging extensions. */
361	#define X86_CPUID_FEATURE_EDX_DE RT_BIT(2)
362	/** Bit 3 - PSE - Page Size Extension. */
363	#define X86_CPUID_FEATURE_EDX_PSE RT_BIT(3)
364	/** Bit 4 - TSC - Time Stamp Counter. */
365	#define X86_CPUID_FEATURE_EDX_TSC RT_BIT(4)
366	/** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
367	#define X86_CPUID_FEATURE_EDX_MSR RT_BIT(5)
368	/** Bit 6 - PAE - Physical Address Extension. */
369	#define X86_CPUID_FEATURE_EDX_PAE RT_BIT(6)
370	/** Bit 7 - MCE - Machine Check Exception. */
371	#define X86_CPUID_FEATURE_EDX_MCE RT_BIT(7)
372	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
373	#define X86_CPUID_FEATURE_EDX_CX8 RT_BIT(8)
374	/** Bit 9 - APIC - APIC On-Chip. */
375	#define X86_CPUID_FEATURE_EDX_APIC RT_BIT(9)
376	/** Bit 11 - SEP - SYSENTER and SYSEXIT. */
377	#define X86_CPUID_FEATURE_EDX_SEP RT_BIT(11)
378	/** Bit 12 - MTRR - Memory Type Range Registers. */
379	#define X86_CPUID_FEATURE_EDX_MTRR RT_BIT(12)
380	/** Bit 13 - PGE - PTE Global Bit. */
381	#define X86_CPUID_FEATURE_EDX_PGE RT_BIT(13)
382	/** Bit 14 - MCA - Machine Check Architecture. */
383	#define X86_CPUID_FEATURE_EDX_MCA RT_BIT(14)
384	/** Bit 15 - CMOV - Conditional Move Instructions. */
385	#define X86_CPUID_FEATURE_EDX_CMOV RT_BIT(15)
386	/** Bit 16 - PAT - Page Attribute Table. */
387	#define X86_CPUID_FEATURE_EDX_PAT RT_BIT(16)
388	/** Bit 17 - PSE-36 - 36-bit Page Size Extention. */
389	#define X86_CPUID_FEATURE_EDX_PSE36 RT_BIT(17)
390	/** Bit 18 - PSN - Processor Serial Number. */
391	#define X86_CPUID_FEATURE_EDX_PSN RT_BIT(18)
392	/** Bit 19 - CLFSH - CLFLUSH Instruction. */
393	#define X86_CPUID_FEATURE_EDX_CLFSH RT_BIT(19)
394	/** Bit 21 - DS - Debug Store. */
395	#define X86_CPUID_FEATURE_EDX_DS RT_BIT(21)
396	/** Bit 22 - ACPI - Termal Monitor and Software Controlled Clock Facilities. */
397	#define X86_CPUID_FEATURE_EDX_ACPI RT_BIT(22)
398	/** Bit 23 - MMX - Intel MMX Technology. */
399	#define X86_CPUID_FEATURE_EDX_MMX RT_BIT(23)
400	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
401	#define X86_CPUID_FEATURE_EDX_FXSR RT_BIT(24)
402	/** Bit 25 - SSE - SSE Support. */
403	#define X86_CPUID_FEATURE_EDX_SSE RT_BIT(25)
404	/** Bit 26 - SSE2 - SSE2 Support. */
405	#define X86_CPUID_FEATURE_EDX_SSE2 RT_BIT(26)
406	/** Bit 27 - SS - Self Snoop. */
407	#define X86_CPUID_FEATURE_EDX_SS RT_BIT(27)
408	/** Bit 28 - HTT - Hyper-Threading Technology. */
409	#define X86_CPUID_FEATURE_EDX_HTT RT_BIT(28)
410	/** Bit 29 - TM - Therm. Monitor. */
411	#define X86_CPUID_FEATURE_EDX_TM RT_BIT(29)
412	/** Bit 31 - PBE - Pending Break Enabled. */
413	#define X86_CPUID_FEATURE_EDX_PBE RT_BIT(31)
414	/** @} */
415
416
417	/** @name CPUID AMD Feature information.
418	* CPUID query with EAX=0x80000001.
419	* @{
420	*/
421	/** Bit 0 - FPU - x87 FPU on Chip. */
422	#define X86_CPUID_AMD_FEATURE_EDX_FPU RT_BIT(0)
423	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
424	#define X86_CPUID_AMD_FEATURE_EDX_VME RT_BIT(1)
425	/** Bit 2 - DE - Debugging extensions. */
426	#define X86_CPUID_AMD_FEATURE_EDX_DE RT_BIT(2)
427	/** Bit 3 - PSE - Page Size Extension. */
428	#define X86_CPUID_AMD_FEATURE_EDX_PSE RT_BIT(3)
429	/** Bit 4 - TSC - Time Stamp Counter. */
430	#define X86_CPUID_AMD_FEATURE_EDX_TSC RT_BIT(4)
431	/** Bit 5 - MSR - K86 Model Specific Registers RDMSR and WRMSR Instructions. */
432	#define X86_CPUID_AMD_FEATURE_EDX_MSR RT_BIT(5)
433	/** Bit 6 - PAE - Physical Address Extension. */
434	#define X86_CPUID_AMD_FEATURE_EDX_PAE RT_BIT(6)
435	/** Bit 7 - MCE - Machine Check Exception. */
436	#define X86_CPUID_AMD_FEATURE_EDX_MCE RT_BIT(7)
437	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
438	#define X86_CPUID_AMD_FEATURE_EDX_CX8 RT_BIT(8)
439	/** Bit 9 - APIC - APIC On-Chip. */
440	#define X86_CPUID_AMD_FEATURE_EDX_APIC RT_BIT(9)
441	/** Bit 11 - SEP - AMD SYSCALL and SYSRET. */
442	#define X86_CPUID_AMD_FEATURE_EDX_SEP RT_BIT(11)
443	/** Bit 12 - MTRR - Memory Type Range Registers. */
444	#define X86_CPUID_AMD_FEATURE_EDX_MTRR RT_BIT(12)
445	/** Bit 13 - PGE - PTE Global Bit. */
446	#define X86_CPUID_AMD_FEATURE_EDX_PGE RT_BIT(13)
447	/** Bit 14 - MCA - Machine Check Architecture. */
448	#define X86_CPUID_AMD_FEATURE_EDX_MCA RT_BIT(14)
449	/** Bit 15 - CMOV - Conditional Move Instructions. */
450	#define X86_CPUID_AMD_FEATURE_EDX_CMOV RT_BIT(15)
451	/** Bit 16 - PAT - Page Attribute Table. */
452	#define X86_CPUID_AMD_FEATURE_EDX_PAT RT_BIT(16)
453	/** Bit 17 - PSE-36 - 36-bit Page Size Extention. */
454	#define X86_CPUID_AMD_FEATURE_EDX_PSE36 RT_BIT(17)
455	/** Bit 20 - NX - AMD No-Execute Page Protection. */
456	#define X86_CPUID_AMD_FEATURE_EDX_NX RT_BIT(20)
457	/** Bit 22 - AXMMX - AMD Extensions to MMX Instructions. */
458	#define X86_CPUID_AMD_FEATURE_EDX_AXMMX RT_BIT(22)
459	/** Bit 23 - MMX - Intel MMX Technology. */
460	#define X86_CPUID_AMD_FEATURE_EDX_MMX RT_BIT(23)
461	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
462	#define X86_CPUID_AMD_FEATURE_EDX_FXSR RT_BIT(24)
463	/** Bit 25 - FFXSR - AMD fast FXSAVE and FXRSTOR Instructions. */
464	#define X86_CPUID_AMD_FEATURE_EDX_FFXSR RT_BIT(25)
465	/** Bit 26 - PAGE1GB - AMD 1GB large page support. */
466	#define X86_CPUID_AMD_FEATURE_EDX_PAGE1GB RT_BIT(26)
467	/** Bit 27 - RDTSCP - AMD RDTSCP instruction. */
468	#define X86_CPUID_AMD_FEATURE_EDX_RDTSCP RT_BIT(27)
469	/** Bit 29 - LM - AMD Long Mode. */
470	#define X86_CPUID_AMD_FEATURE_EDX_LONG_MODE RT_BIT(29)
471	/** Bit 30 - 3DNOWEXT - AMD Extensions to 3DNow. */
472	#define X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX RT_BIT(30)
473	/** Bit 31 - 3DNOW - AMD 3DNow. */
474	#define X86_CPUID_AMD_FEATURE_EDX_3DNOW RT_BIT(31)
475
476	/** Bit 0 - LAHF/SAHF - AMD LAHF and SAHF in 64-bit mode. */
477	#define X86_CPUID_AMD_FEATURE_ECX_LAHF_SAHF RT_BIT(0)
478	/** Bit 1 - CMPL - Core multi-processing legacy mode. */
479	#define X86_CPUID_AMD_FEATURE_ECX_CMPL RT_BIT(1)
480	/** Bit 2 - SVM - AMD VM extensions. */
481	#define X86_CPUID_AMD_FEATURE_ECX_SVM RT_BIT(2)
482	/** Bit 3 - EXTAPIC - AMD extended APIC registers starting at 0x400. */
483	#define X86_CPUID_AMD_FEATURE_ECX_EXT_APIC RT_BIT(3)
484	/** Bit 4 - CR8L - AMD LOCK MOV CR0 means MOV CR8. */
485	#define X86_CPUID_AMD_FEATURE_ECX_CR8L RT_BIT(4)
486	/** Bit 5 - ABM - AMD Advanced bit manipulation. LZCNT instruction support. */
487	#define X86_CPUID_AMD_FEATURE_ECX_ABM RT_BIT(5)
488	/** Bit 6 - SSE4A - AMD EXTRQ, INSERTQ, MOVNTSS, and MOVNTSD instruction support. */
489	#define X86_CPUID_AMD_FEATURE_ECX_SSE4A RT_BIT(6)
490	/** Bit 7 - MISALIGNSSE - AMD Misaligned SSE mode. */
491	#define X86_CPUID_AMD_FEATURE_ECX_MISALNSSE RT_BIT(7)
492	/** Bit 8 - 3DNOWPRF - AMD PREFETCH and PREFETCHW instruction support. */
493	#define X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF RT_BIT(8)
494	/** Bit 9 - OSVW - AMD OS visible workaround. */
495	#define X86_CPUID_AMD_FEATURE_ECX_OSVW RT_BIT(9)
496	/** Bit 12 - SKINIT - AMD SKINIT: SKINIT, STGI, and DEV support. */
497	#define X86_CPUID_AMD_FEATURE_ECX_SKINIT RT_BIT(12)
498	/** Bit 13 - WDT - AMD Watchdog timer support. */
499	#define X86_CPUID_AMD_FEATURE_ECX_WDT RT_BIT(13)
500
501	/** @} */
502
503
504	/** @name CR0
505	* @{ */
506	/** Bit 0 - PE - Protection Enabled */
507	#define X86_CR0_PE RT_BIT(0)
508	#define X86_CR0_PROTECTION_ENABLE RT_BIT(0)
509	/** Bit 1 - MP - Monitor Coprocessor */
510	#define X86_CR0_MP RT_BIT(1)
511	#define X86_CR0_MONITOR_COPROCESSOR RT_BIT(1)
512	/** Bit 2 - EM - Emulation. */
513	#define X86_CR0_EM RT_BIT(2)
514	#define X86_CR0_EMULATE_FPU RT_BIT(2)
515	/** Bit 3 - TS - Task Switch. */
516	#define X86_CR0_TS RT_BIT(3)
517	#define X86_CR0_TASK_SWITCH RT_BIT(3)
518	/** Bit 4 - ET - Extension flag. ('hardcoded' to 1) */
519	#define X86_CR0_ET RT_BIT(4)
520	#define X86_CR0_EXTENSION_TYPE RT_BIT(4)
521	/** Bit 5 - NE - Numeric error. */
522	#define X86_CR0_NE RT_BIT(5)
523	#define X86_CR0_NUMERIC_ERROR RT_BIT(5)
524	/** Bit 16 - WP - Write Protect. */
525	#define X86_CR0_WP RT_BIT(16)
526	#define X86_CR0_WRITE_PROTECT RT_BIT(16)
527	/** Bit 18 - AM - Alignment Mask. */
528	#define X86_CR0_AM RT_BIT(18)
529	#define X86_CR0_ALIGMENT_MASK RT_BIT(18)
530	/** Bit 29 - NW - Not Write-though. */
531	#define X86_CR0_NW RT_BIT(29)
532	#define X86_CR0_NOT_WRITE_THROUGH RT_BIT(29)
533	/** Bit 30 - WP - Cache Disable. */
534	#define X86_CR0_CD RT_BIT(30)
535	#define X86_CR0_CACHE_DISABLE RT_BIT(30)
536	/** Bit 31 - PG - Paging. */
537	#define X86_CR0_PG RT_BIT(31)
538	#define X86_CR0_PAGING RT_BIT(31)
539	/** @} */
540
541
542	/** @name CR3
543	* @{ */
544	/** Bit 3 - PWT - Page-level Writes Transparent. */
545	#define X86_CR3_PWT RT_BIT(3)
546	/** Bit 4 - PCD - Page-level Cache Disable. */
547	#define X86_CR3_PCD RT_BIT(4)
548	/** Bits 12-31 - - Page directory page number. */
549	#define X86_CR3_PAGE_MASK (0xfffff000)
550	/** Bits 5-31 - - PAE Page directory page number. */
551	#define X86_CR3_PAE_PAGE_MASK (0xffffffe0)
552	/** Bits 12-51 - - AMD64 Page directory page number. */
553	#define X86_CR3_AMD64_PAGE_MASK UINT64_C(0x000ffffffffff000)
554	/** @} */
555
556
557	/** @name CR4
558	* @{ */
559	/** Bit 0 - VME - Virtual-8086 Mode Extensions. */
560	#define X86_CR4_VME RT_BIT(0)
561	/** Bit 1 - PVI - Protected-Mode Virtual Interrupts. */
562	#define X86_CR4_PVI RT_BIT(1)
563	/** Bit 2 - TSD - Time Stamp Disable. */
564	#define X86_CR4_TSD RT_BIT(2)
565	/** Bit 3 - DE - Debugging Extensions. */
566	#define X86_CR4_DE RT_BIT(3)
567	/** Bit 4 - PSE - Page Size Extension. */
568	#define X86_CR4_PSE RT_BIT(4)
569	/** Bit 5 - PAE - Physical Address Extension. */
570	#define X86_CR4_PAE RT_BIT(5)
571	/** Bit 6 - MCE - Machine-Check Enable. */
572	#define X86_CR4_MCE RT_BIT(6)
573	/** Bit 7 - PGE - Page Global Enable. */
574	#define X86_CR4_PGE RT_BIT(7)
575	/** Bit 8 - PCE - Performance-Monitoring Counter Enable. */
576	#define X86_CR4_PCE RT_BIT(8)
577	/** Bit 9 - OSFSXR - Operating System Support for FXSAVE and FXRSTORE instruction. */
578	#define X86_CR4_OSFSXR RT_BIT(9)
579	/** Bit 10 - OSXMMEEXCPT - Operating System Support for Unmasked SIMD Floating-Point Exceptions. */
580	#define X86_CR4_OSXMMEEXCPT RT_BIT(10)
581	/** Bit 13 - VMXE - VMX mode is enabled. */
582	#define X86_CR4_VMXE RT_BIT(13)
583	/** @} */
584
585
586	/** @name DR6
587	* @{ */
588	/** Bit 0 - B0 - Breakpoint 0 condition detected. */
589	#define X86_DR6_B0 RT_BIT(0)
590	/** Bit 1 - B1 - Breakpoint 1 condition detected. */
591	#define X86_DR6_B1 RT_BIT(1)
592	/** Bit 2 - B2 - Breakpoint 2 condition detected. */
593	#define X86_DR6_B2 RT_BIT(2)
594	/** Bit 3 - B3 - Breakpoint 3 condition detected. */
595	#define X86_DR6_B3 RT_BIT(3)
596	/** Bit 13 - BD - Debug register access detected. Corresponds to the X86_DR7_GD bit. */
597	#define X86_DR6_BD RT_BIT(13)
598	/** Bit 14 - BS - Single step */
599	#define X86_DR6_BS RT_BIT(14)
600	/** Bit 15 - BT - Task switch. (TSS T bit.) */
601	#define X86_DR6_BT RT_BIT(15)
602	/** @} */
603
604
605	/** @name DR7
606	* @{ */
607	/** Bit 0 - L0 - Local breakpoint enable. Cleared on task switch. */
608	#define X86_DR7_L0 RT_BIT(0)
609	/** Bit 1 - G0 - Global breakpoint enable. Not cleared on task switch. */
610	#define X86_DR7_G0 RT_BIT(1)
611	/** Bit 2 - L1 - Local breakpoint enable. Cleared on task switch. */
612	#define X86_DR7_L1 RT_BIT(2)
613	/** Bit 3 - G1 - Global breakpoint enable. Not cleared on task switch. */
614	#define X86_DR7_G1 RT_BIT(3)
615	/** Bit 4 - L2 - Local breakpoint enable. Cleared on task switch. */
616	#define X86_DR7_L2 RT_BIT(4)
617	/** Bit 5 - G2 - Global breakpoint enable. Not cleared on task switch. */
618	#define X86_DR7_G2 RT_BIT(5)
619	/** Bit 6 - L3 - Local breakpoint enable. Cleared on task switch. */
620	#define X86_DR7_L3 RT_BIT(6)
621	/** Bit 7 - G3 - Global breakpoint enable. Not cleared on task switch. */
622	#define X86_DR7_G3 RT_BIT(7)
623	/** Bit 8 - LE - Local breakpoint exact. (Not supported (read ignored) by P6 and later.) */
624	#define X86_DR7_LE RT_BIT(8)
625	/** Bit 9 - GE - Local breakpoint exact. (Not supported (read ignored) by P6 and later.) */
626	#define X86_DR7_GE RT_BIT(9)
627
628	/** Bit 13 - GD - General detect enable. Enables emulators to get exceptions when
629	* any DR register is accessed. */
630	#define X86_DR7_GD RT_BIT(13)
631	/** Bit 16 & 17 - R/W0 - Read write field 0. Values X86_DR7_RW_. /
632	#define X86_DR7_RW0_MASK (3 << 16)
633	/** Bit 18 & 19 - LEN0 - Length field 0. Values X86_DR7_LEN_. /
634	#define X86_DR7_LEN0_MASK (3 << 18)
635	/** Bit 20 & 21 - R/W1 - Read write field 0. Values X86_DR7_RW_. /
636	#define X86_DR7_RW1_MASK (3 << 20)
637	/** Bit 22 & 23 - LEN1 - Length field 0. Values X86_DR7_LEN_. /
638	#define X86_DR7_LEN1_MASK (3 << 22)
639	/** Bit 24 & 25 - R/W2 - Read write field 0. Values X86_DR7_RW_. /
640	#define X86_DR7_RW2_MASK (3 << 24)
641	/** Bit 26 & 27 - LEN2 - Length field 0. Values X86_DR7_LEN_. /
642	#define X86_DR7_LEN2_MASK (3 << 26)
643	/** Bit 28 & 29 - R/W3 - Read write field 0. Values X86_DR7_RW_. /
644	#define X86_DR7_RW3_MASK (3 << 28)
645	/** Bit 30 & 31 - LEN3 - Length field 0. Values X86_DR7_LEN_. /
646	#define X86_DR7_LEN3_MASK (3 << 30)
647
648	/** Bits which must be 1s. */
649	#define X86_DR7_MB1_MASK (RT_BIT(10))
650
651	/** Calcs the L bit of Nth breakpoint.
652	* @param iBp The breakpoint number [0..3].
653	*/
654	#define X86_DR7_L(iBp) ( 1 << (iBp * 2) )
655
656	/** Calcs the G bit of Nth breakpoint.
657	* @param iBp The breakpoint number [0..3].
658	*/
659	#define X86_DR7_G(iBp) ( 1 << (iBp * 2 + 1) )
660
661	/** @name Read/Write values.
662	* @{ */
663	/** Break on instruction fetch only. */
664	#define X86_DR7_RW_EO 0
665	/** Break on write only. */
666	#define X86_DR7_RW_WO 1
667	/** Break on I/O read/write. This is only defined if CR4.DE is set. */
668	#define X86_DR7_RW_IO 2
669	/** Break on read or write (but not instruction fetches). */
670	#define X86_DR7_RW_RW 3
671	/** @} */
672
673	/** Shifts a X86_DR7_RW_* value to its right place.
674	* @param iBp The breakpoint number [0..3].
675	* @param fRw One of the X86_DR7_RW_* value.
676	*/
677	#define X86_DR7_RW(iBp, fRw) ( (fRw) << ((iBp) * 4 + 16) )
678
679	/** @name Length values.
680	* @{ */
681	#define X86_DR7_LEN_BYTE 0
682	#define X86_DR7_LEN_WORD 1
683	#define X86_DR7_LEN_QWORD 2 /*< AMD64 long mode only. /
684	#define X86_DR7_LEN_DWORD 3
685	/** @} */
686
687	/** Shifts a X86_DR7_LEN_* value to its right place.
688	* @param iBp The breakpoint number [0..3].
689	* @param cb One of the X86_DR7_LEN_* values.
690	*/
691	#define X86_DR7_LEN(iBp, cb) ( (cb) << ((iBp) * 4 + 18) )
692
693	/** Mask used to check if any breakpoints are enabled. */
694	#define X86_DR7_ENABLED_MASK (RT_BIT(0) \| RT_BIT(1) \| RT_BIT(2) \| RT_BIT(3) \| RT_BIT(4) \| RT_BIT(6) \| RT_BIT(7))
695
696	/** @} */
697
698
699	/** @name Machine Specific Registers
700	* @{
701	*/
702
703	/** Time Stamp Counter. */
704	#define MSR_IA32_TSC 0x10
705
706	#ifndef MSR_IA32_APICBASE /* qemu cpu.h klugde */
707	#define MSR_IA32_APICBASE 0x1b
708	#endif
709
710	/** CPU Feature control. */
711	#define MSR_IA32_FEATURE_CONTROL 0x3A
712	#define MSR_IA32_FEATURE_CONTROL_LOCK RT_BIT(0)
713	#define MSR_IA32_FEATURE_CONTROL_VMXON RT_BIT(2)
714
715	/** MTRR Capabilities. */
716	#define MSR_IA32_MTRR_CAP 0xFE
717
718
719	#ifndef MSR_IA32_SYSENTER_CS /* qemu cpu.h klugde */
720	/** SYSENTER_CS - the R0 CS, indirectly giving R0 SS, R3 CS and R3 DS.
721	* R0 SS == CS + 8
722	* R3 CS == CS + 16
723	* R3 SS == CS + 24
724	*/
725	#define MSR_IA32_SYSENTER_CS 0x174
726	/** SYSENTER_ESP - the R0 ESP. */
727	#define MSR_IA32_SYSENTER_ESP 0x175
728	/** SYSENTER_EIP - the R0 EIP. */
729	#define MSR_IA32_SYSENTER_EIP 0x176
730	#endif
731
732	/** Machine Check Global Capabilities Register. */
733	#define MSR_IA32_MCP_CAP 0x179
734	/** Machine Check Global Status Register. */
735	#define MSR_IA32_MCP_STATUS 0x17A
736	/** Machine Check Global Control Register. */
737	#define MSR_IA32_MCP_CTRL 0x17B
738
739	/* Page Attribute Table. */
740	#define MSR_IA32_CR_PAT 0x277
741
742	/** MTRR Default Range. */
743	#define MSR_IA32_MTRR_DEF_TYPE 0x2FF
744
745	/** Basic VMX information. */
746	#define MSR_IA32_VMX_BASIC_INFO 0x480
747	/** Allowed settings for pin-based VM execution controls */
748	#define MSR_IA32_VMX_PINBASED_CTLS 0x481
749	/** Allowed settings for proc-based VM execution controls */
750	#define MSR_IA32_VMX_PROCBASED_CTLS 0x482
751	/** Allowed settings for the VMX exit controls. */
752	#define MSR_IA32_VMX_EXIT_CTLS 0x483
753	/** Allowed settings for the VMX entry controls. */
754	#define MSR_IA32_VMX_ENTRY_CTLS 0x484
755	/** Misc VMX info. */
756	#define MSR_IA32_VMX_MISC 0x485
757	/** Fixed cleared bits in CR0. */
758	#define MSR_IA32_VMX_CR0_FIXED0 0x486
759	/** Fixed set bits in CR0. */
760	#define MSR_IA32_VMX_CR0_FIXED1 0x487
761	/** Fixed cleared bits in CR4. */
762	#define MSR_IA32_VMX_CR4_FIXED0 0x488
763	/** Fixed set bits in CR4. */
764	#define MSR_IA32_VMX_CR4_FIXED1 0x489
765	/** Information for enumerating fields in the VMCS. */
766	#define MSR_IA32_VMX_VMCS_ENUM 0x48A
767
768
769	/** K6 EFER - Extended Feature Enable Register. */
770	#define MSR_K6_EFER 0xc0000080
771	/** @todo document EFER */
772	/** Bit 0 - SCE - System call extensions (SYSCALL / SYSRET). (R/W) */
773	#define MSR_K6_EFER_SCE RT_BIT(0)
774	/** Bit 8 - LME - Long mode enabled. (R/W) */
775	#define MSR_K6_EFER_LME RT_BIT(8)
776	/** Bit 10 - LMA - Long mode active. (R) */
777	#define MSR_K6_EFER_LMA RT_BIT(10)
778	/** Bit 11 - NXE - No-Execute Page Protection Enabled. (R/W) */
779	#define MSR_K6_EFER_NXE RT_BIT(11)
780	/** Bit 12 - SVME - Secure VM Extension Enabled. (R/W) */
781	#define MSR_K6_EFER_SVME RT_BIT(12)
782	/** Bit 13 - LMSLE - Long Mode Segment Limit Enable. (R/W?) */
783	#define MSR_K6_EFER_LMSLE RT_BIT(13)
784	/** Bit 14 - FFXSR - Fast FXSAVE / FXRSTOR (skip XMM). (R/W) /
785	#define MSR_K6_EFER_FFXSR RT_BIT(14)
786	/** K6 STAR - SYSCALL/RET targets. */
787	#define MSR_K6_STAR 0xc0000081
788	/** Shift value for getting the SYSRET CS and SS value. */
789	#define MSR_K6_STAR_SYSRET_CS_SS_SHIFT 48
790	/** Shift value for getting the SYSCALL CS and SS value. */
791	#define MSR_K6_STAR_SYSCALL_CS_SS_SHIFT 32
792	/** Selector mask for use after shifting. */
793	#define MSR_K6_STAR_SEL_MASK 0xffff
794	/** The mask which give the SYSCALL EIP. */
795	#define MSR_K6_STAR_SYSCALL_EIP_MASK 0xffffffff
796	/** K6 WHCR - Write Handling Control Register. */
797	#define MSR_K6_WHCR 0xc0000082
798	/** K6 UWCCR - UC/WC Cacheability Control Register. */
799	#define MSR_K6_UWCCR 0xc0000085
800	/** K6 PSOR - Processor State Observability Register. */
801	#define MSR_K6_PSOR 0xc0000087
802	/** K6 PFIR - Page Flush/Invalidate Register. */
803	#define MSR_K6_PFIR 0xc0000088
804
805	#define MSR_K7_EVNTSEL0 0xc0010000
806	#define MSR_K7_EVNTSEL1 0xc0010001
807	#define MSR_K7_EVNTSEL2 0xc0010002
808	#define MSR_K7_EVNTSEL3 0xc0010003
809	#define MSR_K7_PERFCTR0 0xc0010004
810	#define MSR_K7_PERFCTR1 0xc0010005
811	#define MSR_K7_PERFCTR2 0xc0010006
812	#define MSR_K7_PERFCTR3 0xc0010007
813
814	/** K8 LSTAR - Long mode SYSCALL target (RIP). */
815	#define MSR_K8_LSTAR 0xc0000082
816	/** K8 CSTAR - Compatibility mode SYSCALL target (RIP). */
817	#define MSR_K8_CSTAR 0xc0000083
818	/** K8 SF_MASK - SYSCALL flag mask. (aka SFMASK) */
819	#define MSR_K8_SF_MASK 0xc0000084
820	/** K8 FS.base - The 64-bit base FS register. */
821	#define MSR_K8_FS_BASE 0xc0000100
822	/** K8 GS.base - The 64-bit base GS register. */
823	#define MSR_K8_GS_BASE 0xc0000101
824	/** K8 KernelGSbase - Used with SWAPGS. */
825	#define MSR_K8_KERNEL_GS_BASE 0xc0000102
826	#define MSR_K8_TSC_AUX 0xc0000103
827	#define MSR_K8_SYSCFG 0xc0010010
828	#define MSR_K8_HWCR 0xc0010015
829	#define MSR_K8_IORRBASE0 0xc0010016
830	#define MSR_K8_IORRMASK0 0xc0010017
831	#define MSR_K8_IORRBASE1 0xc0010018
832	#define MSR_K8_IORRMASK1 0xc0010019
833	#define MSR_K8_TOP_MEM1 0xc001001a
834	#define MSR_K8_TOP_MEM2 0xc001001d
835	#define MSR_K8_VM_CR 0xc0010114
836	#define MSR_K8_VM_CR_SVM_DISABLE RT_BIT(4)
837
838	#define MSR_K8_IGNNE 0xc0010115
839	#define MSR_K8_SMM_CTL 0xc0010116
840	/** SVM - VM_HSAVE_PA - Physical address for saving and restoring
841	* host state during world switch.
842	*/
843	#define MSR_K8_VM_HSAVE_PA 0xc0010117
844
845	/** @} */
846
847
848	/** @name Page Table / Directory / Directory Pointers / L4.
849	* @{
850	*/
851
852	/** Page table/directory entry as an unsigned integer. */
853	typedef uint32_t X86PGUINT;
854	/** Pointer to a page table/directory table entry as an unsigned integer. */
855	typedef X86PGUINT *PX86PGUINT;
856
857	/** Number of entries in a 32-bit PT/PD. */
858	#define X86_PG_ENTRIES 1024
859
860
861	/** PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
862	typedef uint64_t X86PGPAEUINT;
863	/** Pointer to a PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
864	typedef X86PGPAEUINT *PX86PGPAEUINT;
865
866	/** Number of entries in a PAE PT/PD. */
867	#define X86_PG_PAE_ENTRIES 512
868	/** Number of entries in a PAE PDPT. */
869	#define X86_PG_PAE_PDPE_ENTRIES 4
870
871	/** Number of entries in an AMD64 PT/PD/PDPT/L4/L5. */
872	#define X86_PG_AMD64_ENTRIES X86_PG_PAE_ENTRIES
873	/** Number of entries in an AMD64 PDPT.
874	* Just for complementing X86_PG_PAE_PDPE_ENTRIES, using X86_PG_AMD64_ENTRIES for this is fine too. */
875	#define X86_PG_AMD64_PDPE_ENTRIES X86_PG_AMD64_ENTRIES
876
877	/** The size of a 4KB page. */
878	#define X86_PAGE_4K_SIZE _4K
879	/** The page shift of a 4KB page. */
880	#define X86_PAGE_4K_SHIFT 12
881	/** The 4KB page offset mask. */
882	#define X86_PAGE_4K_OFFSET_MASK 0xfff
883	/** The 4KB page base mask for virtual addresses. */
884	#define X86_PAGE_4K_BASE_MASK 0xfffffffffffff000ULL
885	/** The 4KB page base mask for virtual addresses - 32bit version. */
886	#define X86_PAGE_4K_BASE_MASK_32 0xfffff000U
887
888	/** The size of a 2MB page. */
889	#define X86_PAGE_2M_SIZE _2M
890	/** The page shift of a 2MB page. */
891	#define X86_PAGE_2M_SHIFT 21
892	/** The 2MB page offset mask. */
893	#define X86_PAGE_2M_OFFSET_MASK 0x001fffff
894	/** The 2MB page base mask for virtual addresses. */
895	#define X86_PAGE_2M_BASE_MASK 0xffffffffffe00000ULL
896	/** The 2MB page base mask for virtual addresses - 32bit version. */
897	#define X86_PAGE_2M_BASE_MASK_32 0xffe00000U
898
899	/** The size of a 4MB page. */
900	#define X86_PAGE_4M_SIZE _4M
901	/** The page shift of a 4MB page. */
902	#define X86_PAGE_4M_SHIFT 22
903	/** The 4MB page offset mask. */
904	#define X86_PAGE_4M_OFFSET_MASK 0x003fffff
905	/** The 4MB page base mask for virtual addresses. */
906	#define X86_PAGE_4M_BASE_MASK 0xffffffffffc00000ULL
907	/** The 4MB page base mask for virtual addresses - 32bit version. */
908	#define X86_PAGE_4M_BASE_MASK_32 0xffc00000U
909
910
911
912	/** @name Page Table Entry
913	* @{
914	*/
915	/** Bit 0 - P - Present bit. */
916	#define X86_PTE_P RT_BIT(0)
917	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
918	#define X86_PTE_RW RT_BIT(1)
919	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
920	#define X86_PTE_US RT_BIT(2)
921	/** Bit 3 - PWT - Page level write thru bit. */
922	#define X86_PTE_PWT RT_BIT(3)
923	/** Bit 4 - PCD - Page level cache disable bit. */
924	#define X86_PTE_PCD RT_BIT(4)
925	/** Bit 5 - A - Access bit. */
926	#define X86_PTE_A RT_BIT(5)
927	/** Bit 6 - D - Dirty bit. */
928	#define X86_PTE_D RT_BIT(6)
929	/** Bit 7 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
930	#define X86_PTE_PAT RT_BIT(7)
931	/** Bit 8 - G - Global flag. */
932	#define X86_PTE_G RT_BIT(8)
933	/** Bits 9-11 - - Available for use to system software. */
934	#define X86_PTE_AVL_MASK (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
935	/** Bits 12-31 - - Physical Page number of the next level. */
936	#define X86_PTE_PG_MASK ( 0xfffff000 )
937
938	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
939	#if 1 /* we're using this internally and have to mask of the top 16-bit. */
940	#define X86_PTE_PAE_PG_MASK ( 0x0000fffffffff000ULL )
941	/** @todo Get rid of the above hack; makes code unreadable. */
942	#define X86_PTE_PAE_PG_MASK_FULL ( 0x000ffffffffff000ULL )
943	#else
944	#define X86_PTE_PAE_PG_MASK ( 0x000ffffffffff000ULL )
945	#endif
946	/** Bits 63 - NX - PAE - No execution flag. */
947	#define X86_PTE_PAE_NX RT_BIT_64(63)
948
949	/**
950	* Page table entry.
951	*/
952	typedef struct X86PTEBITS
953	{
954	/** Flags whether(=1) or not the page is present. */
955	unsigned u1Present : 1;
956	/** Read(=0) / Write(=1) flag. */
957	unsigned u1Write : 1;
958	/** User(=1) / Supervisor (=0) flag. */
959	unsigned u1User : 1;
960	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
961	unsigned u1WriteThru : 1;
962	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
963	unsigned u1CacheDisable : 1;
964	/** Accessed flag.
965	* Indicates that the page have been read or written to. */
966	unsigned u1Accessed : 1;
967	/** Dirty flag.
968	* Indicates that the page have been written to. */
969	unsigned u1Dirty : 1;
970	/** Reserved / If PAT enabled, bit 2 of the index. */
971	unsigned u1PAT : 1;
972	/** Global flag. (Ignored in all but final level.) */
973	unsigned u1Global : 1;
974	/** Available for use to system software. */
975	unsigned u3Available : 3;
976	/** Physical Page number of the next level. */
977	unsigned u20PageNo : 20;
978	} X86PTEBITS;
979	/** Pointer to a page table entry. */
980	typedef X86PTEBITS *PX86PTEBITS;
981	/** Pointer to a const page table entry. */
982	typedef const X86PTEBITS *PCX86PTEBITS;
983
984	/**
985	* Page table entry.
986	*/
987	typedef union X86PTE
988	{
989	/** Bit field view. */
990	X86PTEBITS n;
991	/** Unsigned integer view */
992	X86PGUINT u;
993	/** 32-bit view. */
994	uint32_t au32[1];
995	/** 16-bit view. */
996	uint16_t au16[2];
997	/** 8-bit view. */
998	uint8_t au8[4];
999	} X86PTE;
1000	/** Pointer to a page table entry. */
1001	typedef X86PTE *PX86PTE;
1002	/** Pointer to a const page table entry. */
1003	typedef const X86PTE *PCX86PTE;
1004
1005
1006	/**
1007	* PAE page table entry.
1008	*/
1009	typedef struct X86PTEPAEBITS
1010	{
1011	/** Flags whether(=1) or not the page is present. */
1012	uint32_t u1Present : 1;
1013	/** Read(=0) / Write(=1) flag. */
1014	uint32_t u1Write : 1;
1015	/** User(=1) / Supervisor(=0) flag. */
1016	uint32_t u1User : 1;
1017	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1018	uint32_t u1WriteThru : 1;
1019	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1020	uint32_t u1CacheDisable : 1;
1021	/** Accessed flag.
1022	* Indicates that the page have been read or written to. */
1023	uint32_t u1Accessed : 1;
1024	/** Dirty flag.
1025	* Indicates that the page have been written to. */
1026	uint32_t u1Dirty : 1;
1027	/** Reserved / If PAT enabled, bit 2 of the index. */
1028	uint32_t u1PAT : 1;
1029	/** Global flag. (Ignored in all but final level.) */
1030	uint32_t u1Global : 1;
1031	/** Available for use to system software. */
1032	uint32_t u3Available : 3;
1033	/** Physical Page number of the next level - Low Part. Don't use this. */
1034	uint32_t u20PageNoLow : 20;
1035	/** Physical Page number of the next level - High Part. Don't use this. */
1036	uint32_t u20PageNoHigh : 20;
1037	/** MBZ bits */
1038	uint32_t u11Reserved : 11;
1039	/** No Execute flag. */
1040	uint32_t u1NoExecute : 1;
1041	} X86PTEPAEBITS;
1042	/** Pointer to a page table entry. */
1043	typedef X86PTEPAEBITS *PX86PTEPAEBITS;
1044	/** Pointer to a page table entry. */
1045	typedef const X86PTEPAEBITS *PCX86PTEPAEBITS;
1046
1047	/**
1048	* PAE Page table entry.
1049	*/
1050	typedef union X86PTEPAE
1051	{
1052	/** Bit field view. */
1053	X86PTEPAEBITS n;
1054	/** Unsigned integer view */
1055	X86PGPAEUINT u;
1056	/** 32-bit view. */
1057	uint32_t au32[2];
1058	/** 16-bit view. */
1059	uint16_t au16[4];
1060	/** 8-bit view. */
1061	uint8_t au8[8];
1062	} X86PTEPAE;
1063	/** Pointer to a PAE page table entry. */
1064	typedef X86PTEPAE *PX86PTEPAE;
1065	/** Pointer to a const PAE page table entry. */
1066	typedef const X86PTEPAE *PCX86PTEPAE;
1067	/** @} */
1068
1069	/**
1070	* Page table.
1071	*/
1072	typedef struct X86PT
1073	{
1074	/** PTE Array. */
1075	X86PTE a[X86_PG_ENTRIES];
1076	} X86PT;
1077	/** Pointer to a page table. */
1078	typedef X86PT *PX86PT;
1079	/** Pointer to a const page table. */
1080	typedef const X86PT *PCX86PT;
1081
1082	/** The page shift to get the PT index. */
1083	#define X86_PT_SHIFT 12
1084	/** The PT index mask (apply to a shifted page address). */
1085	#define X86_PT_MASK 0x3ff
1086
1087
1088	/**
1089	* Page directory.
1090	*/
1091	typedef struct X86PTPAE
1092	{
1093	/** PTE Array. */
1094	X86PTEPAE a[X86_PG_PAE_ENTRIES];
1095	} X86PTPAE;
1096	/** Pointer to a page table. */
1097	typedef X86PTPAE *PX86PTPAE;
1098	/** Pointer to a const page table. */
1099	typedef const X86PTPAE *PCX86PTPAE;
1100
1101	/** The page shift to get the PA PTE index. */
1102	#define X86_PT_PAE_SHIFT 12
1103	/** The PAE PT index mask (apply to a shifted page address). */
1104	#define X86_PT_PAE_MASK 0x1ff
1105
1106
1107	/** @name 4KB Page Directory Entry
1108	* @{
1109	*/
1110	/** Bit 0 - P - Present bit. */
1111	#define X86_PDE_P RT_BIT(0)
1112	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1113	#define X86_PDE_RW RT_BIT(1)
1114	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1115	#define X86_PDE_US RT_BIT(2)
1116	/** Bit 3 - PWT - Page level write thru bit. */
1117	#define X86_PDE_PWT RT_BIT(3)
1118	/** Bit 4 - PCD - Page level cache disable bit. */
1119	#define X86_PDE_PCD RT_BIT(4)
1120	/** Bit 5 - A - Access bit. */
1121	#define X86_PDE_A RT_BIT(5)
1122	/** Bit 7 - PS - Page size attribute.
1123	* Clear mean 4KB pages, set means large pages (2/4MB). */
1124	#define X86_PDE_PS RT_BIT(7)
1125	/** Bits 9-11 - - Available for use to system software. */
1126	#define X86_PDE_AVL_MASK (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
1127	/** Bits 12-31 - - Physical Page number of the next level. */
1128	#define X86_PDE_PG_MASK ( 0xfffff000 )
1129
1130	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1131	#if 1 /* we're using this internally and have to mask of the top 16-bit. */
1132	/* Note: This is kind of dangerous if the guest uses these bits (legally or illegally);
1133	* we partly or that part into shadow page table entries. Will be corrected
1134	* soon.
1135	*/
1136	#define X86_PDE_PAE_PG_MASK ( 0x0000fffffffff000ULL )
1137	#define X86_PDE_PAE_PG_MASK_FULL ( 0x000ffffffffff000ULL )
1138	#else
1139	#define X86_PDE_PAE_PG_MASK ( 0x000ffffffffff000ULL )
1140	#endif
1141	/** Bits 63 - NX - PAE - No execution flag. */
1142	#define X86_PDE_PAE_NX RT_BIT_64(63)
1143
1144	/**
1145	* Page directory entry.
1146	*/
1147	typedef struct X86PDEBITS
1148	{
1149	/** Flags whether(=1) or not the page is present. */
1150	unsigned u1Present : 1;
1151	/** Read(=0) / Write(=1) flag. */
1152	unsigned u1Write : 1;
1153	/** User(=1) / Supervisor (=0) flag. */
1154	unsigned u1User : 1;
1155	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1156	unsigned u1WriteThru : 1;
1157	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1158	unsigned u1CacheDisable : 1;
1159	/** Accessed flag.
1160	* Indicates that the page have been read or written to. */
1161	unsigned u1Accessed : 1;
1162	/** Reserved / Ignored (dirty bit). */
1163	unsigned u1Reserved0 : 1;
1164	/** Size bit if PSE is enabled - in any event it's 0. */
1165	unsigned u1Size : 1;
1166	/** Reserved / Ignored (global bit). */
1167	unsigned u1Reserved1 : 1;
1168	/** Available for use to system software. */
1169	unsigned u3Available : 3;
1170	/** Physical Page number of the next level. */
1171	unsigned u20PageNo : 20;
1172	} X86PDEBITS;
1173	/** Pointer to a page directory entry. */
1174	typedef X86PDEBITS *PX86PDEBITS;
1175	/** Pointer to a const page directory entry. */
1176	typedef const X86PDEBITS *PCX86PDEBITS;
1177
1178
1179	/**
1180	* PAE page directory entry.
1181	*/
1182	typedef struct X86PDEPAEBITS
1183	{
1184	/** Flags whether(=1) or not the page is present. */
1185	uint32_t u1Present : 1;
1186	/** Read(=0) / Write(=1) flag. */
1187	uint32_t u1Write : 1;
1188	/** User(=1) / Supervisor (=0) flag. */
1189	uint32_t u1User : 1;
1190	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1191	uint32_t u1WriteThru : 1;
1192	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1193	uint32_t u1CacheDisable : 1;
1194	/** Accessed flag.
1195	* Indicates that the page have been read or written to. */
1196	uint32_t u1Accessed : 1;
1197	/** Reserved / Ignored (dirty bit). */
1198	uint32_t u1Reserved0 : 1;
1199	/** Size bit if PSE is enabled - in any event it's 0. */
1200	uint32_t u1Size : 1;
1201	/** Reserved / Ignored (global bit). / */
1202	uint32_t u1Reserved1 : 1;
1203	/** Available for use to system software. */
1204	uint32_t u3Available : 3;
1205	/** Physical Page number of the next level - Low Part. Don't use! */
1206	uint32_t u20PageNoLow : 20;
1207	/** Physical Page number of the next level - High Part. Don't use! */
1208	uint32_t u20PageNoHigh : 20;
1209	/** MBZ bits */
1210	uint32_t u11Reserved : 11;
1211	/** No Execute flag. */
1212	uint32_t u1NoExecute : 1;
1213	} X86PDEPAEBITS;
1214	/** Pointer to a page directory entry. */
1215	typedef X86PDEPAEBITS *PX86PDEPAEBITS;
1216	/** Pointer to a const page directory entry. */
1217	typedef const X86PDEPAEBITS *PCX86PDEPAEBITS;
1218
1219	/** @} */
1220
1221
1222	/** @name 2/4MB Page Directory Entry
1223	* @{
1224	*/
1225	/** Bit 0 - P - Present bit. */
1226	#define X86_PDE4M_P RT_BIT(0)
1227	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1228	#define X86_PDE4M_RW RT_BIT(1)
1229	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1230	#define X86_PDE4M_US RT_BIT(2)
1231	/** Bit 3 - PWT - Page level write thru bit. */
1232	#define X86_PDE4M_PWT RT_BIT(3)
1233	/** Bit 4 - PCD - Page level cache disable bit. */
1234	#define X86_PDE4M_PCD RT_BIT(4)
1235	/** Bit 5 - A - Access bit. */
1236	#define X86_PDE4M_A RT_BIT(5)
1237	/** Bit 6 - D - Dirty bit. */
1238	#define X86_PDE4M_D RT_BIT(6)
1239	/** Bit 7 - PS - Page size attribute. Clear mean 4KB pages, set means large pages (2/4MB). */
1240	#define X86_PDE4M_PS RT_BIT(7)
1241	/** Bit 8 - G - Global flag. */
1242	#define X86_PDE4M_G RT_BIT(8)
1243	/** Bits 9-11 - AVL - Available for use to system software. */
1244	#define X86_PDE4M_AVL (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
1245	/** Bit 12 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
1246	#define X86_PDE4M_PAT RT_BIT(12)
1247	/** Shift to get from X86_PTE_PAT to X86_PDE4M_PAT. */
1248	#define X86_PDE4M_PAT_SHIFT (12 - 7)
1249	/** Bits 22-31 - - Physical Page number. */
1250	#define X86_PDE4M_PG_MASK ( 0xffc00000 )
1251	/** Bits 13-20 - - Physical Page number high part (32-39 bits). AMD64 hack. */
1252	#define X86_PDE4M_PG_HIGH_MASK ( 0x001fe000 )
1253	/** The number of bits to the high part of the page number. */
1254	#define X86_PDE4M_PG_HIGH_SHIFT 19
1255
1256	/** Bits 21-51 - - PAE & AMD64 - Physical Page number.
1257	* (Bits 40-51 (long mode) & bits 36-51 (pae legacy) are reserved according to the Intel docs; AMD allows for more.) */
1258	#define X86_PDE2M_PAE_PG_MASK ( 0x000fffffffe00000ULL )
1259	/** Bits 63 - NX - PAE & AMD64 - No execution flag. */
1260	#define X86_PDE2M_PAE_NX X86_PDE2M_PAE_NX
1261
1262	/**
1263	* 4MB page directory entry.
1264	*/
1265	typedef struct X86PDE4MBITS
1266	{
1267	/** Flags whether(=1) or not the page is present. */
1268	unsigned u1Present : 1;
1269	/** Read(=0) / Write(=1) flag. */
1270	unsigned u1Write : 1;
1271	/** User(=1) / Supervisor (=0) flag. */
1272	unsigned u1User : 1;
1273	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1274	unsigned u1WriteThru : 1;
1275	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1276	unsigned u1CacheDisable : 1;
1277	/** Accessed flag.
1278	* Indicates that the page have been read or written to. */
1279	unsigned u1Accessed : 1;
1280	/** Dirty flag.
1281	* Indicates that the page have been written to. */
1282	unsigned u1Dirty : 1;
1283	/** Page size flag - always 1 for 4MB entries. */
1284	unsigned u1Size : 1;
1285	/** Global flag. */
1286	unsigned u1Global : 1;
1287	/** Available for use to system software. */
1288	unsigned u3Available : 3;
1289	/** Reserved / If PAT enabled, bit 2 of the index. */
1290	unsigned u1PAT : 1;
1291	/** Bits 32-39 of the page number on AMD64.
1292	* This AMD64 hack allows accessing 40bits of physical memory without PAE. */
1293	unsigned u8PageNoHigh : 8;
1294	/** Reserved. */
1295	unsigned u1Reserved : 1;
1296	/** Physical Page number of the page. */
1297	unsigned u10PageNo : 10;
1298	} X86PDE4MBITS;
1299	/** Pointer to a page table entry. */
1300	typedef X86PDE4MBITS *PX86PDE4MBITS;
1301	/** Pointer to a const page table entry. */
1302	typedef const X86PDE4MBITS *PCX86PDE4MBITS;
1303
1304
1305	/**
1306	* 2MB PAE page directory entry.
1307	*/
1308	typedef struct X86PDE2MPAEBITS
1309	{
1310	/** Flags whether(=1) or not the page is present. */
1311	uint32_t u1Present : 1;
1312	/** Read(=0) / Write(=1) flag. */
1313	uint32_t u1Write : 1;
1314	/** User(=1) / Supervisor(=0) flag. */
1315	uint32_t u1User : 1;
1316	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1317	uint32_t u1WriteThru : 1;
1318	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1319	uint32_t u1CacheDisable : 1;
1320	/** Accessed flag.
1321	* Indicates that the page have been read or written to. */
1322	uint32_t u1Accessed : 1;
1323	/** Dirty flag.
1324	* Indicates that the page have been written to. */
1325	uint32_t u1Dirty : 1;
1326	/** Page size flag - always 1 for 2MB entries. */
1327	uint32_t u1Size : 1;
1328	/** Global flag. */
1329	uint32_t u1Global : 1;
1330	/** Available for use to system software. */
1331	uint32_t u3Available : 3;
1332	/** Reserved / If PAT enabled, bit 2 of the index. */
1333	uint32_t u1PAT : 1;
1334	/** Reserved. */
1335	uint32_t u9Reserved : 9;
1336	/** Physical Page number of the next level - Low part. Don't use! */
1337	uint32_t u10PageNoLow : 10;
1338	/** Physical Page number of the next level - High part. Don't use! */
1339	uint32_t u20PageNoHigh : 20;
1340	/** MBZ bits */
1341	uint32_t u11Reserved : 11;
1342	/** No Execute flag. */
1343	uint32_t u1NoExecute : 1;
1344	} X86PDE2MPAEBITS;
1345	/** Pointer to a 4MB PAE page table entry. */
1346	typedef X86PDE2MPAEBITS *PX86PDE2MPAEBITS;
1347	/** Pointer to a 4MB PAE page table entry. */
1348	typedef const X86PDE2MPAEBITS *PCX86PDE2MPAEBITS;
1349
1350	/** @} */
1351
1352	/**
1353	* Page directory entry.
1354	*/
1355	typedef union X86PDE
1356	{
1357	/** Normal view. */
1358	X86PDEBITS n;
1359	/** 4MB view (big). */
1360	X86PDE4MBITS b;
1361	/** Unsigned integer view. */
1362	X86PGUINT u;
1363	/** 8 bit unsigned integer view. */
1364	uint8_t au8[4];
1365	/** 16 bit unsigned integer view. */
1366	uint16_t au16[2];
1367	/** 32 bit unsigned integer view. */
1368	uint32_t au32[1];
1369	} X86PDE;
1370	/** Pointer to a page directory entry. */
1371	typedef X86PDE *PX86PDE;
1372	/** Pointer to a const page directory entry. */
1373	typedef const X86PDE *PCX86PDE;
1374
1375	/**
1376	* PAE page directory entry.
1377	*/
1378	typedef union X86PDEPAE
1379	{
1380	/** Normal view. */
1381	X86PDEPAEBITS n;
1382	/** 2MB page view (big). */
1383	X86PDE2MPAEBITS b;
1384	/** Unsigned integer view. */
1385	X86PGPAEUINT u;
1386	/** 8 bit unsigned integer view. */
1387	uint8_t au8[8];
1388	/** 16 bit unsigned integer view. */
1389	uint16_t au16[4];
1390	/** 32 bit unsigned integer view. */
1391	uint32_t au32[2];
1392	} X86PDEPAE;
1393	/** Pointer to a page directory entry. */
1394	typedef X86PDEPAE *PX86PDEPAE;
1395	/** Pointer to a const page directory entry. */
1396	typedef const X86PDEPAE *PCX86PDEPAE;
1397
1398	/**
1399	* Page directory.
1400	*/
1401	typedef struct X86PD
1402	{
1403	/** PDE Array. */
1404	X86PDE a[X86_PG_ENTRIES];
1405	} X86PD;
1406	/** Pointer to a page directory. */
1407	typedef X86PD *PX86PD;
1408	/** Pointer to a const page directory. */
1409	typedef const X86PD *PCX86PD;
1410
1411	/** The page shift to get the PD index. */
1412	#define X86_PD_SHIFT 22
1413	/** The PD index mask (apply to a shifted page address). */
1414	#define X86_PD_MASK 0x3ff
1415
1416
1417	/**
1418	* PAE page directory.
1419	*/
1420	typedef struct X86PDPAE
1421	{
1422	/** PDE Array. */
1423	X86PDEPAE a[X86_PG_PAE_ENTRIES];
1424	} X86PDPAE;
1425	/** Pointer to a PAE page directory. */
1426	typedef X86PDPAE *PX86PDPAE;
1427	/** Pointer to a const PAE page directory. */
1428	typedef const X86PDPAE *PCX86PDPAE;
1429
1430	/** The page shift to get the PAE PD index. */
1431	#define X86_PD_PAE_SHIFT 21
1432	/** The PAE PD index mask (apply to a shifted page address). */
1433	#define X86_PD_PAE_MASK 0x1ff
1434
1435
1436	/** @name Page Directory Pointer Table Entry (PAE)
1437	* @{
1438	*/
1439	/** Bit 0 - P - Present bit. */
1440	#define X86_PDPE_P RT_BIT(0)
1441	/** Bit 1 - R/W - Read (clear) / Write (set) bit. Long Mode only. */
1442	#define X86_PDPE_RW RT_BIT(1)
1443	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. Long Mode only. */
1444	#define X86_PDPE_US RT_BIT(2)
1445	/** Bit 3 - PWT - Page level write thru bit. */
1446	#define X86_PDPE_PWT RT_BIT(3)
1447	/** Bit 4 - PCD - Page level cache disable bit. */
1448	#define X86_PDPE_PCD RT_BIT(4)
1449	/** Bit 5 - A - Access bit. Long Mode only. */
1450	#define X86_PDPE_A RT_BIT(5)
1451	/** Bits 9-11 - - Available for use to system software. */
1452	#define X86_PDPE_AVL_MASK (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
1453	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1454	#if 1 /* we're using this internally and have to mask of the top 16-bit. */
1455	#define X86_PDPE_PG_MASK ( 0x0000fffffffff000ULL )
1456	/** @todo Get rid of the above hack; makes code unreadable. */
1457	#define X86_PDPE_PG_MASK_FULL ( 0x000ffffffffff000ULL )
1458	#else
1459	#define X86_PDPE_PG_MASK ( 0x000ffffffffff000ULL )
1460	#endif
1461	/** Bits 63 - NX - PAE - No execution flag. Long Mode only. */
1462	#define X86_PDPE_NX RT_BIT_64(63)
1463
1464	/**
1465	* Page directory pointer table entry.
1466	*/
1467	typedef struct X86PDPEBITS
1468	{
1469	/** Flags whether(=1) or not the page is present. */
1470	uint32_t u1Present : 1;
1471	/** Chunk of reserved bits. */
1472	uint32_t u2Reserved : 2;
1473	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1474	uint32_t u1WriteThru : 1;
1475	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1476	uint32_t u1CacheDisable : 1;
1477	/** Chunk of reserved bits. */
1478	uint32_t u4Reserved : 4;
1479	/** Available for use to system software. */
1480	uint32_t u3Available : 3;
1481	/** Physical Page number of the next level - Low Part. Don't use! */
1482	uint32_t u20PageNoLow : 20;
1483	/** Physical Page number of the next level - High Part. Don't use! */
1484	uint32_t u20PageNoHigh : 20;
1485	/** MBZ bits */
1486	uint32_t u12Reserved : 12;
1487	} X86PDPEBITS;
1488	/** Pointer to a page directory pointer table entry. */
1489	typedef X86PDPEBITS *PX86PTPEBITS;
1490	/** Pointer to a const page directory pointer table entry. */
1491	typedef const X86PDPEBITS *PCX86PTPEBITS;
1492
1493	/**
1494	* Page directory pointer table entry. AMD64 version
1495	*/
1496	typedef struct X86PDPEAMD64BITS
1497	{
1498	/** Flags whether(=1) or not the page is present. */
1499	uint32_t u1Present : 1;
1500	/** Read(=0) / Write(=1) flag. */
1501	uint32_t u1Write : 1;
1502	/** User(=1) / Supervisor (=0) flag. */
1503	uint32_t u1User : 1;
1504	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1505	uint32_t u1WriteThru : 1;
1506	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1507	uint32_t u1CacheDisable : 1;
1508	/** Accessed flag.
1509	* Indicates that the page have been read or written to. */
1510	uint32_t u1Accessed : 1;
1511	/** Chunk of reserved bits. */
1512	uint32_t u3Reserved : 3;
1513	/** Available for use to system software. */
1514	uint32_t u3Available : 3;
1515	/** Physical Page number of the next level - Low Part. Don't use! */
1516	uint32_t u20PageNoLow : 20;
1517	/** Physical Page number of the next level - High Part. Don't use! */
1518	uint32_t u20PageNoHigh : 20;
1519	/** MBZ bits */
1520	uint32_t u11Reserved : 11;
1521	/** No Execute flag. */
1522	uint32_t u1NoExecute : 1;
1523	} X86PDPEAMD64BITS;
1524	/** Pointer to a page directory pointer table entry. */
1525	typedef X86PDPEAMD64BITS *PX86PDPEAMD64BITS;
1526	/** Pointer to a const page directory pointer table entry. */
1527	typedef const X86PDPEBITS *PCX86PDPEAMD64BITS;
1528
1529	/**
1530	* Page directory pointer table entry.
1531	*/
1532	typedef union X86PDPE
1533	{
1534	/** Normal view. */
1535	X86PDPEBITS n;
1536	/** AMD64 view. */
1537	X86PDPEAMD64BITS lm;
1538	/** Unsigned integer view. */
1539	X86PGPAEUINT u;
1540	/** 8 bit unsigned integer view. */
1541	uint8_t au8[8];
1542	/** 16 bit unsigned integer view. */
1543	uint16_t au16[4];
1544	/** 32 bit unsigned integer view. */
1545	uint32_t au32[2];
1546	} X86PDPE;
1547	/** Pointer to a page directory pointer table entry. */
1548	typedef X86PDPE *PX86PDPE;
1549	/** Pointer to a const page directory pointer table entry. */
1550	typedef const X86PDPE *PCX86PDPE;
1551
1552
1553	/**
1554	* Page directory pointer table.
1555	*/
1556	typedef struct X86PDPT
1557	{
1558	/** PDE Array. */
1559	X86PDPE a[X86_PG_AMD64_PDPE_ENTRIES];
1560	} X86PDPT;
1561	/** Pointer to a page directory pointer table. */
1562	typedef X86PDPT *PX86PDPT;
1563	/** Pointer to a const page directory pointer table. */
1564	typedef const X86PDPT *PCX86PDPT;
1565
1566	/** The page shift to get the PDPT index. */
1567	#define X86_PDPT_SHIFT 30
1568	/** The PDPT index mask (apply to a shifted page address). (32 bits PAE) */
1569	#define X86_PDPT_MASK_PAE 0x3
1570	/** The PDPT index mask (apply to a shifted page address). (64 bits PAE)*/
1571	#define X86_PDPT_MASK_AMD64 0x1ff
1572
1573	/** @} */
1574
1575
1576	/** @name Page Map Level-4 Entry (Long Mode PAE)
1577	* @{
1578	*/
1579	/** Bit 0 - P - Present bit. */
1580	#define X86_PML4E_P RT_BIT(0)
1581	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1582	#define X86_PML4E_RW RT_BIT(1)
1583	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1584	#define X86_PML4E_US RT_BIT(2)
1585	/** Bit 3 - PWT - Page level write thru bit. */
1586	#define X86_PML4E_PWT RT_BIT(3)
1587	/** Bit 4 - PCD - Page level cache disable bit. */
1588	#define X86_PML4E_PCD RT_BIT(4)
1589	/** Bit 5 - A - Access bit. */
1590	#define X86_PML4E_A RT_BIT(5)
1591	/** Bits 9-11 - - Available for use to system software. */
1592	#define X86_PML4E_AVL_MASK (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
1593	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1594	#if 1 /* we're using this internally and have to mask of the top 16-bit. */
1595	#define X86_PML4E_PG_MASK ( 0x0000fffffffff000ULL )
1596	#define X86_PML4E_PG_MASK_FULL ( 0x000ffffffffff000ULL )
1597	#else
1598	#define X86_PML4E_PG_MASK ( 0x000ffffffffff000ULL )
1599	#endif
1600	/** Bits 63 - NX - PAE - No execution flag. */
1601	#define X86_PML4E_NX RT_BIT_64(63)
1602
1603	/**
1604	* Page Map Level-4 Entry
1605	*/
1606	typedef struct X86PML4EBITS
1607	{
1608	/** Flags whether(=1) or not the page is present. */
1609	uint32_t u1Present : 1;
1610	/** Read(=0) / Write(=1) flag. */
1611	uint32_t u1Write : 1;
1612	/** User(=1) / Supervisor (=0) flag. */
1613	uint32_t u1User : 1;
1614	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1615	uint32_t u1WriteThru : 1;
1616	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1617	uint32_t u1CacheDisable : 1;
1618	/** Accessed flag.
1619	* Indicates that the page have been read or written to. */
1620	uint32_t u1Accessed : 1;
1621	/** Chunk of reserved bits. */
1622	uint32_t u3Reserved : 3;
1623	/** Available for use to system software. */
1624	uint32_t u3Available : 3;
1625	/** Physical Page number of the next level - Low Part. Don't use! */
1626	uint32_t u20PageNoLow : 20;
1627	/** Physical Page number of the next level - High Part. Don't use! */
1628	uint32_t u20PageNoHigh : 20;
1629	/** MBZ bits */
1630	uint32_t u11Reserved : 11;
1631	/** No Execute flag. */
1632	uint32_t u1NoExecute : 1;
1633	} X86PML4EBITS;
1634	/** Pointer to a page map level-4 entry. */
1635	typedef X86PML4EBITS *PX86PML4EBITS;
1636	/** Pointer to a const page map level-4 entry. */
1637	typedef const X86PML4EBITS *PCX86PML4EBITS;
1638
1639	/**
1640	* Page Map Level-4 Entry.
1641	*/
1642	typedef union X86PML4E
1643	{
1644	/** Normal view. */
1645	X86PML4EBITS n;
1646	/** Unsigned integer view. */
1647	X86PGPAEUINT u;
1648	/** 8 bit unsigned integer view. */
1649	uint8_t au8[8];
1650	/** 16 bit unsigned integer view. */
1651	uint16_t au16[4];
1652	/** 32 bit unsigned integer view. */
1653	uint32_t au32[2];
1654	} X86PML4E;
1655	/** Pointer to a page map level-4 entry. */
1656	typedef X86PML4E *PX86PML4E;
1657	/** Pointer to a const page map level-4 entry. */
1658	typedef const X86PML4E *PCX86PML4E;
1659
1660
1661	/**
1662	* Page Map Level-4.
1663	*/
1664	typedef struct X86PML4
1665	{
1666	/** PDE Array. */
1667	X86PML4E a[X86_PG_PAE_ENTRIES];
1668	} X86PML4;
1669	/** Pointer to a page map level-4. */
1670	typedef X86PML4 *PX86PML4;
1671	/** Pointer to a const page map level-4. */
1672	typedef const X86PML4 *PCX86PML4;
1673
1674	/** The page shift to get the PML4 index. */
1675	#define X86_PML4_SHIFT 39
1676	/** The PML4 index mask (apply to a shifted page address). */
1677	#define X86_PML4_MASK 0x1ff
1678
1679	/** @} */
1680
1681	/** @} */
1682
1683
1684	/**
1685	* 80-bit MMX/FPU register type.
1686	*/
1687	typedef struct X86FPUMMX
1688	{
1689	uint8_t reg[10];
1690	} X86FPUMMX;
1691	/** Pointer to a 80-bit MMX/FPU register type. */
1692	typedef X86FPUMMX *PX86FPUMMX;
1693	/** Pointer to a const 80-bit MMX/FPU register type. */
1694	typedef const X86FPUMMX *PCX86FPUMMX;
1695
1696	/**
1697	* FPU state (aka FSAVE/FRSTOR Memory Region).
1698	*/
1699	#pragma pack(1)
1700	typedef struct X86FPUSTATE
1701	{
1702	/** Control word. */
1703	uint16_t FCW;
1704	/** Alignment word */
1705	uint16_t Dummy1;
1706	/** Status word. */
1707	uint16_t FSW;
1708	/** Alignment word */
1709	uint16_t Dummy2;
1710	/** Tag word */
1711	uint16_t FTW;
1712	/** Alignment word */
1713	uint16_t Dummy3;
1714
1715	/** Instruction pointer. */
1716	uint32_t FPUIP;
1717	/** Code selector. */
1718	uint16_t CS;
1719	/** Opcode. */
1720	uint16_t FOP;
1721	/** FOO. */
1722	uint32_t FPUOO;
1723	/** FOS. */
1724	uint32_t FPUOS;
1725	/** FPU view - todo. */
1726	X86FPUMMX regs[8];
1727	} X86FPUSTATE;
1728	#pragma pack()
1729	/** Pointer to a FPU state. */
1730	typedef X86FPUSTATE *PX86FPUSTATE;
1731	/** Pointer to a const FPU state. */
1732	typedef const X86FPUSTATE *PCX86FPUSTATE;
1733
1734	/**
1735	* FPU Extended state (aka FXSAVE/FXRSTORE Memory Region).
1736	*/
1737	#pragma pack(1)
1738	typedef struct X86FXSTATE
1739	{
1740	/** Control word. */
1741	uint16_t FCW;
1742	/** Status word. */
1743	uint16_t FSW;
1744	/** Tag word (it's a byte actually). */
1745	uint8_t FTW;
1746	uint8_t huh1;
1747	/** Opcode. */
1748	uint16_t FOP;
1749	/** Instruction pointer. */
1750	uint32_t FPUIP;
1751	/** Code selector. */
1752	uint16_t CS;
1753	uint16_t Rsvrd1;
1754	/* - offset 16 - */
1755	/** Data pointer. */
1756	uint32_t FPUDP;
1757	/** Data segment */
1758	uint16_t DS;
1759	uint16_t Rsrvd2;
1760	uint32_t MXCSR;
1761	uint32_t MXCSR_MASK;
1762	/* - offset 32 - */
1763	union
1764	{
1765	/** MMX view. */
1766	uint64_t mmx;
1767	/** FPU view - todo. */
1768	X86FPUMMX fpu;
1769	/** 8-bit view. */
1770	uint8_t au8[16];
1771	/** 16-bit view. */
1772	uint16_t au16[8];
1773	/** 32-bit view. */
1774	uint32_t au32[4];
1775	/** 64-bit view. */
1776	uint64_t au64[2];
1777	/** 128-bit view. (yeah, very helpful) */
1778	uint128_t au128[1];
1779	} aRegs[8];
1780	/* - offset 160 - */
1781	union
1782	{
1783	/** XMM Register view . /
1784	uint128_t xmm;
1785	/** 8-bit view. */
1786	uint8_t au8[16];
1787	/** 16-bit view. */
1788	uint16_t au16[8];
1789	/** 32-bit view. */
1790	uint32_t au32[4];
1791	/** 64-bit view. */
1792	uint64_t au64[2];
1793	/** 128-bit view. (yeah, very helpful) */
1794	uint128_t au128[1];
1795	} aXMM[16]; /* 8 registers in 32 bits mode; 16 in long mode */
1796	/* - offset 416 - */
1797	uint32_t au32RsrvdRest[(512 - 416) / sizeof(uint32_t)];
1798	} X86FXSTATE;
1799	#pragma pack()
1800	/** Pointer to a FPU Extended state. */
1801	typedef X86FXSTATE *PX86FXSTATE;
1802	/** Pointer to a const FPU Extended state. */
1803	typedef const X86FXSTATE *PCX86FXSTATE;
1804
1805
1806	/** @name Selector Descriptor
1807	* @{
1808	*/
1809
1810	/**
1811	* Generic descriptor table entry
1812	*/
1813	#pragma pack(1)
1814	typedef struct X86DESCGENERIC
1815	{
1816	/** Limit - Low word. */
1817	unsigned u16LimitLow : 16;
1818	/** Base address - lowe word.
1819	* Don't try set this to 24 because MSC is doing studing things then. */
1820	unsigned u16BaseLow : 16;
1821	/** Base address - first 8 bits of high word. */
1822	unsigned u8BaseHigh1 : 8;
1823	/** Segment Type. */
1824	unsigned u4Type : 4;
1825	/** Descriptor Type. System(=0) or code/data selector */
1826	unsigned u1DescType : 1;
1827	/** Descriptor Privelege level. */
1828	unsigned u2Dpl : 2;
1829	/** Flags selector present(=1) or not. */
1830	unsigned u1Present : 1;
1831	/** Segment limit 16-19. */
1832	unsigned u4LimitHigh : 4;
1833	/** Available for system software. */
1834	unsigned u1Available : 1;
1835	/** 32 bits mode: Reserved - 0, long mode: Long Attribute Bit. */
1836	unsigned u1Long : 1;
1837	/** This flags meaning depends on the segment type. Try make sense out
1838	* of the intel manual yourself. */
1839	unsigned u1DefBig : 1;
1840	/** Granularity of the limit. If set 4KB granularity is used, if
1841	* clear byte. */
1842	unsigned u1Granularity : 1;
1843	/** Base address - highest 8 bits. */
1844	unsigned u8BaseHigh2 : 8;
1845	} X86DESCGENERIC;
1846	#pragma pack()
1847	/** Pointer to a generic descriptor entry. */
1848	typedef X86DESCGENERIC *PX86DESCGENERIC;
1849	/** Pointer to a const generic descriptor entry. */
1850	typedef const X86DESCGENERIC *PCX86DESCGENERIC;
1851
1852
1853	/**
1854	* Descriptor attributes.
1855	*/
1856	typedef struct X86DESCATTRBITS
1857	{
1858	/** Segment Type. */
1859	unsigned u4Type : 4;
1860	/** Descriptor Type. System(=0) or code/data selector */
1861	unsigned u1DescType : 1;
1862	/** Descriptor Privelege level. */
1863	unsigned u2Dpl : 2;
1864	/** Flags selector present(=1) or not. */
1865	unsigned u1Present : 1;
1866	/** Segment limit 16-19. */
1867	unsigned u4LimitHigh : 4;
1868	/** Available for system software. */
1869	unsigned u1Available : 1;
1870	/** 32 bits mode: Reserved - 0, long mode: Long Attribute Bit. */
1871	unsigned u1Long : 1;
1872	/** This flags meaning depends on the segment type. Try make sense out
1873	* of the intel manual yourself. */
1874	unsigned u1DefBig : 1;
1875	/** Granularity of the limit. If set 4KB granularity is used, if
1876	* clear byte. */
1877	unsigned u1Granularity : 1;
1878	} X86DESCATTRBITS;
1879
1880
1881	#pragma pack(1)
1882	typedef union X86DESCATTR
1883	{
1884	/** Normal view. */
1885	X86DESCATTRBITS n;
1886	/** Unsigned integer view. */
1887	uint32_t u;
1888	} X86DESCATTR;
1889	#pragma pack()
1890
1891	/** Pointer to descriptor attributes. */
1892	typedef X86DESCATTR *PX86DESCATTR;
1893	/** Pointer to const descriptor attributes. */
1894	typedef const X86DESCATTR *PCX86DESCATTR;
1895
1896
1897	/**
1898	* Descriptor table entry.
1899	*/
1900	#pragma pack(1)
1901	typedef union X86DESC
1902	{
1903	/** Generic descriptor view. */
1904	X86DESCGENERIC Gen;
1905	#if 0
1906	/** IDT view. */
1907	VBOXIDTE Idt;
1908	#endif
1909
1910	/** 8 bit unsigned interger view. */
1911	uint8_t au8[8];
1912	/** 16 bit unsigned interger view. */
1913	uint16_t au16[4];
1914	/** 32 bit unsigned interger view. */
1915	uint32_t au32[2];
1916	} X86DESC;
1917	#pragma pack()
1918	/** Pointer to descriptor table entry. */
1919	typedef X86DESC *PX86DESC;
1920	/** Pointer to const descriptor table entry. */
1921	typedef const X86DESC *PCX86DESC;
1922
1923
1924	/** @def X86DESC_BASE
1925	* Return the base address of a descriptor.
1926	*/
1927	#define X86DESC_BASE(desc) \
1928	( ((uint32_t)((desc).Gen.u8BaseHigh2) << 24) \
1929	\| ( (desc).Gen.u8BaseHigh1 << 16) \
1930	\| ( (desc).Gen.u16BaseLow ) )
1931
1932	/** @def X86DESC_LIMIT
1933	* Return the limit of a descriptor.
1934	*/
1935	#define X86DESC_LIMIT(desc) \
1936	( ((uint32_t)((desc).Gen.u4LimitHigh) << 16) \
1937	\| ( (desc).Gen.u16LimitLow ) )
1938
1939	/**
1940	* 64 bits generic descriptor table entry
1941	* Note: most of these bits have no meaning in long mode.
1942	*/
1943	#pragma pack(1)
1944	typedef struct X86DESC64GENERIC
1945	{
1946	/** Limit - Low word - IGNORED. */
1947	unsigned u16LimitLow : 16;
1948	/** Base address - lowe word. - IGNORED
1949	* Don't try set this to 24 because MSC is doing studing things then. */
1950	unsigned u16BaseLow : 16;
1951	/** Base address - first 8 bits of high word. - IGNORED */
1952	unsigned u8BaseHigh1 : 8;
1953	/** Segment Type. */
1954	unsigned u4Type : 4;
1955	/** Descriptor Type. System(=0) or code/data selector */
1956	unsigned u1DescType : 1;
1957	/** Descriptor Privelege level. */
1958	unsigned u2Dpl : 2;
1959	/** Flags selector present(=1) or not. */
1960	unsigned u1Present : 1;
1961	/** Segment limit 16-19. - IGNORED */
1962	unsigned u4LimitHigh : 4;
1963	/** Available for system software. - IGNORED */
1964	unsigned u1Available : 1;
1965	/** Long mode flag. */
1966	unsigned u1Long : 1;
1967	/** This flags meaning depends on the segment type. Try make sense out
1968	* of the intel manual yourself. */
1969	unsigned u1DefBig : 1;
1970	/** Granularity of the limit. If set 4KB granularity is used, if
1971	* clear byte. - IGNORED */
1972	unsigned u1Granularity : 1;
1973	/** Base address - highest 8 bits. - IGNORED */
1974	unsigned u8BaseHigh2 : 8;
1975	/** Base address - bits 63-32. */
1976	unsigned u32BaseHigh3 : 32;
1977	unsigned u8Reserved : 8;
1978	unsigned u5Zeros : 5;
1979	unsigned u19Reserved : 19;
1980	} X86DESC64GENERIC;
1981	#pragma pack()
1982	/** Pointer to a generic descriptor entry. */
1983	typedef X86DESC64GENERIC *PX86DESC64GENERIC;
1984	/** Pointer to a const generic descriptor entry. */
1985	typedef const X86DESC64GENERIC *PCX86DESC64GENERIC;
1986
1987	/**
1988	* System descriptor table entry (64 bits)
1989	*/
1990	#pragma pack(1)
1991	typedef struct X86DESC64SYSTEM
1992	{
1993	/** Limit - Low word. */
1994	unsigned u16LimitLow : 16;
1995	/** Base address - lowe word.
1996	* Don't try set this to 24 because MSC is doing studing things then. */
1997	unsigned u16BaseLow : 16;
1998	/** Base address - first 8 bits of high word. */
1999	unsigned u8BaseHigh1 : 8;
2000	/** Segment Type. */
2001	unsigned u4Type : 4;
2002	/** Descriptor Type. System(=0) or code/data selector */
2003	unsigned u1DescType : 1;
2004	/** Descriptor Privelege level. */
2005	unsigned u2Dpl : 2;
2006	/** Flags selector present(=1) or not. */
2007	unsigned u1Present : 1;
2008	/** Segment limit 16-19. */
2009	unsigned u4LimitHigh : 4;
2010	/** Available for system software. */
2011	unsigned u1Available : 1;
2012	/** Reserved - 0. */
2013	unsigned u1Reserved : 1;
2014	/** This flags meaning depends on the segment type. Try make sense out
2015	* of the intel manual yourself. */
2016	unsigned u1DefBig : 1;
2017	/** Granularity of the limit. If set 4KB granularity is used, if
2018	* clear byte. */
2019	unsigned u1Granularity : 1;
2020	/** Base address - bits 31-24. */
2021	unsigned u8BaseHigh2 : 8;
2022	/** Base address - bits 63-32. */
2023	unsigned u32BaseHigh3 : 32;
2024	unsigned u8Reserved : 8;
2025	unsigned u5Zeros : 5;
2026	unsigned u19Reserved : 19;
2027	} X86DESC64SYSTEM;
2028	#pragma pack()
2029	/** Pointer to a generic descriptor entry. */
2030	typedef X86DESC64SYSTEM *PX86DESC64SYSTEM;
2031	/** Pointer to a const generic descriptor entry. */
2032	typedef const X86DESC64SYSTEM *PCX86DESC64SYSTEM;
2033
2034
2035	/**
2036	* Descriptor table entry.
2037	*/
2038	#pragma pack(1)
2039	typedef union X86DESC64
2040	{
2041	/** Generic descriptor view. */
2042	X86DESC64GENERIC Gen;
2043	/** System descriptor view. */
2044	X86DESC64SYSTEM System;
2045	#if 0
2046	X86DESC64GATE Gate;
2047	#endif
2048
2049	/** 8 bit unsigned interger view. */
2050	uint8_t au8[16];
2051	/** 16 bit unsigned interger view. */
2052	uint16_t au16[8];
2053	/** 32 bit unsigned interger view. */
2054	uint32_t au32[4];
2055	/** 64 bit unsigned interger view. */
2056	uint64_t au64[2];
2057	} X86DESC64;
2058	#pragma pack()
2059	/** Pointer to descriptor table entry. */
2060	typedef X86DESC64 *PX86DESC64;
2061	/** Pointer to const descriptor table entry. */
2062	typedef const X86DESC64 *PCX86DESC64;
2063
2064	#if HC_ARCH_BITS == 64
2065	typedef X86DESC64 X86DESCHC;
2066	typedef X86DESC64 *PX86DESCHC;
2067	#else
2068	typedef X86DESC X86DESCHC;
2069	typedef X86DESC *PX86DESCHC;
2070	#endif
2071
2072	/** @def X86DESC_LIMIT
2073	* Return the base of a 64-bit descriptor.
2074	*/
2075	#define X86DESC64_BASE(desc) \
2076	( ((uint64_t)((desc).Gen.u32BaseHigh3) << 32) \
2077	\| ((uint32_t)((desc).Gen.u8BaseHigh2) << 24) \
2078	\| ( (desc).Gen.u8BaseHigh1 << 16) \
2079	\| ( (desc).Gen.u16BaseLow ) )
2080
2081
2082	/** @name Selector Descriptor Types.
2083	* @{
2084	*/
2085
2086	/** @name Non-System Selector Types.
2087	* @{ */
2088	/** Code(=set)/Data(=clear) bit. */
2089	#define X86_SEL_TYPE_CODE 8
2090	/** Memory(=set)/System(=clear) bit. */
2091	#define X86_SEL_TYPE_MEMORY RT_BIT(4)
2092	/** Accessed bit. */
2093	#define X86_SEL_TYPE_ACCESSED 1
2094	/** Expand down bit (for data selectors only). */
2095	#define X86_SEL_TYPE_DOWN 4
2096	/** Conforming bit (for code selectors only). */
2097	#define X86_SEL_TYPE_CONF 4
2098	/** Write bit (for data selectors only). */
2099	#define X86_SEL_TYPE_WRITE 2
2100	/** Read bit (for code selectors only). */
2101	#define X86_SEL_TYPE_READ 2
2102
2103	/** Read only selector type. */
2104	#define X86_SEL_TYPE_RO 0
2105	/** Accessed read only selector type. */
2106	#define X86_SEL_TYPE_RO_ACC (0 \| X86_SEL_TYPE_ACCESSED)
2107	/** Read write selector type. */
2108	#define X86_SEL_TYPE_RW 2
2109	/** Accessed read write selector type. */
2110	#define X86_SEL_TYPE_RW_ACC (2 \| X86_SEL_TYPE_ACCESSED)
2111	/** Expand down read only selector type. */
2112	#define X86_SEL_TYPE_RO_DOWN 4
2113	/** Accessed expand down read only selector type. */
2114	#define X86_SEL_TYPE_RO_DOWN_ACC (4 \| X86_SEL_TYPE_ACCESSED)
2115	/** Expand down read write selector type. */
2116	#define X86_SEL_TYPE_RW_DOWN 6
2117	/** Accessed expand down read write selector type. */
2118	#define X86_SEL_TYPE_RW_DOWN_ACC (6 \| X86_SEL_TYPE_ACCESSED)
2119	/** Execute only selector type. */
2120	#define X86_SEL_TYPE_EO (0 \| X86_SEL_TYPE_CODE)
2121	/** Accessed execute only selector type. */
2122	#define X86_SEL_TYPE_EO_ACC (0 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
2123	/** Execute and read selector type. */
2124	#define X86_SEL_TYPE_ER (2 \| X86_SEL_TYPE_CODE)
2125	/** Accessed execute and read selector type. */
2126	#define X86_SEL_TYPE_ER_ACC (2 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
2127	/** Conforming execute only selector type. */
2128	#define X86_SEL_TYPE_EO_CONF (4 \| X86_SEL_TYPE_CODE)
2129	/** Accessed Conforming execute only selector type. */
2130	#define X86_SEL_TYPE_EO_CONF_ACC (4 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
2131	/** Conforming execute and write selector type. */
2132	#define X86_SEL_TYPE_ER_CONF (6 \| X86_SEL_TYPE_CODE)
2133	/** Accessed Conforming execute and write selector type. */
2134	#define X86_SEL_TYPE_ER_CONF_ACC (6 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
2135	/** @} */
2136
2137
2138	/** @name System Selector Types.
2139	* @{ */
2140	/** Undefined system selector type. */
2141	#define X86_SEL_TYPE_SYS_UNDEFINED 0
2142	/** 286 TSS selector. */
2143	#define X86_SEL_TYPE_SYS_286_TSS_AVAIL 1
2144	/** LDT selector. */
2145	#define X86_SEL_TYPE_SYS_LDT 2
2146	/** 286 TSS selector - Busy. */
2147	#define X86_SEL_TYPE_SYS_286_TSS_BUSY 3
2148	/** 286 Callgate selector. */
2149	#define X86_SEL_TYPE_SYS_286_CALL_GATE 4
2150	/** Taskgate selector. */
2151	#define X86_SEL_TYPE_SYS_TASK_GATE 5
2152	/** 286 Interrupt gate selector. */
2153	#define X86_SEL_TYPE_SYS_286_INT_GATE 6
2154	/** 286 Trapgate selector. */
2155	#define X86_SEL_TYPE_SYS_286_TRAP_GATE 7
2156	/** Undefined system selector. */
2157	#define X86_SEL_TYPE_SYS_UNDEFINED2 8
2158	/** 386 TSS selector. */
2159	#define X86_SEL_TYPE_SYS_386_TSS_AVAIL 9
2160	/** Undefined system selector. */
2161	#define X86_SEL_TYPE_SYS_UNDEFINED3 0xA
2162	/** 386 TSS selector - Busy. */
2163	#define X86_SEL_TYPE_SYS_386_TSS_BUSY 0xB
2164	/** 386 Callgate selector. */
2165	#define X86_SEL_TYPE_SYS_386_CALL_GATE 0xC
2166	/** Undefined system selector. */
2167	#define X86_SEL_TYPE_SYS_UNDEFINED4 0xD
2168	/** 386 Interruptgate selector. */
2169	#define X86_SEL_TYPE_SYS_386_INT_GATE 0xE
2170	/** 386 Trapgate selector. */
2171	#define X86_SEL_TYPE_SYS_386_TRAP_GATE 0xF
2172	/** @} */
2173
2174	/** @name AMD64 System Selector Types.
2175	* @{ */
2176	#define AMD64_SEL_TYPE_SYS_LDT 2
2177	/** 286 TSS selector - Busy. */
2178	#define AMD64_SEL_TYPE_SYS_TSS_AVAIL 9
2179	/** 386 TSS selector - Busy. */
2180	#define AMD64_SEL_TYPE_SYS_TSS_BUSY 0xB
2181	/** 386 Callgate selector. */
2182	#define AMD64_SEL_TYPE_SYS_CALL_GATE 0xC
2183	/** 386 Interruptgate selector. */
2184	#define AMD64_SEL_TYPE_SYS_INT_GATE 0xE
2185	/** 386 Trapgate selector. */
2186	#define AMD64_SEL_TYPE_SYS_TRAP_GATE 0xF
2187	/** @} */
2188
2189	/** @} */
2190
2191
2192	/** @name Descriptor Table Entry Flag Masks.
2193	* These are for the 2nd 32-bit word of a descriptor.
2194	* @{ */
2195	/** Bits 8-11 - TYPE - Descriptor type mask. */
2196	#define X86_DESC_TYPE_MASK (RT_BIT(8) \| RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
2197	/** Bit 12 - S - System (=0) or Code/Data (=1). */
2198	#define X86_DESC_S RT_BIT(12)
2199	/** Bits 13-14 - DPL - Descriptor Privilege Level. */
2200	#define X86_DESC_DPL (RT_BIT(13) \| RT_BIT(14))
2201	/** Bit 15 - P - Present. */
2202	#define X86_DESC_P RT_BIT(15)
2203	/** Bit 20 - AVL - Available for system software. */
2204	#define X86_DESC_AVL RT_BIT(20)
2205	/** Bit 22 - DB - Default operation size. 0 = 16 bit, 1 = 32 bit. */
2206	#define X86_DESC_DB RT_BIT(22)
2207	/** Bit 23 - G - Granularity of the limit. If set 4KB granularity is
2208	* used, if clear byte. */
2209	#define X86_DESC_G RT_BIT(23)
2210	/** @} */
2211
2212	/** @} */
2213
2214
2215	/** @name Selectors.
2216	* @{
2217	*/
2218
2219	/**
2220	* The shift used to convert a selector from and to index an index (C).
2221	*/
2222	#define X86_SEL_SHIFT 3
2223
2224	/**
2225	* The shift used to convert a selector from and to index an index (C).
2226	*/
2227	#define AMD64_SEL_SHIFT 4
2228
2229	#if HC_ARCH_BITS == 64
2230	#define X86_SEL_SHIFT_HC AMD64_SEL_SHIFT
2231	#else
2232	#define X86_SEL_SHIFT_HC X86_SEL_SHIFT
2233	#endif
2234
2235	/**
2236	* The mask used to mask off the table indicator and CPL of an selector.
2237	*/
2238	#define X86_SEL_MASK 0xfff8
2239
2240	/**
2241	* The bit indicating that a selector is in the LDT and not in the GDT.
2242	*/
2243	#define X86_SEL_LDT 0x0004
2244	/**
2245	* The bit mask for getting the RPL of a selector.
2246	*/
2247	#define X86_SEL_RPL 0x0003
2248
2249	/** @} */
2250
2251
2252	/**
2253	* x86 Exceptions/Faults/Traps.
2254	*/
2255	typedef enum X86XCPT
2256	{
2257	/** \#DE - Divide error. */
2258	X86_XCPT_DE = 0x00,
2259	/** \#DB - Debug event (single step, DRx, ..) */
2260	X86_XCPT_DB = 0x01,
2261	/** NMI - Non-Maskable Interrupt */
2262	X86_XCPT_NMI = 0x02,
2263	/** \#BP - Breakpoint (INT3). */
2264	X86_XCPT_BP = 0x03,
2265	/** \#OF - Overflow (INTO). */
2266	X86_XCPT_OF = 0x04,
2267	/** \#BR - Bound range exceeded (BOUND). */
2268	X86_XCPT_BR = 0x05,
2269	/** \#UD - Undefined opcode. */
2270	X86_XCPT_UD = 0x06,
2271	/** \#NM - Device not available (math coprocessor device). */
2272	X86_XCPT_NM = 0x07,
2273	/** \#DF - Double fault. */
2274	X86_XCPT_DF = 0x08,
2275	/** ??? - Coprocessor segment overrun (obsolete). */
2276	X86_XCPT_CO_SEG_OVERRUN = 0x09,
2277	/** \#TS - Taskswitch (TSS). */
2278	X86_XCPT_TS = 0x0a,
2279	/** \#NP - Segment no present. */
2280	X86_XCPT_NP = 0x0b,
2281	/** \#SS - Stack segment fault. */
2282	X86_XCPT_SS = 0x0c,
2283	/** \#GP - General protection fault. */
2284	X86_XCPT_GP = 0x0d,
2285	/** \#PF - Page fault. */
2286	X86_XCPT_PF = 0x0e,
2287	/* 0x0f is reserved. */
2288	/** \#MF - Math fault (FPU). */
2289	X86_XCPT_MF = 0x10,
2290	/** \#AC - Alignment check. */
2291	X86_XCPT_AC = 0x11,
2292	/** \#MC - Machine check. */
2293	X86_XCPT_MC = 0x12,
2294	/** \#XF - SIMD Floating-Pointer Exception. */
2295	X86_XCPT_XF = 0x13
2296	} X86XCPT;
2297	/** Pointer to a x86 exception code. */
2298	typedef X86XCPT *PX86XCPT;
2299	/** Pointer to a const x86 exception code. */
2300	typedef const X86XCPT *PCX86XCPT;
2301
2302
2303	/** @name Trap Error Codes
2304	* @{
2305	*/
2306	/** External indicator. */
2307	#define X86_TRAP_ERR_EXTERNAL 1
2308	/** IDT indicator. */
2309	#define X86_TRAP_ERR_IDT 2
2310	/** Descriptor table indicator - If set LDT, if clear GDT. */
2311	#define X86_TRAP_ERR_TI 4
2312	/** Mask for getting the selector. */
2313	#define X86_TRAP_ERR_SEL_MASK 0xfff8
2314	/** Shift for getting the selector table index (C type index). */
2315	#define X86_TRAP_ERR_SEL_SHIFT 3
2316	/** @} */
2317
2318
2319	/** @name \#PF Trap Error Codes
2320	* @{
2321	*/
2322	/** Bit 0 - P - Not present (clear) or page level protection (set) fault. */
2323	#define X86_TRAP_PF_P RT_BIT(0)
2324	/** Bit 1 - R/W - Read (clear) or write (set) access. */
2325	#define X86_TRAP_PF_RW RT_BIT(1)
2326	/** Bit 2 - U/S - CPU executing in user mode (set) or supervisor mode (clear). */
2327	#define X86_TRAP_PF_US RT_BIT(2)
2328	/** Bit 3 - RSVD- Reserved bit violation (set), i.e. reserved bit was set to 1. */
2329	#define X86_TRAP_PF_RSVD RT_BIT(3)
2330	/** Bit 4 - I/D - Instruction fetch (set) / Data access (clear) - PAE + NXE. */
2331	#define X86_TRAP_PF_ID RT_BIT(4)
2332	/** @} */
2333
2334	#pragma pack(1)
2335	/**
2336	* 32-bit IDTR/GDTR.
2337	*/
2338	typedef struct X86XDTR32
2339	{
2340	/** Size of the descriptor table. */
2341	uint16_t cb;
2342	/** Address of the descriptor table. */
2343	uint32_t uAddr;
2344	} X86XDTR32, *PX86XDTR32;
2345	#pragma pack()
2346
2347	#pragma pack(1)
2348	/**
2349	* 64-bit IDTR/GDTR.
2350	*/
2351	typedef struct X86XDTR64
2352	{
2353	/** Size of the descriptor table. */
2354	uint16_t cb;
2355	/** Address of the descriptor table. */
2356	uint64_t uAddr;
2357	} X86XDTR64, *PX86XDTR64;
2358	#pragma pack()
2359
2360	/** @} */
2361
2362	#endif
2363

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source: vbox/trunk/include/VBox/x86.h@ 10518

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