x86.h@ 10707

Last change on this file since 10707 was 10707, checked in by vboxsync, 16 years ago
Include bit 5 in the debug register armed mask.
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 83.5 KB

Line
1	/** @file
2	* X86 (and AMD64) Structures and Definitions.
3	*/
4
5	/*
6	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
7	*
8	* This file is part of VirtualBox Open Source Edition (OSE), as
9	* available from http://www.virtualbox.org. This file is free software;
10	* you can redistribute it and/or modify it under the terms of the GNU
11	* General Public License (GPL) as published by the Free Software
12	* Foundation, in version 2 as it comes in the "COPYING" file of the
13	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15	*
16	* The contents of this file may alternatively be used under the terms
17	* of the Common Development and Distribution License Version 1.0
18	* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19	* VirtualBox OSE distribution, in which case the provisions of the
20	* CDDL are applicable instead of those of the GPL.
21	*
22	* You may elect to license modified versions of this file under the
23	* terms and conditions of either the GPL or the CDDL or both.
24	*
25	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
26	* Clara, CA 95054 USA or visit http://www.sun.com if you need
27	* additional information or have any questions.
28	*/
29
30	/*
31	* x86.mac is generated from this file using:
32	* sed -e '/__VBox_x86_h__/d' -e '/#define/!d' -e 's/#define/%define/' include/VBox/x86.h
33	*/
34
35	#ifndef ___VBox_x86_h
36	#define ___VBox_x86_h
37
38	#include <VBox/types.h>
39
40	/* Workaround for Solaris sys/regset.h defining CS, DS */
41	#if defined(RT_OS_SOLARIS)
42	# undef CS
43	# undef DS
44	#endif
45
46	/** @defgroup grp_x86 x86 Types and Definitions
47	* @{
48	*/
49
50	/**
51	* EFLAGS Bits.
52	*/
53	typedef struct X86EFLAGSBITS
54	{
55	/** Bit 0 - CF - Carry flag - Status flag. */
56	unsigned u1CF : 1;
57	/** Bit 1 - 1 - Reserved flag. */
58	unsigned u1Reserved0 : 1;
59	/** Bit 2 - PF - Parity flag - Status flag. */
60	unsigned u1PF : 1;
61	/** Bit 3 - 0 - Reserved flag. */
62	unsigned u1Reserved1 : 1;
63	/** Bit 4 - AF - Auxiliary carry flag - Status flag. */
64	unsigned u1AF : 1;
65	/** Bit 5 - 0 - Reserved flag. */
66	unsigned u1Reserved2 : 1;
67	/** Bit 6 - ZF - Zero flag - Status flag. */
68	unsigned u1ZF : 1;
69	/** Bit 7 - SF - Signed flag - Status flag. */
70	unsigned u1SF : 1;
71	/** Bit 8 - TF - Trap flag - System flag. */
72	unsigned u1TF : 1;
73	/** Bit 9 - IF - Interrupt flag - System flag. */
74	unsigned u1IF : 1;
75	/** Bit 10 - DF - Direction flag - Control flag. */
76	unsigned u1DF : 1;
77	/** Bit 11 - OF - Overflow flag - Status flag. */
78	unsigned u1OF : 1;
79	/** Bit 12-13 - IOPL - I/O prvilege level flag - System flag. */
80	unsigned u2IOPL : 2;
81	/** Bit 14 - NT - Nested task flag - System flag. */
82	unsigned u1NT : 1;
83	/** Bit 15 - 0 - Reserved flag. */
84	unsigned u1Reserved3 : 1;
85	/** Bit 16 - RF - Resume flag - System flag. */
86	unsigned u1RF : 1;
87	/** Bit 17 - VM - Virtual 8086 mode - System flag. */
88	unsigned u1VM : 1;
89	/** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
90	unsigned u1AC : 1;
91	/** Bit 19 - VIF - Virtual interupt flag - System flag. */
92	unsigned u1VIF : 1;
93	/** Bit 20 - VIP - Virtual interupt pending flag - System flag. */
94	unsigned u1VIP : 1;
95	/** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
96	unsigned u1ID : 1;
97	/** Bit 22-31 - 0 - Reserved flag. */
98	unsigned u10Reserved4 : 10;
99	} X86EFLAGSBITS;
100	/** Pointer to EFLAGS bits. */
101	typedef X86EFLAGSBITS *PX86EFLAGSBITS;
102	/** Pointer to const EFLAGS bits. */
103	typedef const X86EFLAGSBITS *PCX86EFLAGSBITS;
104
105	/**
106	* EFLAGS.
107	*/
108	typedef union X86EFLAGS
109	{
110	/** The bitfield view. */
111	X86EFLAGSBITS Bits;
112	/** The 8-bit view. */
113	uint8_t au8[4];
114	/** The 16-bit view. */
115	uint16_t au16[2];
116	/** The 32-bit view. */
117	uint32_t au32[1];
118	/** The 32-bit view. */
119	uint32_t u32;
120	/** The plain unsigned view. */
121	uint32_t u;
122	} X86EFLAGS;
123	/** Pointer to EFLAGS. */
124	typedef X86EFLAGS *PX86EFLAGS;
125	/** Pointer to const EFLAGS. */
126	typedef const X86EFLAGS *PCX86EFLAGS;
127
128	/**
129	* RFLAGS (32 upper bits are reserved).
130	*/
131	typedef union X86RFLAGS
132	{
133	/** The bitfield view. */
134	X86EFLAGSBITS Bits;
135	/** The 8-bit view. */
136	uint8_t au8[8];
137	/** The 16-bit view. */
138	uint16_t au16[4];
139	/** The 32-bit view. */
140	uint32_t au32[2];
141	/** The 64-bit view. */
142	uint64_t au64[1];
143	/** The 64-bit view. */
144	uint64_t u64;
145	/** The plain unsigned view. */
146	uint64_t u;
147	} X86RFLAGS;
148	/** Pointer to RFLAGS. */
149	typedef X86RFLAGS *PX86RFLAGS;
150	/** Pointer to const RFLAGS. */
151	typedef const X86RFLAGS *PCX86RFLAGS;
152
153
154	/** @name EFLAGS
155	* @{
156	*/
157	/** Bit 0 - CF - Carry flag - Status flag. */
158	#define X86_EFL_CF RT_BIT(0)
159	/** Bit 2 - PF - Parity flag - Status flag. */
160	#define X86_EFL_PF RT_BIT(2)
161	/** Bit 4 - AF - Auxiliary carry flag - Status flag. */
162	#define X86_EFL_AF RT_BIT(4)
163	/** Bit 6 - ZF - Zero flag - Status flag. */
164	#define X86_EFL_ZF RT_BIT(6)
165	/** Bit 7 - SF - Signed flag - Status flag. */
166	#define X86_EFL_SF RT_BIT(7)
167	/** Bit 8 - TF - Trap flag - System flag. */
168	#define X86_EFL_TF RT_BIT(8)
169	/** Bit 9 - IF - Interrupt flag - System flag. */
170	#define X86_EFL_IF RT_BIT(9)
171	/** Bit 10 - DF - Direction flag - Control flag. */
172	#define X86_EFL_DF RT_BIT(10)
173	/** Bit 11 - OF - Overflow flag - Status flag. */
174	#define X86_EFL_OF RT_BIT(11)
175	/** Bit 12-13 - IOPL - I/O prvilege level flag - System flag. */
176	#define X86_EFL_IOPL (RT_BIT(12) \| RT_BIT(13))
177	/** Bit 14 - NT - Nested task flag - System flag. */
178	#define X86_EFL_NT RT_BIT(14)
179	/** Bit 16 - RF - Resume flag - System flag. */
180	#define X86_EFL_RF RT_BIT(16)
181	/** Bit 17 - VM - Virtual 8086 mode - System flag. */
182	#define X86_EFL_VM RT_BIT(17)
183	/** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
184	#define X86_EFL_AC RT_BIT(18)
185	/** Bit 19 - VIF - Virtual interupt flag - System flag. */
186	#define X86_EFL_VIF RT_BIT(19)
187	/** Bit 20 - VIP - Virtual interupt pending flag - System flag. */
188	#define X86_EFL_VIP RT_BIT(20)
189	/** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
190	#define X86_EFL_ID RT_BIT(21)
191	/** IOPL shift. */
192	#define X86_EFL_IOPL_SHIFT 12
193	/** The the IOPL level from the flags. */
194	#define X86_EFL_GET_IOPL(efl) (((efl) >> X86_EFL_IOPL_SHIFT) & 3)
195	/** @} */
196
197
198	/** CPUID Feature information - ECX.
199	* CPUID query with EAX=1.
200	*/
201	typedef struct X86CPUIDFEATECX
202	{
203	/** Bit 0 - SSE3 - Supports SSE3 or not. */
204	unsigned u1SSE3 : 1;
205	/** Reserved. */
206	unsigned u2Reserved1 : 2;
207	/** Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
208	unsigned u1Monitor : 1;
209	/** Bit 4 - CPL-DS - CPL Qualified Debug Store. */
210	unsigned u1CPLDS : 1;
211	/** Bit 5 - VMX - Virtual Machine Technology. */
212	unsigned u1VMX : 1;
213	/** Reserved. */
214	unsigned u1Reserved2 : 1;
215	/** Bit 7 - EST - Enh. SpeedStep Tech. */
216	unsigned u1EST : 1;
217	/** Bit 8 - TM2 - Terminal Monitor 2. */
218	unsigned u1TM2 : 1;
219	/** Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
220	unsigned u1SSSE3 : 1;
221	/** Bit 10 - CNTX-ID - L1 Context ID. */
222	unsigned u1CNTXID : 1;
223	/** Reserved. */
224	unsigned u2Reserved4 : 2;
225	/** Bit 13 - CX16 - CMPXCHG16B. */
226	unsigned u1CX16 : 1;
227	/** Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
228	unsigned u1TPRUpdate : 1;
229	/** Reserved. */
230	unsigned u17Reserved5 : 17;
231
232	} X86CPUIDFEATECX;
233	/** Pointer to CPUID Feature Information - ECX. */
234	typedef X86CPUIDFEATECX *PX86CPUIDFEATECX;
235	/** Pointer to const CPUID Feature Information - ECX. */
236	typedef const X86CPUIDFEATECX *PCX86CPUIDFEATECX;
237
238
239	/** CPUID Feature Information - EDX.
240	* CPUID query with EAX=1.
241	*/
242	typedef struct X86CPUIDFEATEDX
243	{
244	/** Bit 0 - FPU - x87 FPU on Chip. */
245	unsigned u1FPU : 1;
246	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
247	unsigned u1VME : 1;
248	/** Bit 2 - DE - Debugging extensions. */
249	unsigned u1DE : 1;
250	/** Bit 3 - PSE - Page Size Extension. */
251	unsigned u1PSE : 1;
252	/** Bit 4 - TSC - Time Stamp Counter. */
253	unsigned u1TSC : 1;
254	/** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
255	unsigned u1MSR : 1;
256	/** Bit 6 - PAE - Physical Address Extension. */
257	unsigned u1PAE : 1;
258	/** Bit 7 - MCE - Machine Check Exception. */
259	unsigned u1MCE : 1;
260	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
261	unsigned u1CX8 : 1;
262	/** Bit 9 - APIC - APIC On-Chip. */
263	unsigned u1APIC : 1;
264	/** Bit 10 - Reserved. */
265	unsigned u1Reserved1 : 1;
266	/** Bit 11 - SEP - SYSENTER and SYSEXIT. */
267	unsigned u1SEP : 1;
268	/** Bit 12 - MTRR - Memory Type Range Registers. */
269	unsigned u1MTRR : 1;
270	/** Bit 13 - PGE - PTE Global Bit. */
271	unsigned u1PGE : 1;
272	/** Bit 14 - MCA - Machine Check Architecture. */
273	unsigned u1MCA : 1;
274	/** Bit 15 - CMOV - Conditional Move Instructions. */
275	unsigned u1CMOV : 1;
276	/** Bit 16 - PAT - Page Attribute Table. */
277	unsigned u1PAT : 1;
278	/** Bit 17 - PSE-36 - 36-bit Page Size Extention. */
279	unsigned u1PSE36 : 1;
280	/** Bit 18 - PSN - Processor Serial Number. */
281	unsigned u1PSN : 1;
282	/** Bit 19 - CLFSH - CLFLUSH Instruction. */
283	unsigned u1CLFSH : 1;
284	/** Bit 20 - Reserved. */
285	unsigned u1Reserved2 : 1;
286	/** Bit 21 - DS - Debug Store. */
287	unsigned u1DS : 1;
288	/** Bit 22 - ACPI - Thermal Monitor and Software Controlled Clock Facilities. */
289	unsigned u1ACPI : 1;
290	/** Bit 23 - MMX - Intel MMX 'Technology'. */
291	unsigned u1MMX : 1;
292	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
293	unsigned u1FXSR : 1;
294	/** Bit 25 - SSE - SSE Support. */
295	unsigned u1SSE : 1;
296	/** Bit 26 - SSE2 - SSE2 Support. */
297	unsigned u1SSE2 : 1;
298	/** Bit 27 - SS - Self Snoop. */
299	unsigned u1SS : 1;
300	/** Bit 28 - HTT - Hyper-Threading Technology. */
301	unsigned u1HTT : 1;
302	/** Bit 29 - TM - Thermal Monitor. */
303	unsigned u1TM : 1;
304	/** Bit 30 - Reserved - . */
305	unsigned u1Reserved3 : 1;
306	/** Bit 31 - PBE - Pending Break Enabled. */
307	unsigned u1PBE : 1;
308	} X86CPUIDFEATEDX;
309	/** Pointer to CPUID Feature Information - EDX. */
310	typedef X86CPUIDFEATEDX *PX86CPUIDFEATEDX;
311	/** Pointer to const CPUID Feature Information - EDX. */
312	typedef const X86CPUIDFEATEDX *PCX86CPUIDFEATEDX;
313
314	/** @name CPUID Vendor information.
315	* CPUID query with EAX=0.
316	* @{
317	*/
318	#define X86_CPUID_VENDOR_INTEL_EBX 0x756e6547 /* Genu */
319	#define X86_CPUID_VENDOR_INTEL_ECX 0x6c65746e /* ntel */
320	#define X86_CPUID_VENDOR_INTEL_EDX 0x49656e69 /* ineI */
321
322	#define X86_CPUID_VENDOR_AMD_EBX 0x68747541 /* Auth */
323	#define X86_CPUID_VENDOR_AMD_ECX 0x444d4163 /* cAMD */
324	#define X86_CPUID_VENDOR_AMD_EDX 0x69746e65 /* enti */
325	/** @} */
326
327
328	/** @name CPUID Feature information.
329	* CPUID query with EAX=1.
330	* @{
331	*/
332	/** ECX Bit 0 - SSE3 - Supports SSE3 or not. */
333	#define X86_CPUID_FEATURE_ECX_SSE3 RT_BIT(0)
334	/** ECX Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
335	#define X86_CPUID_FEATURE_ECX_MONITOR RT_BIT(3)
336	/** ECX Bit 4 - CPL-DS - CPL Qualified Debug Store. */
337	#define X86_CPUID_FEATURE_ECX_CPLDS RT_BIT(4)
338	/** ECX Bit 5 - VMX - Virtual Machine Technology. */
339	#define X86_CPUID_FEATURE_ECX_VMX RT_BIT(5)
340	/** ECX Bit 7 - EST - Enh. SpeedStep Tech. */
341	#define X86_CPUID_FEATURE_ECX_EST RT_BIT(7)
342	/** ECX Bit 8 - TM2 - Terminal Monitor 2. */
343	#define X86_CPUID_FEATURE_ECX_TM2 RT_BIT(8)
344	/** ECX Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
345	#define X86_CPUID_FEATURE_ECX_SSSE3 RT_BIT(9)
346	/** ECX Bit 10 - CNTX-ID - L1 Context ID. */
347	#define X86_CPUID_FEATURE_ECX_CNTXID RT_BIT(10)
348	/** ECX Bit 13 - CX16 - CMPXCHG16B. */
349	#define X86_CPUID_FEATURE_ECX_CX16 RT_BIT(13)
350	/** ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
351	#define X86_CPUID_FEATURE_ECX_TPRUPDATE RT_BIT(14)
352	/** ECX Bit 23 - POPCOUNT instruction. */
353	#define X86_CPUID_FEATURE_ECX_POPCOUNT RT_BIT(23)
354
355
356	/** Bit 0 - FPU - x87 FPU on Chip. */
357	#define X86_CPUID_FEATURE_EDX_FPU RT_BIT(0)
358	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
359	#define X86_CPUID_FEATURE_EDX_VME RT_BIT(1)
360	/** Bit 2 - DE - Debugging extensions. */
361	#define X86_CPUID_FEATURE_EDX_DE RT_BIT(2)
362	/** Bit 3 - PSE - Page Size Extension. */
363	#define X86_CPUID_FEATURE_EDX_PSE RT_BIT(3)
364	/** Bit 4 - TSC - Time Stamp Counter. */
365	#define X86_CPUID_FEATURE_EDX_TSC RT_BIT(4)
366	/** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
367	#define X86_CPUID_FEATURE_EDX_MSR RT_BIT(5)
368	/** Bit 6 - PAE - Physical Address Extension. */
369	#define X86_CPUID_FEATURE_EDX_PAE RT_BIT(6)
370	/** Bit 7 - MCE - Machine Check Exception. */
371	#define X86_CPUID_FEATURE_EDX_MCE RT_BIT(7)
372	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
373	#define X86_CPUID_FEATURE_EDX_CX8 RT_BIT(8)
374	/** Bit 9 - APIC - APIC On-Chip. */
375	#define X86_CPUID_FEATURE_EDX_APIC RT_BIT(9)
376	/** Bit 11 - SEP - SYSENTER and SYSEXIT. */
377	#define X86_CPUID_FEATURE_EDX_SEP RT_BIT(11)
378	/** Bit 12 - MTRR - Memory Type Range Registers. */
379	#define X86_CPUID_FEATURE_EDX_MTRR RT_BIT(12)
380	/** Bit 13 - PGE - PTE Global Bit. */
381	#define X86_CPUID_FEATURE_EDX_PGE RT_BIT(13)
382	/** Bit 14 - MCA - Machine Check Architecture. */
383	#define X86_CPUID_FEATURE_EDX_MCA RT_BIT(14)
384	/** Bit 15 - CMOV - Conditional Move Instructions. */
385	#define X86_CPUID_FEATURE_EDX_CMOV RT_BIT(15)
386	/** Bit 16 - PAT - Page Attribute Table. */
387	#define X86_CPUID_FEATURE_EDX_PAT RT_BIT(16)
388	/** Bit 17 - PSE-36 - 36-bit Page Size Extention. */
389	#define X86_CPUID_FEATURE_EDX_PSE36 RT_BIT(17)
390	/** Bit 18 - PSN - Processor Serial Number. */
391	#define X86_CPUID_FEATURE_EDX_PSN RT_BIT(18)
392	/** Bit 19 - CLFSH - CLFLUSH Instruction. */
393	#define X86_CPUID_FEATURE_EDX_CLFSH RT_BIT(19)
394	/** Bit 21 - DS - Debug Store. */
395	#define X86_CPUID_FEATURE_EDX_DS RT_BIT(21)
396	/** Bit 22 - ACPI - Termal Monitor and Software Controlled Clock Facilities. */
397	#define X86_CPUID_FEATURE_EDX_ACPI RT_BIT(22)
398	/** Bit 23 - MMX - Intel MMX Technology. */
399	#define X86_CPUID_FEATURE_EDX_MMX RT_BIT(23)
400	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
401	#define X86_CPUID_FEATURE_EDX_FXSR RT_BIT(24)
402	/** Bit 25 - SSE - SSE Support. */
403	#define X86_CPUID_FEATURE_EDX_SSE RT_BIT(25)
404	/** Bit 26 - SSE2 - SSE2 Support. */
405	#define X86_CPUID_FEATURE_EDX_SSE2 RT_BIT(26)
406	/** Bit 27 - SS - Self Snoop. */
407	#define X86_CPUID_FEATURE_EDX_SS RT_BIT(27)
408	/** Bit 28 - HTT - Hyper-Threading Technology. */
409	#define X86_CPUID_FEATURE_EDX_HTT RT_BIT(28)
410	/** Bit 29 - TM - Therm. Monitor. */
411	#define X86_CPUID_FEATURE_EDX_TM RT_BIT(29)
412	/** Bit 31 - PBE - Pending Break Enabled. */
413	#define X86_CPUID_FEATURE_EDX_PBE RT_BIT(31)
414	/** @} */
415
416
417	/** @name CPUID AMD Feature information.
418	* CPUID query with EAX=0x80000001.
419	* @{
420	*/
421	/** Bit 0 - FPU - x87 FPU on Chip. */
422	#define X86_CPUID_AMD_FEATURE_EDX_FPU RT_BIT(0)
423	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
424	#define X86_CPUID_AMD_FEATURE_EDX_VME RT_BIT(1)
425	/** Bit 2 - DE - Debugging extensions. */
426	#define X86_CPUID_AMD_FEATURE_EDX_DE RT_BIT(2)
427	/** Bit 3 - PSE - Page Size Extension. */
428	#define X86_CPUID_AMD_FEATURE_EDX_PSE RT_BIT(3)
429	/** Bit 4 - TSC - Time Stamp Counter. */
430	#define X86_CPUID_AMD_FEATURE_EDX_TSC RT_BIT(4)
431	/** Bit 5 - MSR - K86 Model Specific Registers RDMSR and WRMSR Instructions. */
432	#define X86_CPUID_AMD_FEATURE_EDX_MSR RT_BIT(5)
433	/** Bit 6 - PAE - Physical Address Extension. */
434	#define X86_CPUID_AMD_FEATURE_EDX_PAE RT_BIT(6)
435	/** Bit 7 - MCE - Machine Check Exception. */
436	#define X86_CPUID_AMD_FEATURE_EDX_MCE RT_BIT(7)
437	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
438	#define X86_CPUID_AMD_FEATURE_EDX_CX8 RT_BIT(8)
439	/** Bit 9 - APIC - APIC On-Chip. */
440	#define X86_CPUID_AMD_FEATURE_EDX_APIC RT_BIT(9)
441	/** Bit 11 - SEP - AMD SYSCALL and SYSRET. */
442	#define X86_CPUID_AMD_FEATURE_EDX_SEP RT_BIT(11)
443	/** Bit 12 - MTRR - Memory Type Range Registers. */
444	#define X86_CPUID_AMD_FEATURE_EDX_MTRR RT_BIT(12)
445	/** Bit 13 - PGE - PTE Global Bit. */
446	#define X86_CPUID_AMD_FEATURE_EDX_PGE RT_BIT(13)
447	/** Bit 14 - MCA - Machine Check Architecture. */
448	#define X86_CPUID_AMD_FEATURE_EDX_MCA RT_BIT(14)
449	/** Bit 15 - CMOV - Conditional Move Instructions. */
450	#define X86_CPUID_AMD_FEATURE_EDX_CMOV RT_BIT(15)
451	/** Bit 16 - PAT - Page Attribute Table. */
452	#define X86_CPUID_AMD_FEATURE_EDX_PAT RT_BIT(16)
453	/** Bit 17 - PSE-36 - 36-bit Page Size Extention. */
454	#define X86_CPUID_AMD_FEATURE_EDX_PSE36 RT_BIT(17)
455	/** Bit 20 - NX - AMD No-Execute Page Protection. */
456	#define X86_CPUID_AMD_FEATURE_EDX_NX RT_BIT(20)
457	/** Bit 22 - AXMMX - AMD Extensions to MMX Instructions. */
458	#define X86_CPUID_AMD_FEATURE_EDX_AXMMX RT_BIT(22)
459	/** Bit 23 - MMX - Intel MMX Technology. */
460	#define X86_CPUID_AMD_FEATURE_EDX_MMX RT_BIT(23)
461	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
462	#define X86_CPUID_AMD_FEATURE_EDX_FXSR RT_BIT(24)
463	/** Bit 25 - FFXSR - AMD fast FXSAVE and FXRSTOR Instructions. */
464	#define X86_CPUID_AMD_FEATURE_EDX_FFXSR RT_BIT(25)
465	/** Bit 26 - PAGE1GB - AMD 1GB large page support. */
466	#define X86_CPUID_AMD_FEATURE_EDX_PAGE1GB RT_BIT(26)
467	/** Bit 27 - RDTSCP - AMD RDTSCP instruction. */
468	#define X86_CPUID_AMD_FEATURE_EDX_RDTSCP RT_BIT(27)
469	/** Bit 29 - LM - AMD Long Mode. */
470	#define X86_CPUID_AMD_FEATURE_EDX_LONG_MODE RT_BIT(29)
471	/** Bit 30 - 3DNOWEXT - AMD Extensions to 3DNow. */
472	#define X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX RT_BIT(30)
473	/** Bit 31 - 3DNOW - AMD 3DNow. */
474	#define X86_CPUID_AMD_FEATURE_EDX_3DNOW RT_BIT(31)
475
476	/** Bit 0 - LAHF/SAHF - AMD LAHF and SAHF in 64-bit mode. */
477	#define X86_CPUID_AMD_FEATURE_ECX_LAHF_SAHF RT_BIT(0)
478	/** Bit 1 - CMPL - Core multi-processing legacy mode. */
479	#define X86_CPUID_AMD_FEATURE_ECX_CMPL RT_BIT(1)
480	/** Bit 2 - SVM - AMD VM extensions. */
481	#define X86_CPUID_AMD_FEATURE_ECX_SVM RT_BIT(2)
482	/** Bit 3 - EXTAPIC - AMD extended APIC registers starting at 0x400. */
483	#define X86_CPUID_AMD_FEATURE_ECX_EXT_APIC RT_BIT(3)
484	/** Bit 4 - CR8L - AMD LOCK MOV CR0 means MOV CR8. */
485	#define X86_CPUID_AMD_FEATURE_ECX_CR8L RT_BIT(4)
486	/** Bit 5 - ABM - AMD Advanced bit manipulation. LZCNT instruction support. */
487	#define X86_CPUID_AMD_FEATURE_ECX_ABM RT_BIT(5)
488	/** Bit 6 - SSE4A - AMD EXTRQ, INSERTQ, MOVNTSS, and MOVNTSD instruction support. */
489	#define X86_CPUID_AMD_FEATURE_ECX_SSE4A RT_BIT(6)
490	/** Bit 7 - MISALIGNSSE - AMD Misaligned SSE mode. */
491	#define X86_CPUID_AMD_FEATURE_ECX_MISALNSSE RT_BIT(7)
492	/** Bit 8 - 3DNOWPRF - AMD PREFETCH and PREFETCHW instruction support. */
493	#define X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF RT_BIT(8)
494	/** Bit 9 - OSVW - AMD OS visible workaround. */
495	#define X86_CPUID_AMD_FEATURE_ECX_OSVW RT_BIT(9)
496	/** Bit 12 - SKINIT - AMD SKINIT: SKINIT, STGI, and DEV support. */
497	#define X86_CPUID_AMD_FEATURE_ECX_SKINIT RT_BIT(12)
498	/** Bit 13 - WDT - AMD Watchdog timer support. */
499	#define X86_CPUID_AMD_FEATURE_ECX_WDT RT_BIT(13)
500
501	/** @} */
502
503
504	/** @name CPUID AMD Feature information.
505	* CPUID query with EAX=0x80000007.
506	* @{
507	*/
508	/** Bit 0 - TS - Temperature Sensor. */
509	#define X86_CPUID_AMD_ADVPOWER_EDX_TS RT_BIT(0)
510	/** Bit 1 - FID - Frequency ID Control. */
511	#define X86_CPUID_AMD_ADVPOWER_EDX_FID RT_BIT(1)
512	/** Bit 2 - VID - Voltage ID Control. */
513	#define X86_CPUID_AMD_ADVPOWER_EDX_VID RT_BIT(2)
514	/** Bit 3 - TTP - THERMTRIP. */
515	#define X86_CPUID_AMD_ADVPOWER_EDX_TTP RT_BIT(3)
516	/** Bit 4 - TM - Hardware Thermal Control. */
517	#define X86_CPUID_AMD_ADVPOWER_EDX_TM RT_BIT(4)
518	/** Bit 5 - STC - Software Thermal Control. */
519	#define X86_CPUID_AMD_ADVPOWER_EDX_STC RT_BIT(5)
520	/** Bit 6 - MC - 100 Mhz Multiplier Control. */
521	#define X86_CPUID_AMD_ADVPOWER_EDX_MC RT_BIT(6)
522	/** Bit 7 - HWPSTATE - Hardware P-State Control. */
523	#define X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE RT_BIT(7)
524	/** Bit 8 - TSCINVAR - TSC Invariant. */
525	#define X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR RT_BIT(8)
526	/** @} */
527
528
529	/** @name CR0
530	* @{ */
531	/** Bit 0 - PE - Protection Enabled */
532	#define X86_CR0_PE RT_BIT(0)
533	#define X86_CR0_PROTECTION_ENABLE RT_BIT(0)
534	/** Bit 1 - MP - Monitor Coprocessor */
535	#define X86_CR0_MP RT_BIT(1)
536	#define X86_CR0_MONITOR_COPROCESSOR RT_BIT(1)
537	/** Bit 2 - EM - Emulation. */
538	#define X86_CR0_EM RT_BIT(2)
539	#define X86_CR0_EMULATE_FPU RT_BIT(2)
540	/** Bit 3 - TS - Task Switch. */
541	#define X86_CR0_TS RT_BIT(3)
542	#define X86_CR0_TASK_SWITCH RT_BIT(3)
543	/** Bit 4 - ET - Extension flag. ('hardcoded' to 1) */
544	#define X86_CR0_ET RT_BIT(4)
545	#define X86_CR0_EXTENSION_TYPE RT_BIT(4)
546	/** Bit 5 - NE - Numeric error. */
547	#define X86_CR0_NE RT_BIT(5)
548	#define X86_CR0_NUMERIC_ERROR RT_BIT(5)
549	/** Bit 16 - WP - Write Protect. */
550	#define X86_CR0_WP RT_BIT(16)
551	#define X86_CR0_WRITE_PROTECT RT_BIT(16)
552	/** Bit 18 - AM - Alignment Mask. */
553	#define X86_CR0_AM RT_BIT(18)
554	#define X86_CR0_ALIGMENT_MASK RT_BIT(18)
555	/** Bit 29 - NW - Not Write-though. */
556	#define X86_CR0_NW RT_BIT(29)
557	#define X86_CR0_NOT_WRITE_THROUGH RT_BIT(29)
558	/** Bit 30 - WP - Cache Disable. */
559	#define X86_CR0_CD RT_BIT(30)
560	#define X86_CR0_CACHE_DISABLE RT_BIT(30)
561	/** Bit 31 - PG - Paging. */
562	#define X86_CR0_PG RT_BIT(31)
563	#define X86_CR0_PAGING RT_BIT(31)
564	/** @} */
565
566
567	/** @name CR3
568	* @{ */
569	/** Bit 3 - PWT - Page-level Writes Transparent. */
570	#define X86_CR3_PWT RT_BIT(3)
571	/** Bit 4 - PCD - Page-level Cache Disable. */
572	#define X86_CR3_PCD RT_BIT(4)
573	/** Bits 12-31 - - Page directory page number. */
574	#define X86_CR3_PAGE_MASK (0xfffff000)
575	/** Bits 5-31 - - PAE Page directory page number. */
576	#define X86_CR3_PAE_PAGE_MASK (0xffffffe0)
577	/** Bits 12-51 - - AMD64 Page directory page number. */
578	#define X86_CR3_AMD64_PAGE_MASK UINT64_C(0x000ffffffffff000)
579	/** @} */
580
581
582	/** @name CR4
583	* @{ */
584	/** Bit 0 - VME - Virtual-8086 Mode Extensions. */
585	#define X86_CR4_VME RT_BIT(0)
586	/** Bit 1 - PVI - Protected-Mode Virtual Interrupts. */
587	#define X86_CR4_PVI RT_BIT(1)
588	/** Bit 2 - TSD - Time Stamp Disable. */
589	#define X86_CR4_TSD RT_BIT(2)
590	/** Bit 3 - DE - Debugging Extensions. */
591	#define X86_CR4_DE RT_BIT(3)
592	/** Bit 4 - PSE - Page Size Extension. */
593	#define X86_CR4_PSE RT_BIT(4)
594	/** Bit 5 - PAE - Physical Address Extension. */
595	#define X86_CR4_PAE RT_BIT(5)
596	/** Bit 6 - MCE - Machine-Check Enable. */
597	#define X86_CR4_MCE RT_BIT(6)
598	/** Bit 7 - PGE - Page Global Enable. */
599	#define X86_CR4_PGE RT_BIT(7)
600	/** Bit 8 - PCE - Performance-Monitoring Counter Enable. */
601	#define X86_CR4_PCE RT_BIT(8)
602	/** Bit 9 - OSFSXR - Operating System Support for FXSAVE and FXRSTORE instruction. */
603	#define X86_CR4_OSFSXR RT_BIT(9)
604	/** Bit 10 - OSXMMEEXCPT - Operating System Support for Unmasked SIMD Floating-Point Exceptions. */
605	#define X86_CR4_OSXMMEEXCPT RT_BIT(10)
606	/** Bit 13 - VMXE - VMX mode is enabled. */
607	#define X86_CR4_VMXE RT_BIT(13)
608	/** @} */
609
610
611	/** @name DR6
612	* @{ */
613	/** Bit 0 - B0 - Breakpoint 0 condition detected. */
614	#define X86_DR6_B0 RT_BIT(0)
615	/** Bit 1 - B1 - Breakpoint 1 condition detected. */
616	#define X86_DR6_B1 RT_BIT(1)
617	/** Bit 2 - B2 - Breakpoint 2 condition detected. */
618	#define X86_DR6_B2 RT_BIT(2)
619	/** Bit 3 - B3 - Breakpoint 3 condition detected. */
620	#define X86_DR6_B3 RT_BIT(3)
621	/** Bit 13 - BD - Debug register access detected. Corresponds to the X86_DR7_GD bit. */
622	#define X86_DR6_BD RT_BIT(13)
623	/** Bit 14 - BS - Single step */
624	#define X86_DR6_BS RT_BIT(14)
625	/** Bit 15 - BT - Task switch. (TSS T bit.) */
626	#define X86_DR6_BT RT_BIT(15)
627	/** @} */
628
629
630	/** @name DR7
631	* @{ */
632	/** Bit 0 - L0 - Local breakpoint enable. Cleared on task switch. */
633	#define X86_DR7_L0 RT_BIT(0)
634	/** Bit 1 - G0 - Global breakpoint enable. Not cleared on task switch. */
635	#define X86_DR7_G0 RT_BIT(1)
636	/** Bit 2 - L1 - Local breakpoint enable. Cleared on task switch. */
637	#define X86_DR7_L1 RT_BIT(2)
638	/** Bit 3 - G1 - Global breakpoint enable. Not cleared on task switch. */
639	#define X86_DR7_G1 RT_BIT(3)
640	/** Bit 4 - L2 - Local breakpoint enable. Cleared on task switch. */
641	#define X86_DR7_L2 RT_BIT(4)
642	/** Bit 5 - G2 - Global breakpoint enable. Not cleared on task switch. */
643	#define X86_DR7_G2 RT_BIT(5)
644	/** Bit 6 - L3 - Local breakpoint enable. Cleared on task switch. */
645	#define X86_DR7_L3 RT_BIT(6)
646	/** Bit 7 - G3 - Global breakpoint enable. Not cleared on task switch. */
647	#define X86_DR7_G3 RT_BIT(7)
648	/** Bit 8 - LE - Local breakpoint exact. (Not supported (read ignored) by P6 and later.) */
649	#define X86_DR7_LE RT_BIT(8)
650	/** Bit 9 - GE - Local breakpoint exact. (Not supported (read ignored) by P6 and later.) */
651	#define X86_DR7_GE RT_BIT(9)
652
653	/** Bit 13 - GD - General detect enable. Enables emulators to get exceptions when
654	* any DR register is accessed. */
655	#define X86_DR7_GD RT_BIT(13)
656	/** Bit 16 & 17 - R/W0 - Read write field 0. Values X86_DR7_RW_. /
657	#define X86_DR7_RW0_MASK (3 << 16)
658	/** Bit 18 & 19 - LEN0 - Length field 0. Values X86_DR7_LEN_. /
659	#define X86_DR7_LEN0_MASK (3 << 18)
660	/** Bit 20 & 21 - R/W1 - Read write field 0. Values X86_DR7_RW_. /
661	#define X86_DR7_RW1_MASK (3 << 20)
662	/** Bit 22 & 23 - LEN1 - Length field 0. Values X86_DR7_LEN_. /
663	#define X86_DR7_LEN1_MASK (3 << 22)
664	/** Bit 24 & 25 - R/W2 - Read write field 0. Values X86_DR7_RW_. /
665	#define X86_DR7_RW2_MASK (3 << 24)
666	/** Bit 26 & 27 - LEN2 - Length field 0. Values X86_DR7_LEN_. /
667	#define X86_DR7_LEN2_MASK (3 << 26)
668	/** Bit 28 & 29 - R/W3 - Read write field 0. Values X86_DR7_RW_. /
669	#define X86_DR7_RW3_MASK (3 << 28)
670	/** Bit 30 & 31 - LEN3 - Length field 0. Values X86_DR7_LEN_. /
671	#define X86_DR7_LEN3_MASK (3 << 30)
672
673	/** Bits which must be 1s. */
674	#define X86_DR7_MB1_MASK (RT_BIT(10))
675
676	/** Calcs the L bit of Nth breakpoint.
677	* @param iBp The breakpoint number [0..3].
678	*/
679	#define X86_DR7_L(iBp) ( 1 << (iBp * 2) )
680
681	/** Calcs the G bit of Nth breakpoint.
682	* @param iBp The breakpoint number [0..3].
683	*/
684	#define X86_DR7_G(iBp) ( 1 << (iBp * 2 + 1) )
685
686	/** @name Read/Write values.
687	* @{ */
688	/** Break on instruction fetch only. */
689	#define X86_DR7_RW_EO 0
690	/** Break on write only. */
691	#define X86_DR7_RW_WO 1
692	/** Break on I/O read/write. This is only defined if CR4.DE is set. */
693	#define X86_DR7_RW_IO 2
694	/** Break on read or write (but not instruction fetches). */
695	#define X86_DR7_RW_RW 3
696	/** @} */
697
698	/** Shifts a X86_DR7_RW_* value to its right place.
699	* @param iBp The breakpoint number [0..3].
700	* @param fRw One of the X86_DR7_RW_* value.
701	*/
702	#define X86_DR7_RW(iBp, fRw) ( (fRw) << ((iBp) * 4 + 16) )
703
704	/** @name Length values.
705	* @{ */
706	#define X86_DR7_LEN_BYTE 0
707	#define X86_DR7_LEN_WORD 1
708	#define X86_DR7_LEN_QWORD 2 /*< AMD64 long mode only. /
709	#define X86_DR7_LEN_DWORD 3
710	/** @} */
711
712	/** Shifts a X86_DR7_LEN_* value to its right place.
713	* @param iBp The breakpoint number [0..3].
714	* @param cb One of the X86_DR7_LEN_* values.
715	*/
716	#define X86_DR7_LEN(iBp, cb) ( (cb) << ((iBp) * 4 + 18) )
717
718	/** Mask used to check if any breakpoints are enabled. */
719	#define X86_DR7_ENABLED_MASK (RT_BIT(0) \| RT_BIT(1) \| RT_BIT(2) \| RT_BIT(3) \| RT_BIT(4) \| RT_BIT(5) \| RT_BIT(6) \| RT_BIT(7))
720
721	/** @} */
722
723
724	/** @name Machine Specific Registers
725	* @{
726	*/
727
728	/** Time Stamp Counter. */
729	#define MSR_IA32_TSC 0x10
730
731	#ifndef MSR_IA32_APICBASE /* qemu cpu.h klugde */
732	#define MSR_IA32_APICBASE 0x1b
733	#endif
734
735	/** CPU Feature control. */
736	#define MSR_IA32_FEATURE_CONTROL 0x3A
737	#define MSR_IA32_FEATURE_CONTROL_LOCK RT_BIT(0)
738	#define MSR_IA32_FEATURE_CONTROL_VMXON RT_BIT(2)
739
740	/** MTRR Capabilities. */
741	#define MSR_IA32_MTRR_CAP 0xFE
742
743
744	#ifndef MSR_IA32_SYSENTER_CS /* qemu cpu.h klugde */
745	/** SYSENTER_CS - the R0 CS, indirectly giving R0 SS, R3 CS and R3 DS.
746	* R0 SS == CS + 8
747	* R3 CS == CS + 16
748	* R3 SS == CS + 24
749	*/
750	#define MSR_IA32_SYSENTER_CS 0x174
751	/** SYSENTER_ESP - the R0 ESP. */
752	#define MSR_IA32_SYSENTER_ESP 0x175
753	/** SYSENTER_EIP - the R0 EIP. */
754	#define MSR_IA32_SYSENTER_EIP 0x176
755	#endif
756
757	/** Machine Check Global Capabilities Register. */
758	#define MSR_IA32_MCP_CAP 0x179
759	/** Machine Check Global Status Register. */
760	#define MSR_IA32_MCP_STATUS 0x17A
761	/** Machine Check Global Control Register. */
762	#define MSR_IA32_MCP_CTRL 0x17B
763
764	/* Page Attribute Table. */
765	#define MSR_IA32_CR_PAT 0x277
766
767	/** MTRR Default Range. */
768	#define MSR_IA32_MTRR_DEF_TYPE 0x2FF
769
770	/** Basic VMX information. */
771	#define MSR_IA32_VMX_BASIC_INFO 0x480
772	/** Allowed settings for pin-based VM execution controls */
773	#define MSR_IA32_VMX_PINBASED_CTLS 0x481
774	/** Allowed settings for proc-based VM execution controls */
775	#define MSR_IA32_VMX_PROCBASED_CTLS 0x482
776	/** Allowed settings for the VMX exit controls. */
777	#define MSR_IA32_VMX_EXIT_CTLS 0x483
778	/** Allowed settings for the VMX entry controls. */
779	#define MSR_IA32_VMX_ENTRY_CTLS 0x484
780	/** Misc VMX info. */
781	#define MSR_IA32_VMX_MISC 0x485
782	/** Fixed cleared bits in CR0. */
783	#define MSR_IA32_VMX_CR0_FIXED0 0x486
784	/** Fixed set bits in CR0. */
785	#define MSR_IA32_VMX_CR0_FIXED1 0x487
786	/** Fixed cleared bits in CR4. */
787	#define MSR_IA32_VMX_CR4_FIXED0 0x488
788	/** Fixed set bits in CR4. */
789	#define MSR_IA32_VMX_CR4_FIXED1 0x489
790	/** Information for enumerating fields in the VMCS. */
791	#define MSR_IA32_VMX_VMCS_ENUM 0x48A
792
793
794	/** K6 EFER - Extended Feature Enable Register. */
795	#define MSR_K6_EFER 0xc0000080
796	/** @todo document EFER */
797	/** Bit 0 - SCE - System call extensions (SYSCALL / SYSRET). (R/W) */
798	#define MSR_K6_EFER_SCE RT_BIT(0)
799	/** Bit 8 - LME - Long mode enabled. (R/W) */
800	#define MSR_K6_EFER_LME RT_BIT(8)
801	/** Bit 10 - LMA - Long mode active. (R) */
802	#define MSR_K6_EFER_LMA RT_BIT(10)
803	/** Bit 11 - NXE - No-Execute Page Protection Enabled. (R/W) */
804	#define MSR_K6_EFER_NXE RT_BIT(11)
805	/** Bit 12 - SVME - Secure VM Extension Enabled. (R/W) */
806	#define MSR_K6_EFER_SVME RT_BIT(12)
807	/** Bit 13 - LMSLE - Long Mode Segment Limit Enable. (R/W?) */
808	#define MSR_K6_EFER_LMSLE RT_BIT(13)
809	/** Bit 14 - FFXSR - Fast FXSAVE / FXRSTOR (skip XMM). (R/W) /
810	#define MSR_K6_EFER_FFXSR RT_BIT(14)
811	/** K6 STAR - SYSCALL/RET targets. */
812	#define MSR_K6_STAR 0xc0000081
813	/** Shift value for getting the SYSRET CS and SS value. */
814	#define MSR_K6_STAR_SYSRET_CS_SS_SHIFT 48
815	/** Shift value for getting the SYSCALL CS and SS value. */
816	#define MSR_K6_STAR_SYSCALL_CS_SS_SHIFT 32
817	/** Selector mask for use after shifting. */
818	#define MSR_K6_STAR_SEL_MASK 0xffff
819	/** The mask which give the SYSCALL EIP. */
820	#define MSR_K6_STAR_SYSCALL_EIP_MASK 0xffffffff
821	/** K6 WHCR - Write Handling Control Register. */
822	#define MSR_K6_WHCR 0xc0000082
823	/** K6 UWCCR - UC/WC Cacheability Control Register. */
824	#define MSR_K6_UWCCR 0xc0000085
825	/** K6 PSOR - Processor State Observability Register. */
826	#define MSR_K6_PSOR 0xc0000087
827	/** K6 PFIR - Page Flush/Invalidate Register. */
828	#define MSR_K6_PFIR 0xc0000088
829
830	#define MSR_K7_EVNTSEL0 0xc0010000
831	#define MSR_K7_EVNTSEL1 0xc0010001
832	#define MSR_K7_EVNTSEL2 0xc0010002
833	#define MSR_K7_EVNTSEL3 0xc0010003
834	#define MSR_K7_PERFCTR0 0xc0010004
835	#define MSR_K7_PERFCTR1 0xc0010005
836	#define MSR_K7_PERFCTR2 0xc0010006
837	#define MSR_K7_PERFCTR3 0xc0010007
838
839	/** K8 LSTAR - Long mode SYSCALL target (RIP). */
840	#define MSR_K8_LSTAR 0xc0000082
841	/** K8 CSTAR - Compatibility mode SYSCALL target (RIP). */
842	#define MSR_K8_CSTAR 0xc0000083
843	/** K8 SF_MASK - SYSCALL flag mask. (aka SFMASK) */
844	#define MSR_K8_SF_MASK 0xc0000084
845	/** K8 FS.base - The 64-bit base FS register. */
846	#define MSR_K8_FS_BASE 0xc0000100
847	/** K8 GS.base - The 64-bit base GS register. */
848	#define MSR_K8_GS_BASE 0xc0000101
849	/** K8 KernelGSbase - Used with SWAPGS. */
850	#define MSR_K8_KERNEL_GS_BASE 0xc0000102
851	#define MSR_K8_TSC_AUX 0xc0000103
852	#define MSR_K8_SYSCFG 0xc0010010
853	#define MSR_K8_HWCR 0xc0010015
854	#define MSR_K8_IORRBASE0 0xc0010016
855	#define MSR_K8_IORRMASK0 0xc0010017
856	#define MSR_K8_IORRBASE1 0xc0010018
857	#define MSR_K8_IORRMASK1 0xc0010019
858	#define MSR_K8_TOP_MEM1 0xc001001a
859	#define MSR_K8_TOP_MEM2 0xc001001d
860	#define MSR_K8_VM_CR 0xc0010114
861	#define MSR_K8_VM_CR_SVM_DISABLE RT_BIT(4)
862
863	#define MSR_K8_IGNNE 0xc0010115
864	#define MSR_K8_SMM_CTL 0xc0010116
865	/** SVM - VM_HSAVE_PA - Physical address for saving and restoring
866	* host state during world switch.
867	*/
868	#define MSR_K8_VM_HSAVE_PA 0xc0010117
869
870	/** @} */
871
872
873	/** @name Page Table / Directory / Directory Pointers / L4.
874	* @{
875	*/
876
877	/** Page table/directory entry as an unsigned integer. */
878	typedef uint32_t X86PGUINT;
879	/** Pointer to a page table/directory table entry as an unsigned integer. */
880	typedef X86PGUINT *PX86PGUINT;
881
882	/** Number of entries in a 32-bit PT/PD. */
883	#define X86_PG_ENTRIES 1024
884
885
886	/** PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
887	typedef uint64_t X86PGPAEUINT;
888	/** Pointer to a PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
889	typedef X86PGPAEUINT *PX86PGPAEUINT;
890
891	/** Number of entries in a PAE PT/PD. */
892	#define X86_PG_PAE_ENTRIES 512
893	/** Number of entries in a PAE PDPT. */
894	#define X86_PG_PAE_PDPE_ENTRIES 4
895
896	/** Number of entries in an AMD64 PT/PD/PDPT/L4/L5. */
897	#define X86_PG_AMD64_ENTRIES X86_PG_PAE_ENTRIES
898	/** Number of entries in an AMD64 PDPT.
899	* Just for complementing X86_PG_PAE_PDPE_ENTRIES, using X86_PG_AMD64_ENTRIES for this is fine too. */
900	#define X86_PG_AMD64_PDPE_ENTRIES X86_PG_AMD64_ENTRIES
901
902	/** The size of a 4KB page. */
903	#define X86_PAGE_4K_SIZE _4K
904	/** The page shift of a 4KB page. */
905	#define X86_PAGE_4K_SHIFT 12
906	/** The 4KB page offset mask. */
907	#define X86_PAGE_4K_OFFSET_MASK 0xfff
908	/** The 4KB page base mask for virtual addresses. */
909	#define X86_PAGE_4K_BASE_MASK 0xfffffffffffff000ULL
910	/** The 4KB page base mask for virtual addresses - 32bit version. */
911	#define X86_PAGE_4K_BASE_MASK_32 0xfffff000U
912
913	/** The size of a 2MB page. */
914	#define X86_PAGE_2M_SIZE _2M
915	/** The page shift of a 2MB page. */
916	#define X86_PAGE_2M_SHIFT 21
917	/** The 2MB page offset mask. */
918	#define X86_PAGE_2M_OFFSET_MASK 0x001fffff
919	/** The 2MB page base mask for virtual addresses. */
920	#define X86_PAGE_2M_BASE_MASK 0xffffffffffe00000ULL
921	/** The 2MB page base mask for virtual addresses - 32bit version. */
922	#define X86_PAGE_2M_BASE_MASK_32 0xffe00000U
923
924	/** The size of a 4MB page. */
925	#define X86_PAGE_4M_SIZE _4M
926	/** The page shift of a 4MB page. */
927	#define X86_PAGE_4M_SHIFT 22
928	/** The 4MB page offset mask. */
929	#define X86_PAGE_4M_OFFSET_MASK 0x003fffff
930	/** The 4MB page base mask for virtual addresses. */
931	#define X86_PAGE_4M_BASE_MASK 0xffffffffffc00000ULL
932	/** The 4MB page base mask for virtual addresses - 32bit version. */
933	#define X86_PAGE_4M_BASE_MASK_32 0xffc00000U
934
935
936
937	/** @name Page Table Entry
938	* @{
939	*/
940	/** Bit 0 - P - Present bit. */
941	#define X86_PTE_P RT_BIT(0)
942	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
943	#define X86_PTE_RW RT_BIT(1)
944	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
945	#define X86_PTE_US RT_BIT(2)
946	/** Bit 3 - PWT - Page level write thru bit. */
947	#define X86_PTE_PWT RT_BIT(3)
948	/** Bit 4 - PCD - Page level cache disable bit. */
949	#define X86_PTE_PCD RT_BIT(4)
950	/** Bit 5 - A - Access bit. */
951	#define X86_PTE_A RT_BIT(5)
952	/** Bit 6 - D - Dirty bit. */
953	#define X86_PTE_D RT_BIT(6)
954	/** Bit 7 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
955	#define X86_PTE_PAT RT_BIT(7)
956	/** Bit 8 - G - Global flag. */
957	#define X86_PTE_G RT_BIT(8)
958	/** Bits 9-11 - - Available for use to system software. */
959	#define X86_PTE_AVL_MASK (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
960	/** Bits 12-31 - - Physical Page number of the next level. */
961	#define X86_PTE_PG_MASK ( 0xfffff000 )
962
963	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
964	#if 1 /* we're using this internally and have to mask of the top 16-bit. */
965	#define X86_PTE_PAE_PG_MASK ( 0x0000fffffffff000ULL )
966	/** @todo Get rid of the above hack; makes code unreadable. */
967	#define X86_PTE_PAE_PG_MASK_FULL ( 0x000ffffffffff000ULL )
968	#else
969	#define X86_PTE_PAE_PG_MASK ( 0x000ffffffffff000ULL )
970	#endif
971	/** Bits 63 - NX - PAE - No execution flag. */
972	#define X86_PTE_PAE_NX RT_BIT_64(63)
973
974	/**
975	* Page table entry.
976	*/
977	typedef struct X86PTEBITS
978	{
979	/** Flags whether(=1) or not the page is present. */
980	unsigned u1Present : 1;
981	/** Read(=0) / Write(=1) flag. */
982	unsigned u1Write : 1;
983	/** User(=1) / Supervisor (=0) flag. */
984	unsigned u1User : 1;
985	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
986	unsigned u1WriteThru : 1;
987	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
988	unsigned u1CacheDisable : 1;
989	/** Accessed flag.
990	* Indicates that the page have been read or written to. */
991	unsigned u1Accessed : 1;
992	/** Dirty flag.
993	* Indicates that the page have been written to. */
994	unsigned u1Dirty : 1;
995	/** Reserved / If PAT enabled, bit 2 of the index. */
996	unsigned u1PAT : 1;
997	/** Global flag. (Ignored in all but final level.) */
998	unsigned u1Global : 1;
999	/** Available for use to system software. */
1000	unsigned u3Available : 3;
1001	/** Physical Page number of the next level. */
1002	unsigned u20PageNo : 20;
1003	} X86PTEBITS;
1004	/** Pointer to a page table entry. */
1005	typedef X86PTEBITS *PX86PTEBITS;
1006	/** Pointer to a const page table entry. */
1007	typedef const X86PTEBITS *PCX86PTEBITS;
1008
1009	/**
1010	* Page table entry.
1011	*/
1012	typedef union X86PTE
1013	{
1014	/** Bit field view. */
1015	X86PTEBITS n;
1016	/** Unsigned integer view */
1017	X86PGUINT u;
1018	/** 32-bit view. */
1019	uint32_t au32[1];
1020	/** 16-bit view. */
1021	uint16_t au16[2];
1022	/** 8-bit view. */
1023	uint8_t au8[4];
1024	} X86PTE;
1025	/** Pointer to a page table entry. */
1026	typedef X86PTE *PX86PTE;
1027	/** Pointer to a const page table entry. */
1028	typedef const X86PTE *PCX86PTE;
1029
1030
1031	/**
1032	* PAE page table entry.
1033	*/
1034	typedef struct X86PTEPAEBITS
1035	{
1036	/** Flags whether(=1) or not the page is present. */
1037	uint32_t u1Present : 1;
1038	/** Read(=0) / Write(=1) flag. */
1039	uint32_t u1Write : 1;
1040	/** User(=1) / Supervisor(=0) flag. */
1041	uint32_t u1User : 1;
1042	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1043	uint32_t u1WriteThru : 1;
1044	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1045	uint32_t u1CacheDisable : 1;
1046	/** Accessed flag.
1047	* Indicates that the page have been read or written to. */
1048	uint32_t u1Accessed : 1;
1049	/** Dirty flag.
1050	* Indicates that the page have been written to. */
1051	uint32_t u1Dirty : 1;
1052	/** Reserved / If PAT enabled, bit 2 of the index. */
1053	uint32_t u1PAT : 1;
1054	/** Global flag. (Ignored in all but final level.) */
1055	uint32_t u1Global : 1;
1056	/** Available for use to system software. */
1057	uint32_t u3Available : 3;
1058	/** Physical Page number of the next level - Low Part. Don't use this. */
1059	uint32_t u20PageNoLow : 20;
1060	/** Physical Page number of the next level - High Part. Don't use this. */
1061	uint32_t u20PageNoHigh : 20;
1062	/** MBZ bits */
1063	uint32_t u11Reserved : 11;
1064	/** No Execute flag. */
1065	uint32_t u1NoExecute : 1;
1066	} X86PTEPAEBITS;
1067	/** Pointer to a page table entry. */
1068	typedef X86PTEPAEBITS *PX86PTEPAEBITS;
1069	/** Pointer to a page table entry. */
1070	typedef const X86PTEPAEBITS *PCX86PTEPAEBITS;
1071
1072	/**
1073	* PAE Page table entry.
1074	*/
1075	typedef union X86PTEPAE
1076	{
1077	/** Bit field view. */
1078	X86PTEPAEBITS n;
1079	/** Unsigned integer view */
1080	X86PGPAEUINT u;
1081	/** 32-bit view. */
1082	uint32_t au32[2];
1083	/** 16-bit view. */
1084	uint16_t au16[4];
1085	/** 8-bit view. */
1086	uint8_t au8[8];
1087	} X86PTEPAE;
1088	/** Pointer to a PAE page table entry. */
1089	typedef X86PTEPAE *PX86PTEPAE;
1090	/** Pointer to a const PAE page table entry. */
1091	typedef const X86PTEPAE *PCX86PTEPAE;
1092	/** @} */
1093
1094	/**
1095	* Page table.
1096	*/
1097	typedef struct X86PT
1098	{
1099	/** PTE Array. */
1100	X86PTE a[X86_PG_ENTRIES];
1101	} X86PT;
1102	/** Pointer to a page table. */
1103	typedef X86PT *PX86PT;
1104	/** Pointer to a const page table. */
1105	typedef const X86PT *PCX86PT;
1106
1107	/** The page shift to get the PT index. */
1108	#define X86_PT_SHIFT 12
1109	/** The PT index mask (apply to a shifted page address). */
1110	#define X86_PT_MASK 0x3ff
1111
1112
1113	/**
1114	* Page directory.
1115	*/
1116	typedef struct X86PTPAE
1117	{
1118	/** PTE Array. */
1119	X86PTEPAE a[X86_PG_PAE_ENTRIES];
1120	} X86PTPAE;
1121	/** Pointer to a page table. */
1122	typedef X86PTPAE *PX86PTPAE;
1123	/** Pointer to a const page table. */
1124	typedef const X86PTPAE *PCX86PTPAE;
1125
1126	/** The page shift to get the PA PTE index. */
1127	#define X86_PT_PAE_SHIFT 12
1128	/** The PAE PT index mask (apply to a shifted page address). */
1129	#define X86_PT_PAE_MASK 0x1ff
1130
1131
1132	/** @name 4KB Page Directory Entry
1133	* @{
1134	*/
1135	/** Bit 0 - P - Present bit. */
1136	#define X86_PDE_P RT_BIT(0)
1137	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1138	#define X86_PDE_RW RT_BIT(1)
1139	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1140	#define X86_PDE_US RT_BIT(2)
1141	/** Bit 3 - PWT - Page level write thru bit. */
1142	#define X86_PDE_PWT RT_BIT(3)
1143	/** Bit 4 - PCD - Page level cache disable bit. */
1144	#define X86_PDE_PCD RT_BIT(4)
1145	/** Bit 5 - A - Access bit. */
1146	#define X86_PDE_A RT_BIT(5)
1147	/** Bit 7 - PS - Page size attribute.
1148	* Clear mean 4KB pages, set means large pages (2/4MB). */
1149	#define X86_PDE_PS RT_BIT(7)
1150	/** Bits 9-11 - - Available for use to system software. */
1151	#define X86_PDE_AVL_MASK (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
1152	/** Bits 12-31 - - Physical Page number of the next level. */
1153	#define X86_PDE_PG_MASK ( 0xfffff000 )
1154
1155	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1156	#if 1 /* we're using this internally and have to mask of the top 16-bit. */
1157	/* Note: This is kind of dangerous if the guest uses these bits (legally or illegally);
1158	* we partly or that part into shadow page table entries. Will be corrected
1159	* soon.
1160	*/
1161	#define X86_PDE_PAE_PG_MASK ( 0x0000fffffffff000ULL )
1162	#define X86_PDE_PAE_PG_MASK_FULL ( 0x000ffffffffff000ULL )
1163	#else
1164	#define X86_PDE_PAE_PG_MASK ( 0x000ffffffffff000ULL )
1165	#endif
1166	/** Bits 63 - NX - PAE - No execution flag. */
1167	#define X86_PDE_PAE_NX RT_BIT_64(63)
1168
1169	/**
1170	* Page directory entry.
1171	*/
1172	typedef struct X86PDEBITS
1173	{
1174	/** Flags whether(=1) or not the page is present. */
1175	unsigned u1Present : 1;
1176	/** Read(=0) / Write(=1) flag. */
1177	unsigned u1Write : 1;
1178	/** User(=1) / Supervisor (=0) flag. */
1179	unsigned u1User : 1;
1180	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1181	unsigned u1WriteThru : 1;
1182	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1183	unsigned u1CacheDisable : 1;
1184	/** Accessed flag.
1185	* Indicates that the page have been read or written to. */
1186	unsigned u1Accessed : 1;
1187	/** Reserved / Ignored (dirty bit). */
1188	unsigned u1Reserved0 : 1;
1189	/** Size bit if PSE is enabled - in any event it's 0. */
1190	unsigned u1Size : 1;
1191	/** Reserved / Ignored (global bit). */
1192	unsigned u1Reserved1 : 1;
1193	/** Available for use to system software. */
1194	unsigned u3Available : 3;
1195	/** Physical Page number of the next level. */
1196	unsigned u20PageNo : 20;
1197	} X86PDEBITS;
1198	/** Pointer to a page directory entry. */
1199	typedef X86PDEBITS *PX86PDEBITS;
1200	/** Pointer to a const page directory entry. */
1201	typedef const X86PDEBITS *PCX86PDEBITS;
1202
1203
1204	/**
1205	* PAE page directory entry.
1206	*/
1207	typedef struct X86PDEPAEBITS
1208	{
1209	/** Flags whether(=1) or not the page is present. */
1210	uint32_t u1Present : 1;
1211	/** Read(=0) / Write(=1) flag. */
1212	uint32_t u1Write : 1;
1213	/** User(=1) / Supervisor (=0) flag. */
1214	uint32_t u1User : 1;
1215	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1216	uint32_t u1WriteThru : 1;
1217	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1218	uint32_t u1CacheDisable : 1;
1219	/** Accessed flag.
1220	* Indicates that the page have been read or written to. */
1221	uint32_t u1Accessed : 1;
1222	/** Reserved / Ignored (dirty bit). */
1223	uint32_t u1Reserved0 : 1;
1224	/** Size bit if PSE is enabled - in any event it's 0. */
1225	uint32_t u1Size : 1;
1226	/** Reserved / Ignored (global bit). / */
1227	uint32_t u1Reserved1 : 1;
1228	/** Available for use to system software. */
1229	uint32_t u3Available : 3;
1230	/** Physical Page number of the next level - Low Part. Don't use! */
1231	uint32_t u20PageNoLow : 20;
1232	/** Physical Page number of the next level - High Part. Don't use! */
1233	uint32_t u20PageNoHigh : 20;
1234	/** MBZ bits */
1235	uint32_t u11Reserved : 11;
1236	/** No Execute flag. */
1237	uint32_t u1NoExecute : 1;
1238	} X86PDEPAEBITS;
1239	/** Pointer to a page directory entry. */
1240	typedef X86PDEPAEBITS *PX86PDEPAEBITS;
1241	/** Pointer to a const page directory entry. */
1242	typedef const X86PDEPAEBITS *PCX86PDEPAEBITS;
1243
1244	/** @} */
1245
1246
1247	/** @name 2/4MB Page Directory Entry
1248	* @{
1249	*/
1250	/** Bit 0 - P - Present bit. */
1251	#define X86_PDE4M_P RT_BIT(0)
1252	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1253	#define X86_PDE4M_RW RT_BIT(1)
1254	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1255	#define X86_PDE4M_US RT_BIT(2)
1256	/** Bit 3 - PWT - Page level write thru bit. */
1257	#define X86_PDE4M_PWT RT_BIT(3)
1258	/** Bit 4 - PCD - Page level cache disable bit. */
1259	#define X86_PDE4M_PCD RT_BIT(4)
1260	/** Bit 5 - A - Access bit. */
1261	#define X86_PDE4M_A RT_BIT(5)
1262	/** Bit 6 - D - Dirty bit. */
1263	#define X86_PDE4M_D RT_BIT(6)
1264	/** Bit 7 - PS - Page size attribute. Clear mean 4KB pages, set means large pages (2/4MB). */
1265	#define X86_PDE4M_PS RT_BIT(7)
1266	/** Bit 8 - G - Global flag. */
1267	#define X86_PDE4M_G RT_BIT(8)
1268	/** Bits 9-11 - AVL - Available for use to system software. */
1269	#define X86_PDE4M_AVL (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
1270	/** Bit 12 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
1271	#define X86_PDE4M_PAT RT_BIT(12)
1272	/** Shift to get from X86_PTE_PAT to X86_PDE4M_PAT. */
1273	#define X86_PDE4M_PAT_SHIFT (12 - 7)
1274	/** Bits 22-31 - - Physical Page number. */
1275	#define X86_PDE4M_PG_MASK ( 0xffc00000 )
1276	/** Bits 13-20 - - Physical Page number high part (32-39 bits). AMD64 hack. */
1277	#define X86_PDE4M_PG_HIGH_MASK ( 0x001fe000 )
1278	/** The number of bits to the high part of the page number. */
1279	#define X86_PDE4M_PG_HIGH_SHIFT 19
1280
1281	/** Bits 21-51 - - PAE & AMD64 - Physical Page number.
1282	* (Bits 40-51 (long mode) & bits 36-51 (pae legacy) are reserved according to the Intel docs; AMD allows for more.) */
1283	#define X86_PDE2M_PAE_PG_MASK ( 0x000fffffffe00000ULL )
1284	/** Bits 63 - NX - PAE & AMD64 - No execution flag. */
1285	#define X86_PDE2M_PAE_NX X86_PDE2M_PAE_NX
1286
1287	/**
1288	* 4MB page directory entry.
1289	*/
1290	typedef struct X86PDE4MBITS
1291	{
1292	/** Flags whether(=1) or not the page is present. */
1293	unsigned u1Present : 1;
1294	/** Read(=0) / Write(=1) flag. */
1295	unsigned u1Write : 1;
1296	/** User(=1) / Supervisor (=0) flag. */
1297	unsigned u1User : 1;
1298	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1299	unsigned u1WriteThru : 1;
1300	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1301	unsigned u1CacheDisable : 1;
1302	/** Accessed flag.
1303	* Indicates that the page have been read or written to. */
1304	unsigned u1Accessed : 1;
1305	/** Dirty flag.
1306	* Indicates that the page have been written to. */
1307	unsigned u1Dirty : 1;
1308	/** Page size flag - always 1 for 4MB entries. */
1309	unsigned u1Size : 1;
1310	/** Global flag. */
1311	unsigned u1Global : 1;
1312	/** Available for use to system software. */
1313	unsigned u3Available : 3;
1314	/** Reserved / If PAT enabled, bit 2 of the index. */
1315	unsigned u1PAT : 1;
1316	/** Bits 32-39 of the page number on AMD64.
1317	* This AMD64 hack allows accessing 40bits of physical memory without PAE. */
1318	unsigned u8PageNoHigh : 8;
1319	/** Reserved. */
1320	unsigned u1Reserved : 1;
1321	/** Physical Page number of the page. */
1322	unsigned u10PageNo : 10;
1323	} X86PDE4MBITS;
1324	/** Pointer to a page table entry. */
1325	typedef X86PDE4MBITS *PX86PDE4MBITS;
1326	/** Pointer to a const page table entry. */
1327	typedef const X86PDE4MBITS *PCX86PDE4MBITS;
1328
1329
1330	/**
1331	* 2MB PAE page directory entry.
1332	*/
1333	typedef struct X86PDE2MPAEBITS
1334	{
1335	/** Flags whether(=1) or not the page is present. */
1336	uint32_t u1Present : 1;
1337	/** Read(=0) / Write(=1) flag. */
1338	uint32_t u1Write : 1;
1339	/** User(=1) / Supervisor(=0) flag. */
1340	uint32_t u1User : 1;
1341	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1342	uint32_t u1WriteThru : 1;
1343	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1344	uint32_t u1CacheDisable : 1;
1345	/** Accessed flag.
1346	* Indicates that the page have been read or written to. */
1347	uint32_t u1Accessed : 1;
1348	/** Dirty flag.
1349	* Indicates that the page have been written to. */
1350	uint32_t u1Dirty : 1;
1351	/** Page size flag - always 1 for 2MB entries. */
1352	uint32_t u1Size : 1;
1353	/** Global flag. */
1354	uint32_t u1Global : 1;
1355	/** Available for use to system software. */
1356	uint32_t u3Available : 3;
1357	/** Reserved / If PAT enabled, bit 2 of the index. */
1358	uint32_t u1PAT : 1;
1359	/** Reserved. */
1360	uint32_t u9Reserved : 9;
1361	/** Physical Page number of the next level - Low part. Don't use! */
1362	uint32_t u10PageNoLow : 10;
1363	/** Physical Page number of the next level - High part. Don't use! */
1364	uint32_t u20PageNoHigh : 20;
1365	/** MBZ bits */
1366	uint32_t u11Reserved : 11;
1367	/** No Execute flag. */
1368	uint32_t u1NoExecute : 1;
1369	} X86PDE2MPAEBITS;
1370	/** Pointer to a 4MB PAE page table entry. */
1371	typedef X86PDE2MPAEBITS *PX86PDE2MPAEBITS;
1372	/** Pointer to a 4MB PAE page table entry. */
1373	typedef const X86PDE2MPAEBITS *PCX86PDE2MPAEBITS;
1374
1375	/** @} */
1376
1377	/**
1378	* Page directory entry.
1379	*/
1380	typedef union X86PDE
1381	{
1382	/** Normal view. */
1383	X86PDEBITS n;
1384	/** 4MB view (big). */
1385	X86PDE4MBITS b;
1386	/** Unsigned integer view. */
1387	X86PGUINT u;
1388	/** 8 bit unsigned integer view. */
1389	uint8_t au8[4];
1390	/** 16 bit unsigned integer view. */
1391	uint16_t au16[2];
1392	/** 32 bit unsigned integer view. */
1393	uint32_t au32[1];
1394	} X86PDE;
1395	/** Pointer to a page directory entry. */
1396	typedef X86PDE *PX86PDE;
1397	/** Pointer to a const page directory entry. */
1398	typedef const X86PDE *PCX86PDE;
1399
1400	/**
1401	* PAE page directory entry.
1402	*/
1403	typedef union X86PDEPAE
1404	{
1405	/** Normal view. */
1406	X86PDEPAEBITS n;
1407	/** 2MB page view (big). */
1408	X86PDE2MPAEBITS b;
1409	/** Unsigned integer view. */
1410	X86PGPAEUINT u;
1411	/** 8 bit unsigned integer view. */
1412	uint8_t au8[8];
1413	/** 16 bit unsigned integer view. */
1414	uint16_t au16[4];
1415	/** 32 bit unsigned integer view. */
1416	uint32_t au32[2];
1417	} X86PDEPAE;
1418	/** Pointer to a page directory entry. */
1419	typedef X86PDEPAE *PX86PDEPAE;
1420	/** Pointer to a const page directory entry. */
1421	typedef const X86PDEPAE *PCX86PDEPAE;
1422
1423	/**
1424	* Page directory.
1425	*/
1426	typedef struct X86PD
1427	{
1428	/** PDE Array. */
1429	X86PDE a[X86_PG_ENTRIES];
1430	} X86PD;
1431	/** Pointer to a page directory. */
1432	typedef X86PD *PX86PD;
1433	/** Pointer to a const page directory. */
1434	typedef const X86PD *PCX86PD;
1435
1436	/** The page shift to get the PD index. */
1437	#define X86_PD_SHIFT 22
1438	/** The PD index mask (apply to a shifted page address). */
1439	#define X86_PD_MASK 0x3ff
1440
1441
1442	/**
1443	* PAE page directory.
1444	*/
1445	typedef struct X86PDPAE
1446	{
1447	/** PDE Array. */
1448	X86PDEPAE a[X86_PG_PAE_ENTRIES];
1449	} X86PDPAE;
1450	/** Pointer to a PAE page directory. */
1451	typedef X86PDPAE *PX86PDPAE;
1452	/** Pointer to a const PAE page directory. */
1453	typedef const X86PDPAE *PCX86PDPAE;
1454
1455	/** The page shift to get the PAE PD index. */
1456	#define X86_PD_PAE_SHIFT 21
1457	/** The PAE PD index mask (apply to a shifted page address). */
1458	#define X86_PD_PAE_MASK 0x1ff
1459
1460
1461	/** @name Page Directory Pointer Table Entry (PAE)
1462	* @{
1463	*/
1464	/** Bit 0 - P - Present bit. */
1465	#define X86_PDPE_P RT_BIT(0)
1466	/** Bit 1 - R/W - Read (clear) / Write (set) bit. Long Mode only. */
1467	#define X86_PDPE_RW RT_BIT(1)
1468	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. Long Mode only. */
1469	#define X86_PDPE_US RT_BIT(2)
1470	/** Bit 3 - PWT - Page level write thru bit. */
1471	#define X86_PDPE_PWT RT_BIT(3)
1472	/** Bit 4 - PCD - Page level cache disable bit. */
1473	#define X86_PDPE_PCD RT_BIT(4)
1474	/** Bit 5 - A - Access bit. Long Mode only. */
1475	#define X86_PDPE_A RT_BIT(5)
1476	/** Bits 9-11 - - Available for use to system software. */
1477	#define X86_PDPE_AVL_MASK (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
1478	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1479	#if 1 /* we're using this internally and have to mask of the top 16-bit. */
1480	#define X86_PDPE_PG_MASK ( 0x0000fffffffff000ULL )
1481	/** @todo Get rid of the above hack; makes code unreadable. */
1482	#define X86_PDPE_PG_MASK_FULL ( 0x000ffffffffff000ULL )
1483	#else
1484	#define X86_PDPE_PG_MASK ( 0x000ffffffffff000ULL )
1485	#endif
1486	/** Bits 63 - NX - PAE - No execution flag. Long Mode only. */
1487	#define X86_PDPE_NX RT_BIT_64(63)
1488
1489	/**
1490	* Page directory pointer table entry.
1491	*/
1492	typedef struct X86PDPEBITS
1493	{
1494	/** Flags whether(=1) or not the page is present. */
1495	uint32_t u1Present : 1;
1496	/** Chunk of reserved bits. */
1497	uint32_t u2Reserved : 2;
1498	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1499	uint32_t u1WriteThru : 1;
1500	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1501	uint32_t u1CacheDisable : 1;
1502	/** Chunk of reserved bits. */
1503	uint32_t u4Reserved : 4;
1504	/** Available for use to system software. */
1505	uint32_t u3Available : 3;
1506	/** Physical Page number of the next level - Low Part. Don't use! */
1507	uint32_t u20PageNoLow : 20;
1508	/** Physical Page number of the next level - High Part. Don't use! */
1509	uint32_t u20PageNoHigh : 20;
1510	/** MBZ bits */
1511	uint32_t u12Reserved : 12;
1512	} X86PDPEBITS;
1513	/** Pointer to a page directory pointer table entry. */
1514	typedef X86PDPEBITS *PX86PTPEBITS;
1515	/** Pointer to a const page directory pointer table entry. */
1516	typedef const X86PDPEBITS *PCX86PTPEBITS;
1517
1518	/**
1519	* Page directory pointer table entry. AMD64 version
1520	*/
1521	typedef struct X86PDPEAMD64BITS
1522	{
1523	/** Flags whether(=1) or not the page is present. */
1524	uint32_t u1Present : 1;
1525	/** Read(=0) / Write(=1) flag. */
1526	uint32_t u1Write : 1;
1527	/** User(=1) / Supervisor (=0) flag. */
1528	uint32_t u1User : 1;
1529	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1530	uint32_t u1WriteThru : 1;
1531	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1532	uint32_t u1CacheDisable : 1;
1533	/** Accessed flag.
1534	* Indicates that the page have been read or written to. */
1535	uint32_t u1Accessed : 1;
1536	/** Chunk of reserved bits. */
1537	uint32_t u3Reserved : 3;
1538	/** Available for use to system software. */
1539	uint32_t u3Available : 3;
1540	/** Physical Page number of the next level - Low Part. Don't use! */
1541	uint32_t u20PageNoLow : 20;
1542	/** Physical Page number of the next level - High Part. Don't use! */
1543	uint32_t u20PageNoHigh : 20;
1544	/** MBZ bits */
1545	uint32_t u11Reserved : 11;
1546	/** No Execute flag. */
1547	uint32_t u1NoExecute : 1;
1548	} X86PDPEAMD64BITS;
1549	/** Pointer to a page directory pointer table entry. */
1550	typedef X86PDPEAMD64BITS *PX86PDPEAMD64BITS;
1551	/** Pointer to a const page directory pointer table entry. */
1552	typedef const X86PDPEBITS *PCX86PDPEAMD64BITS;
1553
1554	/**
1555	* Page directory pointer table entry.
1556	*/
1557	typedef union X86PDPE
1558	{
1559	/** Normal view. */
1560	X86PDPEBITS n;
1561	/** AMD64 view. */
1562	X86PDPEAMD64BITS lm;
1563	/** Unsigned integer view. */
1564	X86PGPAEUINT u;
1565	/** 8 bit unsigned integer view. */
1566	uint8_t au8[8];
1567	/** 16 bit unsigned integer view. */
1568	uint16_t au16[4];
1569	/** 32 bit unsigned integer view. */
1570	uint32_t au32[2];
1571	} X86PDPE;
1572	/** Pointer to a page directory pointer table entry. */
1573	typedef X86PDPE *PX86PDPE;
1574	/** Pointer to a const page directory pointer table entry. */
1575	typedef const X86PDPE *PCX86PDPE;
1576
1577
1578	/**
1579	* Page directory pointer table.
1580	*/
1581	typedef struct X86PDPT
1582	{
1583	/** PDE Array. */
1584	X86PDPE a[X86_PG_AMD64_PDPE_ENTRIES];
1585	} X86PDPT;
1586	/** Pointer to a page directory pointer table. */
1587	typedef X86PDPT *PX86PDPT;
1588	/** Pointer to a const page directory pointer table. */
1589	typedef const X86PDPT *PCX86PDPT;
1590
1591	/** The page shift to get the PDPT index. */
1592	#define X86_PDPT_SHIFT 30
1593	/** The PDPT index mask (apply to a shifted page address). (32 bits PAE) */
1594	#define X86_PDPT_MASK_PAE 0x3
1595	/** The PDPT index mask (apply to a shifted page address). (64 bits PAE)*/
1596	#define X86_PDPT_MASK_AMD64 0x1ff
1597
1598	/** @} */
1599
1600
1601	/** @name Page Map Level-4 Entry (Long Mode PAE)
1602	* @{
1603	*/
1604	/** Bit 0 - P - Present bit. */
1605	#define X86_PML4E_P RT_BIT(0)
1606	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1607	#define X86_PML4E_RW RT_BIT(1)
1608	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1609	#define X86_PML4E_US RT_BIT(2)
1610	/** Bit 3 - PWT - Page level write thru bit. */
1611	#define X86_PML4E_PWT RT_BIT(3)
1612	/** Bit 4 - PCD - Page level cache disable bit. */
1613	#define X86_PML4E_PCD RT_BIT(4)
1614	/** Bit 5 - A - Access bit. */
1615	#define X86_PML4E_A RT_BIT(5)
1616	/** Bits 9-11 - - Available for use to system software. */
1617	#define X86_PML4E_AVL_MASK (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
1618	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1619	#if 1 /* we're using this internally and have to mask of the top 16-bit. */
1620	#define X86_PML4E_PG_MASK ( 0x0000fffffffff000ULL )
1621	#define X86_PML4E_PG_MASK_FULL ( 0x000ffffffffff000ULL )
1622	#else
1623	#define X86_PML4E_PG_MASK ( 0x000ffffffffff000ULL )
1624	#endif
1625	/** Bits 63 - NX - PAE - No execution flag. */
1626	#define X86_PML4E_NX RT_BIT_64(63)
1627
1628	/**
1629	* Page Map Level-4 Entry
1630	*/
1631	typedef struct X86PML4EBITS
1632	{
1633	/** Flags whether(=1) or not the page is present. */
1634	uint32_t u1Present : 1;
1635	/** Read(=0) / Write(=1) flag. */
1636	uint32_t u1Write : 1;
1637	/** User(=1) / Supervisor (=0) flag. */
1638	uint32_t u1User : 1;
1639	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1640	uint32_t u1WriteThru : 1;
1641	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1642	uint32_t u1CacheDisable : 1;
1643	/** Accessed flag.
1644	* Indicates that the page have been read or written to. */
1645	uint32_t u1Accessed : 1;
1646	/** Chunk of reserved bits. */
1647	uint32_t u3Reserved : 3;
1648	/** Available for use to system software. */
1649	uint32_t u3Available : 3;
1650	/** Physical Page number of the next level - Low Part. Don't use! */
1651	uint32_t u20PageNoLow : 20;
1652	/** Physical Page number of the next level - High Part. Don't use! */
1653	uint32_t u20PageNoHigh : 20;
1654	/** MBZ bits */
1655	uint32_t u11Reserved : 11;
1656	/** No Execute flag. */
1657	uint32_t u1NoExecute : 1;
1658	} X86PML4EBITS;
1659	/** Pointer to a page map level-4 entry. */
1660	typedef X86PML4EBITS *PX86PML4EBITS;
1661	/** Pointer to a const page map level-4 entry. */
1662	typedef const X86PML4EBITS *PCX86PML4EBITS;
1663
1664	/**
1665	* Page Map Level-4 Entry.
1666	*/
1667	typedef union X86PML4E
1668	{
1669	/** Normal view. */
1670	X86PML4EBITS n;
1671	/** Unsigned integer view. */
1672	X86PGPAEUINT u;
1673	/** 8 bit unsigned integer view. */
1674	uint8_t au8[8];
1675	/** 16 bit unsigned integer view. */
1676	uint16_t au16[4];
1677	/** 32 bit unsigned integer view. */
1678	uint32_t au32[2];
1679	} X86PML4E;
1680	/** Pointer to a page map level-4 entry. */
1681	typedef X86PML4E *PX86PML4E;
1682	/** Pointer to a const page map level-4 entry. */
1683	typedef const X86PML4E *PCX86PML4E;
1684
1685
1686	/**
1687	* Page Map Level-4.
1688	*/
1689	typedef struct X86PML4
1690	{
1691	/** PDE Array. */
1692	X86PML4E a[X86_PG_PAE_ENTRIES];
1693	} X86PML4;
1694	/** Pointer to a page map level-4. */
1695	typedef X86PML4 *PX86PML4;
1696	/** Pointer to a const page map level-4. */
1697	typedef const X86PML4 *PCX86PML4;
1698
1699	/** The page shift to get the PML4 index. */
1700	#define X86_PML4_SHIFT 39
1701	/** The PML4 index mask (apply to a shifted page address). */
1702	#define X86_PML4_MASK 0x1ff
1703
1704	/** @} */
1705
1706	/** @} */
1707
1708
1709	/**
1710	* 80-bit MMX/FPU register type.
1711	*/
1712	typedef struct X86FPUMMX
1713	{
1714	uint8_t reg[10];
1715	} X86FPUMMX;
1716	/** Pointer to a 80-bit MMX/FPU register type. */
1717	typedef X86FPUMMX *PX86FPUMMX;
1718	/** Pointer to a const 80-bit MMX/FPU register type. */
1719	typedef const X86FPUMMX *PCX86FPUMMX;
1720
1721	/**
1722	* FPU state (aka FSAVE/FRSTOR Memory Region).
1723	*/
1724	#pragma pack(1)
1725	typedef struct X86FPUSTATE
1726	{
1727	/** Control word. */
1728	uint16_t FCW;
1729	/** Alignment word */
1730	uint16_t Dummy1;
1731	/** Status word. */
1732	uint16_t FSW;
1733	/** Alignment word */
1734	uint16_t Dummy2;
1735	/** Tag word */
1736	uint16_t FTW;
1737	/** Alignment word */
1738	uint16_t Dummy3;
1739
1740	/** Instruction pointer. */
1741	uint32_t FPUIP;
1742	/** Code selector. */
1743	uint16_t CS;
1744	/** Opcode. */
1745	uint16_t FOP;
1746	/** FOO. */
1747	uint32_t FPUOO;
1748	/** FOS. */
1749	uint32_t FPUOS;
1750	/** FPU view - todo. */
1751	X86FPUMMX regs[8];
1752	} X86FPUSTATE;
1753	#pragma pack()
1754	/** Pointer to a FPU state. */
1755	typedef X86FPUSTATE *PX86FPUSTATE;
1756	/** Pointer to a const FPU state. */
1757	typedef const X86FPUSTATE *PCX86FPUSTATE;
1758
1759	/**
1760	* FPU Extended state (aka FXSAVE/FXRSTORE Memory Region).
1761	*/
1762	#pragma pack(1)
1763	typedef struct X86FXSTATE
1764	{
1765	/** Control word. */
1766	uint16_t FCW;
1767	/** Status word. */
1768	uint16_t FSW;
1769	/** Tag word (it's a byte actually). */
1770	uint8_t FTW;
1771	uint8_t huh1;
1772	/** Opcode. */
1773	uint16_t FOP;
1774	/** Instruction pointer. */
1775	uint32_t FPUIP;
1776	/** Code selector. */
1777	uint16_t CS;
1778	uint16_t Rsvrd1;
1779	/* - offset 16 - */
1780	/** Data pointer. */
1781	uint32_t FPUDP;
1782	/** Data segment */
1783	uint16_t DS;
1784	uint16_t Rsrvd2;
1785	uint32_t MXCSR;
1786	uint32_t MXCSR_MASK;
1787	/* - offset 32 - */
1788	union
1789	{
1790	/** MMX view. */
1791	uint64_t mmx;
1792	/** FPU view - todo. */
1793	X86FPUMMX fpu;
1794	/** 8-bit view. */
1795	uint8_t au8[16];
1796	/** 16-bit view. */
1797	uint16_t au16[8];
1798	/** 32-bit view. */
1799	uint32_t au32[4];
1800	/** 64-bit view. */
1801	uint64_t au64[2];
1802	/** 128-bit view. (yeah, very helpful) */
1803	uint128_t au128[1];
1804	} aRegs[8];
1805	/* - offset 160 - */
1806	union
1807	{
1808	/** XMM Register view . /
1809	uint128_t xmm;
1810	/** 8-bit view. */
1811	uint8_t au8[16];
1812	/** 16-bit view. */
1813	uint16_t au16[8];
1814	/** 32-bit view. */
1815	uint32_t au32[4];
1816	/** 64-bit view. */
1817	uint64_t au64[2];
1818	/** 128-bit view. (yeah, very helpful) */
1819	uint128_t au128[1];
1820	} aXMM[16]; /* 8 registers in 32 bits mode; 16 in long mode */
1821	/* - offset 416 - */
1822	uint32_t au32RsrvdRest[(512 - 416) / sizeof(uint32_t)];
1823	} X86FXSTATE;
1824	#pragma pack()
1825	/** Pointer to a FPU Extended state. */
1826	typedef X86FXSTATE *PX86FXSTATE;
1827	/** Pointer to a const FPU Extended state. */
1828	typedef const X86FXSTATE *PCX86FXSTATE;
1829
1830
1831	/** @name Selector Descriptor
1832	* @{
1833	*/
1834
1835	/**
1836	* Generic descriptor table entry
1837	*/
1838	#pragma pack(1)
1839	typedef struct X86DESCGENERIC
1840	{
1841	/** Limit - Low word. */
1842	unsigned u16LimitLow : 16;
1843	/** Base address - lowe word.
1844	* Don't try set this to 24 because MSC is doing studing things then. */
1845	unsigned u16BaseLow : 16;
1846	/** Base address - first 8 bits of high word. */
1847	unsigned u8BaseHigh1 : 8;
1848	/** Segment Type. */
1849	unsigned u4Type : 4;
1850	/** Descriptor Type. System(=0) or code/data selector */
1851	unsigned u1DescType : 1;
1852	/** Descriptor Privelege level. */
1853	unsigned u2Dpl : 2;
1854	/** Flags selector present(=1) or not. */
1855	unsigned u1Present : 1;
1856	/** Segment limit 16-19. */
1857	unsigned u4LimitHigh : 4;
1858	/** Available for system software. */
1859	unsigned u1Available : 1;
1860	/** 32 bits mode: Reserved - 0, long mode: Long Attribute Bit. */
1861	unsigned u1Long : 1;
1862	/** This flags meaning depends on the segment type. Try make sense out
1863	* of the intel manual yourself. */
1864	unsigned u1DefBig : 1;
1865	/** Granularity of the limit. If set 4KB granularity is used, if
1866	* clear byte. */
1867	unsigned u1Granularity : 1;
1868	/** Base address - highest 8 bits. */
1869	unsigned u8BaseHigh2 : 8;
1870	} X86DESCGENERIC;
1871	#pragma pack()
1872	/** Pointer to a generic descriptor entry. */
1873	typedef X86DESCGENERIC *PX86DESCGENERIC;
1874	/** Pointer to a const generic descriptor entry. */
1875	typedef const X86DESCGENERIC *PCX86DESCGENERIC;
1876
1877
1878	/**
1879	* Descriptor attributes.
1880	*/
1881	typedef struct X86DESCATTRBITS
1882	{
1883	/** Segment Type. */
1884	unsigned u4Type : 4;
1885	/** Descriptor Type. System(=0) or code/data selector */
1886	unsigned u1DescType : 1;
1887	/** Descriptor Privelege level. */
1888	unsigned u2Dpl : 2;
1889	/** Flags selector present(=1) or not. */
1890	unsigned u1Present : 1;
1891	/** Segment limit 16-19. */
1892	unsigned u4LimitHigh : 4;
1893	/** Available for system software. */
1894	unsigned u1Available : 1;
1895	/** 32 bits mode: Reserved - 0, long mode: Long Attribute Bit. */
1896	unsigned u1Long : 1;
1897	/** This flags meaning depends on the segment type. Try make sense out
1898	* of the intel manual yourself. */
1899	unsigned u1DefBig : 1;
1900	/** Granularity of the limit. If set 4KB granularity is used, if
1901	* clear byte. */
1902	unsigned u1Granularity : 1;
1903	} X86DESCATTRBITS;
1904
1905
1906	#pragma pack(1)
1907	typedef union X86DESCATTR
1908	{
1909	/** Normal view. */
1910	X86DESCATTRBITS n;
1911	/** Unsigned integer view. */
1912	uint32_t u;
1913	} X86DESCATTR;
1914	#pragma pack()
1915
1916	/** Pointer to descriptor attributes. */
1917	typedef X86DESCATTR *PX86DESCATTR;
1918	/** Pointer to const descriptor attributes. */
1919	typedef const X86DESCATTR *PCX86DESCATTR;
1920
1921
1922	/**
1923	* Descriptor table entry.
1924	*/
1925	#pragma pack(1)
1926	typedef union X86DESC
1927	{
1928	/** Generic descriptor view. */
1929	X86DESCGENERIC Gen;
1930	#if 0
1931	/** IDT view. */
1932	VBOXIDTE Idt;
1933	#endif
1934
1935	/** 8 bit unsigned interger view. */
1936	uint8_t au8[8];
1937	/** 16 bit unsigned interger view. */
1938	uint16_t au16[4];
1939	/** 32 bit unsigned interger view. */
1940	uint32_t au32[2];
1941	} X86DESC;
1942	#pragma pack()
1943	/** Pointer to descriptor table entry. */
1944	typedef X86DESC *PX86DESC;
1945	/** Pointer to const descriptor table entry. */
1946	typedef const X86DESC *PCX86DESC;
1947
1948
1949	/** @def X86DESC_BASE
1950	* Return the base address of a descriptor.
1951	*/
1952	#define X86DESC_BASE(desc) \
1953	( ((uint32_t)((desc).Gen.u8BaseHigh2) << 24) \
1954	\| ( (desc).Gen.u8BaseHigh1 << 16) \
1955	\| ( (desc).Gen.u16BaseLow ) )
1956
1957	/** @def X86DESC_LIMIT
1958	* Return the limit of a descriptor.
1959	*/
1960	#define X86DESC_LIMIT(desc) \
1961	( ((uint32_t)((desc).Gen.u4LimitHigh) << 16) \
1962	\| ( (desc).Gen.u16LimitLow ) )
1963
1964	/**
1965	* 64 bits generic descriptor table entry
1966	* Note: most of these bits have no meaning in long mode.
1967	*/
1968	#pragma pack(1)
1969	typedef struct X86DESC64GENERIC
1970	{
1971	/** Limit - Low word - IGNORED. */
1972	unsigned u16LimitLow : 16;
1973	/** Base address - lowe word. - IGNORED
1974	* Don't try set this to 24 because MSC is doing studing things then. */
1975	unsigned u16BaseLow : 16;
1976	/** Base address - first 8 bits of high word. - IGNORED */
1977	unsigned u8BaseHigh1 : 8;
1978	/** Segment Type. */
1979	unsigned u4Type : 4;
1980	/** Descriptor Type. System(=0) or code/data selector */
1981	unsigned u1DescType : 1;
1982	/** Descriptor Privelege level. */
1983	unsigned u2Dpl : 2;
1984	/** Flags selector present(=1) or not. */
1985	unsigned u1Present : 1;
1986	/** Segment limit 16-19. - IGNORED */
1987	unsigned u4LimitHigh : 4;
1988	/** Available for system software. - IGNORED */
1989	unsigned u1Available : 1;
1990	/** Long mode flag. */
1991	unsigned u1Long : 1;
1992	/** This flags meaning depends on the segment type. Try make sense out
1993	* of the intel manual yourself. */
1994	unsigned u1DefBig : 1;
1995	/** Granularity of the limit. If set 4KB granularity is used, if
1996	* clear byte. - IGNORED */
1997	unsigned u1Granularity : 1;
1998	/** Base address - highest 8 bits. - IGNORED */
1999	unsigned u8BaseHigh2 : 8;
2000	/** Base address - bits 63-32. */
2001	unsigned u32BaseHigh3 : 32;
2002	unsigned u8Reserved : 8;
2003	unsigned u5Zeros : 5;
2004	unsigned u19Reserved : 19;
2005	} X86DESC64GENERIC;
2006	#pragma pack()
2007	/** Pointer to a generic descriptor entry. */
2008	typedef X86DESC64GENERIC *PX86DESC64GENERIC;
2009	/** Pointer to a const generic descriptor entry. */
2010	typedef const X86DESC64GENERIC *PCX86DESC64GENERIC;
2011
2012	/**
2013	* System descriptor table entry (64 bits)
2014	*/
2015	#pragma pack(1)
2016	typedef struct X86DESC64SYSTEM
2017	{
2018	/** Limit - Low word. */
2019	unsigned u16LimitLow : 16;
2020	/** Base address - lowe word.
2021	* Don't try set this to 24 because MSC is doing studing things then. */
2022	unsigned u16BaseLow : 16;
2023	/** Base address - first 8 bits of high word. */
2024	unsigned u8BaseHigh1 : 8;
2025	/** Segment Type. */
2026	unsigned u4Type : 4;
2027	/** Descriptor Type. System(=0) or code/data selector */
2028	unsigned u1DescType : 1;
2029	/** Descriptor Privelege level. */
2030	unsigned u2Dpl : 2;
2031	/** Flags selector present(=1) or not. */
2032	unsigned u1Present : 1;
2033	/** Segment limit 16-19. */
2034	unsigned u4LimitHigh : 4;
2035	/** Available for system software. */
2036	unsigned u1Available : 1;
2037	/** Reserved - 0. */
2038	unsigned u1Reserved : 1;
2039	/** This flags meaning depends on the segment type. Try make sense out
2040	* of the intel manual yourself. */
2041	unsigned u1DefBig : 1;
2042	/** Granularity of the limit. If set 4KB granularity is used, if
2043	* clear byte. */
2044	unsigned u1Granularity : 1;
2045	/** Base address - bits 31-24. */
2046	unsigned u8BaseHigh2 : 8;
2047	/** Base address - bits 63-32. */
2048	unsigned u32BaseHigh3 : 32;
2049	unsigned u8Reserved : 8;
2050	unsigned u5Zeros : 5;
2051	unsigned u19Reserved : 19;
2052	} X86DESC64SYSTEM;
2053	#pragma pack()
2054	/** Pointer to a generic descriptor entry. */
2055	typedef X86DESC64SYSTEM *PX86DESC64SYSTEM;
2056	/** Pointer to a const generic descriptor entry. */
2057	typedef const X86DESC64SYSTEM *PCX86DESC64SYSTEM;
2058
2059
2060	/**
2061	* Descriptor table entry.
2062	*/
2063	#pragma pack(1)
2064	typedef union X86DESC64
2065	{
2066	/** Generic descriptor view. */
2067	X86DESC64GENERIC Gen;
2068	/** System descriptor view. */
2069	X86DESC64SYSTEM System;
2070	#if 0
2071	X86DESC64GATE Gate;
2072	#endif
2073
2074	/** 8 bit unsigned interger view. */
2075	uint8_t au8[16];
2076	/** 16 bit unsigned interger view. */
2077	uint16_t au16[8];
2078	/** 32 bit unsigned interger view. */
2079	uint32_t au32[4];
2080	/** 64 bit unsigned interger view. */
2081	uint64_t au64[2];
2082	} X86DESC64;
2083	#pragma pack()
2084	/** Pointer to descriptor table entry. */
2085	typedef X86DESC64 *PX86DESC64;
2086	/** Pointer to const descriptor table entry. */
2087	typedef const X86DESC64 *PCX86DESC64;
2088
2089	#if HC_ARCH_BITS == 64
2090	typedef X86DESC64 X86DESCHC;
2091	typedef X86DESC64 *PX86DESCHC;
2092	#else
2093	typedef X86DESC X86DESCHC;
2094	typedef X86DESC *PX86DESCHC;
2095	#endif
2096
2097	/** @def X86DESC_LIMIT
2098	* Return the base of a 64-bit descriptor.
2099	*/
2100	#define X86DESC64_BASE(desc) \
2101	( ((uint64_t)((desc).Gen.u32BaseHigh3) << 32) \
2102	\| ((uint32_t)((desc).Gen.u8BaseHigh2) << 24) \
2103	\| ( (desc).Gen.u8BaseHigh1 << 16) \
2104	\| ( (desc).Gen.u16BaseLow ) )
2105
2106
2107	/** @name Selector Descriptor Types.
2108	* @{
2109	*/
2110
2111	/** @name Non-System Selector Types.
2112	* @{ */
2113	/** Code(=set)/Data(=clear) bit. */
2114	#define X86_SEL_TYPE_CODE 8
2115	/** Memory(=set)/System(=clear) bit. */
2116	#define X86_SEL_TYPE_MEMORY RT_BIT(4)
2117	/** Accessed bit. */
2118	#define X86_SEL_TYPE_ACCESSED 1
2119	/** Expand down bit (for data selectors only). */
2120	#define X86_SEL_TYPE_DOWN 4
2121	/** Conforming bit (for code selectors only). */
2122	#define X86_SEL_TYPE_CONF 4
2123	/** Write bit (for data selectors only). */
2124	#define X86_SEL_TYPE_WRITE 2
2125	/** Read bit (for code selectors only). */
2126	#define X86_SEL_TYPE_READ 2
2127
2128	/** Read only selector type. */
2129	#define X86_SEL_TYPE_RO 0
2130	/** Accessed read only selector type. */
2131	#define X86_SEL_TYPE_RO_ACC (0 \| X86_SEL_TYPE_ACCESSED)
2132	/** Read write selector type. */
2133	#define X86_SEL_TYPE_RW 2
2134	/** Accessed read write selector type. */
2135	#define X86_SEL_TYPE_RW_ACC (2 \| X86_SEL_TYPE_ACCESSED)
2136	/** Expand down read only selector type. */
2137	#define X86_SEL_TYPE_RO_DOWN 4
2138	/** Accessed expand down read only selector type. */
2139	#define X86_SEL_TYPE_RO_DOWN_ACC (4 \| X86_SEL_TYPE_ACCESSED)
2140	/** Expand down read write selector type. */
2141	#define X86_SEL_TYPE_RW_DOWN 6
2142	/** Accessed expand down read write selector type. */
2143	#define X86_SEL_TYPE_RW_DOWN_ACC (6 \| X86_SEL_TYPE_ACCESSED)
2144	/** Execute only selector type. */
2145	#define X86_SEL_TYPE_EO (0 \| X86_SEL_TYPE_CODE)
2146	/** Accessed execute only selector type. */
2147	#define X86_SEL_TYPE_EO_ACC (0 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
2148	/** Execute and read selector type. */
2149	#define X86_SEL_TYPE_ER (2 \| X86_SEL_TYPE_CODE)
2150	/** Accessed execute and read selector type. */
2151	#define X86_SEL_TYPE_ER_ACC (2 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
2152	/** Conforming execute only selector type. */
2153	#define X86_SEL_TYPE_EO_CONF (4 \| X86_SEL_TYPE_CODE)
2154	/** Accessed Conforming execute only selector type. */
2155	#define X86_SEL_TYPE_EO_CONF_ACC (4 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
2156	/** Conforming execute and write selector type. */
2157	#define X86_SEL_TYPE_ER_CONF (6 \| X86_SEL_TYPE_CODE)
2158	/** Accessed Conforming execute and write selector type. */
2159	#define X86_SEL_TYPE_ER_CONF_ACC (6 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
2160	/** @} */
2161
2162
2163	/** @name System Selector Types.
2164	* @{ */
2165	/** Undefined system selector type. */
2166	#define X86_SEL_TYPE_SYS_UNDEFINED 0
2167	/** 286 TSS selector. */
2168	#define X86_SEL_TYPE_SYS_286_TSS_AVAIL 1
2169	/** LDT selector. */
2170	#define X86_SEL_TYPE_SYS_LDT 2
2171	/** 286 TSS selector - Busy. */
2172	#define X86_SEL_TYPE_SYS_286_TSS_BUSY 3
2173	/** 286 Callgate selector. */
2174	#define X86_SEL_TYPE_SYS_286_CALL_GATE 4
2175	/** Taskgate selector. */
2176	#define X86_SEL_TYPE_SYS_TASK_GATE 5
2177	/** 286 Interrupt gate selector. */
2178	#define X86_SEL_TYPE_SYS_286_INT_GATE 6
2179	/** 286 Trapgate selector. */
2180	#define X86_SEL_TYPE_SYS_286_TRAP_GATE 7
2181	/** Undefined system selector. */
2182	#define X86_SEL_TYPE_SYS_UNDEFINED2 8
2183	/** 386 TSS selector. */
2184	#define X86_SEL_TYPE_SYS_386_TSS_AVAIL 9
2185	/** Undefined system selector. */
2186	#define X86_SEL_TYPE_SYS_UNDEFINED3 0xA
2187	/** 386 TSS selector - Busy. */
2188	#define X86_SEL_TYPE_SYS_386_TSS_BUSY 0xB
2189	/** 386 Callgate selector. */
2190	#define X86_SEL_TYPE_SYS_386_CALL_GATE 0xC
2191	/** Undefined system selector. */
2192	#define X86_SEL_TYPE_SYS_UNDEFINED4 0xD
2193	/** 386 Interruptgate selector. */
2194	#define X86_SEL_TYPE_SYS_386_INT_GATE 0xE
2195	/** 386 Trapgate selector. */
2196	#define X86_SEL_TYPE_SYS_386_TRAP_GATE 0xF
2197	/** @} */
2198
2199	/** @name AMD64 System Selector Types.
2200	* @{ */
2201	#define AMD64_SEL_TYPE_SYS_LDT 2
2202	/** 286 TSS selector - Busy. */
2203	#define AMD64_SEL_TYPE_SYS_TSS_AVAIL 9
2204	/** 386 TSS selector - Busy. */
2205	#define AMD64_SEL_TYPE_SYS_TSS_BUSY 0xB
2206	/** 386 Callgate selector. */
2207	#define AMD64_SEL_TYPE_SYS_CALL_GATE 0xC
2208	/** 386 Interruptgate selector. */
2209	#define AMD64_SEL_TYPE_SYS_INT_GATE 0xE
2210	/** 386 Trapgate selector. */
2211	#define AMD64_SEL_TYPE_SYS_TRAP_GATE 0xF
2212	/** @} */
2213
2214	/** @} */
2215
2216
2217	/** @name Descriptor Table Entry Flag Masks.
2218	* These are for the 2nd 32-bit word of a descriptor.
2219	* @{ */
2220	/** Bits 8-11 - TYPE - Descriptor type mask. */
2221	#define X86_DESC_TYPE_MASK (RT_BIT(8) \| RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
2222	/** Bit 12 - S - System (=0) or Code/Data (=1). */
2223	#define X86_DESC_S RT_BIT(12)
2224	/** Bits 13-14 - DPL - Descriptor Privilege Level. */
2225	#define X86_DESC_DPL (RT_BIT(13) \| RT_BIT(14))
2226	/** Bit 15 - P - Present. */
2227	#define X86_DESC_P RT_BIT(15)
2228	/** Bit 20 - AVL - Available for system software. */
2229	#define X86_DESC_AVL RT_BIT(20)
2230	/** Bit 22 - DB - Default operation size. 0 = 16 bit, 1 = 32 bit. */
2231	#define X86_DESC_DB RT_BIT(22)
2232	/** Bit 23 - G - Granularity of the limit. If set 4KB granularity is
2233	* used, if clear byte. */
2234	#define X86_DESC_G RT_BIT(23)
2235	/** @} */
2236
2237	/** @} */
2238
2239
2240	/** @name Selectors.
2241	* @{
2242	*/
2243
2244	/**
2245	* The shift used to convert a selector from and to index an index (C).
2246	*/
2247	#define X86_SEL_SHIFT 3
2248
2249	/**
2250	* The shift used to convert a selector from and to index an index (C).
2251	*/
2252	#define AMD64_SEL_SHIFT 4
2253
2254	#if HC_ARCH_BITS == 64
2255	#define X86_SEL_SHIFT_HC AMD64_SEL_SHIFT
2256	#else
2257	#define X86_SEL_SHIFT_HC X86_SEL_SHIFT
2258	#endif
2259
2260	/**
2261	* The mask used to mask off the table indicator and CPL of an selector.
2262	*/
2263	#define X86_SEL_MASK 0xfff8
2264
2265	/**
2266	* The bit indicating that a selector is in the LDT and not in the GDT.
2267	*/
2268	#define X86_SEL_LDT 0x0004
2269	/**
2270	* The bit mask for getting the RPL of a selector.
2271	*/
2272	#define X86_SEL_RPL 0x0003
2273
2274	/** @} */
2275
2276
2277	/**
2278	* x86 Exceptions/Faults/Traps.
2279	*/
2280	typedef enum X86XCPT
2281	{
2282	/** \#DE - Divide error. */
2283	X86_XCPT_DE = 0x00,
2284	/** \#DB - Debug event (single step, DRx, ..) */
2285	X86_XCPT_DB = 0x01,
2286	/** NMI - Non-Maskable Interrupt */
2287	X86_XCPT_NMI = 0x02,
2288	/** \#BP - Breakpoint (INT3). */
2289	X86_XCPT_BP = 0x03,
2290	/** \#OF - Overflow (INTO). */
2291	X86_XCPT_OF = 0x04,
2292	/** \#BR - Bound range exceeded (BOUND). */
2293	X86_XCPT_BR = 0x05,
2294	/** \#UD - Undefined opcode. */
2295	X86_XCPT_UD = 0x06,
2296	/** \#NM - Device not available (math coprocessor device). */
2297	X86_XCPT_NM = 0x07,
2298	/** \#DF - Double fault. */
2299	X86_XCPT_DF = 0x08,
2300	/** ??? - Coprocessor segment overrun (obsolete). */
2301	X86_XCPT_CO_SEG_OVERRUN = 0x09,
2302	/** \#TS - Taskswitch (TSS). */
2303	X86_XCPT_TS = 0x0a,
2304	/** \#NP - Segment no present. */
2305	X86_XCPT_NP = 0x0b,
2306	/** \#SS - Stack segment fault. */
2307	X86_XCPT_SS = 0x0c,
2308	/** \#GP - General protection fault. */
2309	X86_XCPT_GP = 0x0d,
2310	/** \#PF - Page fault. */
2311	X86_XCPT_PF = 0x0e,
2312	/* 0x0f is reserved. */
2313	/** \#MF - Math fault (FPU). */
2314	X86_XCPT_MF = 0x10,
2315	/** \#AC - Alignment check. */
2316	X86_XCPT_AC = 0x11,
2317	/** \#MC - Machine check. */
2318	X86_XCPT_MC = 0x12,
2319	/** \#XF - SIMD Floating-Pointer Exception. */
2320	X86_XCPT_XF = 0x13
2321	} X86XCPT;
2322	/** Pointer to a x86 exception code. */
2323	typedef X86XCPT *PX86XCPT;
2324	/** Pointer to a const x86 exception code. */
2325	typedef const X86XCPT *PCX86XCPT;
2326
2327
2328	/** @name Trap Error Codes
2329	* @{
2330	*/
2331	/** External indicator. */
2332	#define X86_TRAP_ERR_EXTERNAL 1
2333	/** IDT indicator. */
2334	#define X86_TRAP_ERR_IDT 2
2335	/** Descriptor table indicator - If set LDT, if clear GDT. */
2336	#define X86_TRAP_ERR_TI 4
2337	/** Mask for getting the selector. */
2338	#define X86_TRAP_ERR_SEL_MASK 0xfff8
2339	/** Shift for getting the selector table index (C type index). */
2340	#define X86_TRAP_ERR_SEL_SHIFT 3
2341	/** @} */
2342
2343
2344	/** @name \#PF Trap Error Codes
2345	* @{
2346	*/
2347	/** Bit 0 - P - Not present (clear) or page level protection (set) fault. */
2348	#define X86_TRAP_PF_P RT_BIT(0)
2349	/** Bit 1 - R/W - Read (clear) or write (set) access. */
2350	#define X86_TRAP_PF_RW RT_BIT(1)
2351	/** Bit 2 - U/S - CPU executing in user mode (set) or supervisor mode (clear). */
2352	#define X86_TRAP_PF_US RT_BIT(2)
2353	/** Bit 3 - RSVD- Reserved bit violation (set), i.e. reserved bit was set to 1. */
2354	#define X86_TRAP_PF_RSVD RT_BIT(3)
2355	/** Bit 4 - I/D - Instruction fetch (set) / Data access (clear) - PAE + NXE. */
2356	#define X86_TRAP_PF_ID RT_BIT(4)
2357	/** @} */
2358
2359	#pragma pack(1)
2360	/**
2361	* 32-bit IDTR/GDTR.
2362	*/
2363	typedef struct X86XDTR32
2364	{
2365	/** Size of the descriptor table. */
2366	uint16_t cb;
2367	/** Address of the descriptor table. */
2368	uint32_t uAddr;
2369	} X86XDTR32, *PX86XDTR32;
2370	#pragma pack()
2371
2372	#pragma pack(1)
2373	/**
2374	* 64-bit IDTR/GDTR.
2375	*/
2376	typedef struct X86XDTR64
2377	{
2378	/** Size of the descriptor table. */
2379	uint16_t cb;
2380	/** Address of the descriptor table. */
2381	uint64_t uAddr;
2382	} X86XDTR64, *PX86XDTR64;
2383	#pragma pack()
2384
2385	/** @} */
2386
2387	#endif
2388

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source: vbox/trunk/include/VBox/x86.h@ 10707

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